1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2019 MediaTek Inc. 4 */ 5 6 #ifndef _UFS_MEDIATEK_H 7 #define _UFS_MEDIATEK_H 8 9 #include <linux/bitops.h> 10 #include <linux/pm_qos.h> 11 #include <linux/soc/mediatek/mtk_sip_svc.h> 12 13 /* 14 * Vendor specific UFSHCI Registers 15 */ 16 #define REG_UFS_XOUFS_CTRL 0x140 17 #define REG_UFS_REFCLK_CTRL 0x144 18 #define REG_UFS_EXTREG 0x2100 19 #define REG_UFS_MPHYCTRL 0x2200 20 #define REG_UFS_MTK_IP_VER 0x2240 21 #define REG_UFS_REJECT_MON 0x22AC 22 #define REG_UFS_DEBUG_SEL 0x22C0 23 #define REG_UFS_PROBE 0x22C8 24 #define REG_UFS_DEBUG_SEL_B0 0x22D0 25 #define REG_UFS_DEBUG_SEL_B1 0x22D4 26 #define REG_UFS_DEBUG_SEL_B2 0x22D8 27 #define REG_UFS_DEBUG_SEL_B3 0x22DC 28 29 /* 30 * Ref-clk control 31 * 32 * Values for register REG_UFS_REFCLK_CTRL 33 */ 34 #define REFCLK_RELEASE 0x0 35 #define REFCLK_REQUEST BIT(0) 36 #define REFCLK_ACK BIT(1) 37 38 #define REFCLK_REQ_TIMEOUT_US 3000 39 #define REFCLK_DEFAULT_WAIT_US 32 40 41 /* 42 * Other attributes 43 */ 44 #define VS_DEBUGCLOCKENABLE 0xD0A1 45 #define VS_SAVEPOWERCONTROL 0xD0A6 46 #define VS_UNIPROPOWERDOWNCONTROL 0xD0A8 47 48 /* 49 * Vendor specific link state 50 */ 51 enum { 52 VS_LINK_DISABLED = 0, 53 VS_LINK_DOWN = 1, 54 VS_LINK_UP = 2, 55 VS_LINK_HIBERN8 = 3, 56 VS_LINK_LOST = 4, 57 VS_LINK_CFG = 5, 58 }; 59 60 /* 61 * Vendor specific host controller state 62 */ 63 enum { 64 VS_HCE_RESET = 0, 65 VS_HCE_BASE = 1, 66 VS_HCE_OOCPR_WAIT = 2, 67 VS_HCE_DME_RESET = 3, 68 VS_HCE_MIDDLE = 4, 69 VS_HCE_DME_ENABLE = 5, 70 VS_HCE_DEFAULTS = 6, 71 VS_HIB_IDLEEN = 7, 72 VS_HIB_ENTER = 8, 73 VS_HIB_ENTER_CONF = 9, 74 VS_HIB_MIDDLE = 10, 75 VS_HIB_WAITTIMER = 11, 76 VS_HIB_EXIT_CONF = 12, 77 VS_HIB_EXIT = 13, 78 }; 79 80 /* 81 * SiP commands 82 */ 83 #define MTK_SIP_UFS_CONTROL MTK_SIP_SMC_CMD(0x276) 84 #define UFS_MTK_SIP_VA09_PWR_CTRL BIT(0) 85 #define UFS_MTK_SIP_DEVICE_RESET BIT(1) 86 #define UFS_MTK_SIP_CRYPTO_CTRL BIT(2) 87 #define UFS_MTK_SIP_REF_CLK_NOTIFICATION BIT(3) 88 #define UFS_MTK_SIP_HOST_PWR_CTRL BIT(5) 89 #define UFS_MTK_SIP_GET_VCC_NUM BIT(6) 90 #define UFS_MTK_SIP_DEVICE_PWR_CTRL BIT(7) 91 92 /* 93 * VS_DEBUGCLOCKENABLE 94 */ 95 enum { 96 TX_SYMBOL_CLK_REQ_FORCE = 5, 97 }; 98 99 /* 100 * VS_SAVEPOWERCONTROL 101 */ 102 enum { 103 RX_SYMBOL_CLK_GATE_EN = 0, 104 SYS_CLK_GATE_EN = 2, 105 TX_CLK_GATE_EN = 3, 106 }; 107 108 /* 109 * Host capability 110 */ 111 enum ufs_mtk_host_caps { 112 UFS_MTK_CAP_BOOST_CRYPT_ENGINE = 1 << 0, 113 UFS_MTK_CAP_VA09_PWR_CTRL = 1 << 1, 114 UFS_MTK_CAP_DISABLE_AH8 = 1 << 2, 115 UFS_MTK_CAP_BROKEN_VCC = 1 << 3, 116 UFS_MTK_CAP_PMC_VIA_FASTAUTO = 1 << 6, 117 }; 118 119 struct ufs_mtk_crypt_cfg { 120 struct regulator *reg_vcore; 121 struct clk *clk_crypt_perf; 122 struct clk *clk_crypt_mux; 123 struct clk *clk_crypt_lp; 124 int vcore_volt; 125 }; 126 127 struct ufs_mtk_hw_ver { 128 u8 step; 129 u8 minor; 130 u8 major; 131 }; 132 133 struct ufs_mtk_host { 134 struct phy *mphy; 135 struct pm_qos_request pm_qos_req; 136 struct regulator *reg_va09; 137 struct reset_control *hci_reset; 138 struct reset_control *unipro_reset; 139 struct reset_control *crypto_reset; 140 struct ufs_hba *hba; 141 struct ufs_mtk_crypt_cfg *crypt; 142 struct ufs_mtk_hw_ver hw_ver; 143 enum ufs_mtk_host_caps caps; 144 bool mphy_powered_on; 145 bool pm_qos_init; 146 bool unipro_lpm; 147 bool ref_clk_enabled; 148 u16 ref_clk_ungating_wait_us; 149 u16 ref_clk_gating_wait_us; 150 u32 ip_ver; 151 }; 152 153 /* 154 * Multi-VCC by Numbering 155 */ 156 enum ufs_mtk_vcc_num { 157 UFS_VCC_NONE = 0, 158 UFS_VCC_1, 159 UFS_VCC_2, 160 UFS_VCC_MAX 161 }; 162 163 /* 164 * Host Power Control options 165 */ 166 enum { 167 HOST_PWR_HCI = 0, 168 HOST_PWR_MPHY 169 }; 170 171 /* 172 * SMC call wrapper function 173 */ 174 struct ufs_mtk_smc_arg { 175 unsigned long cmd; 176 struct arm_smccc_res *res; 177 unsigned long v1; 178 unsigned long v2; 179 unsigned long v3; 180 unsigned long v4; 181 unsigned long v5; 182 unsigned long v6; 183 unsigned long v7; 184 }; 185 186 static void _ufs_mtk_smc(struct ufs_mtk_smc_arg s) 187 { 188 arm_smccc_smc(MTK_SIP_UFS_CONTROL, 189 s.cmd, s.v1, s.v2, s.v3, s.v4, s.v5, s.v6, s.res); 190 } 191 192 #define ufs_mtk_smc(...) \ 193 _ufs_mtk_smc((struct ufs_mtk_smc_arg) {__VA_ARGS__}) 194 195 /* 196 * SMC call interface 197 */ 198 #define ufs_mtk_va09_pwr_ctrl(res, on) \ 199 ufs_mtk_smc(UFS_MTK_SIP_VA09_PWR_CTRL, &(res), on) 200 201 #define ufs_mtk_crypto_ctrl(res, enable) \ 202 ufs_mtk_smc(UFS_MTK_SIP_CRYPTO_CTRL, &(res), enable) 203 204 #define ufs_mtk_ref_clk_notify(on, stage, res) \ 205 ufs_mtk_smc(UFS_MTK_SIP_REF_CLK_NOTIFICATION, &(res), on, stage) 206 207 #define ufs_mtk_device_reset_ctrl(high, res) \ 208 ufs_mtk_smc(UFS_MTK_SIP_DEVICE_RESET, &(res), high) 209 210 #define ufs_mtk_host_pwr_ctrl(opt, on, res) \ 211 ufs_mtk_smc(UFS_MTK_SIP_HOST_PWR_CTRL, &(res), opt, on) 212 213 #define ufs_mtk_get_vcc_num(res) \ 214 ufs_mtk_smc(UFS_MTK_SIP_GET_VCC_NUM, &(res)) 215 216 #define ufs_mtk_device_pwr_ctrl(on, ufs_ver, res) \ 217 ufs_mtk_smc(UFS_MTK_SIP_DEVICE_PWR_CTRL, &(res), on, ufs_ver) 218 219 #endif /* !_UFS_MEDIATEK_H */ 220