1dd11376bSBart Van Assche /* SPDX-License-Identifier: GPL-2.0 */ 2dd11376bSBart Van Assche /* 3dd11376bSBart Van Assche * Copyright (C) 2019 MediaTek Inc. 4dd11376bSBart Van Assche */ 5dd11376bSBart Van Assche 6dd11376bSBart Van Assche #ifndef _UFS_MEDIATEK_H 7dd11376bSBart Van Assche #define _UFS_MEDIATEK_H 8dd11376bSBart Van Assche 9dd11376bSBart Van Assche #include <linux/bitops.h> 10c64c487dSPeter Wang #include <linux/pm_qos.h> 11dd11376bSBart Van Assche #include <linux/soc/mediatek/mtk_sip_svc.h> 12dd11376bSBart Van Assche 13dd11376bSBart Van Assche /* 14dd11376bSBart Van Assche * Vendor specific UFSHCI Registers 15dd11376bSBart Van Assche */ 162bae03a6SPeter Wang #define REG_UFS_XOUFS_CTRL 0x140 17dd11376bSBart Van Assche #define REG_UFS_REFCLK_CTRL 0x144 18dd11376bSBart Van Assche #define REG_UFS_EXTREG 0x2100 19dd11376bSBart Van Assche #define REG_UFS_MPHYCTRL 0x2200 20dd11376bSBart Van Assche #define REG_UFS_MTK_IP_VER 0x2240 21dd11376bSBart Van Assche #define REG_UFS_REJECT_MON 0x22AC 22dd11376bSBart Van Assche #define REG_UFS_DEBUG_SEL 0x22C0 23dd11376bSBart Van Assche #define REG_UFS_PROBE 0x22C8 24dd11376bSBart Van Assche #define REG_UFS_DEBUG_SEL_B0 0x22D0 25dd11376bSBart Van Assche #define REG_UFS_DEBUG_SEL_B1 0x22D4 26dd11376bSBart Van Assche #define REG_UFS_DEBUG_SEL_B2 0x22D8 27dd11376bSBart Van Assche #define REG_UFS_DEBUG_SEL_B3 0x22DC 28dd11376bSBart Van Assche 29dd11376bSBart Van Assche /* 30dd11376bSBart Van Assche * Ref-clk control 31dd11376bSBart Van Assche * 32dd11376bSBart Van Assche * Values for register REG_UFS_REFCLK_CTRL 33dd11376bSBart Van Assche */ 34dd11376bSBart Van Assche #define REFCLK_RELEASE 0x0 35dd11376bSBart Van Assche #define REFCLK_REQUEST BIT(0) 36dd11376bSBart Van Assche #define REFCLK_ACK BIT(1) 37dd11376bSBart Van Assche 38dd11376bSBart Van Assche #define REFCLK_REQ_TIMEOUT_US 3000 39dd11376bSBart Van Assche #define REFCLK_DEFAULT_WAIT_US 32 40dd11376bSBart Van Assche 41dd11376bSBart Van Assche /* 42dd11376bSBart Van Assche * Other attributes 43dd11376bSBart Van Assche */ 44dd11376bSBart Van Assche #define VS_DEBUGCLOCKENABLE 0xD0A1 45dd11376bSBart Van Assche #define VS_SAVEPOWERCONTROL 0xD0A6 46dd11376bSBart Van Assche #define VS_UNIPROPOWERDOWNCONTROL 0xD0A8 47dd11376bSBart Van Assche 48dd11376bSBart Van Assche /* 49dd11376bSBart Van Assche * Vendor specific link state 50dd11376bSBart Van Assche */ 51dd11376bSBart Van Assche enum { 52dd11376bSBart Van Assche VS_LINK_DISABLED = 0, 53dd11376bSBart Van Assche VS_LINK_DOWN = 1, 54dd11376bSBart Van Assche VS_LINK_UP = 2, 55dd11376bSBart Van Assche VS_LINK_HIBERN8 = 3, 56dd11376bSBart Van Assche VS_LINK_LOST = 4, 57dd11376bSBart Van Assche VS_LINK_CFG = 5, 58dd11376bSBart Van Assche }; 59dd11376bSBart Van Assche 60dd11376bSBart Van Assche /* 61dd11376bSBart Van Assche * Vendor specific host controller state 62dd11376bSBart Van Assche */ 63dd11376bSBart Van Assche enum { 64dd11376bSBart Van Assche VS_HCE_RESET = 0, 65dd11376bSBart Van Assche VS_HCE_BASE = 1, 66dd11376bSBart Van Assche VS_HCE_OOCPR_WAIT = 2, 67dd11376bSBart Van Assche VS_HCE_DME_RESET = 3, 68dd11376bSBart Van Assche VS_HCE_MIDDLE = 4, 69dd11376bSBart Van Assche VS_HCE_DME_ENABLE = 5, 70dd11376bSBart Van Assche VS_HCE_DEFAULTS = 6, 71dd11376bSBart Van Assche VS_HIB_IDLEEN = 7, 72dd11376bSBart Van Assche VS_HIB_ENTER = 8, 73dd11376bSBart Van Assche VS_HIB_ENTER_CONF = 9, 74dd11376bSBart Van Assche VS_HIB_MIDDLE = 10, 75dd11376bSBart Van Assche VS_HIB_WAITTIMER = 11, 76dd11376bSBart Van Assche VS_HIB_EXIT_CONF = 12, 77dd11376bSBart Van Assche VS_HIB_EXIT = 13, 78dd11376bSBart Van Assche }; 79dd11376bSBart Van Assche 80dd11376bSBart Van Assche /* 81dd11376bSBart Van Assche * SiP commands 82dd11376bSBart Van Assche */ 83dd11376bSBart Van Assche #define MTK_SIP_UFS_CONTROL MTK_SIP_SMC_CMD(0x276) 84dd11376bSBart Van Assche #define UFS_MTK_SIP_VA09_PWR_CTRL BIT(0) 85dd11376bSBart Van Assche #define UFS_MTK_SIP_DEVICE_RESET BIT(1) 86dd11376bSBart Van Assche #define UFS_MTK_SIP_CRYPTO_CTRL BIT(2) 87dd11376bSBart Van Assche #define UFS_MTK_SIP_REF_CLK_NOTIFICATION BIT(3) 882cf5cb2bSPo-Wen Kao #define UFS_MTK_SIP_HOST_PWR_CTRL BIT(5) 89ece418d0SStanley Chu #define UFS_MTK_SIP_GET_VCC_NUM BIT(6) 9042b19283SStanley Chu #define UFS_MTK_SIP_DEVICE_PWR_CTRL BIT(7) 91dd11376bSBart Van Assche 92dd11376bSBart Van Assche /* 93dd11376bSBart Van Assche * VS_DEBUGCLOCKENABLE 94dd11376bSBart Van Assche */ 95dd11376bSBart Van Assche enum { 96dd11376bSBart Van Assche TX_SYMBOL_CLK_REQ_FORCE = 5, 97dd11376bSBart Van Assche }; 98dd11376bSBart Van Assche 99dd11376bSBart Van Assche /* 100dd11376bSBart Van Assche * VS_SAVEPOWERCONTROL 101dd11376bSBart Van Assche */ 102dd11376bSBart Van Assche enum { 103dd11376bSBart Van Assche RX_SYMBOL_CLK_GATE_EN = 0, 104dd11376bSBart Van Assche SYS_CLK_GATE_EN = 2, 105dd11376bSBart Van Assche TX_CLK_GATE_EN = 3, 106dd11376bSBart Van Assche }; 107dd11376bSBart Van Assche 108dd11376bSBart Van Assche /* 109dd11376bSBart Van Assche * Host capability 110dd11376bSBart Van Assche */ 111dd11376bSBart Van Assche enum ufs_mtk_host_caps { 112dd11376bSBart Van Assche UFS_MTK_CAP_BOOST_CRYPT_ENGINE = 1 << 0, 113dd11376bSBart Van Assche UFS_MTK_CAP_VA09_PWR_CTRL = 1 << 1, 114dd11376bSBart Van Assche UFS_MTK_CAP_DISABLE_AH8 = 1 << 2, 115dd11376bSBart Van Assche UFS_MTK_CAP_BROKEN_VCC = 1 << 3, 1163f9b6cecSCC Chou UFS_MTK_CAP_PMC_VIA_FASTAUTO = 1 << 6, 117dd11376bSBart Van Assche }; 118dd11376bSBart Van Assche 119dd11376bSBart Van Assche struct ufs_mtk_crypt_cfg { 120dd11376bSBart Van Assche struct regulator *reg_vcore; 121dd11376bSBart Van Assche struct clk *clk_crypt_perf; 122dd11376bSBart Van Assche struct clk *clk_crypt_mux; 123dd11376bSBart Van Assche struct clk *clk_crypt_lp; 124dd11376bSBart Van Assche int vcore_volt; 125dd11376bSBart Van Assche }; 126dd11376bSBart Van Assche 127*b7dbc686SPo-Wen Kao struct ufs_mtk_clk { 128*b7dbc686SPo-Wen Kao struct ufs_clk_info *ufs_sel_clki; /* Mux */ 129*b7dbc686SPo-Wen Kao struct ufs_clk_info *ufs_sel_max_clki; /* Max src */ 130*b7dbc686SPo-Wen Kao struct ufs_clk_info *ufs_sel_min_clki; /* Min src */ 131*b7dbc686SPo-Wen Kao }; 132*b7dbc686SPo-Wen Kao 133dd11376bSBart Van Assche struct ufs_mtk_hw_ver { 134dd11376bSBart Van Assche u8 step; 135dd11376bSBart Van Assche u8 minor; 136dd11376bSBart Van Assche u8 major; 137dd11376bSBart Van Assche }; 138dd11376bSBart Van Assche 139dd11376bSBart Van Assche struct ufs_mtk_host { 140dd11376bSBart Van Assche struct phy *mphy; 141c64c487dSPeter Wang struct pm_qos_request pm_qos_req; 142dd11376bSBart Van Assche struct regulator *reg_va09; 143dd11376bSBart Van Assche struct reset_control *hci_reset; 144dd11376bSBart Van Assche struct reset_control *unipro_reset; 145dd11376bSBart Van Assche struct reset_control *crypto_reset; 146dd11376bSBart Van Assche struct ufs_hba *hba; 147dd11376bSBart Van Assche struct ufs_mtk_crypt_cfg *crypt; 148*b7dbc686SPo-Wen Kao struct ufs_mtk_clk mclk; 149dd11376bSBart Van Assche struct ufs_mtk_hw_ver hw_ver; 150dd11376bSBart Van Assche enum ufs_mtk_host_caps caps; 151dd11376bSBart Van Assche bool mphy_powered_on; 152c64c487dSPeter Wang bool pm_qos_init; 153dd11376bSBart Van Assche bool unipro_lpm; 154dd11376bSBart Van Assche bool ref_clk_enabled; 155dd11376bSBart Van Assche u16 ref_clk_ungating_wait_us; 156dd11376bSBart Van Assche u16 ref_clk_gating_wait_us; 157dd11376bSBart Van Assche u32 ip_ver; 158dd11376bSBart Van Assche }; 159dd11376bSBart Van Assche 160bc602ae9SStanley Chu /* 161ece418d0SStanley Chu * Multi-VCC by Numbering 162ece418d0SStanley Chu */ 163ece418d0SStanley Chu enum ufs_mtk_vcc_num { 164ece418d0SStanley Chu UFS_VCC_NONE = 0, 165ece418d0SStanley Chu UFS_VCC_1, 166ece418d0SStanley Chu UFS_VCC_2, 167ece418d0SStanley Chu UFS_VCC_MAX 168ece418d0SStanley Chu }; 169ece418d0SStanley Chu 170ece418d0SStanley Chu /* 1712cf5cb2bSPo-Wen Kao * Host Power Control options 1722cf5cb2bSPo-Wen Kao */ 1732cf5cb2bSPo-Wen Kao enum { 1742cf5cb2bSPo-Wen Kao HOST_PWR_HCI = 0, 1752cf5cb2bSPo-Wen Kao HOST_PWR_MPHY 1762cf5cb2bSPo-Wen Kao }; 1772cf5cb2bSPo-Wen Kao 1782cf5cb2bSPo-Wen Kao /* 179bc602ae9SStanley Chu * SMC call wrapper function 180bc602ae9SStanley Chu */ 181bc602ae9SStanley Chu struct ufs_mtk_smc_arg { 182bc602ae9SStanley Chu unsigned long cmd; 183bc602ae9SStanley Chu struct arm_smccc_res *res; 184bc602ae9SStanley Chu unsigned long v1; 185bc602ae9SStanley Chu unsigned long v2; 186bc602ae9SStanley Chu unsigned long v3; 187bc602ae9SStanley Chu unsigned long v4; 188bc602ae9SStanley Chu unsigned long v5; 189bc602ae9SStanley Chu unsigned long v6; 190bc602ae9SStanley Chu unsigned long v7; 191bc602ae9SStanley Chu }; 192bc602ae9SStanley Chu 193bc602ae9SStanley Chu static void _ufs_mtk_smc(struct ufs_mtk_smc_arg s) 194bc602ae9SStanley Chu { 195bc602ae9SStanley Chu arm_smccc_smc(MTK_SIP_UFS_CONTROL, 196bc602ae9SStanley Chu s.cmd, s.v1, s.v2, s.v3, s.v4, s.v5, s.v6, s.res); 197bc602ae9SStanley Chu } 198bc602ae9SStanley Chu 199bc602ae9SStanley Chu #define ufs_mtk_smc(...) \ 200bc602ae9SStanley Chu _ufs_mtk_smc((struct ufs_mtk_smc_arg) {__VA_ARGS__}) 201bc602ae9SStanley Chu 202bc602ae9SStanley Chu /* 203bc602ae9SStanley Chu * SMC call interface 204bc602ae9SStanley Chu */ 205bc602ae9SStanley Chu #define ufs_mtk_va09_pwr_ctrl(res, on) \ 206bc602ae9SStanley Chu ufs_mtk_smc(UFS_MTK_SIP_VA09_PWR_CTRL, &(res), on) 207bc602ae9SStanley Chu 208bc602ae9SStanley Chu #define ufs_mtk_crypto_ctrl(res, enable) \ 209bc602ae9SStanley Chu ufs_mtk_smc(UFS_MTK_SIP_CRYPTO_CTRL, &(res), enable) 210bc602ae9SStanley Chu 211f53f1913SPeter Wang #define ufs_mtk_ref_clk_notify(on, stage, res) \ 212f53f1913SPeter Wang ufs_mtk_smc(UFS_MTK_SIP_REF_CLK_NOTIFICATION, &(res), on, stage) 213bc602ae9SStanley Chu 214bc602ae9SStanley Chu #define ufs_mtk_device_reset_ctrl(high, res) \ 215bc602ae9SStanley Chu ufs_mtk_smc(UFS_MTK_SIP_DEVICE_RESET, &(res), high) 216bc602ae9SStanley Chu 2172cf5cb2bSPo-Wen Kao #define ufs_mtk_host_pwr_ctrl(opt, on, res) \ 2182cf5cb2bSPo-Wen Kao ufs_mtk_smc(UFS_MTK_SIP_HOST_PWR_CTRL, &(res), opt, on) 2192cf5cb2bSPo-Wen Kao 220ece418d0SStanley Chu #define ufs_mtk_get_vcc_num(res) \ 221ece418d0SStanley Chu ufs_mtk_smc(UFS_MTK_SIP_GET_VCC_NUM, &(res)) 222ece418d0SStanley Chu 22342b19283SStanley Chu #define ufs_mtk_device_pwr_ctrl(on, ufs_ver, res) \ 22442b19283SStanley Chu ufs_mtk_smc(UFS_MTK_SIP_DEVICE_PWR_CTRL, &(res), on, ufs_ver) 22542b19283SStanley Chu 226dd11376bSBart Van Assche #endif /* !_UFS_MEDIATEK_H */ 227