1dd11376bSBart Van Assche /* SPDX-License-Identifier: GPL-2.0 */
2dd11376bSBart Van Assche /*
3dd11376bSBart Van Assche * Copyright (C) 2019 MediaTek Inc.
4dd11376bSBart Van Assche */
5dd11376bSBart Van Assche
6dd11376bSBart Van Assche #ifndef _UFS_MEDIATEK_H
7dd11376bSBart Van Assche #define _UFS_MEDIATEK_H
8dd11376bSBart Van Assche
9dd11376bSBart Van Assche #include <linux/bitops.h>
10c64c487dSPeter Wang #include <linux/pm_qos.h>
11dd11376bSBart Van Assche #include <linux/soc/mediatek/mtk_sip_svc.h>
12dd11376bSBart Van Assche
13dd11376bSBart Van Assche /*
14*e152a616SPo-Wen Kao * MCQ define and struct
15*e152a616SPo-Wen Kao */
16*e152a616SPo-Wen Kao #define UFSHCD_MAX_Q_NR 8
17*e152a616SPo-Wen Kao #define MTK_MCQ_INVALID_IRQ 0xFFFF
18*e152a616SPo-Wen Kao
19*e152a616SPo-Wen Kao /* REG_UFS_MMIO_OPT_CTRL_0 160h */
20*e152a616SPo-Wen Kao #define EHS_EN BIT(0)
21*e152a616SPo-Wen Kao #define PFM_IMPV BIT(1)
22*e152a616SPo-Wen Kao #define MCQ_MULTI_INTR_EN BIT(2)
23*e152a616SPo-Wen Kao #define MCQ_CMB_INTR_EN BIT(3)
24*e152a616SPo-Wen Kao #define MCQ_AH8 BIT(4)
25*e152a616SPo-Wen Kao
26*e152a616SPo-Wen Kao #define MCQ_INTR_EN_MSK (MCQ_MULTI_INTR_EN | MCQ_CMB_INTR_EN)
27*e152a616SPo-Wen Kao
28*e152a616SPo-Wen Kao /*
29dd11376bSBart Van Assche * Vendor specific UFSHCI Registers
30dd11376bSBart Van Assche */
312bae03a6SPeter Wang #define REG_UFS_XOUFS_CTRL 0x140
32dd11376bSBart Van Assche #define REG_UFS_REFCLK_CTRL 0x144
33*e152a616SPo-Wen Kao #define REG_UFS_MMIO_OPT_CTRL_0 0x160
34dd11376bSBart Van Assche #define REG_UFS_EXTREG 0x2100
35dd11376bSBart Van Assche #define REG_UFS_MPHYCTRL 0x2200
36dd11376bSBart Van Assche #define REG_UFS_MTK_IP_VER 0x2240
37dd11376bSBart Van Assche #define REG_UFS_REJECT_MON 0x22AC
38dd11376bSBart Van Assche #define REG_UFS_DEBUG_SEL 0x22C0
39dd11376bSBart Van Assche #define REG_UFS_PROBE 0x22C8
40dd11376bSBart Van Assche #define REG_UFS_DEBUG_SEL_B0 0x22D0
41dd11376bSBart Van Assche #define REG_UFS_DEBUG_SEL_B1 0x22D4
42dd11376bSBart Van Assche #define REG_UFS_DEBUG_SEL_B2 0x22D8
43dd11376bSBart Van Assche #define REG_UFS_DEBUG_SEL_B3 0x22DC
44dd11376bSBart Van Assche
45*e152a616SPo-Wen Kao #define REG_UFS_MTK_SQD 0x2800
46*e152a616SPo-Wen Kao #define REG_UFS_MTK_SQIS 0x2814
47*e152a616SPo-Wen Kao #define REG_UFS_MTK_CQD 0x281C
48*e152a616SPo-Wen Kao #define REG_UFS_MTK_CQIS 0x2824
49*e152a616SPo-Wen Kao
50*e152a616SPo-Wen Kao #define REG_UFS_MCQ_STRIDE 0x30
51*e152a616SPo-Wen Kao
52dd11376bSBart Van Assche /*
53dd11376bSBart Van Assche * Ref-clk control
54dd11376bSBart Van Assche *
55dd11376bSBart Van Assche * Values for register REG_UFS_REFCLK_CTRL
56dd11376bSBart Van Assche */
57dd11376bSBart Van Assche #define REFCLK_RELEASE 0x0
58dd11376bSBart Van Assche #define REFCLK_REQUEST BIT(0)
59dd11376bSBart Van Assche #define REFCLK_ACK BIT(1)
60dd11376bSBart Van Assche
61dd11376bSBart Van Assche #define REFCLK_REQ_TIMEOUT_US 3000
62dd11376bSBart Van Assche #define REFCLK_DEFAULT_WAIT_US 32
63dd11376bSBart Van Assche
64dd11376bSBart Van Assche /*
65dd11376bSBart Van Assche * Other attributes
66dd11376bSBart Van Assche */
67dd11376bSBart Van Assche #define VS_DEBUGCLOCKENABLE 0xD0A1
68dd11376bSBart Van Assche #define VS_SAVEPOWERCONTROL 0xD0A6
69dd11376bSBart Van Assche #define VS_UNIPROPOWERDOWNCONTROL 0xD0A8
70dd11376bSBart Van Assche
71dd11376bSBart Van Assche /*
72dd11376bSBart Van Assche * Vendor specific link state
73dd11376bSBart Van Assche */
74dd11376bSBart Van Assche enum {
75dd11376bSBart Van Assche VS_LINK_DISABLED = 0,
76dd11376bSBart Van Assche VS_LINK_DOWN = 1,
77dd11376bSBart Van Assche VS_LINK_UP = 2,
78dd11376bSBart Van Assche VS_LINK_HIBERN8 = 3,
79dd11376bSBart Van Assche VS_LINK_LOST = 4,
80dd11376bSBart Van Assche VS_LINK_CFG = 5,
81dd11376bSBart Van Assche };
82dd11376bSBart Van Assche
83dd11376bSBart Van Assche /*
84dd11376bSBart Van Assche * Vendor specific host controller state
85dd11376bSBart Van Assche */
86dd11376bSBart Van Assche enum {
87dd11376bSBart Van Assche VS_HCE_RESET = 0,
88dd11376bSBart Van Assche VS_HCE_BASE = 1,
89dd11376bSBart Van Assche VS_HCE_OOCPR_WAIT = 2,
90dd11376bSBart Van Assche VS_HCE_DME_RESET = 3,
91dd11376bSBart Van Assche VS_HCE_MIDDLE = 4,
92dd11376bSBart Van Assche VS_HCE_DME_ENABLE = 5,
93dd11376bSBart Van Assche VS_HCE_DEFAULTS = 6,
94dd11376bSBart Van Assche VS_HIB_IDLEEN = 7,
95dd11376bSBart Van Assche VS_HIB_ENTER = 8,
96dd11376bSBart Van Assche VS_HIB_ENTER_CONF = 9,
97dd11376bSBart Van Assche VS_HIB_MIDDLE = 10,
98dd11376bSBart Van Assche VS_HIB_WAITTIMER = 11,
99dd11376bSBart Van Assche VS_HIB_EXIT_CONF = 12,
100dd11376bSBart Van Assche VS_HIB_EXIT = 13,
101dd11376bSBart Van Assche };
102dd11376bSBart Van Assche
103dd11376bSBart Van Assche /*
104dd11376bSBart Van Assche * SiP commands
105dd11376bSBart Van Assche */
106dd11376bSBart Van Assche #define MTK_SIP_UFS_CONTROL MTK_SIP_SMC_CMD(0x276)
107dd11376bSBart Van Assche #define UFS_MTK_SIP_VA09_PWR_CTRL BIT(0)
108dd11376bSBart Van Assche #define UFS_MTK_SIP_DEVICE_RESET BIT(1)
109dd11376bSBart Van Assche #define UFS_MTK_SIP_CRYPTO_CTRL BIT(2)
110dd11376bSBart Van Assche #define UFS_MTK_SIP_REF_CLK_NOTIFICATION BIT(3)
1112cf5cb2bSPo-Wen Kao #define UFS_MTK_SIP_HOST_PWR_CTRL BIT(5)
112ece418d0SStanley Chu #define UFS_MTK_SIP_GET_VCC_NUM BIT(6)
11342b19283SStanley Chu #define UFS_MTK_SIP_DEVICE_PWR_CTRL BIT(7)
114dd11376bSBart Van Assche
115dd11376bSBart Van Assche /*
116dd11376bSBart Van Assche * VS_DEBUGCLOCKENABLE
117dd11376bSBart Van Assche */
118dd11376bSBart Van Assche enum {
119dd11376bSBart Van Assche TX_SYMBOL_CLK_REQ_FORCE = 5,
120dd11376bSBart Van Assche };
121dd11376bSBart Van Assche
122dd11376bSBart Van Assche /*
123dd11376bSBart Van Assche * VS_SAVEPOWERCONTROL
124dd11376bSBart Van Assche */
125dd11376bSBart Van Assche enum {
126dd11376bSBart Van Assche RX_SYMBOL_CLK_GATE_EN = 0,
127dd11376bSBart Van Assche SYS_CLK_GATE_EN = 2,
128dd11376bSBart Van Assche TX_CLK_GATE_EN = 3,
129dd11376bSBart Van Assche };
130dd11376bSBart Van Assche
131dd11376bSBart Van Assche /*
132dd11376bSBart Van Assche * Host capability
133dd11376bSBart Van Assche */
134dd11376bSBart Van Assche enum ufs_mtk_host_caps {
135dd11376bSBart Van Assche UFS_MTK_CAP_BOOST_CRYPT_ENGINE = 1 << 0,
136dd11376bSBart Van Assche UFS_MTK_CAP_VA09_PWR_CTRL = 1 << 1,
137dd11376bSBart Van Assche UFS_MTK_CAP_DISABLE_AH8 = 1 << 2,
138dd11376bSBart Van Assche UFS_MTK_CAP_BROKEN_VCC = 1 << 3,
1393f9b6cecSCC Chou UFS_MTK_CAP_PMC_VIA_FASTAUTO = 1 << 6,
140dd11376bSBart Van Assche };
141dd11376bSBart Van Assche
142dd11376bSBart Van Assche struct ufs_mtk_crypt_cfg {
143dd11376bSBart Van Assche struct regulator *reg_vcore;
144dd11376bSBart Van Assche struct clk *clk_crypt_perf;
145dd11376bSBart Van Assche struct clk *clk_crypt_mux;
146dd11376bSBart Van Assche struct clk *clk_crypt_lp;
147dd11376bSBart Van Assche int vcore_volt;
148dd11376bSBart Van Assche };
149dd11376bSBart Van Assche
150b7dbc686SPo-Wen Kao struct ufs_mtk_clk {
151b7dbc686SPo-Wen Kao struct ufs_clk_info *ufs_sel_clki; /* Mux */
152b7dbc686SPo-Wen Kao struct ufs_clk_info *ufs_sel_max_clki; /* Max src */
153b7dbc686SPo-Wen Kao struct ufs_clk_info *ufs_sel_min_clki; /* Min src */
154b7dbc686SPo-Wen Kao };
155b7dbc686SPo-Wen Kao
156dd11376bSBart Van Assche struct ufs_mtk_hw_ver {
157dd11376bSBart Van Assche u8 step;
158dd11376bSBart Van Assche u8 minor;
159dd11376bSBart Van Assche u8 major;
160dd11376bSBart Van Assche };
161dd11376bSBart Van Assche
162*e152a616SPo-Wen Kao struct ufs_mtk_mcq_intr_info {
163*e152a616SPo-Wen Kao struct ufs_hba *hba;
164*e152a616SPo-Wen Kao u32 irq;
165*e152a616SPo-Wen Kao u8 qid;
166*e152a616SPo-Wen Kao };
167*e152a616SPo-Wen Kao
168dd11376bSBart Van Assche struct ufs_mtk_host {
169dd11376bSBart Van Assche struct phy *mphy;
170c64c487dSPeter Wang struct pm_qos_request pm_qos_req;
171dd11376bSBart Van Assche struct regulator *reg_va09;
172dd11376bSBart Van Assche struct reset_control *hci_reset;
173dd11376bSBart Van Assche struct reset_control *unipro_reset;
174dd11376bSBart Van Assche struct reset_control *crypto_reset;
175dd11376bSBart Van Assche struct ufs_hba *hba;
176dd11376bSBart Van Assche struct ufs_mtk_crypt_cfg *crypt;
177b7dbc686SPo-Wen Kao struct ufs_mtk_clk mclk;
178dd11376bSBart Van Assche struct ufs_mtk_hw_ver hw_ver;
179dd11376bSBart Van Assche enum ufs_mtk_host_caps caps;
180dd11376bSBart Van Assche bool mphy_powered_on;
181c64c487dSPeter Wang bool pm_qos_init;
182dd11376bSBart Van Assche bool unipro_lpm;
183dd11376bSBart Van Assche bool ref_clk_enabled;
184dd11376bSBart Van Assche u16 ref_clk_ungating_wait_us;
185dd11376bSBart Van Assche u16 ref_clk_gating_wait_us;
186dd11376bSBart Van Assche u32 ip_ver;
187*e152a616SPo-Wen Kao
188*e152a616SPo-Wen Kao bool mcq_set_intr;
189*e152a616SPo-Wen Kao int mcq_nr_intr;
190*e152a616SPo-Wen Kao struct ufs_mtk_mcq_intr_info mcq_intr_info[UFSHCD_MAX_Q_NR];
191dd11376bSBart Van Assche };
192dd11376bSBart Van Assche
193bc602ae9SStanley Chu /*
194ece418d0SStanley Chu * Multi-VCC by Numbering
195ece418d0SStanley Chu */
196ece418d0SStanley Chu enum ufs_mtk_vcc_num {
197ece418d0SStanley Chu UFS_VCC_NONE = 0,
198ece418d0SStanley Chu UFS_VCC_1,
199ece418d0SStanley Chu UFS_VCC_2,
200ece418d0SStanley Chu UFS_VCC_MAX
201ece418d0SStanley Chu };
202ece418d0SStanley Chu
203ece418d0SStanley Chu /*
2042cf5cb2bSPo-Wen Kao * Host Power Control options
2052cf5cb2bSPo-Wen Kao */
2062cf5cb2bSPo-Wen Kao enum {
2072cf5cb2bSPo-Wen Kao HOST_PWR_HCI = 0,
2082cf5cb2bSPo-Wen Kao HOST_PWR_MPHY
2092cf5cb2bSPo-Wen Kao };
2102cf5cb2bSPo-Wen Kao
2112cf5cb2bSPo-Wen Kao /*
212bc602ae9SStanley Chu * SMC call wrapper function
213bc602ae9SStanley Chu */
214bc602ae9SStanley Chu struct ufs_mtk_smc_arg {
215bc602ae9SStanley Chu unsigned long cmd;
216bc602ae9SStanley Chu struct arm_smccc_res *res;
217bc602ae9SStanley Chu unsigned long v1;
218bc602ae9SStanley Chu unsigned long v2;
219bc602ae9SStanley Chu unsigned long v3;
220bc602ae9SStanley Chu unsigned long v4;
221bc602ae9SStanley Chu unsigned long v5;
222bc602ae9SStanley Chu unsigned long v6;
223bc602ae9SStanley Chu unsigned long v7;
224bc602ae9SStanley Chu };
225bc602ae9SStanley Chu
_ufs_mtk_smc(struct ufs_mtk_smc_arg s)226bc602ae9SStanley Chu static void _ufs_mtk_smc(struct ufs_mtk_smc_arg s)
227bc602ae9SStanley Chu {
228bc602ae9SStanley Chu arm_smccc_smc(MTK_SIP_UFS_CONTROL,
229bc602ae9SStanley Chu s.cmd, s.v1, s.v2, s.v3, s.v4, s.v5, s.v6, s.res);
230bc602ae9SStanley Chu }
231bc602ae9SStanley Chu
232bc602ae9SStanley Chu #define ufs_mtk_smc(...) \
233bc602ae9SStanley Chu _ufs_mtk_smc((struct ufs_mtk_smc_arg) {__VA_ARGS__})
234bc602ae9SStanley Chu
235bc602ae9SStanley Chu /*
236bc602ae9SStanley Chu * SMC call interface
237bc602ae9SStanley Chu */
238bc602ae9SStanley Chu #define ufs_mtk_va09_pwr_ctrl(res, on) \
239bc602ae9SStanley Chu ufs_mtk_smc(UFS_MTK_SIP_VA09_PWR_CTRL, &(res), on)
240bc602ae9SStanley Chu
241bc602ae9SStanley Chu #define ufs_mtk_crypto_ctrl(res, enable) \
242bc602ae9SStanley Chu ufs_mtk_smc(UFS_MTK_SIP_CRYPTO_CTRL, &(res), enable)
243bc602ae9SStanley Chu
244f53f1913SPeter Wang #define ufs_mtk_ref_clk_notify(on, stage, res) \
245f53f1913SPeter Wang ufs_mtk_smc(UFS_MTK_SIP_REF_CLK_NOTIFICATION, &(res), on, stage)
246bc602ae9SStanley Chu
247bc602ae9SStanley Chu #define ufs_mtk_device_reset_ctrl(high, res) \
248bc602ae9SStanley Chu ufs_mtk_smc(UFS_MTK_SIP_DEVICE_RESET, &(res), high)
249bc602ae9SStanley Chu
2502cf5cb2bSPo-Wen Kao #define ufs_mtk_host_pwr_ctrl(opt, on, res) \
2512cf5cb2bSPo-Wen Kao ufs_mtk_smc(UFS_MTK_SIP_HOST_PWR_CTRL, &(res), opt, on)
2522cf5cb2bSPo-Wen Kao
253ece418d0SStanley Chu #define ufs_mtk_get_vcc_num(res) \
254ece418d0SStanley Chu ufs_mtk_smc(UFS_MTK_SIP_GET_VCC_NUM, &(res))
255ece418d0SStanley Chu
25642b19283SStanley Chu #define ufs_mtk_device_pwr_ctrl(on, ufs_ver, res) \
25742b19283SStanley Chu ufs_mtk_smc(UFS_MTK_SIP_DEVICE_PWR_CTRL, &(res), on, ufs_ver)
25842b19283SStanley Chu
259dd11376bSBart Van Assche #endif /* !_UFS_MEDIATEK_H */
260