1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Universal Flash Storage Host controller driver Core 4 * Copyright (C) 2011-2013 Samsung India Software Operations 5 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. 6 * 7 * Authors: 8 * Santosh Yaraganavi <santosh.sy@samsung.com> 9 * Vinayak Holikatti <h.vinayak@samsung.com> 10 */ 11 12 #include <linux/async.h> 13 #include <linux/devfreq.h> 14 #include <linux/nls.h> 15 #include <linux/of.h> 16 #include <linux/bitfield.h> 17 #include <linux/blk-pm.h> 18 #include <linux/blkdev.h> 19 #include <linux/clk.h> 20 #include <linux/delay.h> 21 #include <linux/interrupt.h> 22 #include <linux/module.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/sched/clock.h> 25 #include <linux/iopoll.h> 26 #include <scsi/scsi_cmnd.h> 27 #include <scsi/scsi_dbg.h> 28 #include <scsi/scsi_driver.h> 29 #include <scsi/scsi_eh.h> 30 #include "ufshcd-priv.h" 31 #include <ufs/ufs_quirks.h> 32 #include <ufs/unipro.h> 33 #include "ufs-sysfs.h" 34 #include "ufs-debugfs.h" 35 #include "ufs-fault-injection.h" 36 #include "ufs_bsg.h" 37 #include "ufshcd-crypto.h" 38 #include <asm/unaligned.h> 39 40 #define CREATE_TRACE_POINTS 41 #include <trace/events/ufs.h> 42 43 #define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\ 44 UTP_TASK_REQ_COMPL |\ 45 UFSHCD_ERROR_MASK) 46 47 #define UFSHCD_ENABLE_MCQ_INTRS (UTP_TASK_REQ_COMPL |\ 48 UFSHCD_ERROR_MASK |\ 49 MCQ_CQ_EVENT_STATUS) 50 51 52 /* UIC command timeout, unit: ms */ 53 #define UIC_CMD_TIMEOUT 500 54 55 /* NOP OUT retries waiting for NOP IN response */ 56 #define NOP_OUT_RETRIES 10 57 /* Timeout after 50 msecs if NOP OUT hangs without response */ 58 #define NOP_OUT_TIMEOUT 50 /* msecs */ 59 60 /* Query request retries */ 61 #define QUERY_REQ_RETRIES 3 62 /* Query request timeout */ 63 #define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */ 64 65 /* Advanced RPMB request timeout */ 66 #define ADVANCED_RPMB_REQ_TIMEOUT 3000 /* 3 seconds */ 67 68 /* Task management command timeout */ 69 #define TM_CMD_TIMEOUT 100 /* msecs */ 70 71 /* maximum number of retries for a general UIC command */ 72 #define UFS_UIC_COMMAND_RETRIES 3 73 74 /* maximum number of link-startup retries */ 75 #define DME_LINKSTARTUP_RETRIES 3 76 77 /* maximum number of reset retries before giving up */ 78 #define MAX_HOST_RESET_RETRIES 5 79 80 /* Maximum number of error handler retries before giving up */ 81 #define MAX_ERR_HANDLER_RETRIES 5 82 83 /* Expose the flag value from utp_upiu_query.value */ 84 #define MASK_QUERY_UPIU_FLAG_LOC 0xFF 85 86 /* Interrupt aggregation default timeout, unit: 40us */ 87 #define INT_AGGR_DEF_TO 0x02 88 89 /* default delay of autosuspend: 2000 ms */ 90 #define RPM_AUTOSUSPEND_DELAY_MS 2000 91 92 /* Default delay of RPM device flush delayed work */ 93 #define RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS 5000 94 95 /* Default value of wait time before gating device ref clock */ 96 #define UFSHCD_REF_CLK_GATING_WAIT_US 0xFF /* microsecs */ 97 98 /* Polling time to wait for fDeviceInit */ 99 #define FDEVICEINIT_COMPL_TIMEOUT 1500 /* millisecs */ 100 101 /* UFSHC 4.0 compliant HC support this mode. */ 102 static bool use_mcq_mode = true; 103 104 static bool is_mcq_supported(struct ufs_hba *hba) 105 { 106 return hba->mcq_sup && use_mcq_mode; 107 } 108 109 module_param(use_mcq_mode, bool, 0644); 110 MODULE_PARM_DESC(use_mcq_mode, "Control MCQ mode for controllers starting from UFSHCI 4.0. 1 - enable MCQ, 0 - disable MCQ. MCQ is enabled by default"); 111 112 #define ufshcd_toggle_vreg(_dev, _vreg, _on) \ 113 ({ \ 114 int _ret; \ 115 if (_on) \ 116 _ret = ufshcd_enable_vreg(_dev, _vreg); \ 117 else \ 118 _ret = ufshcd_disable_vreg(_dev, _vreg); \ 119 _ret; \ 120 }) 121 122 #define ufshcd_hex_dump(prefix_str, buf, len) do { \ 123 size_t __len = (len); \ 124 print_hex_dump(KERN_ERR, prefix_str, \ 125 __len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE,\ 126 16, 4, buf, __len, false); \ 127 } while (0) 128 129 int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len, 130 const char *prefix) 131 { 132 u32 *regs; 133 size_t pos; 134 135 if (offset % 4 != 0 || len % 4 != 0) /* keep readl happy */ 136 return -EINVAL; 137 138 regs = kzalloc(len, GFP_ATOMIC); 139 if (!regs) 140 return -ENOMEM; 141 142 for (pos = 0; pos < len; pos += 4) { 143 if (offset == 0 && 144 pos >= REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER && 145 pos <= REG_UIC_ERROR_CODE_DME) 146 continue; 147 regs[pos / 4] = ufshcd_readl(hba, offset + pos); 148 } 149 150 ufshcd_hex_dump(prefix, regs, len); 151 kfree(regs); 152 153 return 0; 154 } 155 EXPORT_SYMBOL_GPL(ufshcd_dump_regs); 156 157 enum { 158 UFSHCD_MAX_CHANNEL = 0, 159 UFSHCD_MAX_ID = 1, 160 UFSHCD_CMD_PER_LUN = 32 - UFSHCD_NUM_RESERVED, 161 UFSHCD_CAN_QUEUE = 32 - UFSHCD_NUM_RESERVED, 162 }; 163 164 static const char *const ufshcd_state_name[] = { 165 [UFSHCD_STATE_RESET] = "reset", 166 [UFSHCD_STATE_OPERATIONAL] = "operational", 167 [UFSHCD_STATE_ERROR] = "error", 168 [UFSHCD_STATE_EH_SCHEDULED_FATAL] = "eh_fatal", 169 [UFSHCD_STATE_EH_SCHEDULED_NON_FATAL] = "eh_non_fatal", 170 }; 171 172 /* UFSHCD error handling flags */ 173 enum { 174 UFSHCD_EH_IN_PROGRESS = (1 << 0), 175 }; 176 177 /* UFSHCD UIC layer error flags */ 178 enum { 179 UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */ 180 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR = (1 << 1), /* Data link layer error */ 181 UFSHCD_UIC_DL_TCx_REPLAY_ERROR = (1 << 2), /* Data link layer error */ 182 UFSHCD_UIC_NL_ERROR = (1 << 3), /* Network layer error */ 183 UFSHCD_UIC_TL_ERROR = (1 << 4), /* Transport Layer error */ 184 UFSHCD_UIC_DME_ERROR = (1 << 5), /* DME error */ 185 UFSHCD_UIC_PA_GENERIC_ERROR = (1 << 6), /* Generic PA error */ 186 }; 187 188 #define ufshcd_set_eh_in_progress(h) \ 189 ((h)->eh_flags |= UFSHCD_EH_IN_PROGRESS) 190 #define ufshcd_eh_in_progress(h) \ 191 ((h)->eh_flags & UFSHCD_EH_IN_PROGRESS) 192 #define ufshcd_clear_eh_in_progress(h) \ 193 ((h)->eh_flags &= ~UFSHCD_EH_IN_PROGRESS) 194 195 const struct ufs_pm_lvl_states ufs_pm_lvl_states[] = { 196 [UFS_PM_LVL_0] = {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE}, 197 [UFS_PM_LVL_1] = {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE}, 198 [UFS_PM_LVL_2] = {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE}, 199 [UFS_PM_LVL_3] = {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE}, 200 [UFS_PM_LVL_4] = {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE}, 201 [UFS_PM_LVL_5] = {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE}, 202 /* 203 * For DeepSleep, the link is first put in hibern8 and then off. 204 * Leaving the link in hibern8 is not supported. 205 */ 206 [UFS_PM_LVL_6] = {UFS_DEEPSLEEP_PWR_MODE, UIC_LINK_OFF_STATE}, 207 }; 208 209 static inline enum ufs_dev_pwr_mode 210 ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl) 211 { 212 return ufs_pm_lvl_states[lvl].dev_state; 213 } 214 215 static inline enum uic_link_state 216 ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl) 217 { 218 return ufs_pm_lvl_states[lvl].link_state; 219 } 220 221 static inline enum ufs_pm_level 222 ufs_get_desired_pm_lvl_for_dev_link_state(enum ufs_dev_pwr_mode dev_state, 223 enum uic_link_state link_state) 224 { 225 enum ufs_pm_level lvl; 226 227 for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++) { 228 if ((ufs_pm_lvl_states[lvl].dev_state == dev_state) && 229 (ufs_pm_lvl_states[lvl].link_state == link_state)) 230 return lvl; 231 } 232 233 /* if no match found, return the level 0 */ 234 return UFS_PM_LVL_0; 235 } 236 237 static const struct ufs_dev_quirk ufs_fixups[] = { 238 /* UFS cards deviations table */ 239 { .wmanufacturerid = UFS_VENDOR_MICRON, 240 .model = UFS_ANY_MODEL, 241 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM }, 242 { .wmanufacturerid = UFS_VENDOR_SAMSUNG, 243 .model = UFS_ANY_MODEL, 244 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM | 245 UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE | 246 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS }, 247 { .wmanufacturerid = UFS_VENDOR_SKHYNIX, 248 .model = UFS_ANY_MODEL, 249 .quirk = UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME }, 250 { .wmanufacturerid = UFS_VENDOR_SKHYNIX, 251 .model = "hB8aL1" /*H28U62301AMR*/, 252 .quirk = UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME }, 253 { .wmanufacturerid = UFS_VENDOR_TOSHIBA, 254 .model = UFS_ANY_MODEL, 255 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM }, 256 { .wmanufacturerid = UFS_VENDOR_TOSHIBA, 257 .model = "THGLF2G9C8KBADG", 258 .quirk = UFS_DEVICE_QUIRK_PA_TACTIVATE }, 259 { .wmanufacturerid = UFS_VENDOR_TOSHIBA, 260 .model = "THGLF2G9D8KBADG", 261 .quirk = UFS_DEVICE_QUIRK_PA_TACTIVATE }, 262 {} 263 }; 264 265 static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba); 266 static void ufshcd_async_scan(void *data, async_cookie_t cookie); 267 static int ufshcd_reset_and_restore(struct ufs_hba *hba); 268 static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd); 269 static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag); 270 static void ufshcd_hba_exit(struct ufs_hba *hba); 271 static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params); 272 static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on); 273 static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba); 274 static int ufshcd_host_reset_and_restore(struct ufs_hba *hba); 275 static void ufshcd_resume_clkscaling(struct ufs_hba *hba); 276 static void ufshcd_suspend_clkscaling(struct ufs_hba *hba); 277 static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba); 278 static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up); 279 static irqreturn_t ufshcd_intr(int irq, void *__hba); 280 static int ufshcd_change_power_mode(struct ufs_hba *hba, 281 struct ufs_pa_layer_attr *pwr_mode); 282 static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on); 283 static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on); 284 static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba, 285 struct ufs_vreg *vreg); 286 static void ufshcd_wb_toggle_buf_flush_during_h8(struct ufs_hba *hba, 287 bool enable); 288 static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba); 289 static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba); 290 291 static inline void ufshcd_enable_irq(struct ufs_hba *hba) 292 { 293 if (!hba->is_irq_enabled) { 294 enable_irq(hba->irq); 295 hba->is_irq_enabled = true; 296 } 297 } 298 299 static inline void ufshcd_disable_irq(struct ufs_hba *hba) 300 { 301 if (hba->is_irq_enabled) { 302 disable_irq(hba->irq); 303 hba->is_irq_enabled = false; 304 } 305 } 306 307 static void ufshcd_configure_wb(struct ufs_hba *hba) 308 { 309 if (!ufshcd_is_wb_allowed(hba)) 310 return; 311 312 ufshcd_wb_toggle(hba, true); 313 314 ufshcd_wb_toggle_buf_flush_during_h8(hba, true); 315 316 if (ufshcd_is_wb_buf_flush_allowed(hba)) 317 ufshcd_wb_toggle_buf_flush(hba, true); 318 } 319 320 static void ufshcd_scsi_unblock_requests(struct ufs_hba *hba) 321 { 322 if (atomic_dec_and_test(&hba->scsi_block_reqs_cnt)) 323 scsi_unblock_requests(hba->host); 324 } 325 326 static void ufshcd_scsi_block_requests(struct ufs_hba *hba) 327 { 328 if (atomic_inc_return(&hba->scsi_block_reqs_cnt) == 1) 329 scsi_block_requests(hba->host); 330 } 331 332 static void ufshcd_add_cmd_upiu_trace(struct ufs_hba *hba, unsigned int tag, 333 enum ufs_trace_str_t str_t) 334 { 335 struct utp_upiu_req *rq = hba->lrb[tag].ucd_req_ptr; 336 struct utp_upiu_header *header; 337 338 if (!trace_ufshcd_upiu_enabled()) 339 return; 340 341 if (str_t == UFS_CMD_SEND) 342 header = &rq->header; 343 else 344 header = &hba->lrb[tag].ucd_rsp_ptr->header; 345 346 trace_ufshcd_upiu(dev_name(hba->dev), str_t, header, &rq->sc.cdb, 347 UFS_TSF_CDB); 348 } 349 350 static void ufshcd_add_query_upiu_trace(struct ufs_hba *hba, 351 enum ufs_trace_str_t str_t, 352 struct utp_upiu_req *rq_rsp) 353 { 354 if (!trace_ufshcd_upiu_enabled()) 355 return; 356 357 trace_ufshcd_upiu(dev_name(hba->dev), str_t, &rq_rsp->header, 358 &rq_rsp->qr, UFS_TSF_OSF); 359 } 360 361 static void ufshcd_add_tm_upiu_trace(struct ufs_hba *hba, unsigned int tag, 362 enum ufs_trace_str_t str_t) 363 { 364 struct utp_task_req_desc *descp = &hba->utmrdl_base_addr[tag]; 365 366 if (!trace_ufshcd_upiu_enabled()) 367 return; 368 369 if (str_t == UFS_TM_SEND) 370 trace_ufshcd_upiu(dev_name(hba->dev), str_t, 371 &descp->upiu_req.req_header, 372 &descp->upiu_req.input_param1, 373 UFS_TSF_TM_INPUT); 374 else 375 trace_ufshcd_upiu(dev_name(hba->dev), str_t, 376 &descp->upiu_rsp.rsp_header, 377 &descp->upiu_rsp.output_param1, 378 UFS_TSF_TM_OUTPUT); 379 } 380 381 static void ufshcd_add_uic_command_trace(struct ufs_hba *hba, 382 const struct uic_command *ucmd, 383 enum ufs_trace_str_t str_t) 384 { 385 u32 cmd; 386 387 if (!trace_ufshcd_uic_command_enabled()) 388 return; 389 390 if (str_t == UFS_CMD_SEND) 391 cmd = ucmd->command; 392 else 393 cmd = ufshcd_readl(hba, REG_UIC_COMMAND); 394 395 trace_ufshcd_uic_command(dev_name(hba->dev), str_t, cmd, 396 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_1), 397 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2), 398 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3)); 399 } 400 401 static void ufshcd_add_command_trace(struct ufs_hba *hba, unsigned int tag, 402 enum ufs_trace_str_t str_t) 403 { 404 u64 lba = 0; 405 u8 opcode = 0, group_id = 0; 406 u32 doorbell = 0; 407 u32 intr; 408 int hwq_id = -1; 409 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 410 struct scsi_cmnd *cmd = lrbp->cmd; 411 struct request *rq = scsi_cmd_to_rq(cmd); 412 int transfer_len = -1; 413 414 if (!cmd) 415 return; 416 417 /* trace UPIU also */ 418 ufshcd_add_cmd_upiu_trace(hba, tag, str_t); 419 if (!trace_ufshcd_command_enabled()) 420 return; 421 422 opcode = cmd->cmnd[0]; 423 424 if (opcode == READ_10 || opcode == WRITE_10) { 425 /* 426 * Currently we only fully trace read(10) and write(10) commands 427 */ 428 transfer_len = 429 be32_to_cpu(lrbp->ucd_req_ptr->sc.exp_data_transfer_len); 430 lba = scsi_get_lba(cmd); 431 if (opcode == WRITE_10) 432 group_id = lrbp->cmd->cmnd[6]; 433 } else if (opcode == UNMAP) { 434 /* 435 * The number of Bytes to be unmapped beginning with the lba. 436 */ 437 transfer_len = blk_rq_bytes(rq); 438 lba = scsi_get_lba(cmd); 439 } 440 441 intr = ufshcd_readl(hba, REG_INTERRUPT_STATUS); 442 443 if (is_mcq_enabled(hba)) { 444 struct ufs_hw_queue *hwq = ufshcd_mcq_req_to_hwq(hba, rq); 445 446 hwq_id = hwq->id; 447 } else { 448 doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 449 } 450 trace_ufshcd_command(dev_name(hba->dev), str_t, tag, 451 doorbell, hwq_id, transfer_len, intr, lba, opcode, group_id); 452 } 453 454 static void ufshcd_print_clk_freqs(struct ufs_hba *hba) 455 { 456 struct ufs_clk_info *clki; 457 struct list_head *head = &hba->clk_list_head; 458 459 if (list_empty(head)) 460 return; 461 462 list_for_each_entry(clki, head, list) { 463 if (!IS_ERR_OR_NULL(clki->clk) && clki->min_freq && 464 clki->max_freq) 465 dev_err(hba->dev, "clk: %s, rate: %u\n", 466 clki->name, clki->curr_freq); 467 } 468 } 469 470 static void ufshcd_print_evt(struct ufs_hba *hba, u32 id, 471 const char *err_name) 472 { 473 int i; 474 bool found = false; 475 const struct ufs_event_hist *e; 476 477 if (id >= UFS_EVT_CNT) 478 return; 479 480 e = &hba->ufs_stats.event[id]; 481 482 for (i = 0; i < UFS_EVENT_HIST_LENGTH; i++) { 483 int p = (i + e->pos) % UFS_EVENT_HIST_LENGTH; 484 485 if (e->tstamp[p] == 0) 486 continue; 487 dev_err(hba->dev, "%s[%d] = 0x%x at %lld us\n", err_name, p, 488 e->val[p], div_u64(e->tstamp[p], 1000)); 489 found = true; 490 } 491 492 if (!found) 493 dev_err(hba->dev, "No record of %s\n", err_name); 494 else 495 dev_err(hba->dev, "%s: total cnt=%llu\n", err_name, e->cnt); 496 } 497 498 static void ufshcd_print_evt_hist(struct ufs_hba *hba) 499 { 500 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: "); 501 502 ufshcd_print_evt(hba, UFS_EVT_PA_ERR, "pa_err"); 503 ufshcd_print_evt(hba, UFS_EVT_DL_ERR, "dl_err"); 504 ufshcd_print_evt(hba, UFS_EVT_NL_ERR, "nl_err"); 505 ufshcd_print_evt(hba, UFS_EVT_TL_ERR, "tl_err"); 506 ufshcd_print_evt(hba, UFS_EVT_DME_ERR, "dme_err"); 507 ufshcd_print_evt(hba, UFS_EVT_AUTO_HIBERN8_ERR, 508 "auto_hibern8_err"); 509 ufshcd_print_evt(hba, UFS_EVT_FATAL_ERR, "fatal_err"); 510 ufshcd_print_evt(hba, UFS_EVT_LINK_STARTUP_FAIL, 511 "link_startup_fail"); 512 ufshcd_print_evt(hba, UFS_EVT_RESUME_ERR, "resume_fail"); 513 ufshcd_print_evt(hba, UFS_EVT_SUSPEND_ERR, 514 "suspend_fail"); 515 ufshcd_print_evt(hba, UFS_EVT_WL_RES_ERR, "wlun resume_fail"); 516 ufshcd_print_evt(hba, UFS_EVT_WL_SUSP_ERR, 517 "wlun suspend_fail"); 518 ufshcd_print_evt(hba, UFS_EVT_DEV_RESET, "dev_reset"); 519 ufshcd_print_evt(hba, UFS_EVT_HOST_RESET, "host_reset"); 520 ufshcd_print_evt(hba, UFS_EVT_ABORT, "task_abort"); 521 522 ufshcd_vops_dbg_register_dump(hba); 523 } 524 525 static 526 void ufshcd_print_tr(struct ufs_hba *hba, int tag, bool pr_prdt) 527 { 528 const struct ufshcd_lrb *lrbp; 529 int prdt_length; 530 531 lrbp = &hba->lrb[tag]; 532 533 dev_err(hba->dev, "UPIU[%d] - issue time %lld us\n", 534 tag, div_u64(lrbp->issue_time_stamp_local_clock, 1000)); 535 dev_err(hba->dev, "UPIU[%d] - complete time %lld us\n", 536 tag, div_u64(lrbp->compl_time_stamp_local_clock, 1000)); 537 dev_err(hba->dev, 538 "UPIU[%d] - Transfer Request Descriptor phys@0x%llx\n", 539 tag, (u64)lrbp->utrd_dma_addr); 540 541 ufshcd_hex_dump("UPIU TRD: ", lrbp->utr_descriptor_ptr, 542 sizeof(struct utp_transfer_req_desc)); 543 dev_err(hba->dev, "UPIU[%d] - Request UPIU phys@0x%llx\n", tag, 544 (u64)lrbp->ucd_req_dma_addr); 545 ufshcd_hex_dump("UPIU REQ: ", lrbp->ucd_req_ptr, 546 sizeof(struct utp_upiu_req)); 547 dev_err(hba->dev, "UPIU[%d] - Response UPIU phys@0x%llx\n", tag, 548 (u64)lrbp->ucd_rsp_dma_addr); 549 ufshcd_hex_dump("UPIU RSP: ", lrbp->ucd_rsp_ptr, 550 sizeof(struct utp_upiu_rsp)); 551 552 prdt_length = le16_to_cpu( 553 lrbp->utr_descriptor_ptr->prd_table_length); 554 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) 555 prdt_length /= ufshcd_sg_entry_size(hba); 556 557 dev_err(hba->dev, 558 "UPIU[%d] - PRDT - %d entries phys@0x%llx\n", 559 tag, prdt_length, 560 (u64)lrbp->ucd_prdt_dma_addr); 561 562 if (pr_prdt) 563 ufshcd_hex_dump("UPIU PRDT: ", lrbp->ucd_prdt_ptr, 564 ufshcd_sg_entry_size(hba) * prdt_length); 565 } 566 567 static bool ufshcd_print_tr_iter(struct request *req, void *priv) 568 { 569 struct scsi_device *sdev = req->q->queuedata; 570 struct Scsi_Host *shost = sdev->host; 571 struct ufs_hba *hba = shost_priv(shost); 572 573 ufshcd_print_tr(hba, req->tag, *(bool *)priv); 574 575 return true; 576 } 577 578 /** 579 * ufshcd_print_trs_all - print trs for all started requests. 580 * @hba: per-adapter instance. 581 * @pr_prdt: need to print prdt or not. 582 */ 583 static void ufshcd_print_trs_all(struct ufs_hba *hba, bool pr_prdt) 584 { 585 blk_mq_tagset_busy_iter(&hba->host->tag_set, ufshcd_print_tr_iter, &pr_prdt); 586 } 587 588 static void ufshcd_print_tmrs(struct ufs_hba *hba, unsigned long bitmap) 589 { 590 int tag; 591 592 for_each_set_bit(tag, &bitmap, hba->nutmrs) { 593 struct utp_task_req_desc *tmrdp = &hba->utmrdl_base_addr[tag]; 594 595 dev_err(hba->dev, "TM[%d] - Task Management Header\n", tag); 596 ufshcd_hex_dump("", tmrdp, sizeof(*tmrdp)); 597 } 598 } 599 600 static void ufshcd_print_host_state(struct ufs_hba *hba) 601 { 602 const struct scsi_device *sdev_ufs = hba->ufs_device_wlun; 603 604 dev_err(hba->dev, "UFS Host state=%d\n", hba->ufshcd_state); 605 dev_err(hba->dev, "outstanding reqs=0x%lx tasks=0x%lx\n", 606 hba->outstanding_reqs, hba->outstanding_tasks); 607 dev_err(hba->dev, "saved_err=0x%x, saved_uic_err=0x%x\n", 608 hba->saved_err, hba->saved_uic_err); 609 dev_err(hba->dev, "Device power mode=%d, UIC link state=%d\n", 610 hba->curr_dev_pwr_mode, hba->uic_link_state); 611 dev_err(hba->dev, "PM in progress=%d, sys. suspended=%d\n", 612 hba->pm_op_in_progress, hba->is_sys_suspended); 613 dev_err(hba->dev, "Auto BKOPS=%d, Host self-block=%d\n", 614 hba->auto_bkops_enabled, hba->host->host_self_blocked); 615 dev_err(hba->dev, "Clk gate=%d\n", hba->clk_gating.state); 616 dev_err(hba->dev, 617 "last_hibern8_exit_tstamp at %lld us, hibern8_exit_cnt=%d\n", 618 div_u64(hba->ufs_stats.last_hibern8_exit_tstamp, 1000), 619 hba->ufs_stats.hibern8_exit_cnt); 620 dev_err(hba->dev, "last intr at %lld us, last intr status=0x%x\n", 621 div_u64(hba->ufs_stats.last_intr_ts, 1000), 622 hba->ufs_stats.last_intr_status); 623 dev_err(hba->dev, "error handling flags=0x%x, req. abort count=%d\n", 624 hba->eh_flags, hba->req_abort_count); 625 dev_err(hba->dev, "hba->ufs_version=0x%x, Host capabilities=0x%x, caps=0x%x\n", 626 hba->ufs_version, hba->capabilities, hba->caps); 627 dev_err(hba->dev, "quirks=0x%x, dev. quirks=0x%x\n", hba->quirks, 628 hba->dev_quirks); 629 if (sdev_ufs) 630 dev_err(hba->dev, "UFS dev info: %.8s %.16s rev %.4s\n", 631 sdev_ufs->vendor, sdev_ufs->model, sdev_ufs->rev); 632 633 ufshcd_print_clk_freqs(hba); 634 } 635 636 /** 637 * ufshcd_print_pwr_info - print power params as saved in hba 638 * power info 639 * @hba: per-adapter instance 640 */ 641 static void ufshcd_print_pwr_info(struct ufs_hba *hba) 642 { 643 static const char * const names[] = { 644 "INVALID MODE", 645 "FAST MODE", 646 "SLOW_MODE", 647 "INVALID MODE", 648 "FASTAUTO_MODE", 649 "SLOWAUTO_MODE", 650 "INVALID MODE", 651 }; 652 653 /* 654 * Using dev_dbg to avoid messages during runtime PM to avoid 655 * never-ending cycles of messages written back to storage by user space 656 * causing runtime resume, causing more messages and so on. 657 */ 658 dev_dbg(hba->dev, "%s:[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n", 659 __func__, 660 hba->pwr_info.gear_rx, hba->pwr_info.gear_tx, 661 hba->pwr_info.lane_rx, hba->pwr_info.lane_tx, 662 names[hba->pwr_info.pwr_rx], 663 names[hba->pwr_info.pwr_tx], 664 hba->pwr_info.hs_rate); 665 } 666 667 static void ufshcd_device_reset(struct ufs_hba *hba) 668 { 669 int err; 670 671 err = ufshcd_vops_device_reset(hba); 672 673 if (!err) { 674 ufshcd_set_ufs_dev_active(hba); 675 if (ufshcd_is_wb_allowed(hba)) { 676 hba->dev_info.wb_enabled = false; 677 hba->dev_info.wb_buf_flush_enabled = false; 678 } 679 } 680 if (err != -EOPNOTSUPP) 681 ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, err); 682 } 683 684 void ufshcd_delay_us(unsigned long us, unsigned long tolerance) 685 { 686 if (!us) 687 return; 688 689 if (us < 10) 690 udelay(us); 691 else 692 usleep_range(us, us + tolerance); 693 } 694 EXPORT_SYMBOL_GPL(ufshcd_delay_us); 695 696 /** 697 * ufshcd_wait_for_register - wait for register value to change 698 * @hba: per-adapter interface 699 * @reg: mmio register offset 700 * @mask: mask to apply to the read register value 701 * @val: value to wait for 702 * @interval_us: polling interval in microseconds 703 * @timeout_ms: timeout in milliseconds 704 * 705 * Return: -ETIMEDOUT on error, zero on success. 706 */ 707 static int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask, 708 u32 val, unsigned long interval_us, 709 unsigned long timeout_ms) 710 { 711 int err = 0; 712 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms); 713 714 /* ignore bits that we don't intend to wait on */ 715 val = val & mask; 716 717 while ((ufshcd_readl(hba, reg) & mask) != val) { 718 usleep_range(interval_us, interval_us + 50); 719 if (time_after(jiffies, timeout)) { 720 if ((ufshcd_readl(hba, reg) & mask) != val) 721 err = -ETIMEDOUT; 722 break; 723 } 724 } 725 726 return err; 727 } 728 729 /** 730 * ufshcd_get_intr_mask - Get the interrupt bit mask 731 * @hba: Pointer to adapter instance 732 * 733 * Return: interrupt bit mask per version 734 */ 735 static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba) 736 { 737 if (hba->ufs_version == ufshci_version(1, 0)) 738 return INTERRUPT_MASK_ALL_VER_10; 739 if (hba->ufs_version <= ufshci_version(2, 0)) 740 return INTERRUPT_MASK_ALL_VER_11; 741 742 return INTERRUPT_MASK_ALL_VER_21; 743 } 744 745 /** 746 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA 747 * @hba: Pointer to adapter instance 748 * 749 * Return: UFSHCI version supported by the controller 750 */ 751 static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba) 752 { 753 u32 ufshci_ver; 754 755 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION) 756 ufshci_ver = ufshcd_vops_get_ufs_hci_version(hba); 757 else 758 ufshci_ver = ufshcd_readl(hba, REG_UFS_VERSION); 759 760 /* 761 * UFSHCI v1.x uses a different version scheme, in order 762 * to allow the use of comparisons with the ufshci_version 763 * function, we convert it to the same scheme as ufs 2.0+. 764 */ 765 if (ufshci_ver & 0x00010000) 766 return ufshci_version(1, ufshci_ver & 0x00000100); 767 768 return ufshci_ver; 769 } 770 771 /** 772 * ufshcd_is_device_present - Check if any device connected to 773 * the host controller 774 * @hba: pointer to adapter instance 775 * 776 * Return: true if device present, false if no device detected 777 */ 778 static inline bool ufshcd_is_device_present(struct ufs_hba *hba) 779 { 780 return ufshcd_readl(hba, REG_CONTROLLER_STATUS) & DEVICE_PRESENT; 781 } 782 783 /** 784 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status 785 * @lrbp: pointer to local command reference block 786 * @cqe: pointer to the completion queue entry 787 * 788 * This function is used to get the OCS field from UTRD 789 * 790 * Return: the OCS field in the UTRD. 791 */ 792 static enum utp_ocs ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp, 793 struct cq_entry *cqe) 794 { 795 if (cqe) 796 return le32_to_cpu(cqe->status) & MASK_OCS; 797 798 return lrbp->utr_descriptor_ptr->header.ocs & MASK_OCS; 799 } 800 801 /** 802 * ufshcd_utrl_clear() - Clear requests from the controller request list. 803 * @hba: per adapter instance 804 * @mask: mask with one bit set for each request to be cleared 805 */ 806 static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 mask) 807 { 808 if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR) 809 mask = ~mask; 810 /* 811 * From the UFSHCI specification: "UTP Transfer Request List CLear 812 * Register (UTRLCLR): This field is bit significant. Each bit 813 * corresponds to a slot in the UTP Transfer Request List, where bit 0 814 * corresponds to request slot 0. A bit in this field is set to ‘0’ 815 * by host software to indicate to the host controller that a transfer 816 * request slot is cleared. The host controller 817 * shall free up any resources associated to the request slot 818 * immediately, and shall set the associated bit in UTRLDBR to ‘0’. The 819 * host software indicates no change to request slots by setting the 820 * associated bits in this field to ‘1’. Bits in this field shall only 821 * be set ‘1’ or ‘0’ by host software when UTRLRSR is set to ‘1’." 822 */ 823 ufshcd_writel(hba, ~mask, REG_UTP_TRANSFER_REQ_LIST_CLEAR); 824 } 825 826 /** 827 * ufshcd_utmrl_clear - Clear a bit in UTMRLCLR register 828 * @hba: per adapter instance 829 * @pos: position of the bit to be cleared 830 */ 831 static inline void ufshcd_utmrl_clear(struct ufs_hba *hba, u32 pos) 832 { 833 if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR) 834 ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR); 835 else 836 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR); 837 } 838 839 /** 840 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY 841 * @reg: Register value of host controller status 842 * 843 * Return: 0 on success; a positive value if failed. 844 */ 845 static inline int ufshcd_get_lists_status(u32 reg) 846 { 847 return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY); 848 } 849 850 /** 851 * ufshcd_get_uic_cmd_result - Get the UIC command result 852 * @hba: Pointer to adapter instance 853 * 854 * This function gets the result of UIC command completion 855 * 856 * Return: 0 on success; non-zero value on error. 857 */ 858 static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba) 859 { 860 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) & 861 MASK_UIC_COMMAND_RESULT; 862 } 863 864 /** 865 * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command 866 * @hba: Pointer to adapter instance 867 * 868 * This function gets UIC command argument3 869 * 870 * Return: 0 on success; non-zero value on error. 871 */ 872 static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba) 873 { 874 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3); 875 } 876 877 /** 878 * ufshcd_get_req_rsp - returns the TR response transaction type 879 * @ucd_rsp_ptr: pointer to response UPIU 880 * 881 * Return: UPIU type. 882 */ 883 static inline enum upiu_response_transaction 884 ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr) 885 { 886 return ucd_rsp_ptr->header.transaction_code; 887 } 888 889 /** 890 * ufshcd_is_exception_event - Check if the device raised an exception event 891 * @ucd_rsp_ptr: pointer to response UPIU 892 * 893 * The function checks if the device raised an exception event indicated in 894 * the Device Information field of response UPIU. 895 * 896 * Return: true if exception is raised, false otherwise. 897 */ 898 static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr) 899 { 900 return ucd_rsp_ptr->header.device_information & 1; 901 } 902 903 /** 904 * ufshcd_reset_intr_aggr - Reset interrupt aggregation values. 905 * @hba: per adapter instance 906 */ 907 static inline void 908 ufshcd_reset_intr_aggr(struct ufs_hba *hba) 909 { 910 ufshcd_writel(hba, INT_AGGR_ENABLE | 911 INT_AGGR_COUNTER_AND_TIMER_RESET, 912 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL); 913 } 914 915 /** 916 * ufshcd_config_intr_aggr - Configure interrupt aggregation values. 917 * @hba: per adapter instance 918 * @cnt: Interrupt aggregation counter threshold 919 * @tmout: Interrupt aggregation timeout value 920 */ 921 static inline void 922 ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout) 923 { 924 ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE | 925 INT_AGGR_COUNTER_THLD_VAL(cnt) | 926 INT_AGGR_TIMEOUT_VAL(tmout), 927 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL); 928 } 929 930 /** 931 * ufshcd_disable_intr_aggr - Disables interrupt aggregation. 932 * @hba: per adapter instance 933 */ 934 static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba) 935 { 936 ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL); 937 } 938 939 /** 940 * ufshcd_enable_run_stop_reg - Enable run-stop registers, 941 * When run-stop registers are set to 1, it indicates the 942 * host controller that it can process the requests 943 * @hba: per adapter instance 944 */ 945 static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba) 946 { 947 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT, 948 REG_UTP_TASK_REQ_LIST_RUN_STOP); 949 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT, 950 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP); 951 } 952 953 /** 954 * ufshcd_hba_start - Start controller initialization sequence 955 * @hba: per adapter instance 956 */ 957 static inline void ufshcd_hba_start(struct ufs_hba *hba) 958 { 959 u32 val = CONTROLLER_ENABLE; 960 961 if (ufshcd_crypto_enable(hba)) 962 val |= CRYPTO_GENERAL_ENABLE; 963 964 ufshcd_writel(hba, val, REG_CONTROLLER_ENABLE); 965 } 966 967 /** 968 * ufshcd_is_hba_active - Get controller state 969 * @hba: per adapter instance 970 * 971 * Return: true if and only if the controller is active. 972 */ 973 bool ufshcd_is_hba_active(struct ufs_hba *hba) 974 { 975 return ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE; 976 } 977 EXPORT_SYMBOL_GPL(ufshcd_is_hba_active); 978 979 u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba) 980 { 981 /* HCI version 1.0 and 1.1 supports UniPro 1.41 */ 982 if (hba->ufs_version <= ufshci_version(1, 1)) 983 return UFS_UNIPRO_VER_1_41; 984 else 985 return UFS_UNIPRO_VER_1_6; 986 } 987 EXPORT_SYMBOL(ufshcd_get_local_unipro_ver); 988 989 static bool ufshcd_is_unipro_pa_params_tuning_req(struct ufs_hba *hba) 990 { 991 /* 992 * If both host and device support UniPro ver1.6 or later, PA layer 993 * parameters tuning happens during link startup itself. 994 * 995 * We can manually tune PA layer parameters if either host or device 996 * doesn't support UniPro ver 1.6 or later. But to keep manual tuning 997 * logic simple, we will only do manual tuning if local unipro version 998 * doesn't support ver1.6 or later. 999 */ 1000 return ufshcd_get_local_unipro_ver(hba) < UFS_UNIPRO_VER_1_6; 1001 } 1002 1003 /** 1004 * ufshcd_set_clk_freq - set UFS controller clock frequencies 1005 * @hba: per adapter instance 1006 * @scale_up: If True, set max possible frequency othewise set low frequency 1007 * 1008 * Return: 0 if successful; < 0 upon failure. 1009 */ 1010 static int ufshcd_set_clk_freq(struct ufs_hba *hba, bool scale_up) 1011 { 1012 int ret = 0; 1013 struct ufs_clk_info *clki; 1014 struct list_head *head = &hba->clk_list_head; 1015 1016 if (list_empty(head)) 1017 goto out; 1018 1019 list_for_each_entry(clki, head, list) { 1020 if (!IS_ERR_OR_NULL(clki->clk)) { 1021 if (scale_up && clki->max_freq) { 1022 if (clki->curr_freq == clki->max_freq) 1023 continue; 1024 1025 ret = clk_set_rate(clki->clk, clki->max_freq); 1026 if (ret) { 1027 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n", 1028 __func__, clki->name, 1029 clki->max_freq, ret); 1030 break; 1031 } 1032 trace_ufshcd_clk_scaling(dev_name(hba->dev), 1033 "scaled up", clki->name, 1034 clki->curr_freq, 1035 clki->max_freq); 1036 1037 clki->curr_freq = clki->max_freq; 1038 1039 } else if (!scale_up && clki->min_freq) { 1040 if (clki->curr_freq == clki->min_freq) 1041 continue; 1042 1043 ret = clk_set_rate(clki->clk, clki->min_freq); 1044 if (ret) { 1045 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n", 1046 __func__, clki->name, 1047 clki->min_freq, ret); 1048 break; 1049 } 1050 trace_ufshcd_clk_scaling(dev_name(hba->dev), 1051 "scaled down", clki->name, 1052 clki->curr_freq, 1053 clki->min_freq); 1054 clki->curr_freq = clki->min_freq; 1055 } 1056 } 1057 dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__, 1058 clki->name, clk_get_rate(clki->clk)); 1059 } 1060 1061 out: 1062 return ret; 1063 } 1064 1065 /** 1066 * ufshcd_scale_clks - scale up or scale down UFS controller clocks 1067 * @hba: per adapter instance 1068 * @scale_up: True if scaling up and false if scaling down 1069 * 1070 * Return: 0 if successful; < 0 upon failure. 1071 */ 1072 static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up) 1073 { 1074 int ret = 0; 1075 ktime_t start = ktime_get(); 1076 1077 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE); 1078 if (ret) 1079 goto out; 1080 1081 ret = ufshcd_set_clk_freq(hba, scale_up); 1082 if (ret) 1083 goto out; 1084 1085 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE); 1086 if (ret) 1087 ufshcd_set_clk_freq(hba, !scale_up); 1088 1089 out: 1090 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev), 1091 (scale_up ? "up" : "down"), 1092 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 1093 return ret; 1094 } 1095 1096 /** 1097 * ufshcd_is_devfreq_scaling_required - check if scaling is required or not 1098 * @hba: per adapter instance 1099 * @scale_up: True if scaling up and false if scaling down 1100 * 1101 * Return: true if scaling is required, false otherwise. 1102 */ 1103 static bool ufshcd_is_devfreq_scaling_required(struct ufs_hba *hba, 1104 bool scale_up) 1105 { 1106 struct ufs_clk_info *clki; 1107 struct list_head *head = &hba->clk_list_head; 1108 1109 if (list_empty(head)) 1110 return false; 1111 1112 list_for_each_entry(clki, head, list) { 1113 if (!IS_ERR_OR_NULL(clki->clk)) { 1114 if (scale_up && clki->max_freq) { 1115 if (clki->curr_freq == clki->max_freq) 1116 continue; 1117 return true; 1118 } else if (!scale_up && clki->min_freq) { 1119 if (clki->curr_freq == clki->min_freq) 1120 continue; 1121 return true; 1122 } 1123 } 1124 } 1125 1126 return false; 1127 } 1128 1129 /* 1130 * Determine the number of pending commands by counting the bits in the SCSI 1131 * device budget maps. This approach has been selected because a bit is set in 1132 * the budget map before scsi_host_queue_ready() checks the host_self_blocked 1133 * flag. The host_self_blocked flag can be modified by calling 1134 * scsi_block_requests() or scsi_unblock_requests(). 1135 */ 1136 static u32 ufshcd_pending_cmds(struct ufs_hba *hba) 1137 { 1138 const struct scsi_device *sdev; 1139 u32 pending = 0; 1140 1141 lockdep_assert_held(hba->host->host_lock); 1142 __shost_for_each_device(sdev, hba->host) 1143 pending += sbitmap_weight(&sdev->budget_map); 1144 1145 return pending; 1146 } 1147 1148 /* 1149 * Wait until all pending SCSI commands and TMFs have finished or the timeout 1150 * has expired. 1151 * 1152 * Return: 0 upon success; -EBUSY upon timeout. 1153 */ 1154 static int ufshcd_wait_for_doorbell_clr(struct ufs_hba *hba, 1155 u64 wait_timeout_us) 1156 { 1157 unsigned long flags; 1158 int ret = 0; 1159 u32 tm_doorbell; 1160 u32 tr_pending; 1161 bool timeout = false, do_last_check = false; 1162 ktime_t start; 1163 1164 ufshcd_hold(hba); 1165 spin_lock_irqsave(hba->host->host_lock, flags); 1166 /* 1167 * Wait for all the outstanding tasks/transfer requests. 1168 * Verify by checking the doorbell registers are clear. 1169 */ 1170 start = ktime_get(); 1171 do { 1172 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) { 1173 ret = -EBUSY; 1174 goto out; 1175 } 1176 1177 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL); 1178 tr_pending = ufshcd_pending_cmds(hba); 1179 if (!tm_doorbell && !tr_pending) { 1180 timeout = false; 1181 break; 1182 } else if (do_last_check) { 1183 break; 1184 } 1185 1186 spin_unlock_irqrestore(hba->host->host_lock, flags); 1187 io_schedule_timeout(msecs_to_jiffies(20)); 1188 if (ktime_to_us(ktime_sub(ktime_get(), start)) > 1189 wait_timeout_us) { 1190 timeout = true; 1191 /* 1192 * We might have scheduled out for long time so make 1193 * sure to check if doorbells are cleared by this time 1194 * or not. 1195 */ 1196 do_last_check = true; 1197 } 1198 spin_lock_irqsave(hba->host->host_lock, flags); 1199 } while (tm_doorbell || tr_pending); 1200 1201 if (timeout) { 1202 dev_err(hba->dev, 1203 "%s: timedout waiting for doorbell to clear (tm=0x%x, tr=0x%x)\n", 1204 __func__, tm_doorbell, tr_pending); 1205 ret = -EBUSY; 1206 } 1207 out: 1208 spin_unlock_irqrestore(hba->host->host_lock, flags); 1209 ufshcd_release(hba); 1210 return ret; 1211 } 1212 1213 /** 1214 * ufshcd_scale_gear - scale up/down UFS gear 1215 * @hba: per adapter instance 1216 * @scale_up: True for scaling up gear and false for scaling down 1217 * 1218 * Return: 0 for success; -EBUSY if scaling can't happen at this time; 1219 * non-zero for any other errors. 1220 */ 1221 static int ufshcd_scale_gear(struct ufs_hba *hba, bool scale_up) 1222 { 1223 int ret = 0; 1224 struct ufs_pa_layer_attr new_pwr_info; 1225 1226 if (scale_up) { 1227 memcpy(&new_pwr_info, &hba->clk_scaling.saved_pwr_info, 1228 sizeof(struct ufs_pa_layer_attr)); 1229 } else { 1230 memcpy(&new_pwr_info, &hba->pwr_info, 1231 sizeof(struct ufs_pa_layer_attr)); 1232 1233 if (hba->pwr_info.gear_tx > hba->clk_scaling.min_gear || 1234 hba->pwr_info.gear_rx > hba->clk_scaling.min_gear) { 1235 /* save the current power mode */ 1236 memcpy(&hba->clk_scaling.saved_pwr_info, 1237 &hba->pwr_info, 1238 sizeof(struct ufs_pa_layer_attr)); 1239 1240 /* scale down gear */ 1241 new_pwr_info.gear_tx = hba->clk_scaling.min_gear; 1242 new_pwr_info.gear_rx = hba->clk_scaling.min_gear; 1243 } 1244 } 1245 1246 /* check if the power mode needs to be changed or not? */ 1247 ret = ufshcd_config_pwr_mode(hba, &new_pwr_info); 1248 if (ret) 1249 dev_err(hba->dev, "%s: failed err %d, old gear: (tx %d rx %d), new gear: (tx %d rx %d)", 1250 __func__, ret, 1251 hba->pwr_info.gear_tx, hba->pwr_info.gear_rx, 1252 new_pwr_info.gear_tx, new_pwr_info.gear_rx); 1253 1254 return ret; 1255 } 1256 1257 /* 1258 * Wait until all pending SCSI commands and TMFs have finished or the timeout 1259 * has expired. 1260 * 1261 * Return: 0 upon success; -EBUSY upon timeout. 1262 */ 1263 static int ufshcd_clock_scaling_prepare(struct ufs_hba *hba, u64 timeout_us) 1264 { 1265 int ret = 0; 1266 /* 1267 * make sure that there are no outstanding requests when 1268 * clock scaling is in progress 1269 */ 1270 ufshcd_scsi_block_requests(hba); 1271 mutex_lock(&hba->wb_mutex); 1272 down_write(&hba->clk_scaling_lock); 1273 1274 if (!hba->clk_scaling.is_allowed || 1275 ufshcd_wait_for_doorbell_clr(hba, timeout_us)) { 1276 ret = -EBUSY; 1277 up_write(&hba->clk_scaling_lock); 1278 mutex_unlock(&hba->wb_mutex); 1279 ufshcd_scsi_unblock_requests(hba); 1280 goto out; 1281 } 1282 1283 /* let's not get into low power until clock scaling is completed */ 1284 ufshcd_hold(hba); 1285 1286 out: 1287 return ret; 1288 } 1289 1290 static void ufshcd_clock_scaling_unprepare(struct ufs_hba *hba, int err, bool scale_up) 1291 { 1292 up_write(&hba->clk_scaling_lock); 1293 1294 /* Enable Write Booster if we have scaled up else disable it */ 1295 if (ufshcd_enable_wb_if_scaling_up(hba) && !err) 1296 ufshcd_wb_toggle(hba, scale_up); 1297 1298 mutex_unlock(&hba->wb_mutex); 1299 1300 ufshcd_scsi_unblock_requests(hba); 1301 ufshcd_release(hba); 1302 } 1303 1304 /** 1305 * ufshcd_devfreq_scale - scale up/down UFS clocks and gear 1306 * @hba: per adapter instance 1307 * @scale_up: True for scaling up and false for scalin down 1308 * 1309 * Return: 0 for success; -EBUSY if scaling can't happen at this time; non-zero 1310 * for any other errors. 1311 */ 1312 static int ufshcd_devfreq_scale(struct ufs_hba *hba, bool scale_up) 1313 { 1314 int ret = 0; 1315 1316 ret = ufshcd_clock_scaling_prepare(hba, 1 * USEC_PER_SEC); 1317 if (ret) 1318 return ret; 1319 1320 /* scale down the gear before scaling down clocks */ 1321 if (!scale_up) { 1322 ret = ufshcd_scale_gear(hba, false); 1323 if (ret) 1324 goto out_unprepare; 1325 } 1326 1327 ret = ufshcd_scale_clks(hba, scale_up); 1328 if (ret) { 1329 if (!scale_up) 1330 ufshcd_scale_gear(hba, true); 1331 goto out_unprepare; 1332 } 1333 1334 /* scale up the gear after scaling up clocks */ 1335 if (scale_up) { 1336 ret = ufshcd_scale_gear(hba, true); 1337 if (ret) { 1338 ufshcd_scale_clks(hba, false); 1339 goto out_unprepare; 1340 } 1341 } 1342 1343 out_unprepare: 1344 ufshcd_clock_scaling_unprepare(hba, ret, scale_up); 1345 return ret; 1346 } 1347 1348 static void ufshcd_clk_scaling_suspend_work(struct work_struct *work) 1349 { 1350 struct ufs_hba *hba = container_of(work, struct ufs_hba, 1351 clk_scaling.suspend_work); 1352 unsigned long irq_flags; 1353 1354 spin_lock_irqsave(hba->host->host_lock, irq_flags); 1355 if (hba->clk_scaling.active_reqs || hba->clk_scaling.is_suspended) { 1356 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1357 return; 1358 } 1359 hba->clk_scaling.is_suspended = true; 1360 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1361 1362 __ufshcd_suspend_clkscaling(hba); 1363 } 1364 1365 static void ufshcd_clk_scaling_resume_work(struct work_struct *work) 1366 { 1367 struct ufs_hba *hba = container_of(work, struct ufs_hba, 1368 clk_scaling.resume_work); 1369 unsigned long irq_flags; 1370 1371 spin_lock_irqsave(hba->host->host_lock, irq_flags); 1372 if (!hba->clk_scaling.is_suspended) { 1373 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1374 return; 1375 } 1376 hba->clk_scaling.is_suspended = false; 1377 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1378 1379 devfreq_resume_device(hba->devfreq); 1380 } 1381 1382 static int ufshcd_devfreq_target(struct device *dev, 1383 unsigned long *freq, u32 flags) 1384 { 1385 int ret = 0; 1386 struct ufs_hba *hba = dev_get_drvdata(dev); 1387 ktime_t start; 1388 bool scale_up, sched_clk_scaling_suspend_work = false; 1389 struct list_head *clk_list = &hba->clk_list_head; 1390 struct ufs_clk_info *clki; 1391 unsigned long irq_flags; 1392 1393 if (!ufshcd_is_clkscaling_supported(hba)) 1394 return -EINVAL; 1395 1396 clki = list_first_entry(&hba->clk_list_head, struct ufs_clk_info, list); 1397 /* Override with the closest supported frequency */ 1398 *freq = (unsigned long) clk_round_rate(clki->clk, *freq); 1399 spin_lock_irqsave(hba->host->host_lock, irq_flags); 1400 if (ufshcd_eh_in_progress(hba)) { 1401 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1402 return 0; 1403 } 1404 1405 if (!hba->clk_scaling.active_reqs) 1406 sched_clk_scaling_suspend_work = true; 1407 1408 if (list_empty(clk_list)) { 1409 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1410 goto out; 1411 } 1412 1413 /* Decide based on the rounded-off frequency and update */ 1414 scale_up = *freq == clki->max_freq; 1415 if (!scale_up) 1416 *freq = clki->min_freq; 1417 /* Update the frequency */ 1418 if (!ufshcd_is_devfreq_scaling_required(hba, scale_up)) { 1419 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1420 ret = 0; 1421 goto out; /* no state change required */ 1422 } 1423 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1424 1425 start = ktime_get(); 1426 ret = ufshcd_devfreq_scale(hba, scale_up); 1427 1428 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev), 1429 (scale_up ? "up" : "down"), 1430 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 1431 1432 out: 1433 if (sched_clk_scaling_suspend_work) 1434 queue_work(hba->clk_scaling.workq, 1435 &hba->clk_scaling.suspend_work); 1436 1437 return ret; 1438 } 1439 1440 static int ufshcd_devfreq_get_dev_status(struct device *dev, 1441 struct devfreq_dev_status *stat) 1442 { 1443 struct ufs_hba *hba = dev_get_drvdata(dev); 1444 struct ufs_clk_scaling *scaling = &hba->clk_scaling; 1445 unsigned long flags; 1446 struct list_head *clk_list = &hba->clk_list_head; 1447 struct ufs_clk_info *clki; 1448 ktime_t curr_t; 1449 1450 if (!ufshcd_is_clkscaling_supported(hba)) 1451 return -EINVAL; 1452 1453 memset(stat, 0, sizeof(*stat)); 1454 1455 spin_lock_irqsave(hba->host->host_lock, flags); 1456 curr_t = ktime_get(); 1457 if (!scaling->window_start_t) 1458 goto start_window; 1459 1460 clki = list_first_entry(clk_list, struct ufs_clk_info, list); 1461 /* 1462 * If current frequency is 0, then the ondemand governor considers 1463 * there's no initial frequency set. And it always requests to set 1464 * to max. frequency. 1465 */ 1466 stat->current_frequency = clki->curr_freq; 1467 if (scaling->is_busy_started) 1468 scaling->tot_busy_t += ktime_us_delta(curr_t, 1469 scaling->busy_start_t); 1470 1471 stat->total_time = ktime_us_delta(curr_t, scaling->window_start_t); 1472 stat->busy_time = scaling->tot_busy_t; 1473 start_window: 1474 scaling->window_start_t = curr_t; 1475 scaling->tot_busy_t = 0; 1476 1477 if (scaling->active_reqs) { 1478 scaling->busy_start_t = curr_t; 1479 scaling->is_busy_started = true; 1480 } else { 1481 scaling->busy_start_t = 0; 1482 scaling->is_busy_started = false; 1483 } 1484 spin_unlock_irqrestore(hba->host->host_lock, flags); 1485 return 0; 1486 } 1487 1488 static int ufshcd_devfreq_init(struct ufs_hba *hba) 1489 { 1490 struct list_head *clk_list = &hba->clk_list_head; 1491 struct ufs_clk_info *clki; 1492 struct devfreq *devfreq; 1493 int ret; 1494 1495 /* Skip devfreq if we don't have any clocks in the list */ 1496 if (list_empty(clk_list)) 1497 return 0; 1498 1499 clki = list_first_entry(clk_list, struct ufs_clk_info, list); 1500 dev_pm_opp_add(hba->dev, clki->min_freq, 0); 1501 dev_pm_opp_add(hba->dev, clki->max_freq, 0); 1502 1503 ufshcd_vops_config_scaling_param(hba, &hba->vps->devfreq_profile, 1504 &hba->vps->ondemand_data); 1505 devfreq = devfreq_add_device(hba->dev, 1506 &hba->vps->devfreq_profile, 1507 DEVFREQ_GOV_SIMPLE_ONDEMAND, 1508 &hba->vps->ondemand_data); 1509 if (IS_ERR(devfreq)) { 1510 ret = PTR_ERR(devfreq); 1511 dev_err(hba->dev, "Unable to register with devfreq %d\n", ret); 1512 1513 dev_pm_opp_remove(hba->dev, clki->min_freq); 1514 dev_pm_opp_remove(hba->dev, clki->max_freq); 1515 return ret; 1516 } 1517 1518 hba->devfreq = devfreq; 1519 1520 return 0; 1521 } 1522 1523 static void ufshcd_devfreq_remove(struct ufs_hba *hba) 1524 { 1525 struct list_head *clk_list = &hba->clk_list_head; 1526 struct ufs_clk_info *clki; 1527 1528 if (!hba->devfreq) 1529 return; 1530 1531 devfreq_remove_device(hba->devfreq); 1532 hba->devfreq = NULL; 1533 1534 clki = list_first_entry(clk_list, struct ufs_clk_info, list); 1535 dev_pm_opp_remove(hba->dev, clki->min_freq); 1536 dev_pm_opp_remove(hba->dev, clki->max_freq); 1537 } 1538 1539 static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba) 1540 { 1541 unsigned long flags; 1542 1543 devfreq_suspend_device(hba->devfreq); 1544 spin_lock_irqsave(hba->host->host_lock, flags); 1545 hba->clk_scaling.window_start_t = 0; 1546 spin_unlock_irqrestore(hba->host->host_lock, flags); 1547 } 1548 1549 static void ufshcd_suspend_clkscaling(struct ufs_hba *hba) 1550 { 1551 unsigned long flags; 1552 bool suspend = false; 1553 1554 cancel_work_sync(&hba->clk_scaling.suspend_work); 1555 cancel_work_sync(&hba->clk_scaling.resume_work); 1556 1557 spin_lock_irqsave(hba->host->host_lock, flags); 1558 if (!hba->clk_scaling.is_suspended) { 1559 suspend = true; 1560 hba->clk_scaling.is_suspended = true; 1561 } 1562 spin_unlock_irqrestore(hba->host->host_lock, flags); 1563 1564 if (suspend) 1565 __ufshcd_suspend_clkscaling(hba); 1566 } 1567 1568 static void ufshcd_resume_clkscaling(struct ufs_hba *hba) 1569 { 1570 unsigned long flags; 1571 bool resume = false; 1572 1573 spin_lock_irqsave(hba->host->host_lock, flags); 1574 if (hba->clk_scaling.is_suspended) { 1575 resume = true; 1576 hba->clk_scaling.is_suspended = false; 1577 } 1578 spin_unlock_irqrestore(hba->host->host_lock, flags); 1579 1580 if (resume) 1581 devfreq_resume_device(hba->devfreq); 1582 } 1583 1584 static ssize_t ufshcd_clkscale_enable_show(struct device *dev, 1585 struct device_attribute *attr, char *buf) 1586 { 1587 struct ufs_hba *hba = dev_get_drvdata(dev); 1588 1589 return sysfs_emit(buf, "%d\n", hba->clk_scaling.is_enabled); 1590 } 1591 1592 static ssize_t ufshcd_clkscale_enable_store(struct device *dev, 1593 struct device_attribute *attr, const char *buf, size_t count) 1594 { 1595 struct ufs_hba *hba = dev_get_drvdata(dev); 1596 u32 value; 1597 int err = 0; 1598 1599 if (kstrtou32(buf, 0, &value)) 1600 return -EINVAL; 1601 1602 down(&hba->host_sem); 1603 if (!ufshcd_is_user_access_allowed(hba)) { 1604 err = -EBUSY; 1605 goto out; 1606 } 1607 1608 value = !!value; 1609 if (value == hba->clk_scaling.is_enabled) 1610 goto out; 1611 1612 ufshcd_rpm_get_sync(hba); 1613 ufshcd_hold(hba); 1614 1615 hba->clk_scaling.is_enabled = value; 1616 1617 if (value) { 1618 ufshcd_resume_clkscaling(hba); 1619 } else { 1620 ufshcd_suspend_clkscaling(hba); 1621 err = ufshcd_devfreq_scale(hba, true); 1622 if (err) 1623 dev_err(hba->dev, "%s: failed to scale clocks up %d\n", 1624 __func__, err); 1625 } 1626 1627 ufshcd_release(hba); 1628 ufshcd_rpm_put_sync(hba); 1629 out: 1630 up(&hba->host_sem); 1631 return err ? err : count; 1632 } 1633 1634 static void ufshcd_init_clk_scaling_sysfs(struct ufs_hba *hba) 1635 { 1636 hba->clk_scaling.enable_attr.show = ufshcd_clkscale_enable_show; 1637 hba->clk_scaling.enable_attr.store = ufshcd_clkscale_enable_store; 1638 sysfs_attr_init(&hba->clk_scaling.enable_attr.attr); 1639 hba->clk_scaling.enable_attr.attr.name = "clkscale_enable"; 1640 hba->clk_scaling.enable_attr.attr.mode = 0644; 1641 if (device_create_file(hba->dev, &hba->clk_scaling.enable_attr)) 1642 dev_err(hba->dev, "Failed to create sysfs for clkscale_enable\n"); 1643 } 1644 1645 static void ufshcd_remove_clk_scaling_sysfs(struct ufs_hba *hba) 1646 { 1647 if (hba->clk_scaling.enable_attr.attr.name) 1648 device_remove_file(hba->dev, &hba->clk_scaling.enable_attr); 1649 } 1650 1651 static void ufshcd_init_clk_scaling(struct ufs_hba *hba) 1652 { 1653 char wq_name[sizeof("ufs_clkscaling_00")]; 1654 1655 if (!ufshcd_is_clkscaling_supported(hba)) 1656 return; 1657 1658 if (!hba->clk_scaling.min_gear) 1659 hba->clk_scaling.min_gear = UFS_HS_G1; 1660 1661 INIT_WORK(&hba->clk_scaling.suspend_work, 1662 ufshcd_clk_scaling_suspend_work); 1663 INIT_WORK(&hba->clk_scaling.resume_work, 1664 ufshcd_clk_scaling_resume_work); 1665 1666 snprintf(wq_name, sizeof(wq_name), "ufs_clkscaling_%d", 1667 hba->host->host_no); 1668 hba->clk_scaling.workq = create_singlethread_workqueue(wq_name); 1669 1670 hba->clk_scaling.is_initialized = true; 1671 } 1672 1673 static void ufshcd_exit_clk_scaling(struct ufs_hba *hba) 1674 { 1675 if (!hba->clk_scaling.is_initialized) 1676 return; 1677 1678 ufshcd_remove_clk_scaling_sysfs(hba); 1679 destroy_workqueue(hba->clk_scaling.workq); 1680 ufshcd_devfreq_remove(hba); 1681 hba->clk_scaling.is_initialized = false; 1682 } 1683 1684 static void ufshcd_ungate_work(struct work_struct *work) 1685 { 1686 int ret; 1687 unsigned long flags; 1688 struct ufs_hba *hba = container_of(work, struct ufs_hba, 1689 clk_gating.ungate_work); 1690 1691 cancel_delayed_work_sync(&hba->clk_gating.gate_work); 1692 1693 spin_lock_irqsave(hba->host->host_lock, flags); 1694 if (hba->clk_gating.state == CLKS_ON) { 1695 spin_unlock_irqrestore(hba->host->host_lock, flags); 1696 return; 1697 } 1698 1699 spin_unlock_irqrestore(hba->host->host_lock, flags); 1700 ufshcd_hba_vreg_set_hpm(hba); 1701 ufshcd_setup_clocks(hba, true); 1702 1703 ufshcd_enable_irq(hba); 1704 1705 /* Exit from hibern8 */ 1706 if (ufshcd_can_hibern8_during_gating(hba)) { 1707 /* Prevent gating in this path */ 1708 hba->clk_gating.is_suspended = true; 1709 if (ufshcd_is_link_hibern8(hba)) { 1710 ret = ufshcd_uic_hibern8_exit(hba); 1711 if (ret) 1712 dev_err(hba->dev, "%s: hibern8 exit failed %d\n", 1713 __func__, ret); 1714 else 1715 ufshcd_set_link_active(hba); 1716 } 1717 hba->clk_gating.is_suspended = false; 1718 } 1719 } 1720 1721 /** 1722 * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release. 1723 * Also, exit from hibern8 mode and set the link as active. 1724 * @hba: per adapter instance 1725 */ 1726 void ufshcd_hold(struct ufs_hba *hba) 1727 { 1728 bool flush_result; 1729 unsigned long flags; 1730 1731 if (!ufshcd_is_clkgating_allowed(hba) || 1732 !hba->clk_gating.is_initialized) 1733 return; 1734 spin_lock_irqsave(hba->host->host_lock, flags); 1735 hba->clk_gating.active_reqs++; 1736 1737 start: 1738 switch (hba->clk_gating.state) { 1739 case CLKS_ON: 1740 /* 1741 * Wait for the ungate work to complete if in progress. 1742 * Though the clocks may be in ON state, the link could 1743 * still be in hibner8 state if hibern8 is allowed 1744 * during clock gating. 1745 * Make sure we exit hibern8 state also in addition to 1746 * clocks being ON. 1747 */ 1748 if (ufshcd_can_hibern8_during_gating(hba) && 1749 ufshcd_is_link_hibern8(hba)) { 1750 spin_unlock_irqrestore(hba->host->host_lock, flags); 1751 flush_result = flush_work(&hba->clk_gating.ungate_work); 1752 if (hba->clk_gating.is_suspended && !flush_result) 1753 return; 1754 spin_lock_irqsave(hba->host->host_lock, flags); 1755 goto start; 1756 } 1757 break; 1758 case REQ_CLKS_OFF: 1759 if (cancel_delayed_work(&hba->clk_gating.gate_work)) { 1760 hba->clk_gating.state = CLKS_ON; 1761 trace_ufshcd_clk_gating(dev_name(hba->dev), 1762 hba->clk_gating.state); 1763 break; 1764 } 1765 /* 1766 * If we are here, it means gating work is either done or 1767 * currently running. Hence, fall through to cancel gating 1768 * work and to enable clocks. 1769 */ 1770 fallthrough; 1771 case CLKS_OFF: 1772 hba->clk_gating.state = REQ_CLKS_ON; 1773 trace_ufshcd_clk_gating(dev_name(hba->dev), 1774 hba->clk_gating.state); 1775 queue_work(hba->clk_gating.clk_gating_workq, 1776 &hba->clk_gating.ungate_work); 1777 /* 1778 * fall through to check if we should wait for this 1779 * work to be done or not. 1780 */ 1781 fallthrough; 1782 case REQ_CLKS_ON: 1783 spin_unlock_irqrestore(hba->host->host_lock, flags); 1784 flush_work(&hba->clk_gating.ungate_work); 1785 /* Make sure state is CLKS_ON before returning */ 1786 spin_lock_irqsave(hba->host->host_lock, flags); 1787 goto start; 1788 default: 1789 dev_err(hba->dev, "%s: clk gating is in invalid state %d\n", 1790 __func__, hba->clk_gating.state); 1791 break; 1792 } 1793 spin_unlock_irqrestore(hba->host->host_lock, flags); 1794 } 1795 EXPORT_SYMBOL_GPL(ufshcd_hold); 1796 1797 static void ufshcd_gate_work(struct work_struct *work) 1798 { 1799 struct ufs_hba *hba = container_of(work, struct ufs_hba, 1800 clk_gating.gate_work.work); 1801 unsigned long flags; 1802 int ret; 1803 1804 spin_lock_irqsave(hba->host->host_lock, flags); 1805 /* 1806 * In case you are here to cancel this work the gating state 1807 * would be marked as REQ_CLKS_ON. In this case save time by 1808 * skipping the gating work and exit after changing the clock 1809 * state to CLKS_ON. 1810 */ 1811 if (hba->clk_gating.is_suspended || 1812 (hba->clk_gating.state != REQ_CLKS_OFF)) { 1813 hba->clk_gating.state = CLKS_ON; 1814 trace_ufshcd_clk_gating(dev_name(hba->dev), 1815 hba->clk_gating.state); 1816 goto rel_lock; 1817 } 1818 1819 if (hba->clk_gating.active_reqs 1820 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL 1821 || hba->outstanding_reqs || hba->outstanding_tasks 1822 || hba->active_uic_cmd || hba->uic_async_done) 1823 goto rel_lock; 1824 1825 spin_unlock_irqrestore(hba->host->host_lock, flags); 1826 1827 /* put the link into hibern8 mode before turning off clocks */ 1828 if (ufshcd_can_hibern8_during_gating(hba)) { 1829 ret = ufshcd_uic_hibern8_enter(hba); 1830 if (ret) { 1831 hba->clk_gating.state = CLKS_ON; 1832 dev_err(hba->dev, "%s: hibern8 enter failed %d\n", 1833 __func__, ret); 1834 trace_ufshcd_clk_gating(dev_name(hba->dev), 1835 hba->clk_gating.state); 1836 goto out; 1837 } 1838 ufshcd_set_link_hibern8(hba); 1839 } 1840 1841 ufshcd_disable_irq(hba); 1842 1843 ufshcd_setup_clocks(hba, false); 1844 1845 /* Put the host controller in low power mode if possible */ 1846 ufshcd_hba_vreg_set_lpm(hba); 1847 /* 1848 * In case you are here to cancel this work the gating state 1849 * would be marked as REQ_CLKS_ON. In this case keep the state 1850 * as REQ_CLKS_ON which would anyway imply that clocks are off 1851 * and a request to turn them on is pending. By doing this way, 1852 * we keep the state machine in tact and this would ultimately 1853 * prevent from doing cancel work multiple times when there are 1854 * new requests arriving before the current cancel work is done. 1855 */ 1856 spin_lock_irqsave(hba->host->host_lock, flags); 1857 if (hba->clk_gating.state == REQ_CLKS_OFF) { 1858 hba->clk_gating.state = CLKS_OFF; 1859 trace_ufshcd_clk_gating(dev_name(hba->dev), 1860 hba->clk_gating.state); 1861 } 1862 rel_lock: 1863 spin_unlock_irqrestore(hba->host->host_lock, flags); 1864 out: 1865 return; 1866 } 1867 1868 /* host lock must be held before calling this variant */ 1869 static void __ufshcd_release(struct ufs_hba *hba) 1870 { 1871 if (!ufshcd_is_clkgating_allowed(hba)) 1872 return; 1873 1874 hba->clk_gating.active_reqs--; 1875 1876 if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended || 1877 hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL || 1878 hba->outstanding_tasks || !hba->clk_gating.is_initialized || 1879 hba->active_uic_cmd || hba->uic_async_done || 1880 hba->clk_gating.state == CLKS_OFF) 1881 return; 1882 1883 hba->clk_gating.state = REQ_CLKS_OFF; 1884 trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state); 1885 queue_delayed_work(hba->clk_gating.clk_gating_workq, 1886 &hba->clk_gating.gate_work, 1887 msecs_to_jiffies(hba->clk_gating.delay_ms)); 1888 } 1889 1890 void ufshcd_release(struct ufs_hba *hba) 1891 { 1892 unsigned long flags; 1893 1894 spin_lock_irqsave(hba->host->host_lock, flags); 1895 __ufshcd_release(hba); 1896 spin_unlock_irqrestore(hba->host->host_lock, flags); 1897 } 1898 EXPORT_SYMBOL_GPL(ufshcd_release); 1899 1900 static ssize_t ufshcd_clkgate_delay_show(struct device *dev, 1901 struct device_attribute *attr, char *buf) 1902 { 1903 struct ufs_hba *hba = dev_get_drvdata(dev); 1904 1905 return sysfs_emit(buf, "%lu\n", hba->clk_gating.delay_ms); 1906 } 1907 1908 void ufshcd_clkgate_delay_set(struct device *dev, unsigned long value) 1909 { 1910 struct ufs_hba *hba = dev_get_drvdata(dev); 1911 unsigned long flags; 1912 1913 spin_lock_irqsave(hba->host->host_lock, flags); 1914 hba->clk_gating.delay_ms = value; 1915 spin_unlock_irqrestore(hba->host->host_lock, flags); 1916 } 1917 EXPORT_SYMBOL_GPL(ufshcd_clkgate_delay_set); 1918 1919 static ssize_t ufshcd_clkgate_delay_store(struct device *dev, 1920 struct device_attribute *attr, const char *buf, size_t count) 1921 { 1922 unsigned long value; 1923 1924 if (kstrtoul(buf, 0, &value)) 1925 return -EINVAL; 1926 1927 ufshcd_clkgate_delay_set(dev, value); 1928 return count; 1929 } 1930 1931 static ssize_t ufshcd_clkgate_enable_show(struct device *dev, 1932 struct device_attribute *attr, char *buf) 1933 { 1934 struct ufs_hba *hba = dev_get_drvdata(dev); 1935 1936 return sysfs_emit(buf, "%d\n", hba->clk_gating.is_enabled); 1937 } 1938 1939 static ssize_t ufshcd_clkgate_enable_store(struct device *dev, 1940 struct device_attribute *attr, const char *buf, size_t count) 1941 { 1942 struct ufs_hba *hba = dev_get_drvdata(dev); 1943 unsigned long flags; 1944 u32 value; 1945 1946 if (kstrtou32(buf, 0, &value)) 1947 return -EINVAL; 1948 1949 value = !!value; 1950 1951 spin_lock_irqsave(hba->host->host_lock, flags); 1952 if (value == hba->clk_gating.is_enabled) 1953 goto out; 1954 1955 if (value) 1956 __ufshcd_release(hba); 1957 else 1958 hba->clk_gating.active_reqs++; 1959 1960 hba->clk_gating.is_enabled = value; 1961 out: 1962 spin_unlock_irqrestore(hba->host->host_lock, flags); 1963 return count; 1964 } 1965 1966 static void ufshcd_init_clk_gating_sysfs(struct ufs_hba *hba) 1967 { 1968 hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show; 1969 hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store; 1970 sysfs_attr_init(&hba->clk_gating.delay_attr.attr); 1971 hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms"; 1972 hba->clk_gating.delay_attr.attr.mode = 0644; 1973 if (device_create_file(hba->dev, &hba->clk_gating.delay_attr)) 1974 dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n"); 1975 1976 hba->clk_gating.enable_attr.show = ufshcd_clkgate_enable_show; 1977 hba->clk_gating.enable_attr.store = ufshcd_clkgate_enable_store; 1978 sysfs_attr_init(&hba->clk_gating.enable_attr.attr); 1979 hba->clk_gating.enable_attr.attr.name = "clkgate_enable"; 1980 hba->clk_gating.enable_attr.attr.mode = 0644; 1981 if (device_create_file(hba->dev, &hba->clk_gating.enable_attr)) 1982 dev_err(hba->dev, "Failed to create sysfs for clkgate_enable\n"); 1983 } 1984 1985 static void ufshcd_remove_clk_gating_sysfs(struct ufs_hba *hba) 1986 { 1987 if (hba->clk_gating.delay_attr.attr.name) 1988 device_remove_file(hba->dev, &hba->clk_gating.delay_attr); 1989 if (hba->clk_gating.enable_attr.attr.name) 1990 device_remove_file(hba->dev, &hba->clk_gating.enable_attr); 1991 } 1992 1993 static void ufshcd_init_clk_gating(struct ufs_hba *hba) 1994 { 1995 char wq_name[sizeof("ufs_clk_gating_00")]; 1996 1997 if (!ufshcd_is_clkgating_allowed(hba)) 1998 return; 1999 2000 hba->clk_gating.state = CLKS_ON; 2001 2002 hba->clk_gating.delay_ms = 150; 2003 INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work); 2004 INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work); 2005 2006 snprintf(wq_name, ARRAY_SIZE(wq_name), "ufs_clk_gating_%d", 2007 hba->host->host_no); 2008 hba->clk_gating.clk_gating_workq = alloc_ordered_workqueue(wq_name, 2009 WQ_MEM_RECLAIM | WQ_HIGHPRI); 2010 2011 ufshcd_init_clk_gating_sysfs(hba); 2012 2013 hba->clk_gating.is_enabled = true; 2014 hba->clk_gating.is_initialized = true; 2015 } 2016 2017 static void ufshcd_exit_clk_gating(struct ufs_hba *hba) 2018 { 2019 if (!hba->clk_gating.is_initialized) 2020 return; 2021 2022 ufshcd_remove_clk_gating_sysfs(hba); 2023 2024 /* Ungate the clock if necessary. */ 2025 ufshcd_hold(hba); 2026 hba->clk_gating.is_initialized = false; 2027 ufshcd_release(hba); 2028 2029 destroy_workqueue(hba->clk_gating.clk_gating_workq); 2030 } 2031 2032 static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba) 2033 { 2034 bool queue_resume_work = false; 2035 ktime_t curr_t = ktime_get(); 2036 unsigned long flags; 2037 2038 if (!ufshcd_is_clkscaling_supported(hba)) 2039 return; 2040 2041 spin_lock_irqsave(hba->host->host_lock, flags); 2042 if (!hba->clk_scaling.active_reqs++) 2043 queue_resume_work = true; 2044 2045 if (!hba->clk_scaling.is_enabled || hba->pm_op_in_progress) { 2046 spin_unlock_irqrestore(hba->host->host_lock, flags); 2047 return; 2048 } 2049 2050 if (queue_resume_work) 2051 queue_work(hba->clk_scaling.workq, 2052 &hba->clk_scaling.resume_work); 2053 2054 if (!hba->clk_scaling.window_start_t) { 2055 hba->clk_scaling.window_start_t = curr_t; 2056 hba->clk_scaling.tot_busy_t = 0; 2057 hba->clk_scaling.is_busy_started = false; 2058 } 2059 2060 if (!hba->clk_scaling.is_busy_started) { 2061 hba->clk_scaling.busy_start_t = curr_t; 2062 hba->clk_scaling.is_busy_started = true; 2063 } 2064 spin_unlock_irqrestore(hba->host->host_lock, flags); 2065 } 2066 2067 static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba) 2068 { 2069 struct ufs_clk_scaling *scaling = &hba->clk_scaling; 2070 unsigned long flags; 2071 2072 if (!ufshcd_is_clkscaling_supported(hba)) 2073 return; 2074 2075 spin_lock_irqsave(hba->host->host_lock, flags); 2076 hba->clk_scaling.active_reqs--; 2077 if (!scaling->active_reqs && scaling->is_busy_started) { 2078 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(), 2079 scaling->busy_start_t)); 2080 scaling->busy_start_t = 0; 2081 scaling->is_busy_started = false; 2082 } 2083 spin_unlock_irqrestore(hba->host->host_lock, flags); 2084 } 2085 2086 static inline int ufshcd_monitor_opcode2dir(u8 opcode) 2087 { 2088 if (opcode == READ_6 || opcode == READ_10 || opcode == READ_16) 2089 return READ; 2090 else if (opcode == WRITE_6 || opcode == WRITE_10 || opcode == WRITE_16) 2091 return WRITE; 2092 else 2093 return -EINVAL; 2094 } 2095 2096 static inline bool ufshcd_should_inform_monitor(struct ufs_hba *hba, 2097 struct ufshcd_lrb *lrbp) 2098 { 2099 const struct ufs_hba_monitor *m = &hba->monitor; 2100 2101 return (m->enabled && lrbp && lrbp->cmd && 2102 (!m->chunk_size || m->chunk_size == lrbp->cmd->sdb.length) && 2103 ktime_before(hba->monitor.enabled_ts, lrbp->issue_time_stamp)); 2104 } 2105 2106 static void ufshcd_start_monitor(struct ufs_hba *hba, 2107 const struct ufshcd_lrb *lrbp) 2108 { 2109 int dir = ufshcd_monitor_opcode2dir(*lrbp->cmd->cmnd); 2110 unsigned long flags; 2111 2112 spin_lock_irqsave(hba->host->host_lock, flags); 2113 if (dir >= 0 && hba->monitor.nr_queued[dir]++ == 0) 2114 hba->monitor.busy_start_ts[dir] = ktime_get(); 2115 spin_unlock_irqrestore(hba->host->host_lock, flags); 2116 } 2117 2118 static void ufshcd_update_monitor(struct ufs_hba *hba, const struct ufshcd_lrb *lrbp) 2119 { 2120 int dir = ufshcd_monitor_opcode2dir(*lrbp->cmd->cmnd); 2121 unsigned long flags; 2122 2123 spin_lock_irqsave(hba->host->host_lock, flags); 2124 if (dir >= 0 && hba->monitor.nr_queued[dir] > 0) { 2125 const struct request *req = scsi_cmd_to_rq(lrbp->cmd); 2126 struct ufs_hba_monitor *m = &hba->monitor; 2127 ktime_t now, inc, lat; 2128 2129 now = lrbp->compl_time_stamp; 2130 inc = ktime_sub(now, m->busy_start_ts[dir]); 2131 m->total_busy[dir] = ktime_add(m->total_busy[dir], inc); 2132 m->nr_sec_rw[dir] += blk_rq_sectors(req); 2133 2134 /* Update latencies */ 2135 m->nr_req[dir]++; 2136 lat = ktime_sub(now, lrbp->issue_time_stamp); 2137 m->lat_sum[dir] += lat; 2138 if (m->lat_max[dir] < lat || !m->lat_max[dir]) 2139 m->lat_max[dir] = lat; 2140 if (m->lat_min[dir] > lat || !m->lat_min[dir]) 2141 m->lat_min[dir] = lat; 2142 2143 m->nr_queued[dir]--; 2144 /* Push forward the busy start of monitor */ 2145 m->busy_start_ts[dir] = now; 2146 } 2147 spin_unlock_irqrestore(hba->host->host_lock, flags); 2148 } 2149 2150 /** 2151 * ufshcd_send_command - Send SCSI or device management commands 2152 * @hba: per adapter instance 2153 * @task_tag: Task tag of the command 2154 * @hwq: pointer to hardware queue instance 2155 */ 2156 static inline 2157 void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag, 2158 struct ufs_hw_queue *hwq) 2159 { 2160 struct ufshcd_lrb *lrbp = &hba->lrb[task_tag]; 2161 unsigned long flags; 2162 2163 lrbp->issue_time_stamp = ktime_get(); 2164 lrbp->issue_time_stamp_local_clock = local_clock(); 2165 lrbp->compl_time_stamp = ktime_set(0, 0); 2166 lrbp->compl_time_stamp_local_clock = 0; 2167 ufshcd_add_command_trace(hba, task_tag, UFS_CMD_SEND); 2168 ufshcd_clk_scaling_start_busy(hba); 2169 if (unlikely(ufshcd_should_inform_monitor(hba, lrbp))) 2170 ufshcd_start_monitor(hba, lrbp); 2171 2172 if (is_mcq_enabled(hba)) { 2173 int utrd_size = sizeof(struct utp_transfer_req_desc); 2174 struct utp_transfer_req_desc *src = lrbp->utr_descriptor_ptr; 2175 struct utp_transfer_req_desc *dest; 2176 2177 spin_lock(&hwq->sq_lock); 2178 dest = hwq->sqe_base_addr + hwq->sq_tail_slot; 2179 memcpy(dest, src, utrd_size); 2180 ufshcd_inc_sq_tail(hwq); 2181 spin_unlock(&hwq->sq_lock); 2182 } else { 2183 spin_lock_irqsave(&hba->outstanding_lock, flags); 2184 if (hba->vops && hba->vops->setup_xfer_req) 2185 hba->vops->setup_xfer_req(hba, lrbp->task_tag, 2186 !!lrbp->cmd); 2187 __set_bit(lrbp->task_tag, &hba->outstanding_reqs); 2188 ufshcd_writel(hba, 1 << lrbp->task_tag, 2189 REG_UTP_TRANSFER_REQ_DOOR_BELL); 2190 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 2191 } 2192 } 2193 2194 /** 2195 * ufshcd_copy_sense_data - Copy sense data in case of check condition 2196 * @lrbp: pointer to local reference block 2197 */ 2198 static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp) 2199 { 2200 u8 *const sense_buffer = lrbp->cmd->sense_buffer; 2201 u16 resp_len; 2202 int len; 2203 2204 resp_len = be16_to_cpu(lrbp->ucd_rsp_ptr->header.data_segment_length); 2205 if (sense_buffer && resp_len) { 2206 int len_to_copy; 2207 2208 len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len); 2209 len_to_copy = min_t(int, UFS_SENSE_SIZE, len); 2210 2211 memcpy(sense_buffer, lrbp->ucd_rsp_ptr->sr.sense_data, 2212 len_to_copy); 2213 } 2214 } 2215 2216 /** 2217 * ufshcd_copy_query_response() - Copy the Query Response and the data 2218 * descriptor 2219 * @hba: per adapter instance 2220 * @lrbp: pointer to local reference block 2221 * 2222 * Return: 0 upon success; < 0 upon failure. 2223 */ 2224 static 2225 int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) 2226 { 2227 struct ufs_query_res *query_res = &hba->dev_cmd.query.response; 2228 2229 memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE); 2230 2231 /* Get the descriptor */ 2232 if (hba->dev_cmd.query.descriptor && 2233 lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) { 2234 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr + 2235 GENERAL_UPIU_REQUEST_SIZE; 2236 u16 resp_len; 2237 u16 buf_len; 2238 2239 /* data segment length */ 2240 resp_len = be16_to_cpu(lrbp->ucd_rsp_ptr->header 2241 .data_segment_length); 2242 buf_len = be16_to_cpu( 2243 hba->dev_cmd.query.request.upiu_req.length); 2244 if (likely(buf_len >= resp_len)) { 2245 memcpy(hba->dev_cmd.query.descriptor, descp, resp_len); 2246 } else { 2247 dev_warn(hba->dev, 2248 "%s: rsp size %d is bigger than buffer size %d", 2249 __func__, resp_len, buf_len); 2250 return -EINVAL; 2251 } 2252 } 2253 2254 return 0; 2255 } 2256 2257 /** 2258 * ufshcd_hba_capabilities - Read controller capabilities 2259 * @hba: per adapter instance 2260 * 2261 * Return: 0 on success, negative on error. 2262 */ 2263 static inline int ufshcd_hba_capabilities(struct ufs_hba *hba) 2264 { 2265 int err; 2266 2267 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES); 2268 if (hba->quirks & UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS) 2269 hba->capabilities &= ~MASK_64_ADDRESSING_SUPPORT; 2270 2271 /* nutrs and nutmrs are 0 based values */ 2272 hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1; 2273 hba->nutmrs = 2274 ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1; 2275 hba->reserved_slot = hba->nutrs - 1; 2276 2277 /* Read crypto capabilities */ 2278 err = ufshcd_hba_init_crypto_capabilities(hba); 2279 if (err) { 2280 dev_err(hba->dev, "crypto setup failed\n"); 2281 return err; 2282 } 2283 2284 hba->mcq_sup = FIELD_GET(MASK_MCQ_SUPPORT, hba->capabilities); 2285 if (!hba->mcq_sup) 2286 return 0; 2287 2288 hba->mcq_capabilities = ufshcd_readl(hba, REG_MCQCAP); 2289 hba->ext_iid_sup = FIELD_GET(MASK_EXT_IID_SUPPORT, 2290 hba->mcq_capabilities); 2291 2292 return 0; 2293 } 2294 2295 /** 2296 * ufshcd_ready_for_uic_cmd - Check if controller is ready 2297 * to accept UIC commands 2298 * @hba: per adapter instance 2299 * 2300 * Return: true on success, else false. 2301 */ 2302 static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba) 2303 { 2304 u32 val; 2305 int ret = read_poll_timeout(ufshcd_readl, val, val & UIC_COMMAND_READY, 2306 500, UIC_CMD_TIMEOUT * 1000, false, hba, 2307 REG_CONTROLLER_STATUS); 2308 return ret == 0 ? true : false; 2309 } 2310 2311 /** 2312 * ufshcd_get_upmcrs - Get the power mode change request status 2313 * @hba: Pointer to adapter instance 2314 * 2315 * This function gets the UPMCRS field of HCS register 2316 * 2317 * Return: value of UPMCRS field. 2318 */ 2319 static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba) 2320 { 2321 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7; 2322 } 2323 2324 /** 2325 * ufshcd_dispatch_uic_cmd - Dispatch an UIC command to the Unipro layer 2326 * @hba: per adapter instance 2327 * @uic_cmd: UIC command 2328 */ 2329 static inline void 2330 ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) 2331 { 2332 lockdep_assert_held(&hba->uic_cmd_mutex); 2333 2334 WARN_ON(hba->active_uic_cmd); 2335 2336 hba->active_uic_cmd = uic_cmd; 2337 2338 /* Write Args */ 2339 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1); 2340 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2); 2341 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3); 2342 2343 ufshcd_add_uic_command_trace(hba, uic_cmd, UFS_CMD_SEND); 2344 2345 /* Write UIC Cmd */ 2346 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK, 2347 REG_UIC_COMMAND); 2348 } 2349 2350 /** 2351 * ufshcd_wait_for_uic_cmd - Wait for completion of an UIC command 2352 * @hba: per adapter instance 2353 * @uic_cmd: UIC command 2354 * 2355 * Return: 0 only if success. 2356 */ 2357 static int 2358 ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) 2359 { 2360 int ret; 2361 unsigned long flags; 2362 2363 lockdep_assert_held(&hba->uic_cmd_mutex); 2364 2365 if (wait_for_completion_timeout(&uic_cmd->done, 2366 msecs_to_jiffies(UIC_CMD_TIMEOUT))) { 2367 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT; 2368 } else { 2369 ret = -ETIMEDOUT; 2370 dev_err(hba->dev, 2371 "uic cmd 0x%x with arg3 0x%x completion timeout\n", 2372 uic_cmd->command, uic_cmd->argument3); 2373 2374 if (!uic_cmd->cmd_active) { 2375 dev_err(hba->dev, "%s: UIC cmd has been completed, return the result\n", 2376 __func__); 2377 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT; 2378 } 2379 } 2380 2381 spin_lock_irqsave(hba->host->host_lock, flags); 2382 hba->active_uic_cmd = NULL; 2383 spin_unlock_irqrestore(hba->host->host_lock, flags); 2384 2385 return ret; 2386 } 2387 2388 /** 2389 * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result 2390 * @hba: per adapter instance 2391 * @uic_cmd: UIC command 2392 * @completion: initialize the completion only if this is set to true 2393 * 2394 * Return: 0 only if success. 2395 */ 2396 static int 2397 __ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd, 2398 bool completion) 2399 { 2400 lockdep_assert_held(&hba->uic_cmd_mutex); 2401 2402 if (!ufshcd_ready_for_uic_cmd(hba)) { 2403 dev_err(hba->dev, 2404 "Controller not ready to accept UIC commands\n"); 2405 return -EIO; 2406 } 2407 2408 if (completion) 2409 init_completion(&uic_cmd->done); 2410 2411 uic_cmd->cmd_active = 1; 2412 ufshcd_dispatch_uic_cmd(hba, uic_cmd); 2413 2414 return 0; 2415 } 2416 2417 /** 2418 * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result 2419 * @hba: per adapter instance 2420 * @uic_cmd: UIC command 2421 * 2422 * Return: 0 only if success. 2423 */ 2424 int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) 2425 { 2426 int ret; 2427 2428 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UIC_CMD) 2429 return 0; 2430 2431 ufshcd_hold(hba); 2432 mutex_lock(&hba->uic_cmd_mutex); 2433 ufshcd_add_delay_before_dme_cmd(hba); 2434 2435 ret = __ufshcd_send_uic_cmd(hba, uic_cmd, true); 2436 if (!ret) 2437 ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd); 2438 2439 mutex_unlock(&hba->uic_cmd_mutex); 2440 2441 ufshcd_release(hba); 2442 return ret; 2443 } 2444 2445 /** 2446 * ufshcd_sgl_to_prdt - SG list to PRTD (Physical Region Description Table, 4DW format) 2447 * @hba: per-adapter instance 2448 * @lrbp: pointer to local reference block 2449 * @sg_entries: The number of sg lists actually used 2450 * @sg_list: Pointer to SG list 2451 */ 2452 static void ufshcd_sgl_to_prdt(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, int sg_entries, 2453 struct scatterlist *sg_list) 2454 { 2455 struct ufshcd_sg_entry *prd; 2456 struct scatterlist *sg; 2457 int i; 2458 2459 if (sg_entries) { 2460 2461 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) 2462 lrbp->utr_descriptor_ptr->prd_table_length = 2463 cpu_to_le16(sg_entries * ufshcd_sg_entry_size(hba)); 2464 else 2465 lrbp->utr_descriptor_ptr->prd_table_length = cpu_to_le16(sg_entries); 2466 2467 prd = lrbp->ucd_prdt_ptr; 2468 2469 for_each_sg(sg_list, sg, sg_entries, i) { 2470 const unsigned int len = sg_dma_len(sg); 2471 2472 /* 2473 * From the UFSHCI spec: "Data Byte Count (DBC): A '0' 2474 * based value that indicates the length, in bytes, of 2475 * the data block. A maximum of length of 256KB may 2476 * exist for any entry. Bits 1:0 of this field shall be 2477 * 11b to indicate Dword granularity. A value of '3' 2478 * indicates 4 bytes, '7' indicates 8 bytes, etc." 2479 */ 2480 WARN_ONCE(len > SZ_256K, "len = %#x\n", len); 2481 prd->size = cpu_to_le32(len - 1); 2482 prd->addr = cpu_to_le64(sg->dma_address); 2483 prd->reserved = 0; 2484 prd = (void *)prd + ufshcd_sg_entry_size(hba); 2485 } 2486 } else { 2487 lrbp->utr_descriptor_ptr->prd_table_length = 0; 2488 } 2489 } 2490 2491 /** 2492 * ufshcd_map_sg - Map scatter-gather list to prdt 2493 * @hba: per adapter instance 2494 * @lrbp: pointer to local reference block 2495 * 2496 * Return: 0 in case of success, non-zero value in case of failure. 2497 */ 2498 static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) 2499 { 2500 struct scsi_cmnd *cmd = lrbp->cmd; 2501 int sg_segments = scsi_dma_map(cmd); 2502 2503 if (sg_segments < 0) 2504 return sg_segments; 2505 2506 ufshcd_sgl_to_prdt(hba, lrbp, sg_segments, scsi_sglist(cmd)); 2507 2508 return 0; 2509 } 2510 2511 /** 2512 * ufshcd_enable_intr - enable interrupts 2513 * @hba: per adapter instance 2514 * @intrs: interrupt bits 2515 */ 2516 static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs) 2517 { 2518 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 2519 2520 if (hba->ufs_version == ufshci_version(1, 0)) { 2521 u32 rw; 2522 rw = set & INTERRUPT_MASK_RW_VER_10; 2523 set = rw | ((set ^ intrs) & intrs); 2524 } else { 2525 set |= intrs; 2526 } 2527 2528 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE); 2529 } 2530 2531 /** 2532 * ufshcd_disable_intr - disable interrupts 2533 * @hba: per adapter instance 2534 * @intrs: interrupt bits 2535 */ 2536 static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs) 2537 { 2538 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 2539 2540 if (hba->ufs_version == ufshci_version(1, 0)) { 2541 u32 rw; 2542 rw = (set & INTERRUPT_MASK_RW_VER_10) & 2543 ~(intrs & INTERRUPT_MASK_RW_VER_10); 2544 set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10); 2545 2546 } else { 2547 set &= ~intrs; 2548 } 2549 2550 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE); 2551 } 2552 2553 /** 2554 * ufshcd_prepare_req_desc_hdr - Fill UTP Transfer request descriptor header according to request 2555 * descriptor according to request 2556 * @lrbp: pointer to local reference block 2557 * @upiu_flags: flags required in the header 2558 * @cmd_dir: requests data direction 2559 * @ehs_length: Total EHS Length (in 32‐bytes units of all Extra Header Segments) 2560 */ 2561 static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp, u8 *upiu_flags, 2562 enum dma_data_direction cmd_dir, int ehs_length) 2563 { 2564 struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr; 2565 struct request_desc_header *h = &req_desc->header; 2566 enum utp_data_direction data_direction; 2567 2568 *h = (typeof(*h)){ }; 2569 2570 if (cmd_dir == DMA_FROM_DEVICE) { 2571 data_direction = UTP_DEVICE_TO_HOST; 2572 *upiu_flags = UPIU_CMD_FLAGS_READ; 2573 } else if (cmd_dir == DMA_TO_DEVICE) { 2574 data_direction = UTP_HOST_TO_DEVICE; 2575 *upiu_flags = UPIU_CMD_FLAGS_WRITE; 2576 } else { 2577 data_direction = UTP_NO_DATA_TRANSFER; 2578 *upiu_flags = UPIU_CMD_FLAGS_NONE; 2579 } 2580 2581 h->command_type = lrbp->command_type; 2582 h->data_direction = data_direction; 2583 h->ehs_length = ehs_length; 2584 2585 if (lrbp->intr_cmd) 2586 h->interrupt = 1; 2587 2588 /* Prepare crypto related dwords */ 2589 ufshcd_prepare_req_desc_hdr_crypto(lrbp, h); 2590 2591 /* 2592 * assigning invalid value for command status. Controller 2593 * updates OCS on command completion, with the command 2594 * status 2595 */ 2596 h->ocs = OCS_INVALID_COMMAND_STATUS; 2597 2598 req_desc->prd_table_length = 0; 2599 } 2600 2601 /** 2602 * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc, 2603 * for scsi commands 2604 * @lrbp: local reference block pointer 2605 * @upiu_flags: flags 2606 */ 2607 static 2608 void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u8 upiu_flags) 2609 { 2610 struct scsi_cmnd *cmd = lrbp->cmd; 2611 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr; 2612 unsigned short cdb_len; 2613 2614 ucd_req_ptr->header = (struct utp_upiu_header){ 2615 .transaction_code = UPIU_TRANSACTION_COMMAND, 2616 .flags = upiu_flags, 2617 .lun = lrbp->lun, 2618 .task_tag = lrbp->task_tag, 2619 .command_set_type = UPIU_COMMAND_SET_TYPE_SCSI, 2620 }; 2621 2622 ucd_req_ptr->sc.exp_data_transfer_len = cpu_to_be32(cmd->sdb.length); 2623 2624 cdb_len = min_t(unsigned short, cmd->cmd_len, UFS_CDB_SIZE); 2625 memset(ucd_req_ptr->sc.cdb, 0, UFS_CDB_SIZE); 2626 memcpy(ucd_req_ptr->sc.cdb, cmd->cmnd, cdb_len); 2627 2628 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 2629 } 2630 2631 /** 2632 * ufshcd_prepare_utp_query_req_upiu() - fill the utp_transfer_req_desc for query request 2633 * @hba: UFS hba 2634 * @lrbp: local reference block pointer 2635 * @upiu_flags: flags 2636 */ 2637 static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba, 2638 struct ufshcd_lrb *lrbp, u8 upiu_flags) 2639 { 2640 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr; 2641 struct ufs_query *query = &hba->dev_cmd.query; 2642 u16 len = be16_to_cpu(query->request.upiu_req.length); 2643 2644 /* Query request header */ 2645 ucd_req_ptr->header = (struct utp_upiu_header){ 2646 .transaction_code = UPIU_TRANSACTION_QUERY_REQ, 2647 .flags = upiu_flags, 2648 .lun = lrbp->lun, 2649 .task_tag = lrbp->task_tag, 2650 .query_function = query->request.query_func, 2651 /* Data segment length only need for WRITE_DESC */ 2652 .data_segment_length = 2653 query->request.upiu_req.opcode == 2654 UPIU_QUERY_OPCODE_WRITE_DESC ? 2655 cpu_to_be16(len) : 2656 0, 2657 }; 2658 2659 /* Copy the Query Request buffer as is */ 2660 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req, 2661 QUERY_OSF_SIZE); 2662 2663 /* Copy the Descriptor */ 2664 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC) 2665 memcpy(ucd_req_ptr + 1, query->descriptor, len); 2666 2667 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 2668 } 2669 2670 static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp) 2671 { 2672 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr; 2673 2674 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req)); 2675 2676 ucd_req_ptr->header = (struct utp_upiu_header){ 2677 .transaction_code = UPIU_TRANSACTION_NOP_OUT, 2678 .task_tag = lrbp->task_tag, 2679 }; 2680 2681 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 2682 } 2683 2684 /** 2685 * ufshcd_compose_devman_upiu - UFS Protocol Information Unit(UPIU) 2686 * for Device Management Purposes 2687 * @hba: per adapter instance 2688 * @lrbp: pointer to local reference block 2689 * 2690 * Return: 0 upon success; < 0 upon failure. 2691 */ 2692 static int ufshcd_compose_devman_upiu(struct ufs_hba *hba, 2693 struct ufshcd_lrb *lrbp) 2694 { 2695 u8 upiu_flags; 2696 int ret = 0; 2697 2698 if (hba->ufs_version <= ufshci_version(1, 1)) 2699 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE; 2700 else 2701 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE; 2702 2703 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE, 0); 2704 if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY) 2705 ufshcd_prepare_utp_query_req_upiu(hba, lrbp, upiu_flags); 2706 else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP) 2707 ufshcd_prepare_utp_nop_upiu(lrbp); 2708 else 2709 ret = -EINVAL; 2710 2711 return ret; 2712 } 2713 2714 /** 2715 * ufshcd_comp_scsi_upiu - UFS Protocol Information Unit(UPIU) 2716 * for SCSI Purposes 2717 * @hba: per adapter instance 2718 * @lrbp: pointer to local reference block 2719 * 2720 * Return: 0 upon success; < 0 upon failure. 2721 */ 2722 static int ufshcd_comp_scsi_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) 2723 { 2724 u8 upiu_flags; 2725 int ret = 0; 2726 2727 if (hba->ufs_version <= ufshci_version(1, 1)) 2728 lrbp->command_type = UTP_CMD_TYPE_SCSI; 2729 else 2730 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE; 2731 2732 if (likely(lrbp->cmd)) { 2733 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, lrbp->cmd->sc_data_direction, 0); 2734 ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags); 2735 } else { 2736 ret = -EINVAL; 2737 } 2738 2739 return ret; 2740 } 2741 2742 /** 2743 * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID 2744 * @upiu_wlun_id: UPIU W-LUN id 2745 * 2746 * Return: SCSI W-LUN id. 2747 */ 2748 static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id) 2749 { 2750 return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE; 2751 } 2752 2753 static inline bool is_device_wlun(struct scsi_device *sdev) 2754 { 2755 return sdev->lun == 2756 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN); 2757 } 2758 2759 /* 2760 * Associate the UFS controller queue with the default and poll HCTX types. 2761 * Initialize the mq_map[] arrays. 2762 */ 2763 static void ufshcd_map_queues(struct Scsi_Host *shost) 2764 { 2765 struct ufs_hba *hba = shost_priv(shost); 2766 int i, queue_offset = 0; 2767 2768 if (!is_mcq_supported(hba)) { 2769 hba->nr_queues[HCTX_TYPE_DEFAULT] = 1; 2770 hba->nr_queues[HCTX_TYPE_READ] = 0; 2771 hba->nr_queues[HCTX_TYPE_POLL] = 1; 2772 hba->nr_hw_queues = 1; 2773 } 2774 2775 for (i = 0; i < shost->nr_maps; i++) { 2776 struct blk_mq_queue_map *map = &shost->tag_set.map[i]; 2777 2778 map->nr_queues = hba->nr_queues[i]; 2779 if (!map->nr_queues) 2780 continue; 2781 map->queue_offset = queue_offset; 2782 if (i == HCTX_TYPE_POLL && !is_mcq_supported(hba)) 2783 map->queue_offset = 0; 2784 2785 blk_mq_map_queues(map); 2786 queue_offset += map->nr_queues; 2787 } 2788 } 2789 2790 static void ufshcd_init_lrb(struct ufs_hba *hba, struct ufshcd_lrb *lrb, int i) 2791 { 2792 struct utp_transfer_cmd_desc *cmd_descp = (void *)hba->ucdl_base_addr + 2793 i * ufshcd_get_ucd_size(hba); 2794 struct utp_transfer_req_desc *utrdlp = hba->utrdl_base_addr; 2795 dma_addr_t cmd_desc_element_addr = hba->ucdl_dma_addr + 2796 i * ufshcd_get_ucd_size(hba); 2797 u16 response_offset = offsetof(struct utp_transfer_cmd_desc, 2798 response_upiu); 2799 u16 prdt_offset = offsetof(struct utp_transfer_cmd_desc, prd_table); 2800 2801 lrb->utr_descriptor_ptr = utrdlp + i; 2802 lrb->utrd_dma_addr = hba->utrdl_dma_addr + 2803 i * sizeof(struct utp_transfer_req_desc); 2804 lrb->ucd_req_ptr = (struct utp_upiu_req *)cmd_descp->command_upiu; 2805 lrb->ucd_req_dma_addr = cmd_desc_element_addr; 2806 lrb->ucd_rsp_ptr = (struct utp_upiu_rsp *)cmd_descp->response_upiu; 2807 lrb->ucd_rsp_dma_addr = cmd_desc_element_addr + response_offset; 2808 lrb->ucd_prdt_ptr = (struct ufshcd_sg_entry *)cmd_descp->prd_table; 2809 lrb->ucd_prdt_dma_addr = cmd_desc_element_addr + prdt_offset; 2810 } 2811 2812 /** 2813 * ufshcd_queuecommand - main entry point for SCSI requests 2814 * @host: SCSI host pointer 2815 * @cmd: command from SCSI Midlayer 2816 * 2817 * Return: 0 for success, non-zero in case of failure. 2818 */ 2819 static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) 2820 { 2821 struct ufs_hba *hba = shost_priv(host); 2822 int tag = scsi_cmd_to_rq(cmd)->tag; 2823 struct ufshcd_lrb *lrbp; 2824 int err = 0; 2825 struct ufs_hw_queue *hwq = NULL; 2826 2827 WARN_ONCE(tag < 0 || tag >= hba->nutrs, "Invalid tag %d\n", tag); 2828 2829 switch (hba->ufshcd_state) { 2830 case UFSHCD_STATE_OPERATIONAL: 2831 break; 2832 case UFSHCD_STATE_EH_SCHEDULED_NON_FATAL: 2833 /* 2834 * SCSI error handler can call ->queuecommand() while UFS error 2835 * handler is in progress. Error interrupts could change the 2836 * state from UFSHCD_STATE_RESET to 2837 * UFSHCD_STATE_EH_SCHEDULED_NON_FATAL. Prevent requests 2838 * being issued in that case. 2839 */ 2840 if (ufshcd_eh_in_progress(hba)) { 2841 err = SCSI_MLQUEUE_HOST_BUSY; 2842 goto out; 2843 } 2844 break; 2845 case UFSHCD_STATE_EH_SCHEDULED_FATAL: 2846 /* 2847 * pm_runtime_get_sync() is used at error handling preparation 2848 * stage. If a scsi cmd, e.g. the SSU cmd, is sent from hba's 2849 * PM ops, it can never be finished if we let SCSI layer keep 2850 * retrying it, which gets err handler stuck forever. Neither 2851 * can we let the scsi cmd pass through, because UFS is in bad 2852 * state, the scsi cmd may eventually time out, which will get 2853 * err handler blocked for too long. So, just fail the scsi cmd 2854 * sent from PM ops, err handler can recover PM error anyways. 2855 */ 2856 if (hba->pm_op_in_progress) { 2857 hba->force_reset = true; 2858 set_host_byte(cmd, DID_BAD_TARGET); 2859 scsi_done(cmd); 2860 goto out; 2861 } 2862 fallthrough; 2863 case UFSHCD_STATE_RESET: 2864 err = SCSI_MLQUEUE_HOST_BUSY; 2865 goto out; 2866 case UFSHCD_STATE_ERROR: 2867 set_host_byte(cmd, DID_ERROR); 2868 scsi_done(cmd); 2869 goto out; 2870 } 2871 2872 hba->req_abort_count = 0; 2873 2874 ufshcd_hold(hba); 2875 2876 lrbp = &hba->lrb[tag]; 2877 lrbp->cmd = cmd; 2878 lrbp->task_tag = tag; 2879 lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun); 2880 lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba); 2881 2882 ufshcd_prepare_lrbp_crypto(scsi_cmd_to_rq(cmd), lrbp); 2883 2884 lrbp->req_abort_skip = false; 2885 2886 ufshcd_comp_scsi_upiu(hba, lrbp); 2887 2888 err = ufshcd_map_sg(hba, lrbp); 2889 if (err) { 2890 ufshcd_release(hba); 2891 goto out; 2892 } 2893 2894 if (is_mcq_enabled(hba)) 2895 hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(cmd)); 2896 2897 ufshcd_send_command(hba, tag, hwq); 2898 2899 out: 2900 if (ufs_trigger_eh()) { 2901 unsigned long flags; 2902 2903 spin_lock_irqsave(hba->host->host_lock, flags); 2904 ufshcd_schedule_eh_work(hba); 2905 spin_unlock_irqrestore(hba->host->host_lock, flags); 2906 } 2907 2908 return err; 2909 } 2910 2911 static int ufshcd_compose_dev_cmd(struct ufs_hba *hba, 2912 struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag) 2913 { 2914 lrbp->cmd = NULL; 2915 lrbp->task_tag = tag; 2916 lrbp->lun = 0; /* device management cmd is not specific to any LUN */ 2917 lrbp->intr_cmd = true; /* No interrupt aggregation */ 2918 ufshcd_prepare_lrbp_crypto(NULL, lrbp); 2919 hba->dev_cmd.type = cmd_type; 2920 2921 return ufshcd_compose_devman_upiu(hba, lrbp); 2922 } 2923 2924 /* 2925 * Check with the block layer if the command is inflight 2926 * @cmd: command to check. 2927 * 2928 * Return: true if command is inflight; false if not. 2929 */ 2930 bool ufshcd_cmd_inflight(struct scsi_cmnd *cmd) 2931 { 2932 struct request *rq; 2933 2934 if (!cmd) 2935 return false; 2936 2937 rq = scsi_cmd_to_rq(cmd); 2938 if (!blk_mq_request_started(rq)) 2939 return false; 2940 2941 return true; 2942 } 2943 2944 /* 2945 * Clear the pending command in the controller and wait until 2946 * the controller confirms that the command has been cleared. 2947 * @hba: per adapter instance 2948 * @task_tag: The tag number of the command to be cleared. 2949 */ 2950 static int ufshcd_clear_cmd(struct ufs_hba *hba, u32 task_tag) 2951 { 2952 u32 mask; 2953 unsigned long flags; 2954 int err; 2955 2956 if (is_mcq_enabled(hba)) { 2957 /* 2958 * MCQ mode. Clean up the MCQ resources similar to 2959 * what the ufshcd_utrl_clear() does for SDB mode. 2960 */ 2961 err = ufshcd_mcq_sq_cleanup(hba, task_tag); 2962 if (err) { 2963 dev_err(hba->dev, "%s: failed tag=%d. err=%d\n", 2964 __func__, task_tag, err); 2965 return err; 2966 } 2967 return 0; 2968 } 2969 2970 mask = 1U << task_tag; 2971 2972 /* clear outstanding transaction before retry */ 2973 spin_lock_irqsave(hba->host->host_lock, flags); 2974 ufshcd_utrl_clear(hba, mask); 2975 spin_unlock_irqrestore(hba->host->host_lock, flags); 2976 2977 /* 2978 * wait for h/w to clear corresponding bit in door-bell. 2979 * max. wait is 1 sec. 2980 */ 2981 return ufshcd_wait_for_register(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL, 2982 mask, ~mask, 1000, 1000); 2983 } 2984 2985 /** 2986 * ufshcd_dev_cmd_completion() - handles device management command responses 2987 * @hba: per adapter instance 2988 * @lrbp: pointer to local reference block 2989 * 2990 * Return: 0 upon success; < 0 upon failure. 2991 */ 2992 static int 2993 ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) 2994 { 2995 enum upiu_response_transaction resp; 2996 int err = 0; 2997 2998 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0); 2999 resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr); 3000 3001 switch (resp) { 3002 case UPIU_TRANSACTION_NOP_IN: 3003 if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) { 3004 err = -EINVAL; 3005 dev_err(hba->dev, "%s: unexpected response %x\n", 3006 __func__, resp); 3007 } 3008 break; 3009 case UPIU_TRANSACTION_QUERY_RSP: { 3010 u8 response = lrbp->ucd_rsp_ptr->header.response; 3011 3012 if (response == 0) 3013 err = ufshcd_copy_query_response(hba, lrbp); 3014 break; 3015 } 3016 case UPIU_TRANSACTION_REJECT_UPIU: 3017 /* TODO: handle Reject UPIU Response */ 3018 err = -EPERM; 3019 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n", 3020 __func__); 3021 break; 3022 case UPIU_TRANSACTION_RESPONSE: 3023 if (hba->dev_cmd.type != DEV_CMD_TYPE_RPMB) { 3024 err = -EINVAL; 3025 dev_err(hba->dev, "%s: unexpected response %x\n", __func__, resp); 3026 } 3027 break; 3028 default: 3029 err = -EINVAL; 3030 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n", 3031 __func__, resp); 3032 break; 3033 } 3034 3035 return err; 3036 } 3037 3038 static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba, 3039 struct ufshcd_lrb *lrbp, int max_timeout) 3040 { 3041 unsigned long time_left = msecs_to_jiffies(max_timeout); 3042 unsigned long flags; 3043 bool pending; 3044 int err; 3045 3046 retry: 3047 time_left = wait_for_completion_timeout(hba->dev_cmd.complete, 3048 time_left); 3049 3050 if (likely(time_left)) { 3051 /* 3052 * The completion handler called complete() and the caller of 3053 * this function still owns the @lrbp tag so the code below does 3054 * not trigger any race conditions. 3055 */ 3056 hba->dev_cmd.complete = NULL; 3057 err = ufshcd_get_tr_ocs(lrbp, NULL); 3058 if (!err) 3059 err = ufshcd_dev_cmd_completion(hba, lrbp); 3060 } else { 3061 err = -ETIMEDOUT; 3062 dev_dbg(hba->dev, "%s: dev_cmd request timedout, tag %d\n", 3063 __func__, lrbp->task_tag); 3064 3065 /* MCQ mode */ 3066 if (is_mcq_enabled(hba)) { 3067 err = ufshcd_clear_cmd(hba, lrbp->task_tag); 3068 hba->dev_cmd.complete = NULL; 3069 return err; 3070 } 3071 3072 /* SDB mode */ 3073 if (ufshcd_clear_cmd(hba, lrbp->task_tag) == 0) { 3074 /* successfully cleared the command, retry if needed */ 3075 err = -EAGAIN; 3076 /* 3077 * Since clearing the command succeeded we also need to 3078 * clear the task tag bit from the outstanding_reqs 3079 * variable. 3080 */ 3081 spin_lock_irqsave(&hba->outstanding_lock, flags); 3082 pending = test_bit(lrbp->task_tag, 3083 &hba->outstanding_reqs); 3084 if (pending) { 3085 hba->dev_cmd.complete = NULL; 3086 __clear_bit(lrbp->task_tag, 3087 &hba->outstanding_reqs); 3088 } 3089 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 3090 3091 if (!pending) { 3092 /* 3093 * The completion handler ran while we tried to 3094 * clear the command. 3095 */ 3096 time_left = 1; 3097 goto retry; 3098 } 3099 } else { 3100 dev_err(hba->dev, "%s: failed to clear tag %d\n", 3101 __func__, lrbp->task_tag); 3102 3103 spin_lock_irqsave(&hba->outstanding_lock, flags); 3104 pending = test_bit(lrbp->task_tag, 3105 &hba->outstanding_reqs); 3106 if (pending) 3107 hba->dev_cmd.complete = NULL; 3108 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 3109 3110 if (!pending) { 3111 /* 3112 * The completion handler ran while we tried to 3113 * clear the command. 3114 */ 3115 time_left = 1; 3116 goto retry; 3117 } 3118 } 3119 } 3120 3121 return err; 3122 } 3123 3124 /** 3125 * ufshcd_exec_dev_cmd - API for sending device management requests 3126 * @hba: UFS hba 3127 * @cmd_type: specifies the type (NOP, Query...) 3128 * @timeout: timeout in milliseconds 3129 * 3130 * Return: 0 upon success; < 0 upon failure. 3131 * 3132 * NOTE: Since there is only one available tag for device management commands, 3133 * it is expected you hold the hba->dev_cmd.lock mutex. 3134 */ 3135 static int ufshcd_exec_dev_cmd(struct ufs_hba *hba, 3136 enum dev_cmd_type cmd_type, int timeout) 3137 { 3138 DECLARE_COMPLETION_ONSTACK(wait); 3139 const u32 tag = hba->reserved_slot; 3140 struct ufshcd_lrb *lrbp; 3141 int err; 3142 3143 /* Protects use of hba->reserved_slot. */ 3144 lockdep_assert_held(&hba->dev_cmd.lock); 3145 3146 down_read(&hba->clk_scaling_lock); 3147 3148 lrbp = &hba->lrb[tag]; 3149 lrbp->cmd = NULL; 3150 err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag); 3151 if (unlikely(err)) 3152 goto out; 3153 3154 hba->dev_cmd.complete = &wait; 3155 3156 ufshcd_add_query_upiu_trace(hba, UFS_QUERY_SEND, lrbp->ucd_req_ptr); 3157 3158 ufshcd_send_command(hba, tag, hba->dev_cmd_queue); 3159 err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout); 3160 ufshcd_add_query_upiu_trace(hba, err ? UFS_QUERY_ERR : UFS_QUERY_COMP, 3161 (struct utp_upiu_req *)lrbp->ucd_rsp_ptr); 3162 3163 out: 3164 up_read(&hba->clk_scaling_lock); 3165 return err; 3166 } 3167 3168 /** 3169 * ufshcd_init_query() - init the query response and request parameters 3170 * @hba: per-adapter instance 3171 * @request: address of the request pointer to be initialized 3172 * @response: address of the response pointer to be initialized 3173 * @opcode: operation to perform 3174 * @idn: flag idn to access 3175 * @index: LU number to access 3176 * @selector: query/flag/descriptor further identification 3177 */ 3178 static inline void ufshcd_init_query(struct ufs_hba *hba, 3179 struct ufs_query_req **request, struct ufs_query_res **response, 3180 enum query_opcode opcode, u8 idn, u8 index, u8 selector) 3181 { 3182 *request = &hba->dev_cmd.query.request; 3183 *response = &hba->dev_cmd.query.response; 3184 memset(*request, 0, sizeof(struct ufs_query_req)); 3185 memset(*response, 0, sizeof(struct ufs_query_res)); 3186 (*request)->upiu_req.opcode = opcode; 3187 (*request)->upiu_req.idn = idn; 3188 (*request)->upiu_req.index = index; 3189 (*request)->upiu_req.selector = selector; 3190 } 3191 3192 static int ufshcd_query_flag_retry(struct ufs_hba *hba, 3193 enum query_opcode opcode, enum flag_idn idn, u8 index, bool *flag_res) 3194 { 3195 int ret; 3196 int retries; 3197 3198 for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) { 3199 ret = ufshcd_query_flag(hba, opcode, idn, index, flag_res); 3200 if (ret) 3201 dev_dbg(hba->dev, 3202 "%s: failed with error %d, retries %d\n", 3203 __func__, ret, retries); 3204 else 3205 break; 3206 } 3207 3208 if (ret) 3209 dev_err(hba->dev, 3210 "%s: query flag, opcode %d, idn %d, failed with error %d after %d retries\n", 3211 __func__, opcode, idn, ret, retries); 3212 return ret; 3213 } 3214 3215 /** 3216 * ufshcd_query_flag() - API function for sending flag query requests 3217 * @hba: per-adapter instance 3218 * @opcode: flag query to perform 3219 * @idn: flag idn to access 3220 * @index: flag index to access 3221 * @flag_res: the flag value after the query request completes 3222 * 3223 * Return: 0 for success, non-zero in case of failure. 3224 */ 3225 int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode, 3226 enum flag_idn idn, u8 index, bool *flag_res) 3227 { 3228 struct ufs_query_req *request = NULL; 3229 struct ufs_query_res *response = NULL; 3230 int err, selector = 0; 3231 int timeout = QUERY_REQ_TIMEOUT; 3232 3233 BUG_ON(!hba); 3234 3235 ufshcd_hold(hba); 3236 mutex_lock(&hba->dev_cmd.lock); 3237 ufshcd_init_query(hba, &request, &response, opcode, idn, index, 3238 selector); 3239 3240 switch (opcode) { 3241 case UPIU_QUERY_OPCODE_SET_FLAG: 3242 case UPIU_QUERY_OPCODE_CLEAR_FLAG: 3243 case UPIU_QUERY_OPCODE_TOGGLE_FLAG: 3244 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 3245 break; 3246 case UPIU_QUERY_OPCODE_READ_FLAG: 3247 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; 3248 if (!flag_res) { 3249 /* No dummy reads */ 3250 dev_err(hba->dev, "%s: Invalid argument for read request\n", 3251 __func__); 3252 err = -EINVAL; 3253 goto out_unlock; 3254 } 3255 break; 3256 default: 3257 dev_err(hba->dev, 3258 "%s: Expected query flag opcode but got = %d\n", 3259 __func__, opcode); 3260 err = -EINVAL; 3261 goto out_unlock; 3262 } 3263 3264 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout); 3265 3266 if (err) { 3267 dev_err(hba->dev, 3268 "%s: Sending flag query for idn %d failed, err = %d\n", 3269 __func__, idn, err); 3270 goto out_unlock; 3271 } 3272 3273 if (flag_res) 3274 *flag_res = (be32_to_cpu(response->upiu_res.value) & 3275 MASK_QUERY_UPIU_FLAG_LOC) & 0x1; 3276 3277 out_unlock: 3278 mutex_unlock(&hba->dev_cmd.lock); 3279 ufshcd_release(hba); 3280 return err; 3281 } 3282 3283 /** 3284 * ufshcd_query_attr - API function for sending attribute requests 3285 * @hba: per-adapter instance 3286 * @opcode: attribute opcode 3287 * @idn: attribute idn to access 3288 * @index: index field 3289 * @selector: selector field 3290 * @attr_val: the attribute value after the query request completes 3291 * 3292 * Return: 0 for success, non-zero in case of failure. 3293 */ 3294 int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode, 3295 enum attr_idn idn, u8 index, u8 selector, u32 *attr_val) 3296 { 3297 struct ufs_query_req *request = NULL; 3298 struct ufs_query_res *response = NULL; 3299 int err; 3300 3301 BUG_ON(!hba); 3302 3303 if (!attr_val) { 3304 dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n", 3305 __func__, opcode); 3306 return -EINVAL; 3307 } 3308 3309 ufshcd_hold(hba); 3310 3311 mutex_lock(&hba->dev_cmd.lock); 3312 ufshcd_init_query(hba, &request, &response, opcode, idn, index, 3313 selector); 3314 3315 switch (opcode) { 3316 case UPIU_QUERY_OPCODE_WRITE_ATTR: 3317 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 3318 request->upiu_req.value = cpu_to_be32(*attr_val); 3319 break; 3320 case UPIU_QUERY_OPCODE_READ_ATTR: 3321 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; 3322 break; 3323 default: 3324 dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n", 3325 __func__, opcode); 3326 err = -EINVAL; 3327 goto out_unlock; 3328 } 3329 3330 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT); 3331 3332 if (err) { 3333 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n", 3334 __func__, opcode, idn, index, err); 3335 goto out_unlock; 3336 } 3337 3338 *attr_val = be32_to_cpu(response->upiu_res.value); 3339 3340 out_unlock: 3341 mutex_unlock(&hba->dev_cmd.lock); 3342 ufshcd_release(hba); 3343 return err; 3344 } 3345 3346 /** 3347 * ufshcd_query_attr_retry() - API function for sending query 3348 * attribute with retries 3349 * @hba: per-adapter instance 3350 * @opcode: attribute opcode 3351 * @idn: attribute idn to access 3352 * @index: index field 3353 * @selector: selector field 3354 * @attr_val: the attribute value after the query request 3355 * completes 3356 * 3357 * Return: 0 for success, non-zero in case of failure. 3358 */ 3359 int ufshcd_query_attr_retry(struct ufs_hba *hba, 3360 enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector, 3361 u32 *attr_val) 3362 { 3363 int ret = 0; 3364 u32 retries; 3365 3366 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) { 3367 ret = ufshcd_query_attr(hba, opcode, idn, index, 3368 selector, attr_val); 3369 if (ret) 3370 dev_dbg(hba->dev, "%s: failed with error %d, retries %d\n", 3371 __func__, ret, retries); 3372 else 3373 break; 3374 } 3375 3376 if (ret) 3377 dev_err(hba->dev, 3378 "%s: query attribute, idn %d, failed with error %d after %d retries\n", 3379 __func__, idn, ret, QUERY_REQ_RETRIES); 3380 return ret; 3381 } 3382 3383 static int __ufshcd_query_descriptor(struct ufs_hba *hba, 3384 enum query_opcode opcode, enum desc_idn idn, u8 index, 3385 u8 selector, u8 *desc_buf, int *buf_len) 3386 { 3387 struct ufs_query_req *request = NULL; 3388 struct ufs_query_res *response = NULL; 3389 int err; 3390 3391 BUG_ON(!hba); 3392 3393 if (!desc_buf) { 3394 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n", 3395 __func__, opcode); 3396 return -EINVAL; 3397 } 3398 3399 if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) { 3400 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n", 3401 __func__, *buf_len); 3402 return -EINVAL; 3403 } 3404 3405 ufshcd_hold(hba); 3406 3407 mutex_lock(&hba->dev_cmd.lock); 3408 ufshcd_init_query(hba, &request, &response, opcode, idn, index, 3409 selector); 3410 hba->dev_cmd.query.descriptor = desc_buf; 3411 request->upiu_req.length = cpu_to_be16(*buf_len); 3412 3413 switch (opcode) { 3414 case UPIU_QUERY_OPCODE_WRITE_DESC: 3415 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 3416 break; 3417 case UPIU_QUERY_OPCODE_READ_DESC: 3418 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; 3419 break; 3420 default: 3421 dev_err(hba->dev, 3422 "%s: Expected query descriptor opcode but got = 0x%.2x\n", 3423 __func__, opcode); 3424 err = -EINVAL; 3425 goto out_unlock; 3426 } 3427 3428 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT); 3429 3430 if (err) { 3431 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n", 3432 __func__, opcode, idn, index, err); 3433 goto out_unlock; 3434 } 3435 3436 *buf_len = be16_to_cpu(response->upiu_res.length); 3437 3438 out_unlock: 3439 hba->dev_cmd.query.descriptor = NULL; 3440 mutex_unlock(&hba->dev_cmd.lock); 3441 ufshcd_release(hba); 3442 return err; 3443 } 3444 3445 /** 3446 * ufshcd_query_descriptor_retry - API function for sending descriptor requests 3447 * @hba: per-adapter instance 3448 * @opcode: attribute opcode 3449 * @idn: attribute idn to access 3450 * @index: index field 3451 * @selector: selector field 3452 * @desc_buf: the buffer that contains the descriptor 3453 * @buf_len: length parameter passed to the device 3454 * 3455 * The buf_len parameter will contain, on return, the length parameter 3456 * received on the response. 3457 * 3458 * Return: 0 for success, non-zero in case of failure. 3459 */ 3460 int ufshcd_query_descriptor_retry(struct ufs_hba *hba, 3461 enum query_opcode opcode, 3462 enum desc_idn idn, u8 index, 3463 u8 selector, 3464 u8 *desc_buf, int *buf_len) 3465 { 3466 int err; 3467 int retries; 3468 3469 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) { 3470 err = __ufshcd_query_descriptor(hba, opcode, idn, index, 3471 selector, desc_buf, buf_len); 3472 if (!err || err == -EINVAL) 3473 break; 3474 } 3475 3476 return err; 3477 } 3478 3479 /** 3480 * ufshcd_read_desc_param - read the specified descriptor parameter 3481 * @hba: Pointer to adapter instance 3482 * @desc_id: descriptor idn value 3483 * @desc_index: descriptor index 3484 * @param_offset: offset of the parameter to read 3485 * @param_read_buf: pointer to buffer where parameter would be read 3486 * @param_size: sizeof(param_read_buf) 3487 * 3488 * Return: 0 in case of success, non-zero otherwise. 3489 */ 3490 int ufshcd_read_desc_param(struct ufs_hba *hba, 3491 enum desc_idn desc_id, 3492 int desc_index, 3493 u8 param_offset, 3494 u8 *param_read_buf, 3495 u8 param_size) 3496 { 3497 int ret; 3498 u8 *desc_buf; 3499 int buff_len = QUERY_DESC_MAX_SIZE; 3500 bool is_kmalloc = true; 3501 3502 /* Safety check */ 3503 if (desc_id >= QUERY_DESC_IDN_MAX || !param_size) 3504 return -EINVAL; 3505 3506 /* Check whether we need temp memory */ 3507 if (param_offset != 0 || param_size < buff_len) { 3508 desc_buf = kzalloc(buff_len, GFP_KERNEL); 3509 if (!desc_buf) 3510 return -ENOMEM; 3511 } else { 3512 desc_buf = param_read_buf; 3513 is_kmalloc = false; 3514 } 3515 3516 /* Request for full descriptor */ 3517 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC, 3518 desc_id, desc_index, 0, 3519 desc_buf, &buff_len); 3520 if (ret) { 3521 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d\n", 3522 __func__, desc_id, desc_index, param_offset, ret); 3523 goto out; 3524 } 3525 3526 /* Update descriptor length */ 3527 buff_len = desc_buf[QUERY_DESC_LENGTH_OFFSET]; 3528 3529 if (param_offset >= buff_len) { 3530 dev_err(hba->dev, "%s: Invalid offset 0x%x in descriptor IDN 0x%x, length 0x%x\n", 3531 __func__, param_offset, desc_id, buff_len); 3532 ret = -EINVAL; 3533 goto out; 3534 } 3535 3536 /* Sanity check */ 3537 if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) { 3538 dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header\n", 3539 __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]); 3540 ret = -EINVAL; 3541 goto out; 3542 } 3543 3544 if (is_kmalloc) { 3545 /* Make sure we don't copy more data than available */ 3546 if (param_offset >= buff_len) 3547 ret = -EINVAL; 3548 else 3549 memcpy(param_read_buf, &desc_buf[param_offset], 3550 min_t(u32, param_size, buff_len - param_offset)); 3551 } 3552 out: 3553 if (is_kmalloc) 3554 kfree(desc_buf); 3555 return ret; 3556 } 3557 3558 /** 3559 * struct uc_string_id - unicode string 3560 * 3561 * @len: size of this descriptor inclusive 3562 * @type: descriptor type 3563 * @uc: unicode string character 3564 */ 3565 struct uc_string_id { 3566 u8 len; 3567 u8 type; 3568 wchar_t uc[]; 3569 } __packed; 3570 3571 /* replace non-printable or non-ASCII characters with spaces */ 3572 static inline char ufshcd_remove_non_printable(u8 ch) 3573 { 3574 return (ch >= 0x20 && ch <= 0x7e) ? ch : ' '; 3575 } 3576 3577 /** 3578 * ufshcd_read_string_desc - read string descriptor 3579 * @hba: pointer to adapter instance 3580 * @desc_index: descriptor index 3581 * @buf: pointer to buffer where descriptor would be read, 3582 * the caller should free the memory. 3583 * @ascii: if true convert from unicode to ascii characters 3584 * null terminated string. 3585 * 3586 * Return: 3587 * * string size on success. 3588 * * -ENOMEM: on allocation failure 3589 * * -EINVAL: on a wrong parameter 3590 */ 3591 int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index, 3592 u8 **buf, bool ascii) 3593 { 3594 struct uc_string_id *uc_str; 3595 u8 *str; 3596 int ret; 3597 3598 if (!buf) 3599 return -EINVAL; 3600 3601 uc_str = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL); 3602 if (!uc_str) 3603 return -ENOMEM; 3604 3605 ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_STRING, desc_index, 0, 3606 (u8 *)uc_str, QUERY_DESC_MAX_SIZE); 3607 if (ret < 0) { 3608 dev_err(hba->dev, "Reading String Desc failed after %d retries. err = %d\n", 3609 QUERY_REQ_RETRIES, ret); 3610 str = NULL; 3611 goto out; 3612 } 3613 3614 if (uc_str->len <= QUERY_DESC_HDR_SIZE) { 3615 dev_dbg(hba->dev, "String Desc is of zero length\n"); 3616 str = NULL; 3617 ret = 0; 3618 goto out; 3619 } 3620 3621 if (ascii) { 3622 ssize_t ascii_len; 3623 int i; 3624 /* remove header and divide by 2 to move from UTF16 to UTF8 */ 3625 ascii_len = (uc_str->len - QUERY_DESC_HDR_SIZE) / 2 + 1; 3626 str = kzalloc(ascii_len, GFP_KERNEL); 3627 if (!str) { 3628 ret = -ENOMEM; 3629 goto out; 3630 } 3631 3632 /* 3633 * the descriptor contains string in UTF16 format 3634 * we need to convert to utf-8 so it can be displayed 3635 */ 3636 ret = utf16s_to_utf8s(uc_str->uc, 3637 uc_str->len - QUERY_DESC_HDR_SIZE, 3638 UTF16_BIG_ENDIAN, str, ascii_len - 1); 3639 3640 /* replace non-printable or non-ASCII characters with spaces */ 3641 for (i = 0; i < ret; i++) 3642 str[i] = ufshcd_remove_non_printable(str[i]); 3643 3644 str[ret++] = '\0'; 3645 3646 } else { 3647 str = kmemdup(uc_str, uc_str->len, GFP_KERNEL); 3648 if (!str) { 3649 ret = -ENOMEM; 3650 goto out; 3651 } 3652 ret = uc_str->len; 3653 } 3654 out: 3655 *buf = str; 3656 kfree(uc_str); 3657 return ret; 3658 } 3659 3660 /** 3661 * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter 3662 * @hba: Pointer to adapter instance 3663 * @lun: lun id 3664 * @param_offset: offset of the parameter to read 3665 * @param_read_buf: pointer to buffer where parameter would be read 3666 * @param_size: sizeof(param_read_buf) 3667 * 3668 * Return: 0 in case of success, non-zero otherwise. 3669 */ 3670 static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba, 3671 int lun, 3672 enum unit_desc_param param_offset, 3673 u8 *param_read_buf, 3674 u32 param_size) 3675 { 3676 /* 3677 * Unit descriptors are only available for general purpose LUs (LUN id 3678 * from 0 to 7) and RPMB Well known LU. 3679 */ 3680 if (!ufs_is_valid_unit_desc_lun(&hba->dev_info, lun)) 3681 return -EOPNOTSUPP; 3682 3683 return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun, 3684 param_offset, param_read_buf, param_size); 3685 } 3686 3687 static int ufshcd_get_ref_clk_gating_wait(struct ufs_hba *hba) 3688 { 3689 int err = 0; 3690 u32 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US; 3691 3692 if (hba->dev_info.wspecversion >= 0x300) { 3693 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 3694 QUERY_ATTR_IDN_REF_CLK_GATING_WAIT_TIME, 0, 0, 3695 &gating_wait); 3696 if (err) 3697 dev_err(hba->dev, "Failed reading bRefClkGatingWait. err = %d, use default %uus\n", 3698 err, gating_wait); 3699 3700 if (gating_wait == 0) { 3701 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US; 3702 dev_err(hba->dev, "Undefined ref clk gating wait time, use default %uus\n", 3703 gating_wait); 3704 } 3705 3706 hba->dev_info.clk_gating_wait_us = gating_wait; 3707 } 3708 3709 return err; 3710 } 3711 3712 /** 3713 * ufshcd_memory_alloc - allocate memory for host memory space data structures 3714 * @hba: per adapter instance 3715 * 3716 * 1. Allocate DMA memory for Command Descriptor array 3717 * Each command descriptor consist of Command UPIU, Response UPIU and PRDT 3718 * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL). 3719 * 3. Allocate DMA memory for UTP Task Management Request Descriptor List 3720 * (UTMRDL) 3721 * 4. Allocate memory for local reference block(lrb). 3722 * 3723 * Return: 0 for success, non-zero in case of failure. 3724 */ 3725 static int ufshcd_memory_alloc(struct ufs_hba *hba) 3726 { 3727 size_t utmrdl_size, utrdl_size, ucdl_size; 3728 3729 /* Allocate memory for UTP command descriptors */ 3730 ucdl_size = ufshcd_get_ucd_size(hba) * hba->nutrs; 3731 hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev, 3732 ucdl_size, 3733 &hba->ucdl_dma_addr, 3734 GFP_KERNEL); 3735 3736 /* 3737 * UFSHCI requires UTP command descriptor to be 128 byte aligned. 3738 */ 3739 if (!hba->ucdl_base_addr || 3740 WARN_ON(hba->ucdl_dma_addr & (128 - 1))) { 3741 dev_err(hba->dev, 3742 "Command Descriptor Memory allocation failed\n"); 3743 goto out; 3744 } 3745 3746 /* 3747 * Allocate memory for UTP Transfer descriptors 3748 * UFSHCI requires 1KB alignment of UTRD 3749 */ 3750 utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs); 3751 hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev, 3752 utrdl_size, 3753 &hba->utrdl_dma_addr, 3754 GFP_KERNEL); 3755 if (!hba->utrdl_base_addr || 3756 WARN_ON(hba->utrdl_dma_addr & (SZ_1K - 1))) { 3757 dev_err(hba->dev, 3758 "Transfer Descriptor Memory allocation failed\n"); 3759 goto out; 3760 } 3761 3762 /* 3763 * Skip utmrdl allocation; it may have been 3764 * allocated during first pass and not released during 3765 * MCQ memory allocation. 3766 * See ufshcd_release_sdb_queue() and ufshcd_config_mcq() 3767 */ 3768 if (hba->utmrdl_base_addr) 3769 goto skip_utmrdl; 3770 /* 3771 * Allocate memory for UTP Task Management descriptors 3772 * UFSHCI requires 1KB alignment of UTMRD 3773 */ 3774 utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs; 3775 hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev, 3776 utmrdl_size, 3777 &hba->utmrdl_dma_addr, 3778 GFP_KERNEL); 3779 if (!hba->utmrdl_base_addr || 3780 WARN_ON(hba->utmrdl_dma_addr & (SZ_1K - 1))) { 3781 dev_err(hba->dev, 3782 "Task Management Descriptor Memory allocation failed\n"); 3783 goto out; 3784 } 3785 3786 skip_utmrdl: 3787 /* Allocate memory for local reference block */ 3788 hba->lrb = devm_kcalloc(hba->dev, 3789 hba->nutrs, sizeof(struct ufshcd_lrb), 3790 GFP_KERNEL); 3791 if (!hba->lrb) { 3792 dev_err(hba->dev, "LRB Memory allocation failed\n"); 3793 goto out; 3794 } 3795 return 0; 3796 out: 3797 return -ENOMEM; 3798 } 3799 3800 /** 3801 * ufshcd_host_memory_configure - configure local reference block with 3802 * memory offsets 3803 * @hba: per adapter instance 3804 * 3805 * Configure Host memory space 3806 * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA 3807 * address. 3808 * 2. Update each UTRD with Response UPIU offset, Response UPIU length 3809 * and PRDT offset. 3810 * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT 3811 * into local reference block. 3812 */ 3813 static void ufshcd_host_memory_configure(struct ufs_hba *hba) 3814 { 3815 struct utp_transfer_req_desc *utrdlp; 3816 dma_addr_t cmd_desc_dma_addr; 3817 dma_addr_t cmd_desc_element_addr; 3818 u16 response_offset; 3819 u16 prdt_offset; 3820 int cmd_desc_size; 3821 int i; 3822 3823 utrdlp = hba->utrdl_base_addr; 3824 3825 response_offset = 3826 offsetof(struct utp_transfer_cmd_desc, response_upiu); 3827 prdt_offset = 3828 offsetof(struct utp_transfer_cmd_desc, prd_table); 3829 3830 cmd_desc_size = ufshcd_get_ucd_size(hba); 3831 cmd_desc_dma_addr = hba->ucdl_dma_addr; 3832 3833 for (i = 0; i < hba->nutrs; i++) { 3834 /* Configure UTRD with command descriptor base address */ 3835 cmd_desc_element_addr = 3836 (cmd_desc_dma_addr + (cmd_desc_size * i)); 3837 utrdlp[i].command_desc_base_addr = 3838 cpu_to_le64(cmd_desc_element_addr); 3839 3840 /* Response upiu and prdt offset should be in double words */ 3841 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) { 3842 utrdlp[i].response_upiu_offset = 3843 cpu_to_le16(response_offset); 3844 utrdlp[i].prd_table_offset = 3845 cpu_to_le16(prdt_offset); 3846 utrdlp[i].response_upiu_length = 3847 cpu_to_le16(ALIGNED_UPIU_SIZE); 3848 } else { 3849 utrdlp[i].response_upiu_offset = 3850 cpu_to_le16(response_offset >> 2); 3851 utrdlp[i].prd_table_offset = 3852 cpu_to_le16(prdt_offset >> 2); 3853 utrdlp[i].response_upiu_length = 3854 cpu_to_le16(ALIGNED_UPIU_SIZE >> 2); 3855 } 3856 3857 ufshcd_init_lrb(hba, &hba->lrb[i], i); 3858 } 3859 } 3860 3861 /** 3862 * ufshcd_dme_link_startup - Notify Unipro to perform link startup 3863 * @hba: per adapter instance 3864 * 3865 * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer, 3866 * in order to initialize the Unipro link startup procedure. 3867 * Once the Unipro links are up, the device connected to the controller 3868 * is detected. 3869 * 3870 * Return: 0 on success, non-zero value on failure. 3871 */ 3872 static int ufshcd_dme_link_startup(struct ufs_hba *hba) 3873 { 3874 struct uic_command uic_cmd = {0}; 3875 int ret; 3876 3877 uic_cmd.command = UIC_CMD_DME_LINK_STARTUP; 3878 3879 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 3880 if (ret) 3881 dev_dbg(hba->dev, 3882 "dme-link-startup: error code %d\n", ret); 3883 return ret; 3884 } 3885 /** 3886 * ufshcd_dme_reset - UIC command for DME_RESET 3887 * @hba: per adapter instance 3888 * 3889 * DME_RESET command is issued in order to reset UniPro stack. 3890 * This function now deals with cold reset. 3891 * 3892 * Return: 0 on success, non-zero value on failure. 3893 */ 3894 static int ufshcd_dme_reset(struct ufs_hba *hba) 3895 { 3896 struct uic_command uic_cmd = {0}; 3897 int ret; 3898 3899 uic_cmd.command = UIC_CMD_DME_RESET; 3900 3901 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 3902 if (ret) 3903 dev_err(hba->dev, 3904 "dme-reset: error code %d\n", ret); 3905 3906 return ret; 3907 } 3908 3909 int ufshcd_dme_configure_adapt(struct ufs_hba *hba, 3910 int agreed_gear, 3911 int adapt_val) 3912 { 3913 int ret; 3914 3915 if (agreed_gear < UFS_HS_G4) 3916 adapt_val = PA_NO_ADAPT; 3917 3918 ret = ufshcd_dme_set(hba, 3919 UIC_ARG_MIB(PA_TXHSADAPTTYPE), 3920 adapt_val); 3921 return ret; 3922 } 3923 EXPORT_SYMBOL_GPL(ufshcd_dme_configure_adapt); 3924 3925 /** 3926 * ufshcd_dme_enable - UIC command for DME_ENABLE 3927 * @hba: per adapter instance 3928 * 3929 * DME_ENABLE command is issued in order to enable UniPro stack. 3930 * 3931 * Return: 0 on success, non-zero value on failure. 3932 */ 3933 static int ufshcd_dme_enable(struct ufs_hba *hba) 3934 { 3935 struct uic_command uic_cmd = {0}; 3936 int ret; 3937 3938 uic_cmd.command = UIC_CMD_DME_ENABLE; 3939 3940 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 3941 if (ret) 3942 dev_err(hba->dev, 3943 "dme-enable: error code %d\n", ret); 3944 3945 return ret; 3946 } 3947 3948 static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba) 3949 { 3950 #define MIN_DELAY_BEFORE_DME_CMDS_US 1000 3951 unsigned long min_sleep_time_us; 3952 3953 if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS)) 3954 return; 3955 3956 /* 3957 * last_dme_cmd_tstamp will be 0 only for 1st call to 3958 * this function 3959 */ 3960 if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) { 3961 min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US; 3962 } else { 3963 unsigned long delta = 3964 (unsigned long) ktime_to_us( 3965 ktime_sub(ktime_get(), 3966 hba->last_dme_cmd_tstamp)); 3967 3968 if (delta < MIN_DELAY_BEFORE_DME_CMDS_US) 3969 min_sleep_time_us = 3970 MIN_DELAY_BEFORE_DME_CMDS_US - delta; 3971 else 3972 return; /* no more delay required */ 3973 } 3974 3975 /* allow sleep for extra 50us if needed */ 3976 usleep_range(min_sleep_time_us, min_sleep_time_us + 50); 3977 } 3978 3979 /** 3980 * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET 3981 * @hba: per adapter instance 3982 * @attr_sel: uic command argument1 3983 * @attr_set: attribute set type as uic command argument2 3984 * @mib_val: setting value as uic command argument3 3985 * @peer: indicate whether peer or local 3986 * 3987 * Return: 0 on success, non-zero value on failure. 3988 */ 3989 int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel, 3990 u8 attr_set, u32 mib_val, u8 peer) 3991 { 3992 struct uic_command uic_cmd = {0}; 3993 static const char *const action[] = { 3994 "dme-set", 3995 "dme-peer-set" 3996 }; 3997 const char *set = action[!!peer]; 3998 int ret; 3999 int retries = UFS_UIC_COMMAND_RETRIES; 4000 4001 uic_cmd.command = peer ? 4002 UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET; 4003 uic_cmd.argument1 = attr_sel; 4004 uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set); 4005 uic_cmd.argument3 = mib_val; 4006 4007 do { 4008 /* for peer attributes we retry upon failure */ 4009 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 4010 if (ret) 4011 dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n", 4012 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret); 4013 } while (ret && peer && --retries); 4014 4015 if (ret) 4016 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n", 4017 set, UIC_GET_ATTR_ID(attr_sel), mib_val, 4018 UFS_UIC_COMMAND_RETRIES - retries); 4019 4020 return ret; 4021 } 4022 EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr); 4023 4024 /** 4025 * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET 4026 * @hba: per adapter instance 4027 * @attr_sel: uic command argument1 4028 * @mib_val: the value of the attribute as returned by the UIC command 4029 * @peer: indicate whether peer or local 4030 * 4031 * Return: 0 on success, non-zero value on failure. 4032 */ 4033 int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel, 4034 u32 *mib_val, u8 peer) 4035 { 4036 struct uic_command uic_cmd = {0}; 4037 static const char *const action[] = { 4038 "dme-get", 4039 "dme-peer-get" 4040 }; 4041 const char *get = action[!!peer]; 4042 int ret; 4043 int retries = UFS_UIC_COMMAND_RETRIES; 4044 struct ufs_pa_layer_attr orig_pwr_info; 4045 struct ufs_pa_layer_attr temp_pwr_info; 4046 bool pwr_mode_change = false; 4047 4048 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) { 4049 orig_pwr_info = hba->pwr_info; 4050 temp_pwr_info = orig_pwr_info; 4051 4052 if (orig_pwr_info.pwr_tx == FAST_MODE || 4053 orig_pwr_info.pwr_rx == FAST_MODE) { 4054 temp_pwr_info.pwr_tx = FASTAUTO_MODE; 4055 temp_pwr_info.pwr_rx = FASTAUTO_MODE; 4056 pwr_mode_change = true; 4057 } else if (orig_pwr_info.pwr_tx == SLOW_MODE || 4058 orig_pwr_info.pwr_rx == SLOW_MODE) { 4059 temp_pwr_info.pwr_tx = SLOWAUTO_MODE; 4060 temp_pwr_info.pwr_rx = SLOWAUTO_MODE; 4061 pwr_mode_change = true; 4062 } 4063 if (pwr_mode_change) { 4064 ret = ufshcd_change_power_mode(hba, &temp_pwr_info); 4065 if (ret) 4066 goto out; 4067 } 4068 } 4069 4070 uic_cmd.command = peer ? 4071 UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET; 4072 uic_cmd.argument1 = attr_sel; 4073 4074 do { 4075 /* for peer attributes we retry upon failure */ 4076 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 4077 if (ret) 4078 dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n", 4079 get, UIC_GET_ATTR_ID(attr_sel), ret); 4080 } while (ret && peer && --retries); 4081 4082 if (ret) 4083 dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n", 4084 get, UIC_GET_ATTR_ID(attr_sel), 4085 UFS_UIC_COMMAND_RETRIES - retries); 4086 4087 if (mib_val && !ret) 4088 *mib_val = uic_cmd.argument3; 4089 4090 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE) 4091 && pwr_mode_change) 4092 ufshcd_change_power_mode(hba, &orig_pwr_info); 4093 out: 4094 return ret; 4095 } 4096 EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr); 4097 4098 /** 4099 * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power 4100 * state) and waits for it to take effect. 4101 * 4102 * @hba: per adapter instance 4103 * @cmd: UIC command to execute 4104 * 4105 * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER & 4106 * DME_HIBERNATE_EXIT commands take some time to take its effect on both host 4107 * and device UniPro link and hence it's final completion would be indicated by 4108 * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in 4109 * addition to normal UIC command completion Status (UCCS). This function only 4110 * returns after the relevant status bits indicate the completion. 4111 * 4112 * Return: 0 on success, non-zero value on failure. 4113 */ 4114 static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd) 4115 { 4116 DECLARE_COMPLETION_ONSTACK(uic_async_done); 4117 unsigned long flags; 4118 u8 status; 4119 int ret; 4120 bool reenable_intr = false; 4121 4122 mutex_lock(&hba->uic_cmd_mutex); 4123 ufshcd_add_delay_before_dme_cmd(hba); 4124 4125 spin_lock_irqsave(hba->host->host_lock, flags); 4126 if (ufshcd_is_link_broken(hba)) { 4127 ret = -ENOLINK; 4128 goto out_unlock; 4129 } 4130 hba->uic_async_done = &uic_async_done; 4131 if (ufshcd_readl(hba, REG_INTERRUPT_ENABLE) & UIC_COMMAND_COMPL) { 4132 ufshcd_disable_intr(hba, UIC_COMMAND_COMPL); 4133 /* 4134 * Make sure UIC command completion interrupt is disabled before 4135 * issuing UIC command. 4136 */ 4137 wmb(); 4138 reenable_intr = true; 4139 } 4140 spin_unlock_irqrestore(hba->host->host_lock, flags); 4141 ret = __ufshcd_send_uic_cmd(hba, cmd, false); 4142 if (ret) { 4143 dev_err(hba->dev, 4144 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n", 4145 cmd->command, cmd->argument3, ret); 4146 goto out; 4147 } 4148 4149 if (!wait_for_completion_timeout(hba->uic_async_done, 4150 msecs_to_jiffies(UIC_CMD_TIMEOUT))) { 4151 dev_err(hba->dev, 4152 "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n", 4153 cmd->command, cmd->argument3); 4154 4155 if (!cmd->cmd_active) { 4156 dev_err(hba->dev, "%s: Power Mode Change operation has been completed, go check UPMCRS\n", 4157 __func__); 4158 goto check_upmcrs; 4159 } 4160 4161 ret = -ETIMEDOUT; 4162 goto out; 4163 } 4164 4165 check_upmcrs: 4166 status = ufshcd_get_upmcrs(hba); 4167 if (status != PWR_LOCAL) { 4168 dev_err(hba->dev, 4169 "pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n", 4170 cmd->command, status); 4171 ret = (status != PWR_OK) ? status : -1; 4172 } 4173 out: 4174 if (ret) { 4175 ufshcd_print_host_state(hba); 4176 ufshcd_print_pwr_info(hba); 4177 ufshcd_print_evt_hist(hba); 4178 } 4179 4180 spin_lock_irqsave(hba->host->host_lock, flags); 4181 hba->active_uic_cmd = NULL; 4182 hba->uic_async_done = NULL; 4183 if (reenable_intr) 4184 ufshcd_enable_intr(hba, UIC_COMMAND_COMPL); 4185 if (ret) { 4186 ufshcd_set_link_broken(hba); 4187 ufshcd_schedule_eh_work(hba); 4188 } 4189 out_unlock: 4190 spin_unlock_irqrestore(hba->host->host_lock, flags); 4191 mutex_unlock(&hba->uic_cmd_mutex); 4192 4193 return ret; 4194 } 4195 4196 /** 4197 * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage 4198 * using DME_SET primitives. 4199 * @hba: per adapter instance 4200 * @mode: powr mode value 4201 * 4202 * Return: 0 on success, non-zero value on failure. 4203 */ 4204 int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode) 4205 { 4206 struct uic_command uic_cmd = {0}; 4207 int ret; 4208 4209 if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) { 4210 ret = ufshcd_dme_set(hba, 4211 UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1); 4212 if (ret) { 4213 dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n", 4214 __func__, ret); 4215 goto out; 4216 } 4217 } 4218 4219 uic_cmd.command = UIC_CMD_DME_SET; 4220 uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE); 4221 uic_cmd.argument3 = mode; 4222 ufshcd_hold(hba); 4223 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd); 4224 ufshcd_release(hba); 4225 4226 out: 4227 return ret; 4228 } 4229 EXPORT_SYMBOL_GPL(ufshcd_uic_change_pwr_mode); 4230 4231 int ufshcd_link_recovery(struct ufs_hba *hba) 4232 { 4233 int ret; 4234 unsigned long flags; 4235 4236 spin_lock_irqsave(hba->host->host_lock, flags); 4237 hba->ufshcd_state = UFSHCD_STATE_RESET; 4238 ufshcd_set_eh_in_progress(hba); 4239 spin_unlock_irqrestore(hba->host->host_lock, flags); 4240 4241 /* Reset the attached device */ 4242 ufshcd_device_reset(hba); 4243 4244 ret = ufshcd_host_reset_and_restore(hba); 4245 4246 spin_lock_irqsave(hba->host->host_lock, flags); 4247 if (ret) 4248 hba->ufshcd_state = UFSHCD_STATE_ERROR; 4249 ufshcd_clear_eh_in_progress(hba); 4250 spin_unlock_irqrestore(hba->host->host_lock, flags); 4251 4252 if (ret) 4253 dev_err(hba->dev, "%s: link recovery failed, err %d", 4254 __func__, ret); 4255 4256 return ret; 4257 } 4258 EXPORT_SYMBOL_GPL(ufshcd_link_recovery); 4259 4260 int ufshcd_uic_hibern8_enter(struct ufs_hba *hba) 4261 { 4262 int ret; 4263 struct uic_command uic_cmd = {0}; 4264 ktime_t start = ktime_get(); 4265 4266 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, PRE_CHANGE); 4267 4268 uic_cmd.command = UIC_CMD_DME_HIBER_ENTER; 4269 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd); 4270 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "enter", 4271 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 4272 4273 if (ret) 4274 dev_err(hba->dev, "%s: hibern8 enter failed. ret = %d\n", 4275 __func__, ret); 4276 else 4277 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, 4278 POST_CHANGE); 4279 4280 return ret; 4281 } 4282 EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_enter); 4283 4284 int ufshcd_uic_hibern8_exit(struct ufs_hba *hba) 4285 { 4286 struct uic_command uic_cmd = {0}; 4287 int ret; 4288 ktime_t start = ktime_get(); 4289 4290 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, PRE_CHANGE); 4291 4292 uic_cmd.command = UIC_CMD_DME_HIBER_EXIT; 4293 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd); 4294 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "exit", 4295 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 4296 4297 if (ret) { 4298 dev_err(hba->dev, "%s: hibern8 exit failed. ret = %d\n", 4299 __func__, ret); 4300 } else { 4301 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, 4302 POST_CHANGE); 4303 hba->ufs_stats.last_hibern8_exit_tstamp = local_clock(); 4304 hba->ufs_stats.hibern8_exit_cnt++; 4305 } 4306 4307 return ret; 4308 } 4309 EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_exit); 4310 4311 void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit) 4312 { 4313 unsigned long flags; 4314 bool update = false; 4315 4316 if (!ufshcd_is_auto_hibern8_supported(hba)) 4317 return; 4318 4319 spin_lock_irqsave(hba->host->host_lock, flags); 4320 if (hba->ahit != ahit) { 4321 hba->ahit = ahit; 4322 update = true; 4323 } 4324 spin_unlock_irqrestore(hba->host->host_lock, flags); 4325 4326 if (update && 4327 !pm_runtime_suspended(&hba->ufs_device_wlun->sdev_gendev)) { 4328 ufshcd_rpm_get_sync(hba); 4329 ufshcd_hold(hba); 4330 ufshcd_auto_hibern8_enable(hba); 4331 ufshcd_release(hba); 4332 ufshcd_rpm_put_sync(hba); 4333 } 4334 } 4335 EXPORT_SYMBOL_GPL(ufshcd_auto_hibern8_update); 4336 4337 void ufshcd_auto_hibern8_enable(struct ufs_hba *hba) 4338 { 4339 if (!ufshcd_is_auto_hibern8_supported(hba)) 4340 return; 4341 4342 ufshcd_writel(hba, hba->ahit, REG_AUTO_HIBERNATE_IDLE_TIMER); 4343 } 4344 4345 /** 4346 * ufshcd_init_pwr_info - setting the POR (power on reset) 4347 * values in hba power info 4348 * @hba: per-adapter instance 4349 */ 4350 static void ufshcd_init_pwr_info(struct ufs_hba *hba) 4351 { 4352 hba->pwr_info.gear_rx = UFS_PWM_G1; 4353 hba->pwr_info.gear_tx = UFS_PWM_G1; 4354 hba->pwr_info.lane_rx = UFS_LANE_1; 4355 hba->pwr_info.lane_tx = UFS_LANE_1; 4356 hba->pwr_info.pwr_rx = SLOWAUTO_MODE; 4357 hba->pwr_info.pwr_tx = SLOWAUTO_MODE; 4358 hba->pwr_info.hs_rate = 0; 4359 } 4360 4361 /** 4362 * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device 4363 * @hba: per-adapter instance 4364 * 4365 * Return: 0 upon success; < 0 upon failure. 4366 */ 4367 static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba) 4368 { 4369 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info; 4370 4371 if (hba->max_pwr_info.is_valid) 4372 return 0; 4373 4374 if (hba->quirks & UFSHCD_QUIRK_HIBERN_FASTAUTO) { 4375 pwr_info->pwr_tx = FASTAUTO_MODE; 4376 pwr_info->pwr_rx = FASTAUTO_MODE; 4377 } else { 4378 pwr_info->pwr_tx = FAST_MODE; 4379 pwr_info->pwr_rx = FAST_MODE; 4380 } 4381 pwr_info->hs_rate = PA_HS_MODE_B; 4382 4383 /* Get the connected lane count */ 4384 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES), 4385 &pwr_info->lane_rx); 4386 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 4387 &pwr_info->lane_tx); 4388 4389 if (!pwr_info->lane_rx || !pwr_info->lane_tx) { 4390 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n", 4391 __func__, 4392 pwr_info->lane_rx, 4393 pwr_info->lane_tx); 4394 return -EINVAL; 4395 } 4396 4397 /* 4398 * First, get the maximum gears of HS speed. 4399 * If a zero value, it means there is no HSGEAR capability. 4400 * Then, get the maximum gears of PWM speed. 4401 */ 4402 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx); 4403 if (!pwr_info->gear_rx) { 4404 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR), 4405 &pwr_info->gear_rx); 4406 if (!pwr_info->gear_rx) { 4407 dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n", 4408 __func__, pwr_info->gear_rx); 4409 return -EINVAL; 4410 } 4411 pwr_info->pwr_rx = SLOW_MODE; 4412 } 4413 4414 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), 4415 &pwr_info->gear_tx); 4416 if (!pwr_info->gear_tx) { 4417 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR), 4418 &pwr_info->gear_tx); 4419 if (!pwr_info->gear_tx) { 4420 dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n", 4421 __func__, pwr_info->gear_tx); 4422 return -EINVAL; 4423 } 4424 pwr_info->pwr_tx = SLOW_MODE; 4425 } 4426 4427 hba->max_pwr_info.is_valid = true; 4428 return 0; 4429 } 4430 4431 static int ufshcd_change_power_mode(struct ufs_hba *hba, 4432 struct ufs_pa_layer_attr *pwr_mode) 4433 { 4434 int ret; 4435 4436 /* if already configured to the requested pwr_mode */ 4437 if (!hba->force_pmc && 4438 pwr_mode->gear_rx == hba->pwr_info.gear_rx && 4439 pwr_mode->gear_tx == hba->pwr_info.gear_tx && 4440 pwr_mode->lane_rx == hba->pwr_info.lane_rx && 4441 pwr_mode->lane_tx == hba->pwr_info.lane_tx && 4442 pwr_mode->pwr_rx == hba->pwr_info.pwr_rx && 4443 pwr_mode->pwr_tx == hba->pwr_info.pwr_tx && 4444 pwr_mode->hs_rate == hba->pwr_info.hs_rate) { 4445 dev_dbg(hba->dev, "%s: power already configured\n", __func__); 4446 return 0; 4447 } 4448 4449 /* 4450 * Configure attributes for power mode change with below. 4451 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION, 4452 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION, 4453 * - PA_HSSERIES 4454 */ 4455 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx); 4456 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES), 4457 pwr_mode->lane_rx); 4458 if (pwr_mode->pwr_rx == FASTAUTO_MODE || 4459 pwr_mode->pwr_rx == FAST_MODE) 4460 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), true); 4461 else 4462 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), false); 4463 4464 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx); 4465 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES), 4466 pwr_mode->lane_tx); 4467 if (pwr_mode->pwr_tx == FASTAUTO_MODE || 4468 pwr_mode->pwr_tx == FAST_MODE) 4469 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), true); 4470 else 4471 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), false); 4472 4473 if (pwr_mode->pwr_rx == FASTAUTO_MODE || 4474 pwr_mode->pwr_tx == FASTAUTO_MODE || 4475 pwr_mode->pwr_rx == FAST_MODE || 4476 pwr_mode->pwr_tx == FAST_MODE) 4477 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES), 4478 pwr_mode->hs_rate); 4479 4480 if (!(hba->quirks & UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING)) { 4481 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 4482 DL_FC0ProtectionTimeOutVal_Default); 4483 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 4484 DL_TC0ReplayTimeOutVal_Default); 4485 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 4486 DL_AFC0ReqTimeOutVal_Default); 4487 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA3), 4488 DL_FC1ProtectionTimeOutVal_Default); 4489 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA4), 4490 DL_TC1ReplayTimeOutVal_Default); 4491 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA5), 4492 DL_AFC1ReqTimeOutVal_Default); 4493 4494 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalFC0ProtectionTimeOutVal), 4495 DL_FC0ProtectionTimeOutVal_Default); 4496 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalTC0ReplayTimeOutVal), 4497 DL_TC0ReplayTimeOutVal_Default); 4498 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalAFC0ReqTimeOutVal), 4499 DL_AFC0ReqTimeOutVal_Default); 4500 } 4501 4502 ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4 4503 | pwr_mode->pwr_tx); 4504 4505 if (ret) { 4506 dev_err(hba->dev, 4507 "%s: power mode change failed %d\n", __func__, ret); 4508 } else { 4509 ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL, 4510 pwr_mode); 4511 4512 memcpy(&hba->pwr_info, pwr_mode, 4513 sizeof(struct ufs_pa_layer_attr)); 4514 } 4515 4516 return ret; 4517 } 4518 4519 /** 4520 * ufshcd_config_pwr_mode - configure a new power mode 4521 * @hba: per-adapter instance 4522 * @desired_pwr_mode: desired power configuration 4523 * 4524 * Return: 0 upon success; < 0 upon failure. 4525 */ 4526 int ufshcd_config_pwr_mode(struct ufs_hba *hba, 4527 struct ufs_pa_layer_attr *desired_pwr_mode) 4528 { 4529 struct ufs_pa_layer_attr final_params = { 0 }; 4530 int ret; 4531 4532 ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE, 4533 desired_pwr_mode, &final_params); 4534 4535 if (ret) 4536 memcpy(&final_params, desired_pwr_mode, sizeof(final_params)); 4537 4538 ret = ufshcd_change_power_mode(hba, &final_params); 4539 4540 return ret; 4541 } 4542 EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode); 4543 4544 /** 4545 * ufshcd_complete_dev_init() - checks device readiness 4546 * @hba: per-adapter instance 4547 * 4548 * Set fDeviceInit flag and poll until device toggles it. 4549 * 4550 * Return: 0 upon success; < 0 upon failure. 4551 */ 4552 static int ufshcd_complete_dev_init(struct ufs_hba *hba) 4553 { 4554 int err; 4555 bool flag_res = true; 4556 ktime_t timeout; 4557 4558 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG, 4559 QUERY_FLAG_IDN_FDEVICEINIT, 0, NULL); 4560 if (err) { 4561 dev_err(hba->dev, 4562 "%s: setting fDeviceInit flag failed with error %d\n", 4563 __func__, err); 4564 goto out; 4565 } 4566 4567 /* Poll fDeviceInit flag to be cleared */ 4568 timeout = ktime_add_ms(ktime_get(), FDEVICEINIT_COMPL_TIMEOUT); 4569 do { 4570 err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_READ_FLAG, 4571 QUERY_FLAG_IDN_FDEVICEINIT, 0, &flag_res); 4572 if (!flag_res) 4573 break; 4574 usleep_range(500, 1000); 4575 } while (ktime_before(ktime_get(), timeout)); 4576 4577 if (err) { 4578 dev_err(hba->dev, 4579 "%s: reading fDeviceInit flag failed with error %d\n", 4580 __func__, err); 4581 } else if (flag_res) { 4582 dev_err(hba->dev, 4583 "%s: fDeviceInit was not cleared by the device\n", 4584 __func__); 4585 err = -EBUSY; 4586 } 4587 out: 4588 return err; 4589 } 4590 4591 /** 4592 * ufshcd_make_hba_operational - Make UFS controller operational 4593 * @hba: per adapter instance 4594 * 4595 * To bring UFS host controller to operational state, 4596 * 1. Enable required interrupts 4597 * 2. Configure interrupt aggregation 4598 * 3. Program UTRL and UTMRL base address 4599 * 4. Configure run-stop-registers 4600 * 4601 * Return: 0 on success, non-zero value on failure. 4602 */ 4603 int ufshcd_make_hba_operational(struct ufs_hba *hba) 4604 { 4605 int err = 0; 4606 u32 reg; 4607 4608 /* Enable required interrupts */ 4609 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS); 4610 4611 /* Configure interrupt aggregation */ 4612 if (ufshcd_is_intr_aggr_allowed(hba)) 4613 ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO); 4614 else 4615 ufshcd_disable_intr_aggr(hba); 4616 4617 /* Configure UTRL and UTMRL base address registers */ 4618 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr), 4619 REG_UTP_TRANSFER_REQ_LIST_BASE_L); 4620 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr), 4621 REG_UTP_TRANSFER_REQ_LIST_BASE_H); 4622 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr), 4623 REG_UTP_TASK_REQ_LIST_BASE_L); 4624 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr), 4625 REG_UTP_TASK_REQ_LIST_BASE_H); 4626 4627 /* 4628 * Make sure base address and interrupt setup are updated before 4629 * enabling the run/stop registers below. 4630 */ 4631 wmb(); 4632 4633 /* 4634 * UCRDY, UTMRLDY and UTRLRDY bits must be 1 4635 */ 4636 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS); 4637 if (!(ufshcd_get_lists_status(reg))) { 4638 ufshcd_enable_run_stop_reg(hba); 4639 } else { 4640 dev_err(hba->dev, 4641 "Host controller not ready to process requests"); 4642 err = -EIO; 4643 } 4644 4645 return err; 4646 } 4647 EXPORT_SYMBOL_GPL(ufshcd_make_hba_operational); 4648 4649 /** 4650 * ufshcd_hba_stop - Send controller to reset state 4651 * @hba: per adapter instance 4652 */ 4653 void ufshcd_hba_stop(struct ufs_hba *hba) 4654 { 4655 unsigned long flags; 4656 int err; 4657 4658 /* 4659 * Obtain the host lock to prevent that the controller is disabled 4660 * while the UFS interrupt handler is active on another CPU. 4661 */ 4662 spin_lock_irqsave(hba->host->host_lock, flags); 4663 ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE); 4664 spin_unlock_irqrestore(hba->host->host_lock, flags); 4665 4666 err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE, 4667 CONTROLLER_ENABLE, CONTROLLER_DISABLE, 4668 10, 1); 4669 if (err) 4670 dev_err(hba->dev, "%s: Controller disable failed\n", __func__); 4671 } 4672 EXPORT_SYMBOL_GPL(ufshcd_hba_stop); 4673 4674 /** 4675 * ufshcd_hba_execute_hce - initialize the controller 4676 * @hba: per adapter instance 4677 * 4678 * The controller resets itself and controller firmware initialization 4679 * sequence kicks off. When controller is ready it will set 4680 * the Host Controller Enable bit to 1. 4681 * 4682 * Return: 0 on success, non-zero value on failure. 4683 */ 4684 static int ufshcd_hba_execute_hce(struct ufs_hba *hba) 4685 { 4686 int retry_outer = 3; 4687 int retry_inner; 4688 4689 start: 4690 if (ufshcd_is_hba_active(hba)) 4691 /* change controller state to "reset state" */ 4692 ufshcd_hba_stop(hba); 4693 4694 /* UniPro link is disabled at this point */ 4695 ufshcd_set_link_off(hba); 4696 4697 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE); 4698 4699 /* start controller initialization sequence */ 4700 ufshcd_hba_start(hba); 4701 4702 /* 4703 * To initialize a UFS host controller HCE bit must be set to 1. 4704 * During initialization the HCE bit value changes from 1->0->1. 4705 * When the host controller completes initialization sequence 4706 * it sets the value of HCE bit to 1. The same HCE bit is read back 4707 * to check if the controller has completed initialization sequence. 4708 * So without this delay the value HCE = 1, set in the previous 4709 * instruction might be read back. 4710 * This delay can be changed based on the controller. 4711 */ 4712 ufshcd_delay_us(hba->vps->hba_enable_delay_us, 100); 4713 4714 /* wait for the host controller to complete initialization */ 4715 retry_inner = 50; 4716 while (!ufshcd_is_hba_active(hba)) { 4717 if (retry_inner) { 4718 retry_inner--; 4719 } else { 4720 dev_err(hba->dev, 4721 "Controller enable failed\n"); 4722 if (retry_outer) { 4723 retry_outer--; 4724 goto start; 4725 } 4726 return -EIO; 4727 } 4728 usleep_range(1000, 1100); 4729 } 4730 4731 /* enable UIC related interrupts */ 4732 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK); 4733 4734 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE); 4735 4736 return 0; 4737 } 4738 4739 int ufshcd_hba_enable(struct ufs_hba *hba) 4740 { 4741 int ret; 4742 4743 if (hba->quirks & UFSHCI_QUIRK_BROKEN_HCE) { 4744 ufshcd_set_link_off(hba); 4745 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE); 4746 4747 /* enable UIC related interrupts */ 4748 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK); 4749 ret = ufshcd_dme_reset(hba); 4750 if (ret) { 4751 dev_err(hba->dev, "DME_RESET failed\n"); 4752 return ret; 4753 } 4754 4755 ret = ufshcd_dme_enable(hba); 4756 if (ret) { 4757 dev_err(hba->dev, "Enabling DME failed\n"); 4758 return ret; 4759 } 4760 4761 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE); 4762 } else { 4763 ret = ufshcd_hba_execute_hce(hba); 4764 } 4765 4766 return ret; 4767 } 4768 EXPORT_SYMBOL_GPL(ufshcd_hba_enable); 4769 4770 static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer) 4771 { 4772 int tx_lanes = 0, i, err = 0; 4773 4774 if (!peer) 4775 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 4776 &tx_lanes); 4777 else 4778 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 4779 &tx_lanes); 4780 for (i = 0; i < tx_lanes; i++) { 4781 if (!peer) 4782 err = ufshcd_dme_set(hba, 4783 UIC_ARG_MIB_SEL(TX_LCC_ENABLE, 4784 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)), 4785 0); 4786 else 4787 err = ufshcd_dme_peer_set(hba, 4788 UIC_ARG_MIB_SEL(TX_LCC_ENABLE, 4789 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)), 4790 0); 4791 if (err) { 4792 dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d", 4793 __func__, peer, i, err); 4794 break; 4795 } 4796 } 4797 4798 return err; 4799 } 4800 4801 static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba) 4802 { 4803 return ufshcd_disable_tx_lcc(hba, true); 4804 } 4805 4806 void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val) 4807 { 4808 struct ufs_event_hist *e; 4809 4810 if (id >= UFS_EVT_CNT) 4811 return; 4812 4813 e = &hba->ufs_stats.event[id]; 4814 e->val[e->pos] = val; 4815 e->tstamp[e->pos] = local_clock(); 4816 e->cnt += 1; 4817 e->pos = (e->pos + 1) % UFS_EVENT_HIST_LENGTH; 4818 4819 ufshcd_vops_event_notify(hba, id, &val); 4820 } 4821 EXPORT_SYMBOL_GPL(ufshcd_update_evt_hist); 4822 4823 /** 4824 * ufshcd_link_startup - Initialize unipro link startup 4825 * @hba: per adapter instance 4826 * 4827 * Return: 0 for success, non-zero in case of failure. 4828 */ 4829 static int ufshcd_link_startup(struct ufs_hba *hba) 4830 { 4831 int ret; 4832 int retries = DME_LINKSTARTUP_RETRIES; 4833 bool link_startup_again = false; 4834 4835 /* 4836 * If UFS device isn't active then we will have to issue link startup 4837 * 2 times to make sure the device state move to active. 4838 */ 4839 if (!ufshcd_is_ufs_dev_active(hba)) 4840 link_startup_again = true; 4841 4842 link_startup: 4843 do { 4844 ufshcd_vops_link_startup_notify(hba, PRE_CHANGE); 4845 4846 ret = ufshcd_dme_link_startup(hba); 4847 4848 /* check if device is detected by inter-connect layer */ 4849 if (!ret && !ufshcd_is_device_present(hba)) { 4850 ufshcd_update_evt_hist(hba, 4851 UFS_EVT_LINK_STARTUP_FAIL, 4852 0); 4853 dev_err(hba->dev, "%s: Device not present\n", __func__); 4854 ret = -ENXIO; 4855 goto out; 4856 } 4857 4858 /* 4859 * DME link lost indication is only received when link is up, 4860 * but we can't be sure if the link is up until link startup 4861 * succeeds. So reset the local Uni-Pro and try again. 4862 */ 4863 if (ret && retries && ufshcd_hba_enable(hba)) { 4864 ufshcd_update_evt_hist(hba, 4865 UFS_EVT_LINK_STARTUP_FAIL, 4866 (u32)ret); 4867 goto out; 4868 } 4869 } while (ret && retries--); 4870 4871 if (ret) { 4872 /* failed to get the link up... retire */ 4873 ufshcd_update_evt_hist(hba, 4874 UFS_EVT_LINK_STARTUP_FAIL, 4875 (u32)ret); 4876 goto out; 4877 } 4878 4879 if (link_startup_again) { 4880 link_startup_again = false; 4881 retries = DME_LINKSTARTUP_RETRIES; 4882 goto link_startup; 4883 } 4884 4885 /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */ 4886 ufshcd_init_pwr_info(hba); 4887 ufshcd_print_pwr_info(hba); 4888 4889 if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) { 4890 ret = ufshcd_disable_device_tx_lcc(hba); 4891 if (ret) 4892 goto out; 4893 } 4894 4895 /* Include any host controller configuration via UIC commands */ 4896 ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE); 4897 if (ret) 4898 goto out; 4899 4900 /* Clear UECPA once due to LINERESET has happened during LINK_STARTUP */ 4901 ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER); 4902 ret = ufshcd_make_hba_operational(hba); 4903 out: 4904 if (ret) { 4905 dev_err(hba->dev, "link startup failed %d\n", ret); 4906 ufshcd_print_host_state(hba); 4907 ufshcd_print_pwr_info(hba); 4908 ufshcd_print_evt_hist(hba); 4909 } 4910 return ret; 4911 } 4912 4913 /** 4914 * ufshcd_verify_dev_init() - Verify device initialization 4915 * @hba: per-adapter instance 4916 * 4917 * Send NOP OUT UPIU and wait for NOP IN response to check whether the 4918 * device Transport Protocol (UTP) layer is ready after a reset. 4919 * If the UTP layer at the device side is not initialized, it may 4920 * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT 4921 * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations. 4922 * 4923 * Return: 0 upon success; < 0 upon failure. 4924 */ 4925 static int ufshcd_verify_dev_init(struct ufs_hba *hba) 4926 { 4927 int err = 0; 4928 int retries; 4929 4930 ufshcd_hold(hba); 4931 mutex_lock(&hba->dev_cmd.lock); 4932 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) { 4933 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP, 4934 hba->nop_out_timeout); 4935 4936 if (!err || err == -ETIMEDOUT) 4937 break; 4938 4939 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err); 4940 } 4941 mutex_unlock(&hba->dev_cmd.lock); 4942 ufshcd_release(hba); 4943 4944 if (err) 4945 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err); 4946 return err; 4947 } 4948 4949 /** 4950 * ufshcd_setup_links - associate link b/w device wlun and other luns 4951 * @sdev: pointer to SCSI device 4952 * @hba: pointer to ufs hba 4953 */ 4954 static void ufshcd_setup_links(struct ufs_hba *hba, struct scsi_device *sdev) 4955 { 4956 struct device_link *link; 4957 4958 /* 4959 * Device wlun is the supplier & rest of the luns are consumers. 4960 * This ensures that device wlun suspends after all other luns. 4961 */ 4962 if (hba->ufs_device_wlun) { 4963 link = device_link_add(&sdev->sdev_gendev, 4964 &hba->ufs_device_wlun->sdev_gendev, 4965 DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE); 4966 if (!link) { 4967 dev_err(&sdev->sdev_gendev, "Failed establishing link - %s\n", 4968 dev_name(&hba->ufs_device_wlun->sdev_gendev)); 4969 return; 4970 } 4971 hba->luns_avail--; 4972 /* Ignore REPORT_LUN wlun probing */ 4973 if (hba->luns_avail == 1) { 4974 ufshcd_rpm_put(hba); 4975 return; 4976 } 4977 } else { 4978 /* 4979 * Device wlun is probed. The assumption is that WLUNs are 4980 * scanned before other LUNs. 4981 */ 4982 hba->luns_avail--; 4983 } 4984 } 4985 4986 /** 4987 * ufshcd_lu_init - Initialize the relevant parameters of the LU 4988 * @hba: per-adapter instance 4989 * @sdev: pointer to SCSI device 4990 */ 4991 static void ufshcd_lu_init(struct ufs_hba *hba, struct scsi_device *sdev) 4992 { 4993 int len = QUERY_DESC_MAX_SIZE; 4994 u8 lun = ufshcd_scsi_to_upiu_lun(sdev->lun); 4995 u8 lun_qdepth = hba->nutrs; 4996 u8 *desc_buf; 4997 int ret; 4998 4999 desc_buf = kzalloc(len, GFP_KERNEL); 5000 if (!desc_buf) 5001 goto set_qdepth; 5002 5003 ret = ufshcd_read_unit_desc_param(hba, lun, 0, desc_buf, len); 5004 if (ret < 0) { 5005 if (ret == -EOPNOTSUPP) 5006 /* If LU doesn't support unit descriptor, its queue depth is set to 1 */ 5007 lun_qdepth = 1; 5008 kfree(desc_buf); 5009 goto set_qdepth; 5010 } 5011 5012 if (desc_buf[UNIT_DESC_PARAM_LU_Q_DEPTH]) { 5013 /* 5014 * In per-LU queueing architecture, bLUQueueDepth will not be 0, then we will 5015 * use the smaller between UFSHCI CAP.NUTRS and UFS LU bLUQueueDepth 5016 */ 5017 lun_qdepth = min_t(int, desc_buf[UNIT_DESC_PARAM_LU_Q_DEPTH], hba->nutrs); 5018 } 5019 /* 5020 * According to UFS device specification, the write protection mode is only supported by 5021 * normal LU, not supported by WLUN. 5022 */ 5023 if (hba->dev_info.f_power_on_wp_en && lun < hba->dev_info.max_lu_supported && 5024 !hba->dev_info.is_lu_power_on_wp && 5025 desc_buf[UNIT_DESC_PARAM_LU_WR_PROTECT] == UFS_LU_POWER_ON_WP) 5026 hba->dev_info.is_lu_power_on_wp = true; 5027 5028 /* In case of RPMB LU, check if advanced RPMB mode is enabled */ 5029 if (desc_buf[UNIT_DESC_PARAM_UNIT_INDEX] == UFS_UPIU_RPMB_WLUN && 5030 desc_buf[RPMB_UNIT_DESC_PARAM_REGION_EN] & BIT(4)) 5031 hba->dev_info.b_advanced_rpmb_en = true; 5032 5033 5034 kfree(desc_buf); 5035 set_qdepth: 5036 /* 5037 * For WLUNs that don't support unit descriptor, queue depth is set to 1. For LUs whose 5038 * bLUQueueDepth == 0, the queue depth is set to a maximum value that host can queue. 5039 */ 5040 dev_dbg(hba->dev, "Set LU %x queue depth %d\n", lun, lun_qdepth); 5041 scsi_change_queue_depth(sdev, lun_qdepth); 5042 } 5043 5044 /** 5045 * ufshcd_slave_alloc - handle initial SCSI device configurations 5046 * @sdev: pointer to SCSI device 5047 * 5048 * Return: success. 5049 */ 5050 static int ufshcd_slave_alloc(struct scsi_device *sdev) 5051 { 5052 struct ufs_hba *hba; 5053 5054 hba = shost_priv(sdev->host); 5055 5056 /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */ 5057 sdev->use_10_for_ms = 1; 5058 5059 /* DBD field should be set to 1 in mode sense(10) */ 5060 sdev->set_dbd_for_ms = 1; 5061 5062 /* allow SCSI layer to restart the device in case of errors */ 5063 sdev->allow_restart = 1; 5064 5065 /* REPORT SUPPORTED OPERATION CODES is not supported */ 5066 sdev->no_report_opcodes = 1; 5067 5068 /* WRITE_SAME command is not supported */ 5069 sdev->no_write_same = 1; 5070 5071 ufshcd_lu_init(hba, sdev); 5072 5073 ufshcd_setup_links(hba, sdev); 5074 5075 return 0; 5076 } 5077 5078 /** 5079 * ufshcd_change_queue_depth - change queue depth 5080 * @sdev: pointer to SCSI device 5081 * @depth: required depth to set 5082 * 5083 * Change queue depth and make sure the max. limits are not crossed. 5084 * 5085 * Return: new queue depth. 5086 */ 5087 static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth) 5088 { 5089 return scsi_change_queue_depth(sdev, min(depth, sdev->host->can_queue)); 5090 } 5091 5092 /** 5093 * ufshcd_slave_configure - adjust SCSI device configurations 5094 * @sdev: pointer to SCSI device 5095 * 5096 * Return: 0 (success). 5097 */ 5098 static int ufshcd_slave_configure(struct scsi_device *sdev) 5099 { 5100 struct ufs_hba *hba = shost_priv(sdev->host); 5101 struct request_queue *q = sdev->request_queue; 5102 5103 blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1); 5104 if (hba->quirks & UFSHCD_QUIRK_4KB_DMA_ALIGNMENT) 5105 blk_queue_update_dma_alignment(q, SZ_4K - 1); 5106 /* 5107 * Block runtime-pm until all consumers are added. 5108 * Refer ufshcd_setup_links(). 5109 */ 5110 if (is_device_wlun(sdev)) 5111 pm_runtime_get_noresume(&sdev->sdev_gendev); 5112 else if (ufshcd_is_rpm_autosuspend_allowed(hba)) 5113 sdev->rpm_autosuspend = 1; 5114 /* 5115 * Do not print messages during runtime PM to avoid never-ending cycles 5116 * of messages written back to storage by user space causing runtime 5117 * resume, causing more messages and so on. 5118 */ 5119 sdev->silence_suspend = 1; 5120 5121 ufshcd_crypto_register(hba, q); 5122 5123 return 0; 5124 } 5125 5126 /** 5127 * ufshcd_slave_destroy - remove SCSI device configurations 5128 * @sdev: pointer to SCSI device 5129 */ 5130 static void ufshcd_slave_destroy(struct scsi_device *sdev) 5131 { 5132 struct ufs_hba *hba; 5133 unsigned long flags; 5134 5135 hba = shost_priv(sdev->host); 5136 5137 /* Drop the reference as it won't be needed anymore */ 5138 if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) { 5139 spin_lock_irqsave(hba->host->host_lock, flags); 5140 hba->ufs_device_wlun = NULL; 5141 spin_unlock_irqrestore(hba->host->host_lock, flags); 5142 } else if (hba->ufs_device_wlun) { 5143 struct device *supplier = NULL; 5144 5145 /* Ensure UFS Device WLUN exists and does not disappear */ 5146 spin_lock_irqsave(hba->host->host_lock, flags); 5147 if (hba->ufs_device_wlun) { 5148 supplier = &hba->ufs_device_wlun->sdev_gendev; 5149 get_device(supplier); 5150 } 5151 spin_unlock_irqrestore(hba->host->host_lock, flags); 5152 5153 if (supplier) { 5154 /* 5155 * If a LUN fails to probe (e.g. absent BOOT WLUN), the 5156 * device will not have been registered but can still 5157 * have a device link holding a reference to the device. 5158 */ 5159 device_link_remove(&sdev->sdev_gendev, supplier); 5160 put_device(supplier); 5161 } 5162 } 5163 } 5164 5165 /** 5166 * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status 5167 * @lrbp: pointer to local reference block of completed command 5168 * @scsi_status: SCSI command status 5169 * 5170 * Return: value base on SCSI command status. 5171 */ 5172 static inline int 5173 ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status) 5174 { 5175 int result = 0; 5176 5177 switch (scsi_status) { 5178 case SAM_STAT_CHECK_CONDITION: 5179 ufshcd_copy_sense_data(lrbp); 5180 fallthrough; 5181 case SAM_STAT_GOOD: 5182 result |= DID_OK << 16 | scsi_status; 5183 break; 5184 case SAM_STAT_TASK_SET_FULL: 5185 case SAM_STAT_BUSY: 5186 case SAM_STAT_TASK_ABORTED: 5187 ufshcd_copy_sense_data(lrbp); 5188 result |= scsi_status; 5189 break; 5190 default: 5191 result |= DID_ERROR << 16; 5192 break; 5193 } /* end of switch */ 5194 5195 return result; 5196 } 5197 5198 /** 5199 * ufshcd_transfer_rsp_status - Get overall status of the response 5200 * @hba: per adapter instance 5201 * @lrbp: pointer to local reference block of completed command 5202 * @cqe: pointer to the completion queue entry 5203 * 5204 * Return: result of the command to notify SCSI midlayer. 5205 */ 5206 static inline int 5207 ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, 5208 struct cq_entry *cqe) 5209 { 5210 int result = 0; 5211 int scsi_status; 5212 enum utp_ocs ocs; 5213 u8 upiu_flags; 5214 u32 resid; 5215 5216 upiu_flags = lrbp->ucd_rsp_ptr->header.flags; 5217 resid = be32_to_cpu(lrbp->ucd_rsp_ptr->sr.residual_transfer_count); 5218 /* 5219 * Test !overflow instead of underflow to support UFS devices that do 5220 * not set either flag. 5221 */ 5222 if (resid && !(upiu_flags & UPIU_RSP_FLAG_OVERFLOW)) 5223 scsi_set_resid(lrbp->cmd, resid); 5224 5225 /* overall command status of utrd */ 5226 ocs = ufshcd_get_tr_ocs(lrbp, cqe); 5227 5228 if (hba->quirks & UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR) { 5229 if (lrbp->ucd_rsp_ptr->header.response || 5230 lrbp->ucd_rsp_ptr->header.status) 5231 ocs = OCS_SUCCESS; 5232 } 5233 5234 switch (ocs) { 5235 case OCS_SUCCESS: 5236 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0); 5237 switch (ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr)) { 5238 case UPIU_TRANSACTION_RESPONSE: 5239 /* 5240 * get the result based on SCSI status response 5241 * to notify the SCSI midlayer of the command status 5242 */ 5243 scsi_status = lrbp->ucd_rsp_ptr->header.status; 5244 result = ufshcd_scsi_cmd_status(lrbp, scsi_status); 5245 5246 /* 5247 * Currently we are only supporting BKOPs exception 5248 * events hence we can ignore BKOPs exception event 5249 * during power management callbacks. BKOPs exception 5250 * event is not expected to be raised in runtime suspend 5251 * callback as it allows the urgent bkops. 5252 * During system suspend, we are anyway forcefully 5253 * disabling the bkops and if urgent bkops is needed 5254 * it will be enabled on system resume. Long term 5255 * solution could be to abort the system suspend if 5256 * UFS device needs urgent BKOPs. 5257 */ 5258 if (!hba->pm_op_in_progress && 5259 !ufshcd_eh_in_progress(hba) && 5260 ufshcd_is_exception_event(lrbp->ucd_rsp_ptr)) 5261 /* Flushed in suspend */ 5262 schedule_work(&hba->eeh_work); 5263 break; 5264 case UPIU_TRANSACTION_REJECT_UPIU: 5265 /* TODO: handle Reject UPIU Response */ 5266 result = DID_ERROR << 16; 5267 dev_err(hba->dev, 5268 "Reject UPIU not fully implemented\n"); 5269 break; 5270 default: 5271 dev_err(hba->dev, 5272 "Unexpected request response code = %x\n", 5273 result); 5274 result = DID_ERROR << 16; 5275 break; 5276 } 5277 break; 5278 case OCS_ABORTED: 5279 result |= DID_ABORT << 16; 5280 break; 5281 case OCS_INVALID_COMMAND_STATUS: 5282 result |= DID_REQUEUE << 16; 5283 break; 5284 case OCS_INVALID_CMD_TABLE_ATTR: 5285 case OCS_INVALID_PRDT_ATTR: 5286 case OCS_MISMATCH_DATA_BUF_SIZE: 5287 case OCS_MISMATCH_RESP_UPIU_SIZE: 5288 case OCS_PEER_COMM_FAILURE: 5289 case OCS_FATAL_ERROR: 5290 case OCS_DEVICE_FATAL_ERROR: 5291 case OCS_INVALID_CRYPTO_CONFIG: 5292 case OCS_GENERAL_CRYPTO_ERROR: 5293 default: 5294 result |= DID_ERROR << 16; 5295 dev_err(hba->dev, 5296 "OCS error from controller = %x for tag %d\n", 5297 ocs, lrbp->task_tag); 5298 ufshcd_print_evt_hist(hba); 5299 ufshcd_print_host_state(hba); 5300 break; 5301 } /* end of switch */ 5302 5303 if ((host_byte(result) != DID_OK) && 5304 (host_byte(result) != DID_REQUEUE) && !hba->silence_err_logs) 5305 ufshcd_print_tr(hba, lrbp->task_tag, true); 5306 return result; 5307 } 5308 5309 static bool ufshcd_is_auto_hibern8_error(struct ufs_hba *hba, 5310 u32 intr_mask) 5311 { 5312 if (!ufshcd_is_auto_hibern8_supported(hba) || 5313 !ufshcd_is_auto_hibern8_enabled(hba)) 5314 return false; 5315 5316 if (!(intr_mask & UFSHCD_UIC_HIBERN8_MASK)) 5317 return false; 5318 5319 if (hba->active_uic_cmd && 5320 (hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_ENTER || 5321 hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_EXIT)) 5322 return false; 5323 5324 return true; 5325 } 5326 5327 /** 5328 * ufshcd_uic_cmd_compl - handle completion of uic command 5329 * @hba: per adapter instance 5330 * @intr_status: interrupt status generated by the controller 5331 * 5332 * Return: 5333 * IRQ_HANDLED - If interrupt is valid 5334 * IRQ_NONE - If invalid interrupt 5335 */ 5336 static irqreturn_t ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status) 5337 { 5338 irqreturn_t retval = IRQ_NONE; 5339 5340 spin_lock(hba->host->host_lock); 5341 if (ufshcd_is_auto_hibern8_error(hba, intr_status)) 5342 hba->errors |= (UFSHCD_UIC_HIBERN8_MASK & intr_status); 5343 5344 if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) { 5345 hba->active_uic_cmd->argument2 |= 5346 ufshcd_get_uic_cmd_result(hba); 5347 hba->active_uic_cmd->argument3 = 5348 ufshcd_get_dme_attr_val(hba); 5349 if (!hba->uic_async_done) 5350 hba->active_uic_cmd->cmd_active = 0; 5351 complete(&hba->active_uic_cmd->done); 5352 retval = IRQ_HANDLED; 5353 } 5354 5355 if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done) { 5356 hba->active_uic_cmd->cmd_active = 0; 5357 complete(hba->uic_async_done); 5358 retval = IRQ_HANDLED; 5359 } 5360 5361 if (retval == IRQ_HANDLED) 5362 ufshcd_add_uic_command_trace(hba, hba->active_uic_cmd, 5363 UFS_CMD_COMP); 5364 spin_unlock(hba->host->host_lock); 5365 return retval; 5366 } 5367 5368 /* Release the resources allocated for processing a SCSI command. */ 5369 void ufshcd_release_scsi_cmd(struct ufs_hba *hba, 5370 struct ufshcd_lrb *lrbp) 5371 { 5372 struct scsi_cmnd *cmd = lrbp->cmd; 5373 5374 scsi_dma_unmap(cmd); 5375 ufshcd_release(hba); 5376 ufshcd_clk_scaling_update_busy(hba); 5377 } 5378 5379 /** 5380 * ufshcd_compl_one_cqe - handle a completion queue entry 5381 * @hba: per adapter instance 5382 * @task_tag: the task tag of the request to be completed 5383 * @cqe: pointer to the completion queue entry 5384 */ 5385 void ufshcd_compl_one_cqe(struct ufs_hba *hba, int task_tag, 5386 struct cq_entry *cqe) 5387 { 5388 struct ufshcd_lrb *lrbp; 5389 struct scsi_cmnd *cmd; 5390 enum utp_ocs ocs; 5391 5392 lrbp = &hba->lrb[task_tag]; 5393 lrbp->compl_time_stamp = ktime_get(); 5394 cmd = lrbp->cmd; 5395 if (cmd) { 5396 if (unlikely(ufshcd_should_inform_monitor(hba, lrbp))) 5397 ufshcd_update_monitor(hba, lrbp); 5398 ufshcd_add_command_trace(hba, task_tag, UFS_CMD_COMP); 5399 cmd->result = ufshcd_transfer_rsp_status(hba, lrbp, cqe); 5400 ufshcd_release_scsi_cmd(hba, lrbp); 5401 /* Do not touch lrbp after scsi done */ 5402 scsi_done(cmd); 5403 } else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE || 5404 lrbp->command_type == UTP_CMD_TYPE_UFS_STORAGE) { 5405 if (hba->dev_cmd.complete) { 5406 if (cqe) { 5407 ocs = le32_to_cpu(cqe->status) & MASK_OCS; 5408 lrbp->utr_descriptor_ptr->header.ocs = ocs; 5409 } 5410 complete(hba->dev_cmd.complete); 5411 ufshcd_clk_scaling_update_busy(hba); 5412 } 5413 } 5414 } 5415 5416 /** 5417 * __ufshcd_transfer_req_compl - handle SCSI and query command completion 5418 * @hba: per adapter instance 5419 * @completed_reqs: bitmask that indicates which requests to complete 5420 */ 5421 static void __ufshcd_transfer_req_compl(struct ufs_hba *hba, 5422 unsigned long completed_reqs) 5423 { 5424 int tag; 5425 5426 for_each_set_bit(tag, &completed_reqs, hba->nutrs) 5427 ufshcd_compl_one_cqe(hba, tag, NULL); 5428 } 5429 5430 /* Any value that is not an existing queue number is fine for this constant. */ 5431 enum { 5432 UFSHCD_POLL_FROM_INTERRUPT_CONTEXT = -1 5433 }; 5434 5435 static void ufshcd_clear_polled(struct ufs_hba *hba, 5436 unsigned long *completed_reqs) 5437 { 5438 int tag; 5439 5440 for_each_set_bit(tag, completed_reqs, hba->nutrs) { 5441 struct scsi_cmnd *cmd = hba->lrb[tag].cmd; 5442 5443 if (!cmd) 5444 continue; 5445 if (scsi_cmd_to_rq(cmd)->cmd_flags & REQ_POLLED) 5446 __clear_bit(tag, completed_reqs); 5447 } 5448 } 5449 5450 /* 5451 * Return: > 0 if one or more commands have been completed or 0 if no 5452 * requests have been completed. 5453 */ 5454 static int ufshcd_poll(struct Scsi_Host *shost, unsigned int queue_num) 5455 { 5456 struct ufs_hba *hba = shost_priv(shost); 5457 unsigned long completed_reqs, flags; 5458 u32 tr_doorbell; 5459 struct ufs_hw_queue *hwq; 5460 5461 if (is_mcq_enabled(hba)) { 5462 hwq = &hba->uhq[queue_num]; 5463 5464 return ufshcd_mcq_poll_cqe_lock(hba, hwq); 5465 } 5466 5467 spin_lock_irqsave(&hba->outstanding_lock, flags); 5468 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 5469 completed_reqs = ~tr_doorbell & hba->outstanding_reqs; 5470 WARN_ONCE(completed_reqs & ~hba->outstanding_reqs, 5471 "completed: %#lx; outstanding: %#lx\n", completed_reqs, 5472 hba->outstanding_reqs); 5473 if (queue_num == UFSHCD_POLL_FROM_INTERRUPT_CONTEXT) { 5474 /* Do not complete polled requests from interrupt context. */ 5475 ufshcd_clear_polled(hba, &completed_reqs); 5476 } 5477 hba->outstanding_reqs &= ~completed_reqs; 5478 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 5479 5480 if (completed_reqs) 5481 __ufshcd_transfer_req_compl(hba, completed_reqs); 5482 5483 return completed_reqs != 0; 5484 } 5485 5486 /** 5487 * ufshcd_mcq_compl_pending_transfer - MCQ mode function. It is 5488 * invoked from the error handler context or ufshcd_host_reset_and_restore() 5489 * to complete the pending transfers and free the resources associated with 5490 * the scsi command. 5491 * 5492 * @hba: per adapter instance 5493 * @force_compl: This flag is set to true when invoked 5494 * from ufshcd_host_reset_and_restore() in which case it requires special 5495 * handling because the host controller has been reset by ufshcd_hba_stop(). 5496 */ 5497 static void ufshcd_mcq_compl_pending_transfer(struct ufs_hba *hba, 5498 bool force_compl) 5499 { 5500 struct ufs_hw_queue *hwq; 5501 struct ufshcd_lrb *lrbp; 5502 struct scsi_cmnd *cmd; 5503 unsigned long flags; 5504 u32 hwq_num, utag; 5505 int tag; 5506 5507 for (tag = 0; tag < hba->nutrs; tag++) { 5508 lrbp = &hba->lrb[tag]; 5509 cmd = lrbp->cmd; 5510 if (!ufshcd_cmd_inflight(cmd) || 5511 test_bit(SCMD_STATE_COMPLETE, &cmd->state)) 5512 continue; 5513 5514 utag = blk_mq_unique_tag(scsi_cmd_to_rq(cmd)); 5515 hwq_num = blk_mq_unique_tag_to_hwq(utag); 5516 hwq = &hba->uhq[hwq_num]; 5517 5518 if (force_compl) { 5519 ufshcd_mcq_compl_all_cqes_lock(hba, hwq); 5520 /* 5521 * For those cmds of which the cqes are not present 5522 * in the cq, complete them explicitly. 5523 */ 5524 if (cmd && !test_bit(SCMD_STATE_COMPLETE, &cmd->state)) { 5525 spin_lock_irqsave(&hwq->cq_lock, flags); 5526 set_host_byte(cmd, DID_REQUEUE); 5527 ufshcd_release_scsi_cmd(hba, lrbp); 5528 scsi_done(cmd); 5529 spin_unlock_irqrestore(&hwq->cq_lock, flags); 5530 } 5531 } else { 5532 ufshcd_mcq_poll_cqe_lock(hba, hwq); 5533 } 5534 } 5535 } 5536 5537 /** 5538 * ufshcd_transfer_req_compl - handle SCSI and query command completion 5539 * @hba: per adapter instance 5540 * 5541 * Return: 5542 * IRQ_HANDLED - If interrupt is valid 5543 * IRQ_NONE - If invalid interrupt 5544 */ 5545 static irqreturn_t ufshcd_transfer_req_compl(struct ufs_hba *hba) 5546 { 5547 /* Resetting interrupt aggregation counters first and reading the 5548 * DOOR_BELL afterward allows us to handle all the completed requests. 5549 * In order to prevent other interrupts starvation the DB is read once 5550 * after reset. The down side of this solution is the possibility of 5551 * false interrupt if device completes another request after resetting 5552 * aggregation and before reading the DB. 5553 */ 5554 if (ufshcd_is_intr_aggr_allowed(hba) && 5555 !(hba->quirks & UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR)) 5556 ufshcd_reset_intr_aggr(hba); 5557 5558 if (ufs_fail_completion()) 5559 return IRQ_HANDLED; 5560 5561 /* 5562 * Ignore the ufshcd_poll() return value and return IRQ_HANDLED since we 5563 * do not want polling to trigger spurious interrupt complaints. 5564 */ 5565 ufshcd_poll(hba->host, UFSHCD_POLL_FROM_INTERRUPT_CONTEXT); 5566 5567 return IRQ_HANDLED; 5568 } 5569 5570 int __ufshcd_write_ee_control(struct ufs_hba *hba, u32 ee_ctrl_mask) 5571 { 5572 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, 5573 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, 5574 &ee_ctrl_mask); 5575 } 5576 5577 int ufshcd_write_ee_control(struct ufs_hba *hba) 5578 { 5579 int err; 5580 5581 mutex_lock(&hba->ee_ctrl_mutex); 5582 err = __ufshcd_write_ee_control(hba, hba->ee_ctrl_mask); 5583 mutex_unlock(&hba->ee_ctrl_mutex); 5584 if (err) 5585 dev_err(hba->dev, "%s: failed to write ee control %d\n", 5586 __func__, err); 5587 return err; 5588 } 5589 5590 int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask, 5591 const u16 *other_mask, u16 set, u16 clr) 5592 { 5593 u16 new_mask, ee_ctrl_mask; 5594 int err = 0; 5595 5596 mutex_lock(&hba->ee_ctrl_mutex); 5597 new_mask = (*mask & ~clr) | set; 5598 ee_ctrl_mask = new_mask | *other_mask; 5599 if (ee_ctrl_mask != hba->ee_ctrl_mask) 5600 err = __ufshcd_write_ee_control(hba, ee_ctrl_mask); 5601 /* Still need to update 'mask' even if 'ee_ctrl_mask' was unchanged */ 5602 if (!err) { 5603 hba->ee_ctrl_mask = ee_ctrl_mask; 5604 *mask = new_mask; 5605 } 5606 mutex_unlock(&hba->ee_ctrl_mutex); 5607 return err; 5608 } 5609 5610 /** 5611 * ufshcd_disable_ee - disable exception event 5612 * @hba: per-adapter instance 5613 * @mask: exception event to disable 5614 * 5615 * Disables exception event in the device so that the EVENT_ALERT 5616 * bit is not set. 5617 * 5618 * Return: zero on success, non-zero error value on failure. 5619 */ 5620 static inline int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask) 5621 { 5622 return ufshcd_update_ee_drv_mask(hba, 0, mask); 5623 } 5624 5625 /** 5626 * ufshcd_enable_ee - enable exception event 5627 * @hba: per-adapter instance 5628 * @mask: exception event to enable 5629 * 5630 * Enable corresponding exception event in the device to allow 5631 * device to alert host in critical scenarios. 5632 * 5633 * Return: zero on success, non-zero error value on failure. 5634 */ 5635 static inline int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask) 5636 { 5637 return ufshcd_update_ee_drv_mask(hba, mask, 0); 5638 } 5639 5640 /** 5641 * ufshcd_enable_auto_bkops - Allow device managed BKOPS 5642 * @hba: per-adapter instance 5643 * 5644 * Allow device to manage background operations on its own. Enabling 5645 * this might lead to inconsistent latencies during normal data transfers 5646 * as the device is allowed to manage its own way of handling background 5647 * operations. 5648 * 5649 * Return: zero on success, non-zero on failure. 5650 */ 5651 static int ufshcd_enable_auto_bkops(struct ufs_hba *hba) 5652 { 5653 int err = 0; 5654 5655 if (hba->auto_bkops_enabled) 5656 goto out; 5657 5658 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG, 5659 QUERY_FLAG_IDN_BKOPS_EN, 0, NULL); 5660 if (err) { 5661 dev_err(hba->dev, "%s: failed to enable bkops %d\n", 5662 __func__, err); 5663 goto out; 5664 } 5665 5666 hba->auto_bkops_enabled = true; 5667 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Enabled"); 5668 5669 /* No need of URGENT_BKOPS exception from the device */ 5670 err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS); 5671 if (err) 5672 dev_err(hba->dev, "%s: failed to disable exception event %d\n", 5673 __func__, err); 5674 out: 5675 return err; 5676 } 5677 5678 /** 5679 * ufshcd_disable_auto_bkops - block device in doing background operations 5680 * @hba: per-adapter instance 5681 * 5682 * Disabling background operations improves command response latency but 5683 * has drawback of device moving into critical state where the device is 5684 * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the 5685 * host is idle so that BKOPS are managed effectively without any negative 5686 * impacts. 5687 * 5688 * Return: zero on success, non-zero on failure. 5689 */ 5690 static int ufshcd_disable_auto_bkops(struct ufs_hba *hba) 5691 { 5692 int err = 0; 5693 5694 if (!hba->auto_bkops_enabled) 5695 goto out; 5696 5697 /* 5698 * If host assisted BKOPs is to be enabled, make sure 5699 * urgent bkops exception is allowed. 5700 */ 5701 err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS); 5702 if (err) { 5703 dev_err(hba->dev, "%s: failed to enable exception event %d\n", 5704 __func__, err); 5705 goto out; 5706 } 5707 5708 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG, 5709 QUERY_FLAG_IDN_BKOPS_EN, 0, NULL); 5710 if (err) { 5711 dev_err(hba->dev, "%s: failed to disable bkops %d\n", 5712 __func__, err); 5713 ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS); 5714 goto out; 5715 } 5716 5717 hba->auto_bkops_enabled = false; 5718 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Disabled"); 5719 hba->is_urgent_bkops_lvl_checked = false; 5720 out: 5721 return err; 5722 } 5723 5724 /** 5725 * ufshcd_force_reset_auto_bkops - force reset auto bkops state 5726 * @hba: per adapter instance 5727 * 5728 * After a device reset the device may toggle the BKOPS_EN flag 5729 * to default value. The s/w tracking variables should be updated 5730 * as well. This function would change the auto-bkops state based on 5731 * UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND. 5732 */ 5733 static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba) 5734 { 5735 if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) { 5736 hba->auto_bkops_enabled = false; 5737 hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS; 5738 ufshcd_enable_auto_bkops(hba); 5739 } else { 5740 hba->auto_bkops_enabled = true; 5741 hba->ee_ctrl_mask &= ~MASK_EE_URGENT_BKOPS; 5742 ufshcd_disable_auto_bkops(hba); 5743 } 5744 hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT; 5745 hba->is_urgent_bkops_lvl_checked = false; 5746 } 5747 5748 static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status) 5749 { 5750 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 5751 QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status); 5752 } 5753 5754 /** 5755 * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status 5756 * @hba: per-adapter instance 5757 * @status: bkops_status value 5758 * 5759 * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn 5760 * flag in the device to permit background operations if the device 5761 * bkops_status is greater than or equal to "status" argument passed to 5762 * this function, disable otherwise. 5763 * 5764 * Return: 0 for success, non-zero in case of failure. 5765 * 5766 * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag 5767 * to know whether auto bkops is enabled or disabled after this function 5768 * returns control to it. 5769 */ 5770 static int ufshcd_bkops_ctrl(struct ufs_hba *hba, 5771 enum bkops_status status) 5772 { 5773 int err; 5774 u32 curr_status = 0; 5775 5776 err = ufshcd_get_bkops_status(hba, &curr_status); 5777 if (err) { 5778 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n", 5779 __func__, err); 5780 goto out; 5781 } else if (curr_status > BKOPS_STATUS_MAX) { 5782 dev_err(hba->dev, "%s: invalid BKOPS status %d\n", 5783 __func__, curr_status); 5784 err = -EINVAL; 5785 goto out; 5786 } 5787 5788 if (curr_status >= status) 5789 err = ufshcd_enable_auto_bkops(hba); 5790 else 5791 err = ufshcd_disable_auto_bkops(hba); 5792 out: 5793 return err; 5794 } 5795 5796 /** 5797 * ufshcd_urgent_bkops - handle urgent bkops exception event 5798 * @hba: per-adapter instance 5799 * 5800 * Enable fBackgroundOpsEn flag in the device to permit background 5801 * operations. 5802 * 5803 * If BKOPs is enabled, this function returns 0, 1 if the bkops in not enabled 5804 * and negative error value for any other failure. 5805 * 5806 * Return: 0 upon success; < 0 upon failure. 5807 */ 5808 static int ufshcd_urgent_bkops(struct ufs_hba *hba) 5809 { 5810 return ufshcd_bkops_ctrl(hba, hba->urgent_bkops_lvl); 5811 } 5812 5813 static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status) 5814 { 5815 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 5816 QUERY_ATTR_IDN_EE_STATUS, 0, 0, status); 5817 } 5818 5819 static void ufshcd_bkops_exception_event_handler(struct ufs_hba *hba) 5820 { 5821 int err; 5822 u32 curr_status = 0; 5823 5824 if (hba->is_urgent_bkops_lvl_checked) 5825 goto enable_auto_bkops; 5826 5827 err = ufshcd_get_bkops_status(hba, &curr_status); 5828 if (err) { 5829 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n", 5830 __func__, err); 5831 goto out; 5832 } 5833 5834 /* 5835 * We are seeing that some devices are raising the urgent bkops 5836 * exception events even when BKOPS status doesn't indicate performace 5837 * impacted or critical. Handle these device by determining their urgent 5838 * bkops status at runtime. 5839 */ 5840 if (curr_status < BKOPS_STATUS_PERF_IMPACT) { 5841 dev_err(hba->dev, "%s: device raised urgent BKOPS exception for bkops status %d\n", 5842 __func__, curr_status); 5843 /* update the current status as the urgent bkops level */ 5844 hba->urgent_bkops_lvl = curr_status; 5845 hba->is_urgent_bkops_lvl_checked = true; 5846 } 5847 5848 enable_auto_bkops: 5849 err = ufshcd_enable_auto_bkops(hba); 5850 out: 5851 if (err < 0) 5852 dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n", 5853 __func__, err); 5854 } 5855 5856 static void ufshcd_temp_exception_event_handler(struct ufs_hba *hba, u16 status) 5857 { 5858 u32 value; 5859 5860 if (ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 5861 QUERY_ATTR_IDN_CASE_ROUGH_TEMP, 0, 0, &value)) 5862 return; 5863 5864 dev_info(hba->dev, "exception Tcase %d\n", value - 80); 5865 5866 ufs_hwmon_notify_event(hba, status & MASK_EE_URGENT_TEMP); 5867 5868 /* 5869 * A placeholder for the platform vendors to add whatever additional 5870 * steps required 5871 */ 5872 } 5873 5874 static int __ufshcd_wb_toggle(struct ufs_hba *hba, bool set, enum flag_idn idn) 5875 { 5876 u8 index; 5877 enum query_opcode opcode = set ? UPIU_QUERY_OPCODE_SET_FLAG : 5878 UPIU_QUERY_OPCODE_CLEAR_FLAG; 5879 5880 index = ufshcd_wb_get_query_index(hba); 5881 return ufshcd_query_flag_retry(hba, opcode, idn, index, NULL); 5882 } 5883 5884 int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable) 5885 { 5886 int ret; 5887 5888 if (!ufshcd_is_wb_allowed(hba) || 5889 hba->dev_info.wb_enabled == enable) 5890 return 0; 5891 5892 ret = __ufshcd_wb_toggle(hba, enable, QUERY_FLAG_IDN_WB_EN); 5893 if (ret) { 5894 dev_err(hba->dev, "%s: Write Booster %s failed %d\n", 5895 __func__, enable ? "enabling" : "disabling", ret); 5896 return ret; 5897 } 5898 5899 hba->dev_info.wb_enabled = enable; 5900 dev_dbg(hba->dev, "%s: Write Booster %s\n", 5901 __func__, enable ? "enabled" : "disabled"); 5902 5903 return ret; 5904 } 5905 5906 static void ufshcd_wb_toggle_buf_flush_during_h8(struct ufs_hba *hba, 5907 bool enable) 5908 { 5909 int ret; 5910 5911 ret = __ufshcd_wb_toggle(hba, enable, 5912 QUERY_FLAG_IDN_WB_BUFF_FLUSH_DURING_HIBERN8); 5913 if (ret) { 5914 dev_err(hba->dev, "%s: WB-Buf Flush during H8 %s failed %d\n", 5915 __func__, enable ? "enabling" : "disabling", ret); 5916 return; 5917 } 5918 dev_dbg(hba->dev, "%s: WB-Buf Flush during H8 %s\n", 5919 __func__, enable ? "enabled" : "disabled"); 5920 } 5921 5922 int ufshcd_wb_toggle_buf_flush(struct ufs_hba *hba, bool enable) 5923 { 5924 int ret; 5925 5926 if (!ufshcd_is_wb_allowed(hba) || 5927 hba->dev_info.wb_buf_flush_enabled == enable) 5928 return 0; 5929 5930 ret = __ufshcd_wb_toggle(hba, enable, QUERY_FLAG_IDN_WB_BUFF_FLUSH_EN); 5931 if (ret) { 5932 dev_err(hba->dev, "%s: WB-Buf Flush %s failed %d\n", 5933 __func__, enable ? "enabling" : "disabling", ret); 5934 return ret; 5935 } 5936 5937 hba->dev_info.wb_buf_flush_enabled = enable; 5938 dev_dbg(hba->dev, "%s: WB-Buf Flush %s\n", 5939 __func__, enable ? "enabled" : "disabled"); 5940 5941 return ret; 5942 } 5943 5944 static bool ufshcd_wb_presrv_usrspc_keep_vcc_on(struct ufs_hba *hba, 5945 u32 avail_buf) 5946 { 5947 u32 cur_buf; 5948 int ret; 5949 u8 index; 5950 5951 index = ufshcd_wb_get_query_index(hba); 5952 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 5953 QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE, 5954 index, 0, &cur_buf); 5955 if (ret) { 5956 dev_err(hba->dev, "%s: dCurWriteBoosterBufferSize read failed %d\n", 5957 __func__, ret); 5958 return false; 5959 } 5960 5961 if (!cur_buf) { 5962 dev_info(hba->dev, "dCurWBBuf: %d WB disabled until free-space is available\n", 5963 cur_buf); 5964 return false; 5965 } 5966 /* Let it continue to flush when available buffer exceeds threshold */ 5967 return avail_buf < hba->vps->wb_flush_threshold; 5968 } 5969 5970 static void ufshcd_wb_force_disable(struct ufs_hba *hba) 5971 { 5972 if (ufshcd_is_wb_buf_flush_allowed(hba)) 5973 ufshcd_wb_toggle_buf_flush(hba, false); 5974 5975 ufshcd_wb_toggle_buf_flush_during_h8(hba, false); 5976 ufshcd_wb_toggle(hba, false); 5977 hba->caps &= ~UFSHCD_CAP_WB_EN; 5978 5979 dev_info(hba->dev, "%s: WB force disabled\n", __func__); 5980 } 5981 5982 static bool ufshcd_is_wb_buf_lifetime_available(struct ufs_hba *hba) 5983 { 5984 u32 lifetime; 5985 int ret; 5986 u8 index; 5987 5988 index = ufshcd_wb_get_query_index(hba); 5989 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 5990 QUERY_ATTR_IDN_WB_BUFF_LIFE_TIME_EST, 5991 index, 0, &lifetime); 5992 if (ret) { 5993 dev_err(hba->dev, 5994 "%s: bWriteBoosterBufferLifeTimeEst read failed %d\n", 5995 __func__, ret); 5996 return false; 5997 } 5998 5999 if (lifetime == UFS_WB_EXCEED_LIFETIME) { 6000 dev_err(hba->dev, "%s: WB buf lifetime is exhausted 0x%02X\n", 6001 __func__, lifetime); 6002 return false; 6003 } 6004 6005 dev_dbg(hba->dev, "%s: WB buf lifetime is 0x%02X\n", 6006 __func__, lifetime); 6007 6008 return true; 6009 } 6010 6011 static bool ufshcd_wb_need_flush(struct ufs_hba *hba) 6012 { 6013 int ret; 6014 u32 avail_buf; 6015 u8 index; 6016 6017 if (!ufshcd_is_wb_allowed(hba)) 6018 return false; 6019 6020 if (!ufshcd_is_wb_buf_lifetime_available(hba)) { 6021 ufshcd_wb_force_disable(hba); 6022 return false; 6023 } 6024 6025 /* 6026 * The ufs device needs the vcc to be ON to flush. 6027 * With user-space reduction enabled, it's enough to enable flush 6028 * by checking only the available buffer. The threshold 6029 * defined here is > 90% full. 6030 * With user-space preserved enabled, the current-buffer 6031 * should be checked too because the wb buffer size can reduce 6032 * when disk tends to be full. This info is provided by current 6033 * buffer (dCurrentWriteBoosterBufferSize). There's no point in 6034 * keeping vcc on when current buffer is empty. 6035 */ 6036 index = ufshcd_wb_get_query_index(hba); 6037 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 6038 QUERY_ATTR_IDN_AVAIL_WB_BUFF_SIZE, 6039 index, 0, &avail_buf); 6040 if (ret) { 6041 dev_warn(hba->dev, "%s: dAvailableWriteBoosterBufferSize read failed %d\n", 6042 __func__, ret); 6043 return false; 6044 } 6045 6046 if (!hba->dev_info.b_presrv_uspc_en) 6047 return avail_buf <= UFS_WB_BUF_REMAIN_PERCENT(10); 6048 6049 return ufshcd_wb_presrv_usrspc_keep_vcc_on(hba, avail_buf); 6050 } 6051 6052 static void ufshcd_rpm_dev_flush_recheck_work(struct work_struct *work) 6053 { 6054 struct ufs_hba *hba = container_of(to_delayed_work(work), 6055 struct ufs_hba, 6056 rpm_dev_flush_recheck_work); 6057 /* 6058 * To prevent unnecessary VCC power drain after device finishes 6059 * WriteBooster buffer flush or Auto BKOPs, force runtime resume 6060 * after a certain delay to recheck the threshold by next runtime 6061 * suspend. 6062 */ 6063 ufshcd_rpm_get_sync(hba); 6064 ufshcd_rpm_put_sync(hba); 6065 } 6066 6067 /** 6068 * ufshcd_exception_event_handler - handle exceptions raised by device 6069 * @work: pointer to work data 6070 * 6071 * Read bExceptionEventStatus attribute from the device and handle the 6072 * exception event accordingly. 6073 */ 6074 static void ufshcd_exception_event_handler(struct work_struct *work) 6075 { 6076 struct ufs_hba *hba; 6077 int err; 6078 u32 status = 0; 6079 hba = container_of(work, struct ufs_hba, eeh_work); 6080 6081 ufshcd_scsi_block_requests(hba); 6082 err = ufshcd_get_ee_status(hba, &status); 6083 if (err) { 6084 dev_err(hba->dev, "%s: failed to get exception status %d\n", 6085 __func__, err); 6086 goto out; 6087 } 6088 6089 trace_ufshcd_exception_event(dev_name(hba->dev), status); 6090 6091 if (status & hba->ee_drv_mask & MASK_EE_URGENT_BKOPS) 6092 ufshcd_bkops_exception_event_handler(hba); 6093 6094 if (status & hba->ee_drv_mask & MASK_EE_URGENT_TEMP) 6095 ufshcd_temp_exception_event_handler(hba, status); 6096 6097 ufs_debugfs_exception_event(hba, status); 6098 out: 6099 ufshcd_scsi_unblock_requests(hba); 6100 } 6101 6102 /* Complete requests that have door-bell cleared */ 6103 static void ufshcd_complete_requests(struct ufs_hba *hba, bool force_compl) 6104 { 6105 if (is_mcq_enabled(hba)) 6106 ufshcd_mcq_compl_pending_transfer(hba, force_compl); 6107 else 6108 ufshcd_transfer_req_compl(hba); 6109 6110 ufshcd_tmc_handler(hba); 6111 } 6112 6113 /** 6114 * ufshcd_quirk_dl_nac_errors - This function checks if error handling is 6115 * to recover from the DL NAC errors or not. 6116 * @hba: per-adapter instance 6117 * 6118 * Return: true if error handling is required, false otherwise. 6119 */ 6120 static bool ufshcd_quirk_dl_nac_errors(struct ufs_hba *hba) 6121 { 6122 unsigned long flags; 6123 bool err_handling = true; 6124 6125 spin_lock_irqsave(hba->host->host_lock, flags); 6126 /* 6127 * UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS only workaround the 6128 * device fatal error and/or DL NAC & REPLAY timeout errors. 6129 */ 6130 if (hba->saved_err & (CONTROLLER_FATAL_ERROR | SYSTEM_BUS_FATAL_ERROR)) 6131 goto out; 6132 6133 if ((hba->saved_err & DEVICE_FATAL_ERROR) || 6134 ((hba->saved_err & UIC_ERROR) && 6135 (hba->saved_uic_err & UFSHCD_UIC_DL_TCx_REPLAY_ERROR))) 6136 goto out; 6137 6138 if ((hba->saved_err & UIC_ERROR) && 6139 (hba->saved_uic_err & UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)) { 6140 int err; 6141 /* 6142 * wait for 50ms to see if we can get any other errors or not. 6143 */ 6144 spin_unlock_irqrestore(hba->host->host_lock, flags); 6145 msleep(50); 6146 spin_lock_irqsave(hba->host->host_lock, flags); 6147 6148 /* 6149 * now check if we have got any other severe errors other than 6150 * DL NAC error? 6151 */ 6152 if ((hba->saved_err & INT_FATAL_ERRORS) || 6153 ((hba->saved_err & UIC_ERROR) && 6154 (hba->saved_uic_err & ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR))) 6155 goto out; 6156 6157 /* 6158 * As DL NAC is the only error received so far, send out NOP 6159 * command to confirm if link is still active or not. 6160 * - If we don't get any response then do error recovery. 6161 * - If we get response then clear the DL NAC error bit. 6162 */ 6163 6164 spin_unlock_irqrestore(hba->host->host_lock, flags); 6165 err = ufshcd_verify_dev_init(hba); 6166 spin_lock_irqsave(hba->host->host_lock, flags); 6167 6168 if (err) 6169 goto out; 6170 6171 /* Link seems to be alive hence ignore the DL NAC errors */ 6172 if (hba->saved_uic_err == UFSHCD_UIC_DL_NAC_RECEIVED_ERROR) 6173 hba->saved_err &= ~UIC_ERROR; 6174 /* clear NAC error */ 6175 hba->saved_uic_err &= ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR; 6176 if (!hba->saved_uic_err) 6177 err_handling = false; 6178 } 6179 out: 6180 spin_unlock_irqrestore(hba->host->host_lock, flags); 6181 return err_handling; 6182 } 6183 6184 /* host lock must be held before calling this func */ 6185 static inline bool ufshcd_is_saved_err_fatal(struct ufs_hba *hba) 6186 { 6187 return (hba->saved_uic_err & UFSHCD_UIC_DL_PA_INIT_ERROR) || 6188 (hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)); 6189 } 6190 6191 void ufshcd_schedule_eh_work(struct ufs_hba *hba) 6192 { 6193 lockdep_assert_held(hba->host->host_lock); 6194 6195 /* handle fatal errors only when link is not in error state */ 6196 if (hba->ufshcd_state != UFSHCD_STATE_ERROR) { 6197 if (hba->force_reset || ufshcd_is_link_broken(hba) || 6198 ufshcd_is_saved_err_fatal(hba)) 6199 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_FATAL; 6200 else 6201 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_NON_FATAL; 6202 queue_work(hba->eh_wq, &hba->eh_work); 6203 } 6204 } 6205 6206 static void ufshcd_force_error_recovery(struct ufs_hba *hba) 6207 { 6208 spin_lock_irq(hba->host->host_lock); 6209 hba->force_reset = true; 6210 ufshcd_schedule_eh_work(hba); 6211 spin_unlock_irq(hba->host->host_lock); 6212 } 6213 6214 static void ufshcd_clk_scaling_allow(struct ufs_hba *hba, bool allow) 6215 { 6216 mutex_lock(&hba->wb_mutex); 6217 down_write(&hba->clk_scaling_lock); 6218 hba->clk_scaling.is_allowed = allow; 6219 up_write(&hba->clk_scaling_lock); 6220 mutex_unlock(&hba->wb_mutex); 6221 } 6222 6223 static void ufshcd_clk_scaling_suspend(struct ufs_hba *hba, bool suspend) 6224 { 6225 if (suspend) { 6226 if (hba->clk_scaling.is_enabled) 6227 ufshcd_suspend_clkscaling(hba); 6228 ufshcd_clk_scaling_allow(hba, false); 6229 } else { 6230 ufshcd_clk_scaling_allow(hba, true); 6231 if (hba->clk_scaling.is_enabled) 6232 ufshcd_resume_clkscaling(hba); 6233 } 6234 } 6235 6236 static void ufshcd_err_handling_prepare(struct ufs_hba *hba) 6237 { 6238 ufshcd_rpm_get_sync(hba); 6239 if (pm_runtime_status_suspended(&hba->ufs_device_wlun->sdev_gendev) || 6240 hba->is_sys_suspended) { 6241 enum ufs_pm_op pm_op; 6242 6243 /* 6244 * Don't assume anything of resume, if 6245 * resume fails, irq and clocks can be OFF, and powers 6246 * can be OFF or in LPM. 6247 */ 6248 ufshcd_setup_hba_vreg(hba, true); 6249 ufshcd_enable_irq(hba); 6250 ufshcd_setup_vreg(hba, true); 6251 ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq); 6252 ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2); 6253 ufshcd_hold(hba); 6254 if (!ufshcd_is_clkgating_allowed(hba)) 6255 ufshcd_setup_clocks(hba, true); 6256 pm_op = hba->is_sys_suspended ? UFS_SYSTEM_PM : UFS_RUNTIME_PM; 6257 ufshcd_vops_resume(hba, pm_op); 6258 } else { 6259 ufshcd_hold(hba); 6260 if (ufshcd_is_clkscaling_supported(hba) && 6261 hba->clk_scaling.is_enabled) 6262 ufshcd_suspend_clkscaling(hba); 6263 ufshcd_clk_scaling_allow(hba, false); 6264 } 6265 ufshcd_scsi_block_requests(hba); 6266 /* Wait for ongoing ufshcd_queuecommand() calls to finish. */ 6267 blk_mq_wait_quiesce_done(&hba->host->tag_set); 6268 cancel_work_sync(&hba->eeh_work); 6269 } 6270 6271 static void ufshcd_err_handling_unprepare(struct ufs_hba *hba) 6272 { 6273 ufshcd_scsi_unblock_requests(hba); 6274 ufshcd_release(hba); 6275 if (ufshcd_is_clkscaling_supported(hba)) 6276 ufshcd_clk_scaling_suspend(hba, false); 6277 ufshcd_rpm_put(hba); 6278 } 6279 6280 static inline bool ufshcd_err_handling_should_stop(struct ufs_hba *hba) 6281 { 6282 return (!hba->is_powered || hba->shutting_down || 6283 !hba->ufs_device_wlun || 6284 hba->ufshcd_state == UFSHCD_STATE_ERROR || 6285 (!(hba->saved_err || hba->saved_uic_err || hba->force_reset || 6286 ufshcd_is_link_broken(hba)))); 6287 } 6288 6289 #ifdef CONFIG_PM 6290 static void ufshcd_recover_pm_error(struct ufs_hba *hba) 6291 { 6292 struct Scsi_Host *shost = hba->host; 6293 struct scsi_device *sdev; 6294 struct request_queue *q; 6295 int ret; 6296 6297 hba->is_sys_suspended = false; 6298 /* 6299 * Set RPM status of wlun device to RPM_ACTIVE, 6300 * this also clears its runtime error. 6301 */ 6302 ret = pm_runtime_set_active(&hba->ufs_device_wlun->sdev_gendev); 6303 6304 /* hba device might have a runtime error otherwise */ 6305 if (ret) 6306 ret = pm_runtime_set_active(hba->dev); 6307 /* 6308 * If wlun device had runtime error, we also need to resume those 6309 * consumer scsi devices in case any of them has failed to be 6310 * resumed due to supplier runtime resume failure. This is to unblock 6311 * blk_queue_enter in case there are bios waiting inside it. 6312 */ 6313 if (!ret) { 6314 shost_for_each_device(sdev, shost) { 6315 q = sdev->request_queue; 6316 if (q->dev && (q->rpm_status == RPM_SUSPENDED || 6317 q->rpm_status == RPM_SUSPENDING)) 6318 pm_request_resume(q->dev); 6319 } 6320 } 6321 } 6322 #else 6323 static inline void ufshcd_recover_pm_error(struct ufs_hba *hba) 6324 { 6325 } 6326 #endif 6327 6328 static bool ufshcd_is_pwr_mode_restore_needed(struct ufs_hba *hba) 6329 { 6330 struct ufs_pa_layer_attr *pwr_info = &hba->pwr_info; 6331 u32 mode; 6332 6333 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PWRMODE), &mode); 6334 6335 if (pwr_info->pwr_rx != ((mode >> PWRMODE_RX_OFFSET) & PWRMODE_MASK)) 6336 return true; 6337 6338 if (pwr_info->pwr_tx != (mode & PWRMODE_MASK)) 6339 return true; 6340 6341 return false; 6342 } 6343 6344 static bool ufshcd_abort_one(struct request *rq, void *priv) 6345 { 6346 int *ret = priv; 6347 u32 tag = rq->tag; 6348 struct scsi_cmnd *cmd = blk_mq_rq_to_pdu(rq); 6349 struct scsi_device *sdev = cmd->device; 6350 struct Scsi_Host *shost = sdev->host; 6351 struct ufs_hba *hba = shost_priv(shost); 6352 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 6353 struct ufs_hw_queue *hwq; 6354 unsigned long flags; 6355 6356 *ret = ufshcd_try_to_abort_task(hba, tag); 6357 dev_err(hba->dev, "Aborting tag %d / CDB %#02x %s\n", tag, 6358 hba->lrb[tag].cmd ? hba->lrb[tag].cmd->cmnd[0] : -1, 6359 *ret ? "failed" : "succeeded"); 6360 6361 /* Release cmd in MCQ mode if abort succeeds */ 6362 if (is_mcq_enabled(hba) && (*ret == 0)) { 6363 hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(lrbp->cmd)); 6364 spin_lock_irqsave(&hwq->cq_lock, flags); 6365 if (ufshcd_cmd_inflight(lrbp->cmd)) 6366 ufshcd_release_scsi_cmd(hba, lrbp); 6367 spin_unlock_irqrestore(&hwq->cq_lock, flags); 6368 } 6369 6370 return *ret == 0; 6371 } 6372 6373 /** 6374 * ufshcd_abort_all - Abort all pending commands. 6375 * @hba: Host bus adapter pointer. 6376 * 6377 * Return: true if and only if the host controller needs to be reset. 6378 */ 6379 static bool ufshcd_abort_all(struct ufs_hba *hba) 6380 { 6381 int tag, ret = 0; 6382 6383 blk_mq_tagset_busy_iter(&hba->host->tag_set, ufshcd_abort_one, &ret); 6384 if (ret) 6385 goto out; 6386 6387 /* Clear pending task management requests */ 6388 for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) { 6389 ret = ufshcd_clear_tm_cmd(hba, tag); 6390 if (ret) 6391 goto out; 6392 } 6393 6394 out: 6395 /* Complete the requests that are cleared by s/w */ 6396 ufshcd_complete_requests(hba, false); 6397 6398 return ret != 0; 6399 } 6400 6401 /** 6402 * ufshcd_err_handler - handle UFS errors that require s/w attention 6403 * @work: pointer to work structure 6404 */ 6405 static void ufshcd_err_handler(struct work_struct *work) 6406 { 6407 int retries = MAX_ERR_HANDLER_RETRIES; 6408 struct ufs_hba *hba; 6409 unsigned long flags; 6410 bool needs_restore; 6411 bool needs_reset; 6412 int pmc_err; 6413 6414 hba = container_of(work, struct ufs_hba, eh_work); 6415 6416 dev_info(hba->dev, 6417 "%s started; HBA state %s; powered %d; shutting down %d; saved_err = %d; saved_uic_err = %d; force_reset = %d%s\n", 6418 __func__, ufshcd_state_name[hba->ufshcd_state], 6419 hba->is_powered, hba->shutting_down, hba->saved_err, 6420 hba->saved_uic_err, hba->force_reset, 6421 ufshcd_is_link_broken(hba) ? "; link is broken" : ""); 6422 6423 down(&hba->host_sem); 6424 spin_lock_irqsave(hba->host->host_lock, flags); 6425 if (ufshcd_err_handling_should_stop(hba)) { 6426 if (hba->ufshcd_state != UFSHCD_STATE_ERROR) 6427 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL; 6428 spin_unlock_irqrestore(hba->host->host_lock, flags); 6429 up(&hba->host_sem); 6430 return; 6431 } 6432 ufshcd_set_eh_in_progress(hba); 6433 spin_unlock_irqrestore(hba->host->host_lock, flags); 6434 ufshcd_err_handling_prepare(hba); 6435 /* Complete requests that have door-bell cleared by h/w */ 6436 ufshcd_complete_requests(hba, false); 6437 spin_lock_irqsave(hba->host->host_lock, flags); 6438 again: 6439 needs_restore = false; 6440 needs_reset = false; 6441 6442 if (hba->ufshcd_state != UFSHCD_STATE_ERROR) 6443 hba->ufshcd_state = UFSHCD_STATE_RESET; 6444 /* 6445 * A full reset and restore might have happened after preparation 6446 * is finished, double check whether we should stop. 6447 */ 6448 if (ufshcd_err_handling_should_stop(hba)) 6449 goto skip_err_handling; 6450 6451 if (hba->dev_quirks & UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) { 6452 bool ret; 6453 6454 spin_unlock_irqrestore(hba->host->host_lock, flags); 6455 /* release the lock as ufshcd_quirk_dl_nac_errors() may sleep */ 6456 ret = ufshcd_quirk_dl_nac_errors(hba); 6457 spin_lock_irqsave(hba->host->host_lock, flags); 6458 if (!ret && ufshcd_err_handling_should_stop(hba)) 6459 goto skip_err_handling; 6460 } 6461 6462 if ((hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) || 6463 (hba->saved_uic_err && 6464 (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) { 6465 bool pr_prdt = !!(hba->saved_err & SYSTEM_BUS_FATAL_ERROR); 6466 6467 spin_unlock_irqrestore(hba->host->host_lock, flags); 6468 ufshcd_print_host_state(hba); 6469 ufshcd_print_pwr_info(hba); 6470 ufshcd_print_evt_hist(hba); 6471 ufshcd_print_tmrs(hba, hba->outstanding_tasks); 6472 ufshcd_print_trs_all(hba, pr_prdt); 6473 spin_lock_irqsave(hba->host->host_lock, flags); 6474 } 6475 6476 /* 6477 * if host reset is required then skip clearing the pending 6478 * transfers forcefully because they will get cleared during 6479 * host reset and restore 6480 */ 6481 if (hba->force_reset || ufshcd_is_link_broken(hba) || 6482 ufshcd_is_saved_err_fatal(hba) || 6483 ((hba->saved_err & UIC_ERROR) && 6484 (hba->saved_uic_err & (UFSHCD_UIC_DL_NAC_RECEIVED_ERROR | 6485 UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))) { 6486 needs_reset = true; 6487 goto do_reset; 6488 } 6489 6490 /* 6491 * If LINERESET was caught, UFS might have been put to PWM mode, 6492 * check if power mode restore is needed. 6493 */ 6494 if (hba->saved_uic_err & UFSHCD_UIC_PA_GENERIC_ERROR) { 6495 hba->saved_uic_err &= ~UFSHCD_UIC_PA_GENERIC_ERROR; 6496 if (!hba->saved_uic_err) 6497 hba->saved_err &= ~UIC_ERROR; 6498 spin_unlock_irqrestore(hba->host->host_lock, flags); 6499 if (ufshcd_is_pwr_mode_restore_needed(hba)) 6500 needs_restore = true; 6501 spin_lock_irqsave(hba->host->host_lock, flags); 6502 if (!hba->saved_err && !needs_restore) 6503 goto skip_err_handling; 6504 } 6505 6506 hba->silence_err_logs = true; 6507 /* release lock as clear command might sleep */ 6508 spin_unlock_irqrestore(hba->host->host_lock, flags); 6509 6510 needs_reset = ufshcd_abort_all(hba); 6511 6512 spin_lock_irqsave(hba->host->host_lock, flags); 6513 hba->silence_err_logs = false; 6514 if (needs_reset) 6515 goto do_reset; 6516 6517 /* 6518 * After all reqs and tasks are cleared from doorbell, 6519 * now it is safe to retore power mode. 6520 */ 6521 if (needs_restore) { 6522 spin_unlock_irqrestore(hba->host->host_lock, flags); 6523 /* 6524 * Hold the scaling lock just in case dev cmds 6525 * are sent via bsg and/or sysfs. 6526 */ 6527 down_write(&hba->clk_scaling_lock); 6528 hba->force_pmc = true; 6529 pmc_err = ufshcd_config_pwr_mode(hba, &(hba->pwr_info)); 6530 if (pmc_err) { 6531 needs_reset = true; 6532 dev_err(hba->dev, "%s: Failed to restore power mode, err = %d\n", 6533 __func__, pmc_err); 6534 } 6535 hba->force_pmc = false; 6536 ufshcd_print_pwr_info(hba); 6537 up_write(&hba->clk_scaling_lock); 6538 spin_lock_irqsave(hba->host->host_lock, flags); 6539 } 6540 6541 do_reset: 6542 /* Fatal errors need reset */ 6543 if (needs_reset) { 6544 int err; 6545 6546 hba->force_reset = false; 6547 spin_unlock_irqrestore(hba->host->host_lock, flags); 6548 err = ufshcd_reset_and_restore(hba); 6549 if (err) 6550 dev_err(hba->dev, "%s: reset and restore failed with err %d\n", 6551 __func__, err); 6552 else 6553 ufshcd_recover_pm_error(hba); 6554 spin_lock_irqsave(hba->host->host_lock, flags); 6555 } 6556 6557 skip_err_handling: 6558 if (!needs_reset) { 6559 if (hba->ufshcd_state == UFSHCD_STATE_RESET) 6560 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL; 6561 if (hba->saved_err || hba->saved_uic_err) 6562 dev_err_ratelimited(hba->dev, "%s: exit: saved_err 0x%x saved_uic_err 0x%x", 6563 __func__, hba->saved_err, hba->saved_uic_err); 6564 } 6565 /* Exit in an operational state or dead */ 6566 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL && 6567 hba->ufshcd_state != UFSHCD_STATE_ERROR) { 6568 if (--retries) 6569 goto again; 6570 hba->ufshcd_state = UFSHCD_STATE_ERROR; 6571 } 6572 ufshcd_clear_eh_in_progress(hba); 6573 spin_unlock_irqrestore(hba->host->host_lock, flags); 6574 ufshcd_err_handling_unprepare(hba); 6575 up(&hba->host_sem); 6576 6577 dev_info(hba->dev, "%s finished; HBA state %s\n", __func__, 6578 ufshcd_state_name[hba->ufshcd_state]); 6579 } 6580 6581 /** 6582 * ufshcd_update_uic_error - check and set fatal UIC error flags. 6583 * @hba: per-adapter instance 6584 * 6585 * Return: 6586 * IRQ_HANDLED - If interrupt is valid 6587 * IRQ_NONE - If invalid interrupt 6588 */ 6589 static irqreturn_t ufshcd_update_uic_error(struct ufs_hba *hba) 6590 { 6591 u32 reg; 6592 irqreturn_t retval = IRQ_NONE; 6593 6594 /* PHY layer error */ 6595 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER); 6596 if ((reg & UIC_PHY_ADAPTER_LAYER_ERROR) && 6597 (reg & UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK)) { 6598 ufshcd_update_evt_hist(hba, UFS_EVT_PA_ERR, reg); 6599 /* 6600 * To know whether this error is fatal or not, DB timeout 6601 * must be checked but this error is handled separately. 6602 */ 6603 if (reg & UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK) 6604 dev_dbg(hba->dev, "%s: UIC Lane error reported\n", 6605 __func__); 6606 6607 /* Got a LINERESET indication. */ 6608 if (reg & UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR) { 6609 struct uic_command *cmd = NULL; 6610 6611 hba->uic_error |= UFSHCD_UIC_PA_GENERIC_ERROR; 6612 if (hba->uic_async_done && hba->active_uic_cmd) 6613 cmd = hba->active_uic_cmd; 6614 /* 6615 * Ignore the LINERESET during power mode change 6616 * operation via DME_SET command. 6617 */ 6618 if (cmd && (cmd->command == UIC_CMD_DME_SET)) 6619 hba->uic_error &= ~UFSHCD_UIC_PA_GENERIC_ERROR; 6620 } 6621 retval |= IRQ_HANDLED; 6622 } 6623 6624 /* PA_INIT_ERROR is fatal and needs UIC reset */ 6625 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER); 6626 if ((reg & UIC_DATA_LINK_LAYER_ERROR) && 6627 (reg & UIC_DATA_LINK_LAYER_ERROR_CODE_MASK)) { 6628 ufshcd_update_evt_hist(hba, UFS_EVT_DL_ERR, reg); 6629 6630 if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT) 6631 hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR; 6632 else if (hba->dev_quirks & 6633 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) { 6634 if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED) 6635 hba->uic_error |= 6636 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR; 6637 else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT) 6638 hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR; 6639 } 6640 retval |= IRQ_HANDLED; 6641 } 6642 6643 /* UIC NL/TL/DME errors needs software retry */ 6644 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER); 6645 if ((reg & UIC_NETWORK_LAYER_ERROR) && 6646 (reg & UIC_NETWORK_LAYER_ERROR_CODE_MASK)) { 6647 ufshcd_update_evt_hist(hba, UFS_EVT_NL_ERR, reg); 6648 hba->uic_error |= UFSHCD_UIC_NL_ERROR; 6649 retval |= IRQ_HANDLED; 6650 } 6651 6652 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER); 6653 if ((reg & UIC_TRANSPORT_LAYER_ERROR) && 6654 (reg & UIC_TRANSPORT_LAYER_ERROR_CODE_MASK)) { 6655 ufshcd_update_evt_hist(hba, UFS_EVT_TL_ERR, reg); 6656 hba->uic_error |= UFSHCD_UIC_TL_ERROR; 6657 retval |= IRQ_HANDLED; 6658 } 6659 6660 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME); 6661 if ((reg & UIC_DME_ERROR) && 6662 (reg & UIC_DME_ERROR_CODE_MASK)) { 6663 ufshcd_update_evt_hist(hba, UFS_EVT_DME_ERR, reg); 6664 hba->uic_error |= UFSHCD_UIC_DME_ERROR; 6665 retval |= IRQ_HANDLED; 6666 } 6667 6668 dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n", 6669 __func__, hba->uic_error); 6670 return retval; 6671 } 6672 6673 /** 6674 * ufshcd_check_errors - Check for errors that need s/w attention 6675 * @hba: per-adapter instance 6676 * @intr_status: interrupt status generated by the controller 6677 * 6678 * Return: 6679 * IRQ_HANDLED - If interrupt is valid 6680 * IRQ_NONE - If invalid interrupt 6681 */ 6682 static irqreturn_t ufshcd_check_errors(struct ufs_hba *hba, u32 intr_status) 6683 { 6684 bool queue_eh_work = false; 6685 irqreturn_t retval = IRQ_NONE; 6686 6687 spin_lock(hba->host->host_lock); 6688 hba->errors |= UFSHCD_ERROR_MASK & intr_status; 6689 6690 if (hba->errors & INT_FATAL_ERRORS) { 6691 ufshcd_update_evt_hist(hba, UFS_EVT_FATAL_ERR, 6692 hba->errors); 6693 queue_eh_work = true; 6694 } 6695 6696 if (hba->errors & UIC_ERROR) { 6697 hba->uic_error = 0; 6698 retval = ufshcd_update_uic_error(hba); 6699 if (hba->uic_error) 6700 queue_eh_work = true; 6701 } 6702 6703 if (hba->errors & UFSHCD_UIC_HIBERN8_MASK) { 6704 dev_err(hba->dev, 6705 "%s: Auto Hibern8 %s failed - status: 0x%08x, upmcrs: 0x%08x\n", 6706 __func__, (hba->errors & UIC_HIBERNATE_ENTER) ? 6707 "Enter" : "Exit", 6708 hba->errors, ufshcd_get_upmcrs(hba)); 6709 ufshcd_update_evt_hist(hba, UFS_EVT_AUTO_HIBERN8_ERR, 6710 hba->errors); 6711 ufshcd_set_link_broken(hba); 6712 queue_eh_work = true; 6713 } 6714 6715 if (queue_eh_work) { 6716 /* 6717 * update the transfer error masks to sticky bits, let's do this 6718 * irrespective of current ufshcd_state. 6719 */ 6720 hba->saved_err |= hba->errors; 6721 hba->saved_uic_err |= hba->uic_error; 6722 6723 /* dump controller state before resetting */ 6724 if ((hba->saved_err & 6725 (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) || 6726 (hba->saved_uic_err && 6727 (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) { 6728 dev_err(hba->dev, "%s: saved_err 0x%x saved_uic_err 0x%x\n", 6729 __func__, hba->saved_err, 6730 hba->saved_uic_err); 6731 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, 6732 "host_regs: "); 6733 ufshcd_print_pwr_info(hba); 6734 } 6735 ufshcd_schedule_eh_work(hba); 6736 retval |= IRQ_HANDLED; 6737 } 6738 /* 6739 * if (!queue_eh_work) - 6740 * Other errors are either non-fatal where host recovers 6741 * itself without s/w intervention or errors that will be 6742 * handled by the SCSI core layer. 6743 */ 6744 hba->errors = 0; 6745 hba->uic_error = 0; 6746 spin_unlock(hba->host->host_lock); 6747 return retval; 6748 } 6749 6750 /** 6751 * ufshcd_tmc_handler - handle task management function completion 6752 * @hba: per adapter instance 6753 * 6754 * Return: 6755 * IRQ_HANDLED - If interrupt is valid 6756 * IRQ_NONE - If invalid interrupt 6757 */ 6758 static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba) 6759 { 6760 unsigned long flags, pending, issued; 6761 irqreturn_t ret = IRQ_NONE; 6762 int tag; 6763 6764 spin_lock_irqsave(hba->host->host_lock, flags); 6765 pending = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL); 6766 issued = hba->outstanding_tasks & ~pending; 6767 for_each_set_bit(tag, &issued, hba->nutmrs) { 6768 struct request *req = hba->tmf_rqs[tag]; 6769 struct completion *c = req->end_io_data; 6770 6771 complete(c); 6772 ret = IRQ_HANDLED; 6773 } 6774 spin_unlock_irqrestore(hba->host->host_lock, flags); 6775 6776 return ret; 6777 } 6778 6779 /** 6780 * ufshcd_handle_mcq_cq_events - handle MCQ completion queue events 6781 * @hba: per adapter instance 6782 * 6783 * Return: IRQ_HANDLED if interrupt is handled. 6784 */ 6785 static irqreturn_t ufshcd_handle_mcq_cq_events(struct ufs_hba *hba) 6786 { 6787 struct ufs_hw_queue *hwq; 6788 unsigned long outstanding_cqs; 6789 unsigned int nr_queues; 6790 int i, ret; 6791 u32 events; 6792 6793 ret = ufshcd_vops_get_outstanding_cqs(hba, &outstanding_cqs); 6794 if (ret) 6795 outstanding_cqs = (1U << hba->nr_hw_queues) - 1; 6796 6797 /* Exclude the poll queues */ 6798 nr_queues = hba->nr_hw_queues - hba->nr_queues[HCTX_TYPE_POLL]; 6799 for_each_set_bit(i, &outstanding_cqs, nr_queues) { 6800 hwq = &hba->uhq[i]; 6801 6802 events = ufshcd_mcq_read_cqis(hba, i); 6803 if (events) 6804 ufshcd_mcq_write_cqis(hba, events, i); 6805 6806 if (events & UFSHCD_MCQ_CQIS_TAIL_ENT_PUSH_STS) 6807 ufshcd_mcq_poll_cqe_lock(hba, hwq); 6808 } 6809 6810 return IRQ_HANDLED; 6811 } 6812 6813 /** 6814 * ufshcd_sl_intr - Interrupt service routine 6815 * @hba: per adapter instance 6816 * @intr_status: contains interrupts generated by the controller 6817 * 6818 * Return: 6819 * IRQ_HANDLED - If interrupt is valid 6820 * IRQ_NONE - If invalid interrupt 6821 */ 6822 static irqreturn_t ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status) 6823 { 6824 irqreturn_t retval = IRQ_NONE; 6825 6826 if (intr_status & UFSHCD_UIC_MASK) 6827 retval |= ufshcd_uic_cmd_compl(hba, intr_status); 6828 6829 if (intr_status & UFSHCD_ERROR_MASK || hba->errors) 6830 retval |= ufshcd_check_errors(hba, intr_status); 6831 6832 if (intr_status & UTP_TASK_REQ_COMPL) 6833 retval |= ufshcd_tmc_handler(hba); 6834 6835 if (intr_status & UTP_TRANSFER_REQ_COMPL) 6836 retval |= ufshcd_transfer_req_compl(hba); 6837 6838 if (intr_status & MCQ_CQ_EVENT_STATUS) 6839 retval |= ufshcd_handle_mcq_cq_events(hba); 6840 6841 return retval; 6842 } 6843 6844 /** 6845 * ufshcd_intr - Main interrupt service routine 6846 * @irq: irq number 6847 * @__hba: pointer to adapter instance 6848 * 6849 * Return: 6850 * IRQ_HANDLED - If interrupt is valid 6851 * IRQ_NONE - If invalid interrupt 6852 */ 6853 static irqreturn_t ufshcd_intr(int irq, void *__hba) 6854 { 6855 u32 intr_status, enabled_intr_status = 0; 6856 irqreturn_t retval = IRQ_NONE; 6857 struct ufs_hba *hba = __hba; 6858 int retries = hba->nutrs; 6859 6860 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS); 6861 hba->ufs_stats.last_intr_status = intr_status; 6862 hba->ufs_stats.last_intr_ts = local_clock(); 6863 6864 /* 6865 * There could be max of hba->nutrs reqs in flight and in worst case 6866 * if the reqs get finished 1 by 1 after the interrupt status is 6867 * read, make sure we handle them by checking the interrupt status 6868 * again in a loop until we process all of the reqs before returning. 6869 */ 6870 while (intr_status && retries--) { 6871 enabled_intr_status = 6872 intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 6873 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS); 6874 if (enabled_intr_status) 6875 retval |= ufshcd_sl_intr(hba, enabled_intr_status); 6876 6877 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS); 6878 } 6879 6880 if (enabled_intr_status && retval == IRQ_NONE && 6881 (!(enabled_intr_status & UTP_TRANSFER_REQ_COMPL) || 6882 hba->outstanding_reqs) && !ufshcd_eh_in_progress(hba)) { 6883 dev_err(hba->dev, "%s: Unhandled interrupt 0x%08x (0x%08x, 0x%08x)\n", 6884 __func__, 6885 intr_status, 6886 hba->ufs_stats.last_intr_status, 6887 enabled_intr_status); 6888 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: "); 6889 } 6890 6891 return retval; 6892 } 6893 6894 static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag) 6895 { 6896 int err = 0; 6897 u32 mask = 1 << tag; 6898 unsigned long flags; 6899 6900 if (!test_bit(tag, &hba->outstanding_tasks)) 6901 goto out; 6902 6903 spin_lock_irqsave(hba->host->host_lock, flags); 6904 ufshcd_utmrl_clear(hba, tag); 6905 spin_unlock_irqrestore(hba->host->host_lock, flags); 6906 6907 /* poll for max. 1 sec to clear door bell register by h/w */ 6908 err = ufshcd_wait_for_register(hba, 6909 REG_UTP_TASK_REQ_DOOR_BELL, 6910 mask, 0, 1000, 1000); 6911 6912 dev_err(hba->dev, "Clearing task management function with tag %d %s\n", 6913 tag, err < 0 ? "failed" : "succeeded"); 6914 6915 out: 6916 return err; 6917 } 6918 6919 static int __ufshcd_issue_tm_cmd(struct ufs_hba *hba, 6920 struct utp_task_req_desc *treq, u8 tm_function) 6921 { 6922 struct request_queue *q = hba->tmf_queue; 6923 struct Scsi_Host *host = hba->host; 6924 DECLARE_COMPLETION_ONSTACK(wait); 6925 struct request *req; 6926 unsigned long flags; 6927 int task_tag, err; 6928 6929 /* 6930 * blk_mq_alloc_request() is used here only to get a free tag. 6931 */ 6932 req = blk_mq_alloc_request(q, REQ_OP_DRV_OUT, 0); 6933 if (IS_ERR(req)) 6934 return PTR_ERR(req); 6935 6936 req->end_io_data = &wait; 6937 ufshcd_hold(hba); 6938 6939 spin_lock_irqsave(host->host_lock, flags); 6940 6941 task_tag = req->tag; 6942 WARN_ONCE(task_tag < 0 || task_tag >= hba->nutmrs, "Invalid tag %d\n", 6943 task_tag); 6944 hba->tmf_rqs[req->tag] = req; 6945 treq->upiu_req.req_header.task_tag = task_tag; 6946 6947 memcpy(hba->utmrdl_base_addr + task_tag, treq, sizeof(*treq)); 6948 ufshcd_vops_setup_task_mgmt(hba, task_tag, tm_function); 6949 6950 /* send command to the controller */ 6951 __set_bit(task_tag, &hba->outstanding_tasks); 6952 6953 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TASK_REQ_DOOR_BELL); 6954 /* Make sure that doorbell is committed immediately */ 6955 wmb(); 6956 6957 spin_unlock_irqrestore(host->host_lock, flags); 6958 6959 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_SEND); 6960 6961 /* wait until the task management command is completed */ 6962 err = wait_for_completion_io_timeout(&wait, 6963 msecs_to_jiffies(TM_CMD_TIMEOUT)); 6964 if (!err) { 6965 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_ERR); 6966 dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n", 6967 __func__, tm_function); 6968 if (ufshcd_clear_tm_cmd(hba, task_tag)) 6969 dev_WARN(hba->dev, "%s: unable to clear tm cmd (slot %d) after timeout\n", 6970 __func__, task_tag); 6971 err = -ETIMEDOUT; 6972 } else { 6973 err = 0; 6974 memcpy(treq, hba->utmrdl_base_addr + task_tag, sizeof(*treq)); 6975 6976 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_COMP); 6977 } 6978 6979 spin_lock_irqsave(hba->host->host_lock, flags); 6980 hba->tmf_rqs[req->tag] = NULL; 6981 __clear_bit(task_tag, &hba->outstanding_tasks); 6982 spin_unlock_irqrestore(hba->host->host_lock, flags); 6983 6984 ufshcd_release(hba); 6985 blk_mq_free_request(req); 6986 6987 return err; 6988 } 6989 6990 /** 6991 * ufshcd_issue_tm_cmd - issues task management commands to controller 6992 * @hba: per adapter instance 6993 * @lun_id: LUN ID to which TM command is sent 6994 * @task_id: task ID to which the TM command is applicable 6995 * @tm_function: task management function opcode 6996 * @tm_response: task management service response return value 6997 * 6998 * Return: non-zero value on error, zero on success. 6999 */ 7000 static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id, 7001 u8 tm_function, u8 *tm_response) 7002 { 7003 struct utp_task_req_desc treq = { }; 7004 enum utp_ocs ocs_value; 7005 int err; 7006 7007 /* Configure task request descriptor */ 7008 treq.header.interrupt = 1; 7009 treq.header.ocs = OCS_INVALID_COMMAND_STATUS; 7010 7011 /* Configure task request UPIU */ 7012 treq.upiu_req.req_header.transaction_code = UPIU_TRANSACTION_TASK_REQ; 7013 treq.upiu_req.req_header.lun = lun_id; 7014 treq.upiu_req.req_header.tm_function = tm_function; 7015 7016 /* 7017 * The host shall provide the same value for LUN field in the basic 7018 * header and for Input Parameter. 7019 */ 7020 treq.upiu_req.input_param1 = cpu_to_be32(lun_id); 7021 treq.upiu_req.input_param2 = cpu_to_be32(task_id); 7022 7023 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_function); 7024 if (err == -ETIMEDOUT) 7025 return err; 7026 7027 ocs_value = treq.header.ocs & MASK_OCS; 7028 if (ocs_value != OCS_SUCCESS) 7029 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n", 7030 __func__, ocs_value); 7031 else if (tm_response) 7032 *tm_response = be32_to_cpu(treq.upiu_rsp.output_param1) & 7033 MASK_TM_SERVICE_RESP; 7034 return err; 7035 } 7036 7037 /** 7038 * ufshcd_issue_devman_upiu_cmd - API for sending "utrd" type requests 7039 * @hba: per-adapter instance 7040 * @req_upiu: upiu request 7041 * @rsp_upiu: upiu reply 7042 * @desc_buff: pointer to descriptor buffer, NULL if NA 7043 * @buff_len: descriptor size, 0 if NA 7044 * @cmd_type: specifies the type (NOP, Query...) 7045 * @desc_op: descriptor operation 7046 * 7047 * Those type of requests uses UTP Transfer Request Descriptor - utrd. 7048 * Therefore, it "rides" the device management infrastructure: uses its tag and 7049 * tasks work queues. 7050 * 7051 * Since there is only one available tag for device management commands, 7052 * the caller is expected to hold the hba->dev_cmd.lock mutex. 7053 * 7054 * Return: 0 upon success; < 0 upon failure. 7055 */ 7056 static int ufshcd_issue_devman_upiu_cmd(struct ufs_hba *hba, 7057 struct utp_upiu_req *req_upiu, 7058 struct utp_upiu_req *rsp_upiu, 7059 u8 *desc_buff, int *buff_len, 7060 enum dev_cmd_type cmd_type, 7061 enum query_opcode desc_op) 7062 { 7063 DECLARE_COMPLETION_ONSTACK(wait); 7064 const u32 tag = hba->reserved_slot; 7065 struct ufshcd_lrb *lrbp; 7066 int err = 0; 7067 u8 upiu_flags; 7068 7069 /* Protects use of hba->reserved_slot. */ 7070 lockdep_assert_held(&hba->dev_cmd.lock); 7071 7072 down_read(&hba->clk_scaling_lock); 7073 7074 lrbp = &hba->lrb[tag]; 7075 lrbp->cmd = NULL; 7076 lrbp->task_tag = tag; 7077 lrbp->lun = 0; 7078 lrbp->intr_cmd = true; 7079 ufshcd_prepare_lrbp_crypto(NULL, lrbp); 7080 hba->dev_cmd.type = cmd_type; 7081 7082 if (hba->ufs_version <= ufshci_version(1, 1)) 7083 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE; 7084 else 7085 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE; 7086 7087 /* update the task tag in the request upiu */ 7088 req_upiu->header.task_tag = tag; 7089 7090 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE, 0); 7091 7092 /* just copy the upiu request as it is */ 7093 memcpy(lrbp->ucd_req_ptr, req_upiu, sizeof(*lrbp->ucd_req_ptr)); 7094 if (desc_buff && desc_op == UPIU_QUERY_OPCODE_WRITE_DESC) { 7095 /* The Data Segment Area is optional depending upon the query 7096 * function value. for WRITE DESCRIPTOR, the data segment 7097 * follows right after the tsf. 7098 */ 7099 memcpy(lrbp->ucd_req_ptr + 1, desc_buff, *buff_len); 7100 *buff_len = 0; 7101 } 7102 7103 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 7104 7105 hba->dev_cmd.complete = &wait; 7106 7107 ufshcd_add_query_upiu_trace(hba, UFS_QUERY_SEND, lrbp->ucd_req_ptr); 7108 7109 ufshcd_send_command(hba, tag, hba->dev_cmd_queue); 7110 /* 7111 * ignore the returning value here - ufshcd_check_query_response is 7112 * bound to fail since dev_cmd.query and dev_cmd.type were left empty. 7113 * read the response directly ignoring all errors. 7114 */ 7115 ufshcd_wait_for_dev_cmd(hba, lrbp, QUERY_REQ_TIMEOUT); 7116 7117 /* just copy the upiu response as it is */ 7118 memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu)); 7119 if (desc_buff && desc_op == UPIU_QUERY_OPCODE_READ_DESC) { 7120 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr + sizeof(*rsp_upiu); 7121 u16 resp_len = be16_to_cpu(lrbp->ucd_rsp_ptr->header 7122 .data_segment_length); 7123 7124 if (*buff_len >= resp_len) { 7125 memcpy(desc_buff, descp, resp_len); 7126 *buff_len = resp_len; 7127 } else { 7128 dev_warn(hba->dev, 7129 "%s: rsp size %d is bigger than buffer size %d", 7130 __func__, resp_len, *buff_len); 7131 *buff_len = 0; 7132 err = -EINVAL; 7133 } 7134 } 7135 ufshcd_add_query_upiu_trace(hba, err ? UFS_QUERY_ERR : UFS_QUERY_COMP, 7136 (struct utp_upiu_req *)lrbp->ucd_rsp_ptr); 7137 7138 up_read(&hba->clk_scaling_lock); 7139 return err; 7140 } 7141 7142 /** 7143 * ufshcd_exec_raw_upiu_cmd - API function for sending raw upiu commands 7144 * @hba: per-adapter instance 7145 * @req_upiu: upiu request 7146 * @rsp_upiu: upiu reply - only 8 DW as we do not support scsi commands 7147 * @msgcode: message code, one of UPIU Transaction Codes Initiator to Target 7148 * @desc_buff: pointer to descriptor buffer, NULL if NA 7149 * @buff_len: descriptor size, 0 if NA 7150 * @desc_op: descriptor operation 7151 * 7152 * Supports UTP Transfer requests (nop and query), and UTP Task 7153 * Management requests. 7154 * It is up to the caller to fill the upiu conent properly, as it will 7155 * be copied without any further input validations. 7156 * 7157 * Return: 0 upon success; < 0 upon failure. 7158 */ 7159 int ufshcd_exec_raw_upiu_cmd(struct ufs_hba *hba, 7160 struct utp_upiu_req *req_upiu, 7161 struct utp_upiu_req *rsp_upiu, 7162 enum upiu_request_transaction msgcode, 7163 u8 *desc_buff, int *buff_len, 7164 enum query_opcode desc_op) 7165 { 7166 int err; 7167 enum dev_cmd_type cmd_type = DEV_CMD_TYPE_QUERY; 7168 struct utp_task_req_desc treq = { }; 7169 enum utp_ocs ocs_value; 7170 u8 tm_f = req_upiu->header.tm_function; 7171 7172 switch (msgcode) { 7173 case UPIU_TRANSACTION_NOP_OUT: 7174 cmd_type = DEV_CMD_TYPE_NOP; 7175 fallthrough; 7176 case UPIU_TRANSACTION_QUERY_REQ: 7177 ufshcd_hold(hba); 7178 mutex_lock(&hba->dev_cmd.lock); 7179 err = ufshcd_issue_devman_upiu_cmd(hba, req_upiu, rsp_upiu, 7180 desc_buff, buff_len, 7181 cmd_type, desc_op); 7182 mutex_unlock(&hba->dev_cmd.lock); 7183 ufshcd_release(hba); 7184 7185 break; 7186 case UPIU_TRANSACTION_TASK_REQ: 7187 treq.header.interrupt = 1; 7188 treq.header.ocs = OCS_INVALID_COMMAND_STATUS; 7189 7190 memcpy(&treq.upiu_req, req_upiu, sizeof(*req_upiu)); 7191 7192 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_f); 7193 if (err == -ETIMEDOUT) 7194 break; 7195 7196 ocs_value = treq.header.ocs & MASK_OCS; 7197 if (ocs_value != OCS_SUCCESS) { 7198 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n", __func__, 7199 ocs_value); 7200 break; 7201 } 7202 7203 memcpy(rsp_upiu, &treq.upiu_rsp, sizeof(*rsp_upiu)); 7204 7205 break; 7206 default: 7207 err = -EINVAL; 7208 7209 break; 7210 } 7211 7212 return err; 7213 } 7214 7215 /** 7216 * ufshcd_advanced_rpmb_req_handler - handle advanced RPMB request 7217 * @hba: per adapter instance 7218 * @req_upiu: upiu request 7219 * @rsp_upiu: upiu reply 7220 * @req_ehs: EHS field which contains Advanced RPMB Request Message 7221 * @rsp_ehs: EHS field which returns Advanced RPMB Response Message 7222 * @sg_cnt: The number of sg lists actually used 7223 * @sg_list: Pointer to SG list when DATA IN/OUT UPIU is required in ARPMB operation 7224 * @dir: DMA direction 7225 * 7226 * Return: zero on success, non-zero on failure. 7227 */ 7228 int ufshcd_advanced_rpmb_req_handler(struct ufs_hba *hba, struct utp_upiu_req *req_upiu, 7229 struct utp_upiu_req *rsp_upiu, struct ufs_ehs *req_ehs, 7230 struct ufs_ehs *rsp_ehs, int sg_cnt, struct scatterlist *sg_list, 7231 enum dma_data_direction dir) 7232 { 7233 DECLARE_COMPLETION_ONSTACK(wait); 7234 const u32 tag = hba->reserved_slot; 7235 struct ufshcd_lrb *lrbp; 7236 int err = 0; 7237 int result; 7238 u8 upiu_flags; 7239 u8 *ehs_data; 7240 u16 ehs_len; 7241 7242 /* Protects use of hba->reserved_slot. */ 7243 ufshcd_hold(hba); 7244 mutex_lock(&hba->dev_cmd.lock); 7245 down_read(&hba->clk_scaling_lock); 7246 7247 lrbp = &hba->lrb[tag]; 7248 lrbp->cmd = NULL; 7249 lrbp->task_tag = tag; 7250 lrbp->lun = UFS_UPIU_RPMB_WLUN; 7251 7252 lrbp->intr_cmd = true; 7253 ufshcd_prepare_lrbp_crypto(NULL, lrbp); 7254 hba->dev_cmd.type = DEV_CMD_TYPE_RPMB; 7255 7256 /* Advanced RPMB starts from UFS 4.0, so its command type is UTP_CMD_TYPE_UFS_STORAGE */ 7257 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE; 7258 7259 /* 7260 * According to UFSHCI 4.0 specification page 24, if EHSLUTRDS is 0, host controller takes 7261 * EHS length from CMD UPIU, and SW driver use EHS Length field in CMD UPIU. if it is 1, 7262 * HW controller takes EHS length from UTRD. 7263 */ 7264 if (hba->capabilities & MASK_EHSLUTRD_SUPPORTED) 7265 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, dir, 2); 7266 else 7267 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, dir, 0); 7268 7269 /* update the task tag */ 7270 req_upiu->header.task_tag = tag; 7271 7272 /* copy the UPIU(contains CDB) request as it is */ 7273 memcpy(lrbp->ucd_req_ptr, req_upiu, sizeof(*lrbp->ucd_req_ptr)); 7274 /* Copy EHS, starting with byte32, immediately after the CDB package */ 7275 memcpy(lrbp->ucd_req_ptr + 1, req_ehs, sizeof(*req_ehs)); 7276 7277 if (dir != DMA_NONE && sg_list) 7278 ufshcd_sgl_to_prdt(hba, lrbp, sg_cnt, sg_list); 7279 7280 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 7281 7282 hba->dev_cmd.complete = &wait; 7283 7284 ufshcd_send_command(hba, tag, hba->dev_cmd_queue); 7285 7286 err = ufshcd_wait_for_dev_cmd(hba, lrbp, ADVANCED_RPMB_REQ_TIMEOUT); 7287 7288 if (!err) { 7289 /* Just copy the upiu response as it is */ 7290 memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu)); 7291 /* Get the response UPIU result */ 7292 result = (lrbp->ucd_rsp_ptr->header.response << 8) | 7293 lrbp->ucd_rsp_ptr->header.status; 7294 7295 ehs_len = lrbp->ucd_rsp_ptr->header.ehs_length; 7296 /* 7297 * Since the bLength in EHS indicates the total size of the EHS Header and EHS Data 7298 * in 32 Byte units, the value of the bLength Request/Response for Advanced RPMB 7299 * Message is 02h 7300 */ 7301 if (ehs_len == 2 && rsp_ehs) { 7302 /* 7303 * ucd_rsp_ptr points to a buffer with a length of 512 bytes 7304 * (ALIGNED_UPIU_SIZE = 512), and the EHS data just starts from byte32 7305 */ 7306 ehs_data = (u8 *)lrbp->ucd_rsp_ptr + EHS_OFFSET_IN_RESPONSE; 7307 memcpy(rsp_ehs, ehs_data, ehs_len * 32); 7308 } 7309 } 7310 7311 up_read(&hba->clk_scaling_lock); 7312 mutex_unlock(&hba->dev_cmd.lock); 7313 ufshcd_release(hba); 7314 return err ? : result; 7315 } 7316 7317 /** 7318 * ufshcd_eh_device_reset_handler() - Reset a single logical unit. 7319 * @cmd: SCSI command pointer 7320 * 7321 * Return: SUCCESS or FAILED. 7322 */ 7323 static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd) 7324 { 7325 unsigned long flags, pending_reqs = 0, not_cleared = 0; 7326 struct Scsi_Host *host; 7327 struct ufs_hba *hba; 7328 struct ufs_hw_queue *hwq; 7329 struct ufshcd_lrb *lrbp; 7330 u32 pos, not_cleared_mask = 0; 7331 int err; 7332 u8 resp = 0xF, lun; 7333 7334 host = cmd->device->host; 7335 hba = shost_priv(host); 7336 7337 lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun); 7338 err = ufshcd_issue_tm_cmd(hba, lun, 0, UFS_LOGICAL_RESET, &resp); 7339 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) { 7340 if (!err) 7341 err = resp; 7342 goto out; 7343 } 7344 7345 if (is_mcq_enabled(hba)) { 7346 for (pos = 0; pos < hba->nutrs; pos++) { 7347 lrbp = &hba->lrb[pos]; 7348 if (ufshcd_cmd_inflight(lrbp->cmd) && 7349 lrbp->lun == lun) { 7350 ufshcd_clear_cmd(hba, pos); 7351 hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(lrbp->cmd)); 7352 ufshcd_mcq_poll_cqe_lock(hba, hwq); 7353 } 7354 } 7355 err = 0; 7356 goto out; 7357 } 7358 7359 /* clear the commands that were pending for corresponding LUN */ 7360 spin_lock_irqsave(&hba->outstanding_lock, flags); 7361 for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) 7362 if (hba->lrb[pos].lun == lun) 7363 __set_bit(pos, &pending_reqs); 7364 hba->outstanding_reqs &= ~pending_reqs; 7365 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 7366 7367 for_each_set_bit(pos, &pending_reqs, hba->nutrs) { 7368 if (ufshcd_clear_cmd(hba, pos) < 0) { 7369 spin_lock_irqsave(&hba->outstanding_lock, flags); 7370 not_cleared = 1U << pos & 7371 ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 7372 hba->outstanding_reqs |= not_cleared; 7373 not_cleared_mask |= not_cleared; 7374 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 7375 7376 dev_err(hba->dev, "%s: failed to clear request %d\n", 7377 __func__, pos); 7378 } 7379 } 7380 __ufshcd_transfer_req_compl(hba, pending_reqs & ~not_cleared_mask); 7381 7382 out: 7383 hba->req_abort_count = 0; 7384 ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, (u32)err); 7385 if (!err) { 7386 err = SUCCESS; 7387 } else { 7388 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err); 7389 err = FAILED; 7390 } 7391 return err; 7392 } 7393 7394 static void ufshcd_set_req_abort_skip(struct ufs_hba *hba, unsigned long bitmap) 7395 { 7396 struct ufshcd_lrb *lrbp; 7397 int tag; 7398 7399 for_each_set_bit(tag, &bitmap, hba->nutrs) { 7400 lrbp = &hba->lrb[tag]; 7401 lrbp->req_abort_skip = true; 7402 } 7403 } 7404 7405 /** 7406 * ufshcd_try_to_abort_task - abort a specific task 7407 * @hba: Pointer to adapter instance 7408 * @tag: Task tag/index to be aborted 7409 * 7410 * Abort the pending command in device by sending UFS_ABORT_TASK task management 7411 * command, and in host controller by clearing the door-bell register. There can 7412 * be race between controller sending the command to the device while abort is 7413 * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is 7414 * really issued and then try to abort it. 7415 * 7416 * Return: zero on success, non-zero on failure. 7417 */ 7418 int ufshcd_try_to_abort_task(struct ufs_hba *hba, int tag) 7419 { 7420 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 7421 int err = 0; 7422 int poll_cnt; 7423 u8 resp = 0xF; 7424 u32 reg; 7425 7426 for (poll_cnt = 100; poll_cnt; poll_cnt--) { 7427 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag, 7428 UFS_QUERY_TASK, &resp); 7429 if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) { 7430 /* cmd pending in the device */ 7431 dev_err(hba->dev, "%s: cmd pending in the device. tag = %d\n", 7432 __func__, tag); 7433 break; 7434 } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) { 7435 /* 7436 * cmd not pending in the device, check if it is 7437 * in transition. 7438 */ 7439 dev_err(hba->dev, "%s: cmd at tag %d not pending in the device.\n", 7440 __func__, tag); 7441 if (is_mcq_enabled(hba)) { 7442 /* MCQ mode */ 7443 if (ufshcd_cmd_inflight(lrbp->cmd)) { 7444 /* sleep for max. 200us same delay as in SDB mode */ 7445 usleep_range(100, 200); 7446 continue; 7447 } 7448 /* command completed already */ 7449 dev_err(hba->dev, "%s: cmd at tag=%d is cleared.\n", 7450 __func__, tag); 7451 goto out; 7452 } 7453 7454 /* Single Doorbell Mode */ 7455 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 7456 if (reg & (1 << tag)) { 7457 /* sleep for max. 200us to stabilize */ 7458 usleep_range(100, 200); 7459 continue; 7460 } 7461 /* command completed already */ 7462 dev_err(hba->dev, "%s: cmd at tag %d successfully cleared from DB.\n", 7463 __func__, tag); 7464 goto out; 7465 } else { 7466 dev_err(hba->dev, 7467 "%s: no response from device. tag = %d, err %d\n", 7468 __func__, tag, err); 7469 if (!err) 7470 err = resp; /* service response error */ 7471 goto out; 7472 } 7473 } 7474 7475 if (!poll_cnt) { 7476 err = -EBUSY; 7477 goto out; 7478 } 7479 7480 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag, 7481 UFS_ABORT_TASK, &resp); 7482 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) { 7483 if (!err) { 7484 err = resp; /* service response error */ 7485 dev_err(hba->dev, "%s: issued. tag = %d, err %d\n", 7486 __func__, tag, err); 7487 } 7488 goto out; 7489 } 7490 7491 err = ufshcd_clear_cmd(hba, tag); 7492 if (err) 7493 dev_err(hba->dev, "%s: Failed clearing cmd at tag %d, err %d\n", 7494 __func__, tag, err); 7495 7496 out: 7497 return err; 7498 } 7499 7500 /** 7501 * ufshcd_abort - scsi host template eh_abort_handler callback 7502 * @cmd: SCSI command pointer 7503 * 7504 * Return: SUCCESS or FAILED. 7505 */ 7506 static int ufshcd_abort(struct scsi_cmnd *cmd) 7507 { 7508 struct Scsi_Host *host = cmd->device->host; 7509 struct ufs_hba *hba = shost_priv(host); 7510 int tag = scsi_cmd_to_rq(cmd)->tag; 7511 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 7512 unsigned long flags; 7513 int err = FAILED; 7514 bool outstanding; 7515 u32 reg; 7516 7517 WARN_ONCE(tag < 0, "Invalid tag %d\n", tag); 7518 7519 ufshcd_hold(hba); 7520 7521 if (!is_mcq_enabled(hba)) { 7522 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 7523 if (!test_bit(tag, &hba->outstanding_reqs)) { 7524 /* If command is already aborted/completed, return FAILED. */ 7525 dev_err(hba->dev, 7526 "%s: cmd at tag %d already completed, outstanding=0x%lx, doorbell=0x%x\n", 7527 __func__, tag, hba->outstanding_reqs, reg); 7528 goto release; 7529 } 7530 } 7531 7532 /* Print Transfer Request of aborted task */ 7533 dev_info(hba->dev, "%s: Device abort task at tag %d\n", __func__, tag); 7534 7535 /* 7536 * Print detailed info about aborted request. 7537 * As more than one request might get aborted at the same time, 7538 * print full information only for the first aborted request in order 7539 * to reduce repeated printouts. For other aborted requests only print 7540 * basic details. 7541 */ 7542 scsi_print_command(cmd); 7543 if (!hba->req_abort_count) { 7544 ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, tag); 7545 ufshcd_print_evt_hist(hba); 7546 ufshcd_print_host_state(hba); 7547 ufshcd_print_pwr_info(hba); 7548 ufshcd_print_tr(hba, tag, true); 7549 } else { 7550 ufshcd_print_tr(hba, tag, false); 7551 } 7552 hba->req_abort_count++; 7553 7554 if (!is_mcq_enabled(hba) && !(reg & (1 << tag))) { 7555 /* only execute this code in single doorbell mode */ 7556 dev_err(hba->dev, 7557 "%s: cmd was completed, but without a notifying intr, tag = %d", 7558 __func__, tag); 7559 __ufshcd_transfer_req_compl(hba, 1UL << tag); 7560 goto release; 7561 } 7562 7563 /* 7564 * Task abort to the device W-LUN is illegal. When this command 7565 * will fail, due to spec violation, scsi err handling next step 7566 * will be to send LU reset which, again, is a spec violation. 7567 * To avoid these unnecessary/illegal steps, first we clean up 7568 * the lrb taken by this cmd and re-set it in outstanding_reqs, 7569 * then queue the eh_work and bail. 7570 */ 7571 if (lrbp->lun == UFS_UPIU_UFS_DEVICE_WLUN) { 7572 ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, lrbp->lun); 7573 7574 spin_lock_irqsave(host->host_lock, flags); 7575 hba->force_reset = true; 7576 ufshcd_schedule_eh_work(hba); 7577 spin_unlock_irqrestore(host->host_lock, flags); 7578 goto release; 7579 } 7580 7581 if (is_mcq_enabled(hba)) { 7582 /* MCQ mode. Branch off to handle abort for mcq mode */ 7583 err = ufshcd_mcq_abort(cmd); 7584 goto release; 7585 } 7586 7587 /* Skip task abort in case previous aborts failed and report failure */ 7588 if (lrbp->req_abort_skip) { 7589 dev_err(hba->dev, "%s: skipping abort\n", __func__); 7590 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs); 7591 goto release; 7592 } 7593 7594 err = ufshcd_try_to_abort_task(hba, tag); 7595 if (err) { 7596 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err); 7597 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs); 7598 err = FAILED; 7599 goto release; 7600 } 7601 7602 /* 7603 * Clear the corresponding bit from outstanding_reqs since the command 7604 * has been aborted successfully. 7605 */ 7606 spin_lock_irqsave(&hba->outstanding_lock, flags); 7607 outstanding = __test_and_clear_bit(tag, &hba->outstanding_reqs); 7608 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 7609 7610 if (outstanding) 7611 ufshcd_release_scsi_cmd(hba, lrbp); 7612 7613 err = SUCCESS; 7614 7615 release: 7616 /* Matches the ufshcd_hold() call at the start of this function. */ 7617 ufshcd_release(hba); 7618 return err; 7619 } 7620 7621 /** 7622 * ufshcd_host_reset_and_restore - reset and restore host controller 7623 * @hba: per-adapter instance 7624 * 7625 * Note that host controller reset may issue DME_RESET to 7626 * local and remote (device) Uni-Pro stack and the attributes 7627 * are reset to default state. 7628 * 7629 * Return: zero on success, non-zero on failure. 7630 */ 7631 static int ufshcd_host_reset_and_restore(struct ufs_hba *hba) 7632 { 7633 int err; 7634 7635 /* 7636 * Stop the host controller and complete the requests 7637 * cleared by h/w 7638 */ 7639 ufshcd_hba_stop(hba); 7640 hba->silence_err_logs = true; 7641 ufshcd_complete_requests(hba, true); 7642 hba->silence_err_logs = false; 7643 7644 /* scale up clocks to max frequency before full reinitialization */ 7645 ufshcd_scale_clks(hba, true); 7646 7647 err = ufshcd_hba_enable(hba); 7648 7649 /* Establish the link again and restore the device */ 7650 if (!err) 7651 err = ufshcd_probe_hba(hba, false); 7652 7653 if (err) 7654 dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err); 7655 ufshcd_update_evt_hist(hba, UFS_EVT_HOST_RESET, (u32)err); 7656 return err; 7657 } 7658 7659 /** 7660 * ufshcd_reset_and_restore - reset and re-initialize host/device 7661 * @hba: per-adapter instance 7662 * 7663 * Reset and recover device, host and re-establish link. This 7664 * is helpful to recover the communication in fatal error conditions. 7665 * 7666 * Return: zero on success, non-zero on failure. 7667 */ 7668 static int ufshcd_reset_and_restore(struct ufs_hba *hba) 7669 { 7670 u32 saved_err = 0; 7671 u32 saved_uic_err = 0; 7672 int err = 0; 7673 unsigned long flags; 7674 int retries = MAX_HOST_RESET_RETRIES; 7675 7676 spin_lock_irqsave(hba->host->host_lock, flags); 7677 do { 7678 /* 7679 * This is a fresh start, cache and clear saved error first, 7680 * in case new error generated during reset and restore. 7681 */ 7682 saved_err |= hba->saved_err; 7683 saved_uic_err |= hba->saved_uic_err; 7684 hba->saved_err = 0; 7685 hba->saved_uic_err = 0; 7686 hba->force_reset = false; 7687 hba->ufshcd_state = UFSHCD_STATE_RESET; 7688 spin_unlock_irqrestore(hba->host->host_lock, flags); 7689 7690 /* Reset the attached device */ 7691 ufshcd_device_reset(hba); 7692 7693 err = ufshcd_host_reset_and_restore(hba); 7694 7695 spin_lock_irqsave(hba->host->host_lock, flags); 7696 if (err) 7697 continue; 7698 /* Do not exit unless operational or dead */ 7699 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL && 7700 hba->ufshcd_state != UFSHCD_STATE_ERROR && 7701 hba->ufshcd_state != UFSHCD_STATE_EH_SCHEDULED_NON_FATAL) 7702 err = -EAGAIN; 7703 } while (err && --retries); 7704 7705 /* 7706 * Inform scsi mid-layer that we did reset and allow to handle 7707 * Unit Attention properly. 7708 */ 7709 scsi_report_bus_reset(hba->host, 0); 7710 if (err) { 7711 hba->ufshcd_state = UFSHCD_STATE_ERROR; 7712 hba->saved_err |= saved_err; 7713 hba->saved_uic_err |= saved_uic_err; 7714 } 7715 spin_unlock_irqrestore(hba->host->host_lock, flags); 7716 7717 return err; 7718 } 7719 7720 /** 7721 * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer 7722 * @cmd: SCSI command pointer 7723 * 7724 * Return: SUCCESS or FAILED. 7725 */ 7726 static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd) 7727 { 7728 int err = SUCCESS; 7729 unsigned long flags; 7730 struct ufs_hba *hba; 7731 7732 hba = shost_priv(cmd->device->host); 7733 7734 spin_lock_irqsave(hba->host->host_lock, flags); 7735 hba->force_reset = true; 7736 ufshcd_schedule_eh_work(hba); 7737 dev_err(hba->dev, "%s: reset in progress - 1\n", __func__); 7738 spin_unlock_irqrestore(hba->host->host_lock, flags); 7739 7740 flush_work(&hba->eh_work); 7741 7742 spin_lock_irqsave(hba->host->host_lock, flags); 7743 if (hba->ufshcd_state == UFSHCD_STATE_ERROR) 7744 err = FAILED; 7745 spin_unlock_irqrestore(hba->host->host_lock, flags); 7746 7747 return err; 7748 } 7749 7750 /** 7751 * ufshcd_get_max_icc_level - calculate the ICC level 7752 * @sup_curr_uA: max. current supported by the regulator 7753 * @start_scan: row at the desc table to start scan from 7754 * @buff: power descriptor buffer 7755 * 7756 * Return: calculated max ICC level for specific regulator. 7757 */ 7758 static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan, 7759 const char *buff) 7760 { 7761 int i; 7762 int curr_uA; 7763 u16 data; 7764 u16 unit; 7765 7766 for (i = start_scan; i >= 0; i--) { 7767 data = get_unaligned_be16(&buff[2 * i]); 7768 unit = (data & ATTR_ICC_LVL_UNIT_MASK) >> 7769 ATTR_ICC_LVL_UNIT_OFFSET; 7770 curr_uA = data & ATTR_ICC_LVL_VALUE_MASK; 7771 switch (unit) { 7772 case UFSHCD_NANO_AMP: 7773 curr_uA = curr_uA / 1000; 7774 break; 7775 case UFSHCD_MILI_AMP: 7776 curr_uA = curr_uA * 1000; 7777 break; 7778 case UFSHCD_AMP: 7779 curr_uA = curr_uA * 1000 * 1000; 7780 break; 7781 case UFSHCD_MICRO_AMP: 7782 default: 7783 break; 7784 } 7785 if (sup_curr_uA >= curr_uA) 7786 break; 7787 } 7788 if (i < 0) { 7789 i = 0; 7790 pr_err("%s: Couldn't find valid icc_level = %d", __func__, i); 7791 } 7792 7793 return (u32)i; 7794 } 7795 7796 /** 7797 * ufshcd_find_max_sup_active_icc_level - calculate the max ICC level 7798 * In case regulators are not initialized we'll return 0 7799 * @hba: per-adapter instance 7800 * @desc_buf: power descriptor buffer to extract ICC levels from. 7801 * 7802 * Return: calculated ICC level. 7803 */ 7804 static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba, 7805 const u8 *desc_buf) 7806 { 7807 u32 icc_level = 0; 7808 7809 if (!hba->vreg_info.vcc || !hba->vreg_info.vccq || 7810 !hba->vreg_info.vccq2) { 7811 /* 7812 * Using dev_dbg to avoid messages during runtime PM to avoid 7813 * never-ending cycles of messages written back to storage by 7814 * user space causing runtime resume, causing more messages and 7815 * so on. 7816 */ 7817 dev_dbg(hba->dev, 7818 "%s: Regulator capability was not set, actvIccLevel=%d", 7819 __func__, icc_level); 7820 goto out; 7821 } 7822 7823 if (hba->vreg_info.vcc->max_uA) 7824 icc_level = ufshcd_get_max_icc_level( 7825 hba->vreg_info.vcc->max_uA, 7826 POWER_DESC_MAX_ACTV_ICC_LVLS - 1, 7827 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]); 7828 7829 if (hba->vreg_info.vccq->max_uA) 7830 icc_level = ufshcd_get_max_icc_level( 7831 hba->vreg_info.vccq->max_uA, 7832 icc_level, 7833 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]); 7834 7835 if (hba->vreg_info.vccq2->max_uA) 7836 icc_level = ufshcd_get_max_icc_level( 7837 hba->vreg_info.vccq2->max_uA, 7838 icc_level, 7839 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]); 7840 out: 7841 return icc_level; 7842 } 7843 7844 static void ufshcd_set_active_icc_lvl(struct ufs_hba *hba) 7845 { 7846 int ret; 7847 u8 *desc_buf; 7848 u32 icc_level; 7849 7850 desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL); 7851 if (!desc_buf) 7852 return; 7853 7854 ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_POWER, 0, 0, 7855 desc_buf, QUERY_DESC_MAX_SIZE); 7856 if (ret) { 7857 dev_err(hba->dev, 7858 "%s: Failed reading power descriptor ret = %d", 7859 __func__, ret); 7860 goto out; 7861 } 7862 7863 icc_level = ufshcd_find_max_sup_active_icc_level(hba, desc_buf); 7864 dev_dbg(hba->dev, "%s: setting icc_level 0x%x", __func__, icc_level); 7865 7866 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, 7867 QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0, &icc_level); 7868 7869 if (ret) 7870 dev_err(hba->dev, 7871 "%s: Failed configuring bActiveICCLevel = %d ret = %d", 7872 __func__, icc_level, ret); 7873 7874 out: 7875 kfree(desc_buf); 7876 } 7877 7878 static inline void ufshcd_blk_pm_runtime_init(struct scsi_device *sdev) 7879 { 7880 scsi_autopm_get_device(sdev); 7881 blk_pm_runtime_init(sdev->request_queue, &sdev->sdev_gendev); 7882 if (sdev->rpm_autosuspend) 7883 pm_runtime_set_autosuspend_delay(&sdev->sdev_gendev, 7884 RPM_AUTOSUSPEND_DELAY_MS); 7885 scsi_autopm_put_device(sdev); 7886 } 7887 7888 /** 7889 * ufshcd_scsi_add_wlus - Adds required W-LUs 7890 * @hba: per-adapter instance 7891 * 7892 * UFS device specification requires the UFS devices to support 4 well known 7893 * logical units: 7894 * "REPORT_LUNS" (address: 01h) 7895 * "UFS Device" (address: 50h) 7896 * "RPMB" (address: 44h) 7897 * "BOOT" (address: 30h) 7898 * UFS device's power management needs to be controlled by "POWER CONDITION" 7899 * field of SSU (START STOP UNIT) command. But this "power condition" field 7900 * will take effect only when its sent to "UFS device" well known logical unit 7901 * hence we require the scsi_device instance to represent this logical unit in 7902 * order for the UFS host driver to send the SSU command for power management. 7903 * 7904 * We also require the scsi_device instance for "RPMB" (Replay Protected Memory 7905 * Block) LU so user space process can control this LU. User space may also 7906 * want to have access to BOOT LU. 7907 * 7908 * This function adds scsi device instances for each of all well known LUs 7909 * (except "REPORT LUNS" LU). 7910 * 7911 * Return: zero on success (all required W-LUs are added successfully), 7912 * non-zero error value on failure (if failed to add any of the required W-LU). 7913 */ 7914 static int ufshcd_scsi_add_wlus(struct ufs_hba *hba) 7915 { 7916 int ret = 0; 7917 struct scsi_device *sdev_boot, *sdev_rpmb; 7918 7919 hba->ufs_device_wlun = __scsi_add_device(hba->host, 0, 0, 7920 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL); 7921 if (IS_ERR(hba->ufs_device_wlun)) { 7922 ret = PTR_ERR(hba->ufs_device_wlun); 7923 hba->ufs_device_wlun = NULL; 7924 goto out; 7925 } 7926 scsi_device_put(hba->ufs_device_wlun); 7927 7928 sdev_rpmb = __scsi_add_device(hba->host, 0, 0, 7929 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL); 7930 if (IS_ERR(sdev_rpmb)) { 7931 ret = PTR_ERR(sdev_rpmb); 7932 goto remove_ufs_device_wlun; 7933 } 7934 ufshcd_blk_pm_runtime_init(sdev_rpmb); 7935 scsi_device_put(sdev_rpmb); 7936 7937 sdev_boot = __scsi_add_device(hba->host, 0, 0, 7938 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL); 7939 if (IS_ERR(sdev_boot)) { 7940 dev_err(hba->dev, "%s: BOOT WLUN not found\n", __func__); 7941 } else { 7942 ufshcd_blk_pm_runtime_init(sdev_boot); 7943 scsi_device_put(sdev_boot); 7944 } 7945 goto out; 7946 7947 remove_ufs_device_wlun: 7948 scsi_remove_device(hba->ufs_device_wlun); 7949 out: 7950 return ret; 7951 } 7952 7953 static void ufshcd_wb_probe(struct ufs_hba *hba, const u8 *desc_buf) 7954 { 7955 struct ufs_dev_info *dev_info = &hba->dev_info; 7956 u8 lun; 7957 u32 d_lu_wb_buf_alloc; 7958 u32 ext_ufs_feature; 7959 7960 if (!ufshcd_is_wb_allowed(hba)) 7961 return; 7962 7963 /* 7964 * Probe WB only for UFS-2.2 and UFS-3.1 (and later) devices or 7965 * UFS devices with quirk UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES 7966 * enabled 7967 */ 7968 if (!(dev_info->wspecversion >= 0x310 || 7969 dev_info->wspecversion == 0x220 || 7970 (hba->dev_quirks & UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES))) 7971 goto wb_disabled; 7972 7973 ext_ufs_feature = get_unaligned_be32(desc_buf + 7974 DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP); 7975 7976 if (!(ext_ufs_feature & UFS_DEV_WRITE_BOOSTER_SUP)) 7977 goto wb_disabled; 7978 7979 /* 7980 * WB may be supported but not configured while provisioning. The spec 7981 * says, in dedicated wb buffer mode, a max of 1 lun would have wb 7982 * buffer configured. 7983 */ 7984 dev_info->wb_buffer_type = desc_buf[DEVICE_DESC_PARAM_WB_TYPE]; 7985 7986 dev_info->b_presrv_uspc_en = 7987 desc_buf[DEVICE_DESC_PARAM_WB_PRESRV_USRSPC_EN]; 7988 7989 if (dev_info->wb_buffer_type == WB_BUF_MODE_SHARED) { 7990 if (!get_unaligned_be32(desc_buf + 7991 DEVICE_DESC_PARAM_WB_SHARED_ALLOC_UNITS)) 7992 goto wb_disabled; 7993 } else { 7994 for (lun = 0; lun < UFS_UPIU_MAX_WB_LUN_ID; lun++) { 7995 d_lu_wb_buf_alloc = 0; 7996 ufshcd_read_unit_desc_param(hba, 7997 lun, 7998 UNIT_DESC_PARAM_WB_BUF_ALLOC_UNITS, 7999 (u8 *)&d_lu_wb_buf_alloc, 8000 sizeof(d_lu_wb_buf_alloc)); 8001 if (d_lu_wb_buf_alloc) { 8002 dev_info->wb_dedicated_lu = lun; 8003 break; 8004 } 8005 } 8006 8007 if (!d_lu_wb_buf_alloc) 8008 goto wb_disabled; 8009 } 8010 8011 if (!ufshcd_is_wb_buf_lifetime_available(hba)) 8012 goto wb_disabled; 8013 8014 return; 8015 8016 wb_disabled: 8017 hba->caps &= ~UFSHCD_CAP_WB_EN; 8018 } 8019 8020 static void ufshcd_temp_notif_probe(struct ufs_hba *hba, const u8 *desc_buf) 8021 { 8022 struct ufs_dev_info *dev_info = &hba->dev_info; 8023 u32 ext_ufs_feature; 8024 u8 mask = 0; 8025 8026 if (!(hba->caps & UFSHCD_CAP_TEMP_NOTIF) || dev_info->wspecversion < 0x300) 8027 return; 8028 8029 ext_ufs_feature = get_unaligned_be32(desc_buf + DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP); 8030 8031 if (ext_ufs_feature & UFS_DEV_LOW_TEMP_NOTIF) 8032 mask |= MASK_EE_TOO_LOW_TEMP; 8033 8034 if (ext_ufs_feature & UFS_DEV_HIGH_TEMP_NOTIF) 8035 mask |= MASK_EE_TOO_HIGH_TEMP; 8036 8037 if (mask) { 8038 ufshcd_enable_ee(hba, mask); 8039 ufs_hwmon_probe(hba, mask); 8040 } 8041 } 8042 8043 static void ufshcd_ext_iid_probe(struct ufs_hba *hba, u8 *desc_buf) 8044 { 8045 struct ufs_dev_info *dev_info = &hba->dev_info; 8046 u32 ext_ufs_feature; 8047 u32 ext_iid_en = 0; 8048 int err; 8049 8050 /* Only UFS-4.0 and above may support EXT_IID */ 8051 if (dev_info->wspecversion < 0x400) 8052 goto out; 8053 8054 ext_ufs_feature = get_unaligned_be32(desc_buf + 8055 DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP); 8056 if (!(ext_ufs_feature & UFS_DEV_EXT_IID_SUP)) 8057 goto out; 8058 8059 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 8060 QUERY_ATTR_IDN_EXT_IID_EN, 0, 0, &ext_iid_en); 8061 if (err) 8062 dev_err(hba->dev, "failed reading bEXTIIDEn. err = %d\n", err); 8063 8064 out: 8065 dev_info->b_ext_iid_en = ext_iid_en; 8066 } 8067 8068 void ufshcd_fixup_dev_quirks(struct ufs_hba *hba, 8069 const struct ufs_dev_quirk *fixups) 8070 { 8071 const struct ufs_dev_quirk *f; 8072 struct ufs_dev_info *dev_info = &hba->dev_info; 8073 8074 if (!fixups) 8075 return; 8076 8077 for (f = fixups; f->quirk; f++) { 8078 if ((f->wmanufacturerid == dev_info->wmanufacturerid || 8079 f->wmanufacturerid == UFS_ANY_VENDOR) && 8080 ((dev_info->model && 8081 STR_PRFX_EQUAL(f->model, dev_info->model)) || 8082 !strcmp(f->model, UFS_ANY_MODEL))) 8083 hba->dev_quirks |= f->quirk; 8084 } 8085 } 8086 EXPORT_SYMBOL_GPL(ufshcd_fixup_dev_quirks); 8087 8088 static void ufs_fixup_device_setup(struct ufs_hba *hba) 8089 { 8090 /* fix by general quirk table */ 8091 ufshcd_fixup_dev_quirks(hba, ufs_fixups); 8092 8093 /* allow vendors to fix quirks */ 8094 ufshcd_vops_fixup_dev_quirks(hba); 8095 } 8096 8097 static int ufs_get_device_desc(struct ufs_hba *hba) 8098 { 8099 int err; 8100 u8 model_index; 8101 u8 *desc_buf; 8102 struct ufs_dev_info *dev_info = &hba->dev_info; 8103 8104 desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL); 8105 if (!desc_buf) { 8106 err = -ENOMEM; 8107 goto out; 8108 } 8109 8110 err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_DEVICE, 0, 0, desc_buf, 8111 QUERY_DESC_MAX_SIZE); 8112 if (err) { 8113 dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n", 8114 __func__, err); 8115 goto out; 8116 } 8117 8118 /* 8119 * getting vendor (manufacturerID) and Bank Index in big endian 8120 * format 8121 */ 8122 dev_info->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 | 8123 desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1]; 8124 8125 /* getting Specification Version in big endian format */ 8126 dev_info->wspecversion = desc_buf[DEVICE_DESC_PARAM_SPEC_VER] << 8 | 8127 desc_buf[DEVICE_DESC_PARAM_SPEC_VER + 1]; 8128 dev_info->bqueuedepth = desc_buf[DEVICE_DESC_PARAM_Q_DPTH]; 8129 8130 model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME]; 8131 8132 err = ufshcd_read_string_desc(hba, model_index, 8133 &dev_info->model, SD_ASCII_STD); 8134 if (err < 0) { 8135 dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n", 8136 __func__, err); 8137 goto out; 8138 } 8139 8140 hba->luns_avail = desc_buf[DEVICE_DESC_PARAM_NUM_LU] + 8141 desc_buf[DEVICE_DESC_PARAM_NUM_WLU]; 8142 8143 ufs_fixup_device_setup(hba); 8144 8145 ufshcd_wb_probe(hba, desc_buf); 8146 8147 ufshcd_temp_notif_probe(hba, desc_buf); 8148 8149 if (hba->ext_iid_sup) 8150 ufshcd_ext_iid_probe(hba, desc_buf); 8151 8152 /* 8153 * ufshcd_read_string_desc returns size of the string 8154 * reset the error value 8155 */ 8156 err = 0; 8157 8158 out: 8159 kfree(desc_buf); 8160 return err; 8161 } 8162 8163 static void ufs_put_device_desc(struct ufs_hba *hba) 8164 { 8165 struct ufs_dev_info *dev_info = &hba->dev_info; 8166 8167 kfree(dev_info->model); 8168 dev_info->model = NULL; 8169 } 8170 8171 /** 8172 * ufshcd_tune_pa_tactivate - Tunes PA_TActivate of local UniPro 8173 * @hba: per-adapter instance 8174 * 8175 * PA_TActivate parameter can be tuned manually if UniPro version is less than 8176 * 1.61. PA_TActivate needs to be greater than or equal to peerM-PHY's 8177 * RX_MIN_ACTIVATETIME_CAPABILITY attribute. This optimal value can help reduce 8178 * the hibern8 exit latency. 8179 * 8180 * Return: zero on success, non-zero error value on failure. 8181 */ 8182 static int ufshcd_tune_pa_tactivate(struct ufs_hba *hba) 8183 { 8184 int ret = 0; 8185 u32 peer_rx_min_activatetime = 0, tuned_pa_tactivate; 8186 8187 ret = ufshcd_dme_peer_get(hba, 8188 UIC_ARG_MIB_SEL( 8189 RX_MIN_ACTIVATETIME_CAPABILITY, 8190 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)), 8191 &peer_rx_min_activatetime); 8192 if (ret) 8193 goto out; 8194 8195 /* make sure proper unit conversion is applied */ 8196 tuned_pa_tactivate = 8197 ((peer_rx_min_activatetime * RX_MIN_ACTIVATETIME_UNIT_US) 8198 / PA_TACTIVATE_TIME_UNIT_US); 8199 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 8200 tuned_pa_tactivate); 8201 8202 out: 8203 return ret; 8204 } 8205 8206 /** 8207 * ufshcd_tune_pa_hibern8time - Tunes PA_Hibern8Time of local UniPro 8208 * @hba: per-adapter instance 8209 * 8210 * PA_Hibern8Time parameter can be tuned manually if UniPro version is less than 8211 * 1.61. PA_Hibern8Time needs to be maximum of local M-PHY's 8212 * TX_HIBERN8TIME_CAPABILITY & peer M-PHY's RX_HIBERN8TIME_CAPABILITY. 8213 * This optimal value can help reduce the hibern8 exit latency. 8214 * 8215 * Return: zero on success, non-zero error value on failure. 8216 */ 8217 static int ufshcd_tune_pa_hibern8time(struct ufs_hba *hba) 8218 { 8219 int ret = 0; 8220 u32 local_tx_hibern8_time_cap = 0, peer_rx_hibern8_time_cap = 0; 8221 u32 max_hibern8_time, tuned_pa_hibern8time; 8222 8223 ret = ufshcd_dme_get(hba, 8224 UIC_ARG_MIB_SEL(TX_HIBERN8TIME_CAPABILITY, 8225 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), 8226 &local_tx_hibern8_time_cap); 8227 if (ret) 8228 goto out; 8229 8230 ret = ufshcd_dme_peer_get(hba, 8231 UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAPABILITY, 8232 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)), 8233 &peer_rx_hibern8_time_cap); 8234 if (ret) 8235 goto out; 8236 8237 max_hibern8_time = max(local_tx_hibern8_time_cap, 8238 peer_rx_hibern8_time_cap); 8239 /* make sure proper unit conversion is applied */ 8240 tuned_pa_hibern8time = ((max_hibern8_time * HIBERN8TIME_UNIT_US) 8241 / PA_HIBERN8_TIME_UNIT_US); 8242 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME), 8243 tuned_pa_hibern8time); 8244 out: 8245 return ret; 8246 } 8247 8248 /** 8249 * ufshcd_quirk_tune_host_pa_tactivate - Ensures that host PA_TACTIVATE is 8250 * less than device PA_TACTIVATE time. 8251 * @hba: per-adapter instance 8252 * 8253 * Some UFS devices require host PA_TACTIVATE to be lower than device 8254 * PA_TACTIVATE, we need to enable UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE quirk 8255 * for such devices. 8256 * 8257 * Return: zero on success, non-zero error value on failure. 8258 */ 8259 static int ufshcd_quirk_tune_host_pa_tactivate(struct ufs_hba *hba) 8260 { 8261 int ret = 0; 8262 u32 granularity, peer_granularity; 8263 u32 pa_tactivate, peer_pa_tactivate; 8264 u32 pa_tactivate_us, peer_pa_tactivate_us; 8265 static const u8 gran_to_us_table[] = {1, 4, 8, 16, 32, 100}; 8266 8267 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY), 8268 &granularity); 8269 if (ret) 8270 goto out; 8271 8272 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY), 8273 &peer_granularity); 8274 if (ret) 8275 goto out; 8276 8277 if ((granularity < PA_GRANULARITY_MIN_VAL) || 8278 (granularity > PA_GRANULARITY_MAX_VAL)) { 8279 dev_err(hba->dev, "%s: invalid host PA_GRANULARITY %d", 8280 __func__, granularity); 8281 return -EINVAL; 8282 } 8283 8284 if ((peer_granularity < PA_GRANULARITY_MIN_VAL) || 8285 (peer_granularity > PA_GRANULARITY_MAX_VAL)) { 8286 dev_err(hba->dev, "%s: invalid device PA_GRANULARITY %d", 8287 __func__, peer_granularity); 8288 return -EINVAL; 8289 } 8290 8291 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate); 8292 if (ret) 8293 goto out; 8294 8295 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE), 8296 &peer_pa_tactivate); 8297 if (ret) 8298 goto out; 8299 8300 pa_tactivate_us = pa_tactivate * gran_to_us_table[granularity - 1]; 8301 peer_pa_tactivate_us = peer_pa_tactivate * 8302 gran_to_us_table[peer_granularity - 1]; 8303 8304 if (pa_tactivate_us >= peer_pa_tactivate_us) { 8305 u32 new_peer_pa_tactivate; 8306 8307 new_peer_pa_tactivate = pa_tactivate_us / 8308 gran_to_us_table[peer_granularity - 1]; 8309 new_peer_pa_tactivate++; 8310 ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 8311 new_peer_pa_tactivate); 8312 } 8313 8314 out: 8315 return ret; 8316 } 8317 8318 static void ufshcd_tune_unipro_params(struct ufs_hba *hba) 8319 { 8320 if (ufshcd_is_unipro_pa_params_tuning_req(hba)) { 8321 ufshcd_tune_pa_tactivate(hba); 8322 ufshcd_tune_pa_hibern8time(hba); 8323 } 8324 8325 ufshcd_vops_apply_dev_quirks(hba); 8326 8327 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TACTIVATE) 8328 /* set 1ms timeout for PA_TACTIVATE */ 8329 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 10); 8330 8331 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE) 8332 ufshcd_quirk_tune_host_pa_tactivate(hba); 8333 } 8334 8335 static void ufshcd_clear_dbg_ufs_stats(struct ufs_hba *hba) 8336 { 8337 hba->ufs_stats.hibern8_exit_cnt = 0; 8338 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0); 8339 hba->req_abort_count = 0; 8340 } 8341 8342 static int ufshcd_device_geo_params_init(struct ufs_hba *hba) 8343 { 8344 int err; 8345 u8 *desc_buf; 8346 8347 desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL); 8348 if (!desc_buf) { 8349 err = -ENOMEM; 8350 goto out; 8351 } 8352 8353 err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_GEOMETRY, 0, 0, 8354 desc_buf, QUERY_DESC_MAX_SIZE); 8355 if (err) { 8356 dev_err(hba->dev, "%s: Failed reading Geometry Desc. err = %d\n", 8357 __func__, err); 8358 goto out; 8359 } 8360 8361 if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 1) 8362 hba->dev_info.max_lu_supported = 32; 8363 else if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 0) 8364 hba->dev_info.max_lu_supported = 8; 8365 8366 out: 8367 kfree(desc_buf); 8368 return err; 8369 } 8370 8371 struct ufs_ref_clk { 8372 unsigned long freq_hz; 8373 enum ufs_ref_clk_freq val; 8374 }; 8375 8376 static const struct ufs_ref_clk ufs_ref_clk_freqs[] = { 8377 {19200000, REF_CLK_FREQ_19_2_MHZ}, 8378 {26000000, REF_CLK_FREQ_26_MHZ}, 8379 {38400000, REF_CLK_FREQ_38_4_MHZ}, 8380 {52000000, REF_CLK_FREQ_52_MHZ}, 8381 {0, REF_CLK_FREQ_INVAL}, 8382 }; 8383 8384 static enum ufs_ref_clk_freq 8385 ufs_get_bref_clk_from_hz(unsigned long freq) 8386 { 8387 int i; 8388 8389 for (i = 0; ufs_ref_clk_freqs[i].freq_hz; i++) 8390 if (ufs_ref_clk_freqs[i].freq_hz == freq) 8391 return ufs_ref_clk_freqs[i].val; 8392 8393 return REF_CLK_FREQ_INVAL; 8394 } 8395 8396 void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk) 8397 { 8398 unsigned long freq; 8399 8400 freq = clk_get_rate(refclk); 8401 8402 hba->dev_ref_clk_freq = 8403 ufs_get_bref_clk_from_hz(freq); 8404 8405 if (hba->dev_ref_clk_freq == REF_CLK_FREQ_INVAL) 8406 dev_err(hba->dev, 8407 "invalid ref_clk setting = %ld\n", freq); 8408 } 8409 8410 static int ufshcd_set_dev_ref_clk(struct ufs_hba *hba) 8411 { 8412 int err; 8413 u32 ref_clk; 8414 u32 freq = hba->dev_ref_clk_freq; 8415 8416 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 8417 QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &ref_clk); 8418 8419 if (err) { 8420 dev_err(hba->dev, "failed reading bRefClkFreq. err = %d\n", 8421 err); 8422 goto out; 8423 } 8424 8425 if (ref_clk == freq) 8426 goto out; /* nothing to update */ 8427 8428 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, 8429 QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &freq); 8430 8431 if (err) { 8432 dev_err(hba->dev, "bRefClkFreq setting to %lu Hz failed\n", 8433 ufs_ref_clk_freqs[freq].freq_hz); 8434 goto out; 8435 } 8436 8437 dev_dbg(hba->dev, "bRefClkFreq setting to %lu Hz succeeded\n", 8438 ufs_ref_clk_freqs[freq].freq_hz); 8439 8440 out: 8441 return err; 8442 } 8443 8444 static int ufshcd_device_params_init(struct ufs_hba *hba) 8445 { 8446 bool flag; 8447 int ret; 8448 8449 /* Init UFS geometry descriptor related parameters */ 8450 ret = ufshcd_device_geo_params_init(hba); 8451 if (ret) 8452 goto out; 8453 8454 /* Check and apply UFS device quirks */ 8455 ret = ufs_get_device_desc(hba); 8456 if (ret) { 8457 dev_err(hba->dev, "%s: Failed getting device info. err = %d\n", 8458 __func__, ret); 8459 goto out; 8460 } 8461 8462 ufshcd_get_ref_clk_gating_wait(hba); 8463 8464 if (!ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG, 8465 QUERY_FLAG_IDN_PWR_ON_WPE, 0, &flag)) 8466 hba->dev_info.f_power_on_wp_en = flag; 8467 8468 /* Probe maximum power mode co-supported by both UFS host and device */ 8469 if (ufshcd_get_max_pwr_mode(hba)) 8470 dev_err(hba->dev, 8471 "%s: Failed getting max supported power mode\n", 8472 __func__); 8473 out: 8474 return ret; 8475 } 8476 8477 static void ufshcd_set_timestamp_attr(struct ufs_hba *hba) 8478 { 8479 int err; 8480 struct ufs_query_req *request = NULL; 8481 struct ufs_query_res *response = NULL; 8482 struct ufs_dev_info *dev_info = &hba->dev_info; 8483 struct utp_upiu_query_v4_0 *upiu_data; 8484 8485 if (dev_info->wspecversion < 0x400) 8486 return; 8487 8488 ufshcd_hold(hba); 8489 8490 mutex_lock(&hba->dev_cmd.lock); 8491 8492 ufshcd_init_query(hba, &request, &response, 8493 UPIU_QUERY_OPCODE_WRITE_ATTR, 8494 QUERY_ATTR_IDN_TIMESTAMP, 0, 0); 8495 8496 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 8497 8498 upiu_data = (struct utp_upiu_query_v4_0 *)&request->upiu_req; 8499 8500 put_unaligned_be64(ktime_get_real_ns(), &upiu_data->osf3); 8501 8502 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT); 8503 8504 if (err) 8505 dev_err(hba->dev, "%s: failed to set timestamp %d\n", 8506 __func__, err); 8507 8508 mutex_unlock(&hba->dev_cmd.lock); 8509 ufshcd_release(hba); 8510 } 8511 8512 /** 8513 * ufshcd_add_lus - probe and add UFS logical units 8514 * @hba: per-adapter instance 8515 * 8516 * Return: 0 upon success; < 0 upon failure. 8517 */ 8518 static int ufshcd_add_lus(struct ufs_hba *hba) 8519 { 8520 int ret; 8521 8522 /* Add required well known logical units to scsi mid layer */ 8523 ret = ufshcd_scsi_add_wlus(hba); 8524 if (ret) 8525 goto out; 8526 8527 /* Initialize devfreq after UFS device is detected */ 8528 if (ufshcd_is_clkscaling_supported(hba)) { 8529 memcpy(&hba->clk_scaling.saved_pwr_info, 8530 &hba->pwr_info, 8531 sizeof(struct ufs_pa_layer_attr)); 8532 hba->clk_scaling.is_allowed = true; 8533 8534 ret = ufshcd_devfreq_init(hba); 8535 if (ret) 8536 goto out; 8537 8538 hba->clk_scaling.is_enabled = true; 8539 ufshcd_init_clk_scaling_sysfs(hba); 8540 } 8541 8542 ufs_bsg_probe(hba); 8543 scsi_scan_host(hba->host); 8544 8545 out: 8546 return ret; 8547 } 8548 8549 /* SDB - Single Doorbell */ 8550 static void ufshcd_release_sdb_queue(struct ufs_hba *hba, int nutrs) 8551 { 8552 size_t ucdl_size, utrdl_size; 8553 8554 ucdl_size = ufshcd_get_ucd_size(hba) * nutrs; 8555 dmam_free_coherent(hba->dev, ucdl_size, hba->ucdl_base_addr, 8556 hba->ucdl_dma_addr); 8557 8558 utrdl_size = sizeof(struct utp_transfer_req_desc) * nutrs; 8559 dmam_free_coherent(hba->dev, utrdl_size, hba->utrdl_base_addr, 8560 hba->utrdl_dma_addr); 8561 8562 devm_kfree(hba->dev, hba->lrb); 8563 } 8564 8565 static int ufshcd_alloc_mcq(struct ufs_hba *hba) 8566 { 8567 int ret; 8568 int old_nutrs = hba->nutrs; 8569 8570 ret = ufshcd_mcq_decide_queue_depth(hba); 8571 if (ret < 0) 8572 return ret; 8573 8574 hba->nutrs = ret; 8575 ret = ufshcd_mcq_init(hba); 8576 if (ret) 8577 goto err; 8578 8579 /* 8580 * Previously allocated memory for nutrs may not be enough in MCQ mode. 8581 * Number of supported tags in MCQ mode may be larger than SDB mode. 8582 */ 8583 if (hba->nutrs != old_nutrs) { 8584 ufshcd_release_sdb_queue(hba, old_nutrs); 8585 ret = ufshcd_memory_alloc(hba); 8586 if (ret) 8587 goto err; 8588 ufshcd_host_memory_configure(hba); 8589 } 8590 8591 ret = ufshcd_mcq_memory_alloc(hba); 8592 if (ret) 8593 goto err; 8594 8595 return 0; 8596 err: 8597 hba->nutrs = old_nutrs; 8598 return ret; 8599 } 8600 8601 static void ufshcd_config_mcq(struct ufs_hba *hba) 8602 { 8603 int ret; 8604 u32 intrs; 8605 8606 ret = ufshcd_mcq_vops_config_esi(hba); 8607 dev_info(hba->dev, "ESI %sconfigured\n", ret ? "is not " : ""); 8608 8609 intrs = UFSHCD_ENABLE_MCQ_INTRS; 8610 if (hba->quirks & UFSHCD_QUIRK_MCQ_BROKEN_INTR) 8611 intrs &= ~MCQ_CQ_EVENT_STATUS; 8612 ufshcd_enable_intr(hba, intrs); 8613 ufshcd_mcq_make_queues_operational(hba); 8614 ufshcd_mcq_config_mac(hba, hba->nutrs); 8615 8616 hba->host->can_queue = hba->nutrs - UFSHCD_NUM_RESERVED; 8617 hba->reserved_slot = hba->nutrs - UFSHCD_NUM_RESERVED; 8618 8619 /* Select MCQ mode */ 8620 ufshcd_writel(hba, ufshcd_readl(hba, REG_UFS_MEM_CFG) | 0x1, 8621 REG_UFS_MEM_CFG); 8622 hba->mcq_enabled = true; 8623 8624 dev_info(hba->dev, "MCQ configured, nr_queues=%d, io_queues=%d, read_queue=%d, poll_queues=%d, queue_depth=%d\n", 8625 hba->nr_hw_queues, hba->nr_queues[HCTX_TYPE_DEFAULT], 8626 hba->nr_queues[HCTX_TYPE_READ], hba->nr_queues[HCTX_TYPE_POLL], 8627 hba->nutrs); 8628 } 8629 8630 static int ufshcd_device_init(struct ufs_hba *hba, bool init_dev_params) 8631 { 8632 int ret; 8633 struct Scsi_Host *host = hba->host; 8634 8635 hba->ufshcd_state = UFSHCD_STATE_RESET; 8636 8637 ret = ufshcd_link_startup(hba); 8638 if (ret) 8639 return ret; 8640 8641 if (hba->quirks & UFSHCD_QUIRK_SKIP_PH_CONFIGURATION) 8642 return ret; 8643 8644 /* Debug counters initialization */ 8645 ufshcd_clear_dbg_ufs_stats(hba); 8646 8647 /* UniPro link is active now */ 8648 ufshcd_set_link_active(hba); 8649 8650 /* Reconfigure MCQ upon reset */ 8651 if (is_mcq_enabled(hba) && !init_dev_params) 8652 ufshcd_config_mcq(hba); 8653 8654 /* Verify device initialization by sending NOP OUT UPIU */ 8655 ret = ufshcd_verify_dev_init(hba); 8656 if (ret) 8657 return ret; 8658 8659 /* Initiate UFS initialization, and waiting until completion */ 8660 ret = ufshcd_complete_dev_init(hba); 8661 if (ret) 8662 return ret; 8663 8664 /* 8665 * Initialize UFS device parameters used by driver, these 8666 * parameters are associated with UFS descriptors. 8667 */ 8668 if (init_dev_params) { 8669 ret = ufshcd_device_params_init(hba); 8670 if (ret) 8671 return ret; 8672 if (is_mcq_supported(hba) && !hba->scsi_host_added) { 8673 ret = ufshcd_alloc_mcq(hba); 8674 if (!ret) { 8675 ufshcd_config_mcq(hba); 8676 } else { 8677 /* Continue with SDB mode */ 8678 use_mcq_mode = false; 8679 dev_err(hba->dev, "MCQ mode is disabled, err=%d\n", 8680 ret); 8681 } 8682 ret = scsi_add_host(host, hba->dev); 8683 if (ret) { 8684 dev_err(hba->dev, "scsi_add_host failed\n"); 8685 return ret; 8686 } 8687 hba->scsi_host_added = true; 8688 } else if (is_mcq_supported(hba)) { 8689 /* UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH is set */ 8690 ufshcd_config_mcq(hba); 8691 } 8692 } 8693 8694 ufshcd_tune_unipro_params(hba); 8695 8696 /* UFS device is also active now */ 8697 ufshcd_set_ufs_dev_active(hba); 8698 ufshcd_force_reset_auto_bkops(hba); 8699 8700 ufshcd_set_timestamp_attr(hba); 8701 8702 /* Gear up to HS gear if supported */ 8703 if (hba->max_pwr_info.is_valid) { 8704 /* 8705 * Set the right value to bRefClkFreq before attempting to 8706 * switch to HS gears. 8707 */ 8708 if (hba->dev_ref_clk_freq != REF_CLK_FREQ_INVAL) 8709 ufshcd_set_dev_ref_clk(hba); 8710 ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info); 8711 if (ret) { 8712 dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n", 8713 __func__, ret); 8714 return ret; 8715 } 8716 } 8717 8718 return 0; 8719 } 8720 8721 /** 8722 * ufshcd_probe_hba - probe hba to detect device and initialize it 8723 * @hba: per-adapter instance 8724 * @init_dev_params: whether or not to call ufshcd_device_params_init(). 8725 * 8726 * Execute link-startup and verify device initialization 8727 * 8728 * Return: 0 upon success; < 0 upon failure. 8729 */ 8730 static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params) 8731 { 8732 ktime_t start = ktime_get(); 8733 unsigned long flags; 8734 int ret; 8735 8736 ret = ufshcd_device_init(hba, init_dev_params); 8737 if (ret) 8738 goto out; 8739 8740 if (!hba->pm_op_in_progress && 8741 (hba->quirks & UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH)) { 8742 /* Reset the device and controller before doing reinit */ 8743 ufshcd_device_reset(hba); 8744 ufshcd_hba_stop(hba); 8745 ufshcd_vops_reinit_notify(hba); 8746 ret = ufshcd_hba_enable(hba); 8747 if (ret) { 8748 dev_err(hba->dev, "Host controller enable failed\n"); 8749 ufshcd_print_evt_hist(hba); 8750 ufshcd_print_host_state(hba); 8751 goto out; 8752 } 8753 8754 /* Reinit the device */ 8755 ret = ufshcd_device_init(hba, init_dev_params); 8756 if (ret) 8757 goto out; 8758 } 8759 8760 ufshcd_print_pwr_info(hba); 8761 8762 /* 8763 * bActiveICCLevel is volatile for UFS device (as per latest v2.1 spec) 8764 * and for removable UFS card as well, hence always set the parameter. 8765 * Note: Error handler may issue the device reset hence resetting 8766 * bActiveICCLevel as well so it is always safe to set this here. 8767 */ 8768 ufshcd_set_active_icc_lvl(hba); 8769 8770 /* Enable UFS Write Booster if supported */ 8771 ufshcd_configure_wb(hba); 8772 8773 if (hba->ee_usr_mask) 8774 ufshcd_write_ee_control(hba); 8775 /* Enable Auto-Hibernate if configured */ 8776 ufshcd_auto_hibern8_enable(hba); 8777 8778 out: 8779 spin_lock_irqsave(hba->host->host_lock, flags); 8780 if (ret) 8781 hba->ufshcd_state = UFSHCD_STATE_ERROR; 8782 else if (hba->ufshcd_state == UFSHCD_STATE_RESET) 8783 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL; 8784 spin_unlock_irqrestore(hba->host->host_lock, flags); 8785 8786 trace_ufshcd_init(dev_name(hba->dev), ret, 8787 ktime_to_us(ktime_sub(ktime_get(), start)), 8788 hba->curr_dev_pwr_mode, hba->uic_link_state); 8789 return ret; 8790 } 8791 8792 /** 8793 * ufshcd_async_scan - asynchronous execution for probing hba 8794 * @data: data pointer to pass to this function 8795 * @cookie: cookie data 8796 */ 8797 static void ufshcd_async_scan(void *data, async_cookie_t cookie) 8798 { 8799 struct ufs_hba *hba = (struct ufs_hba *)data; 8800 int ret; 8801 8802 down(&hba->host_sem); 8803 /* Initialize hba, detect and initialize UFS device */ 8804 ret = ufshcd_probe_hba(hba, true); 8805 up(&hba->host_sem); 8806 if (ret) 8807 goto out; 8808 8809 /* Probe and add UFS logical units */ 8810 ret = ufshcd_add_lus(hba); 8811 8812 out: 8813 pm_runtime_put_sync(hba->dev); 8814 8815 if (ret) 8816 dev_err(hba->dev, "%s failed: %d\n", __func__, ret); 8817 } 8818 8819 static enum scsi_timeout_action ufshcd_eh_timed_out(struct scsi_cmnd *scmd) 8820 { 8821 struct ufs_hba *hba = shost_priv(scmd->device->host); 8822 8823 if (!hba->system_suspending) { 8824 /* Activate the error handler in the SCSI core. */ 8825 return SCSI_EH_NOT_HANDLED; 8826 } 8827 8828 /* 8829 * If we get here we know that no TMFs are outstanding and also that 8830 * the only pending command is a START STOP UNIT command. Handle the 8831 * timeout of that command directly to prevent a deadlock between 8832 * ufshcd_set_dev_pwr_mode() and ufshcd_err_handler(). 8833 */ 8834 ufshcd_link_recovery(hba); 8835 dev_info(hba->dev, "%s() finished; outstanding_tasks = %#lx.\n", 8836 __func__, hba->outstanding_tasks); 8837 8838 return hba->outstanding_reqs ? SCSI_EH_RESET_TIMER : SCSI_EH_DONE; 8839 } 8840 8841 static const struct attribute_group *ufshcd_driver_groups[] = { 8842 &ufs_sysfs_unit_descriptor_group, 8843 &ufs_sysfs_lun_attributes_group, 8844 NULL, 8845 }; 8846 8847 static struct ufs_hba_variant_params ufs_hba_vps = { 8848 .hba_enable_delay_us = 1000, 8849 .wb_flush_threshold = UFS_WB_BUF_REMAIN_PERCENT(40), 8850 .devfreq_profile.polling_ms = 100, 8851 .devfreq_profile.target = ufshcd_devfreq_target, 8852 .devfreq_profile.get_dev_status = ufshcd_devfreq_get_dev_status, 8853 .ondemand_data.upthreshold = 70, 8854 .ondemand_data.downdifferential = 5, 8855 }; 8856 8857 static const struct scsi_host_template ufshcd_driver_template = { 8858 .module = THIS_MODULE, 8859 .name = UFSHCD, 8860 .proc_name = UFSHCD, 8861 .map_queues = ufshcd_map_queues, 8862 .queuecommand = ufshcd_queuecommand, 8863 .mq_poll = ufshcd_poll, 8864 .slave_alloc = ufshcd_slave_alloc, 8865 .slave_configure = ufshcd_slave_configure, 8866 .slave_destroy = ufshcd_slave_destroy, 8867 .change_queue_depth = ufshcd_change_queue_depth, 8868 .eh_abort_handler = ufshcd_abort, 8869 .eh_device_reset_handler = ufshcd_eh_device_reset_handler, 8870 .eh_host_reset_handler = ufshcd_eh_host_reset_handler, 8871 .eh_timed_out = ufshcd_eh_timed_out, 8872 .this_id = -1, 8873 .sg_tablesize = SG_ALL, 8874 .cmd_per_lun = UFSHCD_CMD_PER_LUN, 8875 .can_queue = UFSHCD_CAN_QUEUE, 8876 .max_segment_size = PRDT_DATA_BYTE_COUNT_MAX, 8877 .max_sectors = SZ_1M / SECTOR_SIZE, 8878 .max_host_blocked = 1, 8879 .track_queue_depth = 1, 8880 .skip_settle_delay = 1, 8881 .sdev_groups = ufshcd_driver_groups, 8882 .rpm_autosuspend_delay = RPM_AUTOSUSPEND_DELAY_MS, 8883 }; 8884 8885 static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg, 8886 int ua) 8887 { 8888 int ret; 8889 8890 if (!vreg) 8891 return 0; 8892 8893 /* 8894 * "set_load" operation shall be required on those regulators 8895 * which specifically configured current limitation. Otherwise 8896 * zero max_uA may cause unexpected behavior when regulator is 8897 * enabled or set as high power mode. 8898 */ 8899 if (!vreg->max_uA) 8900 return 0; 8901 8902 ret = regulator_set_load(vreg->reg, ua); 8903 if (ret < 0) { 8904 dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n", 8905 __func__, vreg->name, ua, ret); 8906 } 8907 8908 return ret; 8909 } 8910 8911 static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba, 8912 struct ufs_vreg *vreg) 8913 { 8914 return ufshcd_config_vreg_load(hba->dev, vreg, UFS_VREG_LPM_LOAD_UA); 8915 } 8916 8917 static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba, 8918 struct ufs_vreg *vreg) 8919 { 8920 if (!vreg) 8921 return 0; 8922 8923 return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA); 8924 } 8925 8926 static int ufshcd_config_vreg(struct device *dev, 8927 struct ufs_vreg *vreg, bool on) 8928 { 8929 if (regulator_count_voltages(vreg->reg) <= 0) 8930 return 0; 8931 8932 return ufshcd_config_vreg_load(dev, vreg, on ? vreg->max_uA : 0); 8933 } 8934 8935 static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg) 8936 { 8937 int ret = 0; 8938 8939 if (!vreg || vreg->enabled) 8940 goto out; 8941 8942 ret = ufshcd_config_vreg(dev, vreg, true); 8943 if (!ret) 8944 ret = regulator_enable(vreg->reg); 8945 8946 if (!ret) 8947 vreg->enabled = true; 8948 else 8949 dev_err(dev, "%s: %s enable failed, err=%d\n", 8950 __func__, vreg->name, ret); 8951 out: 8952 return ret; 8953 } 8954 8955 static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg) 8956 { 8957 int ret = 0; 8958 8959 if (!vreg || !vreg->enabled || vreg->always_on) 8960 goto out; 8961 8962 ret = regulator_disable(vreg->reg); 8963 8964 if (!ret) { 8965 /* ignore errors on applying disable config */ 8966 ufshcd_config_vreg(dev, vreg, false); 8967 vreg->enabled = false; 8968 } else { 8969 dev_err(dev, "%s: %s disable failed, err=%d\n", 8970 __func__, vreg->name, ret); 8971 } 8972 out: 8973 return ret; 8974 } 8975 8976 static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on) 8977 { 8978 int ret = 0; 8979 struct device *dev = hba->dev; 8980 struct ufs_vreg_info *info = &hba->vreg_info; 8981 8982 ret = ufshcd_toggle_vreg(dev, info->vcc, on); 8983 if (ret) 8984 goto out; 8985 8986 ret = ufshcd_toggle_vreg(dev, info->vccq, on); 8987 if (ret) 8988 goto out; 8989 8990 ret = ufshcd_toggle_vreg(dev, info->vccq2, on); 8991 8992 out: 8993 if (ret) { 8994 ufshcd_toggle_vreg(dev, info->vccq2, false); 8995 ufshcd_toggle_vreg(dev, info->vccq, false); 8996 ufshcd_toggle_vreg(dev, info->vcc, false); 8997 } 8998 return ret; 8999 } 9000 9001 static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on) 9002 { 9003 struct ufs_vreg_info *info = &hba->vreg_info; 9004 9005 return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on); 9006 } 9007 9008 int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg) 9009 { 9010 int ret = 0; 9011 9012 if (!vreg) 9013 goto out; 9014 9015 vreg->reg = devm_regulator_get(dev, vreg->name); 9016 if (IS_ERR(vreg->reg)) { 9017 ret = PTR_ERR(vreg->reg); 9018 dev_err(dev, "%s: %s get failed, err=%d\n", 9019 __func__, vreg->name, ret); 9020 } 9021 out: 9022 return ret; 9023 } 9024 EXPORT_SYMBOL_GPL(ufshcd_get_vreg); 9025 9026 static int ufshcd_init_vreg(struct ufs_hba *hba) 9027 { 9028 int ret = 0; 9029 struct device *dev = hba->dev; 9030 struct ufs_vreg_info *info = &hba->vreg_info; 9031 9032 ret = ufshcd_get_vreg(dev, info->vcc); 9033 if (ret) 9034 goto out; 9035 9036 ret = ufshcd_get_vreg(dev, info->vccq); 9037 if (!ret) 9038 ret = ufshcd_get_vreg(dev, info->vccq2); 9039 out: 9040 return ret; 9041 } 9042 9043 static int ufshcd_init_hba_vreg(struct ufs_hba *hba) 9044 { 9045 struct ufs_vreg_info *info = &hba->vreg_info; 9046 9047 return ufshcd_get_vreg(hba->dev, info->vdd_hba); 9048 } 9049 9050 static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on) 9051 { 9052 int ret = 0; 9053 struct ufs_clk_info *clki; 9054 struct list_head *head = &hba->clk_list_head; 9055 unsigned long flags; 9056 ktime_t start = ktime_get(); 9057 bool clk_state_changed = false; 9058 9059 if (list_empty(head)) 9060 goto out; 9061 9062 ret = ufshcd_vops_setup_clocks(hba, on, PRE_CHANGE); 9063 if (ret) 9064 return ret; 9065 9066 list_for_each_entry(clki, head, list) { 9067 if (!IS_ERR_OR_NULL(clki->clk)) { 9068 /* 9069 * Don't disable clocks which are needed 9070 * to keep the link active. 9071 */ 9072 if (ufshcd_is_link_active(hba) && 9073 clki->keep_link_active) 9074 continue; 9075 9076 clk_state_changed = on ^ clki->enabled; 9077 if (on && !clki->enabled) { 9078 ret = clk_prepare_enable(clki->clk); 9079 if (ret) { 9080 dev_err(hba->dev, "%s: %s prepare enable failed, %d\n", 9081 __func__, clki->name, ret); 9082 goto out; 9083 } 9084 } else if (!on && clki->enabled) { 9085 clk_disable_unprepare(clki->clk); 9086 } 9087 clki->enabled = on; 9088 dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__, 9089 clki->name, on ? "en" : "dis"); 9090 } 9091 } 9092 9093 ret = ufshcd_vops_setup_clocks(hba, on, POST_CHANGE); 9094 if (ret) 9095 return ret; 9096 9097 out: 9098 if (ret) { 9099 list_for_each_entry(clki, head, list) { 9100 if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled) 9101 clk_disable_unprepare(clki->clk); 9102 } 9103 } else if (!ret && on) { 9104 spin_lock_irqsave(hba->host->host_lock, flags); 9105 hba->clk_gating.state = CLKS_ON; 9106 trace_ufshcd_clk_gating(dev_name(hba->dev), 9107 hba->clk_gating.state); 9108 spin_unlock_irqrestore(hba->host->host_lock, flags); 9109 } 9110 9111 if (clk_state_changed) 9112 trace_ufshcd_profile_clk_gating(dev_name(hba->dev), 9113 (on ? "on" : "off"), 9114 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 9115 return ret; 9116 } 9117 9118 static enum ufs_ref_clk_freq ufshcd_parse_ref_clk_property(struct ufs_hba *hba) 9119 { 9120 u32 freq; 9121 int ret = device_property_read_u32(hba->dev, "ref-clk-freq", &freq); 9122 9123 if (ret) { 9124 dev_dbg(hba->dev, "Cannot query 'ref-clk-freq' property = %d", ret); 9125 return REF_CLK_FREQ_INVAL; 9126 } 9127 9128 return ufs_get_bref_clk_from_hz(freq); 9129 } 9130 9131 static int ufshcd_init_clocks(struct ufs_hba *hba) 9132 { 9133 int ret = 0; 9134 struct ufs_clk_info *clki; 9135 struct device *dev = hba->dev; 9136 struct list_head *head = &hba->clk_list_head; 9137 9138 if (list_empty(head)) 9139 goto out; 9140 9141 list_for_each_entry(clki, head, list) { 9142 if (!clki->name) 9143 continue; 9144 9145 clki->clk = devm_clk_get(dev, clki->name); 9146 if (IS_ERR(clki->clk)) { 9147 ret = PTR_ERR(clki->clk); 9148 dev_err(dev, "%s: %s clk get failed, %d\n", 9149 __func__, clki->name, ret); 9150 goto out; 9151 } 9152 9153 /* 9154 * Parse device ref clk freq as per device tree "ref_clk". 9155 * Default dev_ref_clk_freq is set to REF_CLK_FREQ_INVAL 9156 * in ufshcd_alloc_host(). 9157 */ 9158 if (!strcmp(clki->name, "ref_clk")) 9159 ufshcd_parse_dev_ref_clk_freq(hba, clki->clk); 9160 9161 if (clki->max_freq) { 9162 ret = clk_set_rate(clki->clk, clki->max_freq); 9163 if (ret) { 9164 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n", 9165 __func__, clki->name, 9166 clki->max_freq, ret); 9167 goto out; 9168 } 9169 clki->curr_freq = clki->max_freq; 9170 } 9171 dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__, 9172 clki->name, clk_get_rate(clki->clk)); 9173 } 9174 out: 9175 return ret; 9176 } 9177 9178 static int ufshcd_variant_hba_init(struct ufs_hba *hba) 9179 { 9180 int err = 0; 9181 9182 if (!hba->vops) 9183 goto out; 9184 9185 err = ufshcd_vops_init(hba); 9186 if (err) 9187 dev_err_probe(hba->dev, err, 9188 "%s: variant %s init failed with err %d\n", 9189 __func__, ufshcd_get_var_name(hba), err); 9190 out: 9191 return err; 9192 } 9193 9194 static void ufshcd_variant_hba_exit(struct ufs_hba *hba) 9195 { 9196 if (!hba->vops) 9197 return; 9198 9199 ufshcd_vops_exit(hba); 9200 } 9201 9202 static int ufshcd_hba_init(struct ufs_hba *hba) 9203 { 9204 int err; 9205 9206 /* 9207 * Handle host controller power separately from the UFS device power 9208 * rails as it will help controlling the UFS host controller power 9209 * collapse easily which is different than UFS device power collapse. 9210 * Also, enable the host controller power before we go ahead with rest 9211 * of the initialization here. 9212 */ 9213 err = ufshcd_init_hba_vreg(hba); 9214 if (err) 9215 goto out; 9216 9217 err = ufshcd_setup_hba_vreg(hba, true); 9218 if (err) 9219 goto out; 9220 9221 err = ufshcd_init_clocks(hba); 9222 if (err) 9223 goto out_disable_hba_vreg; 9224 9225 if (hba->dev_ref_clk_freq == REF_CLK_FREQ_INVAL) 9226 hba->dev_ref_clk_freq = ufshcd_parse_ref_clk_property(hba); 9227 9228 err = ufshcd_setup_clocks(hba, true); 9229 if (err) 9230 goto out_disable_hba_vreg; 9231 9232 err = ufshcd_init_vreg(hba); 9233 if (err) 9234 goto out_disable_clks; 9235 9236 err = ufshcd_setup_vreg(hba, true); 9237 if (err) 9238 goto out_disable_clks; 9239 9240 err = ufshcd_variant_hba_init(hba); 9241 if (err) 9242 goto out_disable_vreg; 9243 9244 ufs_debugfs_hba_init(hba); 9245 9246 hba->is_powered = true; 9247 goto out; 9248 9249 out_disable_vreg: 9250 ufshcd_setup_vreg(hba, false); 9251 out_disable_clks: 9252 ufshcd_setup_clocks(hba, false); 9253 out_disable_hba_vreg: 9254 ufshcd_setup_hba_vreg(hba, false); 9255 out: 9256 return err; 9257 } 9258 9259 static void ufshcd_hba_exit(struct ufs_hba *hba) 9260 { 9261 if (hba->is_powered) { 9262 ufshcd_exit_clk_scaling(hba); 9263 ufshcd_exit_clk_gating(hba); 9264 if (hba->eh_wq) 9265 destroy_workqueue(hba->eh_wq); 9266 ufs_debugfs_hba_exit(hba); 9267 ufshcd_variant_hba_exit(hba); 9268 ufshcd_setup_vreg(hba, false); 9269 ufshcd_setup_clocks(hba, false); 9270 ufshcd_setup_hba_vreg(hba, false); 9271 hba->is_powered = false; 9272 ufs_put_device_desc(hba); 9273 } 9274 } 9275 9276 static int ufshcd_execute_start_stop(struct scsi_device *sdev, 9277 enum ufs_dev_pwr_mode pwr_mode, 9278 struct scsi_sense_hdr *sshdr) 9279 { 9280 const unsigned char cdb[6] = { START_STOP, 0, 0, 0, pwr_mode << 4, 0 }; 9281 const struct scsi_exec_args args = { 9282 .sshdr = sshdr, 9283 .req_flags = BLK_MQ_REQ_PM, 9284 .scmd_flags = SCMD_FAIL_IF_RECOVERING, 9285 }; 9286 9287 return scsi_execute_cmd(sdev, cdb, REQ_OP_DRV_IN, /*buffer=*/NULL, 9288 /*bufflen=*/0, /*timeout=*/10 * HZ, /*retries=*/0, 9289 &args); 9290 } 9291 9292 /** 9293 * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device 9294 * power mode 9295 * @hba: per adapter instance 9296 * @pwr_mode: device power mode to set 9297 * 9298 * Return: 0 if requested power mode is set successfully; 9299 * < 0 if failed to set the requested power mode. 9300 */ 9301 static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba, 9302 enum ufs_dev_pwr_mode pwr_mode) 9303 { 9304 struct scsi_sense_hdr sshdr; 9305 struct scsi_device *sdp; 9306 unsigned long flags; 9307 int ret, retries; 9308 9309 spin_lock_irqsave(hba->host->host_lock, flags); 9310 sdp = hba->ufs_device_wlun; 9311 if (sdp && scsi_device_online(sdp)) 9312 ret = scsi_device_get(sdp); 9313 else 9314 ret = -ENODEV; 9315 spin_unlock_irqrestore(hba->host->host_lock, flags); 9316 9317 if (ret) 9318 return ret; 9319 9320 /* 9321 * If scsi commands fail, the scsi mid-layer schedules scsi error- 9322 * handling, which would wait for host to be resumed. Since we know 9323 * we are functional while we are here, skip host resume in error 9324 * handling context. 9325 */ 9326 hba->host->eh_noresume = 1; 9327 9328 /* 9329 * Current function would be generally called from the power management 9330 * callbacks hence set the RQF_PM flag so that it doesn't resume the 9331 * already suspended childs. 9332 */ 9333 for (retries = 3; retries > 0; --retries) { 9334 ret = ufshcd_execute_start_stop(sdp, pwr_mode, &sshdr); 9335 /* 9336 * scsi_execute() only returns a negative value if the request 9337 * queue is dying. 9338 */ 9339 if (ret <= 0) 9340 break; 9341 } 9342 if (ret) { 9343 sdev_printk(KERN_WARNING, sdp, 9344 "START_STOP failed for power mode: %d, result %x\n", 9345 pwr_mode, ret); 9346 if (ret > 0) { 9347 if (scsi_sense_valid(&sshdr)) 9348 scsi_print_sense_hdr(sdp, NULL, &sshdr); 9349 ret = -EIO; 9350 } 9351 } else { 9352 hba->curr_dev_pwr_mode = pwr_mode; 9353 } 9354 9355 scsi_device_put(sdp); 9356 hba->host->eh_noresume = 0; 9357 return ret; 9358 } 9359 9360 static int ufshcd_link_state_transition(struct ufs_hba *hba, 9361 enum uic_link_state req_link_state, 9362 bool check_for_bkops) 9363 { 9364 int ret = 0; 9365 9366 if (req_link_state == hba->uic_link_state) 9367 return 0; 9368 9369 if (req_link_state == UIC_LINK_HIBERN8_STATE) { 9370 ret = ufshcd_uic_hibern8_enter(hba); 9371 if (!ret) { 9372 ufshcd_set_link_hibern8(hba); 9373 } else { 9374 dev_err(hba->dev, "%s: hibern8 enter failed %d\n", 9375 __func__, ret); 9376 goto out; 9377 } 9378 } 9379 /* 9380 * If autobkops is enabled, link can't be turned off because 9381 * turning off the link would also turn off the device, except in the 9382 * case of DeepSleep where the device is expected to remain powered. 9383 */ 9384 else if ((req_link_state == UIC_LINK_OFF_STATE) && 9385 (!check_for_bkops || !hba->auto_bkops_enabled)) { 9386 /* 9387 * Let's make sure that link is in low power mode, we are doing 9388 * this currently by putting the link in Hibern8. Otherway to 9389 * put the link in low power mode is to send the DME end point 9390 * to device and then send the DME reset command to local 9391 * unipro. But putting the link in hibern8 is much faster. 9392 * 9393 * Note also that putting the link in Hibern8 is a requirement 9394 * for entering DeepSleep. 9395 */ 9396 ret = ufshcd_uic_hibern8_enter(hba); 9397 if (ret) { 9398 dev_err(hba->dev, "%s: hibern8 enter failed %d\n", 9399 __func__, ret); 9400 goto out; 9401 } 9402 /* 9403 * Change controller state to "reset state" which 9404 * should also put the link in off/reset state 9405 */ 9406 ufshcd_hba_stop(hba); 9407 /* 9408 * TODO: Check if we need any delay to make sure that 9409 * controller is reset 9410 */ 9411 ufshcd_set_link_off(hba); 9412 } 9413 9414 out: 9415 return ret; 9416 } 9417 9418 static void ufshcd_vreg_set_lpm(struct ufs_hba *hba) 9419 { 9420 bool vcc_off = false; 9421 9422 /* 9423 * It seems some UFS devices may keep drawing more than sleep current 9424 * (atleast for 500us) from UFS rails (especially from VCCQ rail). 9425 * To avoid this situation, add 2ms delay before putting these UFS 9426 * rails in LPM mode. 9427 */ 9428 if (!ufshcd_is_link_active(hba) && 9429 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM) 9430 usleep_range(2000, 2100); 9431 9432 /* 9433 * If UFS device is either in UFS_Sleep turn off VCC rail to save some 9434 * power. 9435 * 9436 * If UFS device and link is in OFF state, all power supplies (VCC, 9437 * VCCQ, VCCQ2) can be turned off if power on write protect is not 9438 * required. If UFS link is inactive (Hibern8 or OFF state) and device 9439 * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode. 9440 * 9441 * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway 9442 * in low power state which would save some power. 9443 * 9444 * If Write Booster is enabled and the device needs to flush the WB 9445 * buffer OR if bkops status is urgent for WB, keep Vcc on. 9446 */ 9447 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) && 9448 !hba->dev_info.is_lu_power_on_wp) { 9449 ufshcd_setup_vreg(hba, false); 9450 vcc_off = true; 9451 } else if (!ufshcd_is_ufs_dev_active(hba)) { 9452 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false); 9453 vcc_off = true; 9454 if (ufshcd_is_link_hibern8(hba) || ufshcd_is_link_off(hba)) { 9455 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq); 9456 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2); 9457 } 9458 } 9459 9460 /* 9461 * Some UFS devices require delay after VCC power rail is turned-off. 9462 */ 9463 if (vcc_off && hba->vreg_info.vcc && 9464 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_AFTER_LPM) 9465 usleep_range(5000, 5100); 9466 } 9467 9468 #ifdef CONFIG_PM 9469 static int ufshcd_vreg_set_hpm(struct ufs_hba *hba) 9470 { 9471 int ret = 0; 9472 9473 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) && 9474 !hba->dev_info.is_lu_power_on_wp) { 9475 ret = ufshcd_setup_vreg(hba, true); 9476 } else if (!ufshcd_is_ufs_dev_active(hba)) { 9477 if (!ufshcd_is_link_active(hba)) { 9478 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq); 9479 if (ret) 9480 goto vcc_disable; 9481 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2); 9482 if (ret) 9483 goto vccq_lpm; 9484 } 9485 ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true); 9486 } 9487 goto out; 9488 9489 vccq_lpm: 9490 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq); 9491 vcc_disable: 9492 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false); 9493 out: 9494 return ret; 9495 } 9496 #endif /* CONFIG_PM */ 9497 9498 static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba) 9499 { 9500 if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba)) 9501 ufshcd_setup_hba_vreg(hba, false); 9502 } 9503 9504 static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba) 9505 { 9506 if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba)) 9507 ufshcd_setup_hba_vreg(hba, true); 9508 } 9509 9510 static int __ufshcd_wl_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op) 9511 { 9512 int ret = 0; 9513 bool check_for_bkops; 9514 enum ufs_pm_level pm_lvl; 9515 enum ufs_dev_pwr_mode req_dev_pwr_mode; 9516 enum uic_link_state req_link_state; 9517 9518 hba->pm_op_in_progress = true; 9519 if (pm_op != UFS_SHUTDOWN_PM) { 9520 pm_lvl = pm_op == UFS_RUNTIME_PM ? 9521 hba->rpm_lvl : hba->spm_lvl; 9522 req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl); 9523 req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl); 9524 } else { 9525 req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE; 9526 req_link_state = UIC_LINK_OFF_STATE; 9527 } 9528 9529 /* 9530 * If we can't transition into any of the low power modes 9531 * just gate the clocks. 9532 */ 9533 ufshcd_hold(hba); 9534 hba->clk_gating.is_suspended = true; 9535 9536 if (ufshcd_is_clkscaling_supported(hba)) 9537 ufshcd_clk_scaling_suspend(hba, true); 9538 9539 if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE && 9540 req_link_state == UIC_LINK_ACTIVE_STATE) { 9541 goto vops_suspend; 9542 } 9543 9544 if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) && 9545 (req_link_state == hba->uic_link_state)) 9546 goto enable_scaling; 9547 9548 /* UFS device & link must be active before we enter in this function */ 9549 if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) { 9550 ret = -EINVAL; 9551 goto enable_scaling; 9552 } 9553 9554 if (pm_op == UFS_RUNTIME_PM) { 9555 if (ufshcd_can_autobkops_during_suspend(hba)) { 9556 /* 9557 * The device is idle with no requests in the queue, 9558 * allow background operations if bkops status shows 9559 * that performance might be impacted. 9560 */ 9561 ret = ufshcd_urgent_bkops(hba); 9562 if (ret) { 9563 /* 9564 * If return err in suspend flow, IO will hang. 9565 * Trigger error handler and break suspend for 9566 * error recovery. 9567 */ 9568 ufshcd_force_error_recovery(hba); 9569 ret = -EBUSY; 9570 goto enable_scaling; 9571 } 9572 } else { 9573 /* make sure that auto bkops is disabled */ 9574 ufshcd_disable_auto_bkops(hba); 9575 } 9576 /* 9577 * If device needs to do BKOP or WB buffer flush during 9578 * Hibern8, keep device power mode as "active power mode" 9579 * and VCC supply. 9580 */ 9581 hba->dev_info.b_rpm_dev_flush_capable = 9582 hba->auto_bkops_enabled || 9583 (((req_link_state == UIC_LINK_HIBERN8_STATE) || 9584 ((req_link_state == UIC_LINK_ACTIVE_STATE) && 9585 ufshcd_is_auto_hibern8_enabled(hba))) && 9586 ufshcd_wb_need_flush(hba)); 9587 } 9588 9589 flush_work(&hba->eeh_work); 9590 9591 ret = ufshcd_vops_suspend(hba, pm_op, PRE_CHANGE); 9592 if (ret) 9593 goto enable_scaling; 9594 9595 if (req_dev_pwr_mode != hba->curr_dev_pwr_mode) { 9596 if (pm_op != UFS_RUNTIME_PM) 9597 /* ensure that bkops is disabled */ 9598 ufshcd_disable_auto_bkops(hba); 9599 9600 if (!hba->dev_info.b_rpm_dev_flush_capable) { 9601 ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode); 9602 if (ret && pm_op != UFS_SHUTDOWN_PM) { 9603 /* 9604 * If return err in suspend flow, IO will hang. 9605 * Trigger error handler and break suspend for 9606 * error recovery. 9607 */ 9608 ufshcd_force_error_recovery(hba); 9609 ret = -EBUSY; 9610 } 9611 if (ret) 9612 goto enable_scaling; 9613 } 9614 } 9615 9616 /* 9617 * In the case of DeepSleep, the device is expected to remain powered 9618 * with the link off, so do not check for bkops. 9619 */ 9620 check_for_bkops = !ufshcd_is_ufs_dev_deepsleep(hba); 9621 ret = ufshcd_link_state_transition(hba, req_link_state, check_for_bkops); 9622 if (ret && pm_op != UFS_SHUTDOWN_PM) { 9623 /* 9624 * If return err in suspend flow, IO will hang. 9625 * Trigger error handler and break suspend for 9626 * error recovery. 9627 */ 9628 ufshcd_force_error_recovery(hba); 9629 ret = -EBUSY; 9630 } 9631 if (ret) 9632 goto set_dev_active; 9633 9634 vops_suspend: 9635 /* 9636 * Call vendor specific suspend callback. As these callbacks may access 9637 * vendor specific host controller register space call them before the 9638 * host clocks are ON. 9639 */ 9640 ret = ufshcd_vops_suspend(hba, pm_op, POST_CHANGE); 9641 if (ret) 9642 goto set_link_active; 9643 goto out; 9644 9645 set_link_active: 9646 /* 9647 * Device hardware reset is required to exit DeepSleep. Also, for 9648 * DeepSleep, the link is off so host reset and restore will be done 9649 * further below. 9650 */ 9651 if (ufshcd_is_ufs_dev_deepsleep(hba)) { 9652 ufshcd_device_reset(hba); 9653 WARN_ON(!ufshcd_is_link_off(hba)); 9654 } 9655 if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba)) 9656 ufshcd_set_link_active(hba); 9657 else if (ufshcd_is_link_off(hba)) 9658 ufshcd_host_reset_and_restore(hba); 9659 set_dev_active: 9660 /* Can also get here needing to exit DeepSleep */ 9661 if (ufshcd_is_ufs_dev_deepsleep(hba)) { 9662 ufshcd_device_reset(hba); 9663 ufshcd_host_reset_and_restore(hba); 9664 } 9665 if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE)) 9666 ufshcd_disable_auto_bkops(hba); 9667 enable_scaling: 9668 if (ufshcd_is_clkscaling_supported(hba)) 9669 ufshcd_clk_scaling_suspend(hba, false); 9670 9671 hba->dev_info.b_rpm_dev_flush_capable = false; 9672 out: 9673 if (hba->dev_info.b_rpm_dev_flush_capable) { 9674 schedule_delayed_work(&hba->rpm_dev_flush_recheck_work, 9675 msecs_to_jiffies(RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS)); 9676 } 9677 9678 if (ret) { 9679 ufshcd_update_evt_hist(hba, UFS_EVT_WL_SUSP_ERR, (u32)ret); 9680 hba->clk_gating.is_suspended = false; 9681 ufshcd_release(hba); 9682 } 9683 hba->pm_op_in_progress = false; 9684 return ret; 9685 } 9686 9687 #ifdef CONFIG_PM 9688 static int __ufshcd_wl_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) 9689 { 9690 int ret; 9691 enum uic_link_state old_link_state = hba->uic_link_state; 9692 9693 hba->pm_op_in_progress = true; 9694 9695 /* 9696 * Call vendor specific resume callback. As these callbacks may access 9697 * vendor specific host controller register space call them when the 9698 * host clocks are ON. 9699 */ 9700 ret = ufshcd_vops_resume(hba, pm_op); 9701 if (ret) 9702 goto out; 9703 9704 /* For DeepSleep, the only supported option is to have the link off */ 9705 WARN_ON(ufshcd_is_ufs_dev_deepsleep(hba) && !ufshcd_is_link_off(hba)); 9706 9707 if (ufshcd_is_link_hibern8(hba)) { 9708 ret = ufshcd_uic_hibern8_exit(hba); 9709 if (!ret) { 9710 ufshcd_set_link_active(hba); 9711 } else { 9712 dev_err(hba->dev, "%s: hibern8 exit failed %d\n", 9713 __func__, ret); 9714 goto vendor_suspend; 9715 } 9716 } else if (ufshcd_is_link_off(hba)) { 9717 /* 9718 * A full initialization of the host and the device is 9719 * required since the link was put to off during suspend. 9720 * Note, in the case of DeepSleep, the device will exit 9721 * DeepSleep due to device reset. 9722 */ 9723 ret = ufshcd_reset_and_restore(hba); 9724 /* 9725 * ufshcd_reset_and_restore() should have already 9726 * set the link state as active 9727 */ 9728 if (ret || !ufshcd_is_link_active(hba)) 9729 goto vendor_suspend; 9730 } 9731 9732 if (!ufshcd_is_ufs_dev_active(hba)) { 9733 ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE); 9734 if (ret) 9735 goto set_old_link_state; 9736 ufshcd_set_timestamp_attr(hba); 9737 } 9738 9739 if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) 9740 ufshcd_enable_auto_bkops(hba); 9741 else 9742 /* 9743 * If BKOPs operations are urgently needed at this moment then 9744 * keep auto-bkops enabled or else disable it. 9745 */ 9746 ufshcd_urgent_bkops(hba); 9747 9748 if (hba->ee_usr_mask) 9749 ufshcd_write_ee_control(hba); 9750 9751 if (ufshcd_is_clkscaling_supported(hba)) 9752 ufshcd_clk_scaling_suspend(hba, false); 9753 9754 if (hba->dev_info.b_rpm_dev_flush_capable) { 9755 hba->dev_info.b_rpm_dev_flush_capable = false; 9756 cancel_delayed_work(&hba->rpm_dev_flush_recheck_work); 9757 } 9758 9759 /* Enable Auto-Hibernate if configured */ 9760 ufshcd_auto_hibern8_enable(hba); 9761 9762 goto out; 9763 9764 set_old_link_state: 9765 ufshcd_link_state_transition(hba, old_link_state, 0); 9766 vendor_suspend: 9767 ufshcd_vops_suspend(hba, pm_op, PRE_CHANGE); 9768 ufshcd_vops_suspend(hba, pm_op, POST_CHANGE); 9769 out: 9770 if (ret) 9771 ufshcd_update_evt_hist(hba, UFS_EVT_WL_RES_ERR, (u32)ret); 9772 hba->clk_gating.is_suspended = false; 9773 ufshcd_release(hba); 9774 hba->pm_op_in_progress = false; 9775 return ret; 9776 } 9777 9778 static int ufshcd_wl_runtime_suspend(struct device *dev) 9779 { 9780 struct scsi_device *sdev = to_scsi_device(dev); 9781 struct ufs_hba *hba; 9782 int ret; 9783 ktime_t start = ktime_get(); 9784 9785 hba = shost_priv(sdev->host); 9786 9787 ret = __ufshcd_wl_suspend(hba, UFS_RUNTIME_PM); 9788 if (ret) 9789 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret); 9790 9791 trace_ufshcd_wl_runtime_suspend(dev_name(dev), ret, 9792 ktime_to_us(ktime_sub(ktime_get(), start)), 9793 hba->curr_dev_pwr_mode, hba->uic_link_state); 9794 9795 return ret; 9796 } 9797 9798 static int ufshcd_wl_runtime_resume(struct device *dev) 9799 { 9800 struct scsi_device *sdev = to_scsi_device(dev); 9801 struct ufs_hba *hba; 9802 int ret = 0; 9803 ktime_t start = ktime_get(); 9804 9805 hba = shost_priv(sdev->host); 9806 9807 ret = __ufshcd_wl_resume(hba, UFS_RUNTIME_PM); 9808 if (ret) 9809 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret); 9810 9811 trace_ufshcd_wl_runtime_resume(dev_name(dev), ret, 9812 ktime_to_us(ktime_sub(ktime_get(), start)), 9813 hba->curr_dev_pwr_mode, hba->uic_link_state); 9814 9815 return ret; 9816 } 9817 #endif 9818 9819 #ifdef CONFIG_PM_SLEEP 9820 static int ufshcd_wl_suspend(struct device *dev) 9821 { 9822 struct scsi_device *sdev = to_scsi_device(dev); 9823 struct ufs_hba *hba; 9824 int ret = 0; 9825 ktime_t start = ktime_get(); 9826 9827 hba = shost_priv(sdev->host); 9828 down(&hba->host_sem); 9829 hba->system_suspending = true; 9830 9831 if (pm_runtime_suspended(dev)) 9832 goto out; 9833 9834 ret = __ufshcd_wl_suspend(hba, UFS_SYSTEM_PM); 9835 if (ret) { 9836 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret); 9837 up(&hba->host_sem); 9838 } 9839 9840 out: 9841 if (!ret) 9842 hba->is_sys_suspended = true; 9843 trace_ufshcd_wl_suspend(dev_name(dev), ret, 9844 ktime_to_us(ktime_sub(ktime_get(), start)), 9845 hba->curr_dev_pwr_mode, hba->uic_link_state); 9846 9847 return ret; 9848 } 9849 9850 static int ufshcd_wl_resume(struct device *dev) 9851 { 9852 struct scsi_device *sdev = to_scsi_device(dev); 9853 struct ufs_hba *hba; 9854 int ret = 0; 9855 ktime_t start = ktime_get(); 9856 9857 hba = shost_priv(sdev->host); 9858 9859 if (pm_runtime_suspended(dev)) 9860 goto out; 9861 9862 ret = __ufshcd_wl_resume(hba, UFS_SYSTEM_PM); 9863 if (ret) 9864 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret); 9865 out: 9866 trace_ufshcd_wl_resume(dev_name(dev), ret, 9867 ktime_to_us(ktime_sub(ktime_get(), start)), 9868 hba->curr_dev_pwr_mode, hba->uic_link_state); 9869 if (!ret) 9870 hba->is_sys_suspended = false; 9871 hba->system_suspending = false; 9872 up(&hba->host_sem); 9873 return ret; 9874 } 9875 #endif 9876 9877 /** 9878 * ufshcd_suspend - helper function for suspend operations 9879 * @hba: per adapter instance 9880 * 9881 * This function will put disable irqs, turn off clocks 9882 * and set vreg and hba-vreg in lpm mode. 9883 * 9884 * Return: 0 upon success; < 0 upon failure. 9885 */ 9886 static int ufshcd_suspend(struct ufs_hba *hba) 9887 { 9888 int ret; 9889 9890 if (!hba->is_powered) 9891 return 0; 9892 /* 9893 * Disable the host irq as host controller as there won't be any 9894 * host controller transaction expected till resume. 9895 */ 9896 ufshcd_disable_irq(hba); 9897 ret = ufshcd_setup_clocks(hba, false); 9898 if (ret) { 9899 ufshcd_enable_irq(hba); 9900 return ret; 9901 } 9902 if (ufshcd_is_clkgating_allowed(hba)) { 9903 hba->clk_gating.state = CLKS_OFF; 9904 trace_ufshcd_clk_gating(dev_name(hba->dev), 9905 hba->clk_gating.state); 9906 } 9907 9908 ufshcd_vreg_set_lpm(hba); 9909 /* Put the host controller in low power mode if possible */ 9910 ufshcd_hba_vreg_set_lpm(hba); 9911 return ret; 9912 } 9913 9914 #ifdef CONFIG_PM 9915 /** 9916 * ufshcd_resume - helper function for resume operations 9917 * @hba: per adapter instance 9918 * 9919 * This function basically turns on the regulators, clocks and 9920 * irqs of the hba. 9921 * 9922 * Return: 0 for success and non-zero for failure. 9923 */ 9924 static int ufshcd_resume(struct ufs_hba *hba) 9925 { 9926 int ret; 9927 9928 if (!hba->is_powered) 9929 return 0; 9930 9931 ufshcd_hba_vreg_set_hpm(hba); 9932 ret = ufshcd_vreg_set_hpm(hba); 9933 if (ret) 9934 goto out; 9935 9936 /* Make sure clocks are enabled before accessing controller */ 9937 ret = ufshcd_setup_clocks(hba, true); 9938 if (ret) 9939 goto disable_vreg; 9940 9941 /* enable the host irq as host controller would be active soon */ 9942 ufshcd_enable_irq(hba); 9943 9944 goto out; 9945 9946 disable_vreg: 9947 ufshcd_vreg_set_lpm(hba); 9948 out: 9949 if (ret) 9950 ufshcd_update_evt_hist(hba, UFS_EVT_RESUME_ERR, (u32)ret); 9951 return ret; 9952 } 9953 #endif /* CONFIG_PM */ 9954 9955 #ifdef CONFIG_PM_SLEEP 9956 /** 9957 * ufshcd_system_suspend - system suspend callback 9958 * @dev: Device associated with the UFS controller. 9959 * 9960 * Executed before putting the system into a sleep state in which the contents 9961 * of main memory are preserved. 9962 * 9963 * Return: 0 for success and non-zero for failure. 9964 */ 9965 int ufshcd_system_suspend(struct device *dev) 9966 { 9967 struct ufs_hba *hba = dev_get_drvdata(dev); 9968 int ret = 0; 9969 ktime_t start = ktime_get(); 9970 9971 if (pm_runtime_suspended(hba->dev)) 9972 goto out; 9973 9974 ret = ufshcd_suspend(hba); 9975 out: 9976 trace_ufshcd_system_suspend(dev_name(hba->dev), ret, 9977 ktime_to_us(ktime_sub(ktime_get(), start)), 9978 hba->curr_dev_pwr_mode, hba->uic_link_state); 9979 return ret; 9980 } 9981 EXPORT_SYMBOL(ufshcd_system_suspend); 9982 9983 /** 9984 * ufshcd_system_resume - system resume callback 9985 * @dev: Device associated with the UFS controller. 9986 * 9987 * Executed after waking the system up from a sleep state in which the contents 9988 * of main memory were preserved. 9989 * 9990 * Return: 0 for success and non-zero for failure. 9991 */ 9992 int ufshcd_system_resume(struct device *dev) 9993 { 9994 struct ufs_hba *hba = dev_get_drvdata(dev); 9995 ktime_t start = ktime_get(); 9996 int ret = 0; 9997 9998 if (pm_runtime_suspended(hba->dev)) 9999 goto out; 10000 10001 ret = ufshcd_resume(hba); 10002 10003 out: 10004 trace_ufshcd_system_resume(dev_name(hba->dev), ret, 10005 ktime_to_us(ktime_sub(ktime_get(), start)), 10006 hba->curr_dev_pwr_mode, hba->uic_link_state); 10007 10008 return ret; 10009 } 10010 EXPORT_SYMBOL(ufshcd_system_resume); 10011 #endif /* CONFIG_PM_SLEEP */ 10012 10013 #ifdef CONFIG_PM 10014 /** 10015 * ufshcd_runtime_suspend - runtime suspend callback 10016 * @dev: Device associated with the UFS controller. 10017 * 10018 * Check the description of ufshcd_suspend() function for more details. 10019 * 10020 * Return: 0 for success and non-zero for failure. 10021 */ 10022 int ufshcd_runtime_suspend(struct device *dev) 10023 { 10024 struct ufs_hba *hba = dev_get_drvdata(dev); 10025 int ret; 10026 ktime_t start = ktime_get(); 10027 10028 ret = ufshcd_suspend(hba); 10029 10030 trace_ufshcd_runtime_suspend(dev_name(hba->dev), ret, 10031 ktime_to_us(ktime_sub(ktime_get(), start)), 10032 hba->curr_dev_pwr_mode, hba->uic_link_state); 10033 return ret; 10034 } 10035 EXPORT_SYMBOL(ufshcd_runtime_suspend); 10036 10037 /** 10038 * ufshcd_runtime_resume - runtime resume routine 10039 * @dev: Device associated with the UFS controller. 10040 * 10041 * This function basically brings controller 10042 * to active state. Following operations are done in this function: 10043 * 10044 * 1. Turn on all the controller related clocks 10045 * 2. Turn ON VCC rail 10046 * 10047 * Return: 0 upon success; < 0 upon failure. 10048 */ 10049 int ufshcd_runtime_resume(struct device *dev) 10050 { 10051 struct ufs_hba *hba = dev_get_drvdata(dev); 10052 int ret; 10053 ktime_t start = ktime_get(); 10054 10055 ret = ufshcd_resume(hba); 10056 10057 trace_ufshcd_runtime_resume(dev_name(hba->dev), ret, 10058 ktime_to_us(ktime_sub(ktime_get(), start)), 10059 hba->curr_dev_pwr_mode, hba->uic_link_state); 10060 return ret; 10061 } 10062 EXPORT_SYMBOL(ufshcd_runtime_resume); 10063 #endif /* CONFIG_PM */ 10064 10065 static void ufshcd_wl_shutdown(struct device *dev) 10066 { 10067 struct scsi_device *sdev = to_scsi_device(dev); 10068 struct ufs_hba *hba = shost_priv(sdev->host); 10069 10070 down(&hba->host_sem); 10071 hba->shutting_down = true; 10072 up(&hba->host_sem); 10073 10074 /* Turn on everything while shutting down */ 10075 ufshcd_rpm_get_sync(hba); 10076 scsi_device_quiesce(sdev); 10077 shost_for_each_device(sdev, hba->host) { 10078 if (sdev == hba->ufs_device_wlun) 10079 continue; 10080 scsi_device_quiesce(sdev); 10081 } 10082 __ufshcd_wl_suspend(hba, UFS_SHUTDOWN_PM); 10083 10084 /* 10085 * Next, turn off the UFS controller and the UFS regulators. Disable 10086 * clocks. 10087 */ 10088 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba)) 10089 ufshcd_suspend(hba); 10090 10091 hba->is_powered = false; 10092 } 10093 10094 /** 10095 * ufshcd_remove - de-allocate SCSI host and host memory space 10096 * data structure memory 10097 * @hba: per adapter instance 10098 */ 10099 void ufshcd_remove(struct ufs_hba *hba) 10100 { 10101 if (hba->ufs_device_wlun) 10102 ufshcd_rpm_get_sync(hba); 10103 ufs_hwmon_remove(hba); 10104 ufs_bsg_remove(hba); 10105 ufs_sysfs_remove_nodes(hba->dev); 10106 blk_mq_destroy_queue(hba->tmf_queue); 10107 blk_put_queue(hba->tmf_queue); 10108 blk_mq_free_tag_set(&hba->tmf_tag_set); 10109 scsi_remove_host(hba->host); 10110 /* disable interrupts */ 10111 ufshcd_disable_intr(hba, hba->intr_mask); 10112 ufshcd_hba_stop(hba); 10113 ufshcd_hba_exit(hba); 10114 } 10115 EXPORT_SYMBOL_GPL(ufshcd_remove); 10116 10117 #ifdef CONFIG_PM_SLEEP 10118 int ufshcd_system_freeze(struct device *dev) 10119 { 10120 10121 return ufshcd_system_suspend(dev); 10122 10123 } 10124 EXPORT_SYMBOL_GPL(ufshcd_system_freeze); 10125 10126 int ufshcd_system_restore(struct device *dev) 10127 { 10128 10129 struct ufs_hba *hba = dev_get_drvdata(dev); 10130 int ret; 10131 10132 ret = ufshcd_system_resume(dev); 10133 if (ret) 10134 return ret; 10135 10136 /* Configure UTRL and UTMRL base address registers */ 10137 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr), 10138 REG_UTP_TRANSFER_REQ_LIST_BASE_L); 10139 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr), 10140 REG_UTP_TRANSFER_REQ_LIST_BASE_H); 10141 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr), 10142 REG_UTP_TASK_REQ_LIST_BASE_L); 10143 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr), 10144 REG_UTP_TASK_REQ_LIST_BASE_H); 10145 /* 10146 * Make sure that UTRL and UTMRL base address registers 10147 * are updated with the latest queue addresses. Only after 10148 * updating these addresses, we can queue the new commands. 10149 */ 10150 mb(); 10151 10152 /* Resuming from hibernate, assume that link was OFF */ 10153 ufshcd_set_link_off(hba); 10154 10155 return 0; 10156 10157 } 10158 EXPORT_SYMBOL_GPL(ufshcd_system_restore); 10159 10160 int ufshcd_system_thaw(struct device *dev) 10161 { 10162 return ufshcd_system_resume(dev); 10163 } 10164 EXPORT_SYMBOL_GPL(ufshcd_system_thaw); 10165 #endif /* CONFIG_PM_SLEEP */ 10166 10167 /** 10168 * ufshcd_dealloc_host - deallocate Host Bus Adapter (HBA) 10169 * @hba: pointer to Host Bus Adapter (HBA) 10170 */ 10171 void ufshcd_dealloc_host(struct ufs_hba *hba) 10172 { 10173 scsi_host_put(hba->host); 10174 } 10175 EXPORT_SYMBOL_GPL(ufshcd_dealloc_host); 10176 10177 /** 10178 * ufshcd_set_dma_mask - Set dma mask based on the controller 10179 * addressing capability 10180 * @hba: per adapter instance 10181 * 10182 * Return: 0 for success, non-zero for failure. 10183 */ 10184 static int ufshcd_set_dma_mask(struct ufs_hba *hba) 10185 { 10186 if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) { 10187 if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64))) 10188 return 0; 10189 } 10190 return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32)); 10191 } 10192 10193 /** 10194 * ufshcd_alloc_host - allocate Host Bus Adapter (HBA) 10195 * @dev: pointer to device handle 10196 * @hba_handle: driver private handle 10197 * 10198 * Return: 0 on success, non-zero value on failure. 10199 */ 10200 int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle) 10201 { 10202 struct Scsi_Host *host; 10203 struct ufs_hba *hba; 10204 int err = 0; 10205 10206 if (!dev) { 10207 dev_err(dev, 10208 "Invalid memory reference for dev is NULL\n"); 10209 err = -ENODEV; 10210 goto out_error; 10211 } 10212 10213 host = scsi_host_alloc(&ufshcd_driver_template, 10214 sizeof(struct ufs_hba)); 10215 if (!host) { 10216 dev_err(dev, "scsi_host_alloc failed\n"); 10217 err = -ENOMEM; 10218 goto out_error; 10219 } 10220 host->nr_maps = HCTX_TYPE_POLL + 1; 10221 hba = shost_priv(host); 10222 hba->host = host; 10223 hba->dev = dev; 10224 hba->dev_ref_clk_freq = REF_CLK_FREQ_INVAL; 10225 hba->nop_out_timeout = NOP_OUT_TIMEOUT; 10226 ufshcd_set_sg_entry_size(hba, sizeof(struct ufshcd_sg_entry)); 10227 INIT_LIST_HEAD(&hba->clk_list_head); 10228 spin_lock_init(&hba->outstanding_lock); 10229 10230 *hba_handle = hba; 10231 10232 out_error: 10233 return err; 10234 } 10235 EXPORT_SYMBOL(ufshcd_alloc_host); 10236 10237 /* This function exists because blk_mq_alloc_tag_set() requires this. */ 10238 static blk_status_t ufshcd_queue_tmf(struct blk_mq_hw_ctx *hctx, 10239 const struct blk_mq_queue_data *qd) 10240 { 10241 WARN_ON_ONCE(true); 10242 return BLK_STS_NOTSUPP; 10243 } 10244 10245 static const struct blk_mq_ops ufshcd_tmf_ops = { 10246 .queue_rq = ufshcd_queue_tmf, 10247 }; 10248 10249 /** 10250 * ufshcd_init - Driver initialization routine 10251 * @hba: per-adapter instance 10252 * @mmio_base: base register address 10253 * @irq: Interrupt line of device 10254 * 10255 * Return: 0 on success, non-zero value on failure. 10256 */ 10257 int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq) 10258 { 10259 int err; 10260 struct Scsi_Host *host = hba->host; 10261 struct device *dev = hba->dev; 10262 char eh_wq_name[sizeof("ufs_eh_wq_00")]; 10263 10264 /* 10265 * dev_set_drvdata() must be called before any callbacks are registered 10266 * that use dev_get_drvdata() (frequency scaling, clock scaling, hwmon, 10267 * sysfs). 10268 */ 10269 dev_set_drvdata(dev, hba); 10270 10271 if (!mmio_base) { 10272 dev_err(hba->dev, 10273 "Invalid memory reference for mmio_base is NULL\n"); 10274 err = -ENODEV; 10275 goto out_error; 10276 } 10277 10278 hba->mmio_base = mmio_base; 10279 hba->irq = irq; 10280 hba->vps = &ufs_hba_vps; 10281 10282 err = ufshcd_hba_init(hba); 10283 if (err) 10284 goto out_error; 10285 10286 /* Read capabilities registers */ 10287 err = ufshcd_hba_capabilities(hba); 10288 if (err) 10289 goto out_disable; 10290 10291 /* Get UFS version supported by the controller */ 10292 hba->ufs_version = ufshcd_get_ufs_version(hba); 10293 10294 /* Get Interrupt bit mask per version */ 10295 hba->intr_mask = ufshcd_get_intr_mask(hba); 10296 10297 err = ufshcd_set_dma_mask(hba); 10298 if (err) { 10299 dev_err(hba->dev, "set dma mask failed\n"); 10300 goto out_disable; 10301 } 10302 10303 /* Allocate memory for host memory space */ 10304 err = ufshcd_memory_alloc(hba); 10305 if (err) { 10306 dev_err(hba->dev, "Memory allocation failed\n"); 10307 goto out_disable; 10308 } 10309 10310 /* Configure LRB */ 10311 ufshcd_host_memory_configure(hba); 10312 10313 host->can_queue = hba->nutrs - UFSHCD_NUM_RESERVED; 10314 host->cmd_per_lun = hba->nutrs - UFSHCD_NUM_RESERVED; 10315 host->max_id = UFSHCD_MAX_ID; 10316 host->max_lun = UFS_MAX_LUNS; 10317 host->max_channel = UFSHCD_MAX_CHANNEL; 10318 host->unique_id = host->host_no; 10319 host->max_cmd_len = UFS_CDB_SIZE; 10320 host->queuecommand_may_block = !!(hba->caps & UFSHCD_CAP_CLK_GATING); 10321 10322 hba->max_pwr_info.is_valid = false; 10323 10324 /* Initialize work queues */ 10325 snprintf(eh_wq_name, sizeof(eh_wq_name), "ufs_eh_wq_%d", 10326 hba->host->host_no); 10327 hba->eh_wq = create_singlethread_workqueue(eh_wq_name); 10328 if (!hba->eh_wq) { 10329 dev_err(hba->dev, "%s: failed to create eh workqueue\n", 10330 __func__); 10331 err = -ENOMEM; 10332 goto out_disable; 10333 } 10334 INIT_WORK(&hba->eh_work, ufshcd_err_handler); 10335 INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler); 10336 10337 sema_init(&hba->host_sem, 1); 10338 10339 /* Initialize UIC command mutex */ 10340 mutex_init(&hba->uic_cmd_mutex); 10341 10342 /* Initialize mutex for device management commands */ 10343 mutex_init(&hba->dev_cmd.lock); 10344 10345 /* Initialize mutex for exception event control */ 10346 mutex_init(&hba->ee_ctrl_mutex); 10347 10348 mutex_init(&hba->wb_mutex); 10349 init_rwsem(&hba->clk_scaling_lock); 10350 10351 ufshcd_init_clk_gating(hba); 10352 10353 ufshcd_init_clk_scaling(hba); 10354 10355 /* 10356 * In order to avoid any spurious interrupt immediately after 10357 * registering UFS controller interrupt handler, clear any pending UFS 10358 * interrupt status and disable all the UFS interrupts. 10359 */ 10360 ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS), 10361 REG_INTERRUPT_STATUS); 10362 ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE); 10363 /* 10364 * Make sure that UFS interrupts are disabled and any pending interrupt 10365 * status is cleared before registering UFS interrupt handler. 10366 */ 10367 mb(); 10368 10369 /* IRQ registration */ 10370 err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba); 10371 if (err) { 10372 dev_err(hba->dev, "request irq failed\n"); 10373 goto out_disable; 10374 } else { 10375 hba->is_irq_enabled = true; 10376 } 10377 10378 if (!is_mcq_supported(hba)) { 10379 err = scsi_add_host(host, hba->dev); 10380 if (err) { 10381 dev_err(hba->dev, "scsi_add_host failed\n"); 10382 goto out_disable; 10383 } 10384 } 10385 10386 hba->tmf_tag_set = (struct blk_mq_tag_set) { 10387 .nr_hw_queues = 1, 10388 .queue_depth = hba->nutmrs, 10389 .ops = &ufshcd_tmf_ops, 10390 .flags = BLK_MQ_F_NO_SCHED, 10391 }; 10392 err = blk_mq_alloc_tag_set(&hba->tmf_tag_set); 10393 if (err < 0) 10394 goto out_remove_scsi_host; 10395 hba->tmf_queue = blk_mq_init_queue(&hba->tmf_tag_set); 10396 if (IS_ERR(hba->tmf_queue)) { 10397 err = PTR_ERR(hba->tmf_queue); 10398 goto free_tmf_tag_set; 10399 } 10400 hba->tmf_rqs = devm_kcalloc(hba->dev, hba->nutmrs, 10401 sizeof(*hba->tmf_rqs), GFP_KERNEL); 10402 if (!hba->tmf_rqs) { 10403 err = -ENOMEM; 10404 goto free_tmf_queue; 10405 } 10406 10407 /* Reset the attached device */ 10408 ufshcd_device_reset(hba); 10409 10410 ufshcd_init_crypto(hba); 10411 10412 /* Host controller enable */ 10413 err = ufshcd_hba_enable(hba); 10414 if (err) { 10415 dev_err(hba->dev, "Host controller enable failed\n"); 10416 ufshcd_print_evt_hist(hba); 10417 ufshcd_print_host_state(hba); 10418 goto free_tmf_queue; 10419 } 10420 10421 /* 10422 * Set the default power management level for runtime and system PM. 10423 * Default power saving mode is to keep UFS link in Hibern8 state 10424 * and UFS device in sleep state. 10425 */ 10426 hba->rpm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state( 10427 UFS_SLEEP_PWR_MODE, 10428 UIC_LINK_HIBERN8_STATE); 10429 hba->spm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state( 10430 UFS_SLEEP_PWR_MODE, 10431 UIC_LINK_HIBERN8_STATE); 10432 10433 INIT_DELAYED_WORK(&hba->rpm_dev_flush_recheck_work, 10434 ufshcd_rpm_dev_flush_recheck_work); 10435 10436 /* Set the default auto-hiberate idle timer value to 150 ms */ 10437 if (ufshcd_is_auto_hibern8_supported(hba) && !hba->ahit) { 10438 hba->ahit = FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, 150) | 10439 FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3); 10440 } 10441 10442 /* Hold auto suspend until async scan completes */ 10443 pm_runtime_get_sync(dev); 10444 atomic_set(&hba->scsi_block_reqs_cnt, 0); 10445 /* 10446 * We are assuming that device wasn't put in sleep/power-down 10447 * state exclusively during the boot stage before kernel. 10448 * This assumption helps avoid doing link startup twice during 10449 * ufshcd_probe_hba(). 10450 */ 10451 ufshcd_set_ufs_dev_active(hba); 10452 10453 async_schedule(ufshcd_async_scan, hba); 10454 ufs_sysfs_add_nodes(hba->dev); 10455 10456 device_enable_async_suspend(dev); 10457 return 0; 10458 10459 free_tmf_queue: 10460 blk_mq_destroy_queue(hba->tmf_queue); 10461 blk_put_queue(hba->tmf_queue); 10462 free_tmf_tag_set: 10463 blk_mq_free_tag_set(&hba->tmf_tag_set); 10464 out_remove_scsi_host: 10465 scsi_remove_host(hba->host); 10466 out_disable: 10467 hba->is_irq_enabled = false; 10468 ufshcd_hba_exit(hba); 10469 out_error: 10470 return err; 10471 } 10472 EXPORT_SYMBOL_GPL(ufshcd_init); 10473 10474 void ufshcd_resume_complete(struct device *dev) 10475 { 10476 struct ufs_hba *hba = dev_get_drvdata(dev); 10477 10478 if (hba->complete_put) { 10479 ufshcd_rpm_put(hba); 10480 hba->complete_put = false; 10481 } 10482 } 10483 EXPORT_SYMBOL_GPL(ufshcd_resume_complete); 10484 10485 static bool ufshcd_rpm_ok_for_spm(struct ufs_hba *hba) 10486 { 10487 struct device *dev = &hba->ufs_device_wlun->sdev_gendev; 10488 enum ufs_dev_pwr_mode dev_pwr_mode; 10489 enum uic_link_state link_state; 10490 unsigned long flags; 10491 bool res; 10492 10493 spin_lock_irqsave(&dev->power.lock, flags); 10494 dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl); 10495 link_state = ufs_get_pm_lvl_to_link_pwr_state(hba->spm_lvl); 10496 res = pm_runtime_suspended(dev) && 10497 hba->curr_dev_pwr_mode == dev_pwr_mode && 10498 hba->uic_link_state == link_state && 10499 !hba->dev_info.b_rpm_dev_flush_capable; 10500 spin_unlock_irqrestore(&dev->power.lock, flags); 10501 10502 return res; 10503 } 10504 10505 int __ufshcd_suspend_prepare(struct device *dev, bool rpm_ok_for_spm) 10506 { 10507 struct ufs_hba *hba = dev_get_drvdata(dev); 10508 int ret; 10509 10510 /* 10511 * SCSI assumes that runtime-pm and system-pm for scsi drivers 10512 * are same. And it doesn't wake up the device for system-suspend 10513 * if it's runtime suspended. But ufs doesn't follow that. 10514 * Refer ufshcd_resume_complete() 10515 */ 10516 if (hba->ufs_device_wlun) { 10517 /* Prevent runtime suspend */ 10518 ufshcd_rpm_get_noresume(hba); 10519 /* 10520 * Check if already runtime suspended in same state as system 10521 * suspend would be. 10522 */ 10523 if (!rpm_ok_for_spm || !ufshcd_rpm_ok_for_spm(hba)) { 10524 /* RPM state is not ok for SPM, so runtime resume */ 10525 ret = ufshcd_rpm_resume(hba); 10526 if (ret < 0 && ret != -EACCES) { 10527 ufshcd_rpm_put(hba); 10528 return ret; 10529 } 10530 } 10531 hba->complete_put = true; 10532 } 10533 return 0; 10534 } 10535 EXPORT_SYMBOL_GPL(__ufshcd_suspend_prepare); 10536 10537 int ufshcd_suspend_prepare(struct device *dev) 10538 { 10539 return __ufshcd_suspend_prepare(dev, true); 10540 } 10541 EXPORT_SYMBOL_GPL(ufshcd_suspend_prepare); 10542 10543 #ifdef CONFIG_PM_SLEEP 10544 static int ufshcd_wl_poweroff(struct device *dev) 10545 { 10546 struct scsi_device *sdev = to_scsi_device(dev); 10547 struct ufs_hba *hba = shost_priv(sdev->host); 10548 10549 __ufshcd_wl_suspend(hba, UFS_SHUTDOWN_PM); 10550 return 0; 10551 } 10552 #endif 10553 10554 static int ufshcd_wl_probe(struct device *dev) 10555 { 10556 struct scsi_device *sdev = to_scsi_device(dev); 10557 10558 if (!is_device_wlun(sdev)) 10559 return -ENODEV; 10560 10561 blk_pm_runtime_init(sdev->request_queue, dev); 10562 pm_runtime_set_autosuspend_delay(dev, 0); 10563 pm_runtime_allow(dev); 10564 10565 return 0; 10566 } 10567 10568 static int ufshcd_wl_remove(struct device *dev) 10569 { 10570 pm_runtime_forbid(dev); 10571 return 0; 10572 } 10573 10574 static const struct dev_pm_ops ufshcd_wl_pm_ops = { 10575 #ifdef CONFIG_PM_SLEEP 10576 .suspend = ufshcd_wl_suspend, 10577 .resume = ufshcd_wl_resume, 10578 .freeze = ufshcd_wl_suspend, 10579 .thaw = ufshcd_wl_resume, 10580 .poweroff = ufshcd_wl_poweroff, 10581 .restore = ufshcd_wl_resume, 10582 #endif 10583 SET_RUNTIME_PM_OPS(ufshcd_wl_runtime_suspend, ufshcd_wl_runtime_resume, NULL) 10584 }; 10585 10586 static void ufshcd_check_header_layout(void) 10587 { 10588 /* 10589 * gcc compilers before version 10 cannot do constant-folding for 10590 * sub-byte bitfields. Hence skip the layout checks for gcc 9 and 10591 * before. 10592 */ 10593 if (IS_ENABLED(CONFIG_CC_IS_GCC) && CONFIG_GCC_VERSION < 100000) 10594 return; 10595 10596 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10597 .cci = 3})[0] != 3); 10598 10599 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10600 .ehs_length = 2})[1] != 2); 10601 10602 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10603 .enable_crypto = 1})[2] 10604 != 0x80); 10605 10606 BUILD_BUG_ON((((u8 *)&(struct request_desc_header){ 10607 .command_type = 5, 10608 .data_direction = 3, 10609 .interrupt = 1, 10610 })[3]) != ((5 << 4) | (3 << 1) | 1)); 10611 10612 BUILD_BUG_ON(((__le32 *)&(struct request_desc_header){ 10613 .dunl = cpu_to_le32(0xdeadbeef)})[1] != 10614 cpu_to_le32(0xdeadbeef)); 10615 10616 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10617 .ocs = 4})[8] != 4); 10618 10619 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10620 .cds = 5})[9] != 5); 10621 10622 BUILD_BUG_ON(((__le32 *)&(struct request_desc_header){ 10623 .dunu = cpu_to_le32(0xbadcafe)})[3] != 10624 cpu_to_le32(0xbadcafe)); 10625 10626 BUILD_BUG_ON(((u8 *)&(struct utp_upiu_header){ 10627 .iid = 0xf })[4] != 0xf0); 10628 10629 BUILD_BUG_ON(((u8 *)&(struct utp_upiu_header){ 10630 .command_set_type = 0xf })[4] != 0xf); 10631 } 10632 10633 /* 10634 * ufs_dev_wlun_template - describes ufs device wlun 10635 * ufs-device wlun - used to send pm commands 10636 * All luns are consumers of ufs-device wlun. 10637 * 10638 * Currently, no sd driver is present for wluns. 10639 * Hence the no specific pm operations are performed. 10640 * With ufs design, SSU should be sent to ufs-device wlun. 10641 * Hence register a scsi driver for ufs wluns only. 10642 */ 10643 static struct scsi_driver ufs_dev_wlun_template = { 10644 .gendrv = { 10645 .name = "ufs_device_wlun", 10646 .owner = THIS_MODULE, 10647 .probe = ufshcd_wl_probe, 10648 .remove = ufshcd_wl_remove, 10649 .pm = &ufshcd_wl_pm_ops, 10650 .shutdown = ufshcd_wl_shutdown, 10651 }, 10652 }; 10653 10654 static int __init ufshcd_core_init(void) 10655 { 10656 int ret; 10657 10658 ufshcd_check_header_layout(); 10659 10660 ufs_debugfs_init(); 10661 10662 ret = scsi_register_driver(&ufs_dev_wlun_template.gendrv); 10663 if (ret) 10664 ufs_debugfs_exit(); 10665 return ret; 10666 } 10667 10668 static void __exit ufshcd_core_exit(void) 10669 { 10670 ufs_debugfs_exit(); 10671 scsi_unregister_driver(&ufs_dev_wlun_template.gendrv); 10672 } 10673 10674 module_init(ufshcd_core_init); 10675 module_exit(ufshcd_core_exit); 10676 10677 MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>"); 10678 MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>"); 10679 MODULE_DESCRIPTION("Generic UFS host controller driver Core"); 10680 MODULE_SOFTDEP("pre: governor_simpleondemand"); 10681 MODULE_LICENSE("GPL"); 10682