1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Universal Flash Storage Host controller driver Core 4 * Copyright (C) 2011-2013 Samsung India Software Operations 5 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. 6 * 7 * Authors: 8 * Santosh Yaraganavi <santosh.sy@samsung.com> 9 * Vinayak Holikatti <h.vinayak@samsung.com> 10 */ 11 12 #include <linux/async.h> 13 #include <linux/devfreq.h> 14 #include <linux/nls.h> 15 #include <linux/of.h> 16 #include <linux/bitfield.h> 17 #include <linux/blk-pm.h> 18 #include <linux/blkdev.h> 19 #include <linux/clk.h> 20 #include <linux/delay.h> 21 #include <linux/interrupt.h> 22 #include <linux/module.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/sched/clock.h> 25 #include <linux/iopoll.h> 26 #include <scsi/scsi_cmnd.h> 27 #include <scsi/scsi_dbg.h> 28 #include <scsi/scsi_driver.h> 29 #include <scsi/scsi_eh.h> 30 #include "ufshcd-priv.h" 31 #include <ufs/ufs_quirks.h> 32 #include <ufs/unipro.h> 33 #include "ufs-sysfs.h" 34 #include "ufs-debugfs.h" 35 #include "ufs-fault-injection.h" 36 #include "ufs_bsg.h" 37 #include "ufshcd-crypto.h" 38 #include <asm/unaligned.h> 39 40 #define CREATE_TRACE_POINTS 41 #include <trace/events/ufs.h> 42 43 #define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\ 44 UTP_TASK_REQ_COMPL |\ 45 UFSHCD_ERROR_MASK) 46 47 #define UFSHCD_ENABLE_MCQ_INTRS (UTP_TASK_REQ_COMPL |\ 48 UFSHCD_ERROR_MASK |\ 49 MCQ_CQ_EVENT_STATUS) 50 51 52 /* UIC command timeout, unit: ms */ 53 #define UIC_CMD_TIMEOUT 500 54 55 /* NOP OUT retries waiting for NOP IN response */ 56 #define NOP_OUT_RETRIES 10 57 /* Timeout after 50 msecs if NOP OUT hangs without response */ 58 #define NOP_OUT_TIMEOUT 50 /* msecs */ 59 60 /* Query request retries */ 61 #define QUERY_REQ_RETRIES 3 62 /* Query request timeout */ 63 #define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */ 64 65 /* Advanced RPMB request timeout */ 66 #define ADVANCED_RPMB_REQ_TIMEOUT 3000 /* 3 seconds */ 67 68 /* Task management command timeout */ 69 #define TM_CMD_TIMEOUT 100 /* msecs */ 70 71 /* maximum number of retries for a general UIC command */ 72 #define UFS_UIC_COMMAND_RETRIES 3 73 74 /* maximum number of link-startup retries */ 75 #define DME_LINKSTARTUP_RETRIES 3 76 77 /* maximum number of reset retries before giving up */ 78 #define MAX_HOST_RESET_RETRIES 5 79 80 /* Maximum number of error handler retries before giving up */ 81 #define MAX_ERR_HANDLER_RETRIES 5 82 83 /* Expose the flag value from utp_upiu_query.value */ 84 #define MASK_QUERY_UPIU_FLAG_LOC 0xFF 85 86 /* Interrupt aggregation default timeout, unit: 40us */ 87 #define INT_AGGR_DEF_TO 0x02 88 89 /* default delay of autosuspend: 2000 ms */ 90 #define RPM_AUTOSUSPEND_DELAY_MS 2000 91 92 /* Default delay of RPM device flush delayed work */ 93 #define RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS 5000 94 95 /* Default value of wait time before gating device ref clock */ 96 #define UFSHCD_REF_CLK_GATING_WAIT_US 0xFF /* microsecs */ 97 98 /* Polling time to wait for fDeviceInit */ 99 #define FDEVICEINIT_COMPL_TIMEOUT 1500 /* millisecs */ 100 101 /* UFSHC 4.0 compliant HC support this mode. */ 102 static bool use_mcq_mode = true; 103 104 static bool is_mcq_supported(struct ufs_hba *hba) 105 { 106 return hba->mcq_sup && use_mcq_mode; 107 } 108 109 module_param(use_mcq_mode, bool, 0644); 110 MODULE_PARM_DESC(use_mcq_mode, "Control MCQ mode for controllers starting from UFSHCI 4.0. 1 - enable MCQ, 0 - disable MCQ. MCQ is enabled by default"); 111 112 #define ufshcd_toggle_vreg(_dev, _vreg, _on) \ 113 ({ \ 114 int _ret; \ 115 if (_on) \ 116 _ret = ufshcd_enable_vreg(_dev, _vreg); \ 117 else \ 118 _ret = ufshcd_disable_vreg(_dev, _vreg); \ 119 _ret; \ 120 }) 121 122 #define ufshcd_hex_dump(prefix_str, buf, len) do { \ 123 size_t __len = (len); \ 124 print_hex_dump(KERN_ERR, prefix_str, \ 125 __len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE,\ 126 16, 4, buf, __len, false); \ 127 } while (0) 128 129 int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len, 130 const char *prefix) 131 { 132 u32 *regs; 133 size_t pos; 134 135 if (offset % 4 != 0 || len % 4 != 0) /* keep readl happy */ 136 return -EINVAL; 137 138 regs = kzalloc(len, GFP_ATOMIC); 139 if (!regs) 140 return -ENOMEM; 141 142 for (pos = 0; pos < len; pos += 4) { 143 if (offset == 0 && 144 pos >= REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER && 145 pos <= REG_UIC_ERROR_CODE_DME) 146 continue; 147 regs[pos / 4] = ufshcd_readl(hba, offset + pos); 148 } 149 150 ufshcd_hex_dump(prefix, regs, len); 151 kfree(regs); 152 153 return 0; 154 } 155 EXPORT_SYMBOL_GPL(ufshcd_dump_regs); 156 157 enum { 158 UFSHCD_MAX_CHANNEL = 0, 159 UFSHCD_MAX_ID = 1, 160 UFSHCD_CMD_PER_LUN = 32 - UFSHCD_NUM_RESERVED, 161 UFSHCD_CAN_QUEUE = 32 - UFSHCD_NUM_RESERVED, 162 }; 163 164 static const char *const ufshcd_state_name[] = { 165 [UFSHCD_STATE_RESET] = "reset", 166 [UFSHCD_STATE_OPERATIONAL] = "operational", 167 [UFSHCD_STATE_ERROR] = "error", 168 [UFSHCD_STATE_EH_SCHEDULED_FATAL] = "eh_fatal", 169 [UFSHCD_STATE_EH_SCHEDULED_NON_FATAL] = "eh_non_fatal", 170 }; 171 172 /* UFSHCD error handling flags */ 173 enum { 174 UFSHCD_EH_IN_PROGRESS = (1 << 0), 175 }; 176 177 /* UFSHCD UIC layer error flags */ 178 enum { 179 UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */ 180 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR = (1 << 1), /* Data link layer error */ 181 UFSHCD_UIC_DL_TCx_REPLAY_ERROR = (1 << 2), /* Data link layer error */ 182 UFSHCD_UIC_NL_ERROR = (1 << 3), /* Network layer error */ 183 UFSHCD_UIC_TL_ERROR = (1 << 4), /* Transport Layer error */ 184 UFSHCD_UIC_DME_ERROR = (1 << 5), /* DME error */ 185 UFSHCD_UIC_PA_GENERIC_ERROR = (1 << 6), /* Generic PA error */ 186 }; 187 188 #define ufshcd_set_eh_in_progress(h) \ 189 ((h)->eh_flags |= UFSHCD_EH_IN_PROGRESS) 190 #define ufshcd_eh_in_progress(h) \ 191 ((h)->eh_flags & UFSHCD_EH_IN_PROGRESS) 192 #define ufshcd_clear_eh_in_progress(h) \ 193 ((h)->eh_flags &= ~UFSHCD_EH_IN_PROGRESS) 194 195 const struct ufs_pm_lvl_states ufs_pm_lvl_states[] = { 196 [UFS_PM_LVL_0] = {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE}, 197 [UFS_PM_LVL_1] = {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE}, 198 [UFS_PM_LVL_2] = {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE}, 199 [UFS_PM_LVL_3] = {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE}, 200 [UFS_PM_LVL_4] = {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE}, 201 [UFS_PM_LVL_5] = {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE}, 202 /* 203 * For DeepSleep, the link is first put in hibern8 and then off. 204 * Leaving the link in hibern8 is not supported. 205 */ 206 [UFS_PM_LVL_6] = {UFS_DEEPSLEEP_PWR_MODE, UIC_LINK_OFF_STATE}, 207 }; 208 209 static inline enum ufs_dev_pwr_mode 210 ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl) 211 { 212 return ufs_pm_lvl_states[lvl].dev_state; 213 } 214 215 static inline enum uic_link_state 216 ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl) 217 { 218 return ufs_pm_lvl_states[lvl].link_state; 219 } 220 221 static inline enum ufs_pm_level 222 ufs_get_desired_pm_lvl_for_dev_link_state(enum ufs_dev_pwr_mode dev_state, 223 enum uic_link_state link_state) 224 { 225 enum ufs_pm_level lvl; 226 227 for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++) { 228 if ((ufs_pm_lvl_states[lvl].dev_state == dev_state) && 229 (ufs_pm_lvl_states[lvl].link_state == link_state)) 230 return lvl; 231 } 232 233 /* if no match found, return the level 0 */ 234 return UFS_PM_LVL_0; 235 } 236 237 static const struct ufs_dev_quirk ufs_fixups[] = { 238 /* UFS cards deviations table */ 239 { .wmanufacturerid = UFS_VENDOR_MICRON, 240 .model = UFS_ANY_MODEL, 241 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM }, 242 { .wmanufacturerid = UFS_VENDOR_SAMSUNG, 243 .model = UFS_ANY_MODEL, 244 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM | 245 UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE | 246 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS }, 247 { .wmanufacturerid = UFS_VENDOR_SKHYNIX, 248 .model = UFS_ANY_MODEL, 249 .quirk = UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME }, 250 { .wmanufacturerid = UFS_VENDOR_SKHYNIX, 251 .model = "hB8aL1" /*H28U62301AMR*/, 252 .quirk = UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME }, 253 { .wmanufacturerid = UFS_VENDOR_TOSHIBA, 254 .model = UFS_ANY_MODEL, 255 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM }, 256 { .wmanufacturerid = UFS_VENDOR_TOSHIBA, 257 .model = "THGLF2G9C8KBADG", 258 .quirk = UFS_DEVICE_QUIRK_PA_TACTIVATE }, 259 { .wmanufacturerid = UFS_VENDOR_TOSHIBA, 260 .model = "THGLF2G9D8KBADG", 261 .quirk = UFS_DEVICE_QUIRK_PA_TACTIVATE }, 262 {} 263 }; 264 265 static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba); 266 static void ufshcd_async_scan(void *data, async_cookie_t cookie); 267 static int ufshcd_reset_and_restore(struct ufs_hba *hba); 268 static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd); 269 static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag); 270 static void ufshcd_hba_exit(struct ufs_hba *hba); 271 static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params); 272 static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on); 273 static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba); 274 static int ufshcd_host_reset_and_restore(struct ufs_hba *hba); 275 static void ufshcd_resume_clkscaling(struct ufs_hba *hba); 276 static void ufshcd_suspend_clkscaling(struct ufs_hba *hba); 277 static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba); 278 static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up); 279 static irqreturn_t ufshcd_intr(int irq, void *__hba); 280 static int ufshcd_change_power_mode(struct ufs_hba *hba, 281 struct ufs_pa_layer_attr *pwr_mode); 282 static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on); 283 static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on); 284 static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba, 285 struct ufs_vreg *vreg); 286 static void ufshcd_wb_toggle_buf_flush_during_h8(struct ufs_hba *hba, 287 bool enable); 288 static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba); 289 static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba); 290 291 static inline void ufshcd_enable_irq(struct ufs_hba *hba) 292 { 293 if (!hba->is_irq_enabled) { 294 enable_irq(hba->irq); 295 hba->is_irq_enabled = true; 296 } 297 } 298 299 static inline void ufshcd_disable_irq(struct ufs_hba *hba) 300 { 301 if (hba->is_irq_enabled) { 302 disable_irq(hba->irq); 303 hba->is_irq_enabled = false; 304 } 305 } 306 307 static void ufshcd_configure_wb(struct ufs_hba *hba) 308 { 309 if (!ufshcd_is_wb_allowed(hba)) 310 return; 311 312 ufshcd_wb_toggle(hba, true); 313 314 ufshcd_wb_toggle_buf_flush_during_h8(hba, true); 315 316 if (ufshcd_is_wb_buf_flush_allowed(hba)) 317 ufshcd_wb_toggle_buf_flush(hba, true); 318 } 319 320 static void ufshcd_scsi_unblock_requests(struct ufs_hba *hba) 321 { 322 if (atomic_dec_and_test(&hba->scsi_block_reqs_cnt)) 323 scsi_unblock_requests(hba->host); 324 } 325 326 static void ufshcd_scsi_block_requests(struct ufs_hba *hba) 327 { 328 if (atomic_inc_return(&hba->scsi_block_reqs_cnt) == 1) 329 scsi_block_requests(hba->host); 330 } 331 332 static void ufshcd_add_cmd_upiu_trace(struct ufs_hba *hba, unsigned int tag, 333 enum ufs_trace_str_t str_t) 334 { 335 struct utp_upiu_req *rq = hba->lrb[tag].ucd_req_ptr; 336 struct utp_upiu_header *header; 337 338 if (!trace_ufshcd_upiu_enabled()) 339 return; 340 341 if (str_t == UFS_CMD_SEND) 342 header = &rq->header; 343 else 344 header = &hba->lrb[tag].ucd_rsp_ptr->header; 345 346 trace_ufshcd_upiu(dev_name(hba->dev), str_t, header, &rq->sc.cdb, 347 UFS_TSF_CDB); 348 } 349 350 static void ufshcd_add_query_upiu_trace(struct ufs_hba *hba, 351 enum ufs_trace_str_t str_t, 352 struct utp_upiu_req *rq_rsp) 353 { 354 if (!trace_ufshcd_upiu_enabled()) 355 return; 356 357 trace_ufshcd_upiu(dev_name(hba->dev), str_t, &rq_rsp->header, 358 &rq_rsp->qr, UFS_TSF_OSF); 359 } 360 361 static void ufshcd_add_tm_upiu_trace(struct ufs_hba *hba, unsigned int tag, 362 enum ufs_trace_str_t str_t) 363 { 364 struct utp_task_req_desc *descp = &hba->utmrdl_base_addr[tag]; 365 366 if (!trace_ufshcd_upiu_enabled()) 367 return; 368 369 if (str_t == UFS_TM_SEND) 370 trace_ufshcd_upiu(dev_name(hba->dev), str_t, 371 &descp->upiu_req.req_header, 372 &descp->upiu_req.input_param1, 373 UFS_TSF_TM_INPUT); 374 else 375 trace_ufshcd_upiu(dev_name(hba->dev), str_t, 376 &descp->upiu_rsp.rsp_header, 377 &descp->upiu_rsp.output_param1, 378 UFS_TSF_TM_OUTPUT); 379 } 380 381 static void ufshcd_add_uic_command_trace(struct ufs_hba *hba, 382 const struct uic_command *ucmd, 383 enum ufs_trace_str_t str_t) 384 { 385 u32 cmd; 386 387 if (!trace_ufshcd_uic_command_enabled()) 388 return; 389 390 if (str_t == UFS_CMD_SEND) 391 cmd = ucmd->command; 392 else 393 cmd = ufshcd_readl(hba, REG_UIC_COMMAND); 394 395 trace_ufshcd_uic_command(dev_name(hba->dev), str_t, cmd, 396 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_1), 397 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2), 398 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3)); 399 } 400 401 static void ufshcd_add_command_trace(struct ufs_hba *hba, unsigned int tag, 402 enum ufs_trace_str_t str_t) 403 { 404 u64 lba = 0; 405 u8 opcode = 0, group_id = 0; 406 u32 doorbell = 0; 407 u32 intr; 408 int hwq_id = -1; 409 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 410 struct scsi_cmnd *cmd = lrbp->cmd; 411 struct request *rq = scsi_cmd_to_rq(cmd); 412 int transfer_len = -1; 413 414 if (!cmd) 415 return; 416 417 /* trace UPIU also */ 418 ufshcd_add_cmd_upiu_trace(hba, tag, str_t); 419 if (!trace_ufshcd_command_enabled()) 420 return; 421 422 opcode = cmd->cmnd[0]; 423 424 if (opcode == READ_10 || opcode == WRITE_10) { 425 /* 426 * Currently we only fully trace read(10) and write(10) commands 427 */ 428 transfer_len = 429 be32_to_cpu(lrbp->ucd_req_ptr->sc.exp_data_transfer_len); 430 lba = scsi_get_lba(cmd); 431 if (opcode == WRITE_10) 432 group_id = lrbp->cmd->cmnd[6]; 433 } else if (opcode == UNMAP) { 434 /* 435 * The number of Bytes to be unmapped beginning with the lba. 436 */ 437 transfer_len = blk_rq_bytes(rq); 438 lba = scsi_get_lba(cmd); 439 } 440 441 intr = ufshcd_readl(hba, REG_INTERRUPT_STATUS); 442 443 if (is_mcq_enabled(hba)) { 444 struct ufs_hw_queue *hwq = ufshcd_mcq_req_to_hwq(hba, rq); 445 446 hwq_id = hwq->id; 447 } else { 448 doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 449 } 450 trace_ufshcd_command(dev_name(hba->dev), str_t, tag, 451 doorbell, hwq_id, transfer_len, intr, lba, opcode, group_id); 452 } 453 454 static void ufshcd_print_clk_freqs(struct ufs_hba *hba) 455 { 456 struct ufs_clk_info *clki; 457 struct list_head *head = &hba->clk_list_head; 458 459 if (list_empty(head)) 460 return; 461 462 list_for_each_entry(clki, head, list) { 463 if (!IS_ERR_OR_NULL(clki->clk) && clki->min_freq && 464 clki->max_freq) 465 dev_err(hba->dev, "clk: %s, rate: %u\n", 466 clki->name, clki->curr_freq); 467 } 468 } 469 470 static void ufshcd_print_evt(struct ufs_hba *hba, u32 id, 471 const char *err_name) 472 { 473 int i; 474 bool found = false; 475 const struct ufs_event_hist *e; 476 477 if (id >= UFS_EVT_CNT) 478 return; 479 480 e = &hba->ufs_stats.event[id]; 481 482 for (i = 0; i < UFS_EVENT_HIST_LENGTH; i++) { 483 int p = (i + e->pos) % UFS_EVENT_HIST_LENGTH; 484 485 if (e->tstamp[p] == 0) 486 continue; 487 dev_err(hba->dev, "%s[%d] = 0x%x at %lld us\n", err_name, p, 488 e->val[p], div_u64(e->tstamp[p], 1000)); 489 found = true; 490 } 491 492 if (!found) 493 dev_err(hba->dev, "No record of %s\n", err_name); 494 else 495 dev_err(hba->dev, "%s: total cnt=%llu\n", err_name, e->cnt); 496 } 497 498 static void ufshcd_print_evt_hist(struct ufs_hba *hba) 499 { 500 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: "); 501 502 ufshcd_print_evt(hba, UFS_EVT_PA_ERR, "pa_err"); 503 ufshcd_print_evt(hba, UFS_EVT_DL_ERR, "dl_err"); 504 ufshcd_print_evt(hba, UFS_EVT_NL_ERR, "nl_err"); 505 ufshcd_print_evt(hba, UFS_EVT_TL_ERR, "tl_err"); 506 ufshcd_print_evt(hba, UFS_EVT_DME_ERR, "dme_err"); 507 ufshcd_print_evt(hba, UFS_EVT_AUTO_HIBERN8_ERR, 508 "auto_hibern8_err"); 509 ufshcd_print_evt(hba, UFS_EVT_FATAL_ERR, "fatal_err"); 510 ufshcd_print_evt(hba, UFS_EVT_LINK_STARTUP_FAIL, 511 "link_startup_fail"); 512 ufshcd_print_evt(hba, UFS_EVT_RESUME_ERR, "resume_fail"); 513 ufshcd_print_evt(hba, UFS_EVT_SUSPEND_ERR, 514 "suspend_fail"); 515 ufshcd_print_evt(hba, UFS_EVT_WL_RES_ERR, "wlun resume_fail"); 516 ufshcd_print_evt(hba, UFS_EVT_WL_SUSP_ERR, 517 "wlun suspend_fail"); 518 ufshcd_print_evt(hba, UFS_EVT_DEV_RESET, "dev_reset"); 519 ufshcd_print_evt(hba, UFS_EVT_HOST_RESET, "host_reset"); 520 ufshcd_print_evt(hba, UFS_EVT_ABORT, "task_abort"); 521 522 ufshcd_vops_dbg_register_dump(hba); 523 } 524 525 static 526 void ufshcd_print_tr(struct ufs_hba *hba, int tag, bool pr_prdt) 527 { 528 const struct ufshcd_lrb *lrbp; 529 int prdt_length; 530 531 lrbp = &hba->lrb[tag]; 532 533 dev_err(hba->dev, "UPIU[%d] - issue time %lld us\n", 534 tag, div_u64(lrbp->issue_time_stamp_local_clock, 1000)); 535 dev_err(hba->dev, "UPIU[%d] - complete time %lld us\n", 536 tag, div_u64(lrbp->compl_time_stamp_local_clock, 1000)); 537 dev_err(hba->dev, 538 "UPIU[%d] - Transfer Request Descriptor phys@0x%llx\n", 539 tag, (u64)lrbp->utrd_dma_addr); 540 541 ufshcd_hex_dump("UPIU TRD: ", lrbp->utr_descriptor_ptr, 542 sizeof(struct utp_transfer_req_desc)); 543 dev_err(hba->dev, "UPIU[%d] - Request UPIU phys@0x%llx\n", tag, 544 (u64)lrbp->ucd_req_dma_addr); 545 ufshcd_hex_dump("UPIU REQ: ", lrbp->ucd_req_ptr, 546 sizeof(struct utp_upiu_req)); 547 dev_err(hba->dev, "UPIU[%d] - Response UPIU phys@0x%llx\n", tag, 548 (u64)lrbp->ucd_rsp_dma_addr); 549 ufshcd_hex_dump("UPIU RSP: ", lrbp->ucd_rsp_ptr, 550 sizeof(struct utp_upiu_rsp)); 551 552 prdt_length = le16_to_cpu( 553 lrbp->utr_descriptor_ptr->prd_table_length); 554 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) 555 prdt_length /= ufshcd_sg_entry_size(hba); 556 557 dev_err(hba->dev, 558 "UPIU[%d] - PRDT - %d entries phys@0x%llx\n", 559 tag, prdt_length, 560 (u64)lrbp->ucd_prdt_dma_addr); 561 562 if (pr_prdt) 563 ufshcd_hex_dump("UPIU PRDT: ", lrbp->ucd_prdt_ptr, 564 ufshcd_sg_entry_size(hba) * prdt_length); 565 } 566 567 static bool ufshcd_print_tr_iter(struct request *req, void *priv) 568 { 569 struct scsi_device *sdev = req->q->queuedata; 570 struct Scsi_Host *shost = sdev->host; 571 struct ufs_hba *hba = shost_priv(shost); 572 573 ufshcd_print_tr(hba, req->tag, *(bool *)priv); 574 575 return true; 576 } 577 578 /** 579 * ufshcd_print_trs_all - print trs for all started requests. 580 * @hba: per-adapter instance. 581 * @pr_prdt: need to print prdt or not. 582 */ 583 static void ufshcd_print_trs_all(struct ufs_hba *hba, bool pr_prdt) 584 { 585 blk_mq_tagset_busy_iter(&hba->host->tag_set, ufshcd_print_tr_iter, &pr_prdt); 586 } 587 588 static void ufshcd_print_tmrs(struct ufs_hba *hba, unsigned long bitmap) 589 { 590 int tag; 591 592 for_each_set_bit(tag, &bitmap, hba->nutmrs) { 593 struct utp_task_req_desc *tmrdp = &hba->utmrdl_base_addr[tag]; 594 595 dev_err(hba->dev, "TM[%d] - Task Management Header\n", tag); 596 ufshcd_hex_dump("", tmrdp, sizeof(*tmrdp)); 597 } 598 } 599 600 static void ufshcd_print_host_state(struct ufs_hba *hba) 601 { 602 const struct scsi_device *sdev_ufs = hba->ufs_device_wlun; 603 604 dev_err(hba->dev, "UFS Host state=%d\n", hba->ufshcd_state); 605 dev_err(hba->dev, "outstanding reqs=0x%lx tasks=0x%lx\n", 606 hba->outstanding_reqs, hba->outstanding_tasks); 607 dev_err(hba->dev, "saved_err=0x%x, saved_uic_err=0x%x\n", 608 hba->saved_err, hba->saved_uic_err); 609 dev_err(hba->dev, "Device power mode=%d, UIC link state=%d\n", 610 hba->curr_dev_pwr_mode, hba->uic_link_state); 611 dev_err(hba->dev, "PM in progress=%d, sys. suspended=%d\n", 612 hba->pm_op_in_progress, hba->is_sys_suspended); 613 dev_err(hba->dev, "Auto BKOPS=%d, Host self-block=%d\n", 614 hba->auto_bkops_enabled, hba->host->host_self_blocked); 615 dev_err(hba->dev, "Clk gate=%d\n", hba->clk_gating.state); 616 dev_err(hba->dev, 617 "last_hibern8_exit_tstamp at %lld us, hibern8_exit_cnt=%d\n", 618 div_u64(hba->ufs_stats.last_hibern8_exit_tstamp, 1000), 619 hba->ufs_stats.hibern8_exit_cnt); 620 dev_err(hba->dev, "last intr at %lld us, last intr status=0x%x\n", 621 div_u64(hba->ufs_stats.last_intr_ts, 1000), 622 hba->ufs_stats.last_intr_status); 623 dev_err(hba->dev, "error handling flags=0x%x, req. abort count=%d\n", 624 hba->eh_flags, hba->req_abort_count); 625 dev_err(hba->dev, "hba->ufs_version=0x%x, Host capabilities=0x%x, caps=0x%x\n", 626 hba->ufs_version, hba->capabilities, hba->caps); 627 dev_err(hba->dev, "quirks=0x%x, dev. quirks=0x%x\n", hba->quirks, 628 hba->dev_quirks); 629 if (sdev_ufs) 630 dev_err(hba->dev, "UFS dev info: %.8s %.16s rev %.4s\n", 631 sdev_ufs->vendor, sdev_ufs->model, sdev_ufs->rev); 632 633 ufshcd_print_clk_freqs(hba); 634 } 635 636 /** 637 * ufshcd_print_pwr_info - print power params as saved in hba 638 * power info 639 * @hba: per-adapter instance 640 */ 641 static void ufshcd_print_pwr_info(struct ufs_hba *hba) 642 { 643 static const char * const names[] = { 644 "INVALID MODE", 645 "FAST MODE", 646 "SLOW_MODE", 647 "INVALID MODE", 648 "FASTAUTO_MODE", 649 "SLOWAUTO_MODE", 650 "INVALID MODE", 651 }; 652 653 /* 654 * Using dev_dbg to avoid messages during runtime PM to avoid 655 * never-ending cycles of messages written back to storage by user space 656 * causing runtime resume, causing more messages and so on. 657 */ 658 dev_dbg(hba->dev, "%s:[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n", 659 __func__, 660 hba->pwr_info.gear_rx, hba->pwr_info.gear_tx, 661 hba->pwr_info.lane_rx, hba->pwr_info.lane_tx, 662 names[hba->pwr_info.pwr_rx], 663 names[hba->pwr_info.pwr_tx], 664 hba->pwr_info.hs_rate); 665 } 666 667 static void ufshcd_device_reset(struct ufs_hba *hba) 668 { 669 int err; 670 671 err = ufshcd_vops_device_reset(hba); 672 673 if (!err) { 674 ufshcd_set_ufs_dev_active(hba); 675 if (ufshcd_is_wb_allowed(hba)) { 676 hba->dev_info.wb_enabled = false; 677 hba->dev_info.wb_buf_flush_enabled = false; 678 } 679 } 680 if (err != -EOPNOTSUPP) 681 ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, err); 682 } 683 684 void ufshcd_delay_us(unsigned long us, unsigned long tolerance) 685 { 686 if (!us) 687 return; 688 689 if (us < 10) 690 udelay(us); 691 else 692 usleep_range(us, us + tolerance); 693 } 694 EXPORT_SYMBOL_GPL(ufshcd_delay_us); 695 696 /** 697 * ufshcd_wait_for_register - wait for register value to change 698 * @hba: per-adapter interface 699 * @reg: mmio register offset 700 * @mask: mask to apply to the read register value 701 * @val: value to wait for 702 * @interval_us: polling interval in microseconds 703 * @timeout_ms: timeout in milliseconds 704 * 705 * Return: -ETIMEDOUT on error, zero on success. 706 */ 707 static int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask, 708 u32 val, unsigned long interval_us, 709 unsigned long timeout_ms) 710 { 711 int err = 0; 712 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms); 713 714 /* ignore bits that we don't intend to wait on */ 715 val = val & mask; 716 717 while ((ufshcd_readl(hba, reg) & mask) != val) { 718 usleep_range(interval_us, interval_us + 50); 719 if (time_after(jiffies, timeout)) { 720 if ((ufshcd_readl(hba, reg) & mask) != val) 721 err = -ETIMEDOUT; 722 break; 723 } 724 } 725 726 return err; 727 } 728 729 /** 730 * ufshcd_get_intr_mask - Get the interrupt bit mask 731 * @hba: Pointer to adapter instance 732 * 733 * Return: interrupt bit mask per version 734 */ 735 static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba) 736 { 737 if (hba->ufs_version == ufshci_version(1, 0)) 738 return INTERRUPT_MASK_ALL_VER_10; 739 if (hba->ufs_version <= ufshci_version(2, 0)) 740 return INTERRUPT_MASK_ALL_VER_11; 741 742 return INTERRUPT_MASK_ALL_VER_21; 743 } 744 745 /** 746 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA 747 * @hba: Pointer to adapter instance 748 * 749 * Return: UFSHCI version supported by the controller 750 */ 751 static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba) 752 { 753 u32 ufshci_ver; 754 755 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION) 756 ufshci_ver = ufshcd_vops_get_ufs_hci_version(hba); 757 else 758 ufshci_ver = ufshcd_readl(hba, REG_UFS_VERSION); 759 760 /* 761 * UFSHCI v1.x uses a different version scheme, in order 762 * to allow the use of comparisons with the ufshci_version 763 * function, we convert it to the same scheme as ufs 2.0+. 764 */ 765 if (ufshci_ver & 0x00010000) 766 return ufshci_version(1, ufshci_ver & 0x00000100); 767 768 return ufshci_ver; 769 } 770 771 /** 772 * ufshcd_is_device_present - Check if any device connected to 773 * the host controller 774 * @hba: pointer to adapter instance 775 * 776 * Return: true if device present, false if no device detected 777 */ 778 static inline bool ufshcd_is_device_present(struct ufs_hba *hba) 779 { 780 return ufshcd_readl(hba, REG_CONTROLLER_STATUS) & DEVICE_PRESENT; 781 } 782 783 /** 784 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status 785 * @lrbp: pointer to local command reference block 786 * @cqe: pointer to the completion queue entry 787 * 788 * This function is used to get the OCS field from UTRD 789 * 790 * Return: the OCS field in the UTRD. 791 */ 792 static enum utp_ocs ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp, 793 struct cq_entry *cqe) 794 { 795 if (cqe) 796 return le32_to_cpu(cqe->status) & MASK_OCS; 797 798 return lrbp->utr_descriptor_ptr->header.ocs & MASK_OCS; 799 } 800 801 /** 802 * ufshcd_utrl_clear() - Clear requests from the controller request list. 803 * @hba: per adapter instance 804 * @mask: mask with one bit set for each request to be cleared 805 */ 806 static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 mask) 807 { 808 if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR) 809 mask = ~mask; 810 /* 811 * From the UFSHCI specification: "UTP Transfer Request List CLear 812 * Register (UTRLCLR): This field is bit significant. Each bit 813 * corresponds to a slot in the UTP Transfer Request List, where bit 0 814 * corresponds to request slot 0. A bit in this field is set to ‘0’ 815 * by host software to indicate to the host controller that a transfer 816 * request slot is cleared. The host controller 817 * shall free up any resources associated to the request slot 818 * immediately, and shall set the associated bit in UTRLDBR to ‘0’. The 819 * host software indicates no change to request slots by setting the 820 * associated bits in this field to ‘1’. Bits in this field shall only 821 * be set ‘1’ or ‘0’ by host software when UTRLRSR is set to ‘1’." 822 */ 823 ufshcd_writel(hba, ~mask, REG_UTP_TRANSFER_REQ_LIST_CLEAR); 824 } 825 826 /** 827 * ufshcd_utmrl_clear - Clear a bit in UTMRLCLR register 828 * @hba: per adapter instance 829 * @pos: position of the bit to be cleared 830 */ 831 static inline void ufshcd_utmrl_clear(struct ufs_hba *hba, u32 pos) 832 { 833 if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR) 834 ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR); 835 else 836 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR); 837 } 838 839 /** 840 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY 841 * @reg: Register value of host controller status 842 * 843 * Return: 0 on success; a positive value if failed. 844 */ 845 static inline int ufshcd_get_lists_status(u32 reg) 846 { 847 return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY); 848 } 849 850 /** 851 * ufshcd_get_uic_cmd_result - Get the UIC command result 852 * @hba: Pointer to adapter instance 853 * 854 * This function gets the result of UIC command completion 855 * 856 * Return: 0 on success; non-zero value on error. 857 */ 858 static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba) 859 { 860 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) & 861 MASK_UIC_COMMAND_RESULT; 862 } 863 864 /** 865 * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command 866 * @hba: Pointer to adapter instance 867 * 868 * This function gets UIC command argument3 869 * 870 * Return: 0 on success; non-zero value on error. 871 */ 872 static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba) 873 { 874 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3); 875 } 876 877 /** 878 * ufshcd_get_req_rsp - returns the TR response transaction type 879 * @ucd_rsp_ptr: pointer to response UPIU 880 * 881 * Return: UPIU type. 882 */ 883 static inline enum upiu_response_transaction 884 ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr) 885 { 886 return ucd_rsp_ptr->header.transaction_code; 887 } 888 889 /** 890 * ufshcd_is_exception_event - Check if the device raised an exception event 891 * @ucd_rsp_ptr: pointer to response UPIU 892 * 893 * The function checks if the device raised an exception event indicated in 894 * the Device Information field of response UPIU. 895 * 896 * Return: true if exception is raised, false otherwise. 897 */ 898 static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr) 899 { 900 return ucd_rsp_ptr->header.device_information & 1; 901 } 902 903 /** 904 * ufshcd_reset_intr_aggr - Reset interrupt aggregation values. 905 * @hba: per adapter instance 906 */ 907 static inline void 908 ufshcd_reset_intr_aggr(struct ufs_hba *hba) 909 { 910 ufshcd_writel(hba, INT_AGGR_ENABLE | 911 INT_AGGR_COUNTER_AND_TIMER_RESET, 912 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL); 913 } 914 915 /** 916 * ufshcd_config_intr_aggr - Configure interrupt aggregation values. 917 * @hba: per adapter instance 918 * @cnt: Interrupt aggregation counter threshold 919 * @tmout: Interrupt aggregation timeout value 920 */ 921 static inline void 922 ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout) 923 { 924 ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE | 925 INT_AGGR_COUNTER_THLD_VAL(cnt) | 926 INT_AGGR_TIMEOUT_VAL(tmout), 927 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL); 928 } 929 930 /** 931 * ufshcd_disable_intr_aggr - Disables interrupt aggregation. 932 * @hba: per adapter instance 933 */ 934 static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba) 935 { 936 ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL); 937 } 938 939 /** 940 * ufshcd_enable_run_stop_reg - Enable run-stop registers, 941 * When run-stop registers are set to 1, it indicates the 942 * host controller that it can process the requests 943 * @hba: per adapter instance 944 */ 945 static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba) 946 { 947 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT, 948 REG_UTP_TASK_REQ_LIST_RUN_STOP); 949 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT, 950 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP); 951 } 952 953 /** 954 * ufshcd_hba_start - Start controller initialization sequence 955 * @hba: per adapter instance 956 */ 957 static inline void ufshcd_hba_start(struct ufs_hba *hba) 958 { 959 u32 val = CONTROLLER_ENABLE; 960 961 if (ufshcd_crypto_enable(hba)) 962 val |= CRYPTO_GENERAL_ENABLE; 963 964 ufshcd_writel(hba, val, REG_CONTROLLER_ENABLE); 965 } 966 967 /** 968 * ufshcd_is_hba_active - Get controller state 969 * @hba: per adapter instance 970 * 971 * Return: true if and only if the controller is active. 972 */ 973 bool ufshcd_is_hba_active(struct ufs_hba *hba) 974 { 975 return ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE; 976 } 977 EXPORT_SYMBOL_GPL(ufshcd_is_hba_active); 978 979 u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba) 980 { 981 /* HCI version 1.0 and 1.1 supports UniPro 1.41 */ 982 if (hba->ufs_version <= ufshci_version(1, 1)) 983 return UFS_UNIPRO_VER_1_41; 984 else 985 return UFS_UNIPRO_VER_1_6; 986 } 987 EXPORT_SYMBOL(ufshcd_get_local_unipro_ver); 988 989 static bool ufshcd_is_unipro_pa_params_tuning_req(struct ufs_hba *hba) 990 { 991 /* 992 * If both host and device support UniPro ver1.6 or later, PA layer 993 * parameters tuning happens during link startup itself. 994 * 995 * We can manually tune PA layer parameters if either host or device 996 * doesn't support UniPro ver 1.6 or later. But to keep manual tuning 997 * logic simple, we will only do manual tuning if local unipro version 998 * doesn't support ver1.6 or later. 999 */ 1000 return ufshcd_get_local_unipro_ver(hba) < UFS_UNIPRO_VER_1_6; 1001 } 1002 1003 /** 1004 * ufshcd_set_clk_freq - set UFS controller clock frequencies 1005 * @hba: per adapter instance 1006 * @scale_up: If True, set max possible frequency othewise set low frequency 1007 * 1008 * Return: 0 if successful; < 0 upon failure. 1009 */ 1010 static int ufshcd_set_clk_freq(struct ufs_hba *hba, bool scale_up) 1011 { 1012 int ret = 0; 1013 struct ufs_clk_info *clki; 1014 struct list_head *head = &hba->clk_list_head; 1015 1016 if (list_empty(head)) 1017 goto out; 1018 1019 list_for_each_entry(clki, head, list) { 1020 if (!IS_ERR_OR_NULL(clki->clk)) { 1021 if (scale_up && clki->max_freq) { 1022 if (clki->curr_freq == clki->max_freq) 1023 continue; 1024 1025 ret = clk_set_rate(clki->clk, clki->max_freq); 1026 if (ret) { 1027 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n", 1028 __func__, clki->name, 1029 clki->max_freq, ret); 1030 break; 1031 } 1032 trace_ufshcd_clk_scaling(dev_name(hba->dev), 1033 "scaled up", clki->name, 1034 clki->curr_freq, 1035 clki->max_freq); 1036 1037 clki->curr_freq = clki->max_freq; 1038 1039 } else if (!scale_up && clki->min_freq) { 1040 if (clki->curr_freq == clki->min_freq) 1041 continue; 1042 1043 ret = clk_set_rate(clki->clk, clki->min_freq); 1044 if (ret) { 1045 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n", 1046 __func__, clki->name, 1047 clki->min_freq, ret); 1048 break; 1049 } 1050 trace_ufshcd_clk_scaling(dev_name(hba->dev), 1051 "scaled down", clki->name, 1052 clki->curr_freq, 1053 clki->min_freq); 1054 clki->curr_freq = clki->min_freq; 1055 } 1056 } 1057 dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__, 1058 clki->name, clk_get_rate(clki->clk)); 1059 } 1060 1061 out: 1062 return ret; 1063 } 1064 1065 /** 1066 * ufshcd_scale_clks - scale up or scale down UFS controller clocks 1067 * @hba: per adapter instance 1068 * @scale_up: True if scaling up and false if scaling down 1069 * 1070 * Return: 0 if successful; < 0 upon failure. 1071 */ 1072 static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up) 1073 { 1074 int ret = 0; 1075 ktime_t start = ktime_get(); 1076 1077 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE); 1078 if (ret) 1079 goto out; 1080 1081 ret = ufshcd_set_clk_freq(hba, scale_up); 1082 if (ret) 1083 goto out; 1084 1085 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE); 1086 if (ret) 1087 ufshcd_set_clk_freq(hba, !scale_up); 1088 1089 out: 1090 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev), 1091 (scale_up ? "up" : "down"), 1092 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 1093 return ret; 1094 } 1095 1096 /** 1097 * ufshcd_is_devfreq_scaling_required - check if scaling is required or not 1098 * @hba: per adapter instance 1099 * @scale_up: True if scaling up and false if scaling down 1100 * 1101 * Return: true if scaling is required, false otherwise. 1102 */ 1103 static bool ufshcd_is_devfreq_scaling_required(struct ufs_hba *hba, 1104 bool scale_up) 1105 { 1106 struct ufs_clk_info *clki; 1107 struct list_head *head = &hba->clk_list_head; 1108 1109 if (list_empty(head)) 1110 return false; 1111 1112 list_for_each_entry(clki, head, list) { 1113 if (!IS_ERR_OR_NULL(clki->clk)) { 1114 if (scale_up && clki->max_freq) { 1115 if (clki->curr_freq == clki->max_freq) 1116 continue; 1117 return true; 1118 } else if (!scale_up && clki->min_freq) { 1119 if (clki->curr_freq == clki->min_freq) 1120 continue; 1121 return true; 1122 } 1123 } 1124 } 1125 1126 return false; 1127 } 1128 1129 /* 1130 * Determine the number of pending commands by counting the bits in the SCSI 1131 * device budget maps. This approach has been selected because a bit is set in 1132 * the budget map before scsi_host_queue_ready() checks the host_self_blocked 1133 * flag. The host_self_blocked flag can be modified by calling 1134 * scsi_block_requests() or scsi_unblock_requests(). 1135 */ 1136 static u32 ufshcd_pending_cmds(struct ufs_hba *hba) 1137 { 1138 const struct scsi_device *sdev; 1139 u32 pending = 0; 1140 1141 lockdep_assert_held(hba->host->host_lock); 1142 __shost_for_each_device(sdev, hba->host) 1143 pending += sbitmap_weight(&sdev->budget_map); 1144 1145 return pending; 1146 } 1147 1148 /* 1149 * Wait until all pending SCSI commands and TMFs have finished or the timeout 1150 * has expired. 1151 * 1152 * Return: 0 upon success; -EBUSY upon timeout. 1153 */ 1154 static int ufshcd_wait_for_doorbell_clr(struct ufs_hba *hba, 1155 u64 wait_timeout_us) 1156 { 1157 unsigned long flags; 1158 int ret = 0; 1159 u32 tm_doorbell; 1160 u32 tr_pending; 1161 bool timeout = false, do_last_check = false; 1162 ktime_t start; 1163 1164 ufshcd_hold(hba); 1165 spin_lock_irqsave(hba->host->host_lock, flags); 1166 /* 1167 * Wait for all the outstanding tasks/transfer requests. 1168 * Verify by checking the doorbell registers are clear. 1169 */ 1170 start = ktime_get(); 1171 do { 1172 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) { 1173 ret = -EBUSY; 1174 goto out; 1175 } 1176 1177 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL); 1178 tr_pending = ufshcd_pending_cmds(hba); 1179 if (!tm_doorbell && !tr_pending) { 1180 timeout = false; 1181 break; 1182 } else if (do_last_check) { 1183 break; 1184 } 1185 1186 spin_unlock_irqrestore(hba->host->host_lock, flags); 1187 io_schedule_timeout(msecs_to_jiffies(20)); 1188 if (ktime_to_us(ktime_sub(ktime_get(), start)) > 1189 wait_timeout_us) { 1190 timeout = true; 1191 /* 1192 * We might have scheduled out for long time so make 1193 * sure to check if doorbells are cleared by this time 1194 * or not. 1195 */ 1196 do_last_check = true; 1197 } 1198 spin_lock_irqsave(hba->host->host_lock, flags); 1199 } while (tm_doorbell || tr_pending); 1200 1201 if (timeout) { 1202 dev_err(hba->dev, 1203 "%s: timedout waiting for doorbell to clear (tm=0x%x, tr=0x%x)\n", 1204 __func__, tm_doorbell, tr_pending); 1205 ret = -EBUSY; 1206 } 1207 out: 1208 spin_unlock_irqrestore(hba->host->host_lock, flags); 1209 ufshcd_release(hba); 1210 return ret; 1211 } 1212 1213 /** 1214 * ufshcd_scale_gear - scale up/down UFS gear 1215 * @hba: per adapter instance 1216 * @scale_up: True for scaling up gear and false for scaling down 1217 * 1218 * Return: 0 for success; -EBUSY if scaling can't happen at this time; 1219 * non-zero for any other errors. 1220 */ 1221 static int ufshcd_scale_gear(struct ufs_hba *hba, bool scale_up) 1222 { 1223 int ret = 0; 1224 struct ufs_pa_layer_attr new_pwr_info; 1225 1226 if (scale_up) { 1227 memcpy(&new_pwr_info, &hba->clk_scaling.saved_pwr_info, 1228 sizeof(struct ufs_pa_layer_attr)); 1229 } else { 1230 memcpy(&new_pwr_info, &hba->pwr_info, 1231 sizeof(struct ufs_pa_layer_attr)); 1232 1233 if (hba->pwr_info.gear_tx > hba->clk_scaling.min_gear || 1234 hba->pwr_info.gear_rx > hba->clk_scaling.min_gear) { 1235 /* save the current power mode */ 1236 memcpy(&hba->clk_scaling.saved_pwr_info, 1237 &hba->pwr_info, 1238 sizeof(struct ufs_pa_layer_attr)); 1239 1240 /* scale down gear */ 1241 new_pwr_info.gear_tx = hba->clk_scaling.min_gear; 1242 new_pwr_info.gear_rx = hba->clk_scaling.min_gear; 1243 } 1244 } 1245 1246 /* check if the power mode needs to be changed or not? */ 1247 ret = ufshcd_config_pwr_mode(hba, &new_pwr_info); 1248 if (ret) 1249 dev_err(hba->dev, "%s: failed err %d, old gear: (tx %d rx %d), new gear: (tx %d rx %d)", 1250 __func__, ret, 1251 hba->pwr_info.gear_tx, hba->pwr_info.gear_rx, 1252 new_pwr_info.gear_tx, new_pwr_info.gear_rx); 1253 1254 return ret; 1255 } 1256 1257 /* 1258 * Wait until all pending SCSI commands and TMFs have finished or the timeout 1259 * has expired. 1260 * 1261 * Return: 0 upon success; -EBUSY upon timeout. 1262 */ 1263 static int ufshcd_clock_scaling_prepare(struct ufs_hba *hba, u64 timeout_us) 1264 { 1265 int ret = 0; 1266 /* 1267 * make sure that there are no outstanding requests when 1268 * clock scaling is in progress 1269 */ 1270 blk_mq_quiesce_tagset(&hba->host->tag_set); 1271 mutex_lock(&hba->wb_mutex); 1272 down_write(&hba->clk_scaling_lock); 1273 1274 if (!hba->clk_scaling.is_allowed || 1275 ufshcd_wait_for_doorbell_clr(hba, timeout_us)) { 1276 ret = -EBUSY; 1277 up_write(&hba->clk_scaling_lock); 1278 mutex_unlock(&hba->wb_mutex); 1279 blk_mq_unquiesce_tagset(&hba->host->tag_set); 1280 goto out; 1281 } 1282 1283 /* let's not get into low power until clock scaling is completed */ 1284 ufshcd_hold(hba); 1285 1286 out: 1287 return ret; 1288 } 1289 1290 static void ufshcd_clock_scaling_unprepare(struct ufs_hba *hba, int err, bool scale_up) 1291 { 1292 up_write(&hba->clk_scaling_lock); 1293 1294 /* Enable Write Booster if we have scaled up else disable it */ 1295 if (ufshcd_enable_wb_if_scaling_up(hba) && !err) 1296 ufshcd_wb_toggle(hba, scale_up); 1297 1298 mutex_unlock(&hba->wb_mutex); 1299 1300 blk_mq_unquiesce_tagset(&hba->host->tag_set); 1301 ufshcd_release(hba); 1302 } 1303 1304 /** 1305 * ufshcd_devfreq_scale - scale up/down UFS clocks and gear 1306 * @hba: per adapter instance 1307 * @scale_up: True for scaling up and false for scalin down 1308 * 1309 * Return: 0 for success; -EBUSY if scaling can't happen at this time; non-zero 1310 * for any other errors. 1311 */ 1312 static int ufshcd_devfreq_scale(struct ufs_hba *hba, bool scale_up) 1313 { 1314 int ret = 0; 1315 1316 ret = ufshcd_clock_scaling_prepare(hba, 1 * USEC_PER_SEC); 1317 if (ret) 1318 return ret; 1319 1320 /* scale down the gear before scaling down clocks */ 1321 if (!scale_up) { 1322 ret = ufshcd_scale_gear(hba, false); 1323 if (ret) 1324 goto out_unprepare; 1325 } 1326 1327 ret = ufshcd_scale_clks(hba, scale_up); 1328 if (ret) { 1329 if (!scale_up) 1330 ufshcd_scale_gear(hba, true); 1331 goto out_unprepare; 1332 } 1333 1334 /* scale up the gear after scaling up clocks */ 1335 if (scale_up) { 1336 ret = ufshcd_scale_gear(hba, true); 1337 if (ret) { 1338 ufshcd_scale_clks(hba, false); 1339 goto out_unprepare; 1340 } 1341 } 1342 1343 out_unprepare: 1344 ufshcd_clock_scaling_unprepare(hba, ret, scale_up); 1345 return ret; 1346 } 1347 1348 static void ufshcd_clk_scaling_suspend_work(struct work_struct *work) 1349 { 1350 struct ufs_hba *hba = container_of(work, struct ufs_hba, 1351 clk_scaling.suspend_work); 1352 unsigned long irq_flags; 1353 1354 spin_lock_irqsave(hba->host->host_lock, irq_flags); 1355 if (hba->clk_scaling.active_reqs || hba->clk_scaling.is_suspended) { 1356 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1357 return; 1358 } 1359 hba->clk_scaling.is_suspended = true; 1360 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1361 1362 __ufshcd_suspend_clkscaling(hba); 1363 } 1364 1365 static void ufshcd_clk_scaling_resume_work(struct work_struct *work) 1366 { 1367 struct ufs_hba *hba = container_of(work, struct ufs_hba, 1368 clk_scaling.resume_work); 1369 unsigned long irq_flags; 1370 1371 spin_lock_irqsave(hba->host->host_lock, irq_flags); 1372 if (!hba->clk_scaling.is_suspended) { 1373 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1374 return; 1375 } 1376 hba->clk_scaling.is_suspended = false; 1377 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1378 1379 devfreq_resume_device(hba->devfreq); 1380 } 1381 1382 static int ufshcd_devfreq_target(struct device *dev, 1383 unsigned long *freq, u32 flags) 1384 { 1385 int ret = 0; 1386 struct ufs_hba *hba = dev_get_drvdata(dev); 1387 ktime_t start; 1388 bool scale_up, sched_clk_scaling_suspend_work = false; 1389 struct list_head *clk_list = &hba->clk_list_head; 1390 struct ufs_clk_info *clki; 1391 unsigned long irq_flags; 1392 1393 if (!ufshcd_is_clkscaling_supported(hba)) 1394 return -EINVAL; 1395 1396 clki = list_first_entry(&hba->clk_list_head, struct ufs_clk_info, list); 1397 /* Override with the closest supported frequency */ 1398 *freq = (unsigned long) clk_round_rate(clki->clk, *freq); 1399 spin_lock_irqsave(hba->host->host_lock, irq_flags); 1400 if (ufshcd_eh_in_progress(hba)) { 1401 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1402 return 0; 1403 } 1404 1405 if (!hba->clk_scaling.active_reqs) 1406 sched_clk_scaling_suspend_work = true; 1407 1408 if (list_empty(clk_list)) { 1409 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1410 goto out; 1411 } 1412 1413 /* Decide based on the rounded-off frequency and update */ 1414 scale_up = *freq == clki->max_freq; 1415 if (!scale_up) 1416 *freq = clki->min_freq; 1417 /* Update the frequency */ 1418 if (!ufshcd_is_devfreq_scaling_required(hba, scale_up)) { 1419 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1420 ret = 0; 1421 goto out; /* no state change required */ 1422 } 1423 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1424 1425 start = ktime_get(); 1426 ret = ufshcd_devfreq_scale(hba, scale_up); 1427 1428 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev), 1429 (scale_up ? "up" : "down"), 1430 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 1431 1432 out: 1433 if (sched_clk_scaling_suspend_work) 1434 queue_work(hba->clk_scaling.workq, 1435 &hba->clk_scaling.suspend_work); 1436 1437 return ret; 1438 } 1439 1440 static int ufshcd_devfreq_get_dev_status(struct device *dev, 1441 struct devfreq_dev_status *stat) 1442 { 1443 struct ufs_hba *hba = dev_get_drvdata(dev); 1444 struct ufs_clk_scaling *scaling = &hba->clk_scaling; 1445 unsigned long flags; 1446 struct list_head *clk_list = &hba->clk_list_head; 1447 struct ufs_clk_info *clki; 1448 ktime_t curr_t; 1449 1450 if (!ufshcd_is_clkscaling_supported(hba)) 1451 return -EINVAL; 1452 1453 memset(stat, 0, sizeof(*stat)); 1454 1455 spin_lock_irqsave(hba->host->host_lock, flags); 1456 curr_t = ktime_get(); 1457 if (!scaling->window_start_t) 1458 goto start_window; 1459 1460 clki = list_first_entry(clk_list, struct ufs_clk_info, list); 1461 /* 1462 * If current frequency is 0, then the ondemand governor considers 1463 * there's no initial frequency set. And it always requests to set 1464 * to max. frequency. 1465 */ 1466 stat->current_frequency = clki->curr_freq; 1467 if (scaling->is_busy_started) 1468 scaling->tot_busy_t += ktime_us_delta(curr_t, 1469 scaling->busy_start_t); 1470 1471 stat->total_time = ktime_us_delta(curr_t, scaling->window_start_t); 1472 stat->busy_time = scaling->tot_busy_t; 1473 start_window: 1474 scaling->window_start_t = curr_t; 1475 scaling->tot_busy_t = 0; 1476 1477 if (scaling->active_reqs) { 1478 scaling->busy_start_t = curr_t; 1479 scaling->is_busy_started = true; 1480 } else { 1481 scaling->busy_start_t = 0; 1482 scaling->is_busy_started = false; 1483 } 1484 spin_unlock_irqrestore(hba->host->host_lock, flags); 1485 return 0; 1486 } 1487 1488 static int ufshcd_devfreq_init(struct ufs_hba *hba) 1489 { 1490 struct list_head *clk_list = &hba->clk_list_head; 1491 struct ufs_clk_info *clki; 1492 struct devfreq *devfreq; 1493 int ret; 1494 1495 /* Skip devfreq if we don't have any clocks in the list */ 1496 if (list_empty(clk_list)) 1497 return 0; 1498 1499 clki = list_first_entry(clk_list, struct ufs_clk_info, list); 1500 dev_pm_opp_add(hba->dev, clki->min_freq, 0); 1501 dev_pm_opp_add(hba->dev, clki->max_freq, 0); 1502 1503 ufshcd_vops_config_scaling_param(hba, &hba->vps->devfreq_profile, 1504 &hba->vps->ondemand_data); 1505 devfreq = devfreq_add_device(hba->dev, 1506 &hba->vps->devfreq_profile, 1507 DEVFREQ_GOV_SIMPLE_ONDEMAND, 1508 &hba->vps->ondemand_data); 1509 if (IS_ERR(devfreq)) { 1510 ret = PTR_ERR(devfreq); 1511 dev_err(hba->dev, "Unable to register with devfreq %d\n", ret); 1512 1513 dev_pm_opp_remove(hba->dev, clki->min_freq); 1514 dev_pm_opp_remove(hba->dev, clki->max_freq); 1515 return ret; 1516 } 1517 1518 hba->devfreq = devfreq; 1519 1520 return 0; 1521 } 1522 1523 static void ufshcd_devfreq_remove(struct ufs_hba *hba) 1524 { 1525 struct list_head *clk_list = &hba->clk_list_head; 1526 struct ufs_clk_info *clki; 1527 1528 if (!hba->devfreq) 1529 return; 1530 1531 devfreq_remove_device(hba->devfreq); 1532 hba->devfreq = NULL; 1533 1534 clki = list_first_entry(clk_list, struct ufs_clk_info, list); 1535 dev_pm_opp_remove(hba->dev, clki->min_freq); 1536 dev_pm_opp_remove(hba->dev, clki->max_freq); 1537 } 1538 1539 static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba) 1540 { 1541 unsigned long flags; 1542 1543 devfreq_suspend_device(hba->devfreq); 1544 spin_lock_irqsave(hba->host->host_lock, flags); 1545 hba->clk_scaling.window_start_t = 0; 1546 spin_unlock_irqrestore(hba->host->host_lock, flags); 1547 } 1548 1549 static void ufshcd_suspend_clkscaling(struct ufs_hba *hba) 1550 { 1551 unsigned long flags; 1552 bool suspend = false; 1553 1554 cancel_work_sync(&hba->clk_scaling.suspend_work); 1555 cancel_work_sync(&hba->clk_scaling.resume_work); 1556 1557 spin_lock_irqsave(hba->host->host_lock, flags); 1558 if (!hba->clk_scaling.is_suspended) { 1559 suspend = true; 1560 hba->clk_scaling.is_suspended = true; 1561 } 1562 spin_unlock_irqrestore(hba->host->host_lock, flags); 1563 1564 if (suspend) 1565 __ufshcd_suspend_clkscaling(hba); 1566 } 1567 1568 static void ufshcd_resume_clkscaling(struct ufs_hba *hba) 1569 { 1570 unsigned long flags; 1571 bool resume = false; 1572 1573 spin_lock_irqsave(hba->host->host_lock, flags); 1574 if (hba->clk_scaling.is_suspended) { 1575 resume = true; 1576 hba->clk_scaling.is_suspended = false; 1577 } 1578 spin_unlock_irqrestore(hba->host->host_lock, flags); 1579 1580 if (resume) 1581 devfreq_resume_device(hba->devfreq); 1582 } 1583 1584 static ssize_t ufshcd_clkscale_enable_show(struct device *dev, 1585 struct device_attribute *attr, char *buf) 1586 { 1587 struct ufs_hba *hba = dev_get_drvdata(dev); 1588 1589 return sysfs_emit(buf, "%d\n", hba->clk_scaling.is_enabled); 1590 } 1591 1592 static ssize_t ufshcd_clkscale_enable_store(struct device *dev, 1593 struct device_attribute *attr, const char *buf, size_t count) 1594 { 1595 struct ufs_hba *hba = dev_get_drvdata(dev); 1596 u32 value; 1597 int err = 0; 1598 1599 if (kstrtou32(buf, 0, &value)) 1600 return -EINVAL; 1601 1602 down(&hba->host_sem); 1603 if (!ufshcd_is_user_access_allowed(hba)) { 1604 err = -EBUSY; 1605 goto out; 1606 } 1607 1608 value = !!value; 1609 if (value == hba->clk_scaling.is_enabled) 1610 goto out; 1611 1612 ufshcd_rpm_get_sync(hba); 1613 ufshcd_hold(hba); 1614 1615 hba->clk_scaling.is_enabled = value; 1616 1617 if (value) { 1618 ufshcd_resume_clkscaling(hba); 1619 } else { 1620 ufshcd_suspend_clkscaling(hba); 1621 err = ufshcd_devfreq_scale(hba, true); 1622 if (err) 1623 dev_err(hba->dev, "%s: failed to scale clocks up %d\n", 1624 __func__, err); 1625 } 1626 1627 ufshcd_release(hba); 1628 ufshcd_rpm_put_sync(hba); 1629 out: 1630 up(&hba->host_sem); 1631 return err ? err : count; 1632 } 1633 1634 static void ufshcd_init_clk_scaling_sysfs(struct ufs_hba *hba) 1635 { 1636 hba->clk_scaling.enable_attr.show = ufshcd_clkscale_enable_show; 1637 hba->clk_scaling.enable_attr.store = ufshcd_clkscale_enable_store; 1638 sysfs_attr_init(&hba->clk_scaling.enable_attr.attr); 1639 hba->clk_scaling.enable_attr.attr.name = "clkscale_enable"; 1640 hba->clk_scaling.enable_attr.attr.mode = 0644; 1641 if (device_create_file(hba->dev, &hba->clk_scaling.enable_attr)) 1642 dev_err(hba->dev, "Failed to create sysfs for clkscale_enable\n"); 1643 } 1644 1645 static void ufshcd_remove_clk_scaling_sysfs(struct ufs_hba *hba) 1646 { 1647 if (hba->clk_scaling.enable_attr.attr.name) 1648 device_remove_file(hba->dev, &hba->clk_scaling.enable_attr); 1649 } 1650 1651 static void ufshcd_init_clk_scaling(struct ufs_hba *hba) 1652 { 1653 char wq_name[sizeof("ufs_clkscaling_00")]; 1654 1655 if (!ufshcd_is_clkscaling_supported(hba)) 1656 return; 1657 1658 if (!hba->clk_scaling.min_gear) 1659 hba->clk_scaling.min_gear = UFS_HS_G1; 1660 1661 INIT_WORK(&hba->clk_scaling.suspend_work, 1662 ufshcd_clk_scaling_suspend_work); 1663 INIT_WORK(&hba->clk_scaling.resume_work, 1664 ufshcd_clk_scaling_resume_work); 1665 1666 snprintf(wq_name, sizeof(wq_name), "ufs_clkscaling_%d", 1667 hba->host->host_no); 1668 hba->clk_scaling.workq = create_singlethread_workqueue(wq_name); 1669 1670 hba->clk_scaling.is_initialized = true; 1671 } 1672 1673 static void ufshcd_exit_clk_scaling(struct ufs_hba *hba) 1674 { 1675 if (!hba->clk_scaling.is_initialized) 1676 return; 1677 1678 ufshcd_remove_clk_scaling_sysfs(hba); 1679 destroy_workqueue(hba->clk_scaling.workq); 1680 ufshcd_devfreq_remove(hba); 1681 hba->clk_scaling.is_initialized = false; 1682 } 1683 1684 static void ufshcd_ungate_work(struct work_struct *work) 1685 { 1686 int ret; 1687 unsigned long flags; 1688 struct ufs_hba *hba = container_of(work, struct ufs_hba, 1689 clk_gating.ungate_work); 1690 1691 cancel_delayed_work_sync(&hba->clk_gating.gate_work); 1692 1693 spin_lock_irqsave(hba->host->host_lock, flags); 1694 if (hba->clk_gating.state == CLKS_ON) { 1695 spin_unlock_irqrestore(hba->host->host_lock, flags); 1696 return; 1697 } 1698 1699 spin_unlock_irqrestore(hba->host->host_lock, flags); 1700 ufshcd_hba_vreg_set_hpm(hba); 1701 ufshcd_setup_clocks(hba, true); 1702 1703 ufshcd_enable_irq(hba); 1704 1705 /* Exit from hibern8 */ 1706 if (ufshcd_can_hibern8_during_gating(hba)) { 1707 /* Prevent gating in this path */ 1708 hba->clk_gating.is_suspended = true; 1709 if (ufshcd_is_link_hibern8(hba)) { 1710 ret = ufshcd_uic_hibern8_exit(hba); 1711 if (ret) 1712 dev_err(hba->dev, "%s: hibern8 exit failed %d\n", 1713 __func__, ret); 1714 else 1715 ufshcd_set_link_active(hba); 1716 } 1717 hba->clk_gating.is_suspended = false; 1718 } 1719 } 1720 1721 /** 1722 * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release. 1723 * Also, exit from hibern8 mode and set the link as active. 1724 * @hba: per adapter instance 1725 */ 1726 void ufshcd_hold(struct ufs_hba *hba) 1727 { 1728 bool flush_result; 1729 unsigned long flags; 1730 1731 if (!ufshcd_is_clkgating_allowed(hba) || 1732 !hba->clk_gating.is_initialized) 1733 return; 1734 spin_lock_irqsave(hba->host->host_lock, flags); 1735 hba->clk_gating.active_reqs++; 1736 1737 start: 1738 switch (hba->clk_gating.state) { 1739 case CLKS_ON: 1740 /* 1741 * Wait for the ungate work to complete if in progress. 1742 * Though the clocks may be in ON state, the link could 1743 * still be in hibner8 state if hibern8 is allowed 1744 * during clock gating. 1745 * Make sure we exit hibern8 state also in addition to 1746 * clocks being ON. 1747 */ 1748 if (ufshcd_can_hibern8_during_gating(hba) && 1749 ufshcd_is_link_hibern8(hba)) { 1750 spin_unlock_irqrestore(hba->host->host_lock, flags); 1751 flush_result = flush_work(&hba->clk_gating.ungate_work); 1752 if (hba->clk_gating.is_suspended && !flush_result) 1753 return; 1754 spin_lock_irqsave(hba->host->host_lock, flags); 1755 goto start; 1756 } 1757 break; 1758 case REQ_CLKS_OFF: 1759 if (cancel_delayed_work(&hba->clk_gating.gate_work)) { 1760 hba->clk_gating.state = CLKS_ON; 1761 trace_ufshcd_clk_gating(dev_name(hba->dev), 1762 hba->clk_gating.state); 1763 break; 1764 } 1765 /* 1766 * If we are here, it means gating work is either done or 1767 * currently running. Hence, fall through to cancel gating 1768 * work and to enable clocks. 1769 */ 1770 fallthrough; 1771 case CLKS_OFF: 1772 hba->clk_gating.state = REQ_CLKS_ON; 1773 trace_ufshcd_clk_gating(dev_name(hba->dev), 1774 hba->clk_gating.state); 1775 queue_work(hba->clk_gating.clk_gating_workq, 1776 &hba->clk_gating.ungate_work); 1777 /* 1778 * fall through to check if we should wait for this 1779 * work to be done or not. 1780 */ 1781 fallthrough; 1782 case REQ_CLKS_ON: 1783 spin_unlock_irqrestore(hba->host->host_lock, flags); 1784 flush_work(&hba->clk_gating.ungate_work); 1785 /* Make sure state is CLKS_ON before returning */ 1786 spin_lock_irqsave(hba->host->host_lock, flags); 1787 goto start; 1788 default: 1789 dev_err(hba->dev, "%s: clk gating is in invalid state %d\n", 1790 __func__, hba->clk_gating.state); 1791 break; 1792 } 1793 spin_unlock_irqrestore(hba->host->host_lock, flags); 1794 } 1795 EXPORT_SYMBOL_GPL(ufshcd_hold); 1796 1797 static void ufshcd_gate_work(struct work_struct *work) 1798 { 1799 struct ufs_hba *hba = container_of(work, struct ufs_hba, 1800 clk_gating.gate_work.work); 1801 unsigned long flags; 1802 int ret; 1803 1804 spin_lock_irqsave(hba->host->host_lock, flags); 1805 /* 1806 * In case you are here to cancel this work the gating state 1807 * would be marked as REQ_CLKS_ON. In this case save time by 1808 * skipping the gating work and exit after changing the clock 1809 * state to CLKS_ON. 1810 */ 1811 if (hba->clk_gating.is_suspended || 1812 (hba->clk_gating.state != REQ_CLKS_OFF)) { 1813 hba->clk_gating.state = CLKS_ON; 1814 trace_ufshcd_clk_gating(dev_name(hba->dev), 1815 hba->clk_gating.state); 1816 goto rel_lock; 1817 } 1818 1819 if (hba->clk_gating.active_reqs 1820 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL 1821 || hba->outstanding_reqs || hba->outstanding_tasks 1822 || hba->active_uic_cmd || hba->uic_async_done) 1823 goto rel_lock; 1824 1825 spin_unlock_irqrestore(hba->host->host_lock, flags); 1826 1827 /* put the link into hibern8 mode before turning off clocks */ 1828 if (ufshcd_can_hibern8_during_gating(hba)) { 1829 ret = ufshcd_uic_hibern8_enter(hba); 1830 if (ret) { 1831 hba->clk_gating.state = CLKS_ON; 1832 dev_err(hba->dev, "%s: hibern8 enter failed %d\n", 1833 __func__, ret); 1834 trace_ufshcd_clk_gating(dev_name(hba->dev), 1835 hba->clk_gating.state); 1836 goto out; 1837 } 1838 ufshcd_set_link_hibern8(hba); 1839 } 1840 1841 ufshcd_disable_irq(hba); 1842 1843 ufshcd_setup_clocks(hba, false); 1844 1845 /* Put the host controller in low power mode if possible */ 1846 ufshcd_hba_vreg_set_lpm(hba); 1847 /* 1848 * In case you are here to cancel this work the gating state 1849 * would be marked as REQ_CLKS_ON. In this case keep the state 1850 * as REQ_CLKS_ON which would anyway imply that clocks are off 1851 * and a request to turn them on is pending. By doing this way, 1852 * we keep the state machine in tact and this would ultimately 1853 * prevent from doing cancel work multiple times when there are 1854 * new requests arriving before the current cancel work is done. 1855 */ 1856 spin_lock_irqsave(hba->host->host_lock, flags); 1857 if (hba->clk_gating.state == REQ_CLKS_OFF) { 1858 hba->clk_gating.state = CLKS_OFF; 1859 trace_ufshcd_clk_gating(dev_name(hba->dev), 1860 hba->clk_gating.state); 1861 } 1862 rel_lock: 1863 spin_unlock_irqrestore(hba->host->host_lock, flags); 1864 out: 1865 return; 1866 } 1867 1868 /* host lock must be held before calling this variant */ 1869 static void __ufshcd_release(struct ufs_hba *hba) 1870 { 1871 if (!ufshcd_is_clkgating_allowed(hba)) 1872 return; 1873 1874 hba->clk_gating.active_reqs--; 1875 1876 if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended || 1877 hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL || 1878 hba->outstanding_tasks || !hba->clk_gating.is_initialized || 1879 hba->active_uic_cmd || hba->uic_async_done || 1880 hba->clk_gating.state == CLKS_OFF) 1881 return; 1882 1883 hba->clk_gating.state = REQ_CLKS_OFF; 1884 trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state); 1885 queue_delayed_work(hba->clk_gating.clk_gating_workq, 1886 &hba->clk_gating.gate_work, 1887 msecs_to_jiffies(hba->clk_gating.delay_ms)); 1888 } 1889 1890 void ufshcd_release(struct ufs_hba *hba) 1891 { 1892 unsigned long flags; 1893 1894 spin_lock_irqsave(hba->host->host_lock, flags); 1895 __ufshcd_release(hba); 1896 spin_unlock_irqrestore(hba->host->host_lock, flags); 1897 } 1898 EXPORT_SYMBOL_GPL(ufshcd_release); 1899 1900 static ssize_t ufshcd_clkgate_delay_show(struct device *dev, 1901 struct device_attribute *attr, char *buf) 1902 { 1903 struct ufs_hba *hba = dev_get_drvdata(dev); 1904 1905 return sysfs_emit(buf, "%lu\n", hba->clk_gating.delay_ms); 1906 } 1907 1908 void ufshcd_clkgate_delay_set(struct device *dev, unsigned long value) 1909 { 1910 struct ufs_hba *hba = dev_get_drvdata(dev); 1911 unsigned long flags; 1912 1913 spin_lock_irqsave(hba->host->host_lock, flags); 1914 hba->clk_gating.delay_ms = value; 1915 spin_unlock_irqrestore(hba->host->host_lock, flags); 1916 } 1917 EXPORT_SYMBOL_GPL(ufshcd_clkgate_delay_set); 1918 1919 static ssize_t ufshcd_clkgate_delay_store(struct device *dev, 1920 struct device_attribute *attr, const char *buf, size_t count) 1921 { 1922 unsigned long value; 1923 1924 if (kstrtoul(buf, 0, &value)) 1925 return -EINVAL; 1926 1927 ufshcd_clkgate_delay_set(dev, value); 1928 return count; 1929 } 1930 1931 static ssize_t ufshcd_clkgate_enable_show(struct device *dev, 1932 struct device_attribute *attr, char *buf) 1933 { 1934 struct ufs_hba *hba = dev_get_drvdata(dev); 1935 1936 return sysfs_emit(buf, "%d\n", hba->clk_gating.is_enabled); 1937 } 1938 1939 static ssize_t ufshcd_clkgate_enable_store(struct device *dev, 1940 struct device_attribute *attr, const char *buf, size_t count) 1941 { 1942 struct ufs_hba *hba = dev_get_drvdata(dev); 1943 unsigned long flags; 1944 u32 value; 1945 1946 if (kstrtou32(buf, 0, &value)) 1947 return -EINVAL; 1948 1949 value = !!value; 1950 1951 spin_lock_irqsave(hba->host->host_lock, flags); 1952 if (value == hba->clk_gating.is_enabled) 1953 goto out; 1954 1955 if (value) 1956 __ufshcd_release(hba); 1957 else 1958 hba->clk_gating.active_reqs++; 1959 1960 hba->clk_gating.is_enabled = value; 1961 out: 1962 spin_unlock_irqrestore(hba->host->host_lock, flags); 1963 return count; 1964 } 1965 1966 static void ufshcd_init_clk_gating_sysfs(struct ufs_hba *hba) 1967 { 1968 hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show; 1969 hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store; 1970 sysfs_attr_init(&hba->clk_gating.delay_attr.attr); 1971 hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms"; 1972 hba->clk_gating.delay_attr.attr.mode = 0644; 1973 if (device_create_file(hba->dev, &hba->clk_gating.delay_attr)) 1974 dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n"); 1975 1976 hba->clk_gating.enable_attr.show = ufshcd_clkgate_enable_show; 1977 hba->clk_gating.enable_attr.store = ufshcd_clkgate_enable_store; 1978 sysfs_attr_init(&hba->clk_gating.enable_attr.attr); 1979 hba->clk_gating.enable_attr.attr.name = "clkgate_enable"; 1980 hba->clk_gating.enable_attr.attr.mode = 0644; 1981 if (device_create_file(hba->dev, &hba->clk_gating.enable_attr)) 1982 dev_err(hba->dev, "Failed to create sysfs for clkgate_enable\n"); 1983 } 1984 1985 static void ufshcd_remove_clk_gating_sysfs(struct ufs_hba *hba) 1986 { 1987 if (hba->clk_gating.delay_attr.attr.name) 1988 device_remove_file(hba->dev, &hba->clk_gating.delay_attr); 1989 if (hba->clk_gating.enable_attr.attr.name) 1990 device_remove_file(hba->dev, &hba->clk_gating.enable_attr); 1991 } 1992 1993 static void ufshcd_init_clk_gating(struct ufs_hba *hba) 1994 { 1995 char wq_name[sizeof("ufs_clk_gating_00")]; 1996 1997 if (!ufshcd_is_clkgating_allowed(hba)) 1998 return; 1999 2000 hba->clk_gating.state = CLKS_ON; 2001 2002 hba->clk_gating.delay_ms = 150; 2003 INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work); 2004 INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work); 2005 2006 snprintf(wq_name, ARRAY_SIZE(wq_name), "ufs_clk_gating_%d", 2007 hba->host->host_no); 2008 hba->clk_gating.clk_gating_workq = alloc_ordered_workqueue(wq_name, 2009 WQ_MEM_RECLAIM | WQ_HIGHPRI); 2010 2011 ufshcd_init_clk_gating_sysfs(hba); 2012 2013 hba->clk_gating.is_enabled = true; 2014 hba->clk_gating.is_initialized = true; 2015 } 2016 2017 static void ufshcd_exit_clk_gating(struct ufs_hba *hba) 2018 { 2019 if (!hba->clk_gating.is_initialized) 2020 return; 2021 2022 ufshcd_remove_clk_gating_sysfs(hba); 2023 2024 /* Ungate the clock if necessary. */ 2025 ufshcd_hold(hba); 2026 hba->clk_gating.is_initialized = false; 2027 ufshcd_release(hba); 2028 2029 destroy_workqueue(hba->clk_gating.clk_gating_workq); 2030 } 2031 2032 static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba) 2033 { 2034 bool queue_resume_work = false; 2035 ktime_t curr_t = ktime_get(); 2036 unsigned long flags; 2037 2038 if (!ufshcd_is_clkscaling_supported(hba)) 2039 return; 2040 2041 spin_lock_irqsave(hba->host->host_lock, flags); 2042 if (!hba->clk_scaling.active_reqs++) 2043 queue_resume_work = true; 2044 2045 if (!hba->clk_scaling.is_enabled || hba->pm_op_in_progress) { 2046 spin_unlock_irqrestore(hba->host->host_lock, flags); 2047 return; 2048 } 2049 2050 if (queue_resume_work) 2051 queue_work(hba->clk_scaling.workq, 2052 &hba->clk_scaling.resume_work); 2053 2054 if (!hba->clk_scaling.window_start_t) { 2055 hba->clk_scaling.window_start_t = curr_t; 2056 hba->clk_scaling.tot_busy_t = 0; 2057 hba->clk_scaling.is_busy_started = false; 2058 } 2059 2060 if (!hba->clk_scaling.is_busy_started) { 2061 hba->clk_scaling.busy_start_t = curr_t; 2062 hba->clk_scaling.is_busy_started = true; 2063 } 2064 spin_unlock_irqrestore(hba->host->host_lock, flags); 2065 } 2066 2067 static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba) 2068 { 2069 struct ufs_clk_scaling *scaling = &hba->clk_scaling; 2070 unsigned long flags; 2071 2072 if (!ufshcd_is_clkscaling_supported(hba)) 2073 return; 2074 2075 spin_lock_irqsave(hba->host->host_lock, flags); 2076 hba->clk_scaling.active_reqs--; 2077 if (!scaling->active_reqs && scaling->is_busy_started) { 2078 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(), 2079 scaling->busy_start_t)); 2080 scaling->busy_start_t = 0; 2081 scaling->is_busy_started = false; 2082 } 2083 spin_unlock_irqrestore(hba->host->host_lock, flags); 2084 } 2085 2086 static inline int ufshcd_monitor_opcode2dir(u8 opcode) 2087 { 2088 if (opcode == READ_6 || opcode == READ_10 || opcode == READ_16) 2089 return READ; 2090 else if (opcode == WRITE_6 || opcode == WRITE_10 || opcode == WRITE_16) 2091 return WRITE; 2092 else 2093 return -EINVAL; 2094 } 2095 2096 static inline bool ufshcd_should_inform_monitor(struct ufs_hba *hba, 2097 struct ufshcd_lrb *lrbp) 2098 { 2099 const struct ufs_hba_monitor *m = &hba->monitor; 2100 2101 return (m->enabled && lrbp && lrbp->cmd && 2102 (!m->chunk_size || m->chunk_size == lrbp->cmd->sdb.length) && 2103 ktime_before(hba->monitor.enabled_ts, lrbp->issue_time_stamp)); 2104 } 2105 2106 static void ufshcd_start_monitor(struct ufs_hba *hba, 2107 const struct ufshcd_lrb *lrbp) 2108 { 2109 int dir = ufshcd_monitor_opcode2dir(*lrbp->cmd->cmnd); 2110 unsigned long flags; 2111 2112 spin_lock_irqsave(hba->host->host_lock, flags); 2113 if (dir >= 0 && hba->monitor.nr_queued[dir]++ == 0) 2114 hba->monitor.busy_start_ts[dir] = ktime_get(); 2115 spin_unlock_irqrestore(hba->host->host_lock, flags); 2116 } 2117 2118 static void ufshcd_update_monitor(struct ufs_hba *hba, const struct ufshcd_lrb *lrbp) 2119 { 2120 int dir = ufshcd_monitor_opcode2dir(*lrbp->cmd->cmnd); 2121 unsigned long flags; 2122 2123 spin_lock_irqsave(hba->host->host_lock, flags); 2124 if (dir >= 0 && hba->monitor.nr_queued[dir] > 0) { 2125 const struct request *req = scsi_cmd_to_rq(lrbp->cmd); 2126 struct ufs_hba_monitor *m = &hba->monitor; 2127 ktime_t now, inc, lat; 2128 2129 now = lrbp->compl_time_stamp; 2130 inc = ktime_sub(now, m->busy_start_ts[dir]); 2131 m->total_busy[dir] = ktime_add(m->total_busy[dir], inc); 2132 m->nr_sec_rw[dir] += blk_rq_sectors(req); 2133 2134 /* Update latencies */ 2135 m->nr_req[dir]++; 2136 lat = ktime_sub(now, lrbp->issue_time_stamp); 2137 m->lat_sum[dir] += lat; 2138 if (m->lat_max[dir] < lat || !m->lat_max[dir]) 2139 m->lat_max[dir] = lat; 2140 if (m->lat_min[dir] > lat || !m->lat_min[dir]) 2141 m->lat_min[dir] = lat; 2142 2143 m->nr_queued[dir]--; 2144 /* Push forward the busy start of monitor */ 2145 m->busy_start_ts[dir] = now; 2146 } 2147 spin_unlock_irqrestore(hba->host->host_lock, flags); 2148 } 2149 2150 /** 2151 * ufshcd_send_command - Send SCSI or device management commands 2152 * @hba: per adapter instance 2153 * @task_tag: Task tag of the command 2154 * @hwq: pointer to hardware queue instance 2155 */ 2156 static inline 2157 void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag, 2158 struct ufs_hw_queue *hwq) 2159 { 2160 struct ufshcd_lrb *lrbp = &hba->lrb[task_tag]; 2161 unsigned long flags; 2162 2163 lrbp->issue_time_stamp = ktime_get(); 2164 lrbp->issue_time_stamp_local_clock = local_clock(); 2165 lrbp->compl_time_stamp = ktime_set(0, 0); 2166 lrbp->compl_time_stamp_local_clock = 0; 2167 ufshcd_add_command_trace(hba, task_tag, UFS_CMD_SEND); 2168 ufshcd_clk_scaling_start_busy(hba); 2169 if (unlikely(ufshcd_should_inform_monitor(hba, lrbp))) 2170 ufshcd_start_monitor(hba, lrbp); 2171 2172 if (is_mcq_enabled(hba)) { 2173 int utrd_size = sizeof(struct utp_transfer_req_desc); 2174 struct utp_transfer_req_desc *src = lrbp->utr_descriptor_ptr; 2175 struct utp_transfer_req_desc *dest; 2176 2177 spin_lock(&hwq->sq_lock); 2178 dest = hwq->sqe_base_addr + hwq->sq_tail_slot; 2179 memcpy(dest, src, utrd_size); 2180 ufshcd_inc_sq_tail(hwq); 2181 spin_unlock(&hwq->sq_lock); 2182 } else { 2183 spin_lock_irqsave(&hba->outstanding_lock, flags); 2184 if (hba->vops && hba->vops->setup_xfer_req) 2185 hba->vops->setup_xfer_req(hba, lrbp->task_tag, 2186 !!lrbp->cmd); 2187 __set_bit(lrbp->task_tag, &hba->outstanding_reqs); 2188 ufshcd_writel(hba, 1 << lrbp->task_tag, 2189 REG_UTP_TRANSFER_REQ_DOOR_BELL); 2190 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 2191 } 2192 } 2193 2194 /** 2195 * ufshcd_copy_sense_data - Copy sense data in case of check condition 2196 * @lrbp: pointer to local reference block 2197 */ 2198 static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp) 2199 { 2200 u8 *const sense_buffer = lrbp->cmd->sense_buffer; 2201 u16 resp_len; 2202 int len; 2203 2204 resp_len = be16_to_cpu(lrbp->ucd_rsp_ptr->header.data_segment_length); 2205 if (sense_buffer && resp_len) { 2206 int len_to_copy; 2207 2208 len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len); 2209 len_to_copy = min_t(int, UFS_SENSE_SIZE, len); 2210 2211 memcpy(sense_buffer, lrbp->ucd_rsp_ptr->sr.sense_data, 2212 len_to_copy); 2213 } 2214 } 2215 2216 /** 2217 * ufshcd_copy_query_response() - Copy the Query Response and the data 2218 * descriptor 2219 * @hba: per adapter instance 2220 * @lrbp: pointer to local reference block 2221 * 2222 * Return: 0 upon success; < 0 upon failure. 2223 */ 2224 static 2225 int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) 2226 { 2227 struct ufs_query_res *query_res = &hba->dev_cmd.query.response; 2228 2229 memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE); 2230 2231 /* Get the descriptor */ 2232 if (hba->dev_cmd.query.descriptor && 2233 lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) { 2234 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr + 2235 GENERAL_UPIU_REQUEST_SIZE; 2236 u16 resp_len; 2237 u16 buf_len; 2238 2239 /* data segment length */ 2240 resp_len = be16_to_cpu(lrbp->ucd_rsp_ptr->header 2241 .data_segment_length); 2242 buf_len = be16_to_cpu( 2243 hba->dev_cmd.query.request.upiu_req.length); 2244 if (likely(buf_len >= resp_len)) { 2245 memcpy(hba->dev_cmd.query.descriptor, descp, resp_len); 2246 } else { 2247 dev_warn(hba->dev, 2248 "%s: rsp size %d is bigger than buffer size %d", 2249 __func__, resp_len, buf_len); 2250 return -EINVAL; 2251 } 2252 } 2253 2254 return 0; 2255 } 2256 2257 /** 2258 * ufshcd_hba_capabilities - Read controller capabilities 2259 * @hba: per adapter instance 2260 * 2261 * Return: 0 on success, negative on error. 2262 */ 2263 static inline int ufshcd_hba_capabilities(struct ufs_hba *hba) 2264 { 2265 int err; 2266 2267 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES); 2268 if (hba->quirks & UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS) 2269 hba->capabilities &= ~MASK_64_ADDRESSING_SUPPORT; 2270 2271 /* nutrs and nutmrs are 0 based values */ 2272 hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1; 2273 hba->nutmrs = 2274 ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1; 2275 hba->reserved_slot = hba->nutrs - 1; 2276 2277 /* Read crypto capabilities */ 2278 err = ufshcd_hba_init_crypto_capabilities(hba); 2279 if (err) { 2280 dev_err(hba->dev, "crypto setup failed\n"); 2281 return err; 2282 } 2283 2284 /* 2285 * The UFSHCI 3.0 specification does not define MCQ_SUPPORT and 2286 * LSDB_SUPPORT, but [31:29] as reserved bits with reset value 0s, which 2287 * means we can simply read values regardless of version. 2288 */ 2289 hba->mcq_sup = FIELD_GET(MASK_MCQ_SUPPORT, hba->capabilities); 2290 /* 2291 * 0h: legacy single doorbell support is available 2292 * 1h: indicate that legacy single doorbell support has been removed 2293 */ 2294 hba->lsdb_sup = !FIELD_GET(MASK_LSDB_SUPPORT, hba->capabilities); 2295 if (!hba->mcq_sup) 2296 return 0; 2297 2298 hba->mcq_capabilities = ufshcd_readl(hba, REG_MCQCAP); 2299 hba->ext_iid_sup = FIELD_GET(MASK_EXT_IID_SUPPORT, 2300 hba->mcq_capabilities); 2301 2302 return 0; 2303 } 2304 2305 /** 2306 * ufshcd_ready_for_uic_cmd - Check if controller is ready 2307 * to accept UIC commands 2308 * @hba: per adapter instance 2309 * 2310 * Return: true on success, else false. 2311 */ 2312 static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba) 2313 { 2314 u32 val; 2315 int ret = read_poll_timeout(ufshcd_readl, val, val & UIC_COMMAND_READY, 2316 500, UIC_CMD_TIMEOUT * 1000, false, hba, 2317 REG_CONTROLLER_STATUS); 2318 return ret == 0 ? true : false; 2319 } 2320 2321 /** 2322 * ufshcd_get_upmcrs - Get the power mode change request status 2323 * @hba: Pointer to adapter instance 2324 * 2325 * This function gets the UPMCRS field of HCS register 2326 * 2327 * Return: value of UPMCRS field. 2328 */ 2329 static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba) 2330 { 2331 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7; 2332 } 2333 2334 /** 2335 * ufshcd_dispatch_uic_cmd - Dispatch an UIC command to the Unipro layer 2336 * @hba: per adapter instance 2337 * @uic_cmd: UIC command 2338 */ 2339 static inline void 2340 ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) 2341 { 2342 lockdep_assert_held(&hba->uic_cmd_mutex); 2343 2344 WARN_ON(hba->active_uic_cmd); 2345 2346 hba->active_uic_cmd = uic_cmd; 2347 2348 /* Write Args */ 2349 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1); 2350 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2); 2351 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3); 2352 2353 ufshcd_add_uic_command_trace(hba, uic_cmd, UFS_CMD_SEND); 2354 2355 /* Write UIC Cmd */ 2356 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK, 2357 REG_UIC_COMMAND); 2358 } 2359 2360 /** 2361 * ufshcd_wait_for_uic_cmd - Wait for completion of an UIC command 2362 * @hba: per adapter instance 2363 * @uic_cmd: UIC command 2364 * 2365 * Return: 0 only if success. 2366 */ 2367 static int 2368 ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) 2369 { 2370 int ret; 2371 unsigned long flags; 2372 2373 lockdep_assert_held(&hba->uic_cmd_mutex); 2374 2375 if (wait_for_completion_timeout(&uic_cmd->done, 2376 msecs_to_jiffies(UIC_CMD_TIMEOUT))) { 2377 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT; 2378 } else { 2379 ret = -ETIMEDOUT; 2380 dev_err(hba->dev, 2381 "uic cmd 0x%x with arg3 0x%x completion timeout\n", 2382 uic_cmd->command, uic_cmd->argument3); 2383 2384 if (!uic_cmd->cmd_active) { 2385 dev_err(hba->dev, "%s: UIC cmd has been completed, return the result\n", 2386 __func__); 2387 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT; 2388 } 2389 } 2390 2391 spin_lock_irqsave(hba->host->host_lock, flags); 2392 hba->active_uic_cmd = NULL; 2393 spin_unlock_irqrestore(hba->host->host_lock, flags); 2394 2395 return ret; 2396 } 2397 2398 /** 2399 * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result 2400 * @hba: per adapter instance 2401 * @uic_cmd: UIC command 2402 * 2403 * Return: 0 only if success. 2404 */ 2405 static int 2406 __ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) 2407 { 2408 lockdep_assert_held(&hba->uic_cmd_mutex); 2409 2410 if (!ufshcd_ready_for_uic_cmd(hba)) { 2411 dev_err(hba->dev, 2412 "Controller not ready to accept UIC commands\n"); 2413 return -EIO; 2414 } 2415 2416 init_completion(&uic_cmd->done); 2417 2418 uic_cmd->cmd_active = 1; 2419 ufshcd_dispatch_uic_cmd(hba, uic_cmd); 2420 2421 return 0; 2422 } 2423 2424 /** 2425 * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result 2426 * @hba: per adapter instance 2427 * @uic_cmd: UIC command 2428 * 2429 * Return: 0 only if success. 2430 */ 2431 int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) 2432 { 2433 int ret; 2434 2435 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UIC_CMD) 2436 return 0; 2437 2438 ufshcd_hold(hba); 2439 mutex_lock(&hba->uic_cmd_mutex); 2440 ufshcd_add_delay_before_dme_cmd(hba); 2441 2442 ret = __ufshcd_send_uic_cmd(hba, uic_cmd); 2443 if (!ret) 2444 ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd); 2445 2446 mutex_unlock(&hba->uic_cmd_mutex); 2447 2448 ufshcd_release(hba); 2449 return ret; 2450 } 2451 2452 /** 2453 * ufshcd_sgl_to_prdt - SG list to PRTD (Physical Region Description Table, 4DW format) 2454 * @hba: per-adapter instance 2455 * @lrbp: pointer to local reference block 2456 * @sg_entries: The number of sg lists actually used 2457 * @sg_list: Pointer to SG list 2458 */ 2459 static void ufshcd_sgl_to_prdt(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, int sg_entries, 2460 struct scatterlist *sg_list) 2461 { 2462 struct ufshcd_sg_entry *prd; 2463 struct scatterlist *sg; 2464 int i; 2465 2466 if (sg_entries) { 2467 2468 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) 2469 lrbp->utr_descriptor_ptr->prd_table_length = 2470 cpu_to_le16(sg_entries * ufshcd_sg_entry_size(hba)); 2471 else 2472 lrbp->utr_descriptor_ptr->prd_table_length = cpu_to_le16(sg_entries); 2473 2474 prd = lrbp->ucd_prdt_ptr; 2475 2476 for_each_sg(sg_list, sg, sg_entries, i) { 2477 const unsigned int len = sg_dma_len(sg); 2478 2479 /* 2480 * From the UFSHCI spec: "Data Byte Count (DBC): A '0' 2481 * based value that indicates the length, in bytes, of 2482 * the data block. A maximum of length of 256KB may 2483 * exist for any entry. Bits 1:0 of this field shall be 2484 * 11b to indicate Dword granularity. A value of '3' 2485 * indicates 4 bytes, '7' indicates 8 bytes, etc." 2486 */ 2487 WARN_ONCE(len > SZ_256K, "len = %#x\n", len); 2488 prd->size = cpu_to_le32(len - 1); 2489 prd->addr = cpu_to_le64(sg->dma_address); 2490 prd->reserved = 0; 2491 prd = (void *)prd + ufshcd_sg_entry_size(hba); 2492 } 2493 } else { 2494 lrbp->utr_descriptor_ptr->prd_table_length = 0; 2495 } 2496 } 2497 2498 /** 2499 * ufshcd_map_sg - Map scatter-gather list to prdt 2500 * @hba: per adapter instance 2501 * @lrbp: pointer to local reference block 2502 * 2503 * Return: 0 in case of success, non-zero value in case of failure. 2504 */ 2505 static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) 2506 { 2507 struct scsi_cmnd *cmd = lrbp->cmd; 2508 int sg_segments = scsi_dma_map(cmd); 2509 2510 if (sg_segments < 0) 2511 return sg_segments; 2512 2513 ufshcd_sgl_to_prdt(hba, lrbp, sg_segments, scsi_sglist(cmd)); 2514 2515 return 0; 2516 } 2517 2518 /** 2519 * ufshcd_enable_intr - enable interrupts 2520 * @hba: per adapter instance 2521 * @intrs: interrupt bits 2522 */ 2523 static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs) 2524 { 2525 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 2526 2527 if (hba->ufs_version == ufshci_version(1, 0)) { 2528 u32 rw; 2529 rw = set & INTERRUPT_MASK_RW_VER_10; 2530 set = rw | ((set ^ intrs) & intrs); 2531 } else { 2532 set |= intrs; 2533 } 2534 2535 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE); 2536 } 2537 2538 /** 2539 * ufshcd_disable_intr - disable interrupts 2540 * @hba: per adapter instance 2541 * @intrs: interrupt bits 2542 */ 2543 static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs) 2544 { 2545 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 2546 2547 if (hba->ufs_version == ufshci_version(1, 0)) { 2548 u32 rw; 2549 rw = (set & INTERRUPT_MASK_RW_VER_10) & 2550 ~(intrs & INTERRUPT_MASK_RW_VER_10); 2551 set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10); 2552 2553 } else { 2554 set &= ~intrs; 2555 } 2556 2557 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE); 2558 } 2559 2560 /** 2561 * ufshcd_prepare_req_desc_hdr - Fill UTP Transfer request descriptor header according to request 2562 * descriptor according to request 2563 * @lrbp: pointer to local reference block 2564 * @upiu_flags: flags required in the header 2565 * @cmd_dir: requests data direction 2566 * @ehs_length: Total EHS Length (in 32‐bytes units of all Extra Header Segments) 2567 */ 2568 static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp, u8 *upiu_flags, 2569 enum dma_data_direction cmd_dir, int ehs_length) 2570 { 2571 struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr; 2572 struct request_desc_header *h = &req_desc->header; 2573 enum utp_data_direction data_direction; 2574 2575 *h = (typeof(*h)){ }; 2576 2577 if (cmd_dir == DMA_FROM_DEVICE) { 2578 data_direction = UTP_DEVICE_TO_HOST; 2579 *upiu_flags = UPIU_CMD_FLAGS_READ; 2580 } else if (cmd_dir == DMA_TO_DEVICE) { 2581 data_direction = UTP_HOST_TO_DEVICE; 2582 *upiu_flags = UPIU_CMD_FLAGS_WRITE; 2583 } else { 2584 data_direction = UTP_NO_DATA_TRANSFER; 2585 *upiu_flags = UPIU_CMD_FLAGS_NONE; 2586 } 2587 2588 h->command_type = lrbp->command_type; 2589 h->data_direction = data_direction; 2590 h->ehs_length = ehs_length; 2591 2592 if (lrbp->intr_cmd) 2593 h->interrupt = 1; 2594 2595 /* Prepare crypto related dwords */ 2596 ufshcd_prepare_req_desc_hdr_crypto(lrbp, h); 2597 2598 /* 2599 * assigning invalid value for command status. Controller 2600 * updates OCS on command completion, with the command 2601 * status 2602 */ 2603 h->ocs = OCS_INVALID_COMMAND_STATUS; 2604 2605 req_desc->prd_table_length = 0; 2606 } 2607 2608 /** 2609 * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc, 2610 * for scsi commands 2611 * @lrbp: local reference block pointer 2612 * @upiu_flags: flags 2613 */ 2614 static 2615 void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u8 upiu_flags) 2616 { 2617 struct scsi_cmnd *cmd = lrbp->cmd; 2618 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr; 2619 unsigned short cdb_len; 2620 2621 ucd_req_ptr->header = (struct utp_upiu_header){ 2622 .transaction_code = UPIU_TRANSACTION_COMMAND, 2623 .flags = upiu_flags, 2624 .lun = lrbp->lun, 2625 .task_tag = lrbp->task_tag, 2626 .command_set_type = UPIU_COMMAND_SET_TYPE_SCSI, 2627 }; 2628 2629 ucd_req_ptr->sc.exp_data_transfer_len = cpu_to_be32(cmd->sdb.length); 2630 2631 cdb_len = min_t(unsigned short, cmd->cmd_len, UFS_CDB_SIZE); 2632 memset(ucd_req_ptr->sc.cdb, 0, UFS_CDB_SIZE); 2633 memcpy(ucd_req_ptr->sc.cdb, cmd->cmnd, cdb_len); 2634 2635 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 2636 } 2637 2638 /** 2639 * ufshcd_prepare_utp_query_req_upiu() - fill the utp_transfer_req_desc for query request 2640 * @hba: UFS hba 2641 * @lrbp: local reference block pointer 2642 * @upiu_flags: flags 2643 */ 2644 static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba, 2645 struct ufshcd_lrb *lrbp, u8 upiu_flags) 2646 { 2647 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr; 2648 struct ufs_query *query = &hba->dev_cmd.query; 2649 u16 len = be16_to_cpu(query->request.upiu_req.length); 2650 2651 /* Query request header */ 2652 ucd_req_ptr->header = (struct utp_upiu_header){ 2653 .transaction_code = UPIU_TRANSACTION_QUERY_REQ, 2654 .flags = upiu_flags, 2655 .lun = lrbp->lun, 2656 .task_tag = lrbp->task_tag, 2657 .query_function = query->request.query_func, 2658 /* Data segment length only need for WRITE_DESC */ 2659 .data_segment_length = 2660 query->request.upiu_req.opcode == 2661 UPIU_QUERY_OPCODE_WRITE_DESC ? 2662 cpu_to_be16(len) : 2663 0, 2664 }; 2665 2666 /* Copy the Query Request buffer as is */ 2667 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req, 2668 QUERY_OSF_SIZE); 2669 2670 /* Copy the Descriptor */ 2671 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC) 2672 memcpy(ucd_req_ptr + 1, query->descriptor, len); 2673 2674 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 2675 } 2676 2677 static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp) 2678 { 2679 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr; 2680 2681 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req)); 2682 2683 ucd_req_ptr->header = (struct utp_upiu_header){ 2684 .transaction_code = UPIU_TRANSACTION_NOP_OUT, 2685 .task_tag = lrbp->task_tag, 2686 }; 2687 2688 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 2689 } 2690 2691 /** 2692 * ufshcd_compose_devman_upiu - UFS Protocol Information Unit(UPIU) 2693 * for Device Management Purposes 2694 * @hba: per adapter instance 2695 * @lrbp: pointer to local reference block 2696 * 2697 * Return: 0 upon success; < 0 upon failure. 2698 */ 2699 static int ufshcd_compose_devman_upiu(struct ufs_hba *hba, 2700 struct ufshcd_lrb *lrbp) 2701 { 2702 u8 upiu_flags; 2703 int ret = 0; 2704 2705 if (hba->ufs_version <= ufshci_version(1, 1)) 2706 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE; 2707 else 2708 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE; 2709 2710 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE, 0); 2711 if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY) 2712 ufshcd_prepare_utp_query_req_upiu(hba, lrbp, upiu_flags); 2713 else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP) 2714 ufshcd_prepare_utp_nop_upiu(lrbp); 2715 else 2716 ret = -EINVAL; 2717 2718 return ret; 2719 } 2720 2721 /** 2722 * ufshcd_comp_scsi_upiu - UFS Protocol Information Unit(UPIU) 2723 * for SCSI Purposes 2724 * @hba: per adapter instance 2725 * @lrbp: pointer to local reference block 2726 * 2727 * Return: 0 upon success; < 0 upon failure. 2728 */ 2729 static int ufshcd_comp_scsi_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) 2730 { 2731 u8 upiu_flags; 2732 int ret = 0; 2733 2734 if (hba->ufs_version <= ufshci_version(1, 1)) 2735 lrbp->command_type = UTP_CMD_TYPE_SCSI; 2736 else 2737 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE; 2738 2739 if (likely(lrbp->cmd)) { 2740 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, lrbp->cmd->sc_data_direction, 0); 2741 ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags); 2742 } else { 2743 ret = -EINVAL; 2744 } 2745 2746 return ret; 2747 } 2748 2749 /** 2750 * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID 2751 * @upiu_wlun_id: UPIU W-LUN id 2752 * 2753 * Return: SCSI W-LUN id. 2754 */ 2755 static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id) 2756 { 2757 return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE; 2758 } 2759 2760 static inline bool is_device_wlun(struct scsi_device *sdev) 2761 { 2762 return sdev->lun == 2763 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN); 2764 } 2765 2766 /* 2767 * Associate the UFS controller queue with the default and poll HCTX types. 2768 * Initialize the mq_map[] arrays. 2769 */ 2770 static void ufshcd_map_queues(struct Scsi_Host *shost) 2771 { 2772 struct ufs_hba *hba = shost_priv(shost); 2773 int i, queue_offset = 0; 2774 2775 if (!is_mcq_supported(hba)) { 2776 hba->nr_queues[HCTX_TYPE_DEFAULT] = 1; 2777 hba->nr_queues[HCTX_TYPE_READ] = 0; 2778 hba->nr_queues[HCTX_TYPE_POLL] = 1; 2779 hba->nr_hw_queues = 1; 2780 } 2781 2782 for (i = 0; i < shost->nr_maps; i++) { 2783 struct blk_mq_queue_map *map = &shost->tag_set.map[i]; 2784 2785 map->nr_queues = hba->nr_queues[i]; 2786 if (!map->nr_queues) 2787 continue; 2788 map->queue_offset = queue_offset; 2789 if (i == HCTX_TYPE_POLL && !is_mcq_supported(hba)) 2790 map->queue_offset = 0; 2791 2792 blk_mq_map_queues(map); 2793 queue_offset += map->nr_queues; 2794 } 2795 } 2796 2797 static void ufshcd_init_lrb(struct ufs_hba *hba, struct ufshcd_lrb *lrb, int i) 2798 { 2799 struct utp_transfer_cmd_desc *cmd_descp = (void *)hba->ucdl_base_addr + 2800 i * ufshcd_get_ucd_size(hba); 2801 struct utp_transfer_req_desc *utrdlp = hba->utrdl_base_addr; 2802 dma_addr_t cmd_desc_element_addr = hba->ucdl_dma_addr + 2803 i * ufshcd_get_ucd_size(hba); 2804 u16 response_offset = le16_to_cpu(utrdlp[i].response_upiu_offset); 2805 u16 prdt_offset = le16_to_cpu(utrdlp[i].prd_table_offset); 2806 2807 lrb->utr_descriptor_ptr = utrdlp + i; 2808 lrb->utrd_dma_addr = hba->utrdl_dma_addr + 2809 i * sizeof(struct utp_transfer_req_desc); 2810 lrb->ucd_req_ptr = (struct utp_upiu_req *)cmd_descp->command_upiu; 2811 lrb->ucd_req_dma_addr = cmd_desc_element_addr; 2812 lrb->ucd_rsp_ptr = (struct utp_upiu_rsp *)cmd_descp->response_upiu; 2813 lrb->ucd_rsp_dma_addr = cmd_desc_element_addr + response_offset; 2814 lrb->ucd_prdt_ptr = (struct ufshcd_sg_entry *)cmd_descp->prd_table; 2815 lrb->ucd_prdt_dma_addr = cmd_desc_element_addr + prdt_offset; 2816 } 2817 2818 /** 2819 * ufshcd_queuecommand - main entry point for SCSI requests 2820 * @host: SCSI host pointer 2821 * @cmd: command from SCSI Midlayer 2822 * 2823 * Return: 0 for success, non-zero in case of failure. 2824 */ 2825 static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) 2826 { 2827 struct ufs_hba *hba = shost_priv(host); 2828 int tag = scsi_cmd_to_rq(cmd)->tag; 2829 struct ufshcd_lrb *lrbp; 2830 int err = 0; 2831 struct ufs_hw_queue *hwq = NULL; 2832 2833 WARN_ONCE(tag < 0 || tag >= hba->nutrs, "Invalid tag %d\n", tag); 2834 2835 switch (hba->ufshcd_state) { 2836 case UFSHCD_STATE_OPERATIONAL: 2837 break; 2838 case UFSHCD_STATE_EH_SCHEDULED_NON_FATAL: 2839 /* 2840 * SCSI error handler can call ->queuecommand() while UFS error 2841 * handler is in progress. Error interrupts could change the 2842 * state from UFSHCD_STATE_RESET to 2843 * UFSHCD_STATE_EH_SCHEDULED_NON_FATAL. Prevent requests 2844 * being issued in that case. 2845 */ 2846 if (ufshcd_eh_in_progress(hba)) { 2847 err = SCSI_MLQUEUE_HOST_BUSY; 2848 goto out; 2849 } 2850 break; 2851 case UFSHCD_STATE_EH_SCHEDULED_FATAL: 2852 /* 2853 * pm_runtime_get_sync() is used at error handling preparation 2854 * stage. If a scsi cmd, e.g. the SSU cmd, is sent from hba's 2855 * PM ops, it can never be finished if we let SCSI layer keep 2856 * retrying it, which gets err handler stuck forever. Neither 2857 * can we let the scsi cmd pass through, because UFS is in bad 2858 * state, the scsi cmd may eventually time out, which will get 2859 * err handler blocked for too long. So, just fail the scsi cmd 2860 * sent from PM ops, err handler can recover PM error anyways. 2861 */ 2862 if (hba->pm_op_in_progress) { 2863 hba->force_reset = true; 2864 set_host_byte(cmd, DID_BAD_TARGET); 2865 scsi_done(cmd); 2866 goto out; 2867 } 2868 fallthrough; 2869 case UFSHCD_STATE_RESET: 2870 err = SCSI_MLQUEUE_HOST_BUSY; 2871 goto out; 2872 case UFSHCD_STATE_ERROR: 2873 set_host_byte(cmd, DID_ERROR); 2874 scsi_done(cmd); 2875 goto out; 2876 } 2877 2878 hba->req_abort_count = 0; 2879 2880 ufshcd_hold(hba); 2881 2882 lrbp = &hba->lrb[tag]; 2883 lrbp->cmd = cmd; 2884 lrbp->task_tag = tag; 2885 lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun); 2886 lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba); 2887 2888 ufshcd_prepare_lrbp_crypto(scsi_cmd_to_rq(cmd), lrbp); 2889 2890 lrbp->req_abort_skip = false; 2891 2892 ufshcd_comp_scsi_upiu(hba, lrbp); 2893 2894 err = ufshcd_map_sg(hba, lrbp); 2895 if (err) { 2896 ufshcd_release(hba); 2897 goto out; 2898 } 2899 2900 if (is_mcq_enabled(hba)) 2901 hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(cmd)); 2902 2903 ufshcd_send_command(hba, tag, hwq); 2904 2905 out: 2906 if (ufs_trigger_eh()) { 2907 unsigned long flags; 2908 2909 spin_lock_irqsave(hba->host->host_lock, flags); 2910 ufshcd_schedule_eh_work(hba); 2911 spin_unlock_irqrestore(hba->host->host_lock, flags); 2912 } 2913 2914 return err; 2915 } 2916 2917 static int ufshcd_compose_dev_cmd(struct ufs_hba *hba, 2918 struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag) 2919 { 2920 lrbp->cmd = NULL; 2921 lrbp->task_tag = tag; 2922 lrbp->lun = 0; /* device management cmd is not specific to any LUN */ 2923 lrbp->intr_cmd = true; /* No interrupt aggregation */ 2924 ufshcd_prepare_lrbp_crypto(NULL, lrbp); 2925 hba->dev_cmd.type = cmd_type; 2926 2927 return ufshcd_compose_devman_upiu(hba, lrbp); 2928 } 2929 2930 /* 2931 * Check with the block layer if the command is inflight 2932 * @cmd: command to check. 2933 * 2934 * Return: true if command is inflight; false if not. 2935 */ 2936 bool ufshcd_cmd_inflight(struct scsi_cmnd *cmd) 2937 { 2938 struct request *rq; 2939 2940 if (!cmd) 2941 return false; 2942 2943 rq = scsi_cmd_to_rq(cmd); 2944 if (!blk_mq_request_started(rq)) 2945 return false; 2946 2947 return true; 2948 } 2949 2950 /* 2951 * Clear the pending command in the controller and wait until 2952 * the controller confirms that the command has been cleared. 2953 * @hba: per adapter instance 2954 * @task_tag: The tag number of the command to be cleared. 2955 */ 2956 static int ufshcd_clear_cmd(struct ufs_hba *hba, u32 task_tag) 2957 { 2958 u32 mask; 2959 unsigned long flags; 2960 int err; 2961 2962 if (is_mcq_enabled(hba)) { 2963 /* 2964 * MCQ mode. Clean up the MCQ resources similar to 2965 * what the ufshcd_utrl_clear() does for SDB mode. 2966 */ 2967 err = ufshcd_mcq_sq_cleanup(hba, task_tag); 2968 if (err) { 2969 dev_err(hba->dev, "%s: failed tag=%d. err=%d\n", 2970 __func__, task_tag, err); 2971 return err; 2972 } 2973 return 0; 2974 } 2975 2976 mask = 1U << task_tag; 2977 2978 /* clear outstanding transaction before retry */ 2979 spin_lock_irqsave(hba->host->host_lock, flags); 2980 ufshcd_utrl_clear(hba, mask); 2981 spin_unlock_irqrestore(hba->host->host_lock, flags); 2982 2983 /* 2984 * wait for h/w to clear corresponding bit in door-bell. 2985 * max. wait is 1 sec. 2986 */ 2987 return ufshcd_wait_for_register(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL, 2988 mask, ~mask, 1000, 1000); 2989 } 2990 2991 /** 2992 * ufshcd_dev_cmd_completion() - handles device management command responses 2993 * @hba: per adapter instance 2994 * @lrbp: pointer to local reference block 2995 * 2996 * Return: 0 upon success; < 0 upon failure. 2997 */ 2998 static int 2999 ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) 3000 { 3001 enum upiu_response_transaction resp; 3002 int err = 0; 3003 3004 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0); 3005 resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr); 3006 3007 switch (resp) { 3008 case UPIU_TRANSACTION_NOP_IN: 3009 if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) { 3010 err = -EINVAL; 3011 dev_err(hba->dev, "%s: unexpected response %x\n", 3012 __func__, resp); 3013 } 3014 break; 3015 case UPIU_TRANSACTION_QUERY_RSP: { 3016 u8 response = lrbp->ucd_rsp_ptr->header.response; 3017 3018 if (response == 0) 3019 err = ufshcd_copy_query_response(hba, lrbp); 3020 break; 3021 } 3022 case UPIU_TRANSACTION_REJECT_UPIU: 3023 /* TODO: handle Reject UPIU Response */ 3024 err = -EPERM; 3025 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n", 3026 __func__); 3027 break; 3028 case UPIU_TRANSACTION_RESPONSE: 3029 if (hba->dev_cmd.type != DEV_CMD_TYPE_RPMB) { 3030 err = -EINVAL; 3031 dev_err(hba->dev, "%s: unexpected response %x\n", __func__, resp); 3032 } 3033 break; 3034 default: 3035 err = -EINVAL; 3036 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n", 3037 __func__, resp); 3038 break; 3039 } 3040 3041 return err; 3042 } 3043 3044 static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba, 3045 struct ufshcd_lrb *lrbp, int max_timeout) 3046 { 3047 unsigned long time_left = msecs_to_jiffies(max_timeout); 3048 unsigned long flags; 3049 bool pending; 3050 int err; 3051 3052 retry: 3053 time_left = wait_for_completion_timeout(hba->dev_cmd.complete, 3054 time_left); 3055 3056 if (likely(time_left)) { 3057 /* 3058 * The completion handler called complete() and the caller of 3059 * this function still owns the @lrbp tag so the code below does 3060 * not trigger any race conditions. 3061 */ 3062 hba->dev_cmd.complete = NULL; 3063 err = ufshcd_get_tr_ocs(lrbp, NULL); 3064 if (!err) 3065 err = ufshcd_dev_cmd_completion(hba, lrbp); 3066 } else { 3067 err = -ETIMEDOUT; 3068 dev_dbg(hba->dev, "%s: dev_cmd request timedout, tag %d\n", 3069 __func__, lrbp->task_tag); 3070 3071 /* MCQ mode */ 3072 if (is_mcq_enabled(hba)) { 3073 /* successfully cleared the command, retry if needed */ 3074 if (ufshcd_clear_cmd(hba, lrbp->task_tag) == 0) 3075 err = -EAGAIN; 3076 hba->dev_cmd.complete = NULL; 3077 return err; 3078 } 3079 3080 /* SDB mode */ 3081 if (ufshcd_clear_cmd(hba, lrbp->task_tag) == 0) { 3082 /* successfully cleared the command, retry if needed */ 3083 err = -EAGAIN; 3084 /* 3085 * Since clearing the command succeeded we also need to 3086 * clear the task tag bit from the outstanding_reqs 3087 * variable. 3088 */ 3089 spin_lock_irqsave(&hba->outstanding_lock, flags); 3090 pending = test_bit(lrbp->task_tag, 3091 &hba->outstanding_reqs); 3092 if (pending) { 3093 hba->dev_cmd.complete = NULL; 3094 __clear_bit(lrbp->task_tag, 3095 &hba->outstanding_reqs); 3096 } 3097 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 3098 3099 if (!pending) { 3100 /* 3101 * The completion handler ran while we tried to 3102 * clear the command. 3103 */ 3104 time_left = 1; 3105 goto retry; 3106 } 3107 } else { 3108 dev_err(hba->dev, "%s: failed to clear tag %d\n", 3109 __func__, lrbp->task_tag); 3110 3111 spin_lock_irqsave(&hba->outstanding_lock, flags); 3112 pending = test_bit(lrbp->task_tag, 3113 &hba->outstanding_reqs); 3114 if (pending) 3115 hba->dev_cmd.complete = NULL; 3116 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 3117 3118 if (!pending) { 3119 /* 3120 * The completion handler ran while we tried to 3121 * clear the command. 3122 */ 3123 time_left = 1; 3124 goto retry; 3125 } 3126 } 3127 } 3128 3129 return err; 3130 } 3131 3132 /** 3133 * ufshcd_exec_dev_cmd - API for sending device management requests 3134 * @hba: UFS hba 3135 * @cmd_type: specifies the type (NOP, Query...) 3136 * @timeout: timeout in milliseconds 3137 * 3138 * Return: 0 upon success; < 0 upon failure. 3139 * 3140 * NOTE: Since there is only one available tag for device management commands, 3141 * it is expected you hold the hba->dev_cmd.lock mutex. 3142 */ 3143 static int ufshcd_exec_dev_cmd(struct ufs_hba *hba, 3144 enum dev_cmd_type cmd_type, int timeout) 3145 { 3146 DECLARE_COMPLETION_ONSTACK(wait); 3147 const u32 tag = hba->reserved_slot; 3148 struct ufshcd_lrb *lrbp; 3149 int err; 3150 3151 /* Protects use of hba->reserved_slot. */ 3152 lockdep_assert_held(&hba->dev_cmd.lock); 3153 3154 down_read(&hba->clk_scaling_lock); 3155 3156 lrbp = &hba->lrb[tag]; 3157 lrbp->cmd = NULL; 3158 err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag); 3159 if (unlikely(err)) 3160 goto out; 3161 3162 hba->dev_cmd.complete = &wait; 3163 3164 ufshcd_add_query_upiu_trace(hba, UFS_QUERY_SEND, lrbp->ucd_req_ptr); 3165 3166 ufshcd_send_command(hba, tag, hba->dev_cmd_queue); 3167 err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout); 3168 ufshcd_add_query_upiu_trace(hba, err ? UFS_QUERY_ERR : UFS_QUERY_COMP, 3169 (struct utp_upiu_req *)lrbp->ucd_rsp_ptr); 3170 3171 out: 3172 up_read(&hba->clk_scaling_lock); 3173 return err; 3174 } 3175 3176 /** 3177 * ufshcd_init_query() - init the query response and request parameters 3178 * @hba: per-adapter instance 3179 * @request: address of the request pointer to be initialized 3180 * @response: address of the response pointer to be initialized 3181 * @opcode: operation to perform 3182 * @idn: flag idn to access 3183 * @index: LU number to access 3184 * @selector: query/flag/descriptor further identification 3185 */ 3186 static inline void ufshcd_init_query(struct ufs_hba *hba, 3187 struct ufs_query_req **request, struct ufs_query_res **response, 3188 enum query_opcode opcode, u8 idn, u8 index, u8 selector) 3189 { 3190 *request = &hba->dev_cmd.query.request; 3191 *response = &hba->dev_cmd.query.response; 3192 memset(*request, 0, sizeof(struct ufs_query_req)); 3193 memset(*response, 0, sizeof(struct ufs_query_res)); 3194 (*request)->upiu_req.opcode = opcode; 3195 (*request)->upiu_req.idn = idn; 3196 (*request)->upiu_req.index = index; 3197 (*request)->upiu_req.selector = selector; 3198 } 3199 3200 static int ufshcd_query_flag_retry(struct ufs_hba *hba, 3201 enum query_opcode opcode, enum flag_idn idn, u8 index, bool *flag_res) 3202 { 3203 int ret; 3204 int retries; 3205 3206 for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) { 3207 ret = ufshcd_query_flag(hba, opcode, idn, index, flag_res); 3208 if (ret) 3209 dev_dbg(hba->dev, 3210 "%s: failed with error %d, retries %d\n", 3211 __func__, ret, retries); 3212 else 3213 break; 3214 } 3215 3216 if (ret) 3217 dev_err(hba->dev, 3218 "%s: query flag, opcode %d, idn %d, failed with error %d after %d retries\n", 3219 __func__, opcode, idn, ret, retries); 3220 return ret; 3221 } 3222 3223 /** 3224 * ufshcd_query_flag() - API function for sending flag query requests 3225 * @hba: per-adapter instance 3226 * @opcode: flag query to perform 3227 * @idn: flag idn to access 3228 * @index: flag index to access 3229 * @flag_res: the flag value after the query request completes 3230 * 3231 * Return: 0 for success, non-zero in case of failure. 3232 */ 3233 int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode, 3234 enum flag_idn idn, u8 index, bool *flag_res) 3235 { 3236 struct ufs_query_req *request = NULL; 3237 struct ufs_query_res *response = NULL; 3238 int err, selector = 0; 3239 int timeout = QUERY_REQ_TIMEOUT; 3240 3241 BUG_ON(!hba); 3242 3243 ufshcd_hold(hba); 3244 mutex_lock(&hba->dev_cmd.lock); 3245 ufshcd_init_query(hba, &request, &response, opcode, idn, index, 3246 selector); 3247 3248 switch (opcode) { 3249 case UPIU_QUERY_OPCODE_SET_FLAG: 3250 case UPIU_QUERY_OPCODE_CLEAR_FLAG: 3251 case UPIU_QUERY_OPCODE_TOGGLE_FLAG: 3252 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 3253 break; 3254 case UPIU_QUERY_OPCODE_READ_FLAG: 3255 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; 3256 if (!flag_res) { 3257 /* No dummy reads */ 3258 dev_err(hba->dev, "%s: Invalid argument for read request\n", 3259 __func__); 3260 err = -EINVAL; 3261 goto out_unlock; 3262 } 3263 break; 3264 default: 3265 dev_err(hba->dev, 3266 "%s: Expected query flag opcode but got = %d\n", 3267 __func__, opcode); 3268 err = -EINVAL; 3269 goto out_unlock; 3270 } 3271 3272 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout); 3273 3274 if (err) { 3275 dev_err(hba->dev, 3276 "%s: Sending flag query for idn %d failed, err = %d\n", 3277 __func__, idn, err); 3278 goto out_unlock; 3279 } 3280 3281 if (flag_res) 3282 *flag_res = (be32_to_cpu(response->upiu_res.value) & 3283 MASK_QUERY_UPIU_FLAG_LOC) & 0x1; 3284 3285 out_unlock: 3286 mutex_unlock(&hba->dev_cmd.lock); 3287 ufshcd_release(hba); 3288 return err; 3289 } 3290 3291 /** 3292 * ufshcd_query_attr - API function for sending attribute requests 3293 * @hba: per-adapter instance 3294 * @opcode: attribute opcode 3295 * @idn: attribute idn to access 3296 * @index: index field 3297 * @selector: selector field 3298 * @attr_val: the attribute value after the query request completes 3299 * 3300 * Return: 0 for success, non-zero in case of failure. 3301 */ 3302 int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode, 3303 enum attr_idn idn, u8 index, u8 selector, u32 *attr_val) 3304 { 3305 struct ufs_query_req *request = NULL; 3306 struct ufs_query_res *response = NULL; 3307 int err; 3308 3309 BUG_ON(!hba); 3310 3311 if (!attr_val) { 3312 dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n", 3313 __func__, opcode); 3314 return -EINVAL; 3315 } 3316 3317 ufshcd_hold(hba); 3318 3319 mutex_lock(&hba->dev_cmd.lock); 3320 ufshcd_init_query(hba, &request, &response, opcode, idn, index, 3321 selector); 3322 3323 switch (opcode) { 3324 case UPIU_QUERY_OPCODE_WRITE_ATTR: 3325 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 3326 request->upiu_req.value = cpu_to_be32(*attr_val); 3327 break; 3328 case UPIU_QUERY_OPCODE_READ_ATTR: 3329 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; 3330 break; 3331 default: 3332 dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n", 3333 __func__, opcode); 3334 err = -EINVAL; 3335 goto out_unlock; 3336 } 3337 3338 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT); 3339 3340 if (err) { 3341 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n", 3342 __func__, opcode, idn, index, err); 3343 goto out_unlock; 3344 } 3345 3346 *attr_val = be32_to_cpu(response->upiu_res.value); 3347 3348 out_unlock: 3349 mutex_unlock(&hba->dev_cmd.lock); 3350 ufshcd_release(hba); 3351 return err; 3352 } 3353 3354 /** 3355 * ufshcd_query_attr_retry() - API function for sending query 3356 * attribute with retries 3357 * @hba: per-adapter instance 3358 * @opcode: attribute opcode 3359 * @idn: attribute idn to access 3360 * @index: index field 3361 * @selector: selector field 3362 * @attr_val: the attribute value after the query request 3363 * completes 3364 * 3365 * Return: 0 for success, non-zero in case of failure. 3366 */ 3367 int ufshcd_query_attr_retry(struct ufs_hba *hba, 3368 enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector, 3369 u32 *attr_val) 3370 { 3371 int ret = 0; 3372 u32 retries; 3373 3374 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) { 3375 ret = ufshcd_query_attr(hba, opcode, idn, index, 3376 selector, attr_val); 3377 if (ret) 3378 dev_dbg(hba->dev, "%s: failed with error %d, retries %d\n", 3379 __func__, ret, retries); 3380 else 3381 break; 3382 } 3383 3384 if (ret) 3385 dev_err(hba->dev, 3386 "%s: query attribute, idn %d, failed with error %d after %d retries\n", 3387 __func__, idn, ret, QUERY_REQ_RETRIES); 3388 return ret; 3389 } 3390 3391 static int __ufshcd_query_descriptor(struct ufs_hba *hba, 3392 enum query_opcode opcode, enum desc_idn idn, u8 index, 3393 u8 selector, u8 *desc_buf, int *buf_len) 3394 { 3395 struct ufs_query_req *request = NULL; 3396 struct ufs_query_res *response = NULL; 3397 int err; 3398 3399 BUG_ON(!hba); 3400 3401 if (!desc_buf) { 3402 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n", 3403 __func__, opcode); 3404 return -EINVAL; 3405 } 3406 3407 if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) { 3408 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n", 3409 __func__, *buf_len); 3410 return -EINVAL; 3411 } 3412 3413 ufshcd_hold(hba); 3414 3415 mutex_lock(&hba->dev_cmd.lock); 3416 ufshcd_init_query(hba, &request, &response, opcode, idn, index, 3417 selector); 3418 hba->dev_cmd.query.descriptor = desc_buf; 3419 request->upiu_req.length = cpu_to_be16(*buf_len); 3420 3421 switch (opcode) { 3422 case UPIU_QUERY_OPCODE_WRITE_DESC: 3423 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 3424 break; 3425 case UPIU_QUERY_OPCODE_READ_DESC: 3426 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; 3427 break; 3428 default: 3429 dev_err(hba->dev, 3430 "%s: Expected query descriptor opcode but got = 0x%.2x\n", 3431 __func__, opcode); 3432 err = -EINVAL; 3433 goto out_unlock; 3434 } 3435 3436 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT); 3437 3438 if (err) { 3439 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n", 3440 __func__, opcode, idn, index, err); 3441 goto out_unlock; 3442 } 3443 3444 *buf_len = be16_to_cpu(response->upiu_res.length); 3445 3446 out_unlock: 3447 hba->dev_cmd.query.descriptor = NULL; 3448 mutex_unlock(&hba->dev_cmd.lock); 3449 ufshcd_release(hba); 3450 return err; 3451 } 3452 3453 /** 3454 * ufshcd_query_descriptor_retry - API function for sending descriptor requests 3455 * @hba: per-adapter instance 3456 * @opcode: attribute opcode 3457 * @idn: attribute idn to access 3458 * @index: index field 3459 * @selector: selector field 3460 * @desc_buf: the buffer that contains the descriptor 3461 * @buf_len: length parameter passed to the device 3462 * 3463 * The buf_len parameter will contain, on return, the length parameter 3464 * received on the response. 3465 * 3466 * Return: 0 for success, non-zero in case of failure. 3467 */ 3468 int ufshcd_query_descriptor_retry(struct ufs_hba *hba, 3469 enum query_opcode opcode, 3470 enum desc_idn idn, u8 index, 3471 u8 selector, 3472 u8 *desc_buf, int *buf_len) 3473 { 3474 int err; 3475 int retries; 3476 3477 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) { 3478 err = __ufshcd_query_descriptor(hba, opcode, idn, index, 3479 selector, desc_buf, buf_len); 3480 if (!err || err == -EINVAL) 3481 break; 3482 } 3483 3484 return err; 3485 } 3486 3487 /** 3488 * ufshcd_read_desc_param - read the specified descriptor parameter 3489 * @hba: Pointer to adapter instance 3490 * @desc_id: descriptor idn value 3491 * @desc_index: descriptor index 3492 * @param_offset: offset of the parameter to read 3493 * @param_read_buf: pointer to buffer where parameter would be read 3494 * @param_size: sizeof(param_read_buf) 3495 * 3496 * Return: 0 in case of success, non-zero otherwise. 3497 */ 3498 int ufshcd_read_desc_param(struct ufs_hba *hba, 3499 enum desc_idn desc_id, 3500 int desc_index, 3501 u8 param_offset, 3502 u8 *param_read_buf, 3503 u8 param_size) 3504 { 3505 int ret; 3506 u8 *desc_buf; 3507 int buff_len = QUERY_DESC_MAX_SIZE; 3508 bool is_kmalloc = true; 3509 3510 /* Safety check */ 3511 if (desc_id >= QUERY_DESC_IDN_MAX || !param_size) 3512 return -EINVAL; 3513 3514 /* Check whether we need temp memory */ 3515 if (param_offset != 0 || param_size < buff_len) { 3516 desc_buf = kzalloc(buff_len, GFP_KERNEL); 3517 if (!desc_buf) 3518 return -ENOMEM; 3519 } else { 3520 desc_buf = param_read_buf; 3521 is_kmalloc = false; 3522 } 3523 3524 /* Request for full descriptor */ 3525 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC, 3526 desc_id, desc_index, 0, 3527 desc_buf, &buff_len); 3528 if (ret) { 3529 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d\n", 3530 __func__, desc_id, desc_index, param_offset, ret); 3531 goto out; 3532 } 3533 3534 /* Update descriptor length */ 3535 buff_len = desc_buf[QUERY_DESC_LENGTH_OFFSET]; 3536 3537 if (param_offset >= buff_len) { 3538 dev_err(hba->dev, "%s: Invalid offset 0x%x in descriptor IDN 0x%x, length 0x%x\n", 3539 __func__, param_offset, desc_id, buff_len); 3540 ret = -EINVAL; 3541 goto out; 3542 } 3543 3544 /* Sanity check */ 3545 if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) { 3546 dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header\n", 3547 __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]); 3548 ret = -EINVAL; 3549 goto out; 3550 } 3551 3552 if (is_kmalloc) { 3553 /* Make sure we don't copy more data than available */ 3554 if (param_offset >= buff_len) 3555 ret = -EINVAL; 3556 else 3557 memcpy(param_read_buf, &desc_buf[param_offset], 3558 min_t(u32, param_size, buff_len - param_offset)); 3559 } 3560 out: 3561 if (is_kmalloc) 3562 kfree(desc_buf); 3563 return ret; 3564 } 3565 3566 /** 3567 * struct uc_string_id - unicode string 3568 * 3569 * @len: size of this descriptor inclusive 3570 * @type: descriptor type 3571 * @uc: unicode string character 3572 */ 3573 struct uc_string_id { 3574 u8 len; 3575 u8 type; 3576 wchar_t uc[]; 3577 } __packed; 3578 3579 /* replace non-printable or non-ASCII characters with spaces */ 3580 static inline char ufshcd_remove_non_printable(u8 ch) 3581 { 3582 return (ch >= 0x20 && ch <= 0x7e) ? ch : ' '; 3583 } 3584 3585 /** 3586 * ufshcd_read_string_desc - read string descriptor 3587 * @hba: pointer to adapter instance 3588 * @desc_index: descriptor index 3589 * @buf: pointer to buffer where descriptor would be read, 3590 * the caller should free the memory. 3591 * @ascii: if true convert from unicode to ascii characters 3592 * null terminated string. 3593 * 3594 * Return: 3595 * * string size on success. 3596 * * -ENOMEM: on allocation failure 3597 * * -EINVAL: on a wrong parameter 3598 */ 3599 int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index, 3600 u8 **buf, bool ascii) 3601 { 3602 struct uc_string_id *uc_str; 3603 u8 *str; 3604 int ret; 3605 3606 if (!buf) 3607 return -EINVAL; 3608 3609 uc_str = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL); 3610 if (!uc_str) 3611 return -ENOMEM; 3612 3613 ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_STRING, desc_index, 0, 3614 (u8 *)uc_str, QUERY_DESC_MAX_SIZE); 3615 if (ret < 0) { 3616 dev_err(hba->dev, "Reading String Desc failed after %d retries. err = %d\n", 3617 QUERY_REQ_RETRIES, ret); 3618 str = NULL; 3619 goto out; 3620 } 3621 3622 if (uc_str->len <= QUERY_DESC_HDR_SIZE) { 3623 dev_dbg(hba->dev, "String Desc is of zero length\n"); 3624 str = NULL; 3625 ret = 0; 3626 goto out; 3627 } 3628 3629 if (ascii) { 3630 ssize_t ascii_len; 3631 int i; 3632 /* remove header and divide by 2 to move from UTF16 to UTF8 */ 3633 ascii_len = (uc_str->len - QUERY_DESC_HDR_SIZE) / 2 + 1; 3634 str = kzalloc(ascii_len, GFP_KERNEL); 3635 if (!str) { 3636 ret = -ENOMEM; 3637 goto out; 3638 } 3639 3640 /* 3641 * the descriptor contains string in UTF16 format 3642 * we need to convert to utf-8 so it can be displayed 3643 */ 3644 ret = utf16s_to_utf8s(uc_str->uc, 3645 uc_str->len - QUERY_DESC_HDR_SIZE, 3646 UTF16_BIG_ENDIAN, str, ascii_len - 1); 3647 3648 /* replace non-printable or non-ASCII characters with spaces */ 3649 for (i = 0; i < ret; i++) 3650 str[i] = ufshcd_remove_non_printable(str[i]); 3651 3652 str[ret++] = '\0'; 3653 3654 } else { 3655 str = kmemdup(uc_str, uc_str->len, GFP_KERNEL); 3656 if (!str) { 3657 ret = -ENOMEM; 3658 goto out; 3659 } 3660 ret = uc_str->len; 3661 } 3662 out: 3663 *buf = str; 3664 kfree(uc_str); 3665 return ret; 3666 } 3667 3668 /** 3669 * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter 3670 * @hba: Pointer to adapter instance 3671 * @lun: lun id 3672 * @param_offset: offset of the parameter to read 3673 * @param_read_buf: pointer to buffer where parameter would be read 3674 * @param_size: sizeof(param_read_buf) 3675 * 3676 * Return: 0 in case of success, non-zero otherwise. 3677 */ 3678 static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba, 3679 int lun, 3680 enum unit_desc_param param_offset, 3681 u8 *param_read_buf, 3682 u32 param_size) 3683 { 3684 /* 3685 * Unit descriptors are only available for general purpose LUs (LUN id 3686 * from 0 to 7) and RPMB Well known LU. 3687 */ 3688 if (!ufs_is_valid_unit_desc_lun(&hba->dev_info, lun)) 3689 return -EOPNOTSUPP; 3690 3691 return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun, 3692 param_offset, param_read_buf, param_size); 3693 } 3694 3695 static int ufshcd_get_ref_clk_gating_wait(struct ufs_hba *hba) 3696 { 3697 int err = 0; 3698 u32 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US; 3699 3700 if (hba->dev_info.wspecversion >= 0x300) { 3701 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 3702 QUERY_ATTR_IDN_REF_CLK_GATING_WAIT_TIME, 0, 0, 3703 &gating_wait); 3704 if (err) 3705 dev_err(hba->dev, "Failed reading bRefClkGatingWait. err = %d, use default %uus\n", 3706 err, gating_wait); 3707 3708 if (gating_wait == 0) { 3709 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US; 3710 dev_err(hba->dev, "Undefined ref clk gating wait time, use default %uus\n", 3711 gating_wait); 3712 } 3713 3714 hba->dev_info.clk_gating_wait_us = gating_wait; 3715 } 3716 3717 return err; 3718 } 3719 3720 /** 3721 * ufshcd_memory_alloc - allocate memory for host memory space data structures 3722 * @hba: per adapter instance 3723 * 3724 * 1. Allocate DMA memory for Command Descriptor array 3725 * Each command descriptor consist of Command UPIU, Response UPIU and PRDT 3726 * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL). 3727 * 3. Allocate DMA memory for UTP Task Management Request Descriptor List 3728 * (UTMRDL) 3729 * 4. Allocate memory for local reference block(lrb). 3730 * 3731 * Return: 0 for success, non-zero in case of failure. 3732 */ 3733 static int ufshcd_memory_alloc(struct ufs_hba *hba) 3734 { 3735 size_t utmrdl_size, utrdl_size, ucdl_size; 3736 3737 /* Allocate memory for UTP command descriptors */ 3738 ucdl_size = ufshcd_get_ucd_size(hba) * hba->nutrs; 3739 hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev, 3740 ucdl_size, 3741 &hba->ucdl_dma_addr, 3742 GFP_KERNEL); 3743 3744 /* 3745 * UFSHCI requires UTP command descriptor to be 128 byte aligned. 3746 */ 3747 if (!hba->ucdl_base_addr || 3748 WARN_ON(hba->ucdl_dma_addr & (128 - 1))) { 3749 dev_err(hba->dev, 3750 "Command Descriptor Memory allocation failed\n"); 3751 goto out; 3752 } 3753 3754 /* 3755 * Allocate memory for UTP Transfer descriptors 3756 * UFSHCI requires 1KB alignment of UTRD 3757 */ 3758 utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs); 3759 hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev, 3760 utrdl_size, 3761 &hba->utrdl_dma_addr, 3762 GFP_KERNEL); 3763 if (!hba->utrdl_base_addr || 3764 WARN_ON(hba->utrdl_dma_addr & (SZ_1K - 1))) { 3765 dev_err(hba->dev, 3766 "Transfer Descriptor Memory allocation failed\n"); 3767 goto out; 3768 } 3769 3770 /* 3771 * Skip utmrdl allocation; it may have been 3772 * allocated during first pass and not released during 3773 * MCQ memory allocation. 3774 * See ufshcd_release_sdb_queue() and ufshcd_config_mcq() 3775 */ 3776 if (hba->utmrdl_base_addr) 3777 goto skip_utmrdl; 3778 /* 3779 * Allocate memory for UTP Task Management descriptors 3780 * UFSHCI requires 1KB alignment of UTMRD 3781 */ 3782 utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs; 3783 hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev, 3784 utmrdl_size, 3785 &hba->utmrdl_dma_addr, 3786 GFP_KERNEL); 3787 if (!hba->utmrdl_base_addr || 3788 WARN_ON(hba->utmrdl_dma_addr & (SZ_1K - 1))) { 3789 dev_err(hba->dev, 3790 "Task Management Descriptor Memory allocation failed\n"); 3791 goto out; 3792 } 3793 3794 skip_utmrdl: 3795 /* Allocate memory for local reference block */ 3796 hba->lrb = devm_kcalloc(hba->dev, 3797 hba->nutrs, sizeof(struct ufshcd_lrb), 3798 GFP_KERNEL); 3799 if (!hba->lrb) { 3800 dev_err(hba->dev, "LRB Memory allocation failed\n"); 3801 goto out; 3802 } 3803 return 0; 3804 out: 3805 return -ENOMEM; 3806 } 3807 3808 /** 3809 * ufshcd_host_memory_configure - configure local reference block with 3810 * memory offsets 3811 * @hba: per adapter instance 3812 * 3813 * Configure Host memory space 3814 * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA 3815 * address. 3816 * 2. Update each UTRD with Response UPIU offset, Response UPIU length 3817 * and PRDT offset. 3818 * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT 3819 * into local reference block. 3820 */ 3821 static void ufshcd_host_memory_configure(struct ufs_hba *hba) 3822 { 3823 struct utp_transfer_req_desc *utrdlp; 3824 dma_addr_t cmd_desc_dma_addr; 3825 dma_addr_t cmd_desc_element_addr; 3826 u16 response_offset; 3827 u16 prdt_offset; 3828 int cmd_desc_size; 3829 int i; 3830 3831 utrdlp = hba->utrdl_base_addr; 3832 3833 response_offset = 3834 offsetof(struct utp_transfer_cmd_desc, response_upiu); 3835 prdt_offset = 3836 offsetof(struct utp_transfer_cmd_desc, prd_table); 3837 3838 cmd_desc_size = ufshcd_get_ucd_size(hba); 3839 cmd_desc_dma_addr = hba->ucdl_dma_addr; 3840 3841 for (i = 0; i < hba->nutrs; i++) { 3842 /* Configure UTRD with command descriptor base address */ 3843 cmd_desc_element_addr = 3844 (cmd_desc_dma_addr + (cmd_desc_size * i)); 3845 utrdlp[i].command_desc_base_addr = 3846 cpu_to_le64(cmd_desc_element_addr); 3847 3848 /* Response upiu and prdt offset should be in double words */ 3849 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) { 3850 utrdlp[i].response_upiu_offset = 3851 cpu_to_le16(response_offset); 3852 utrdlp[i].prd_table_offset = 3853 cpu_to_le16(prdt_offset); 3854 utrdlp[i].response_upiu_length = 3855 cpu_to_le16(ALIGNED_UPIU_SIZE); 3856 } else { 3857 utrdlp[i].response_upiu_offset = 3858 cpu_to_le16(response_offset >> 2); 3859 utrdlp[i].prd_table_offset = 3860 cpu_to_le16(prdt_offset >> 2); 3861 utrdlp[i].response_upiu_length = 3862 cpu_to_le16(ALIGNED_UPIU_SIZE >> 2); 3863 } 3864 3865 ufshcd_init_lrb(hba, &hba->lrb[i], i); 3866 } 3867 } 3868 3869 /** 3870 * ufshcd_dme_link_startup - Notify Unipro to perform link startup 3871 * @hba: per adapter instance 3872 * 3873 * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer, 3874 * in order to initialize the Unipro link startup procedure. 3875 * Once the Unipro links are up, the device connected to the controller 3876 * is detected. 3877 * 3878 * Return: 0 on success, non-zero value on failure. 3879 */ 3880 static int ufshcd_dme_link_startup(struct ufs_hba *hba) 3881 { 3882 struct uic_command uic_cmd = {0}; 3883 int ret; 3884 3885 uic_cmd.command = UIC_CMD_DME_LINK_STARTUP; 3886 3887 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 3888 if (ret) 3889 dev_dbg(hba->dev, 3890 "dme-link-startup: error code %d\n", ret); 3891 return ret; 3892 } 3893 /** 3894 * ufshcd_dme_reset - UIC command for DME_RESET 3895 * @hba: per adapter instance 3896 * 3897 * DME_RESET command is issued in order to reset UniPro stack. 3898 * This function now deals with cold reset. 3899 * 3900 * Return: 0 on success, non-zero value on failure. 3901 */ 3902 static int ufshcd_dme_reset(struct ufs_hba *hba) 3903 { 3904 struct uic_command uic_cmd = {0}; 3905 int ret; 3906 3907 uic_cmd.command = UIC_CMD_DME_RESET; 3908 3909 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 3910 if (ret) 3911 dev_err(hba->dev, 3912 "dme-reset: error code %d\n", ret); 3913 3914 return ret; 3915 } 3916 3917 int ufshcd_dme_configure_adapt(struct ufs_hba *hba, 3918 int agreed_gear, 3919 int adapt_val) 3920 { 3921 int ret; 3922 3923 if (agreed_gear < UFS_HS_G4) 3924 adapt_val = PA_NO_ADAPT; 3925 3926 ret = ufshcd_dme_set(hba, 3927 UIC_ARG_MIB(PA_TXHSADAPTTYPE), 3928 adapt_val); 3929 return ret; 3930 } 3931 EXPORT_SYMBOL_GPL(ufshcd_dme_configure_adapt); 3932 3933 /** 3934 * ufshcd_dme_enable - UIC command for DME_ENABLE 3935 * @hba: per adapter instance 3936 * 3937 * DME_ENABLE command is issued in order to enable UniPro stack. 3938 * 3939 * Return: 0 on success, non-zero value on failure. 3940 */ 3941 static int ufshcd_dme_enable(struct ufs_hba *hba) 3942 { 3943 struct uic_command uic_cmd = {0}; 3944 int ret; 3945 3946 uic_cmd.command = UIC_CMD_DME_ENABLE; 3947 3948 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 3949 if (ret) 3950 dev_err(hba->dev, 3951 "dme-enable: error code %d\n", ret); 3952 3953 return ret; 3954 } 3955 3956 static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba) 3957 { 3958 #define MIN_DELAY_BEFORE_DME_CMDS_US 1000 3959 unsigned long min_sleep_time_us; 3960 3961 if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS)) 3962 return; 3963 3964 /* 3965 * last_dme_cmd_tstamp will be 0 only for 1st call to 3966 * this function 3967 */ 3968 if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) { 3969 min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US; 3970 } else { 3971 unsigned long delta = 3972 (unsigned long) ktime_to_us( 3973 ktime_sub(ktime_get(), 3974 hba->last_dme_cmd_tstamp)); 3975 3976 if (delta < MIN_DELAY_BEFORE_DME_CMDS_US) 3977 min_sleep_time_us = 3978 MIN_DELAY_BEFORE_DME_CMDS_US - delta; 3979 else 3980 min_sleep_time_us = 0; /* no more delay required */ 3981 } 3982 3983 if (min_sleep_time_us > 0) { 3984 /* allow sleep for extra 50us if needed */ 3985 usleep_range(min_sleep_time_us, min_sleep_time_us + 50); 3986 } 3987 3988 /* update the last_dme_cmd_tstamp */ 3989 hba->last_dme_cmd_tstamp = ktime_get(); 3990 } 3991 3992 /** 3993 * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET 3994 * @hba: per adapter instance 3995 * @attr_sel: uic command argument1 3996 * @attr_set: attribute set type as uic command argument2 3997 * @mib_val: setting value as uic command argument3 3998 * @peer: indicate whether peer or local 3999 * 4000 * Return: 0 on success, non-zero value on failure. 4001 */ 4002 int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel, 4003 u8 attr_set, u32 mib_val, u8 peer) 4004 { 4005 struct uic_command uic_cmd = {0}; 4006 static const char *const action[] = { 4007 "dme-set", 4008 "dme-peer-set" 4009 }; 4010 const char *set = action[!!peer]; 4011 int ret; 4012 int retries = UFS_UIC_COMMAND_RETRIES; 4013 4014 uic_cmd.command = peer ? 4015 UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET; 4016 uic_cmd.argument1 = attr_sel; 4017 uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set); 4018 uic_cmd.argument3 = mib_val; 4019 4020 do { 4021 /* for peer attributes we retry upon failure */ 4022 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 4023 if (ret) 4024 dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n", 4025 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret); 4026 } while (ret && peer && --retries); 4027 4028 if (ret) 4029 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n", 4030 set, UIC_GET_ATTR_ID(attr_sel), mib_val, 4031 UFS_UIC_COMMAND_RETRIES - retries); 4032 4033 return ret; 4034 } 4035 EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr); 4036 4037 /** 4038 * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET 4039 * @hba: per adapter instance 4040 * @attr_sel: uic command argument1 4041 * @mib_val: the value of the attribute as returned by the UIC command 4042 * @peer: indicate whether peer or local 4043 * 4044 * Return: 0 on success, non-zero value on failure. 4045 */ 4046 int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel, 4047 u32 *mib_val, u8 peer) 4048 { 4049 struct uic_command uic_cmd = {0}; 4050 static const char *const action[] = { 4051 "dme-get", 4052 "dme-peer-get" 4053 }; 4054 const char *get = action[!!peer]; 4055 int ret; 4056 int retries = UFS_UIC_COMMAND_RETRIES; 4057 struct ufs_pa_layer_attr orig_pwr_info; 4058 struct ufs_pa_layer_attr temp_pwr_info; 4059 bool pwr_mode_change = false; 4060 4061 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) { 4062 orig_pwr_info = hba->pwr_info; 4063 temp_pwr_info = orig_pwr_info; 4064 4065 if (orig_pwr_info.pwr_tx == FAST_MODE || 4066 orig_pwr_info.pwr_rx == FAST_MODE) { 4067 temp_pwr_info.pwr_tx = FASTAUTO_MODE; 4068 temp_pwr_info.pwr_rx = FASTAUTO_MODE; 4069 pwr_mode_change = true; 4070 } else if (orig_pwr_info.pwr_tx == SLOW_MODE || 4071 orig_pwr_info.pwr_rx == SLOW_MODE) { 4072 temp_pwr_info.pwr_tx = SLOWAUTO_MODE; 4073 temp_pwr_info.pwr_rx = SLOWAUTO_MODE; 4074 pwr_mode_change = true; 4075 } 4076 if (pwr_mode_change) { 4077 ret = ufshcd_change_power_mode(hba, &temp_pwr_info); 4078 if (ret) 4079 goto out; 4080 } 4081 } 4082 4083 uic_cmd.command = peer ? 4084 UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET; 4085 uic_cmd.argument1 = attr_sel; 4086 4087 do { 4088 /* for peer attributes we retry upon failure */ 4089 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 4090 if (ret) 4091 dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n", 4092 get, UIC_GET_ATTR_ID(attr_sel), ret); 4093 } while (ret && peer && --retries); 4094 4095 if (ret) 4096 dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n", 4097 get, UIC_GET_ATTR_ID(attr_sel), 4098 UFS_UIC_COMMAND_RETRIES - retries); 4099 4100 if (mib_val && !ret) 4101 *mib_val = uic_cmd.argument3; 4102 4103 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE) 4104 && pwr_mode_change) 4105 ufshcd_change_power_mode(hba, &orig_pwr_info); 4106 out: 4107 return ret; 4108 } 4109 EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr); 4110 4111 /** 4112 * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power 4113 * state) and waits for it to take effect. 4114 * 4115 * @hba: per adapter instance 4116 * @cmd: UIC command to execute 4117 * 4118 * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER & 4119 * DME_HIBERNATE_EXIT commands take some time to take its effect on both host 4120 * and device UniPro link and hence it's final completion would be indicated by 4121 * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in 4122 * addition to normal UIC command completion Status (UCCS). This function only 4123 * returns after the relevant status bits indicate the completion. 4124 * 4125 * Return: 0 on success, non-zero value on failure. 4126 */ 4127 static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd) 4128 { 4129 DECLARE_COMPLETION_ONSTACK(uic_async_done); 4130 unsigned long flags; 4131 u8 status; 4132 int ret; 4133 bool reenable_intr = false; 4134 4135 mutex_lock(&hba->uic_cmd_mutex); 4136 ufshcd_add_delay_before_dme_cmd(hba); 4137 4138 spin_lock_irqsave(hba->host->host_lock, flags); 4139 if (ufshcd_is_link_broken(hba)) { 4140 ret = -ENOLINK; 4141 goto out_unlock; 4142 } 4143 hba->uic_async_done = &uic_async_done; 4144 if (ufshcd_readl(hba, REG_INTERRUPT_ENABLE) & UIC_COMMAND_COMPL) { 4145 ufshcd_disable_intr(hba, UIC_COMMAND_COMPL); 4146 /* 4147 * Make sure UIC command completion interrupt is disabled before 4148 * issuing UIC command. 4149 */ 4150 ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 4151 reenable_intr = true; 4152 } 4153 spin_unlock_irqrestore(hba->host->host_lock, flags); 4154 ret = __ufshcd_send_uic_cmd(hba, cmd); 4155 if (ret) { 4156 dev_err(hba->dev, 4157 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n", 4158 cmd->command, cmd->argument3, ret); 4159 goto out; 4160 } 4161 4162 if (!wait_for_completion_timeout(hba->uic_async_done, 4163 msecs_to_jiffies(UIC_CMD_TIMEOUT))) { 4164 dev_err(hba->dev, 4165 "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n", 4166 cmd->command, cmd->argument3); 4167 4168 if (!cmd->cmd_active) { 4169 dev_err(hba->dev, "%s: Power Mode Change operation has been completed, go check UPMCRS\n", 4170 __func__); 4171 goto check_upmcrs; 4172 } 4173 4174 ret = -ETIMEDOUT; 4175 goto out; 4176 } 4177 4178 check_upmcrs: 4179 status = ufshcd_get_upmcrs(hba); 4180 if (status != PWR_LOCAL) { 4181 dev_err(hba->dev, 4182 "pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n", 4183 cmd->command, status); 4184 ret = (status != PWR_OK) ? status : -1; 4185 } 4186 out: 4187 if (ret) { 4188 ufshcd_print_host_state(hba); 4189 ufshcd_print_pwr_info(hba); 4190 ufshcd_print_evt_hist(hba); 4191 } 4192 4193 spin_lock_irqsave(hba->host->host_lock, flags); 4194 hba->active_uic_cmd = NULL; 4195 hba->uic_async_done = NULL; 4196 if (reenable_intr) 4197 ufshcd_enable_intr(hba, UIC_COMMAND_COMPL); 4198 if (ret) { 4199 ufshcd_set_link_broken(hba); 4200 ufshcd_schedule_eh_work(hba); 4201 } 4202 out_unlock: 4203 spin_unlock_irqrestore(hba->host->host_lock, flags); 4204 mutex_unlock(&hba->uic_cmd_mutex); 4205 4206 return ret; 4207 } 4208 4209 /** 4210 * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage 4211 * using DME_SET primitives. 4212 * @hba: per adapter instance 4213 * @mode: powr mode value 4214 * 4215 * Return: 0 on success, non-zero value on failure. 4216 */ 4217 int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode) 4218 { 4219 struct uic_command uic_cmd = {0}; 4220 int ret; 4221 4222 if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) { 4223 ret = ufshcd_dme_set(hba, 4224 UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1); 4225 if (ret) { 4226 dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n", 4227 __func__, ret); 4228 goto out; 4229 } 4230 } 4231 4232 uic_cmd.command = UIC_CMD_DME_SET; 4233 uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE); 4234 uic_cmd.argument3 = mode; 4235 ufshcd_hold(hba); 4236 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd); 4237 ufshcd_release(hba); 4238 4239 out: 4240 return ret; 4241 } 4242 EXPORT_SYMBOL_GPL(ufshcd_uic_change_pwr_mode); 4243 4244 int ufshcd_link_recovery(struct ufs_hba *hba) 4245 { 4246 int ret; 4247 unsigned long flags; 4248 4249 spin_lock_irqsave(hba->host->host_lock, flags); 4250 hba->ufshcd_state = UFSHCD_STATE_RESET; 4251 ufshcd_set_eh_in_progress(hba); 4252 spin_unlock_irqrestore(hba->host->host_lock, flags); 4253 4254 /* Reset the attached device */ 4255 ufshcd_device_reset(hba); 4256 4257 ret = ufshcd_host_reset_and_restore(hba); 4258 4259 spin_lock_irqsave(hba->host->host_lock, flags); 4260 if (ret) 4261 hba->ufshcd_state = UFSHCD_STATE_ERROR; 4262 ufshcd_clear_eh_in_progress(hba); 4263 spin_unlock_irqrestore(hba->host->host_lock, flags); 4264 4265 if (ret) 4266 dev_err(hba->dev, "%s: link recovery failed, err %d", 4267 __func__, ret); 4268 4269 return ret; 4270 } 4271 EXPORT_SYMBOL_GPL(ufshcd_link_recovery); 4272 4273 int ufshcd_uic_hibern8_enter(struct ufs_hba *hba) 4274 { 4275 int ret; 4276 struct uic_command uic_cmd = {0}; 4277 ktime_t start = ktime_get(); 4278 4279 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, PRE_CHANGE); 4280 4281 uic_cmd.command = UIC_CMD_DME_HIBER_ENTER; 4282 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd); 4283 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "enter", 4284 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 4285 4286 if (ret) 4287 dev_err(hba->dev, "%s: hibern8 enter failed. ret = %d\n", 4288 __func__, ret); 4289 else 4290 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, 4291 POST_CHANGE); 4292 4293 return ret; 4294 } 4295 EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_enter); 4296 4297 int ufshcd_uic_hibern8_exit(struct ufs_hba *hba) 4298 { 4299 struct uic_command uic_cmd = {0}; 4300 int ret; 4301 ktime_t start = ktime_get(); 4302 4303 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, PRE_CHANGE); 4304 4305 uic_cmd.command = UIC_CMD_DME_HIBER_EXIT; 4306 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd); 4307 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "exit", 4308 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 4309 4310 if (ret) { 4311 dev_err(hba->dev, "%s: hibern8 exit failed. ret = %d\n", 4312 __func__, ret); 4313 } else { 4314 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, 4315 POST_CHANGE); 4316 hba->ufs_stats.last_hibern8_exit_tstamp = local_clock(); 4317 hba->ufs_stats.hibern8_exit_cnt++; 4318 } 4319 4320 return ret; 4321 } 4322 EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_exit); 4323 4324 void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit) 4325 { 4326 unsigned long flags; 4327 bool update = false; 4328 4329 if (!ufshcd_is_auto_hibern8_supported(hba)) 4330 return; 4331 4332 spin_lock_irqsave(hba->host->host_lock, flags); 4333 if (hba->ahit != ahit) { 4334 hba->ahit = ahit; 4335 update = true; 4336 } 4337 spin_unlock_irqrestore(hba->host->host_lock, flags); 4338 4339 if (update && 4340 !pm_runtime_suspended(&hba->ufs_device_wlun->sdev_gendev)) { 4341 ufshcd_rpm_get_sync(hba); 4342 ufshcd_hold(hba); 4343 ufshcd_auto_hibern8_enable(hba); 4344 ufshcd_release(hba); 4345 ufshcd_rpm_put_sync(hba); 4346 } 4347 } 4348 EXPORT_SYMBOL_GPL(ufshcd_auto_hibern8_update); 4349 4350 void ufshcd_auto_hibern8_enable(struct ufs_hba *hba) 4351 { 4352 if (!ufshcd_is_auto_hibern8_supported(hba)) 4353 return; 4354 4355 ufshcd_writel(hba, hba->ahit, REG_AUTO_HIBERNATE_IDLE_TIMER); 4356 } 4357 4358 /** 4359 * ufshcd_init_pwr_info - setting the POR (power on reset) 4360 * values in hba power info 4361 * @hba: per-adapter instance 4362 */ 4363 static void ufshcd_init_pwr_info(struct ufs_hba *hba) 4364 { 4365 hba->pwr_info.gear_rx = UFS_PWM_G1; 4366 hba->pwr_info.gear_tx = UFS_PWM_G1; 4367 hba->pwr_info.lane_rx = UFS_LANE_1; 4368 hba->pwr_info.lane_tx = UFS_LANE_1; 4369 hba->pwr_info.pwr_rx = SLOWAUTO_MODE; 4370 hba->pwr_info.pwr_tx = SLOWAUTO_MODE; 4371 hba->pwr_info.hs_rate = 0; 4372 } 4373 4374 /** 4375 * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device 4376 * @hba: per-adapter instance 4377 * 4378 * Return: 0 upon success; < 0 upon failure. 4379 */ 4380 static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba) 4381 { 4382 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info; 4383 4384 if (hba->max_pwr_info.is_valid) 4385 return 0; 4386 4387 if (hba->quirks & UFSHCD_QUIRK_HIBERN_FASTAUTO) { 4388 pwr_info->pwr_tx = FASTAUTO_MODE; 4389 pwr_info->pwr_rx = FASTAUTO_MODE; 4390 } else { 4391 pwr_info->pwr_tx = FAST_MODE; 4392 pwr_info->pwr_rx = FAST_MODE; 4393 } 4394 pwr_info->hs_rate = PA_HS_MODE_B; 4395 4396 /* Get the connected lane count */ 4397 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES), 4398 &pwr_info->lane_rx); 4399 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 4400 &pwr_info->lane_tx); 4401 4402 if (!pwr_info->lane_rx || !pwr_info->lane_tx) { 4403 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n", 4404 __func__, 4405 pwr_info->lane_rx, 4406 pwr_info->lane_tx); 4407 return -EINVAL; 4408 } 4409 4410 /* 4411 * First, get the maximum gears of HS speed. 4412 * If a zero value, it means there is no HSGEAR capability. 4413 * Then, get the maximum gears of PWM speed. 4414 */ 4415 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx); 4416 if (!pwr_info->gear_rx) { 4417 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR), 4418 &pwr_info->gear_rx); 4419 if (!pwr_info->gear_rx) { 4420 dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n", 4421 __func__, pwr_info->gear_rx); 4422 return -EINVAL; 4423 } 4424 pwr_info->pwr_rx = SLOW_MODE; 4425 } 4426 4427 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), 4428 &pwr_info->gear_tx); 4429 if (!pwr_info->gear_tx) { 4430 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR), 4431 &pwr_info->gear_tx); 4432 if (!pwr_info->gear_tx) { 4433 dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n", 4434 __func__, pwr_info->gear_tx); 4435 return -EINVAL; 4436 } 4437 pwr_info->pwr_tx = SLOW_MODE; 4438 } 4439 4440 hba->max_pwr_info.is_valid = true; 4441 return 0; 4442 } 4443 4444 static int ufshcd_change_power_mode(struct ufs_hba *hba, 4445 struct ufs_pa_layer_attr *pwr_mode) 4446 { 4447 int ret; 4448 4449 /* if already configured to the requested pwr_mode */ 4450 if (!hba->force_pmc && 4451 pwr_mode->gear_rx == hba->pwr_info.gear_rx && 4452 pwr_mode->gear_tx == hba->pwr_info.gear_tx && 4453 pwr_mode->lane_rx == hba->pwr_info.lane_rx && 4454 pwr_mode->lane_tx == hba->pwr_info.lane_tx && 4455 pwr_mode->pwr_rx == hba->pwr_info.pwr_rx && 4456 pwr_mode->pwr_tx == hba->pwr_info.pwr_tx && 4457 pwr_mode->hs_rate == hba->pwr_info.hs_rate) { 4458 dev_dbg(hba->dev, "%s: power already configured\n", __func__); 4459 return 0; 4460 } 4461 4462 /* 4463 * Configure attributes for power mode change with below. 4464 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION, 4465 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION, 4466 * - PA_HSSERIES 4467 */ 4468 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx); 4469 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES), 4470 pwr_mode->lane_rx); 4471 if (pwr_mode->pwr_rx == FASTAUTO_MODE || 4472 pwr_mode->pwr_rx == FAST_MODE) 4473 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), true); 4474 else 4475 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), false); 4476 4477 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx); 4478 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES), 4479 pwr_mode->lane_tx); 4480 if (pwr_mode->pwr_tx == FASTAUTO_MODE || 4481 pwr_mode->pwr_tx == FAST_MODE) 4482 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), true); 4483 else 4484 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), false); 4485 4486 if (pwr_mode->pwr_rx == FASTAUTO_MODE || 4487 pwr_mode->pwr_tx == FASTAUTO_MODE || 4488 pwr_mode->pwr_rx == FAST_MODE || 4489 pwr_mode->pwr_tx == FAST_MODE) 4490 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES), 4491 pwr_mode->hs_rate); 4492 4493 if (!(hba->quirks & UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING)) { 4494 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 4495 DL_FC0ProtectionTimeOutVal_Default); 4496 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 4497 DL_TC0ReplayTimeOutVal_Default); 4498 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 4499 DL_AFC0ReqTimeOutVal_Default); 4500 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA3), 4501 DL_FC1ProtectionTimeOutVal_Default); 4502 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA4), 4503 DL_TC1ReplayTimeOutVal_Default); 4504 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA5), 4505 DL_AFC1ReqTimeOutVal_Default); 4506 4507 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalFC0ProtectionTimeOutVal), 4508 DL_FC0ProtectionTimeOutVal_Default); 4509 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalTC0ReplayTimeOutVal), 4510 DL_TC0ReplayTimeOutVal_Default); 4511 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalAFC0ReqTimeOutVal), 4512 DL_AFC0ReqTimeOutVal_Default); 4513 } 4514 4515 ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4 4516 | pwr_mode->pwr_tx); 4517 4518 if (ret) { 4519 dev_err(hba->dev, 4520 "%s: power mode change failed %d\n", __func__, ret); 4521 } else { 4522 ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL, 4523 pwr_mode); 4524 4525 memcpy(&hba->pwr_info, pwr_mode, 4526 sizeof(struct ufs_pa_layer_attr)); 4527 } 4528 4529 return ret; 4530 } 4531 4532 /** 4533 * ufshcd_config_pwr_mode - configure a new power mode 4534 * @hba: per-adapter instance 4535 * @desired_pwr_mode: desired power configuration 4536 * 4537 * Return: 0 upon success; < 0 upon failure. 4538 */ 4539 int ufshcd_config_pwr_mode(struct ufs_hba *hba, 4540 struct ufs_pa_layer_attr *desired_pwr_mode) 4541 { 4542 struct ufs_pa_layer_attr final_params = { 0 }; 4543 int ret; 4544 4545 ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE, 4546 desired_pwr_mode, &final_params); 4547 4548 if (ret) 4549 memcpy(&final_params, desired_pwr_mode, sizeof(final_params)); 4550 4551 ret = ufshcd_change_power_mode(hba, &final_params); 4552 4553 return ret; 4554 } 4555 EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode); 4556 4557 /** 4558 * ufshcd_complete_dev_init() - checks device readiness 4559 * @hba: per-adapter instance 4560 * 4561 * Set fDeviceInit flag and poll until device toggles it. 4562 * 4563 * Return: 0 upon success; < 0 upon failure. 4564 */ 4565 static int ufshcd_complete_dev_init(struct ufs_hba *hba) 4566 { 4567 int err; 4568 bool flag_res = true; 4569 ktime_t timeout; 4570 4571 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG, 4572 QUERY_FLAG_IDN_FDEVICEINIT, 0, NULL); 4573 if (err) { 4574 dev_err(hba->dev, 4575 "%s: setting fDeviceInit flag failed with error %d\n", 4576 __func__, err); 4577 goto out; 4578 } 4579 4580 /* Poll fDeviceInit flag to be cleared */ 4581 timeout = ktime_add_ms(ktime_get(), FDEVICEINIT_COMPL_TIMEOUT); 4582 do { 4583 err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_READ_FLAG, 4584 QUERY_FLAG_IDN_FDEVICEINIT, 0, &flag_res); 4585 if (!flag_res) 4586 break; 4587 usleep_range(500, 1000); 4588 } while (ktime_before(ktime_get(), timeout)); 4589 4590 if (err) { 4591 dev_err(hba->dev, 4592 "%s: reading fDeviceInit flag failed with error %d\n", 4593 __func__, err); 4594 } else if (flag_res) { 4595 dev_err(hba->dev, 4596 "%s: fDeviceInit was not cleared by the device\n", 4597 __func__); 4598 err = -EBUSY; 4599 } 4600 out: 4601 return err; 4602 } 4603 4604 /** 4605 * ufshcd_make_hba_operational - Make UFS controller operational 4606 * @hba: per adapter instance 4607 * 4608 * To bring UFS host controller to operational state, 4609 * 1. Enable required interrupts 4610 * 2. Configure interrupt aggregation 4611 * 3. Program UTRL and UTMRL base address 4612 * 4. Configure run-stop-registers 4613 * 4614 * Return: 0 on success, non-zero value on failure. 4615 */ 4616 int ufshcd_make_hba_operational(struct ufs_hba *hba) 4617 { 4618 int err = 0; 4619 u32 reg; 4620 4621 /* Enable required interrupts */ 4622 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS); 4623 4624 /* Configure interrupt aggregation */ 4625 if (ufshcd_is_intr_aggr_allowed(hba)) 4626 ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO); 4627 else 4628 ufshcd_disable_intr_aggr(hba); 4629 4630 /* Configure UTRL and UTMRL base address registers */ 4631 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr), 4632 REG_UTP_TRANSFER_REQ_LIST_BASE_L); 4633 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr), 4634 REG_UTP_TRANSFER_REQ_LIST_BASE_H); 4635 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr), 4636 REG_UTP_TASK_REQ_LIST_BASE_L); 4637 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr), 4638 REG_UTP_TASK_REQ_LIST_BASE_H); 4639 4640 /* 4641 * Make sure base address and interrupt setup are updated before 4642 * enabling the run/stop registers below. 4643 */ 4644 wmb(); 4645 4646 /* 4647 * UCRDY, UTMRLDY and UTRLRDY bits must be 1 4648 */ 4649 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS); 4650 if (!(ufshcd_get_lists_status(reg))) { 4651 ufshcd_enable_run_stop_reg(hba); 4652 } else { 4653 dev_err(hba->dev, 4654 "Host controller not ready to process requests"); 4655 err = -EIO; 4656 } 4657 4658 return err; 4659 } 4660 EXPORT_SYMBOL_GPL(ufshcd_make_hba_operational); 4661 4662 /** 4663 * ufshcd_hba_stop - Send controller to reset state 4664 * @hba: per adapter instance 4665 */ 4666 void ufshcd_hba_stop(struct ufs_hba *hba) 4667 { 4668 unsigned long flags; 4669 int err; 4670 4671 /* 4672 * Obtain the host lock to prevent that the controller is disabled 4673 * while the UFS interrupt handler is active on another CPU. 4674 */ 4675 spin_lock_irqsave(hba->host->host_lock, flags); 4676 ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE); 4677 spin_unlock_irqrestore(hba->host->host_lock, flags); 4678 4679 err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE, 4680 CONTROLLER_ENABLE, CONTROLLER_DISABLE, 4681 10, 1); 4682 if (err) 4683 dev_err(hba->dev, "%s: Controller disable failed\n", __func__); 4684 } 4685 EXPORT_SYMBOL_GPL(ufshcd_hba_stop); 4686 4687 /** 4688 * ufshcd_hba_execute_hce - initialize the controller 4689 * @hba: per adapter instance 4690 * 4691 * The controller resets itself and controller firmware initialization 4692 * sequence kicks off. When controller is ready it will set 4693 * the Host Controller Enable bit to 1. 4694 * 4695 * Return: 0 on success, non-zero value on failure. 4696 */ 4697 static int ufshcd_hba_execute_hce(struct ufs_hba *hba) 4698 { 4699 int retry_outer = 3; 4700 int retry_inner; 4701 4702 start: 4703 if (ufshcd_is_hba_active(hba)) 4704 /* change controller state to "reset state" */ 4705 ufshcd_hba_stop(hba); 4706 4707 /* UniPro link is disabled at this point */ 4708 ufshcd_set_link_off(hba); 4709 4710 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE); 4711 4712 /* start controller initialization sequence */ 4713 ufshcd_hba_start(hba); 4714 4715 /* 4716 * To initialize a UFS host controller HCE bit must be set to 1. 4717 * During initialization the HCE bit value changes from 1->0->1. 4718 * When the host controller completes initialization sequence 4719 * it sets the value of HCE bit to 1. The same HCE bit is read back 4720 * to check if the controller has completed initialization sequence. 4721 * So without this delay the value HCE = 1, set in the previous 4722 * instruction might be read back. 4723 * This delay can be changed based on the controller. 4724 */ 4725 ufshcd_delay_us(hba->vps->hba_enable_delay_us, 100); 4726 4727 /* wait for the host controller to complete initialization */ 4728 retry_inner = 50; 4729 while (!ufshcd_is_hba_active(hba)) { 4730 if (retry_inner) { 4731 retry_inner--; 4732 } else { 4733 dev_err(hba->dev, 4734 "Controller enable failed\n"); 4735 if (retry_outer) { 4736 retry_outer--; 4737 goto start; 4738 } 4739 return -EIO; 4740 } 4741 usleep_range(1000, 1100); 4742 } 4743 4744 /* enable UIC related interrupts */ 4745 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK); 4746 4747 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE); 4748 4749 return 0; 4750 } 4751 4752 int ufshcd_hba_enable(struct ufs_hba *hba) 4753 { 4754 int ret; 4755 4756 if (hba->quirks & UFSHCI_QUIRK_BROKEN_HCE) { 4757 ufshcd_set_link_off(hba); 4758 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE); 4759 4760 /* enable UIC related interrupts */ 4761 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK); 4762 ret = ufshcd_dme_reset(hba); 4763 if (ret) { 4764 dev_err(hba->dev, "DME_RESET failed\n"); 4765 return ret; 4766 } 4767 4768 ret = ufshcd_dme_enable(hba); 4769 if (ret) { 4770 dev_err(hba->dev, "Enabling DME failed\n"); 4771 return ret; 4772 } 4773 4774 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE); 4775 } else { 4776 ret = ufshcd_hba_execute_hce(hba); 4777 } 4778 4779 return ret; 4780 } 4781 EXPORT_SYMBOL_GPL(ufshcd_hba_enable); 4782 4783 static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer) 4784 { 4785 int tx_lanes = 0, i, err = 0; 4786 4787 if (!peer) 4788 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 4789 &tx_lanes); 4790 else 4791 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 4792 &tx_lanes); 4793 for (i = 0; i < tx_lanes; i++) { 4794 if (!peer) 4795 err = ufshcd_dme_set(hba, 4796 UIC_ARG_MIB_SEL(TX_LCC_ENABLE, 4797 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)), 4798 0); 4799 else 4800 err = ufshcd_dme_peer_set(hba, 4801 UIC_ARG_MIB_SEL(TX_LCC_ENABLE, 4802 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)), 4803 0); 4804 if (err) { 4805 dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d", 4806 __func__, peer, i, err); 4807 break; 4808 } 4809 } 4810 4811 return err; 4812 } 4813 4814 static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba) 4815 { 4816 return ufshcd_disable_tx_lcc(hba, true); 4817 } 4818 4819 void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val) 4820 { 4821 struct ufs_event_hist *e; 4822 4823 if (id >= UFS_EVT_CNT) 4824 return; 4825 4826 e = &hba->ufs_stats.event[id]; 4827 e->val[e->pos] = val; 4828 e->tstamp[e->pos] = local_clock(); 4829 e->cnt += 1; 4830 e->pos = (e->pos + 1) % UFS_EVENT_HIST_LENGTH; 4831 4832 ufshcd_vops_event_notify(hba, id, &val); 4833 } 4834 EXPORT_SYMBOL_GPL(ufshcd_update_evt_hist); 4835 4836 /** 4837 * ufshcd_link_startup - Initialize unipro link startup 4838 * @hba: per adapter instance 4839 * 4840 * Return: 0 for success, non-zero in case of failure. 4841 */ 4842 static int ufshcd_link_startup(struct ufs_hba *hba) 4843 { 4844 int ret; 4845 int retries = DME_LINKSTARTUP_RETRIES; 4846 bool link_startup_again = false; 4847 4848 /* 4849 * If UFS device isn't active then we will have to issue link startup 4850 * 2 times to make sure the device state move to active. 4851 */ 4852 if (!ufshcd_is_ufs_dev_active(hba)) 4853 link_startup_again = true; 4854 4855 link_startup: 4856 do { 4857 ufshcd_vops_link_startup_notify(hba, PRE_CHANGE); 4858 4859 ret = ufshcd_dme_link_startup(hba); 4860 4861 /* check if device is detected by inter-connect layer */ 4862 if (!ret && !ufshcd_is_device_present(hba)) { 4863 ufshcd_update_evt_hist(hba, 4864 UFS_EVT_LINK_STARTUP_FAIL, 4865 0); 4866 dev_err(hba->dev, "%s: Device not present\n", __func__); 4867 ret = -ENXIO; 4868 goto out; 4869 } 4870 4871 /* 4872 * DME link lost indication is only received when link is up, 4873 * but we can't be sure if the link is up until link startup 4874 * succeeds. So reset the local Uni-Pro and try again. 4875 */ 4876 if (ret && retries && ufshcd_hba_enable(hba)) { 4877 ufshcd_update_evt_hist(hba, 4878 UFS_EVT_LINK_STARTUP_FAIL, 4879 (u32)ret); 4880 goto out; 4881 } 4882 } while (ret && retries--); 4883 4884 if (ret) { 4885 /* failed to get the link up... retire */ 4886 ufshcd_update_evt_hist(hba, 4887 UFS_EVT_LINK_STARTUP_FAIL, 4888 (u32)ret); 4889 goto out; 4890 } 4891 4892 if (link_startup_again) { 4893 link_startup_again = false; 4894 retries = DME_LINKSTARTUP_RETRIES; 4895 goto link_startup; 4896 } 4897 4898 /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */ 4899 ufshcd_init_pwr_info(hba); 4900 ufshcd_print_pwr_info(hba); 4901 4902 if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) { 4903 ret = ufshcd_disable_device_tx_lcc(hba); 4904 if (ret) 4905 goto out; 4906 } 4907 4908 /* Include any host controller configuration via UIC commands */ 4909 ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE); 4910 if (ret) 4911 goto out; 4912 4913 /* Clear UECPA once due to LINERESET has happened during LINK_STARTUP */ 4914 ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER); 4915 ret = ufshcd_make_hba_operational(hba); 4916 out: 4917 if (ret) { 4918 dev_err(hba->dev, "link startup failed %d\n", ret); 4919 ufshcd_print_host_state(hba); 4920 ufshcd_print_pwr_info(hba); 4921 ufshcd_print_evt_hist(hba); 4922 } 4923 return ret; 4924 } 4925 4926 /** 4927 * ufshcd_verify_dev_init() - Verify device initialization 4928 * @hba: per-adapter instance 4929 * 4930 * Send NOP OUT UPIU and wait for NOP IN response to check whether the 4931 * device Transport Protocol (UTP) layer is ready after a reset. 4932 * If the UTP layer at the device side is not initialized, it may 4933 * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT 4934 * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations. 4935 * 4936 * Return: 0 upon success; < 0 upon failure. 4937 */ 4938 static int ufshcd_verify_dev_init(struct ufs_hba *hba) 4939 { 4940 int err = 0; 4941 int retries; 4942 4943 ufshcd_hold(hba); 4944 mutex_lock(&hba->dev_cmd.lock); 4945 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) { 4946 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP, 4947 hba->nop_out_timeout); 4948 4949 if (!err || err == -ETIMEDOUT) 4950 break; 4951 4952 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err); 4953 } 4954 mutex_unlock(&hba->dev_cmd.lock); 4955 ufshcd_release(hba); 4956 4957 if (err) 4958 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err); 4959 return err; 4960 } 4961 4962 /** 4963 * ufshcd_setup_links - associate link b/w device wlun and other luns 4964 * @sdev: pointer to SCSI device 4965 * @hba: pointer to ufs hba 4966 */ 4967 static void ufshcd_setup_links(struct ufs_hba *hba, struct scsi_device *sdev) 4968 { 4969 struct device_link *link; 4970 4971 /* 4972 * Device wlun is the supplier & rest of the luns are consumers. 4973 * This ensures that device wlun suspends after all other luns. 4974 */ 4975 if (hba->ufs_device_wlun) { 4976 link = device_link_add(&sdev->sdev_gendev, 4977 &hba->ufs_device_wlun->sdev_gendev, 4978 DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE); 4979 if (!link) { 4980 dev_err(&sdev->sdev_gendev, "Failed establishing link - %s\n", 4981 dev_name(&hba->ufs_device_wlun->sdev_gendev)); 4982 return; 4983 } 4984 hba->luns_avail--; 4985 /* Ignore REPORT_LUN wlun probing */ 4986 if (hba->luns_avail == 1) { 4987 ufshcd_rpm_put(hba); 4988 return; 4989 } 4990 } else { 4991 /* 4992 * Device wlun is probed. The assumption is that WLUNs are 4993 * scanned before other LUNs. 4994 */ 4995 hba->luns_avail--; 4996 } 4997 } 4998 4999 /** 5000 * ufshcd_lu_init - Initialize the relevant parameters of the LU 5001 * @hba: per-adapter instance 5002 * @sdev: pointer to SCSI device 5003 */ 5004 static void ufshcd_lu_init(struct ufs_hba *hba, struct scsi_device *sdev) 5005 { 5006 int len = QUERY_DESC_MAX_SIZE; 5007 u8 lun = ufshcd_scsi_to_upiu_lun(sdev->lun); 5008 u8 lun_qdepth = hba->nutrs; 5009 u8 *desc_buf; 5010 int ret; 5011 5012 desc_buf = kzalloc(len, GFP_KERNEL); 5013 if (!desc_buf) 5014 goto set_qdepth; 5015 5016 ret = ufshcd_read_unit_desc_param(hba, lun, 0, desc_buf, len); 5017 if (ret < 0) { 5018 if (ret == -EOPNOTSUPP) 5019 /* If LU doesn't support unit descriptor, its queue depth is set to 1 */ 5020 lun_qdepth = 1; 5021 kfree(desc_buf); 5022 goto set_qdepth; 5023 } 5024 5025 if (desc_buf[UNIT_DESC_PARAM_LU_Q_DEPTH]) { 5026 /* 5027 * In per-LU queueing architecture, bLUQueueDepth will not be 0, then we will 5028 * use the smaller between UFSHCI CAP.NUTRS and UFS LU bLUQueueDepth 5029 */ 5030 lun_qdepth = min_t(int, desc_buf[UNIT_DESC_PARAM_LU_Q_DEPTH], hba->nutrs); 5031 } 5032 /* 5033 * According to UFS device specification, the write protection mode is only supported by 5034 * normal LU, not supported by WLUN. 5035 */ 5036 if (hba->dev_info.f_power_on_wp_en && lun < hba->dev_info.max_lu_supported && 5037 !hba->dev_info.is_lu_power_on_wp && 5038 desc_buf[UNIT_DESC_PARAM_LU_WR_PROTECT] == UFS_LU_POWER_ON_WP) 5039 hba->dev_info.is_lu_power_on_wp = true; 5040 5041 /* In case of RPMB LU, check if advanced RPMB mode is enabled */ 5042 if (desc_buf[UNIT_DESC_PARAM_UNIT_INDEX] == UFS_UPIU_RPMB_WLUN && 5043 desc_buf[RPMB_UNIT_DESC_PARAM_REGION_EN] & BIT(4)) 5044 hba->dev_info.b_advanced_rpmb_en = true; 5045 5046 5047 kfree(desc_buf); 5048 set_qdepth: 5049 /* 5050 * For WLUNs that don't support unit descriptor, queue depth is set to 1. For LUs whose 5051 * bLUQueueDepth == 0, the queue depth is set to a maximum value that host can queue. 5052 */ 5053 dev_dbg(hba->dev, "Set LU %x queue depth %d\n", lun, lun_qdepth); 5054 scsi_change_queue_depth(sdev, lun_qdepth); 5055 } 5056 5057 /** 5058 * ufshcd_slave_alloc - handle initial SCSI device configurations 5059 * @sdev: pointer to SCSI device 5060 * 5061 * Return: success. 5062 */ 5063 static int ufshcd_slave_alloc(struct scsi_device *sdev) 5064 { 5065 struct ufs_hba *hba; 5066 5067 hba = shost_priv(sdev->host); 5068 5069 /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */ 5070 sdev->use_10_for_ms = 1; 5071 5072 /* DBD field should be set to 1 in mode sense(10) */ 5073 sdev->set_dbd_for_ms = 1; 5074 5075 /* allow SCSI layer to restart the device in case of errors */ 5076 sdev->allow_restart = 1; 5077 5078 /* REPORT SUPPORTED OPERATION CODES is not supported */ 5079 sdev->no_report_opcodes = 1; 5080 5081 /* WRITE_SAME command is not supported */ 5082 sdev->no_write_same = 1; 5083 5084 ufshcd_lu_init(hba, sdev); 5085 5086 ufshcd_setup_links(hba, sdev); 5087 5088 return 0; 5089 } 5090 5091 /** 5092 * ufshcd_change_queue_depth - change queue depth 5093 * @sdev: pointer to SCSI device 5094 * @depth: required depth to set 5095 * 5096 * Change queue depth and make sure the max. limits are not crossed. 5097 * 5098 * Return: new queue depth. 5099 */ 5100 static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth) 5101 { 5102 return scsi_change_queue_depth(sdev, min(depth, sdev->host->can_queue)); 5103 } 5104 5105 /** 5106 * ufshcd_slave_configure - adjust SCSI device configurations 5107 * @sdev: pointer to SCSI device 5108 * 5109 * Return: 0 (success). 5110 */ 5111 static int ufshcd_slave_configure(struct scsi_device *sdev) 5112 { 5113 struct ufs_hba *hba = shost_priv(sdev->host); 5114 struct request_queue *q = sdev->request_queue; 5115 5116 blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1); 5117 if (hba->quirks & UFSHCD_QUIRK_4KB_DMA_ALIGNMENT) 5118 blk_queue_update_dma_alignment(q, SZ_4K - 1); 5119 /* 5120 * Block runtime-pm until all consumers are added. 5121 * Refer ufshcd_setup_links(). 5122 */ 5123 if (is_device_wlun(sdev)) 5124 pm_runtime_get_noresume(&sdev->sdev_gendev); 5125 else if (ufshcd_is_rpm_autosuspend_allowed(hba)) 5126 sdev->rpm_autosuspend = 1; 5127 /* 5128 * Do not print messages during runtime PM to avoid never-ending cycles 5129 * of messages written back to storage by user space causing runtime 5130 * resume, causing more messages and so on. 5131 */ 5132 sdev->silence_suspend = 1; 5133 5134 ufshcd_crypto_register(hba, q); 5135 5136 return 0; 5137 } 5138 5139 /** 5140 * ufshcd_slave_destroy - remove SCSI device configurations 5141 * @sdev: pointer to SCSI device 5142 */ 5143 static void ufshcd_slave_destroy(struct scsi_device *sdev) 5144 { 5145 struct ufs_hba *hba; 5146 unsigned long flags; 5147 5148 hba = shost_priv(sdev->host); 5149 5150 /* Drop the reference as it won't be needed anymore */ 5151 if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) { 5152 spin_lock_irqsave(hba->host->host_lock, flags); 5153 hba->ufs_device_wlun = NULL; 5154 spin_unlock_irqrestore(hba->host->host_lock, flags); 5155 } else if (hba->ufs_device_wlun) { 5156 struct device *supplier = NULL; 5157 5158 /* Ensure UFS Device WLUN exists and does not disappear */ 5159 spin_lock_irqsave(hba->host->host_lock, flags); 5160 if (hba->ufs_device_wlun) { 5161 supplier = &hba->ufs_device_wlun->sdev_gendev; 5162 get_device(supplier); 5163 } 5164 spin_unlock_irqrestore(hba->host->host_lock, flags); 5165 5166 if (supplier) { 5167 /* 5168 * If a LUN fails to probe (e.g. absent BOOT WLUN), the 5169 * device will not have been registered but can still 5170 * have a device link holding a reference to the device. 5171 */ 5172 device_link_remove(&sdev->sdev_gendev, supplier); 5173 put_device(supplier); 5174 } 5175 } 5176 } 5177 5178 /** 5179 * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status 5180 * @lrbp: pointer to local reference block of completed command 5181 * @scsi_status: SCSI command status 5182 * 5183 * Return: value base on SCSI command status. 5184 */ 5185 static inline int 5186 ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status) 5187 { 5188 int result = 0; 5189 5190 switch (scsi_status) { 5191 case SAM_STAT_CHECK_CONDITION: 5192 ufshcd_copy_sense_data(lrbp); 5193 fallthrough; 5194 case SAM_STAT_GOOD: 5195 result |= DID_OK << 16 | scsi_status; 5196 break; 5197 case SAM_STAT_TASK_SET_FULL: 5198 case SAM_STAT_BUSY: 5199 case SAM_STAT_TASK_ABORTED: 5200 ufshcd_copy_sense_data(lrbp); 5201 result |= scsi_status; 5202 break; 5203 default: 5204 result |= DID_ERROR << 16; 5205 break; 5206 } /* end of switch */ 5207 5208 return result; 5209 } 5210 5211 /** 5212 * ufshcd_transfer_rsp_status - Get overall status of the response 5213 * @hba: per adapter instance 5214 * @lrbp: pointer to local reference block of completed command 5215 * @cqe: pointer to the completion queue entry 5216 * 5217 * Return: result of the command to notify SCSI midlayer. 5218 */ 5219 static inline int 5220 ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, 5221 struct cq_entry *cqe) 5222 { 5223 int result = 0; 5224 int scsi_status; 5225 enum utp_ocs ocs; 5226 u8 upiu_flags; 5227 u32 resid; 5228 5229 upiu_flags = lrbp->ucd_rsp_ptr->header.flags; 5230 resid = be32_to_cpu(lrbp->ucd_rsp_ptr->sr.residual_transfer_count); 5231 /* 5232 * Test !overflow instead of underflow to support UFS devices that do 5233 * not set either flag. 5234 */ 5235 if (resid && !(upiu_flags & UPIU_RSP_FLAG_OVERFLOW)) 5236 scsi_set_resid(lrbp->cmd, resid); 5237 5238 /* overall command status of utrd */ 5239 ocs = ufshcd_get_tr_ocs(lrbp, cqe); 5240 5241 if (hba->quirks & UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR) { 5242 if (lrbp->ucd_rsp_ptr->header.response || 5243 lrbp->ucd_rsp_ptr->header.status) 5244 ocs = OCS_SUCCESS; 5245 } 5246 5247 switch (ocs) { 5248 case OCS_SUCCESS: 5249 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0); 5250 switch (ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr)) { 5251 case UPIU_TRANSACTION_RESPONSE: 5252 /* 5253 * get the result based on SCSI status response 5254 * to notify the SCSI midlayer of the command status 5255 */ 5256 scsi_status = lrbp->ucd_rsp_ptr->header.status; 5257 result = ufshcd_scsi_cmd_status(lrbp, scsi_status); 5258 5259 /* 5260 * Currently we are only supporting BKOPs exception 5261 * events hence we can ignore BKOPs exception event 5262 * during power management callbacks. BKOPs exception 5263 * event is not expected to be raised in runtime suspend 5264 * callback as it allows the urgent bkops. 5265 * During system suspend, we are anyway forcefully 5266 * disabling the bkops and if urgent bkops is needed 5267 * it will be enabled on system resume. Long term 5268 * solution could be to abort the system suspend if 5269 * UFS device needs urgent BKOPs. 5270 */ 5271 if (!hba->pm_op_in_progress && 5272 !ufshcd_eh_in_progress(hba) && 5273 ufshcd_is_exception_event(lrbp->ucd_rsp_ptr)) 5274 /* Flushed in suspend */ 5275 schedule_work(&hba->eeh_work); 5276 break; 5277 case UPIU_TRANSACTION_REJECT_UPIU: 5278 /* TODO: handle Reject UPIU Response */ 5279 result = DID_ERROR << 16; 5280 dev_err(hba->dev, 5281 "Reject UPIU not fully implemented\n"); 5282 break; 5283 default: 5284 dev_err(hba->dev, 5285 "Unexpected request response code = %x\n", 5286 result); 5287 result = DID_ERROR << 16; 5288 break; 5289 } 5290 break; 5291 case OCS_ABORTED: 5292 result |= DID_ABORT << 16; 5293 break; 5294 case OCS_INVALID_COMMAND_STATUS: 5295 result |= DID_REQUEUE << 16; 5296 break; 5297 case OCS_INVALID_CMD_TABLE_ATTR: 5298 case OCS_INVALID_PRDT_ATTR: 5299 case OCS_MISMATCH_DATA_BUF_SIZE: 5300 case OCS_MISMATCH_RESP_UPIU_SIZE: 5301 case OCS_PEER_COMM_FAILURE: 5302 case OCS_FATAL_ERROR: 5303 case OCS_DEVICE_FATAL_ERROR: 5304 case OCS_INVALID_CRYPTO_CONFIG: 5305 case OCS_GENERAL_CRYPTO_ERROR: 5306 default: 5307 result |= DID_ERROR << 16; 5308 dev_err(hba->dev, 5309 "OCS error from controller = %x for tag %d\n", 5310 ocs, lrbp->task_tag); 5311 ufshcd_print_evt_hist(hba); 5312 ufshcd_print_host_state(hba); 5313 break; 5314 } /* end of switch */ 5315 5316 if ((host_byte(result) != DID_OK) && 5317 (host_byte(result) != DID_REQUEUE) && !hba->silence_err_logs) 5318 ufshcd_print_tr(hba, lrbp->task_tag, true); 5319 return result; 5320 } 5321 5322 static bool ufshcd_is_auto_hibern8_error(struct ufs_hba *hba, 5323 u32 intr_mask) 5324 { 5325 if (!ufshcd_is_auto_hibern8_supported(hba) || 5326 !ufshcd_is_auto_hibern8_enabled(hba)) 5327 return false; 5328 5329 if (!(intr_mask & UFSHCD_UIC_HIBERN8_MASK)) 5330 return false; 5331 5332 if (hba->active_uic_cmd && 5333 (hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_ENTER || 5334 hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_EXIT)) 5335 return false; 5336 5337 return true; 5338 } 5339 5340 /** 5341 * ufshcd_uic_cmd_compl - handle completion of uic command 5342 * @hba: per adapter instance 5343 * @intr_status: interrupt status generated by the controller 5344 * 5345 * Return: 5346 * IRQ_HANDLED - If interrupt is valid 5347 * IRQ_NONE - If invalid interrupt 5348 */ 5349 static irqreturn_t ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status) 5350 { 5351 irqreturn_t retval = IRQ_NONE; 5352 5353 spin_lock(hba->host->host_lock); 5354 if (ufshcd_is_auto_hibern8_error(hba, intr_status)) 5355 hba->errors |= (UFSHCD_UIC_HIBERN8_MASK & intr_status); 5356 5357 if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) { 5358 hba->active_uic_cmd->argument2 |= 5359 ufshcd_get_uic_cmd_result(hba); 5360 hba->active_uic_cmd->argument3 = 5361 ufshcd_get_dme_attr_val(hba); 5362 if (!hba->uic_async_done) 5363 hba->active_uic_cmd->cmd_active = 0; 5364 complete(&hba->active_uic_cmd->done); 5365 retval = IRQ_HANDLED; 5366 } 5367 5368 if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done) { 5369 hba->active_uic_cmd->cmd_active = 0; 5370 complete(hba->uic_async_done); 5371 retval = IRQ_HANDLED; 5372 } 5373 5374 if (retval == IRQ_HANDLED) 5375 ufshcd_add_uic_command_trace(hba, hba->active_uic_cmd, 5376 UFS_CMD_COMP); 5377 spin_unlock(hba->host->host_lock); 5378 return retval; 5379 } 5380 5381 /* Release the resources allocated for processing a SCSI command. */ 5382 void ufshcd_release_scsi_cmd(struct ufs_hba *hba, 5383 struct ufshcd_lrb *lrbp) 5384 { 5385 struct scsi_cmnd *cmd = lrbp->cmd; 5386 5387 scsi_dma_unmap(cmd); 5388 ufshcd_release(hba); 5389 ufshcd_clk_scaling_update_busy(hba); 5390 } 5391 5392 /** 5393 * ufshcd_compl_one_cqe - handle a completion queue entry 5394 * @hba: per adapter instance 5395 * @task_tag: the task tag of the request to be completed 5396 * @cqe: pointer to the completion queue entry 5397 */ 5398 void ufshcd_compl_one_cqe(struct ufs_hba *hba, int task_tag, 5399 struct cq_entry *cqe) 5400 { 5401 struct ufshcd_lrb *lrbp; 5402 struct scsi_cmnd *cmd; 5403 enum utp_ocs ocs; 5404 5405 lrbp = &hba->lrb[task_tag]; 5406 lrbp->compl_time_stamp = ktime_get(); 5407 cmd = lrbp->cmd; 5408 if (cmd) { 5409 if (unlikely(ufshcd_should_inform_monitor(hba, lrbp))) 5410 ufshcd_update_monitor(hba, lrbp); 5411 ufshcd_add_command_trace(hba, task_tag, UFS_CMD_COMP); 5412 cmd->result = ufshcd_transfer_rsp_status(hba, lrbp, cqe); 5413 ufshcd_release_scsi_cmd(hba, lrbp); 5414 /* Do not touch lrbp after scsi done */ 5415 scsi_done(cmd); 5416 } else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE || 5417 lrbp->command_type == UTP_CMD_TYPE_UFS_STORAGE) { 5418 if (hba->dev_cmd.complete) { 5419 if (cqe) { 5420 ocs = le32_to_cpu(cqe->status) & MASK_OCS; 5421 lrbp->utr_descriptor_ptr->header.ocs = ocs; 5422 } 5423 complete(hba->dev_cmd.complete); 5424 ufshcd_clk_scaling_update_busy(hba); 5425 } 5426 } 5427 } 5428 5429 /** 5430 * __ufshcd_transfer_req_compl - handle SCSI and query command completion 5431 * @hba: per adapter instance 5432 * @completed_reqs: bitmask that indicates which requests to complete 5433 */ 5434 static void __ufshcd_transfer_req_compl(struct ufs_hba *hba, 5435 unsigned long completed_reqs) 5436 { 5437 int tag; 5438 5439 for_each_set_bit(tag, &completed_reqs, hba->nutrs) 5440 ufshcd_compl_one_cqe(hba, tag, NULL); 5441 } 5442 5443 /* Any value that is not an existing queue number is fine for this constant. */ 5444 enum { 5445 UFSHCD_POLL_FROM_INTERRUPT_CONTEXT = -1 5446 }; 5447 5448 static void ufshcd_clear_polled(struct ufs_hba *hba, 5449 unsigned long *completed_reqs) 5450 { 5451 int tag; 5452 5453 for_each_set_bit(tag, completed_reqs, hba->nutrs) { 5454 struct scsi_cmnd *cmd = hba->lrb[tag].cmd; 5455 5456 if (!cmd) 5457 continue; 5458 if (scsi_cmd_to_rq(cmd)->cmd_flags & REQ_POLLED) 5459 __clear_bit(tag, completed_reqs); 5460 } 5461 } 5462 5463 /* 5464 * Return: > 0 if one or more commands have been completed or 0 if no 5465 * requests have been completed. 5466 */ 5467 static int ufshcd_poll(struct Scsi_Host *shost, unsigned int queue_num) 5468 { 5469 struct ufs_hba *hba = shost_priv(shost); 5470 unsigned long completed_reqs, flags; 5471 u32 tr_doorbell; 5472 struct ufs_hw_queue *hwq; 5473 5474 if (is_mcq_enabled(hba)) { 5475 hwq = &hba->uhq[queue_num]; 5476 5477 return ufshcd_mcq_poll_cqe_lock(hba, hwq); 5478 } 5479 5480 spin_lock_irqsave(&hba->outstanding_lock, flags); 5481 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 5482 completed_reqs = ~tr_doorbell & hba->outstanding_reqs; 5483 WARN_ONCE(completed_reqs & ~hba->outstanding_reqs, 5484 "completed: %#lx; outstanding: %#lx\n", completed_reqs, 5485 hba->outstanding_reqs); 5486 if (queue_num == UFSHCD_POLL_FROM_INTERRUPT_CONTEXT) { 5487 /* Do not complete polled requests from interrupt context. */ 5488 ufshcd_clear_polled(hba, &completed_reqs); 5489 } 5490 hba->outstanding_reqs &= ~completed_reqs; 5491 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 5492 5493 if (completed_reqs) 5494 __ufshcd_transfer_req_compl(hba, completed_reqs); 5495 5496 return completed_reqs != 0; 5497 } 5498 5499 /** 5500 * ufshcd_mcq_compl_pending_transfer - MCQ mode function. It is 5501 * invoked from the error handler context or ufshcd_host_reset_and_restore() 5502 * to complete the pending transfers and free the resources associated with 5503 * the scsi command. 5504 * 5505 * @hba: per adapter instance 5506 * @force_compl: This flag is set to true when invoked 5507 * from ufshcd_host_reset_and_restore() in which case it requires special 5508 * handling because the host controller has been reset by ufshcd_hba_stop(). 5509 */ 5510 static void ufshcd_mcq_compl_pending_transfer(struct ufs_hba *hba, 5511 bool force_compl) 5512 { 5513 struct ufs_hw_queue *hwq; 5514 struct ufshcd_lrb *lrbp; 5515 struct scsi_cmnd *cmd; 5516 unsigned long flags; 5517 u32 hwq_num, utag; 5518 int tag; 5519 5520 for (tag = 0; tag < hba->nutrs; tag++) { 5521 lrbp = &hba->lrb[tag]; 5522 cmd = lrbp->cmd; 5523 if (!ufshcd_cmd_inflight(cmd) || 5524 test_bit(SCMD_STATE_COMPLETE, &cmd->state)) 5525 continue; 5526 5527 utag = blk_mq_unique_tag(scsi_cmd_to_rq(cmd)); 5528 hwq_num = blk_mq_unique_tag_to_hwq(utag); 5529 hwq = &hba->uhq[hwq_num]; 5530 5531 if (force_compl) { 5532 ufshcd_mcq_compl_all_cqes_lock(hba, hwq); 5533 /* 5534 * For those cmds of which the cqes are not present 5535 * in the cq, complete them explicitly. 5536 */ 5537 if (cmd && !test_bit(SCMD_STATE_COMPLETE, &cmd->state)) { 5538 spin_lock_irqsave(&hwq->cq_lock, flags); 5539 set_host_byte(cmd, DID_REQUEUE); 5540 ufshcd_release_scsi_cmd(hba, lrbp); 5541 scsi_done(cmd); 5542 spin_unlock_irqrestore(&hwq->cq_lock, flags); 5543 } 5544 } else { 5545 ufshcd_mcq_poll_cqe_lock(hba, hwq); 5546 } 5547 } 5548 } 5549 5550 /** 5551 * ufshcd_transfer_req_compl - handle SCSI and query command completion 5552 * @hba: per adapter instance 5553 * 5554 * Return: 5555 * IRQ_HANDLED - If interrupt is valid 5556 * IRQ_NONE - If invalid interrupt 5557 */ 5558 static irqreturn_t ufshcd_transfer_req_compl(struct ufs_hba *hba) 5559 { 5560 /* Resetting interrupt aggregation counters first and reading the 5561 * DOOR_BELL afterward allows us to handle all the completed requests. 5562 * In order to prevent other interrupts starvation the DB is read once 5563 * after reset. The down side of this solution is the possibility of 5564 * false interrupt if device completes another request after resetting 5565 * aggregation and before reading the DB. 5566 */ 5567 if (ufshcd_is_intr_aggr_allowed(hba) && 5568 !(hba->quirks & UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR)) 5569 ufshcd_reset_intr_aggr(hba); 5570 5571 if (ufs_fail_completion()) 5572 return IRQ_HANDLED; 5573 5574 /* 5575 * Ignore the ufshcd_poll() return value and return IRQ_HANDLED since we 5576 * do not want polling to trigger spurious interrupt complaints. 5577 */ 5578 ufshcd_poll(hba->host, UFSHCD_POLL_FROM_INTERRUPT_CONTEXT); 5579 5580 return IRQ_HANDLED; 5581 } 5582 5583 int __ufshcd_write_ee_control(struct ufs_hba *hba, u32 ee_ctrl_mask) 5584 { 5585 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, 5586 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, 5587 &ee_ctrl_mask); 5588 } 5589 5590 int ufshcd_write_ee_control(struct ufs_hba *hba) 5591 { 5592 int err; 5593 5594 mutex_lock(&hba->ee_ctrl_mutex); 5595 err = __ufshcd_write_ee_control(hba, hba->ee_ctrl_mask); 5596 mutex_unlock(&hba->ee_ctrl_mutex); 5597 if (err) 5598 dev_err(hba->dev, "%s: failed to write ee control %d\n", 5599 __func__, err); 5600 return err; 5601 } 5602 5603 int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask, 5604 const u16 *other_mask, u16 set, u16 clr) 5605 { 5606 u16 new_mask, ee_ctrl_mask; 5607 int err = 0; 5608 5609 mutex_lock(&hba->ee_ctrl_mutex); 5610 new_mask = (*mask & ~clr) | set; 5611 ee_ctrl_mask = new_mask | *other_mask; 5612 if (ee_ctrl_mask != hba->ee_ctrl_mask) 5613 err = __ufshcd_write_ee_control(hba, ee_ctrl_mask); 5614 /* Still need to update 'mask' even if 'ee_ctrl_mask' was unchanged */ 5615 if (!err) { 5616 hba->ee_ctrl_mask = ee_ctrl_mask; 5617 *mask = new_mask; 5618 } 5619 mutex_unlock(&hba->ee_ctrl_mutex); 5620 return err; 5621 } 5622 5623 /** 5624 * ufshcd_disable_ee - disable exception event 5625 * @hba: per-adapter instance 5626 * @mask: exception event to disable 5627 * 5628 * Disables exception event in the device so that the EVENT_ALERT 5629 * bit is not set. 5630 * 5631 * Return: zero on success, non-zero error value on failure. 5632 */ 5633 static inline int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask) 5634 { 5635 return ufshcd_update_ee_drv_mask(hba, 0, mask); 5636 } 5637 5638 /** 5639 * ufshcd_enable_ee - enable exception event 5640 * @hba: per-adapter instance 5641 * @mask: exception event to enable 5642 * 5643 * Enable corresponding exception event in the device to allow 5644 * device to alert host in critical scenarios. 5645 * 5646 * Return: zero on success, non-zero error value on failure. 5647 */ 5648 static inline int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask) 5649 { 5650 return ufshcd_update_ee_drv_mask(hba, mask, 0); 5651 } 5652 5653 /** 5654 * ufshcd_enable_auto_bkops - Allow device managed BKOPS 5655 * @hba: per-adapter instance 5656 * 5657 * Allow device to manage background operations on its own. Enabling 5658 * this might lead to inconsistent latencies during normal data transfers 5659 * as the device is allowed to manage its own way of handling background 5660 * operations. 5661 * 5662 * Return: zero on success, non-zero on failure. 5663 */ 5664 static int ufshcd_enable_auto_bkops(struct ufs_hba *hba) 5665 { 5666 int err = 0; 5667 5668 if (hba->auto_bkops_enabled) 5669 goto out; 5670 5671 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG, 5672 QUERY_FLAG_IDN_BKOPS_EN, 0, NULL); 5673 if (err) { 5674 dev_err(hba->dev, "%s: failed to enable bkops %d\n", 5675 __func__, err); 5676 goto out; 5677 } 5678 5679 hba->auto_bkops_enabled = true; 5680 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Enabled"); 5681 5682 /* No need of URGENT_BKOPS exception from the device */ 5683 err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS); 5684 if (err) 5685 dev_err(hba->dev, "%s: failed to disable exception event %d\n", 5686 __func__, err); 5687 out: 5688 return err; 5689 } 5690 5691 /** 5692 * ufshcd_disable_auto_bkops - block device in doing background operations 5693 * @hba: per-adapter instance 5694 * 5695 * Disabling background operations improves command response latency but 5696 * has drawback of device moving into critical state where the device is 5697 * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the 5698 * host is idle so that BKOPS are managed effectively without any negative 5699 * impacts. 5700 * 5701 * Return: zero on success, non-zero on failure. 5702 */ 5703 static int ufshcd_disable_auto_bkops(struct ufs_hba *hba) 5704 { 5705 int err = 0; 5706 5707 if (!hba->auto_bkops_enabled) 5708 goto out; 5709 5710 /* 5711 * If host assisted BKOPs is to be enabled, make sure 5712 * urgent bkops exception is allowed. 5713 */ 5714 err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS); 5715 if (err) { 5716 dev_err(hba->dev, "%s: failed to enable exception event %d\n", 5717 __func__, err); 5718 goto out; 5719 } 5720 5721 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG, 5722 QUERY_FLAG_IDN_BKOPS_EN, 0, NULL); 5723 if (err) { 5724 dev_err(hba->dev, "%s: failed to disable bkops %d\n", 5725 __func__, err); 5726 ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS); 5727 goto out; 5728 } 5729 5730 hba->auto_bkops_enabled = false; 5731 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Disabled"); 5732 hba->is_urgent_bkops_lvl_checked = false; 5733 out: 5734 return err; 5735 } 5736 5737 /** 5738 * ufshcd_force_reset_auto_bkops - force reset auto bkops state 5739 * @hba: per adapter instance 5740 * 5741 * After a device reset the device may toggle the BKOPS_EN flag 5742 * to default value. The s/w tracking variables should be updated 5743 * as well. This function would change the auto-bkops state based on 5744 * UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND. 5745 */ 5746 static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba) 5747 { 5748 if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) { 5749 hba->auto_bkops_enabled = false; 5750 hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS; 5751 ufshcd_enable_auto_bkops(hba); 5752 } else { 5753 hba->auto_bkops_enabled = true; 5754 hba->ee_ctrl_mask &= ~MASK_EE_URGENT_BKOPS; 5755 ufshcd_disable_auto_bkops(hba); 5756 } 5757 hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT; 5758 hba->is_urgent_bkops_lvl_checked = false; 5759 } 5760 5761 static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status) 5762 { 5763 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 5764 QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status); 5765 } 5766 5767 /** 5768 * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status 5769 * @hba: per-adapter instance 5770 * @status: bkops_status value 5771 * 5772 * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn 5773 * flag in the device to permit background operations if the device 5774 * bkops_status is greater than or equal to "status" argument passed to 5775 * this function, disable otherwise. 5776 * 5777 * Return: 0 for success, non-zero in case of failure. 5778 * 5779 * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag 5780 * to know whether auto bkops is enabled or disabled after this function 5781 * returns control to it. 5782 */ 5783 static int ufshcd_bkops_ctrl(struct ufs_hba *hba, 5784 enum bkops_status status) 5785 { 5786 int err; 5787 u32 curr_status = 0; 5788 5789 err = ufshcd_get_bkops_status(hba, &curr_status); 5790 if (err) { 5791 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n", 5792 __func__, err); 5793 goto out; 5794 } else if (curr_status > BKOPS_STATUS_MAX) { 5795 dev_err(hba->dev, "%s: invalid BKOPS status %d\n", 5796 __func__, curr_status); 5797 err = -EINVAL; 5798 goto out; 5799 } 5800 5801 if (curr_status >= status) 5802 err = ufshcd_enable_auto_bkops(hba); 5803 else 5804 err = ufshcd_disable_auto_bkops(hba); 5805 out: 5806 return err; 5807 } 5808 5809 /** 5810 * ufshcd_urgent_bkops - handle urgent bkops exception event 5811 * @hba: per-adapter instance 5812 * 5813 * Enable fBackgroundOpsEn flag in the device to permit background 5814 * operations. 5815 * 5816 * If BKOPs is enabled, this function returns 0, 1 if the bkops in not enabled 5817 * and negative error value for any other failure. 5818 * 5819 * Return: 0 upon success; < 0 upon failure. 5820 */ 5821 static int ufshcd_urgent_bkops(struct ufs_hba *hba) 5822 { 5823 return ufshcd_bkops_ctrl(hba, hba->urgent_bkops_lvl); 5824 } 5825 5826 static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status) 5827 { 5828 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 5829 QUERY_ATTR_IDN_EE_STATUS, 0, 0, status); 5830 } 5831 5832 static void ufshcd_bkops_exception_event_handler(struct ufs_hba *hba) 5833 { 5834 int err; 5835 u32 curr_status = 0; 5836 5837 if (hba->is_urgent_bkops_lvl_checked) 5838 goto enable_auto_bkops; 5839 5840 err = ufshcd_get_bkops_status(hba, &curr_status); 5841 if (err) { 5842 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n", 5843 __func__, err); 5844 goto out; 5845 } 5846 5847 /* 5848 * We are seeing that some devices are raising the urgent bkops 5849 * exception events even when BKOPS status doesn't indicate performace 5850 * impacted or critical. Handle these device by determining their urgent 5851 * bkops status at runtime. 5852 */ 5853 if (curr_status < BKOPS_STATUS_PERF_IMPACT) { 5854 dev_err(hba->dev, "%s: device raised urgent BKOPS exception for bkops status %d\n", 5855 __func__, curr_status); 5856 /* update the current status as the urgent bkops level */ 5857 hba->urgent_bkops_lvl = curr_status; 5858 hba->is_urgent_bkops_lvl_checked = true; 5859 } 5860 5861 enable_auto_bkops: 5862 err = ufshcd_enable_auto_bkops(hba); 5863 out: 5864 if (err < 0) 5865 dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n", 5866 __func__, err); 5867 } 5868 5869 static void ufshcd_temp_exception_event_handler(struct ufs_hba *hba, u16 status) 5870 { 5871 u32 value; 5872 5873 if (ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 5874 QUERY_ATTR_IDN_CASE_ROUGH_TEMP, 0, 0, &value)) 5875 return; 5876 5877 dev_info(hba->dev, "exception Tcase %d\n", value - 80); 5878 5879 ufs_hwmon_notify_event(hba, status & MASK_EE_URGENT_TEMP); 5880 5881 /* 5882 * A placeholder for the platform vendors to add whatever additional 5883 * steps required 5884 */ 5885 } 5886 5887 static int __ufshcd_wb_toggle(struct ufs_hba *hba, bool set, enum flag_idn idn) 5888 { 5889 u8 index; 5890 enum query_opcode opcode = set ? UPIU_QUERY_OPCODE_SET_FLAG : 5891 UPIU_QUERY_OPCODE_CLEAR_FLAG; 5892 5893 index = ufshcd_wb_get_query_index(hba); 5894 return ufshcd_query_flag_retry(hba, opcode, idn, index, NULL); 5895 } 5896 5897 int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable) 5898 { 5899 int ret; 5900 5901 if (!ufshcd_is_wb_allowed(hba) || 5902 hba->dev_info.wb_enabled == enable) 5903 return 0; 5904 5905 ret = __ufshcd_wb_toggle(hba, enable, QUERY_FLAG_IDN_WB_EN); 5906 if (ret) { 5907 dev_err(hba->dev, "%s: Write Booster %s failed %d\n", 5908 __func__, enable ? "enabling" : "disabling", ret); 5909 return ret; 5910 } 5911 5912 hba->dev_info.wb_enabled = enable; 5913 dev_dbg(hba->dev, "%s: Write Booster %s\n", 5914 __func__, enable ? "enabled" : "disabled"); 5915 5916 return ret; 5917 } 5918 5919 static void ufshcd_wb_toggle_buf_flush_during_h8(struct ufs_hba *hba, 5920 bool enable) 5921 { 5922 int ret; 5923 5924 ret = __ufshcd_wb_toggle(hba, enable, 5925 QUERY_FLAG_IDN_WB_BUFF_FLUSH_DURING_HIBERN8); 5926 if (ret) { 5927 dev_err(hba->dev, "%s: WB-Buf Flush during H8 %s failed %d\n", 5928 __func__, enable ? "enabling" : "disabling", ret); 5929 return; 5930 } 5931 dev_dbg(hba->dev, "%s: WB-Buf Flush during H8 %s\n", 5932 __func__, enable ? "enabled" : "disabled"); 5933 } 5934 5935 int ufshcd_wb_toggle_buf_flush(struct ufs_hba *hba, bool enable) 5936 { 5937 int ret; 5938 5939 if (!ufshcd_is_wb_allowed(hba) || 5940 hba->dev_info.wb_buf_flush_enabled == enable) 5941 return 0; 5942 5943 ret = __ufshcd_wb_toggle(hba, enable, QUERY_FLAG_IDN_WB_BUFF_FLUSH_EN); 5944 if (ret) { 5945 dev_err(hba->dev, "%s: WB-Buf Flush %s failed %d\n", 5946 __func__, enable ? "enabling" : "disabling", ret); 5947 return ret; 5948 } 5949 5950 hba->dev_info.wb_buf_flush_enabled = enable; 5951 dev_dbg(hba->dev, "%s: WB-Buf Flush %s\n", 5952 __func__, enable ? "enabled" : "disabled"); 5953 5954 return ret; 5955 } 5956 5957 static bool ufshcd_wb_presrv_usrspc_keep_vcc_on(struct ufs_hba *hba, 5958 u32 avail_buf) 5959 { 5960 u32 cur_buf; 5961 int ret; 5962 u8 index; 5963 5964 index = ufshcd_wb_get_query_index(hba); 5965 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 5966 QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE, 5967 index, 0, &cur_buf); 5968 if (ret) { 5969 dev_err(hba->dev, "%s: dCurWriteBoosterBufferSize read failed %d\n", 5970 __func__, ret); 5971 return false; 5972 } 5973 5974 if (!cur_buf) { 5975 dev_info(hba->dev, "dCurWBBuf: %d WB disabled until free-space is available\n", 5976 cur_buf); 5977 return false; 5978 } 5979 /* Let it continue to flush when available buffer exceeds threshold */ 5980 return avail_buf < hba->vps->wb_flush_threshold; 5981 } 5982 5983 static void ufshcd_wb_force_disable(struct ufs_hba *hba) 5984 { 5985 if (ufshcd_is_wb_buf_flush_allowed(hba)) 5986 ufshcd_wb_toggle_buf_flush(hba, false); 5987 5988 ufshcd_wb_toggle_buf_flush_during_h8(hba, false); 5989 ufshcd_wb_toggle(hba, false); 5990 hba->caps &= ~UFSHCD_CAP_WB_EN; 5991 5992 dev_info(hba->dev, "%s: WB force disabled\n", __func__); 5993 } 5994 5995 static bool ufshcd_is_wb_buf_lifetime_available(struct ufs_hba *hba) 5996 { 5997 u32 lifetime; 5998 int ret; 5999 u8 index; 6000 6001 index = ufshcd_wb_get_query_index(hba); 6002 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 6003 QUERY_ATTR_IDN_WB_BUFF_LIFE_TIME_EST, 6004 index, 0, &lifetime); 6005 if (ret) { 6006 dev_err(hba->dev, 6007 "%s: bWriteBoosterBufferLifeTimeEst read failed %d\n", 6008 __func__, ret); 6009 return false; 6010 } 6011 6012 if (lifetime == UFS_WB_EXCEED_LIFETIME) { 6013 dev_err(hba->dev, "%s: WB buf lifetime is exhausted 0x%02X\n", 6014 __func__, lifetime); 6015 return false; 6016 } 6017 6018 dev_dbg(hba->dev, "%s: WB buf lifetime is 0x%02X\n", 6019 __func__, lifetime); 6020 6021 return true; 6022 } 6023 6024 static bool ufshcd_wb_need_flush(struct ufs_hba *hba) 6025 { 6026 int ret; 6027 u32 avail_buf; 6028 u8 index; 6029 6030 if (!ufshcd_is_wb_allowed(hba)) 6031 return false; 6032 6033 if (!ufshcd_is_wb_buf_lifetime_available(hba)) { 6034 ufshcd_wb_force_disable(hba); 6035 return false; 6036 } 6037 6038 /* 6039 * The ufs device needs the vcc to be ON to flush. 6040 * With user-space reduction enabled, it's enough to enable flush 6041 * by checking only the available buffer. The threshold 6042 * defined here is > 90% full. 6043 * With user-space preserved enabled, the current-buffer 6044 * should be checked too because the wb buffer size can reduce 6045 * when disk tends to be full. This info is provided by current 6046 * buffer (dCurrentWriteBoosterBufferSize). There's no point in 6047 * keeping vcc on when current buffer is empty. 6048 */ 6049 index = ufshcd_wb_get_query_index(hba); 6050 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 6051 QUERY_ATTR_IDN_AVAIL_WB_BUFF_SIZE, 6052 index, 0, &avail_buf); 6053 if (ret) { 6054 dev_warn(hba->dev, "%s: dAvailableWriteBoosterBufferSize read failed %d\n", 6055 __func__, ret); 6056 return false; 6057 } 6058 6059 if (!hba->dev_info.b_presrv_uspc_en) 6060 return avail_buf <= UFS_WB_BUF_REMAIN_PERCENT(10); 6061 6062 return ufshcd_wb_presrv_usrspc_keep_vcc_on(hba, avail_buf); 6063 } 6064 6065 static void ufshcd_rpm_dev_flush_recheck_work(struct work_struct *work) 6066 { 6067 struct ufs_hba *hba = container_of(to_delayed_work(work), 6068 struct ufs_hba, 6069 rpm_dev_flush_recheck_work); 6070 /* 6071 * To prevent unnecessary VCC power drain after device finishes 6072 * WriteBooster buffer flush or Auto BKOPs, force runtime resume 6073 * after a certain delay to recheck the threshold by next runtime 6074 * suspend. 6075 */ 6076 ufshcd_rpm_get_sync(hba); 6077 ufshcd_rpm_put_sync(hba); 6078 } 6079 6080 /** 6081 * ufshcd_exception_event_handler - handle exceptions raised by device 6082 * @work: pointer to work data 6083 * 6084 * Read bExceptionEventStatus attribute from the device and handle the 6085 * exception event accordingly. 6086 */ 6087 static void ufshcd_exception_event_handler(struct work_struct *work) 6088 { 6089 struct ufs_hba *hba; 6090 int err; 6091 u32 status = 0; 6092 hba = container_of(work, struct ufs_hba, eeh_work); 6093 6094 ufshcd_scsi_block_requests(hba); 6095 err = ufshcd_get_ee_status(hba, &status); 6096 if (err) { 6097 dev_err(hba->dev, "%s: failed to get exception status %d\n", 6098 __func__, err); 6099 goto out; 6100 } 6101 6102 trace_ufshcd_exception_event(dev_name(hba->dev), status); 6103 6104 if (status & hba->ee_drv_mask & MASK_EE_URGENT_BKOPS) 6105 ufshcd_bkops_exception_event_handler(hba); 6106 6107 if (status & hba->ee_drv_mask & MASK_EE_URGENT_TEMP) 6108 ufshcd_temp_exception_event_handler(hba, status); 6109 6110 ufs_debugfs_exception_event(hba, status); 6111 out: 6112 ufshcd_scsi_unblock_requests(hba); 6113 } 6114 6115 /* Complete requests that have door-bell cleared */ 6116 static void ufshcd_complete_requests(struct ufs_hba *hba, bool force_compl) 6117 { 6118 if (is_mcq_enabled(hba)) 6119 ufshcd_mcq_compl_pending_transfer(hba, force_compl); 6120 else 6121 ufshcd_transfer_req_compl(hba); 6122 6123 ufshcd_tmc_handler(hba); 6124 } 6125 6126 /** 6127 * ufshcd_quirk_dl_nac_errors - This function checks if error handling is 6128 * to recover from the DL NAC errors or not. 6129 * @hba: per-adapter instance 6130 * 6131 * Return: true if error handling is required, false otherwise. 6132 */ 6133 static bool ufshcd_quirk_dl_nac_errors(struct ufs_hba *hba) 6134 { 6135 unsigned long flags; 6136 bool err_handling = true; 6137 6138 spin_lock_irqsave(hba->host->host_lock, flags); 6139 /* 6140 * UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS only workaround the 6141 * device fatal error and/or DL NAC & REPLAY timeout errors. 6142 */ 6143 if (hba->saved_err & (CONTROLLER_FATAL_ERROR | SYSTEM_BUS_FATAL_ERROR)) 6144 goto out; 6145 6146 if ((hba->saved_err & DEVICE_FATAL_ERROR) || 6147 ((hba->saved_err & UIC_ERROR) && 6148 (hba->saved_uic_err & UFSHCD_UIC_DL_TCx_REPLAY_ERROR))) 6149 goto out; 6150 6151 if ((hba->saved_err & UIC_ERROR) && 6152 (hba->saved_uic_err & UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)) { 6153 int err; 6154 /* 6155 * wait for 50ms to see if we can get any other errors or not. 6156 */ 6157 spin_unlock_irqrestore(hba->host->host_lock, flags); 6158 msleep(50); 6159 spin_lock_irqsave(hba->host->host_lock, flags); 6160 6161 /* 6162 * now check if we have got any other severe errors other than 6163 * DL NAC error? 6164 */ 6165 if ((hba->saved_err & INT_FATAL_ERRORS) || 6166 ((hba->saved_err & UIC_ERROR) && 6167 (hba->saved_uic_err & ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR))) 6168 goto out; 6169 6170 /* 6171 * As DL NAC is the only error received so far, send out NOP 6172 * command to confirm if link is still active or not. 6173 * - If we don't get any response then do error recovery. 6174 * - If we get response then clear the DL NAC error bit. 6175 */ 6176 6177 spin_unlock_irqrestore(hba->host->host_lock, flags); 6178 err = ufshcd_verify_dev_init(hba); 6179 spin_lock_irqsave(hba->host->host_lock, flags); 6180 6181 if (err) 6182 goto out; 6183 6184 /* Link seems to be alive hence ignore the DL NAC errors */ 6185 if (hba->saved_uic_err == UFSHCD_UIC_DL_NAC_RECEIVED_ERROR) 6186 hba->saved_err &= ~UIC_ERROR; 6187 /* clear NAC error */ 6188 hba->saved_uic_err &= ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR; 6189 if (!hba->saved_uic_err) 6190 err_handling = false; 6191 } 6192 out: 6193 spin_unlock_irqrestore(hba->host->host_lock, flags); 6194 return err_handling; 6195 } 6196 6197 /* host lock must be held before calling this func */ 6198 static inline bool ufshcd_is_saved_err_fatal(struct ufs_hba *hba) 6199 { 6200 return (hba->saved_uic_err & UFSHCD_UIC_DL_PA_INIT_ERROR) || 6201 (hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)); 6202 } 6203 6204 void ufshcd_schedule_eh_work(struct ufs_hba *hba) 6205 { 6206 lockdep_assert_held(hba->host->host_lock); 6207 6208 /* handle fatal errors only when link is not in error state */ 6209 if (hba->ufshcd_state != UFSHCD_STATE_ERROR) { 6210 if (hba->force_reset || ufshcd_is_link_broken(hba) || 6211 ufshcd_is_saved_err_fatal(hba)) 6212 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_FATAL; 6213 else 6214 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_NON_FATAL; 6215 queue_work(hba->eh_wq, &hba->eh_work); 6216 } 6217 } 6218 6219 static void ufshcd_force_error_recovery(struct ufs_hba *hba) 6220 { 6221 spin_lock_irq(hba->host->host_lock); 6222 hba->force_reset = true; 6223 ufshcd_schedule_eh_work(hba); 6224 spin_unlock_irq(hba->host->host_lock); 6225 } 6226 6227 static void ufshcd_clk_scaling_allow(struct ufs_hba *hba, bool allow) 6228 { 6229 mutex_lock(&hba->wb_mutex); 6230 down_write(&hba->clk_scaling_lock); 6231 hba->clk_scaling.is_allowed = allow; 6232 up_write(&hba->clk_scaling_lock); 6233 mutex_unlock(&hba->wb_mutex); 6234 } 6235 6236 static void ufshcd_clk_scaling_suspend(struct ufs_hba *hba, bool suspend) 6237 { 6238 if (suspend) { 6239 if (hba->clk_scaling.is_enabled) 6240 ufshcd_suspend_clkscaling(hba); 6241 ufshcd_clk_scaling_allow(hba, false); 6242 } else { 6243 ufshcd_clk_scaling_allow(hba, true); 6244 if (hba->clk_scaling.is_enabled) 6245 ufshcd_resume_clkscaling(hba); 6246 } 6247 } 6248 6249 static void ufshcd_err_handling_prepare(struct ufs_hba *hba) 6250 { 6251 ufshcd_rpm_get_sync(hba); 6252 if (pm_runtime_status_suspended(&hba->ufs_device_wlun->sdev_gendev) || 6253 hba->is_sys_suspended) { 6254 enum ufs_pm_op pm_op; 6255 6256 /* 6257 * Don't assume anything of resume, if 6258 * resume fails, irq and clocks can be OFF, and powers 6259 * can be OFF or in LPM. 6260 */ 6261 ufshcd_setup_hba_vreg(hba, true); 6262 ufshcd_enable_irq(hba); 6263 ufshcd_setup_vreg(hba, true); 6264 ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq); 6265 ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2); 6266 ufshcd_hold(hba); 6267 if (!ufshcd_is_clkgating_allowed(hba)) 6268 ufshcd_setup_clocks(hba, true); 6269 pm_op = hba->is_sys_suspended ? UFS_SYSTEM_PM : UFS_RUNTIME_PM; 6270 ufshcd_vops_resume(hba, pm_op); 6271 } else { 6272 ufshcd_hold(hba); 6273 if (ufshcd_is_clkscaling_supported(hba) && 6274 hba->clk_scaling.is_enabled) 6275 ufshcd_suspend_clkscaling(hba); 6276 ufshcd_clk_scaling_allow(hba, false); 6277 } 6278 ufshcd_scsi_block_requests(hba); 6279 /* Wait for ongoing ufshcd_queuecommand() calls to finish. */ 6280 blk_mq_wait_quiesce_done(&hba->host->tag_set); 6281 cancel_work_sync(&hba->eeh_work); 6282 } 6283 6284 static void ufshcd_err_handling_unprepare(struct ufs_hba *hba) 6285 { 6286 ufshcd_scsi_unblock_requests(hba); 6287 ufshcd_release(hba); 6288 if (ufshcd_is_clkscaling_supported(hba)) 6289 ufshcd_clk_scaling_suspend(hba, false); 6290 ufshcd_rpm_put(hba); 6291 } 6292 6293 static inline bool ufshcd_err_handling_should_stop(struct ufs_hba *hba) 6294 { 6295 return (!hba->is_powered || hba->shutting_down || 6296 !hba->ufs_device_wlun || 6297 hba->ufshcd_state == UFSHCD_STATE_ERROR || 6298 (!(hba->saved_err || hba->saved_uic_err || hba->force_reset || 6299 ufshcd_is_link_broken(hba)))); 6300 } 6301 6302 #ifdef CONFIG_PM 6303 static void ufshcd_recover_pm_error(struct ufs_hba *hba) 6304 { 6305 struct Scsi_Host *shost = hba->host; 6306 struct scsi_device *sdev; 6307 struct request_queue *q; 6308 int ret; 6309 6310 hba->is_sys_suspended = false; 6311 /* 6312 * Set RPM status of wlun device to RPM_ACTIVE, 6313 * this also clears its runtime error. 6314 */ 6315 ret = pm_runtime_set_active(&hba->ufs_device_wlun->sdev_gendev); 6316 6317 /* hba device might have a runtime error otherwise */ 6318 if (ret) 6319 ret = pm_runtime_set_active(hba->dev); 6320 /* 6321 * If wlun device had runtime error, we also need to resume those 6322 * consumer scsi devices in case any of them has failed to be 6323 * resumed due to supplier runtime resume failure. This is to unblock 6324 * blk_queue_enter in case there are bios waiting inside it. 6325 */ 6326 if (!ret) { 6327 shost_for_each_device(sdev, shost) { 6328 q = sdev->request_queue; 6329 if (q->dev && (q->rpm_status == RPM_SUSPENDED || 6330 q->rpm_status == RPM_SUSPENDING)) 6331 pm_request_resume(q->dev); 6332 } 6333 } 6334 } 6335 #else 6336 static inline void ufshcd_recover_pm_error(struct ufs_hba *hba) 6337 { 6338 } 6339 #endif 6340 6341 static bool ufshcd_is_pwr_mode_restore_needed(struct ufs_hba *hba) 6342 { 6343 struct ufs_pa_layer_attr *pwr_info = &hba->pwr_info; 6344 u32 mode; 6345 6346 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PWRMODE), &mode); 6347 6348 if (pwr_info->pwr_rx != ((mode >> PWRMODE_RX_OFFSET) & PWRMODE_MASK)) 6349 return true; 6350 6351 if (pwr_info->pwr_tx != (mode & PWRMODE_MASK)) 6352 return true; 6353 6354 return false; 6355 } 6356 6357 static bool ufshcd_abort_one(struct request *rq, void *priv) 6358 { 6359 int *ret = priv; 6360 u32 tag = rq->tag; 6361 struct scsi_cmnd *cmd = blk_mq_rq_to_pdu(rq); 6362 struct scsi_device *sdev = cmd->device; 6363 struct Scsi_Host *shost = sdev->host; 6364 struct ufs_hba *hba = shost_priv(shost); 6365 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 6366 struct ufs_hw_queue *hwq; 6367 unsigned long flags; 6368 6369 *ret = ufshcd_try_to_abort_task(hba, tag); 6370 dev_err(hba->dev, "Aborting tag %d / CDB %#02x %s\n", tag, 6371 hba->lrb[tag].cmd ? hba->lrb[tag].cmd->cmnd[0] : -1, 6372 *ret ? "failed" : "succeeded"); 6373 6374 /* Release cmd in MCQ mode if abort succeeds */ 6375 if (is_mcq_enabled(hba) && (*ret == 0)) { 6376 hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(lrbp->cmd)); 6377 if (!hwq) 6378 return 0; 6379 spin_lock_irqsave(&hwq->cq_lock, flags); 6380 if (ufshcd_cmd_inflight(lrbp->cmd)) 6381 ufshcd_release_scsi_cmd(hba, lrbp); 6382 spin_unlock_irqrestore(&hwq->cq_lock, flags); 6383 } 6384 6385 return *ret == 0; 6386 } 6387 6388 /** 6389 * ufshcd_abort_all - Abort all pending commands. 6390 * @hba: Host bus adapter pointer. 6391 * 6392 * Return: true if and only if the host controller needs to be reset. 6393 */ 6394 static bool ufshcd_abort_all(struct ufs_hba *hba) 6395 { 6396 int tag, ret = 0; 6397 6398 blk_mq_tagset_busy_iter(&hba->host->tag_set, ufshcd_abort_one, &ret); 6399 if (ret) 6400 goto out; 6401 6402 /* Clear pending task management requests */ 6403 for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) { 6404 ret = ufshcd_clear_tm_cmd(hba, tag); 6405 if (ret) 6406 goto out; 6407 } 6408 6409 out: 6410 /* Complete the requests that are cleared by s/w */ 6411 ufshcd_complete_requests(hba, false); 6412 6413 return ret != 0; 6414 } 6415 6416 /** 6417 * ufshcd_err_handler - handle UFS errors that require s/w attention 6418 * @work: pointer to work structure 6419 */ 6420 static void ufshcd_err_handler(struct work_struct *work) 6421 { 6422 int retries = MAX_ERR_HANDLER_RETRIES; 6423 struct ufs_hba *hba; 6424 unsigned long flags; 6425 bool needs_restore; 6426 bool needs_reset; 6427 int pmc_err; 6428 6429 hba = container_of(work, struct ufs_hba, eh_work); 6430 6431 dev_info(hba->dev, 6432 "%s started; HBA state %s; powered %d; shutting down %d; saved_err = %d; saved_uic_err = %d; force_reset = %d%s\n", 6433 __func__, ufshcd_state_name[hba->ufshcd_state], 6434 hba->is_powered, hba->shutting_down, hba->saved_err, 6435 hba->saved_uic_err, hba->force_reset, 6436 ufshcd_is_link_broken(hba) ? "; link is broken" : ""); 6437 6438 down(&hba->host_sem); 6439 spin_lock_irqsave(hba->host->host_lock, flags); 6440 if (ufshcd_err_handling_should_stop(hba)) { 6441 if (hba->ufshcd_state != UFSHCD_STATE_ERROR) 6442 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL; 6443 spin_unlock_irqrestore(hba->host->host_lock, flags); 6444 up(&hba->host_sem); 6445 return; 6446 } 6447 ufshcd_set_eh_in_progress(hba); 6448 spin_unlock_irqrestore(hba->host->host_lock, flags); 6449 ufshcd_err_handling_prepare(hba); 6450 /* Complete requests that have door-bell cleared by h/w */ 6451 ufshcd_complete_requests(hba, false); 6452 spin_lock_irqsave(hba->host->host_lock, flags); 6453 again: 6454 needs_restore = false; 6455 needs_reset = false; 6456 6457 if (hba->ufshcd_state != UFSHCD_STATE_ERROR) 6458 hba->ufshcd_state = UFSHCD_STATE_RESET; 6459 /* 6460 * A full reset and restore might have happened after preparation 6461 * is finished, double check whether we should stop. 6462 */ 6463 if (ufshcd_err_handling_should_stop(hba)) 6464 goto skip_err_handling; 6465 6466 if ((hba->dev_quirks & UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) && 6467 !hba->force_reset) { 6468 bool ret; 6469 6470 spin_unlock_irqrestore(hba->host->host_lock, flags); 6471 /* release the lock as ufshcd_quirk_dl_nac_errors() may sleep */ 6472 ret = ufshcd_quirk_dl_nac_errors(hba); 6473 spin_lock_irqsave(hba->host->host_lock, flags); 6474 if (!ret && ufshcd_err_handling_should_stop(hba)) 6475 goto skip_err_handling; 6476 } 6477 6478 if ((hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) || 6479 (hba->saved_uic_err && 6480 (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) { 6481 bool pr_prdt = !!(hba->saved_err & SYSTEM_BUS_FATAL_ERROR); 6482 6483 spin_unlock_irqrestore(hba->host->host_lock, flags); 6484 ufshcd_print_host_state(hba); 6485 ufshcd_print_pwr_info(hba); 6486 ufshcd_print_evt_hist(hba); 6487 ufshcd_print_tmrs(hba, hba->outstanding_tasks); 6488 ufshcd_print_trs_all(hba, pr_prdt); 6489 spin_lock_irqsave(hba->host->host_lock, flags); 6490 } 6491 6492 /* 6493 * if host reset is required then skip clearing the pending 6494 * transfers forcefully because they will get cleared during 6495 * host reset and restore 6496 */ 6497 if (hba->force_reset || ufshcd_is_link_broken(hba) || 6498 ufshcd_is_saved_err_fatal(hba) || 6499 ((hba->saved_err & UIC_ERROR) && 6500 (hba->saved_uic_err & (UFSHCD_UIC_DL_NAC_RECEIVED_ERROR | 6501 UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))) { 6502 needs_reset = true; 6503 goto do_reset; 6504 } 6505 6506 /* 6507 * If LINERESET was caught, UFS might have been put to PWM mode, 6508 * check if power mode restore is needed. 6509 */ 6510 if (hba->saved_uic_err & UFSHCD_UIC_PA_GENERIC_ERROR) { 6511 hba->saved_uic_err &= ~UFSHCD_UIC_PA_GENERIC_ERROR; 6512 if (!hba->saved_uic_err) 6513 hba->saved_err &= ~UIC_ERROR; 6514 spin_unlock_irqrestore(hba->host->host_lock, flags); 6515 if (ufshcd_is_pwr_mode_restore_needed(hba)) 6516 needs_restore = true; 6517 spin_lock_irqsave(hba->host->host_lock, flags); 6518 if (!hba->saved_err && !needs_restore) 6519 goto skip_err_handling; 6520 } 6521 6522 hba->silence_err_logs = true; 6523 /* release lock as clear command might sleep */ 6524 spin_unlock_irqrestore(hba->host->host_lock, flags); 6525 6526 needs_reset = ufshcd_abort_all(hba); 6527 6528 spin_lock_irqsave(hba->host->host_lock, flags); 6529 hba->silence_err_logs = false; 6530 if (needs_reset) 6531 goto do_reset; 6532 6533 /* 6534 * After all reqs and tasks are cleared from doorbell, 6535 * now it is safe to retore power mode. 6536 */ 6537 if (needs_restore) { 6538 spin_unlock_irqrestore(hba->host->host_lock, flags); 6539 /* 6540 * Hold the scaling lock just in case dev cmds 6541 * are sent via bsg and/or sysfs. 6542 */ 6543 down_write(&hba->clk_scaling_lock); 6544 hba->force_pmc = true; 6545 pmc_err = ufshcd_config_pwr_mode(hba, &(hba->pwr_info)); 6546 if (pmc_err) { 6547 needs_reset = true; 6548 dev_err(hba->dev, "%s: Failed to restore power mode, err = %d\n", 6549 __func__, pmc_err); 6550 } 6551 hba->force_pmc = false; 6552 ufshcd_print_pwr_info(hba); 6553 up_write(&hba->clk_scaling_lock); 6554 spin_lock_irqsave(hba->host->host_lock, flags); 6555 } 6556 6557 do_reset: 6558 /* Fatal errors need reset */ 6559 if (needs_reset) { 6560 int err; 6561 6562 hba->force_reset = false; 6563 spin_unlock_irqrestore(hba->host->host_lock, flags); 6564 err = ufshcd_reset_and_restore(hba); 6565 if (err) 6566 dev_err(hba->dev, "%s: reset and restore failed with err %d\n", 6567 __func__, err); 6568 else 6569 ufshcd_recover_pm_error(hba); 6570 spin_lock_irqsave(hba->host->host_lock, flags); 6571 } 6572 6573 skip_err_handling: 6574 if (!needs_reset) { 6575 if (hba->ufshcd_state == UFSHCD_STATE_RESET) 6576 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL; 6577 if (hba->saved_err || hba->saved_uic_err) 6578 dev_err_ratelimited(hba->dev, "%s: exit: saved_err 0x%x saved_uic_err 0x%x", 6579 __func__, hba->saved_err, hba->saved_uic_err); 6580 } 6581 /* Exit in an operational state or dead */ 6582 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL && 6583 hba->ufshcd_state != UFSHCD_STATE_ERROR) { 6584 if (--retries) 6585 goto again; 6586 hba->ufshcd_state = UFSHCD_STATE_ERROR; 6587 } 6588 ufshcd_clear_eh_in_progress(hba); 6589 spin_unlock_irqrestore(hba->host->host_lock, flags); 6590 ufshcd_err_handling_unprepare(hba); 6591 up(&hba->host_sem); 6592 6593 dev_info(hba->dev, "%s finished; HBA state %s\n", __func__, 6594 ufshcd_state_name[hba->ufshcd_state]); 6595 } 6596 6597 /** 6598 * ufshcd_update_uic_error - check and set fatal UIC error flags. 6599 * @hba: per-adapter instance 6600 * 6601 * Return: 6602 * IRQ_HANDLED - If interrupt is valid 6603 * IRQ_NONE - If invalid interrupt 6604 */ 6605 static irqreturn_t ufshcd_update_uic_error(struct ufs_hba *hba) 6606 { 6607 u32 reg; 6608 irqreturn_t retval = IRQ_NONE; 6609 6610 /* PHY layer error */ 6611 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER); 6612 if ((reg & UIC_PHY_ADAPTER_LAYER_ERROR) && 6613 (reg & UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK)) { 6614 ufshcd_update_evt_hist(hba, UFS_EVT_PA_ERR, reg); 6615 /* 6616 * To know whether this error is fatal or not, DB timeout 6617 * must be checked but this error is handled separately. 6618 */ 6619 if (reg & UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK) 6620 dev_dbg(hba->dev, "%s: UIC Lane error reported\n", 6621 __func__); 6622 6623 /* Got a LINERESET indication. */ 6624 if (reg & UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR) { 6625 struct uic_command *cmd = NULL; 6626 6627 hba->uic_error |= UFSHCD_UIC_PA_GENERIC_ERROR; 6628 if (hba->uic_async_done && hba->active_uic_cmd) 6629 cmd = hba->active_uic_cmd; 6630 /* 6631 * Ignore the LINERESET during power mode change 6632 * operation via DME_SET command. 6633 */ 6634 if (cmd && (cmd->command == UIC_CMD_DME_SET)) 6635 hba->uic_error &= ~UFSHCD_UIC_PA_GENERIC_ERROR; 6636 } 6637 retval |= IRQ_HANDLED; 6638 } 6639 6640 /* PA_INIT_ERROR is fatal and needs UIC reset */ 6641 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER); 6642 if ((reg & UIC_DATA_LINK_LAYER_ERROR) && 6643 (reg & UIC_DATA_LINK_LAYER_ERROR_CODE_MASK)) { 6644 ufshcd_update_evt_hist(hba, UFS_EVT_DL_ERR, reg); 6645 6646 if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT) 6647 hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR; 6648 else if (hba->dev_quirks & 6649 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) { 6650 if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED) 6651 hba->uic_error |= 6652 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR; 6653 else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT) 6654 hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR; 6655 } 6656 retval |= IRQ_HANDLED; 6657 } 6658 6659 /* UIC NL/TL/DME errors needs software retry */ 6660 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER); 6661 if ((reg & UIC_NETWORK_LAYER_ERROR) && 6662 (reg & UIC_NETWORK_LAYER_ERROR_CODE_MASK)) { 6663 ufshcd_update_evt_hist(hba, UFS_EVT_NL_ERR, reg); 6664 hba->uic_error |= UFSHCD_UIC_NL_ERROR; 6665 retval |= IRQ_HANDLED; 6666 } 6667 6668 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER); 6669 if ((reg & UIC_TRANSPORT_LAYER_ERROR) && 6670 (reg & UIC_TRANSPORT_LAYER_ERROR_CODE_MASK)) { 6671 ufshcd_update_evt_hist(hba, UFS_EVT_TL_ERR, reg); 6672 hba->uic_error |= UFSHCD_UIC_TL_ERROR; 6673 retval |= IRQ_HANDLED; 6674 } 6675 6676 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME); 6677 if ((reg & UIC_DME_ERROR) && 6678 (reg & UIC_DME_ERROR_CODE_MASK)) { 6679 ufshcd_update_evt_hist(hba, UFS_EVT_DME_ERR, reg); 6680 hba->uic_error |= UFSHCD_UIC_DME_ERROR; 6681 retval |= IRQ_HANDLED; 6682 } 6683 6684 dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n", 6685 __func__, hba->uic_error); 6686 return retval; 6687 } 6688 6689 /** 6690 * ufshcd_check_errors - Check for errors that need s/w attention 6691 * @hba: per-adapter instance 6692 * @intr_status: interrupt status generated by the controller 6693 * 6694 * Return: 6695 * IRQ_HANDLED - If interrupt is valid 6696 * IRQ_NONE - If invalid interrupt 6697 */ 6698 static irqreturn_t ufshcd_check_errors(struct ufs_hba *hba, u32 intr_status) 6699 { 6700 bool queue_eh_work = false; 6701 irqreturn_t retval = IRQ_NONE; 6702 6703 spin_lock(hba->host->host_lock); 6704 hba->errors |= UFSHCD_ERROR_MASK & intr_status; 6705 6706 if (hba->errors & INT_FATAL_ERRORS) { 6707 ufshcd_update_evt_hist(hba, UFS_EVT_FATAL_ERR, 6708 hba->errors); 6709 queue_eh_work = true; 6710 } 6711 6712 if (hba->errors & UIC_ERROR) { 6713 hba->uic_error = 0; 6714 retval = ufshcd_update_uic_error(hba); 6715 if (hba->uic_error) 6716 queue_eh_work = true; 6717 } 6718 6719 if (hba->errors & UFSHCD_UIC_HIBERN8_MASK) { 6720 dev_err(hba->dev, 6721 "%s: Auto Hibern8 %s failed - status: 0x%08x, upmcrs: 0x%08x\n", 6722 __func__, (hba->errors & UIC_HIBERNATE_ENTER) ? 6723 "Enter" : "Exit", 6724 hba->errors, ufshcd_get_upmcrs(hba)); 6725 ufshcd_update_evt_hist(hba, UFS_EVT_AUTO_HIBERN8_ERR, 6726 hba->errors); 6727 ufshcd_set_link_broken(hba); 6728 queue_eh_work = true; 6729 } 6730 6731 if (queue_eh_work) { 6732 /* 6733 * update the transfer error masks to sticky bits, let's do this 6734 * irrespective of current ufshcd_state. 6735 */ 6736 hba->saved_err |= hba->errors; 6737 hba->saved_uic_err |= hba->uic_error; 6738 6739 /* dump controller state before resetting */ 6740 if ((hba->saved_err & 6741 (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) || 6742 (hba->saved_uic_err && 6743 (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) { 6744 dev_err(hba->dev, "%s: saved_err 0x%x saved_uic_err 0x%x\n", 6745 __func__, hba->saved_err, 6746 hba->saved_uic_err); 6747 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, 6748 "host_regs: "); 6749 ufshcd_print_pwr_info(hba); 6750 } 6751 ufshcd_schedule_eh_work(hba); 6752 retval |= IRQ_HANDLED; 6753 } 6754 /* 6755 * if (!queue_eh_work) - 6756 * Other errors are either non-fatal where host recovers 6757 * itself without s/w intervention or errors that will be 6758 * handled by the SCSI core layer. 6759 */ 6760 hba->errors = 0; 6761 hba->uic_error = 0; 6762 spin_unlock(hba->host->host_lock); 6763 return retval; 6764 } 6765 6766 /** 6767 * ufshcd_tmc_handler - handle task management function completion 6768 * @hba: per adapter instance 6769 * 6770 * Return: 6771 * IRQ_HANDLED - If interrupt is valid 6772 * IRQ_NONE - If invalid interrupt 6773 */ 6774 static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba) 6775 { 6776 unsigned long flags, pending, issued; 6777 irqreturn_t ret = IRQ_NONE; 6778 int tag; 6779 6780 spin_lock_irqsave(hba->host->host_lock, flags); 6781 pending = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL); 6782 issued = hba->outstanding_tasks & ~pending; 6783 for_each_set_bit(tag, &issued, hba->nutmrs) { 6784 struct request *req = hba->tmf_rqs[tag]; 6785 struct completion *c = req->end_io_data; 6786 6787 complete(c); 6788 ret = IRQ_HANDLED; 6789 } 6790 spin_unlock_irqrestore(hba->host->host_lock, flags); 6791 6792 return ret; 6793 } 6794 6795 /** 6796 * ufshcd_handle_mcq_cq_events - handle MCQ completion queue events 6797 * @hba: per adapter instance 6798 * 6799 * Return: IRQ_HANDLED if interrupt is handled. 6800 */ 6801 static irqreturn_t ufshcd_handle_mcq_cq_events(struct ufs_hba *hba) 6802 { 6803 struct ufs_hw_queue *hwq; 6804 unsigned long outstanding_cqs; 6805 unsigned int nr_queues; 6806 int i, ret; 6807 u32 events; 6808 6809 ret = ufshcd_vops_get_outstanding_cqs(hba, &outstanding_cqs); 6810 if (ret) 6811 outstanding_cqs = (1U << hba->nr_hw_queues) - 1; 6812 6813 /* Exclude the poll queues */ 6814 nr_queues = hba->nr_hw_queues - hba->nr_queues[HCTX_TYPE_POLL]; 6815 for_each_set_bit(i, &outstanding_cqs, nr_queues) { 6816 hwq = &hba->uhq[i]; 6817 6818 events = ufshcd_mcq_read_cqis(hba, i); 6819 if (events) 6820 ufshcd_mcq_write_cqis(hba, events, i); 6821 6822 if (events & UFSHCD_MCQ_CQIS_TAIL_ENT_PUSH_STS) 6823 ufshcd_mcq_poll_cqe_lock(hba, hwq); 6824 } 6825 6826 return IRQ_HANDLED; 6827 } 6828 6829 /** 6830 * ufshcd_sl_intr - Interrupt service routine 6831 * @hba: per adapter instance 6832 * @intr_status: contains interrupts generated by the controller 6833 * 6834 * Return: 6835 * IRQ_HANDLED - If interrupt is valid 6836 * IRQ_NONE - If invalid interrupt 6837 */ 6838 static irqreturn_t ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status) 6839 { 6840 irqreturn_t retval = IRQ_NONE; 6841 6842 if (intr_status & UFSHCD_UIC_MASK) 6843 retval |= ufshcd_uic_cmd_compl(hba, intr_status); 6844 6845 if (intr_status & UFSHCD_ERROR_MASK || hba->errors) 6846 retval |= ufshcd_check_errors(hba, intr_status); 6847 6848 if (intr_status & UTP_TASK_REQ_COMPL) 6849 retval |= ufshcd_tmc_handler(hba); 6850 6851 if (intr_status & UTP_TRANSFER_REQ_COMPL) 6852 retval |= ufshcd_transfer_req_compl(hba); 6853 6854 if (intr_status & MCQ_CQ_EVENT_STATUS) 6855 retval |= ufshcd_handle_mcq_cq_events(hba); 6856 6857 return retval; 6858 } 6859 6860 /** 6861 * ufshcd_intr - Main interrupt service routine 6862 * @irq: irq number 6863 * @__hba: pointer to adapter instance 6864 * 6865 * Return: 6866 * IRQ_HANDLED - If interrupt is valid 6867 * IRQ_NONE - If invalid interrupt 6868 */ 6869 static irqreturn_t ufshcd_intr(int irq, void *__hba) 6870 { 6871 u32 intr_status, enabled_intr_status = 0; 6872 irqreturn_t retval = IRQ_NONE; 6873 struct ufs_hba *hba = __hba; 6874 int retries = hba->nutrs; 6875 6876 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS); 6877 hba->ufs_stats.last_intr_status = intr_status; 6878 hba->ufs_stats.last_intr_ts = local_clock(); 6879 6880 /* 6881 * There could be max of hba->nutrs reqs in flight and in worst case 6882 * if the reqs get finished 1 by 1 after the interrupt status is 6883 * read, make sure we handle them by checking the interrupt status 6884 * again in a loop until we process all of the reqs before returning. 6885 */ 6886 while (intr_status && retries--) { 6887 enabled_intr_status = 6888 intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 6889 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS); 6890 if (enabled_intr_status) 6891 retval |= ufshcd_sl_intr(hba, enabled_intr_status); 6892 6893 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS); 6894 } 6895 6896 if (enabled_intr_status && retval == IRQ_NONE && 6897 (!(enabled_intr_status & UTP_TRANSFER_REQ_COMPL) || 6898 hba->outstanding_reqs) && !ufshcd_eh_in_progress(hba)) { 6899 dev_err(hba->dev, "%s: Unhandled interrupt 0x%08x (0x%08x, 0x%08x)\n", 6900 __func__, 6901 intr_status, 6902 hba->ufs_stats.last_intr_status, 6903 enabled_intr_status); 6904 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: "); 6905 } 6906 6907 return retval; 6908 } 6909 6910 static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag) 6911 { 6912 int err = 0; 6913 u32 mask = 1 << tag; 6914 unsigned long flags; 6915 6916 if (!test_bit(tag, &hba->outstanding_tasks)) 6917 goto out; 6918 6919 spin_lock_irqsave(hba->host->host_lock, flags); 6920 ufshcd_utmrl_clear(hba, tag); 6921 spin_unlock_irqrestore(hba->host->host_lock, flags); 6922 6923 /* poll for max. 1 sec to clear door bell register by h/w */ 6924 err = ufshcd_wait_for_register(hba, 6925 REG_UTP_TASK_REQ_DOOR_BELL, 6926 mask, 0, 1000, 1000); 6927 6928 dev_err(hba->dev, "Clearing task management function with tag %d %s\n", 6929 tag, err < 0 ? "failed" : "succeeded"); 6930 6931 out: 6932 return err; 6933 } 6934 6935 static int __ufshcd_issue_tm_cmd(struct ufs_hba *hba, 6936 struct utp_task_req_desc *treq, u8 tm_function) 6937 { 6938 struct request_queue *q = hba->tmf_queue; 6939 struct Scsi_Host *host = hba->host; 6940 DECLARE_COMPLETION_ONSTACK(wait); 6941 struct request *req; 6942 unsigned long flags; 6943 int task_tag, err; 6944 6945 /* 6946 * blk_mq_alloc_request() is used here only to get a free tag. 6947 */ 6948 req = blk_mq_alloc_request(q, REQ_OP_DRV_OUT, 0); 6949 if (IS_ERR(req)) 6950 return PTR_ERR(req); 6951 6952 req->end_io_data = &wait; 6953 ufshcd_hold(hba); 6954 6955 spin_lock_irqsave(host->host_lock, flags); 6956 6957 task_tag = req->tag; 6958 WARN_ONCE(task_tag < 0 || task_tag >= hba->nutmrs, "Invalid tag %d\n", 6959 task_tag); 6960 hba->tmf_rqs[req->tag] = req; 6961 treq->upiu_req.req_header.task_tag = task_tag; 6962 6963 memcpy(hba->utmrdl_base_addr + task_tag, treq, sizeof(*treq)); 6964 ufshcd_vops_setup_task_mgmt(hba, task_tag, tm_function); 6965 6966 /* send command to the controller */ 6967 __set_bit(task_tag, &hba->outstanding_tasks); 6968 6969 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TASK_REQ_DOOR_BELL); 6970 /* Make sure that doorbell is committed immediately */ 6971 wmb(); 6972 6973 spin_unlock_irqrestore(host->host_lock, flags); 6974 6975 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_SEND); 6976 6977 /* wait until the task management command is completed */ 6978 err = wait_for_completion_io_timeout(&wait, 6979 msecs_to_jiffies(TM_CMD_TIMEOUT)); 6980 if (!err) { 6981 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_ERR); 6982 dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n", 6983 __func__, tm_function); 6984 if (ufshcd_clear_tm_cmd(hba, task_tag)) 6985 dev_WARN(hba->dev, "%s: unable to clear tm cmd (slot %d) after timeout\n", 6986 __func__, task_tag); 6987 err = -ETIMEDOUT; 6988 } else { 6989 err = 0; 6990 memcpy(treq, hba->utmrdl_base_addr + task_tag, sizeof(*treq)); 6991 6992 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_COMP); 6993 } 6994 6995 spin_lock_irqsave(hba->host->host_lock, flags); 6996 hba->tmf_rqs[req->tag] = NULL; 6997 __clear_bit(task_tag, &hba->outstanding_tasks); 6998 spin_unlock_irqrestore(hba->host->host_lock, flags); 6999 7000 ufshcd_release(hba); 7001 blk_mq_free_request(req); 7002 7003 return err; 7004 } 7005 7006 /** 7007 * ufshcd_issue_tm_cmd - issues task management commands to controller 7008 * @hba: per adapter instance 7009 * @lun_id: LUN ID to which TM command is sent 7010 * @task_id: task ID to which the TM command is applicable 7011 * @tm_function: task management function opcode 7012 * @tm_response: task management service response return value 7013 * 7014 * Return: non-zero value on error, zero on success. 7015 */ 7016 static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id, 7017 u8 tm_function, u8 *tm_response) 7018 { 7019 struct utp_task_req_desc treq = { }; 7020 enum utp_ocs ocs_value; 7021 int err; 7022 7023 /* Configure task request descriptor */ 7024 treq.header.interrupt = 1; 7025 treq.header.ocs = OCS_INVALID_COMMAND_STATUS; 7026 7027 /* Configure task request UPIU */ 7028 treq.upiu_req.req_header.transaction_code = UPIU_TRANSACTION_TASK_REQ; 7029 treq.upiu_req.req_header.lun = lun_id; 7030 treq.upiu_req.req_header.tm_function = tm_function; 7031 7032 /* 7033 * The host shall provide the same value for LUN field in the basic 7034 * header and for Input Parameter. 7035 */ 7036 treq.upiu_req.input_param1 = cpu_to_be32(lun_id); 7037 treq.upiu_req.input_param2 = cpu_to_be32(task_id); 7038 7039 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_function); 7040 if (err == -ETIMEDOUT) 7041 return err; 7042 7043 ocs_value = treq.header.ocs & MASK_OCS; 7044 if (ocs_value != OCS_SUCCESS) 7045 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n", 7046 __func__, ocs_value); 7047 else if (tm_response) 7048 *tm_response = be32_to_cpu(treq.upiu_rsp.output_param1) & 7049 MASK_TM_SERVICE_RESP; 7050 return err; 7051 } 7052 7053 /** 7054 * ufshcd_issue_devman_upiu_cmd - API for sending "utrd" type requests 7055 * @hba: per-adapter instance 7056 * @req_upiu: upiu request 7057 * @rsp_upiu: upiu reply 7058 * @desc_buff: pointer to descriptor buffer, NULL if NA 7059 * @buff_len: descriptor size, 0 if NA 7060 * @cmd_type: specifies the type (NOP, Query...) 7061 * @desc_op: descriptor operation 7062 * 7063 * Those type of requests uses UTP Transfer Request Descriptor - utrd. 7064 * Therefore, it "rides" the device management infrastructure: uses its tag and 7065 * tasks work queues. 7066 * 7067 * Since there is only one available tag for device management commands, 7068 * the caller is expected to hold the hba->dev_cmd.lock mutex. 7069 * 7070 * Return: 0 upon success; < 0 upon failure. 7071 */ 7072 static int ufshcd_issue_devman_upiu_cmd(struct ufs_hba *hba, 7073 struct utp_upiu_req *req_upiu, 7074 struct utp_upiu_req *rsp_upiu, 7075 u8 *desc_buff, int *buff_len, 7076 enum dev_cmd_type cmd_type, 7077 enum query_opcode desc_op) 7078 { 7079 DECLARE_COMPLETION_ONSTACK(wait); 7080 const u32 tag = hba->reserved_slot; 7081 struct ufshcd_lrb *lrbp; 7082 int err = 0; 7083 u8 upiu_flags; 7084 7085 /* Protects use of hba->reserved_slot. */ 7086 lockdep_assert_held(&hba->dev_cmd.lock); 7087 7088 down_read(&hba->clk_scaling_lock); 7089 7090 lrbp = &hba->lrb[tag]; 7091 lrbp->cmd = NULL; 7092 lrbp->task_tag = tag; 7093 lrbp->lun = 0; 7094 lrbp->intr_cmd = true; 7095 ufshcd_prepare_lrbp_crypto(NULL, lrbp); 7096 hba->dev_cmd.type = cmd_type; 7097 7098 if (hba->ufs_version <= ufshci_version(1, 1)) 7099 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE; 7100 else 7101 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE; 7102 7103 /* update the task tag in the request upiu */ 7104 req_upiu->header.task_tag = tag; 7105 7106 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE, 0); 7107 7108 /* just copy the upiu request as it is */ 7109 memcpy(lrbp->ucd_req_ptr, req_upiu, sizeof(*lrbp->ucd_req_ptr)); 7110 if (desc_buff && desc_op == UPIU_QUERY_OPCODE_WRITE_DESC) { 7111 /* The Data Segment Area is optional depending upon the query 7112 * function value. for WRITE DESCRIPTOR, the data segment 7113 * follows right after the tsf. 7114 */ 7115 memcpy(lrbp->ucd_req_ptr + 1, desc_buff, *buff_len); 7116 *buff_len = 0; 7117 } 7118 7119 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 7120 7121 hba->dev_cmd.complete = &wait; 7122 7123 ufshcd_add_query_upiu_trace(hba, UFS_QUERY_SEND, lrbp->ucd_req_ptr); 7124 7125 ufshcd_send_command(hba, tag, hba->dev_cmd_queue); 7126 /* 7127 * ignore the returning value here - ufshcd_check_query_response is 7128 * bound to fail since dev_cmd.query and dev_cmd.type were left empty. 7129 * read the response directly ignoring all errors. 7130 */ 7131 ufshcd_wait_for_dev_cmd(hba, lrbp, QUERY_REQ_TIMEOUT); 7132 7133 /* just copy the upiu response as it is */ 7134 memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu)); 7135 if (desc_buff && desc_op == UPIU_QUERY_OPCODE_READ_DESC) { 7136 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr + sizeof(*rsp_upiu); 7137 u16 resp_len = be16_to_cpu(lrbp->ucd_rsp_ptr->header 7138 .data_segment_length); 7139 7140 if (*buff_len >= resp_len) { 7141 memcpy(desc_buff, descp, resp_len); 7142 *buff_len = resp_len; 7143 } else { 7144 dev_warn(hba->dev, 7145 "%s: rsp size %d is bigger than buffer size %d", 7146 __func__, resp_len, *buff_len); 7147 *buff_len = 0; 7148 err = -EINVAL; 7149 } 7150 } 7151 ufshcd_add_query_upiu_trace(hba, err ? UFS_QUERY_ERR : UFS_QUERY_COMP, 7152 (struct utp_upiu_req *)lrbp->ucd_rsp_ptr); 7153 7154 up_read(&hba->clk_scaling_lock); 7155 return err; 7156 } 7157 7158 /** 7159 * ufshcd_exec_raw_upiu_cmd - API function for sending raw upiu commands 7160 * @hba: per-adapter instance 7161 * @req_upiu: upiu request 7162 * @rsp_upiu: upiu reply - only 8 DW as we do not support scsi commands 7163 * @msgcode: message code, one of UPIU Transaction Codes Initiator to Target 7164 * @desc_buff: pointer to descriptor buffer, NULL if NA 7165 * @buff_len: descriptor size, 0 if NA 7166 * @desc_op: descriptor operation 7167 * 7168 * Supports UTP Transfer requests (nop and query), and UTP Task 7169 * Management requests. 7170 * It is up to the caller to fill the upiu conent properly, as it will 7171 * be copied without any further input validations. 7172 * 7173 * Return: 0 upon success; < 0 upon failure. 7174 */ 7175 int ufshcd_exec_raw_upiu_cmd(struct ufs_hba *hba, 7176 struct utp_upiu_req *req_upiu, 7177 struct utp_upiu_req *rsp_upiu, 7178 enum upiu_request_transaction msgcode, 7179 u8 *desc_buff, int *buff_len, 7180 enum query_opcode desc_op) 7181 { 7182 int err; 7183 enum dev_cmd_type cmd_type = DEV_CMD_TYPE_QUERY; 7184 struct utp_task_req_desc treq = { }; 7185 enum utp_ocs ocs_value; 7186 u8 tm_f = req_upiu->header.tm_function; 7187 7188 switch (msgcode) { 7189 case UPIU_TRANSACTION_NOP_OUT: 7190 cmd_type = DEV_CMD_TYPE_NOP; 7191 fallthrough; 7192 case UPIU_TRANSACTION_QUERY_REQ: 7193 ufshcd_hold(hba); 7194 mutex_lock(&hba->dev_cmd.lock); 7195 err = ufshcd_issue_devman_upiu_cmd(hba, req_upiu, rsp_upiu, 7196 desc_buff, buff_len, 7197 cmd_type, desc_op); 7198 mutex_unlock(&hba->dev_cmd.lock); 7199 ufshcd_release(hba); 7200 7201 break; 7202 case UPIU_TRANSACTION_TASK_REQ: 7203 treq.header.interrupt = 1; 7204 treq.header.ocs = OCS_INVALID_COMMAND_STATUS; 7205 7206 memcpy(&treq.upiu_req, req_upiu, sizeof(*req_upiu)); 7207 7208 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_f); 7209 if (err == -ETIMEDOUT) 7210 break; 7211 7212 ocs_value = treq.header.ocs & MASK_OCS; 7213 if (ocs_value != OCS_SUCCESS) { 7214 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n", __func__, 7215 ocs_value); 7216 break; 7217 } 7218 7219 memcpy(rsp_upiu, &treq.upiu_rsp, sizeof(*rsp_upiu)); 7220 7221 break; 7222 default: 7223 err = -EINVAL; 7224 7225 break; 7226 } 7227 7228 return err; 7229 } 7230 7231 /** 7232 * ufshcd_advanced_rpmb_req_handler - handle advanced RPMB request 7233 * @hba: per adapter instance 7234 * @req_upiu: upiu request 7235 * @rsp_upiu: upiu reply 7236 * @req_ehs: EHS field which contains Advanced RPMB Request Message 7237 * @rsp_ehs: EHS field which returns Advanced RPMB Response Message 7238 * @sg_cnt: The number of sg lists actually used 7239 * @sg_list: Pointer to SG list when DATA IN/OUT UPIU is required in ARPMB operation 7240 * @dir: DMA direction 7241 * 7242 * Return: zero on success, non-zero on failure. 7243 */ 7244 int ufshcd_advanced_rpmb_req_handler(struct ufs_hba *hba, struct utp_upiu_req *req_upiu, 7245 struct utp_upiu_req *rsp_upiu, struct ufs_ehs *req_ehs, 7246 struct ufs_ehs *rsp_ehs, int sg_cnt, struct scatterlist *sg_list, 7247 enum dma_data_direction dir) 7248 { 7249 DECLARE_COMPLETION_ONSTACK(wait); 7250 const u32 tag = hba->reserved_slot; 7251 struct ufshcd_lrb *lrbp; 7252 int err = 0; 7253 int result; 7254 u8 upiu_flags; 7255 u8 *ehs_data; 7256 u16 ehs_len; 7257 7258 /* Protects use of hba->reserved_slot. */ 7259 ufshcd_hold(hba); 7260 mutex_lock(&hba->dev_cmd.lock); 7261 down_read(&hba->clk_scaling_lock); 7262 7263 lrbp = &hba->lrb[tag]; 7264 lrbp->cmd = NULL; 7265 lrbp->task_tag = tag; 7266 lrbp->lun = UFS_UPIU_RPMB_WLUN; 7267 7268 lrbp->intr_cmd = true; 7269 ufshcd_prepare_lrbp_crypto(NULL, lrbp); 7270 hba->dev_cmd.type = DEV_CMD_TYPE_RPMB; 7271 7272 /* Advanced RPMB starts from UFS 4.0, so its command type is UTP_CMD_TYPE_UFS_STORAGE */ 7273 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE; 7274 7275 /* 7276 * According to UFSHCI 4.0 specification page 24, if EHSLUTRDS is 0, host controller takes 7277 * EHS length from CMD UPIU, and SW driver use EHS Length field in CMD UPIU. if it is 1, 7278 * HW controller takes EHS length from UTRD. 7279 */ 7280 if (hba->capabilities & MASK_EHSLUTRD_SUPPORTED) 7281 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, dir, 2); 7282 else 7283 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, dir, 0); 7284 7285 /* update the task tag */ 7286 req_upiu->header.task_tag = tag; 7287 7288 /* copy the UPIU(contains CDB) request as it is */ 7289 memcpy(lrbp->ucd_req_ptr, req_upiu, sizeof(*lrbp->ucd_req_ptr)); 7290 /* Copy EHS, starting with byte32, immediately after the CDB package */ 7291 memcpy(lrbp->ucd_req_ptr + 1, req_ehs, sizeof(*req_ehs)); 7292 7293 if (dir != DMA_NONE && sg_list) 7294 ufshcd_sgl_to_prdt(hba, lrbp, sg_cnt, sg_list); 7295 7296 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 7297 7298 hba->dev_cmd.complete = &wait; 7299 7300 ufshcd_send_command(hba, tag, hba->dev_cmd_queue); 7301 7302 err = ufshcd_wait_for_dev_cmd(hba, lrbp, ADVANCED_RPMB_REQ_TIMEOUT); 7303 7304 if (!err) { 7305 /* Just copy the upiu response as it is */ 7306 memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu)); 7307 /* Get the response UPIU result */ 7308 result = (lrbp->ucd_rsp_ptr->header.response << 8) | 7309 lrbp->ucd_rsp_ptr->header.status; 7310 7311 ehs_len = lrbp->ucd_rsp_ptr->header.ehs_length; 7312 /* 7313 * Since the bLength in EHS indicates the total size of the EHS Header and EHS Data 7314 * in 32 Byte units, the value of the bLength Request/Response for Advanced RPMB 7315 * Message is 02h 7316 */ 7317 if (ehs_len == 2 && rsp_ehs) { 7318 /* 7319 * ucd_rsp_ptr points to a buffer with a length of 512 bytes 7320 * (ALIGNED_UPIU_SIZE = 512), and the EHS data just starts from byte32 7321 */ 7322 ehs_data = (u8 *)lrbp->ucd_rsp_ptr + EHS_OFFSET_IN_RESPONSE; 7323 memcpy(rsp_ehs, ehs_data, ehs_len * 32); 7324 } 7325 } 7326 7327 up_read(&hba->clk_scaling_lock); 7328 mutex_unlock(&hba->dev_cmd.lock); 7329 ufshcd_release(hba); 7330 return err ? : result; 7331 } 7332 7333 /** 7334 * ufshcd_eh_device_reset_handler() - Reset a single logical unit. 7335 * @cmd: SCSI command pointer 7336 * 7337 * Return: SUCCESS or FAILED. 7338 */ 7339 static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd) 7340 { 7341 unsigned long flags, pending_reqs = 0, not_cleared = 0; 7342 struct Scsi_Host *host; 7343 struct ufs_hba *hba; 7344 struct ufs_hw_queue *hwq; 7345 struct ufshcd_lrb *lrbp; 7346 u32 pos, not_cleared_mask = 0; 7347 int err; 7348 u8 resp = 0xF, lun; 7349 7350 host = cmd->device->host; 7351 hba = shost_priv(host); 7352 7353 lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun); 7354 err = ufshcd_issue_tm_cmd(hba, lun, 0, UFS_LOGICAL_RESET, &resp); 7355 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) { 7356 if (!err) 7357 err = resp; 7358 goto out; 7359 } 7360 7361 if (is_mcq_enabled(hba)) { 7362 for (pos = 0; pos < hba->nutrs; pos++) { 7363 lrbp = &hba->lrb[pos]; 7364 if (ufshcd_cmd_inflight(lrbp->cmd) && 7365 lrbp->lun == lun) { 7366 ufshcd_clear_cmd(hba, pos); 7367 hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(lrbp->cmd)); 7368 ufshcd_mcq_poll_cqe_lock(hba, hwq); 7369 } 7370 } 7371 err = 0; 7372 goto out; 7373 } 7374 7375 /* clear the commands that were pending for corresponding LUN */ 7376 spin_lock_irqsave(&hba->outstanding_lock, flags); 7377 for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) 7378 if (hba->lrb[pos].lun == lun) 7379 __set_bit(pos, &pending_reqs); 7380 hba->outstanding_reqs &= ~pending_reqs; 7381 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 7382 7383 for_each_set_bit(pos, &pending_reqs, hba->nutrs) { 7384 if (ufshcd_clear_cmd(hba, pos) < 0) { 7385 spin_lock_irqsave(&hba->outstanding_lock, flags); 7386 not_cleared = 1U << pos & 7387 ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 7388 hba->outstanding_reqs |= not_cleared; 7389 not_cleared_mask |= not_cleared; 7390 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 7391 7392 dev_err(hba->dev, "%s: failed to clear request %d\n", 7393 __func__, pos); 7394 } 7395 } 7396 __ufshcd_transfer_req_compl(hba, pending_reqs & ~not_cleared_mask); 7397 7398 out: 7399 hba->req_abort_count = 0; 7400 ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, (u32)err); 7401 if (!err) { 7402 err = SUCCESS; 7403 } else { 7404 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err); 7405 err = FAILED; 7406 } 7407 return err; 7408 } 7409 7410 static void ufshcd_set_req_abort_skip(struct ufs_hba *hba, unsigned long bitmap) 7411 { 7412 struct ufshcd_lrb *lrbp; 7413 int tag; 7414 7415 for_each_set_bit(tag, &bitmap, hba->nutrs) { 7416 lrbp = &hba->lrb[tag]; 7417 lrbp->req_abort_skip = true; 7418 } 7419 } 7420 7421 /** 7422 * ufshcd_try_to_abort_task - abort a specific task 7423 * @hba: Pointer to adapter instance 7424 * @tag: Task tag/index to be aborted 7425 * 7426 * Abort the pending command in device by sending UFS_ABORT_TASK task management 7427 * command, and in host controller by clearing the door-bell register. There can 7428 * be race between controller sending the command to the device while abort is 7429 * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is 7430 * really issued and then try to abort it. 7431 * 7432 * Return: zero on success, non-zero on failure. 7433 */ 7434 int ufshcd_try_to_abort_task(struct ufs_hba *hba, int tag) 7435 { 7436 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 7437 int err = 0; 7438 int poll_cnt; 7439 u8 resp = 0xF; 7440 u32 reg; 7441 7442 for (poll_cnt = 100; poll_cnt; poll_cnt--) { 7443 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag, 7444 UFS_QUERY_TASK, &resp); 7445 if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) { 7446 /* cmd pending in the device */ 7447 dev_err(hba->dev, "%s: cmd pending in the device. tag = %d\n", 7448 __func__, tag); 7449 break; 7450 } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) { 7451 /* 7452 * cmd not pending in the device, check if it is 7453 * in transition. 7454 */ 7455 dev_err(hba->dev, "%s: cmd at tag %d not pending in the device.\n", 7456 __func__, tag); 7457 if (is_mcq_enabled(hba)) { 7458 /* MCQ mode */ 7459 if (ufshcd_cmd_inflight(lrbp->cmd)) { 7460 /* sleep for max. 200us same delay as in SDB mode */ 7461 usleep_range(100, 200); 7462 continue; 7463 } 7464 /* command completed already */ 7465 dev_err(hba->dev, "%s: cmd at tag=%d is cleared.\n", 7466 __func__, tag); 7467 goto out; 7468 } 7469 7470 /* Single Doorbell Mode */ 7471 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 7472 if (reg & (1 << tag)) { 7473 /* sleep for max. 200us to stabilize */ 7474 usleep_range(100, 200); 7475 continue; 7476 } 7477 /* command completed already */ 7478 dev_err(hba->dev, "%s: cmd at tag %d successfully cleared from DB.\n", 7479 __func__, tag); 7480 goto out; 7481 } else { 7482 dev_err(hba->dev, 7483 "%s: no response from device. tag = %d, err %d\n", 7484 __func__, tag, err); 7485 if (!err) 7486 err = resp; /* service response error */ 7487 goto out; 7488 } 7489 } 7490 7491 if (!poll_cnt) { 7492 err = -EBUSY; 7493 goto out; 7494 } 7495 7496 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag, 7497 UFS_ABORT_TASK, &resp); 7498 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) { 7499 if (!err) { 7500 err = resp; /* service response error */ 7501 dev_err(hba->dev, "%s: issued. tag = %d, err %d\n", 7502 __func__, tag, err); 7503 } 7504 goto out; 7505 } 7506 7507 err = ufshcd_clear_cmd(hba, tag); 7508 if (err) 7509 dev_err(hba->dev, "%s: Failed clearing cmd at tag %d, err %d\n", 7510 __func__, tag, err); 7511 7512 out: 7513 return err; 7514 } 7515 7516 /** 7517 * ufshcd_abort - scsi host template eh_abort_handler callback 7518 * @cmd: SCSI command pointer 7519 * 7520 * Return: SUCCESS or FAILED. 7521 */ 7522 static int ufshcd_abort(struct scsi_cmnd *cmd) 7523 { 7524 struct Scsi_Host *host = cmd->device->host; 7525 struct ufs_hba *hba = shost_priv(host); 7526 int tag = scsi_cmd_to_rq(cmd)->tag; 7527 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 7528 unsigned long flags; 7529 int err = FAILED; 7530 bool outstanding; 7531 u32 reg; 7532 7533 WARN_ONCE(tag < 0, "Invalid tag %d\n", tag); 7534 7535 ufshcd_hold(hba); 7536 7537 if (!is_mcq_enabled(hba)) { 7538 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 7539 if (!test_bit(tag, &hba->outstanding_reqs)) { 7540 /* If command is already aborted/completed, return FAILED. */ 7541 dev_err(hba->dev, 7542 "%s: cmd at tag %d already completed, outstanding=0x%lx, doorbell=0x%x\n", 7543 __func__, tag, hba->outstanding_reqs, reg); 7544 goto release; 7545 } 7546 } 7547 7548 /* Print Transfer Request of aborted task */ 7549 dev_info(hba->dev, "%s: Device abort task at tag %d\n", __func__, tag); 7550 7551 /* 7552 * Print detailed info about aborted request. 7553 * As more than one request might get aborted at the same time, 7554 * print full information only for the first aborted request in order 7555 * to reduce repeated printouts. For other aborted requests only print 7556 * basic details. 7557 */ 7558 scsi_print_command(cmd); 7559 if (!hba->req_abort_count) { 7560 ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, tag); 7561 ufshcd_print_evt_hist(hba); 7562 ufshcd_print_host_state(hba); 7563 ufshcd_print_pwr_info(hba); 7564 ufshcd_print_tr(hba, tag, true); 7565 } else { 7566 ufshcd_print_tr(hba, tag, false); 7567 } 7568 hba->req_abort_count++; 7569 7570 if (!is_mcq_enabled(hba) && !(reg & (1 << tag))) { 7571 /* only execute this code in single doorbell mode */ 7572 dev_err(hba->dev, 7573 "%s: cmd was completed, but without a notifying intr, tag = %d", 7574 __func__, tag); 7575 __ufshcd_transfer_req_compl(hba, 1UL << tag); 7576 goto release; 7577 } 7578 7579 /* 7580 * Task abort to the device W-LUN is illegal. When this command 7581 * will fail, due to spec violation, scsi err handling next step 7582 * will be to send LU reset which, again, is a spec violation. 7583 * To avoid these unnecessary/illegal steps, first we clean up 7584 * the lrb taken by this cmd and re-set it in outstanding_reqs, 7585 * then queue the eh_work and bail. 7586 */ 7587 if (lrbp->lun == UFS_UPIU_UFS_DEVICE_WLUN) { 7588 ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, lrbp->lun); 7589 7590 spin_lock_irqsave(host->host_lock, flags); 7591 hba->force_reset = true; 7592 ufshcd_schedule_eh_work(hba); 7593 spin_unlock_irqrestore(host->host_lock, flags); 7594 goto release; 7595 } 7596 7597 if (is_mcq_enabled(hba)) { 7598 /* MCQ mode. Branch off to handle abort for mcq mode */ 7599 err = ufshcd_mcq_abort(cmd); 7600 goto release; 7601 } 7602 7603 /* Skip task abort in case previous aborts failed and report failure */ 7604 if (lrbp->req_abort_skip) { 7605 dev_err(hba->dev, "%s: skipping abort\n", __func__); 7606 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs); 7607 goto release; 7608 } 7609 7610 err = ufshcd_try_to_abort_task(hba, tag); 7611 if (err) { 7612 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err); 7613 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs); 7614 err = FAILED; 7615 goto release; 7616 } 7617 7618 /* 7619 * Clear the corresponding bit from outstanding_reqs since the command 7620 * has been aborted successfully. 7621 */ 7622 spin_lock_irqsave(&hba->outstanding_lock, flags); 7623 outstanding = __test_and_clear_bit(tag, &hba->outstanding_reqs); 7624 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 7625 7626 if (outstanding) 7627 ufshcd_release_scsi_cmd(hba, lrbp); 7628 7629 err = SUCCESS; 7630 7631 release: 7632 /* Matches the ufshcd_hold() call at the start of this function. */ 7633 ufshcd_release(hba); 7634 return err; 7635 } 7636 7637 /** 7638 * ufshcd_host_reset_and_restore - reset and restore host controller 7639 * @hba: per-adapter instance 7640 * 7641 * Note that host controller reset may issue DME_RESET to 7642 * local and remote (device) Uni-Pro stack and the attributes 7643 * are reset to default state. 7644 * 7645 * Return: zero on success, non-zero on failure. 7646 */ 7647 static int ufshcd_host_reset_and_restore(struct ufs_hba *hba) 7648 { 7649 int err; 7650 7651 /* 7652 * Stop the host controller and complete the requests 7653 * cleared by h/w 7654 */ 7655 ufshcd_hba_stop(hba); 7656 hba->silence_err_logs = true; 7657 ufshcd_complete_requests(hba, true); 7658 hba->silence_err_logs = false; 7659 7660 /* scale up clocks to max frequency before full reinitialization */ 7661 ufshcd_scale_clks(hba, true); 7662 7663 err = ufshcd_hba_enable(hba); 7664 7665 /* Establish the link again and restore the device */ 7666 if (!err) 7667 err = ufshcd_probe_hba(hba, false); 7668 7669 if (err) 7670 dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err); 7671 ufshcd_update_evt_hist(hba, UFS_EVT_HOST_RESET, (u32)err); 7672 return err; 7673 } 7674 7675 /** 7676 * ufshcd_reset_and_restore - reset and re-initialize host/device 7677 * @hba: per-adapter instance 7678 * 7679 * Reset and recover device, host and re-establish link. This 7680 * is helpful to recover the communication in fatal error conditions. 7681 * 7682 * Return: zero on success, non-zero on failure. 7683 */ 7684 static int ufshcd_reset_and_restore(struct ufs_hba *hba) 7685 { 7686 u32 saved_err = 0; 7687 u32 saved_uic_err = 0; 7688 int err = 0; 7689 unsigned long flags; 7690 int retries = MAX_HOST_RESET_RETRIES; 7691 7692 spin_lock_irqsave(hba->host->host_lock, flags); 7693 do { 7694 /* 7695 * This is a fresh start, cache and clear saved error first, 7696 * in case new error generated during reset and restore. 7697 */ 7698 saved_err |= hba->saved_err; 7699 saved_uic_err |= hba->saved_uic_err; 7700 hba->saved_err = 0; 7701 hba->saved_uic_err = 0; 7702 hba->force_reset = false; 7703 hba->ufshcd_state = UFSHCD_STATE_RESET; 7704 spin_unlock_irqrestore(hba->host->host_lock, flags); 7705 7706 /* Reset the attached device */ 7707 ufshcd_device_reset(hba); 7708 7709 err = ufshcd_host_reset_and_restore(hba); 7710 7711 spin_lock_irqsave(hba->host->host_lock, flags); 7712 if (err) 7713 continue; 7714 /* Do not exit unless operational or dead */ 7715 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL && 7716 hba->ufshcd_state != UFSHCD_STATE_ERROR && 7717 hba->ufshcd_state != UFSHCD_STATE_EH_SCHEDULED_NON_FATAL) 7718 err = -EAGAIN; 7719 } while (err && --retries); 7720 7721 /* 7722 * Inform scsi mid-layer that we did reset and allow to handle 7723 * Unit Attention properly. 7724 */ 7725 scsi_report_bus_reset(hba->host, 0); 7726 if (err) { 7727 hba->ufshcd_state = UFSHCD_STATE_ERROR; 7728 hba->saved_err |= saved_err; 7729 hba->saved_uic_err |= saved_uic_err; 7730 } 7731 spin_unlock_irqrestore(hba->host->host_lock, flags); 7732 7733 return err; 7734 } 7735 7736 /** 7737 * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer 7738 * @cmd: SCSI command pointer 7739 * 7740 * Return: SUCCESS or FAILED. 7741 */ 7742 static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd) 7743 { 7744 int err = SUCCESS; 7745 unsigned long flags; 7746 struct ufs_hba *hba; 7747 7748 hba = shost_priv(cmd->device->host); 7749 7750 spin_lock_irqsave(hba->host->host_lock, flags); 7751 hba->force_reset = true; 7752 ufshcd_schedule_eh_work(hba); 7753 dev_err(hba->dev, "%s: reset in progress - 1\n", __func__); 7754 spin_unlock_irqrestore(hba->host->host_lock, flags); 7755 7756 flush_work(&hba->eh_work); 7757 7758 spin_lock_irqsave(hba->host->host_lock, flags); 7759 if (hba->ufshcd_state == UFSHCD_STATE_ERROR) 7760 err = FAILED; 7761 spin_unlock_irqrestore(hba->host->host_lock, flags); 7762 7763 return err; 7764 } 7765 7766 /** 7767 * ufshcd_get_max_icc_level - calculate the ICC level 7768 * @sup_curr_uA: max. current supported by the regulator 7769 * @start_scan: row at the desc table to start scan from 7770 * @buff: power descriptor buffer 7771 * 7772 * Return: calculated max ICC level for specific regulator. 7773 */ 7774 static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan, 7775 const char *buff) 7776 { 7777 int i; 7778 int curr_uA; 7779 u16 data; 7780 u16 unit; 7781 7782 for (i = start_scan; i >= 0; i--) { 7783 data = get_unaligned_be16(&buff[2 * i]); 7784 unit = (data & ATTR_ICC_LVL_UNIT_MASK) >> 7785 ATTR_ICC_LVL_UNIT_OFFSET; 7786 curr_uA = data & ATTR_ICC_LVL_VALUE_MASK; 7787 switch (unit) { 7788 case UFSHCD_NANO_AMP: 7789 curr_uA = curr_uA / 1000; 7790 break; 7791 case UFSHCD_MILI_AMP: 7792 curr_uA = curr_uA * 1000; 7793 break; 7794 case UFSHCD_AMP: 7795 curr_uA = curr_uA * 1000 * 1000; 7796 break; 7797 case UFSHCD_MICRO_AMP: 7798 default: 7799 break; 7800 } 7801 if (sup_curr_uA >= curr_uA) 7802 break; 7803 } 7804 if (i < 0) { 7805 i = 0; 7806 pr_err("%s: Couldn't find valid icc_level = %d", __func__, i); 7807 } 7808 7809 return (u32)i; 7810 } 7811 7812 /** 7813 * ufshcd_find_max_sup_active_icc_level - calculate the max ICC level 7814 * In case regulators are not initialized we'll return 0 7815 * @hba: per-adapter instance 7816 * @desc_buf: power descriptor buffer to extract ICC levels from. 7817 * 7818 * Return: calculated ICC level. 7819 */ 7820 static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba, 7821 const u8 *desc_buf) 7822 { 7823 u32 icc_level = 0; 7824 7825 if (!hba->vreg_info.vcc || !hba->vreg_info.vccq || 7826 !hba->vreg_info.vccq2) { 7827 /* 7828 * Using dev_dbg to avoid messages during runtime PM to avoid 7829 * never-ending cycles of messages written back to storage by 7830 * user space causing runtime resume, causing more messages and 7831 * so on. 7832 */ 7833 dev_dbg(hba->dev, 7834 "%s: Regulator capability was not set, actvIccLevel=%d", 7835 __func__, icc_level); 7836 goto out; 7837 } 7838 7839 if (hba->vreg_info.vcc->max_uA) 7840 icc_level = ufshcd_get_max_icc_level( 7841 hba->vreg_info.vcc->max_uA, 7842 POWER_DESC_MAX_ACTV_ICC_LVLS - 1, 7843 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]); 7844 7845 if (hba->vreg_info.vccq->max_uA) 7846 icc_level = ufshcd_get_max_icc_level( 7847 hba->vreg_info.vccq->max_uA, 7848 icc_level, 7849 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]); 7850 7851 if (hba->vreg_info.vccq2->max_uA) 7852 icc_level = ufshcd_get_max_icc_level( 7853 hba->vreg_info.vccq2->max_uA, 7854 icc_level, 7855 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]); 7856 out: 7857 return icc_level; 7858 } 7859 7860 static void ufshcd_set_active_icc_lvl(struct ufs_hba *hba) 7861 { 7862 int ret; 7863 u8 *desc_buf; 7864 u32 icc_level; 7865 7866 desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL); 7867 if (!desc_buf) 7868 return; 7869 7870 ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_POWER, 0, 0, 7871 desc_buf, QUERY_DESC_MAX_SIZE); 7872 if (ret) { 7873 dev_err(hba->dev, 7874 "%s: Failed reading power descriptor ret = %d", 7875 __func__, ret); 7876 goto out; 7877 } 7878 7879 icc_level = ufshcd_find_max_sup_active_icc_level(hba, desc_buf); 7880 dev_dbg(hba->dev, "%s: setting icc_level 0x%x", __func__, icc_level); 7881 7882 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, 7883 QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0, &icc_level); 7884 7885 if (ret) 7886 dev_err(hba->dev, 7887 "%s: Failed configuring bActiveICCLevel = %d ret = %d", 7888 __func__, icc_level, ret); 7889 7890 out: 7891 kfree(desc_buf); 7892 } 7893 7894 static inline void ufshcd_blk_pm_runtime_init(struct scsi_device *sdev) 7895 { 7896 scsi_autopm_get_device(sdev); 7897 blk_pm_runtime_init(sdev->request_queue, &sdev->sdev_gendev); 7898 if (sdev->rpm_autosuspend) 7899 pm_runtime_set_autosuspend_delay(&sdev->sdev_gendev, 7900 RPM_AUTOSUSPEND_DELAY_MS); 7901 scsi_autopm_put_device(sdev); 7902 } 7903 7904 /** 7905 * ufshcd_scsi_add_wlus - Adds required W-LUs 7906 * @hba: per-adapter instance 7907 * 7908 * UFS device specification requires the UFS devices to support 4 well known 7909 * logical units: 7910 * "REPORT_LUNS" (address: 01h) 7911 * "UFS Device" (address: 50h) 7912 * "RPMB" (address: 44h) 7913 * "BOOT" (address: 30h) 7914 * UFS device's power management needs to be controlled by "POWER CONDITION" 7915 * field of SSU (START STOP UNIT) command. But this "power condition" field 7916 * will take effect only when its sent to "UFS device" well known logical unit 7917 * hence we require the scsi_device instance to represent this logical unit in 7918 * order for the UFS host driver to send the SSU command for power management. 7919 * 7920 * We also require the scsi_device instance for "RPMB" (Replay Protected Memory 7921 * Block) LU so user space process can control this LU. User space may also 7922 * want to have access to BOOT LU. 7923 * 7924 * This function adds scsi device instances for each of all well known LUs 7925 * (except "REPORT LUNS" LU). 7926 * 7927 * Return: zero on success (all required W-LUs are added successfully), 7928 * non-zero error value on failure (if failed to add any of the required W-LU). 7929 */ 7930 static int ufshcd_scsi_add_wlus(struct ufs_hba *hba) 7931 { 7932 int ret = 0; 7933 struct scsi_device *sdev_boot, *sdev_rpmb; 7934 7935 hba->ufs_device_wlun = __scsi_add_device(hba->host, 0, 0, 7936 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL); 7937 if (IS_ERR(hba->ufs_device_wlun)) { 7938 ret = PTR_ERR(hba->ufs_device_wlun); 7939 hba->ufs_device_wlun = NULL; 7940 goto out; 7941 } 7942 scsi_device_put(hba->ufs_device_wlun); 7943 7944 sdev_rpmb = __scsi_add_device(hba->host, 0, 0, 7945 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL); 7946 if (IS_ERR(sdev_rpmb)) { 7947 ret = PTR_ERR(sdev_rpmb); 7948 goto remove_ufs_device_wlun; 7949 } 7950 ufshcd_blk_pm_runtime_init(sdev_rpmb); 7951 scsi_device_put(sdev_rpmb); 7952 7953 sdev_boot = __scsi_add_device(hba->host, 0, 0, 7954 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL); 7955 if (IS_ERR(sdev_boot)) { 7956 dev_err(hba->dev, "%s: BOOT WLUN not found\n", __func__); 7957 } else { 7958 ufshcd_blk_pm_runtime_init(sdev_boot); 7959 scsi_device_put(sdev_boot); 7960 } 7961 goto out; 7962 7963 remove_ufs_device_wlun: 7964 scsi_remove_device(hba->ufs_device_wlun); 7965 out: 7966 return ret; 7967 } 7968 7969 static void ufshcd_wb_probe(struct ufs_hba *hba, const u8 *desc_buf) 7970 { 7971 struct ufs_dev_info *dev_info = &hba->dev_info; 7972 u8 lun; 7973 u32 d_lu_wb_buf_alloc; 7974 u32 ext_ufs_feature; 7975 7976 if (!ufshcd_is_wb_allowed(hba)) 7977 return; 7978 7979 /* 7980 * Probe WB only for UFS-2.2 and UFS-3.1 (and later) devices or 7981 * UFS devices with quirk UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES 7982 * enabled 7983 */ 7984 if (!(dev_info->wspecversion >= 0x310 || 7985 dev_info->wspecversion == 0x220 || 7986 (hba->dev_quirks & UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES))) 7987 goto wb_disabled; 7988 7989 ext_ufs_feature = get_unaligned_be32(desc_buf + 7990 DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP); 7991 7992 if (!(ext_ufs_feature & UFS_DEV_WRITE_BOOSTER_SUP)) 7993 goto wb_disabled; 7994 7995 /* 7996 * WB may be supported but not configured while provisioning. The spec 7997 * says, in dedicated wb buffer mode, a max of 1 lun would have wb 7998 * buffer configured. 7999 */ 8000 dev_info->wb_buffer_type = desc_buf[DEVICE_DESC_PARAM_WB_TYPE]; 8001 8002 dev_info->b_presrv_uspc_en = 8003 desc_buf[DEVICE_DESC_PARAM_WB_PRESRV_USRSPC_EN]; 8004 8005 if (dev_info->wb_buffer_type == WB_BUF_MODE_SHARED) { 8006 if (!get_unaligned_be32(desc_buf + 8007 DEVICE_DESC_PARAM_WB_SHARED_ALLOC_UNITS)) 8008 goto wb_disabled; 8009 } else { 8010 for (lun = 0; lun < UFS_UPIU_MAX_WB_LUN_ID; lun++) { 8011 d_lu_wb_buf_alloc = 0; 8012 ufshcd_read_unit_desc_param(hba, 8013 lun, 8014 UNIT_DESC_PARAM_WB_BUF_ALLOC_UNITS, 8015 (u8 *)&d_lu_wb_buf_alloc, 8016 sizeof(d_lu_wb_buf_alloc)); 8017 if (d_lu_wb_buf_alloc) { 8018 dev_info->wb_dedicated_lu = lun; 8019 break; 8020 } 8021 } 8022 8023 if (!d_lu_wb_buf_alloc) 8024 goto wb_disabled; 8025 } 8026 8027 if (!ufshcd_is_wb_buf_lifetime_available(hba)) 8028 goto wb_disabled; 8029 8030 return; 8031 8032 wb_disabled: 8033 hba->caps &= ~UFSHCD_CAP_WB_EN; 8034 } 8035 8036 static void ufshcd_temp_notif_probe(struct ufs_hba *hba, const u8 *desc_buf) 8037 { 8038 struct ufs_dev_info *dev_info = &hba->dev_info; 8039 u32 ext_ufs_feature; 8040 u8 mask = 0; 8041 8042 if (!(hba->caps & UFSHCD_CAP_TEMP_NOTIF) || dev_info->wspecversion < 0x300) 8043 return; 8044 8045 ext_ufs_feature = get_unaligned_be32(desc_buf + DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP); 8046 8047 if (ext_ufs_feature & UFS_DEV_LOW_TEMP_NOTIF) 8048 mask |= MASK_EE_TOO_LOW_TEMP; 8049 8050 if (ext_ufs_feature & UFS_DEV_HIGH_TEMP_NOTIF) 8051 mask |= MASK_EE_TOO_HIGH_TEMP; 8052 8053 if (mask) { 8054 ufshcd_enable_ee(hba, mask); 8055 ufs_hwmon_probe(hba, mask); 8056 } 8057 } 8058 8059 static void ufshcd_ext_iid_probe(struct ufs_hba *hba, u8 *desc_buf) 8060 { 8061 struct ufs_dev_info *dev_info = &hba->dev_info; 8062 u32 ext_ufs_feature; 8063 u32 ext_iid_en = 0; 8064 int err; 8065 8066 /* Only UFS-4.0 and above may support EXT_IID */ 8067 if (dev_info->wspecversion < 0x400) 8068 goto out; 8069 8070 ext_ufs_feature = get_unaligned_be32(desc_buf + 8071 DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP); 8072 if (!(ext_ufs_feature & UFS_DEV_EXT_IID_SUP)) 8073 goto out; 8074 8075 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 8076 QUERY_ATTR_IDN_EXT_IID_EN, 0, 0, &ext_iid_en); 8077 if (err) 8078 dev_err(hba->dev, "failed reading bEXTIIDEn. err = %d\n", err); 8079 8080 out: 8081 dev_info->b_ext_iid_en = ext_iid_en; 8082 } 8083 8084 void ufshcd_fixup_dev_quirks(struct ufs_hba *hba, 8085 const struct ufs_dev_quirk *fixups) 8086 { 8087 const struct ufs_dev_quirk *f; 8088 struct ufs_dev_info *dev_info = &hba->dev_info; 8089 8090 if (!fixups) 8091 return; 8092 8093 for (f = fixups; f->quirk; f++) { 8094 if ((f->wmanufacturerid == dev_info->wmanufacturerid || 8095 f->wmanufacturerid == UFS_ANY_VENDOR) && 8096 ((dev_info->model && 8097 STR_PRFX_EQUAL(f->model, dev_info->model)) || 8098 !strcmp(f->model, UFS_ANY_MODEL))) 8099 hba->dev_quirks |= f->quirk; 8100 } 8101 } 8102 EXPORT_SYMBOL_GPL(ufshcd_fixup_dev_quirks); 8103 8104 static void ufs_fixup_device_setup(struct ufs_hba *hba) 8105 { 8106 /* fix by general quirk table */ 8107 ufshcd_fixup_dev_quirks(hba, ufs_fixups); 8108 8109 /* allow vendors to fix quirks */ 8110 ufshcd_vops_fixup_dev_quirks(hba); 8111 } 8112 8113 static int ufs_get_device_desc(struct ufs_hba *hba) 8114 { 8115 int err; 8116 u8 model_index; 8117 u8 *desc_buf; 8118 struct ufs_dev_info *dev_info = &hba->dev_info; 8119 8120 desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL); 8121 if (!desc_buf) { 8122 err = -ENOMEM; 8123 goto out; 8124 } 8125 8126 err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_DEVICE, 0, 0, desc_buf, 8127 QUERY_DESC_MAX_SIZE); 8128 if (err) { 8129 dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n", 8130 __func__, err); 8131 goto out; 8132 } 8133 8134 /* 8135 * getting vendor (manufacturerID) and Bank Index in big endian 8136 * format 8137 */ 8138 dev_info->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 | 8139 desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1]; 8140 8141 /* getting Specification Version in big endian format */ 8142 dev_info->wspecversion = desc_buf[DEVICE_DESC_PARAM_SPEC_VER] << 8 | 8143 desc_buf[DEVICE_DESC_PARAM_SPEC_VER + 1]; 8144 dev_info->bqueuedepth = desc_buf[DEVICE_DESC_PARAM_Q_DPTH]; 8145 8146 model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME]; 8147 8148 err = ufshcd_read_string_desc(hba, model_index, 8149 &dev_info->model, SD_ASCII_STD); 8150 if (err < 0) { 8151 dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n", 8152 __func__, err); 8153 goto out; 8154 } 8155 8156 hba->luns_avail = desc_buf[DEVICE_DESC_PARAM_NUM_LU] + 8157 desc_buf[DEVICE_DESC_PARAM_NUM_WLU]; 8158 8159 ufs_fixup_device_setup(hba); 8160 8161 ufshcd_wb_probe(hba, desc_buf); 8162 8163 ufshcd_temp_notif_probe(hba, desc_buf); 8164 8165 if (hba->ext_iid_sup) 8166 ufshcd_ext_iid_probe(hba, desc_buf); 8167 8168 /* 8169 * ufshcd_read_string_desc returns size of the string 8170 * reset the error value 8171 */ 8172 err = 0; 8173 8174 out: 8175 kfree(desc_buf); 8176 return err; 8177 } 8178 8179 static void ufs_put_device_desc(struct ufs_hba *hba) 8180 { 8181 struct ufs_dev_info *dev_info = &hba->dev_info; 8182 8183 kfree(dev_info->model); 8184 dev_info->model = NULL; 8185 } 8186 8187 /** 8188 * ufshcd_tune_pa_tactivate - Tunes PA_TActivate of local UniPro 8189 * @hba: per-adapter instance 8190 * 8191 * PA_TActivate parameter can be tuned manually if UniPro version is less than 8192 * 1.61. PA_TActivate needs to be greater than or equal to peerM-PHY's 8193 * RX_MIN_ACTIVATETIME_CAPABILITY attribute. This optimal value can help reduce 8194 * the hibern8 exit latency. 8195 * 8196 * Return: zero on success, non-zero error value on failure. 8197 */ 8198 static int ufshcd_tune_pa_tactivate(struct ufs_hba *hba) 8199 { 8200 int ret = 0; 8201 u32 peer_rx_min_activatetime = 0, tuned_pa_tactivate; 8202 8203 ret = ufshcd_dme_peer_get(hba, 8204 UIC_ARG_MIB_SEL( 8205 RX_MIN_ACTIVATETIME_CAPABILITY, 8206 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)), 8207 &peer_rx_min_activatetime); 8208 if (ret) 8209 goto out; 8210 8211 /* make sure proper unit conversion is applied */ 8212 tuned_pa_tactivate = 8213 ((peer_rx_min_activatetime * RX_MIN_ACTIVATETIME_UNIT_US) 8214 / PA_TACTIVATE_TIME_UNIT_US); 8215 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 8216 tuned_pa_tactivate); 8217 8218 out: 8219 return ret; 8220 } 8221 8222 /** 8223 * ufshcd_tune_pa_hibern8time - Tunes PA_Hibern8Time of local UniPro 8224 * @hba: per-adapter instance 8225 * 8226 * PA_Hibern8Time parameter can be tuned manually if UniPro version is less than 8227 * 1.61. PA_Hibern8Time needs to be maximum of local M-PHY's 8228 * TX_HIBERN8TIME_CAPABILITY & peer M-PHY's RX_HIBERN8TIME_CAPABILITY. 8229 * This optimal value can help reduce the hibern8 exit latency. 8230 * 8231 * Return: zero on success, non-zero error value on failure. 8232 */ 8233 static int ufshcd_tune_pa_hibern8time(struct ufs_hba *hba) 8234 { 8235 int ret = 0; 8236 u32 local_tx_hibern8_time_cap = 0, peer_rx_hibern8_time_cap = 0; 8237 u32 max_hibern8_time, tuned_pa_hibern8time; 8238 8239 ret = ufshcd_dme_get(hba, 8240 UIC_ARG_MIB_SEL(TX_HIBERN8TIME_CAPABILITY, 8241 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), 8242 &local_tx_hibern8_time_cap); 8243 if (ret) 8244 goto out; 8245 8246 ret = ufshcd_dme_peer_get(hba, 8247 UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAPABILITY, 8248 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)), 8249 &peer_rx_hibern8_time_cap); 8250 if (ret) 8251 goto out; 8252 8253 max_hibern8_time = max(local_tx_hibern8_time_cap, 8254 peer_rx_hibern8_time_cap); 8255 /* make sure proper unit conversion is applied */ 8256 tuned_pa_hibern8time = ((max_hibern8_time * HIBERN8TIME_UNIT_US) 8257 / PA_HIBERN8_TIME_UNIT_US); 8258 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME), 8259 tuned_pa_hibern8time); 8260 out: 8261 return ret; 8262 } 8263 8264 /** 8265 * ufshcd_quirk_tune_host_pa_tactivate - Ensures that host PA_TACTIVATE is 8266 * less than device PA_TACTIVATE time. 8267 * @hba: per-adapter instance 8268 * 8269 * Some UFS devices require host PA_TACTIVATE to be lower than device 8270 * PA_TACTIVATE, we need to enable UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE quirk 8271 * for such devices. 8272 * 8273 * Return: zero on success, non-zero error value on failure. 8274 */ 8275 static int ufshcd_quirk_tune_host_pa_tactivate(struct ufs_hba *hba) 8276 { 8277 int ret = 0; 8278 u32 granularity, peer_granularity; 8279 u32 pa_tactivate, peer_pa_tactivate; 8280 u32 pa_tactivate_us, peer_pa_tactivate_us; 8281 static const u8 gran_to_us_table[] = {1, 4, 8, 16, 32, 100}; 8282 8283 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY), 8284 &granularity); 8285 if (ret) 8286 goto out; 8287 8288 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY), 8289 &peer_granularity); 8290 if (ret) 8291 goto out; 8292 8293 if ((granularity < PA_GRANULARITY_MIN_VAL) || 8294 (granularity > PA_GRANULARITY_MAX_VAL)) { 8295 dev_err(hba->dev, "%s: invalid host PA_GRANULARITY %d", 8296 __func__, granularity); 8297 return -EINVAL; 8298 } 8299 8300 if ((peer_granularity < PA_GRANULARITY_MIN_VAL) || 8301 (peer_granularity > PA_GRANULARITY_MAX_VAL)) { 8302 dev_err(hba->dev, "%s: invalid device PA_GRANULARITY %d", 8303 __func__, peer_granularity); 8304 return -EINVAL; 8305 } 8306 8307 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate); 8308 if (ret) 8309 goto out; 8310 8311 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE), 8312 &peer_pa_tactivate); 8313 if (ret) 8314 goto out; 8315 8316 pa_tactivate_us = pa_tactivate * gran_to_us_table[granularity - 1]; 8317 peer_pa_tactivate_us = peer_pa_tactivate * 8318 gran_to_us_table[peer_granularity - 1]; 8319 8320 if (pa_tactivate_us >= peer_pa_tactivate_us) { 8321 u32 new_peer_pa_tactivate; 8322 8323 new_peer_pa_tactivate = pa_tactivate_us / 8324 gran_to_us_table[peer_granularity - 1]; 8325 new_peer_pa_tactivate++; 8326 ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 8327 new_peer_pa_tactivate); 8328 } 8329 8330 out: 8331 return ret; 8332 } 8333 8334 static void ufshcd_tune_unipro_params(struct ufs_hba *hba) 8335 { 8336 if (ufshcd_is_unipro_pa_params_tuning_req(hba)) { 8337 ufshcd_tune_pa_tactivate(hba); 8338 ufshcd_tune_pa_hibern8time(hba); 8339 } 8340 8341 ufshcd_vops_apply_dev_quirks(hba); 8342 8343 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TACTIVATE) 8344 /* set 1ms timeout for PA_TACTIVATE */ 8345 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 10); 8346 8347 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE) 8348 ufshcd_quirk_tune_host_pa_tactivate(hba); 8349 } 8350 8351 static void ufshcd_clear_dbg_ufs_stats(struct ufs_hba *hba) 8352 { 8353 hba->ufs_stats.hibern8_exit_cnt = 0; 8354 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0); 8355 hba->req_abort_count = 0; 8356 } 8357 8358 static int ufshcd_device_geo_params_init(struct ufs_hba *hba) 8359 { 8360 int err; 8361 u8 *desc_buf; 8362 8363 desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL); 8364 if (!desc_buf) { 8365 err = -ENOMEM; 8366 goto out; 8367 } 8368 8369 err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_GEOMETRY, 0, 0, 8370 desc_buf, QUERY_DESC_MAX_SIZE); 8371 if (err) { 8372 dev_err(hba->dev, "%s: Failed reading Geometry Desc. err = %d\n", 8373 __func__, err); 8374 goto out; 8375 } 8376 8377 if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 1) 8378 hba->dev_info.max_lu_supported = 32; 8379 else if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 0) 8380 hba->dev_info.max_lu_supported = 8; 8381 8382 out: 8383 kfree(desc_buf); 8384 return err; 8385 } 8386 8387 struct ufs_ref_clk { 8388 unsigned long freq_hz; 8389 enum ufs_ref_clk_freq val; 8390 }; 8391 8392 static const struct ufs_ref_clk ufs_ref_clk_freqs[] = { 8393 {19200000, REF_CLK_FREQ_19_2_MHZ}, 8394 {26000000, REF_CLK_FREQ_26_MHZ}, 8395 {38400000, REF_CLK_FREQ_38_4_MHZ}, 8396 {52000000, REF_CLK_FREQ_52_MHZ}, 8397 {0, REF_CLK_FREQ_INVAL}, 8398 }; 8399 8400 static enum ufs_ref_clk_freq 8401 ufs_get_bref_clk_from_hz(unsigned long freq) 8402 { 8403 int i; 8404 8405 for (i = 0; ufs_ref_clk_freqs[i].freq_hz; i++) 8406 if (ufs_ref_clk_freqs[i].freq_hz == freq) 8407 return ufs_ref_clk_freqs[i].val; 8408 8409 return REF_CLK_FREQ_INVAL; 8410 } 8411 8412 void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk) 8413 { 8414 unsigned long freq; 8415 8416 freq = clk_get_rate(refclk); 8417 8418 hba->dev_ref_clk_freq = 8419 ufs_get_bref_clk_from_hz(freq); 8420 8421 if (hba->dev_ref_clk_freq == REF_CLK_FREQ_INVAL) 8422 dev_err(hba->dev, 8423 "invalid ref_clk setting = %ld\n", freq); 8424 } 8425 8426 static int ufshcd_set_dev_ref_clk(struct ufs_hba *hba) 8427 { 8428 int err; 8429 u32 ref_clk; 8430 u32 freq = hba->dev_ref_clk_freq; 8431 8432 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 8433 QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &ref_clk); 8434 8435 if (err) { 8436 dev_err(hba->dev, "failed reading bRefClkFreq. err = %d\n", 8437 err); 8438 goto out; 8439 } 8440 8441 if (ref_clk == freq) 8442 goto out; /* nothing to update */ 8443 8444 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, 8445 QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &freq); 8446 8447 if (err) { 8448 dev_err(hba->dev, "bRefClkFreq setting to %lu Hz failed\n", 8449 ufs_ref_clk_freqs[freq].freq_hz); 8450 goto out; 8451 } 8452 8453 dev_dbg(hba->dev, "bRefClkFreq setting to %lu Hz succeeded\n", 8454 ufs_ref_clk_freqs[freq].freq_hz); 8455 8456 out: 8457 return err; 8458 } 8459 8460 static int ufshcd_device_params_init(struct ufs_hba *hba) 8461 { 8462 bool flag; 8463 int ret; 8464 8465 /* Init UFS geometry descriptor related parameters */ 8466 ret = ufshcd_device_geo_params_init(hba); 8467 if (ret) 8468 goto out; 8469 8470 /* Check and apply UFS device quirks */ 8471 ret = ufs_get_device_desc(hba); 8472 if (ret) { 8473 dev_err(hba->dev, "%s: Failed getting device info. err = %d\n", 8474 __func__, ret); 8475 goto out; 8476 } 8477 8478 ufshcd_get_ref_clk_gating_wait(hba); 8479 8480 if (!ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG, 8481 QUERY_FLAG_IDN_PWR_ON_WPE, 0, &flag)) 8482 hba->dev_info.f_power_on_wp_en = flag; 8483 8484 /* Probe maximum power mode co-supported by both UFS host and device */ 8485 if (ufshcd_get_max_pwr_mode(hba)) 8486 dev_err(hba->dev, 8487 "%s: Failed getting max supported power mode\n", 8488 __func__); 8489 out: 8490 return ret; 8491 } 8492 8493 static void ufshcd_set_timestamp_attr(struct ufs_hba *hba) 8494 { 8495 int err; 8496 struct ufs_query_req *request = NULL; 8497 struct ufs_query_res *response = NULL; 8498 struct ufs_dev_info *dev_info = &hba->dev_info; 8499 struct utp_upiu_query_v4_0 *upiu_data; 8500 8501 if (dev_info->wspecversion < 0x400) 8502 return; 8503 8504 ufshcd_hold(hba); 8505 8506 mutex_lock(&hba->dev_cmd.lock); 8507 8508 ufshcd_init_query(hba, &request, &response, 8509 UPIU_QUERY_OPCODE_WRITE_ATTR, 8510 QUERY_ATTR_IDN_TIMESTAMP, 0, 0); 8511 8512 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 8513 8514 upiu_data = (struct utp_upiu_query_v4_0 *)&request->upiu_req; 8515 8516 put_unaligned_be64(ktime_get_real_ns(), &upiu_data->osf3); 8517 8518 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT); 8519 8520 if (err) 8521 dev_err(hba->dev, "%s: failed to set timestamp %d\n", 8522 __func__, err); 8523 8524 mutex_unlock(&hba->dev_cmd.lock); 8525 ufshcd_release(hba); 8526 } 8527 8528 /** 8529 * ufshcd_add_lus - probe and add UFS logical units 8530 * @hba: per-adapter instance 8531 * 8532 * Return: 0 upon success; < 0 upon failure. 8533 */ 8534 static int ufshcd_add_lus(struct ufs_hba *hba) 8535 { 8536 int ret; 8537 8538 /* Add required well known logical units to scsi mid layer */ 8539 ret = ufshcd_scsi_add_wlus(hba); 8540 if (ret) 8541 goto out; 8542 8543 /* Initialize devfreq after UFS device is detected */ 8544 if (ufshcd_is_clkscaling_supported(hba)) { 8545 memcpy(&hba->clk_scaling.saved_pwr_info, 8546 &hba->pwr_info, 8547 sizeof(struct ufs_pa_layer_attr)); 8548 hba->clk_scaling.is_allowed = true; 8549 8550 ret = ufshcd_devfreq_init(hba); 8551 if (ret) 8552 goto out; 8553 8554 hba->clk_scaling.is_enabled = true; 8555 ufshcd_init_clk_scaling_sysfs(hba); 8556 } 8557 8558 ufs_bsg_probe(hba); 8559 scsi_scan_host(hba->host); 8560 8561 out: 8562 return ret; 8563 } 8564 8565 /* SDB - Single Doorbell */ 8566 static void ufshcd_release_sdb_queue(struct ufs_hba *hba, int nutrs) 8567 { 8568 size_t ucdl_size, utrdl_size; 8569 8570 ucdl_size = ufshcd_get_ucd_size(hba) * nutrs; 8571 dmam_free_coherent(hba->dev, ucdl_size, hba->ucdl_base_addr, 8572 hba->ucdl_dma_addr); 8573 8574 utrdl_size = sizeof(struct utp_transfer_req_desc) * nutrs; 8575 dmam_free_coherent(hba->dev, utrdl_size, hba->utrdl_base_addr, 8576 hba->utrdl_dma_addr); 8577 8578 devm_kfree(hba->dev, hba->lrb); 8579 } 8580 8581 static int ufshcd_alloc_mcq(struct ufs_hba *hba) 8582 { 8583 int ret; 8584 int old_nutrs = hba->nutrs; 8585 8586 ret = ufshcd_mcq_decide_queue_depth(hba); 8587 if (ret < 0) 8588 return ret; 8589 8590 hba->nutrs = ret; 8591 ret = ufshcd_mcq_init(hba); 8592 if (ret) 8593 goto err; 8594 8595 /* 8596 * Previously allocated memory for nutrs may not be enough in MCQ mode. 8597 * Number of supported tags in MCQ mode may be larger than SDB mode. 8598 */ 8599 if (hba->nutrs != old_nutrs) { 8600 ufshcd_release_sdb_queue(hba, old_nutrs); 8601 ret = ufshcd_memory_alloc(hba); 8602 if (ret) 8603 goto err; 8604 ufshcd_host_memory_configure(hba); 8605 } 8606 8607 ret = ufshcd_mcq_memory_alloc(hba); 8608 if (ret) 8609 goto err; 8610 8611 return 0; 8612 err: 8613 hba->nutrs = old_nutrs; 8614 return ret; 8615 } 8616 8617 static void ufshcd_config_mcq(struct ufs_hba *hba) 8618 { 8619 int ret; 8620 u32 intrs; 8621 8622 ret = ufshcd_mcq_vops_config_esi(hba); 8623 dev_info(hba->dev, "ESI %sconfigured\n", ret ? "is not " : ""); 8624 8625 intrs = UFSHCD_ENABLE_MCQ_INTRS; 8626 if (hba->quirks & UFSHCD_QUIRK_MCQ_BROKEN_INTR) 8627 intrs &= ~MCQ_CQ_EVENT_STATUS; 8628 ufshcd_enable_intr(hba, intrs); 8629 ufshcd_mcq_make_queues_operational(hba); 8630 ufshcd_mcq_config_mac(hba, hba->nutrs); 8631 8632 hba->host->can_queue = hba->nutrs - UFSHCD_NUM_RESERVED; 8633 hba->reserved_slot = hba->nutrs - UFSHCD_NUM_RESERVED; 8634 8635 /* Select MCQ mode */ 8636 ufshcd_writel(hba, ufshcd_readl(hba, REG_UFS_MEM_CFG) | 0x1, 8637 REG_UFS_MEM_CFG); 8638 hba->mcq_enabled = true; 8639 8640 dev_info(hba->dev, "MCQ configured, nr_queues=%d, io_queues=%d, read_queue=%d, poll_queues=%d, queue_depth=%d\n", 8641 hba->nr_hw_queues, hba->nr_queues[HCTX_TYPE_DEFAULT], 8642 hba->nr_queues[HCTX_TYPE_READ], hba->nr_queues[HCTX_TYPE_POLL], 8643 hba->nutrs); 8644 } 8645 8646 static int ufshcd_device_init(struct ufs_hba *hba, bool init_dev_params) 8647 { 8648 int ret; 8649 struct Scsi_Host *host = hba->host; 8650 8651 hba->ufshcd_state = UFSHCD_STATE_RESET; 8652 8653 ret = ufshcd_link_startup(hba); 8654 if (ret) 8655 return ret; 8656 8657 if (hba->quirks & UFSHCD_QUIRK_SKIP_PH_CONFIGURATION) 8658 return ret; 8659 8660 /* Debug counters initialization */ 8661 ufshcd_clear_dbg_ufs_stats(hba); 8662 8663 /* UniPro link is active now */ 8664 ufshcd_set_link_active(hba); 8665 8666 /* Reconfigure MCQ upon reset */ 8667 if (is_mcq_enabled(hba) && !init_dev_params) 8668 ufshcd_config_mcq(hba); 8669 8670 /* Verify device initialization by sending NOP OUT UPIU */ 8671 ret = ufshcd_verify_dev_init(hba); 8672 if (ret) 8673 return ret; 8674 8675 /* Initiate UFS initialization, and waiting until completion */ 8676 ret = ufshcd_complete_dev_init(hba); 8677 if (ret) 8678 return ret; 8679 8680 /* 8681 * Initialize UFS device parameters used by driver, these 8682 * parameters are associated with UFS descriptors. 8683 */ 8684 if (init_dev_params) { 8685 ret = ufshcd_device_params_init(hba); 8686 if (ret) 8687 return ret; 8688 if (is_mcq_supported(hba) && !hba->scsi_host_added) { 8689 ret = ufshcd_alloc_mcq(hba); 8690 if (!ret) { 8691 ufshcd_config_mcq(hba); 8692 } else { 8693 /* Continue with SDB mode */ 8694 use_mcq_mode = false; 8695 dev_err(hba->dev, "MCQ mode is disabled, err=%d\n", 8696 ret); 8697 } 8698 ret = scsi_add_host(host, hba->dev); 8699 if (ret) { 8700 dev_err(hba->dev, "scsi_add_host failed\n"); 8701 return ret; 8702 } 8703 hba->scsi_host_added = true; 8704 } else if (is_mcq_supported(hba)) { 8705 /* UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH is set */ 8706 ufshcd_config_mcq(hba); 8707 } 8708 } 8709 8710 ufshcd_tune_unipro_params(hba); 8711 8712 /* UFS device is also active now */ 8713 ufshcd_set_ufs_dev_active(hba); 8714 ufshcd_force_reset_auto_bkops(hba); 8715 8716 ufshcd_set_timestamp_attr(hba); 8717 8718 /* Gear up to HS gear if supported */ 8719 if (hba->max_pwr_info.is_valid) { 8720 /* 8721 * Set the right value to bRefClkFreq before attempting to 8722 * switch to HS gears. 8723 */ 8724 if (hba->dev_ref_clk_freq != REF_CLK_FREQ_INVAL) 8725 ufshcd_set_dev_ref_clk(hba); 8726 ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info); 8727 if (ret) { 8728 dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n", 8729 __func__, ret); 8730 return ret; 8731 } 8732 } 8733 8734 return 0; 8735 } 8736 8737 /** 8738 * ufshcd_probe_hba - probe hba to detect device and initialize it 8739 * @hba: per-adapter instance 8740 * @init_dev_params: whether or not to call ufshcd_device_params_init(). 8741 * 8742 * Execute link-startup and verify device initialization 8743 * 8744 * Return: 0 upon success; < 0 upon failure. 8745 */ 8746 static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params) 8747 { 8748 ktime_t start = ktime_get(); 8749 unsigned long flags; 8750 int ret; 8751 8752 ret = ufshcd_device_init(hba, init_dev_params); 8753 if (ret) 8754 goto out; 8755 8756 if (!hba->pm_op_in_progress && 8757 (hba->quirks & UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH)) { 8758 /* Reset the device and controller before doing reinit */ 8759 ufshcd_device_reset(hba); 8760 ufs_put_device_desc(hba); 8761 ufshcd_hba_stop(hba); 8762 ufshcd_vops_reinit_notify(hba); 8763 ret = ufshcd_hba_enable(hba); 8764 if (ret) { 8765 dev_err(hba->dev, "Host controller enable failed\n"); 8766 ufshcd_print_evt_hist(hba); 8767 ufshcd_print_host_state(hba); 8768 goto out; 8769 } 8770 8771 /* Reinit the device */ 8772 ret = ufshcd_device_init(hba, init_dev_params); 8773 if (ret) 8774 goto out; 8775 } 8776 8777 ufshcd_print_pwr_info(hba); 8778 8779 /* 8780 * bActiveICCLevel is volatile for UFS device (as per latest v2.1 spec) 8781 * and for removable UFS card as well, hence always set the parameter. 8782 * Note: Error handler may issue the device reset hence resetting 8783 * bActiveICCLevel as well so it is always safe to set this here. 8784 */ 8785 ufshcd_set_active_icc_lvl(hba); 8786 8787 /* Enable UFS Write Booster if supported */ 8788 ufshcd_configure_wb(hba); 8789 8790 if (hba->ee_usr_mask) 8791 ufshcd_write_ee_control(hba); 8792 /* Enable Auto-Hibernate if configured */ 8793 ufshcd_auto_hibern8_enable(hba); 8794 8795 out: 8796 spin_lock_irqsave(hba->host->host_lock, flags); 8797 if (ret) 8798 hba->ufshcd_state = UFSHCD_STATE_ERROR; 8799 else if (hba->ufshcd_state == UFSHCD_STATE_RESET) 8800 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL; 8801 spin_unlock_irqrestore(hba->host->host_lock, flags); 8802 8803 trace_ufshcd_init(dev_name(hba->dev), ret, 8804 ktime_to_us(ktime_sub(ktime_get(), start)), 8805 hba->curr_dev_pwr_mode, hba->uic_link_state); 8806 return ret; 8807 } 8808 8809 /** 8810 * ufshcd_async_scan - asynchronous execution for probing hba 8811 * @data: data pointer to pass to this function 8812 * @cookie: cookie data 8813 */ 8814 static void ufshcd_async_scan(void *data, async_cookie_t cookie) 8815 { 8816 struct ufs_hba *hba = (struct ufs_hba *)data; 8817 int ret; 8818 8819 down(&hba->host_sem); 8820 /* Initialize hba, detect and initialize UFS device */ 8821 ret = ufshcd_probe_hba(hba, true); 8822 up(&hba->host_sem); 8823 if (ret) 8824 goto out; 8825 8826 /* Probe and add UFS logical units */ 8827 ret = ufshcd_add_lus(hba); 8828 8829 out: 8830 pm_runtime_put_sync(hba->dev); 8831 8832 if (ret) 8833 dev_err(hba->dev, "%s failed: %d\n", __func__, ret); 8834 } 8835 8836 static enum scsi_timeout_action ufshcd_eh_timed_out(struct scsi_cmnd *scmd) 8837 { 8838 struct ufs_hba *hba = shost_priv(scmd->device->host); 8839 8840 if (!hba->system_suspending) { 8841 /* Activate the error handler in the SCSI core. */ 8842 return SCSI_EH_NOT_HANDLED; 8843 } 8844 8845 /* 8846 * If we get here we know that no TMFs are outstanding and also that 8847 * the only pending command is a START STOP UNIT command. Handle the 8848 * timeout of that command directly to prevent a deadlock between 8849 * ufshcd_set_dev_pwr_mode() and ufshcd_err_handler(). 8850 */ 8851 ufshcd_link_recovery(hba); 8852 dev_info(hba->dev, "%s() finished; outstanding_tasks = %#lx.\n", 8853 __func__, hba->outstanding_tasks); 8854 8855 return hba->outstanding_reqs ? SCSI_EH_RESET_TIMER : SCSI_EH_DONE; 8856 } 8857 8858 static const struct attribute_group *ufshcd_driver_groups[] = { 8859 &ufs_sysfs_unit_descriptor_group, 8860 &ufs_sysfs_lun_attributes_group, 8861 NULL, 8862 }; 8863 8864 static struct ufs_hba_variant_params ufs_hba_vps = { 8865 .hba_enable_delay_us = 1000, 8866 .wb_flush_threshold = UFS_WB_BUF_REMAIN_PERCENT(40), 8867 .devfreq_profile.polling_ms = 100, 8868 .devfreq_profile.target = ufshcd_devfreq_target, 8869 .devfreq_profile.get_dev_status = ufshcd_devfreq_get_dev_status, 8870 .ondemand_data.upthreshold = 70, 8871 .ondemand_data.downdifferential = 5, 8872 }; 8873 8874 static const struct scsi_host_template ufshcd_driver_template = { 8875 .module = THIS_MODULE, 8876 .name = UFSHCD, 8877 .proc_name = UFSHCD, 8878 .map_queues = ufshcd_map_queues, 8879 .queuecommand = ufshcd_queuecommand, 8880 .mq_poll = ufshcd_poll, 8881 .slave_alloc = ufshcd_slave_alloc, 8882 .slave_configure = ufshcd_slave_configure, 8883 .slave_destroy = ufshcd_slave_destroy, 8884 .change_queue_depth = ufshcd_change_queue_depth, 8885 .eh_abort_handler = ufshcd_abort, 8886 .eh_device_reset_handler = ufshcd_eh_device_reset_handler, 8887 .eh_host_reset_handler = ufshcd_eh_host_reset_handler, 8888 .eh_timed_out = ufshcd_eh_timed_out, 8889 .this_id = -1, 8890 .sg_tablesize = SG_ALL, 8891 .cmd_per_lun = UFSHCD_CMD_PER_LUN, 8892 .can_queue = UFSHCD_CAN_QUEUE, 8893 .max_segment_size = PRDT_DATA_BYTE_COUNT_MAX, 8894 .max_sectors = SZ_1M / SECTOR_SIZE, 8895 .max_host_blocked = 1, 8896 .track_queue_depth = 1, 8897 .skip_settle_delay = 1, 8898 .sdev_groups = ufshcd_driver_groups, 8899 .rpm_autosuspend_delay = RPM_AUTOSUSPEND_DELAY_MS, 8900 }; 8901 8902 static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg, 8903 int ua) 8904 { 8905 int ret; 8906 8907 if (!vreg) 8908 return 0; 8909 8910 /* 8911 * "set_load" operation shall be required on those regulators 8912 * which specifically configured current limitation. Otherwise 8913 * zero max_uA may cause unexpected behavior when regulator is 8914 * enabled or set as high power mode. 8915 */ 8916 if (!vreg->max_uA) 8917 return 0; 8918 8919 ret = regulator_set_load(vreg->reg, ua); 8920 if (ret < 0) { 8921 dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n", 8922 __func__, vreg->name, ua, ret); 8923 } 8924 8925 return ret; 8926 } 8927 8928 static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba, 8929 struct ufs_vreg *vreg) 8930 { 8931 return ufshcd_config_vreg_load(hba->dev, vreg, UFS_VREG_LPM_LOAD_UA); 8932 } 8933 8934 static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba, 8935 struct ufs_vreg *vreg) 8936 { 8937 if (!vreg) 8938 return 0; 8939 8940 return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA); 8941 } 8942 8943 static int ufshcd_config_vreg(struct device *dev, 8944 struct ufs_vreg *vreg, bool on) 8945 { 8946 if (regulator_count_voltages(vreg->reg) <= 0) 8947 return 0; 8948 8949 return ufshcd_config_vreg_load(dev, vreg, on ? vreg->max_uA : 0); 8950 } 8951 8952 static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg) 8953 { 8954 int ret = 0; 8955 8956 if (!vreg || vreg->enabled) 8957 goto out; 8958 8959 ret = ufshcd_config_vreg(dev, vreg, true); 8960 if (!ret) 8961 ret = regulator_enable(vreg->reg); 8962 8963 if (!ret) 8964 vreg->enabled = true; 8965 else 8966 dev_err(dev, "%s: %s enable failed, err=%d\n", 8967 __func__, vreg->name, ret); 8968 out: 8969 return ret; 8970 } 8971 8972 static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg) 8973 { 8974 int ret = 0; 8975 8976 if (!vreg || !vreg->enabled || vreg->always_on) 8977 goto out; 8978 8979 ret = regulator_disable(vreg->reg); 8980 8981 if (!ret) { 8982 /* ignore errors on applying disable config */ 8983 ufshcd_config_vreg(dev, vreg, false); 8984 vreg->enabled = false; 8985 } else { 8986 dev_err(dev, "%s: %s disable failed, err=%d\n", 8987 __func__, vreg->name, ret); 8988 } 8989 out: 8990 return ret; 8991 } 8992 8993 static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on) 8994 { 8995 int ret = 0; 8996 struct device *dev = hba->dev; 8997 struct ufs_vreg_info *info = &hba->vreg_info; 8998 8999 ret = ufshcd_toggle_vreg(dev, info->vcc, on); 9000 if (ret) 9001 goto out; 9002 9003 ret = ufshcd_toggle_vreg(dev, info->vccq, on); 9004 if (ret) 9005 goto out; 9006 9007 ret = ufshcd_toggle_vreg(dev, info->vccq2, on); 9008 9009 out: 9010 if (ret) { 9011 ufshcd_toggle_vreg(dev, info->vccq2, false); 9012 ufshcd_toggle_vreg(dev, info->vccq, false); 9013 ufshcd_toggle_vreg(dev, info->vcc, false); 9014 } 9015 return ret; 9016 } 9017 9018 static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on) 9019 { 9020 struct ufs_vreg_info *info = &hba->vreg_info; 9021 9022 return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on); 9023 } 9024 9025 int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg) 9026 { 9027 int ret = 0; 9028 9029 if (!vreg) 9030 goto out; 9031 9032 vreg->reg = devm_regulator_get(dev, vreg->name); 9033 if (IS_ERR(vreg->reg)) { 9034 ret = PTR_ERR(vreg->reg); 9035 dev_err(dev, "%s: %s get failed, err=%d\n", 9036 __func__, vreg->name, ret); 9037 } 9038 out: 9039 return ret; 9040 } 9041 EXPORT_SYMBOL_GPL(ufshcd_get_vreg); 9042 9043 static int ufshcd_init_vreg(struct ufs_hba *hba) 9044 { 9045 int ret = 0; 9046 struct device *dev = hba->dev; 9047 struct ufs_vreg_info *info = &hba->vreg_info; 9048 9049 ret = ufshcd_get_vreg(dev, info->vcc); 9050 if (ret) 9051 goto out; 9052 9053 ret = ufshcd_get_vreg(dev, info->vccq); 9054 if (!ret) 9055 ret = ufshcd_get_vreg(dev, info->vccq2); 9056 out: 9057 return ret; 9058 } 9059 9060 static int ufshcd_init_hba_vreg(struct ufs_hba *hba) 9061 { 9062 struct ufs_vreg_info *info = &hba->vreg_info; 9063 9064 return ufshcd_get_vreg(hba->dev, info->vdd_hba); 9065 } 9066 9067 static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on) 9068 { 9069 int ret = 0; 9070 struct ufs_clk_info *clki; 9071 struct list_head *head = &hba->clk_list_head; 9072 unsigned long flags; 9073 ktime_t start = ktime_get(); 9074 bool clk_state_changed = false; 9075 9076 if (list_empty(head)) 9077 goto out; 9078 9079 ret = ufshcd_vops_setup_clocks(hba, on, PRE_CHANGE); 9080 if (ret) 9081 return ret; 9082 9083 list_for_each_entry(clki, head, list) { 9084 if (!IS_ERR_OR_NULL(clki->clk)) { 9085 /* 9086 * Don't disable clocks which are needed 9087 * to keep the link active. 9088 */ 9089 if (ufshcd_is_link_active(hba) && 9090 clki->keep_link_active) 9091 continue; 9092 9093 clk_state_changed = on ^ clki->enabled; 9094 if (on && !clki->enabled) { 9095 ret = clk_prepare_enable(clki->clk); 9096 if (ret) { 9097 dev_err(hba->dev, "%s: %s prepare enable failed, %d\n", 9098 __func__, clki->name, ret); 9099 goto out; 9100 } 9101 } else if (!on && clki->enabled) { 9102 clk_disable_unprepare(clki->clk); 9103 } 9104 clki->enabled = on; 9105 dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__, 9106 clki->name, on ? "en" : "dis"); 9107 } 9108 } 9109 9110 ret = ufshcd_vops_setup_clocks(hba, on, POST_CHANGE); 9111 if (ret) 9112 return ret; 9113 9114 out: 9115 if (ret) { 9116 list_for_each_entry(clki, head, list) { 9117 if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled) 9118 clk_disable_unprepare(clki->clk); 9119 } 9120 } else if (!ret && on) { 9121 spin_lock_irqsave(hba->host->host_lock, flags); 9122 hba->clk_gating.state = CLKS_ON; 9123 trace_ufshcd_clk_gating(dev_name(hba->dev), 9124 hba->clk_gating.state); 9125 spin_unlock_irqrestore(hba->host->host_lock, flags); 9126 } 9127 9128 if (clk_state_changed) 9129 trace_ufshcd_profile_clk_gating(dev_name(hba->dev), 9130 (on ? "on" : "off"), 9131 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 9132 return ret; 9133 } 9134 9135 static enum ufs_ref_clk_freq ufshcd_parse_ref_clk_property(struct ufs_hba *hba) 9136 { 9137 u32 freq; 9138 int ret = device_property_read_u32(hba->dev, "ref-clk-freq", &freq); 9139 9140 if (ret) { 9141 dev_dbg(hba->dev, "Cannot query 'ref-clk-freq' property = %d", ret); 9142 return REF_CLK_FREQ_INVAL; 9143 } 9144 9145 return ufs_get_bref_clk_from_hz(freq); 9146 } 9147 9148 static int ufshcd_init_clocks(struct ufs_hba *hba) 9149 { 9150 int ret = 0; 9151 struct ufs_clk_info *clki; 9152 struct device *dev = hba->dev; 9153 struct list_head *head = &hba->clk_list_head; 9154 9155 if (list_empty(head)) 9156 goto out; 9157 9158 list_for_each_entry(clki, head, list) { 9159 if (!clki->name) 9160 continue; 9161 9162 clki->clk = devm_clk_get(dev, clki->name); 9163 if (IS_ERR(clki->clk)) { 9164 ret = PTR_ERR(clki->clk); 9165 dev_err(dev, "%s: %s clk get failed, %d\n", 9166 __func__, clki->name, ret); 9167 goto out; 9168 } 9169 9170 /* 9171 * Parse device ref clk freq as per device tree "ref_clk". 9172 * Default dev_ref_clk_freq is set to REF_CLK_FREQ_INVAL 9173 * in ufshcd_alloc_host(). 9174 */ 9175 if (!strcmp(clki->name, "ref_clk")) 9176 ufshcd_parse_dev_ref_clk_freq(hba, clki->clk); 9177 9178 if (clki->max_freq) { 9179 ret = clk_set_rate(clki->clk, clki->max_freq); 9180 if (ret) { 9181 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n", 9182 __func__, clki->name, 9183 clki->max_freq, ret); 9184 goto out; 9185 } 9186 clki->curr_freq = clki->max_freq; 9187 } 9188 dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__, 9189 clki->name, clk_get_rate(clki->clk)); 9190 } 9191 out: 9192 return ret; 9193 } 9194 9195 static int ufshcd_variant_hba_init(struct ufs_hba *hba) 9196 { 9197 int err = 0; 9198 9199 if (!hba->vops) 9200 goto out; 9201 9202 err = ufshcd_vops_init(hba); 9203 if (err) 9204 dev_err_probe(hba->dev, err, 9205 "%s: variant %s init failed with err %d\n", 9206 __func__, ufshcd_get_var_name(hba), err); 9207 out: 9208 return err; 9209 } 9210 9211 static void ufshcd_variant_hba_exit(struct ufs_hba *hba) 9212 { 9213 if (!hba->vops) 9214 return; 9215 9216 ufshcd_vops_exit(hba); 9217 } 9218 9219 static int ufshcd_hba_init(struct ufs_hba *hba) 9220 { 9221 int err; 9222 9223 /* 9224 * Handle host controller power separately from the UFS device power 9225 * rails as it will help controlling the UFS host controller power 9226 * collapse easily which is different than UFS device power collapse. 9227 * Also, enable the host controller power before we go ahead with rest 9228 * of the initialization here. 9229 */ 9230 err = ufshcd_init_hba_vreg(hba); 9231 if (err) 9232 goto out; 9233 9234 err = ufshcd_setup_hba_vreg(hba, true); 9235 if (err) 9236 goto out; 9237 9238 err = ufshcd_init_clocks(hba); 9239 if (err) 9240 goto out_disable_hba_vreg; 9241 9242 if (hba->dev_ref_clk_freq == REF_CLK_FREQ_INVAL) 9243 hba->dev_ref_clk_freq = ufshcd_parse_ref_clk_property(hba); 9244 9245 err = ufshcd_setup_clocks(hba, true); 9246 if (err) 9247 goto out_disable_hba_vreg; 9248 9249 err = ufshcd_init_vreg(hba); 9250 if (err) 9251 goto out_disable_clks; 9252 9253 err = ufshcd_setup_vreg(hba, true); 9254 if (err) 9255 goto out_disable_clks; 9256 9257 err = ufshcd_variant_hba_init(hba); 9258 if (err) 9259 goto out_disable_vreg; 9260 9261 ufs_debugfs_hba_init(hba); 9262 9263 hba->is_powered = true; 9264 goto out; 9265 9266 out_disable_vreg: 9267 ufshcd_setup_vreg(hba, false); 9268 out_disable_clks: 9269 ufshcd_setup_clocks(hba, false); 9270 out_disable_hba_vreg: 9271 ufshcd_setup_hba_vreg(hba, false); 9272 out: 9273 return err; 9274 } 9275 9276 static void ufshcd_hba_exit(struct ufs_hba *hba) 9277 { 9278 if (hba->is_powered) { 9279 ufshcd_exit_clk_scaling(hba); 9280 ufshcd_exit_clk_gating(hba); 9281 if (hba->eh_wq) 9282 destroy_workqueue(hba->eh_wq); 9283 ufs_debugfs_hba_exit(hba); 9284 ufshcd_variant_hba_exit(hba); 9285 ufshcd_setup_vreg(hba, false); 9286 ufshcd_setup_clocks(hba, false); 9287 ufshcd_setup_hba_vreg(hba, false); 9288 hba->is_powered = false; 9289 ufs_put_device_desc(hba); 9290 } 9291 } 9292 9293 static int ufshcd_execute_start_stop(struct scsi_device *sdev, 9294 enum ufs_dev_pwr_mode pwr_mode, 9295 struct scsi_sense_hdr *sshdr) 9296 { 9297 const unsigned char cdb[6] = { START_STOP, 0, 0, 0, pwr_mode << 4, 0 }; 9298 const struct scsi_exec_args args = { 9299 .sshdr = sshdr, 9300 .req_flags = BLK_MQ_REQ_PM, 9301 .scmd_flags = SCMD_FAIL_IF_RECOVERING, 9302 }; 9303 9304 return scsi_execute_cmd(sdev, cdb, REQ_OP_DRV_IN, /*buffer=*/NULL, 9305 /*bufflen=*/0, /*timeout=*/10 * HZ, /*retries=*/0, 9306 &args); 9307 } 9308 9309 /** 9310 * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device 9311 * power mode 9312 * @hba: per adapter instance 9313 * @pwr_mode: device power mode to set 9314 * 9315 * Return: 0 if requested power mode is set successfully; 9316 * < 0 if failed to set the requested power mode. 9317 */ 9318 static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba, 9319 enum ufs_dev_pwr_mode pwr_mode) 9320 { 9321 struct scsi_sense_hdr sshdr; 9322 struct scsi_device *sdp; 9323 unsigned long flags; 9324 int ret, retries; 9325 9326 spin_lock_irqsave(hba->host->host_lock, flags); 9327 sdp = hba->ufs_device_wlun; 9328 if (sdp && scsi_device_online(sdp)) 9329 ret = scsi_device_get(sdp); 9330 else 9331 ret = -ENODEV; 9332 spin_unlock_irqrestore(hba->host->host_lock, flags); 9333 9334 if (ret) 9335 return ret; 9336 9337 /* 9338 * If scsi commands fail, the scsi mid-layer schedules scsi error- 9339 * handling, which would wait for host to be resumed. Since we know 9340 * we are functional while we are here, skip host resume in error 9341 * handling context. 9342 */ 9343 hba->host->eh_noresume = 1; 9344 9345 /* 9346 * Current function would be generally called from the power management 9347 * callbacks hence set the RQF_PM flag so that it doesn't resume the 9348 * already suspended childs. 9349 */ 9350 for (retries = 3; retries > 0; --retries) { 9351 ret = ufshcd_execute_start_stop(sdp, pwr_mode, &sshdr); 9352 /* 9353 * scsi_execute() only returns a negative value if the request 9354 * queue is dying. 9355 */ 9356 if (ret <= 0) 9357 break; 9358 } 9359 if (ret) { 9360 sdev_printk(KERN_WARNING, sdp, 9361 "START_STOP failed for power mode: %d, result %x\n", 9362 pwr_mode, ret); 9363 if (ret > 0) { 9364 if (scsi_sense_valid(&sshdr)) 9365 scsi_print_sense_hdr(sdp, NULL, &sshdr); 9366 ret = -EIO; 9367 } 9368 } else { 9369 hba->curr_dev_pwr_mode = pwr_mode; 9370 } 9371 9372 scsi_device_put(sdp); 9373 hba->host->eh_noresume = 0; 9374 return ret; 9375 } 9376 9377 static int ufshcd_link_state_transition(struct ufs_hba *hba, 9378 enum uic_link_state req_link_state, 9379 bool check_for_bkops) 9380 { 9381 int ret = 0; 9382 9383 if (req_link_state == hba->uic_link_state) 9384 return 0; 9385 9386 if (req_link_state == UIC_LINK_HIBERN8_STATE) { 9387 ret = ufshcd_uic_hibern8_enter(hba); 9388 if (!ret) { 9389 ufshcd_set_link_hibern8(hba); 9390 } else { 9391 dev_err(hba->dev, "%s: hibern8 enter failed %d\n", 9392 __func__, ret); 9393 goto out; 9394 } 9395 } 9396 /* 9397 * If autobkops is enabled, link can't be turned off because 9398 * turning off the link would also turn off the device, except in the 9399 * case of DeepSleep where the device is expected to remain powered. 9400 */ 9401 else if ((req_link_state == UIC_LINK_OFF_STATE) && 9402 (!check_for_bkops || !hba->auto_bkops_enabled)) { 9403 /* 9404 * Let's make sure that link is in low power mode, we are doing 9405 * this currently by putting the link in Hibern8. Otherway to 9406 * put the link in low power mode is to send the DME end point 9407 * to device and then send the DME reset command to local 9408 * unipro. But putting the link in hibern8 is much faster. 9409 * 9410 * Note also that putting the link in Hibern8 is a requirement 9411 * for entering DeepSleep. 9412 */ 9413 ret = ufshcd_uic_hibern8_enter(hba); 9414 if (ret) { 9415 dev_err(hba->dev, "%s: hibern8 enter failed %d\n", 9416 __func__, ret); 9417 goto out; 9418 } 9419 /* 9420 * Change controller state to "reset state" which 9421 * should also put the link in off/reset state 9422 */ 9423 ufshcd_hba_stop(hba); 9424 /* 9425 * TODO: Check if we need any delay to make sure that 9426 * controller is reset 9427 */ 9428 ufshcd_set_link_off(hba); 9429 } 9430 9431 out: 9432 return ret; 9433 } 9434 9435 static void ufshcd_vreg_set_lpm(struct ufs_hba *hba) 9436 { 9437 bool vcc_off = false; 9438 9439 /* 9440 * It seems some UFS devices may keep drawing more than sleep current 9441 * (atleast for 500us) from UFS rails (especially from VCCQ rail). 9442 * To avoid this situation, add 2ms delay before putting these UFS 9443 * rails in LPM mode. 9444 */ 9445 if (!ufshcd_is_link_active(hba) && 9446 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM) 9447 usleep_range(2000, 2100); 9448 9449 /* 9450 * If UFS device is either in UFS_Sleep turn off VCC rail to save some 9451 * power. 9452 * 9453 * If UFS device and link is in OFF state, all power supplies (VCC, 9454 * VCCQ, VCCQ2) can be turned off if power on write protect is not 9455 * required. If UFS link is inactive (Hibern8 or OFF state) and device 9456 * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode. 9457 * 9458 * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway 9459 * in low power state which would save some power. 9460 * 9461 * If Write Booster is enabled and the device needs to flush the WB 9462 * buffer OR if bkops status is urgent for WB, keep Vcc on. 9463 */ 9464 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) && 9465 !hba->dev_info.is_lu_power_on_wp) { 9466 ufshcd_setup_vreg(hba, false); 9467 vcc_off = true; 9468 } else if (!ufshcd_is_ufs_dev_active(hba)) { 9469 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false); 9470 vcc_off = true; 9471 if (ufshcd_is_link_hibern8(hba) || ufshcd_is_link_off(hba)) { 9472 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq); 9473 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2); 9474 } 9475 } 9476 9477 /* 9478 * Some UFS devices require delay after VCC power rail is turned-off. 9479 */ 9480 if (vcc_off && hba->vreg_info.vcc && 9481 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_AFTER_LPM) 9482 usleep_range(5000, 5100); 9483 } 9484 9485 #ifdef CONFIG_PM 9486 static int ufshcd_vreg_set_hpm(struct ufs_hba *hba) 9487 { 9488 int ret = 0; 9489 9490 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) && 9491 !hba->dev_info.is_lu_power_on_wp) { 9492 ret = ufshcd_setup_vreg(hba, true); 9493 } else if (!ufshcd_is_ufs_dev_active(hba)) { 9494 if (!ufshcd_is_link_active(hba)) { 9495 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq); 9496 if (ret) 9497 goto vcc_disable; 9498 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2); 9499 if (ret) 9500 goto vccq_lpm; 9501 } 9502 ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true); 9503 } 9504 goto out; 9505 9506 vccq_lpm: 9507 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq); 9508 vcc_disable: 9509 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false); 9510 out: 9511 return ret; 9512 } 9513 #endif /* CONFIG_PM */ 9514 9515 static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba) 9516 { 9517 if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba)) 9518 ufshcd_setup_hba_vreg(hba, false); 9519 } 9520 9521 static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba) 9522 { 9523 if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba)) 9524 ufshcd_setup_hba_vreg(hba, true); 9525 } 9526 9527 static int __ufshcd_wl_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op) 9528 { 9529 int ret = 0; 9530 bool check_for_bkops; 9531 enum ufs_pm_level pm_lvl; 9532 enum ufs_dev_pwr_mode req_dev_pwr_mode; 9533 enum uic_link_state req_link_state; 9534 9535 hba->pm_op_in_progress = true; 9536 if (pm_op != UFS_SHUTDOWN_PM) { 9537 pm_lvl = pm_op == UFS_RUNTIME_PM ? 9538 hba->rpm_lvl : hba->spm_lvl; 9539 req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl); 9540 req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl); 9541 } else { 9542 req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE; 9543 req_link_state = UIC_LINK_OFF_STATE; 9544 } 9545 9546 /* 9547 * If we can't transition into any of the low power modes 9548 * just gate the clocks. 9549 */ 9550 ufshcd_hold(hba); 9551 hba->clk_gating.is_suspended = true; 9552 9553 if (ufshcd_is_clkscaling_supported(hba)) 9554 ufshcd_clk_scaling_suspend(hba, true); 9555 9556 if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE && 9557 req_link_state == UIC_LINK_ACTIVE_STATE) { 9558 goto vops_suspend; 9559 } 9560 9561 if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) && 9562 (req_link_state == hba->uic_link_state)) 9563 goto enable_scaling; 9564 9565 /* UFS device & link must be active before we enter in this function */ 9566 if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) { 9567 /* Wait err handler finish or trigger err recovery */ 9568 if (!ufshcd_eh_in_progress(hba)) 9569 ufshcd_force_error_recovery(hba); 9570 ret = -EBUSY; 9571 goto enable_scaling; 9572 } 9573 9574 if (pm_op == UFS_RUNTIME_PM) { 9575 if (ufshcd_can_autobkops_during_suspend(hba)) { 9576 /* 9577 * The device is idle with no requests in the queue, 9578 * allow background operations if bkops status shows 9579 * that performance might be impacted. 9580 */ 9581 ret = ufshcd_urgent_bkops(hba); 9582 if (ret) { 9583 /* 9584 * If return err in suspend flow, IO will hang. 9585 * Trigger error handler and break suspend for 9586 * error recovery. 9587 */ 9588 ufshcd_force_error_recovery(hba); 9589 ret = -EBUSY; 9590 goto enable_scaling; 9591 } 9592 } else { 9593 /* make sure that auto bkops is disabled */ 9594 ufshcd_disable_auto_bkops(hba); 9595 } 9596 /* 9597 * If device needs to do BKOP or WB buffer flush during 9598 * Hibern8, keep device power mode as "active power mode" 9599 * and VCC supply. 9600 */ 9601 hba->dev_info.b_rpm_dev_flush_capable = 9602 hba->auto_bkops_enabled || 9603 (((req_link_state == UIC_LINK_HIBERN8_STATE) || 9604 ((req_link_state == UIC_LINK_ACTIVE_STATE) && 9605 ufshcd_is_auto_hibern8_enabled(hba))) && 9606 ufshcd_wb_need_flush(hba)); 9607 } 9608 9609 flush_work(&hba->eeh_work); 9610 9611 ret = ufshcd_vops_suspend(hba, pm_op, PRE_CHANGE); 9612 if (ret) 9613 goto enable_scaling; 9614 9615 if (req_dev_pwr_mode != hba->curr_dev_pwr_mode) { 9616 if (pm_op != UFS_RUNTIME_PM) 9617 /* ensure that bkops is disabled */ 9618 ufshcd_disable_auto_bkops(hba); 9619 9620 if (!hba->dev_info.b_rpm_dev_flush_capable) { 9621 ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode); 9622 if (ret && pm_op != UFS_SHUTDOWN_PM) { 9623 /* 9624 * If return err in suspend flow, IO will hang. 9625 * Trigger error handler and break suspend for 9626 * error recovery. 9627 */ 9628 ufshcd_force_error_recovery(hba); 9629 ret = -EBUSY; 9630 } 9631 if (ret) 9632 goto enable_scaling; 9633 } 9634 } 9635 9636 /* 9637 * In the case of DeepSleep, the device is expected to remain powered 9638 * with the link off, so do not check for bkops. 9639 */ 9640 check_for_bkops = !ufshcd_is_ufs_dev_deepsleep(hba); 9641 ret = ufshcd_link_state_transition(hba, req_link_state, check_for_bkops); 9642 if (ret && pm_op != UFS_SHUTDOWN_PM) { 9643 /* 9644 * If return err in suspend flow, IO will hang. 9645 * Trigger error handler and break suspend for 9646 * error recovery. 9647 */ 9648 ufshcd_force_error_recovery(hba); 9649 ret = -EBUSY; 9650 } 9651 if (ret) 9652 goto set_dev_active; 9653 9654 vops_suspend: 9655 /* 9656 * Call vendor specific suspend callback. As these callbacks may access 9657 * vendor specific host controller register space call them before the 9658 * host clocks are ON. 9659 */ 9660 ret = ufshcd_vops_suspend(hba, pm_op, POST_CHANGE); 9661 if (ret) 9662 goto set_link_active; 9663 goto out; 9664 9665 set_link_active: 9666 /* 9667 * Device hardware reset is required to exit DeepSleep. Also, for 9668 * DeepSleep, the link is off so host reset and restore will be done 9669 * further below. 9670 */ 9671 if (ufshcd_is_ufs_dev_deepsleep(hba)) { 9672 ufshcd_device_reset(hba); 9673 WARN_ON(!ufshcd_is_link_off(hba)); 9674 } 9675 if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba)) 9676 ufshcd_set_link_active(hba); 9677 else if (ufshcd_is_link_off(hba)) 9678 ufshcd_host_reset_and_restore(hba); 9679 set_dev_active: 9680 /* Can also get here needing to exit DeepSleep */ 9681 if (ufshcd_is_ufs_dev_deepsleep(hba)) { 9682 ufshcd_device_reset(hba); 9683 ufshcd_host_reset_and_restore(hba); 9684 } 9685 if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE)) 9686 ufshcd_disable_auto_bkops(hba); 9687 enable_scaling: 9688 if (ufshcd_is_clkscaling_supported(hba)) 9689 ufshcd_clk_scaling_suspend(hba, false); 9690 9691 hba->dev_info.b_rpm_dev_flush_capable = false; 9692 out: 9693 if (hba->dev_info.b_rpm_dev_flush_capable) { 9694 schedule_delayed_work(&hba->rpm_dev_flush_recheck_work, 9695 msecs_to_jiffies(RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS)); 9696 } 9697 9698 if (ret) { 9699 ufshcd_update_evt_hist(hba, UFS_EVT_WL_SUSP_ERR, (u32)ret); 9700 hba->clk_gating.is_suspended = false; 9701 ufshcd_release(hba); 9702 } 9703 hba->pm_op_in_progress = false; 9704 return ret; 9705 } 9706 9707 #ifdef CONFIG_PM 9708 static int __ufshcd_wl_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) 9709 { 9710 int ret; 9711 enum uic_link_state old_link_state = hba->uic_link_state; 9712 9713 hba->pm_op_in_progress = true; 9714 9715 /* 9716 * Call vendor specific resume callback. As these callbacks may access 9717 * vendor specific host controller register space call them when the 9718 * host clocks are ON. 9719 */ 9720 ret = ufshcd_vops_resume(hba, pm_op); 9721 if (ret) 9722 goto out; 9723 9724 /* For DeepSleep, the only supported option is to have the link off */ 9725 WARN_ON(ufshcd_is_ufs_dev_deepsleep(hba) && !ufshcd_is_link_off(hba)); 9726 9727 if (ufshcd_is_link_hibern8(hba)) { 9728 ret = ufshcd_uic_hibern8_exit(hba); 9729 if (!ret) { 9730 ufshcd_set_link_active(hba); 9731 } else { 9732 dev_err(hba->dev, "%s: hibern8 exit failed %d\n", 9733 __func__, ret); 9734 goto vendor_suspend; 9735 } 9736 } else if (ufshcd_is_link_off(hba)) { 9737 /* 9738 * A full initialization of the host and the device is 9739 * required since the link was put to off during suspend. 9740 * Note, in the case of DeepSleep, the device will exit 9741 * DeepSleep due to device reset. 9742 */ 9743 ret = ufshcd_reset_and_restore(hba); 9744 /* 9745 * ufshcd_reset_and_restore() should have already 9746 * set the link state as active 9747 */ 9748 if (ret || !ufshcd_is_link_active(hba)) 9749 goto vendor_suspend; 9750 } 9751 9752 if (!ufshcd_is_ufs_dev_active(hba)) { 9753 ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE); 9754 if (ret) 9755 goto set_old_link_state; 9756 ufshcd_set_timestamp_attr(hba); 9757 } 9758 9759 if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) 9760 ufshcd_enable_auto_bkops(hba); 9761 else 9762 /* 9763 * If BKOPs operations are urgently needed at this moment then 9764 * keep auto-bkops enabled or else disable it. 9765 */ 9766 ufshcd_urgent_bkops(hba); 9767 9768 if (hba->ee_usr_mask) 9769 ufshcd_write_ee_control(hba); 9770 9771 if (ufshcd_is_clkscaling_supported(hba)) 9772 ufshcd_clk_scaling_suspend(hba, false); 9773 9774 if (hba->dev_info.b_rpm_dev_flush_capable) { 9775 hba->dev_info.b_rpm_dev_flush_capable = false; 9776 cancel_delayed_work(&hba->rpm_dev_flush_recheck_work); 9777 } 9778 9779 /* Enable Auto-Hibernate if configured */ 9780 ufshcd_auto_hibern8_enable(hba); 9781 9782 goto out; 9783 9784 set_old_link_state: 9785 ufshcd_link_state_transition(hba, old_link_state, 0); 9786 vendor_suspend: 9787 ufshcd_vops_suspend(hba, pm_op, PRE_CHANGE); 9788 ufshcd_vops_suspend(hba, pm_op, POST_CHANGE); 9789 out: 9790 if (ret) 9791 ufshcd_update_evt_hist(hba, UFS_EVT_WL_RES_ERR, (u32)ret); 9792 hba->clk_gating.is_suspended = false; 9793 ufshcd_release(hba); 9794 hba->pm_op_in_progress = false; 9795 return ret; 9796 } 9797 9798 static int ufshcd_wl_runtime_suspend(struct device *dev) 9799 { 9800 struct scsi_device *sdev = to_scsi_device(dev); 9801 struct ufs_hba *hba; 9802 int ret; 9803 ktime_t start = ktime_get(); 9804 9805 hba = shost_priv(sdev->host); 9806 9807 ret = __ufshcd_wl_suspend(hba, UFS_RUNTIME_PM); 9808 if (ret) 9809 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret); 9810 9811 trace_ufshcd_wl_runtime_suspend(dev_name(dev), ret, 9812 ktime_to_us(ktime_sub(ktime_get(), start)), 9813 hba->curr_dev_pwr_mode, hba->uic_link_state); 9814 9815 return ret; 9816 } 9817 9818 static int ufshcd_wl_runtime_resume(struct device *dev) 9819 { 9820 struct scsi_device *sdev = to_scsi_device(dev); 9821 struct ufs_hba *hba; 9822 int ret = 0; 9823 ktime_t start = ktime_get(); 9824 9825 hba = shost_priv(sdev->host); 9826 9827 ret = __ufshcd_wl_resume(hba, UFS_RUNTIME_PM); 9828 if (ret) 9829 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret); 9830 9831 trace_ufshcd_wl_runtime_resume(dev_name(dev), ret, 9832 ktime_to_us(ktime_sub(ktime_get(), start)), 9833 hba->curr_dev_pwr_mode, hba->uic_link_state); 9834 9835 return ret; 9836 } 9837 #endif 9838 9839 #ifdef CONFIG_PM_SLEEP 9840 static int ufshcd_wl_suspend(struct device *dev) 9841 { 9842 struct scsi_device *sdev = to_scsi_device(dev); 9843 struct ufs_hba *hba; 9844 int ret = 0; 9845 ktime_t start = ktime_get(); 9846 9847 hba = shost_priv(sdev->host); 9848 down(&hba->host_sem); 9849 hba->system_suspending = true; 9850 9851 if (pm_runtime_suspended(dev)) 9852 goto out; 9853 9854 ret = __ufshcd_wl_suspend(hba, UFS_SYSTEM_PM); 9855 if (ret) { 9856 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret); 9857 up(&hba->host_sem); 9858 } 9859 9860 out: 9861 if (!ret) 9862 hba->is_sys_suspended = true; 9863 trace_ufshcd_wl_suspend(dev_name(dev), ret, 9864 ktime_to_us(ktime_sub(ktime_get(), start)), 9865 hba->curr_dev_pwr_mode, hba->uic_link_state); 9866 9867 return ret; 9868 } 9869 9870 static int ufshcd_wl_resume(struct device *dev) 9871 { 9872 struct scsi_device *sdev = to_scsi_device(dev); 9873 struct ufs_hba *hba; 9874 int ret = 0; 9875 ktime_t start = ktime_get(); 9876 9877 hba = shost_priv(sdev->host); 9878 9879 if (pm_runtime_suspended(dev)) 9880 goto out; 9881 9882 ret = __ufshcd_wl_resume(hba, UFS_SYSTEM_PM); 9883 if (ret) 9884 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret); 9885 out: 9886 trace_ufshcd_wl_resume(dev_name(dev), ret, 9887 ktime_to_us(ktime_sub(ktime_get(), start)), 9888 hba->curr_dev_pwr_mode, hba->uic_link_state); 9889 if (!ret) 9890 hba->is_sys_suspended = false; 9891 hba->system_suspending = false; 9892 up(&hba->host_sem); 9893 return ret; 9894 } 9895 #endif 9896 9897 /** 9898 * ufshcd_suspend - helper function for suspend operations 9899 * @hba: per adapter instance 9900 * 9901 * This function will put disable irqs, turn off clocks 9902 * and set vreg and hba-vreg in lpm mode. 9903 * 9904 * Return: 0 upon success; < 0 upon failure. 9905 */ 9906 static int ufshcd_suspend(struct ufs_hba *hba) 9907 { 9908 int ret; 9909 9910 if (!hba->is_powered) 9911 return 0; 9912 /* 9913 * Disable the host irq as host controller as there won't be any 9914 * host controller transaction expected till resume. 9915 */ 9916 ufshcd_disable_irq(hba); 9917 ret = ufshcd_setup_clocks(hba, false); 9918 if (ret) { 9919 ufshcd_enable_irq(hba); 9920 return ret; 9921 } 9922 if (ufshcd_is_clkgating_allowed(hba)) { 9923 hba->clk_gating.state = CLKS_OFF; 9924 trace_ufshcd_clk_gating(dev_name(hba->dev), 9925 hba->clk_gating.state); 9926 } 9927 9928 ufshcd_vreg_set_lpm(hba); 9929 /* Put the host controller in low power mode if possible */ 9930 ufshcd_hba_vreg_set_lpm(hba); 9931 return ret; 9932 } 9933 9934 #ifdef CONFIG_PM 9935 /** 9936 * ufshcd_resume - helper function for resume operations 9937 * @hba: per adapter instance 9938 * 9939 * This function basically turns on the regulators, clocks and 9940 * irqs of the hba. 9941 * 9942 * Return: 0 for success and non-zero for failure. 9943 */ 9944 static int ufshcd_resume(struct ufs_hba *hba) 9945 { 9946 int ret; 9947 9948 if (!hba->is_powered) 9949 return 0; 9950 9951 ufshcd_hba_vreg_set_hpm(hba); 9952 ret = ufshcd_vreg_set_hpm(hba); 9953 if (ret) 9954 goto out; 9955 9956 /* Make sure clocks are enabled before accessing controller */ 9957 ret = ufshcd_setup_clocks(hba, true); 9958 if (ret) 9959 goto disable_vreg; 9960 9961 /* enable the host irq as host controller would be active soon */ 9962 ufshcd_enable_irq(hba); 9963 9964 goto out; 9965 9966 disable_vreg: 9967 ufshcd_vreg_set_lpm(hba); 9968 out: 9969 if (ret) 9970 ufshcd_update_evt_hist(hba, UFS_EVT_RESUME_ERR, (u32)ret); 9971 return ret; 9972 } 9973 #endif /* CONFIG_PM */ 9974 9975 #ifdef CONFIG_PM_SLEEP 9976 /** 9977 * ufshcd_system_suspend - system suspend callback 9978 * @dev: Device associated with the UFS controller. 9979 * 9980 * Executed before putting the system into a sleep state in which the contents 9981 * of main memory are preserved. 9982 * 9983 * Return: 0 for success and non-zero for failure. 9984 */ 9985 int ufshcd_system_suspend(struct device *dev) 9986 { 9987 struct ufs_hba *hba = dev_get_drvdata(dev); 9988 int ret = 0; 9989 ktime_t start = ktime_get(); 9990 9991 if (pm_runtime_suspended(hba->dev)) 9992 goto out; 9993 9994 ret = ufshcd_suspend(hba); 9995 out: 9996 trace_ufshcd_system_suspend(dev_name(hba->dev), ret, 9997 ktime_to_us(ktime_sub(ktime_get(), start)), 9998 hba->curr_dev_pwr_mode, hba->uic_link_state); 9999 return ret; 10000 } 10001 EXPORT_SYMBOL(ufshcd_system_suspend); 10002 10003 /** 10004 * ufshcd_system_resume - system resume callback 10005 * @dev: Device associated with the UFS controller. 10006 * 10007 * Executed after waking the system up from a sleep state in which the contents 10008 * of main memory were preserved. 10009 * 10010 * Return: 0 for success and non-zero for failure. 10011 */ 10012 int ufshcd_system_resume(struct device *dev) 10013 { 10014 struct ufs_hba *hba = dev_get_drvdata(dev); 10015 ktime_t start = ktime_get(); 10016 int ret = 0; 10017 10018 if (pm_runtime_suspended(hba->dev)) 10019 goto out; 10020 10021 ret = ufshcd_resume(hba); 10022 10023 out: 10024 trace_ufshcd_system_resume(dev_name(hba->dev), ret, 10025 ktime_to_us(ktime_sub(ktime_get(), start)), 10026 hba->curr_dev_pwr_mode, hba->uic_link_state); 10027 10028 return ret; 10029 } 10030 EXPORT_SYMBOL(ufshcd_system_resume); 10031 #endif /* CONFIG_PM_SLEEP */ 10032 10033 #ifdef CONFIG_PM 10034 /** 10035 * ufshcd_runtime_suspend - runtime suspend callback 10036 * @dev: Device associated with the UFS controller. 10037 * 10038 * Check the description of ufshcd_suspend() function for more details. 10039 * 10040 * Return: 0 for success and non-zero for failure. 10041 */ 10042 int ufshcd_runtime_suspend(struct device *dev) 10043 { 10044 struct ufs_hba *hba = dev_get_drvdata(dev); 10045 int ret; 10046 ktime_t start = ktime_get(); 10047 10048 ret = ufshcd_suspend(hba); 10049 10050 trace_ufshcd_runtime_suspend(dev_name(hba->dev), ret, 10051 ktime_to_us(ktime_sub(ktime_get(), start)), 10052 hba->curr_dev_pwr_mode, hba->uic_link_state); 10053 return ret; 10054 } 10055 EXPORT_SYMBOL(ufshcd_runtime_suspend); 10056 10057 /** 10058 * ufshcd_runtime_resume - runtime resume routine 10059 * @dev: Device associated with the UFS controller. 10060 * 10061 * This function basically brings controller 10062 * to active state. Following operations are done in this function: 10063 * 10064 * 1. Turn on all the controller related clocks 10065 * 2. Turn ON VCC rail 10066 * 10067 * Return: 0 upon success; < 0 upon failure. 10068 */ 10069 int ufshcd_runtime_resume(struct device *dev) 10070 { 10071 struct ufs_hba *hba = dev_get_drvdata(dev); 10072 int ret; 10073 ktime_t start = ktime_get(); 10074 10075 ret = ufshcd_resume(hba); 10076 10077 trace_ufshcd_runtime_resume(dev_name(hba->dev), ret, 10078 ktime_to_us(ktime_sub(ktime_get(), start)), 10079 hba->curr_dev_pwr_mode, hba->uic_link_state); 10080 return ret; 10081 } 10082 EXPORT_SYMBOL(ufshcd_runtime_resume); 10083 #endif /* CONFIG_PM */ 10084 10085 static void ufshcd_wl_shutdown(struct device *dev) 10086 { 10087 struct scsi_device *sdev = to_scsi_device(dev); 10088 struct ufs_hba *hba = shost_priv(sdev->host); 10089 10090 down(&hba->host_sem); 10091 hba->shutting_down = true; 10092 up(&hba->host_sem); 10093 10094 /* Turn on everything while shutting down */ 10095 ufshcd_rpm_get_sync(hba); 10096 scsi_device_quiesce(sdev); 10097 shost_for_each_device(sdev, hba->host) { 10098 if (sdev == hba->ufs_device_wlun) 10099 continue; 10100 mutex_lock(&sdev->state_mutex); 10101 scsi_device_set_state(sdev, SDEV_OFFLINE); 10102 mutex_unlock(&sdev->state_mutex); 10103 } 10104 __ufshcd_wl_suspend(hba, UFS_SHUTDOWN_PM); 10105 10106 /* 10107 * Next, turn off the UFS controller and the UFS regulators. Disable 10108 * clocks. 10109 */ 10110 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba)) 10111 ufshcd_suspend(hba); 10112 10113 hba->is_powered = false; 10114 } 10115 10116 /** 10117 * ufshcd_remove - de-allocate SCSI host and host memory space 10118 * data structure memory 10119 * @hba: per adapter instance 10120 */ 10121 void ufshcd_remove(struct ufs_hba *hba) 10122 { 10123 if (hba->ufs_device_wlun) 10124 ufshcd_rpm_get_sync(hba); 10125 ufs_hwmon_remove(hba); 10126 ufs_bsg_remove(hba); 10127 ufs_sysfs_remove_nodes(hba->dev); 10128 blk_mq_destroy_queue(hba->tmf_queue); 10129 blk_put_queue(hba->tmf_queue); 10130 blk_mq_free_tag_set(&hba->tmf_tag_set); 10131 if (hba->scsi_host_added) 10132 scsi_remove_host(hba->host); 10133 /* disable interrupts */ 10134 ufshcd_disable_intr(hba, hba->intr_mask); 10135 ufshcd_hba_stop(hba); 10136 ufshcd_hba_exit(hba); 10137 } 10138 EXPORT_SYMBOL_GPL(ufshcd_remove); 10139 10140 #ifdef CONFIG_PM_SLEEP 10141 int ufshcd_system_freeze(struct device *dev) 10142 { 10143 10144 return ufshcd_system_suspend(dev); 10145 10146 } 10147 EXPORT_SYMBOL_GPL(ufshcd_system_freeze); 10148 10149 int ufshcd_system_restore(struct device *dev) 10150 { 10151 10152 struct ufs_hba *hba = dev_get_drvdata(dev); 10153 int ret; 10154 10155 ret = ufshcd_system_resume(dev); 10156 if (ret) 10157 return ret; 10158 10159 /* Configure UTRL and UTMRL base address registers */ 10160 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr), 10161 REG_UTP_TRANSFER_REQ_LIST_BASE_L); 10162 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr), 10163 REG_UTP_TRANSFER_REQ_LIST_BASE_H); 10164 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr), 10165 REG_UTP_TASK_REQ_LIST_BASE_L); 10166 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr), 10167 REG_UTP_TASK_REQ_LIST_BASE_H); 10168 /* 10169 * Make sure that UTRL and UTMRL base address registers 10170 * are updated with the latest queue addresses. Only after 10171 * updating these addresses, we can queue the new commands. 10172 */ 10173 ufshcd_readl(hba, REG_UTP_TASK_REQ_LIST_BASE_H); 10174 10175 return 0; 10176 10177 } 10178 EXPORT_SYMBOL_GPL(ufshcd_system_restore); 10179 10180 int ufshcd_system_thaw(struct device *dev) 10181 { 10182 return ufshcd_system_resume(dev); 10183 } 10184 EXPORT_SYMBOL_GPL(ufshcd_system_thaw); 10185 #endif /* CONFIG_PM_SLEEP */ 10186 10187 /** 10188 * ufshcd_dealloc_host - deallocate Host Bus Adapter (HBA) 10189 * @hba: pointer to Host Bus Adapter (HBA) 10190 */ 10191 void ufshcd_dealloc_host(struct ufs_hba *hba) 10192 { 10193 scsi_host_put(hba->host); 10194 } 10195 EXPORT_SYMBOL_GPL(ufshcd_dealloc_host); 10196 10197 /** 10198 * ufshcd_set_dma_mask - Set dma mask based on the controller 10199 * addressing capability 10200 * @hba: per adapter instance 10201 * 10202 * Return: 0 for success, non-zero for failure. 10203 */ 10204 static int ufshcd_set_dma_mask(struct ufs_hba *hba) 10205 { 10206 if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) { 10207 if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64))) 10208 return 0; 10209 } 10210 return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32)); 10211 } 10212 10213 /** 10214 * ufshcd_alloc_host - allocate Host Bus Adapter (HBA) 10215 * @dev: pointer to device handle 10216 * @hba_handle: driver private handle 10217 * 10218 * Return: 0 on success, non-zero value on failure. 10219 */ 10220 int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle) 10221 { 10222 struct Scsi_Host *host; 10223 struct ufs_hba *hba; 10224 int err = 0; 10225 10226 if (!dev) { 10227 dev_err(dev, 10228 "Invalid memory reference for dev is NULL\n"); 10229 err = -ENODEV; 10230 goto out_error; 10231 } 10232 10233 host = scsi_host_alloc(&ufshcd_driver_template, 10234 sizeof(struct ufs_hba)); 10235 if (!host) { 10236 dev_err(dev, "scsi_host_alloc failed\n"); 10237 err = -ENOMEM; 10238 goto out_error; 10239 } 10240 host->nr_maps = HCTX_TYPE_POLL + 1; 10241 hba = shost_priv(host); 10242 hba->host = host; 10243 hba->dev = dev; 10244 hba->dev_ref_clk_freq = REF_CLK_FREQ_INVAL; 10245 hba->nop_out_timeout = NOP_OUT_TIMEOUT; 10246 ufshcd_set_sg_entry_size(hba, sizeof(struct ufshcd_sg_entry)); 10247 INIT_LIST_HEAD(&hba->clk_list_head); 10248 spin_lock_init(&hba->outstanding_lock); 10249 10250 *hba_handle = hba; 10251 10252 out_error: 10253 return err; 10254 } 10255 EXPORT_SYMBOL(ufshcd_alloc_host); 10256 10257 /* This function exists because blk_mq_alloc_tag_set() requires this. */ 10258 static blk_status_t ufshcd_queue_tmf(struct blk_mq_hw_ctx *hctx, 10259 const struct blk_mq_queue_data *qd) 10260 { 10261 WARN_ON_ONCE(true); 10262 return BLK_STS_NOTSUPP; 10263 } 10264 10265 static const struct blk_mq_ops ufshcd_tmf_ops = { 10266 .queue_rq = ufshcd_queue_tmf, 10267 }; 10268 10269 /** 10270 * ufshcd_init - Driver initialization routine 10271 * @hba: per-adapter instance 10272 * @mmio_base: base register address 10273 * @irq: Interrupt line of device 10274 * 10275 * Return: 0 on success, non-zero value on failure. 10276 */ 10277 int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq) 10278 { 10279 int err; 10280 struct Scsi_Host *host = hba->host; 10281 struct device *dev = hba->dev; 10282 char eh_wq_name[sizeof("ufs_eh_wq_00")]; 10283 10284 /* 10285 * dev_set_drvdata() must be called before any callbacks are registered 10286 * that use dev_get_drvdata() (frequency scaling, clock scaling, hwmon, 10287 * sysfs). 10288 */ 10289 dev_set_drvdata(dev, hba); 10290 10291 if (!mmio_base) { 10292 dev_err(hba->dev, 10293 "Invalid memory reference for mmio_base is NULL\n"); 10294 err = -ENODEV; 10295 goto out_error; 10296 } 10297 10298 hba->mmio_base = mmio_base; 10299 hba->irq = irq; 10300 hba->vps = &ufs_hba_vps; 10301 10302 err = ufshcd_hba_init(hba); 10303 if (err) 10304 goto out_error; 10305 10306 /* Read capabilities registers */ 10307 err = ufshcd_hba_capabilities(hba); 10308 if (err) 10309 goto out_disable; 10310 10311 /* Get UFS version supported by the controller */ 10312 hba->ufs_version = ufshcd_get_ufs_version(hba); 10313 10314 /* Get Interrupt bit mask per version */ 10315 hba->intr_mask = ufshcd_get_intr_mask(hba); 10316 10317 err = ufshcd_set_dma_mask(hba); 10318 if (err) { 10319 dev_err(hba->dev, "set dma mask failed\n"); 10320 goto out_disable; 10321 } 10322 10323 /* Allocate memory for host memory space */ 10324 err = ufshcd_memory_alloc(hba); 10325 if (err) { 10326 dev_err(hba->dev, "Memory allocation failed\n"); 10327 goto out_disable; 10328 } 10329 10330 /* Configure LRB */ 10331 ufshcd_host_memory_configure(hba); 10332 10333 host->can_queue = hba->nutrs - UFSHCD_NUM_RESERVED; 10334 host->cmd_per_lun = hba->nutrs - UFSHCD_NUM_RESERVED; 10335 host->max_id = UFSHCD_MAX_ID; 10336 host->max_lun = UFS_MAX_LUNS; 10337 host->max_channel = UFSHCD_MAX_CHANNEL; 10338 host->unique_id = host->host_no; 10339 host->max_cmd_len = UFS_CDB_SIZE; 10340 host->queuecommand_may_block = !!(hba->caps & UFSHCD_CAP_CLK_GATING); 10341 10342 hba->max_pwr_info.is_valid = false; 10343 10344 /* Initialize work queues */ 10345 snprintf(eh_wq_name, sizeof(eh_wq_name), "ufs_eh_wq_%d", 10346 hba->host->host_no); 10347 hba->eh_wq = create_singlethread_workqueue(eh_wq_name); 10348 if (!hba->eh_wq) { 10349 dev_err(hba->dev, "%s: failed to create eh workqueue\n", 10350 __func__); 10351 err = -ENOMEM; 10352 goto out_disable; 10353 } 10354 INIT_WORK(&hba->eh_work, ufshcd_err_handler); 10355 INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler); 10356 10357 sema_init(&hba->host_sem, 1); 10358 10359 /* Initialize UIC command mutex */ 10360 mutex_init(&hba->uic_cmd_mutex); 10361 10362 /* Initialize mutex for device management commands */ 10363 mutex_init(&hba->dev_cmd.lock); 10364 10365 /* Initialize mutex for exception event control */ 10366 mutex_init(&hba->ee_ctrl_mutex); 10367 10368 mutex_init(&hba->wb_mutex); 10369 init_rwsem(&hba->clk_scaling_lock); 10370 10371 ufshcd_init_clk_gating(hba); 10372 10373 ufshcd_init_clk_scaling(hba); 10374 10375 /* 10376 * In order to avoid any spurious interrupt immediately after 10377 * registering UFS controller interrupt handler, clear any pending UFS 10378 * interrupt status and disable all the UFS interrupts. 10379 */ 10380 ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS), 10381 REG_INTERRUPT_STATUS); 10382 ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE); 10383 /* 10384 * Make sure that UFS interrupts are disabled and any pending interrupt 10385 * status is cleared before registering UFS interrupt handler. 10386 */ 10387 ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 10388 10389 /* IRQ registration */ 10390 err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba); 10391 if (err) { 10392 dev_err(hba->dev, "request irq failed\n"); 10393 goto out_disable; 10394 } else { 10395 hba->is_irq_enabled = true; 10396 } 10397 10398 if (!is_mcq_supported(hba)) { 10399 if (!hba->lsdb_sup) { 10400 dev_err(hba->dev, "%s: failed to initialize (legacy doorbell mode not supported)\n", 10401 __func__); 10402 err = -EINVAL; 10403 goto out_disable; 10404 } 10405 err = scsi_add_host(host, hba->dev); 10406 if (err) { 10407 dev_err(hba->dev, "scsi_add_host failed\n"); 10408 goto out_disable; 10409 } 10410 hba->scsi_host_added = true; 10411 } 10412 10413 hba->tmf_tag_set = (struct blk_mq_tag_set) { 10414 .nr_hw_queues = 1, 10415 .queue_depth = hba->nutmrs, 10416 .ops = &ufshcd_tmf_ops, 10417 .flags = BLK_MQ_F_NO_SCHED, 10418 }; 10419 err = blk_mq_alloc_tag_set(&hba->tmf_tag_set); 10420 if (err < 0) 10421 goto out_remove_scsi_host; 10422 hba->tmf_queue = blk_mq_init_queue(&hba->tmf_tag_set); 10423 if (IS_ERR(hba->tmf_queue)) { 10424 err = PTR_ERR(hba->tmf_queue); 10425 goto free_tmf_tag_set; 10426 } 10427 hba->tmf_rqs = devm_kcalloc(hba->dev, hba->nutmrs, 10428 sizeof(*hba->tmf_rqs), GFP_KERNEL); 10429 if (!hba->tmf_rqs) { 10430 err = -ENOMEM; 10431 goto free_tmf_queue; 10432 } 10433 10434 /* Reset the attached device */ 10435 ufshcd_device_reset(hba); 10436 10437 ufshcd_init_crypto(hba); 10438 10439 /* Host controller enable */ 10440 err = ufshcd_hba_enable(hba); 10441 if (err) { 10442 dev_err(hba->dev, "Host controller enable failed\n"); 10443 ufshcd_print_evt_hist(hba); 10444 ufshcd_print_host_state(hba); 10445 goto free_tmf_queue; 10446 } 10447 10448 /* 10449 * Set the default power management level for runtime and system PM. 10450 * Default power saving mode is to keep UFS link in Hibern8 state 10451 * and UFS device in sleep state. 10452 */ 10453 hba->rpm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state( 10454 UFS_SLEEP_PWR_MODE, 10455 UIC_LINK_HIBERN8_STATE); 10456 hba->spm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state( 10457 UFS_SLEEP_PWR_MODE, 10458 UIC_LINK_HIBERN8_STATE); 10459 10460 INIT_DELAYED_WORK(&hba->rpm_dev_flush_recheck_work, 10461 ufshcd_rpm_dev_flush_recheck_work); 10462 10463 /* Set the default auto-hiberate idle timer value to 150 ms */ 10464 if (ufshcd_is_auto_hibern8_supported(hba) && !hba->ahit) { 10465 hba->ahit = FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, 150) | 10466 FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3); 10467 } 10468 10469 /* Hold auto suspend until async scan completes */ 10470 pm_runtime_get_sync(dev); 10471 atomic_set(&hba->scsi_block_reqs_cnt, 0); 10472 /* 10473 * We are assuming that device wasn't put in sleep/power-down 10474 * state exclusively during the boot stage before kernel. 10475 * This assumption helps avoid doing link startup twice during 10476 * ufshcd_probe_hba(). 10477 */ 10478 ufshcd_set_ufs_dev_active(hba); 10479 10480 async_schedule(ufshcd_async_scan, hba); 10481 ufs_sysfs_add_nodes(hba->dev); 10482 10483 device_enable_async_suspend(dev); 10484 return 0; 10485 10486 free_tmf_queue: 10487 blk_mq_destroy_queue(hba->tmf_queue); 10488 blk_put_queue(hba->tmf_queue); 10489 free_tmf_tag_set: 10490 blk_mq_free_tag_set(&hba->tmf_tag_set); 10491 out_remove_scsi_host: 10492 if (hba->scsi_host_added) 10493 scsi_remove_host(hba->host); 10494 out_disable: 10495 hba->is_irq_enabled = false; 10496 ufshcd_hba_exit(hba); 10497 out_error: 10498 return err; 10499 } 10500 EXPORT_SYMBOL_GPL(ufshcd_init); 10501 10502 void ufshcd_resume_complete(struct device *dev) 10503 { 10504 struct ufs_hba *hba = dev_get_drvdata(dev); 10505 10506 if (hba->complete_put) { 10507 ufshcd_rpm_put(hba); 10508 hba->complete_put = false; 10509 } 10510 } 10511 EXPORT_SYMBOL_GPL(ufshcd_resume_complete); 10512 10513 static bool ufshcd_rpm_ok_for_spm(struct ufs_hba *hba) 10514 { 10515 struct device *dev = &hba->ufs_device_wlun->sdev_gendev; 10516 enum ufs_dev_pwr_mode dev_pwr_mode; 10517 enum uic_link_state link_state; 10518 unsigned long flags; 10519 bool res; 10520 10521 spin_lock_irqsave(&dev->power.lock, flags); 10522 dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl); 10523 link_state = ufs_get_pm_lvl_to_link_pwr_state(hba->spm_lvl); 10524 res = pm_runtime_suspended(dev) && 10525 hba->curr_dev_pwr_mode == dev_pwr_mode && 10526 hba->uic_link_state == link_state && 10527 !hba->dev_info.b_rpm_dev_flush_capable; 10528 spin_unlock_irqrestore(&dev->power.lock, flags); 10529 10530 return res; 10531 } 10532 10533 int __ufshcd_suspend_prepare(struct device *dev, bool rpm_ok_for_spm) 10534 { 10535 struct ufs_hba *hba = dev_get_drvdata(dev); 10536 int ret; 10537 10538 /* 10539 * SCSI assumes that runtime-pm and system-pm for scsi drivers 10540 * are same. And it doesn't wake up the device for system-suspend 10541 * if it's runtime suspended. But ufs doesn't follow that. 10542 * Refer ufshcd_resume_complete() 10543 */ 10544 if (hba->ufs_device_wlun) { 10545 /* Prevent runtime suspend */ 10546 ufshcd_rpm_get_noresume(hba); 10547 /* 10548 * Check if already runtime suspended in same state as system 10549 * suspend would be. 10550 */ 10551 if (!rpm_ok_for_spm || !ufshcd_rpm_ok_for_spm(hba)) { 10552 /* RPM state is not ok for SPM, so runtime resume */ 10553 ret = ufshcd_rpm_resume(hba); 10554 if (ret < 0 && ret != -EACCES) { 10555 ufshcd_rpm_put(hba); 10556 return ret; 10557 } 10558 } 10559 hba->complete_put = true; 10560 } 10561 return 0; 10562 } 10563 EXPORT_SYMBOL_GPL(__ufshcd_suspend_prepare); 10564 10565 int ufshcd_suspend_prepare(struct device *dev) 10566 { 10567 return __ufshcd_suspend_prepare(dev, true); 10568 } 10569 EXPORT_SYMBOL_GPL(ufshcd_suspend_prepare); 10570 10571 #ifdef CONFIG_PM_SLEEP 10572 static int ufshcd_wl_poweroff(struct device *dev) 10573 { 10574 struct scsi_device *sdev = to_scsi_device(dev); 10575 struct ufs_hba *hba = shost_priv(sdev->host); 10576 10577 __ufshcd_wl_suspend(hba, UFS_SHUTDOWN_PM); 10578 return 0; 10579 } 10580 #endif 10581 10582 static int ufshcd_wl_probe(struct device *dev) 10583 { 10584 struct scsi_device *sdev = to_scsi_device(dev); 10585 10586 if (!is_device_wlun(sdev)) 10587 return -ENODEV; 10588 10589 blk_pm_runtime_init(sdev->request_queue, dev); 10590 pm_runtime_set_autosuspend_delay(dev, 0); 10591 pm_runtime_allow(dev); 10592 10593 return 0; 10594 } 10595 10596 static int ufshcd_wl_remove(struct device *dev) 10597 { 10598 pm_runtime_forbid(dev); 10599 return 0; 10600 } 10601 10602 static const struct dev_pm_ops ufshcd_wl_pm_ops = { 10603 #ifdef CONFIG_PM_SLEEP 10604 .suspend = ufshcd_wl_suspend, 10605 .resume = ufshcd_wl_resume, 10606 .freeze = ufshcd_wl_suspend, 10607 .thaw = ufshcd_wl_resume, 10608 .poweroff = ufshcd_wl_poweroff, 10609 .restore = ufshcd_wl_resume, 10610 #endif 10611 SET_RUNTIME_PM_OPS(ufshcd_wl_runtime_suspend, ufshcd_wl_runtime_resume, NULL) 10612 }; 10613 10614 static void ufshcd_check_header_layout(void) 10615 { 10616 /* 10617 * gcc compilers before version 10 cannot do constant-folding for 10618 * sub-byte bitfields. Hence skip the layout checks for gcc 9 and 10619 * before. 10620 */ 10621 if (IS_ENABLED(CONFIG_CC_IS_GCC) && CONFIG_GCC_VERSION < 100000) 10622 return; 10623 10624 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10625 .cci = 3})[0] != 3); 10626 10627 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10628 .ehs_length = 2})[1] != 2); 10629 10630 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10631 .enable_crypto = 1})[2] 10632 != 0x80); 10633 10634 BUILD_BUG_ON((((u8 *)&(struct request_desc_header){ 10635 .command_type = 5, 10636 .data_direction = 3, 10637 .interrupt = 1, 10638 })[3]) != ((5 << 4) | (3 << 1) | 1)); 10639 10640 BUILD_BUG_ON(((__le32 *)&(struct request_desc_header){ 10641 .dunl = cpu_to_le32(0xdeadbeef)})[1] != 10642 cpu_to_le32(0xdeadbeef)); 10643 10644 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10645 .ocs = 4})[8] != 4); 10646 10647 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10648 .cds = 5})[9] != 5); 10649 10650 BUILD_BUG_ON(((__le32 *)&(struct request_desc_header){ 10651 .dunu = cpu_to_le32(0xbadcafe)})[3] != 10652 cpu_to_le32(0xbadcafe)); 10653 10654 BUILD_BUG_ON(((u8 *)&(struct utp_upiu_header){ 10655 .iid = 0xf })[4] != 0xf0); 10656 10657 BUILD_BUG_ON(((u8 *)&(struct utp_upiu_header){ 10658 .command_set_type = 0xf })[4] != 0xf); 10659 } 10660 10661 /* 10662 * ufs_dev_wlun_template - describes ufs device wlun 10663 * ufs-device wlun - used to send pm commands 10664 * All luns are consumers of ufs-device wlun. 10665 * 10666 * Currently, no sd driver is present for wluns. 10667 * Hence the no specific pm operations are performed. 10668 * With ufs design, SSU should be sent to ufs-device wlun. 10669 * Hence register a scsi driver for ufs wluns only. 10670 */ 10671 static struct scsi_driver ufs_dev_wlun_template = { 10672 .gendrv = { 10673 .name = "ufs_device_wlun", 10674 .owner = THIS_MODULE, 10675 .probe = ufshcd_wl_probe, 10676 .remove = ufshcd_wl_remove, 10677 .pm = &ufshcd_wl_pm_ops, 10678 .shutdown = ufshcd_wl_shutdown, 10679 }, 10680 }; 10681 10682 static int __init ufshcd_core_init(void) 10683 { 10684 int ret; 10685 10686 ufshcd_check_header_layout(); 10687 10688 ufs_debugfs_init(); 10689 10690 ret = scsi_register_driver(&ufs_dev_wlun_template.gendrv); 10691 if (ret) 10692 ufs_debugfs_exit(); 10693 return ret; 10694 } 10695 10696 static void __exit ufshcd_core_exit(void) 10697 { 10698 ufs_debugfs_exit(); 10699 scsi_unregister_driver(&ufs_dev_wlun_template.gendrv); 10700 } 10701 10702 module_init(ufshcd_core_init); 10703 module_exit(ufshcd_core_exit); 10704 10705 MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>"); 10706 MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>"); 10707 MODULE_DESCRIPTION("Generic UFS host controller driver Core"); 10708 MODULE_SOFTDEP("pre: governor_simpleondemand"); 10709 MODULE_LICENSE("GPL"); 10710