1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Universal Flash Storage Host controller driver Core 4 * Copyright (C) 2011-2013 Samsung India Software Operations 5 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. 6 * 7 * Authors: 8 * Santosh Yaraganavi <santosh.sy@samsung.com> 9 * Vinayak Holikatti <h.vinayak@samsung.com> 10 */ 11 12 #include <linux/async.h> 13 #include <linux/devfreq.h> 14 #include <linux/nls.h> 15 #include <linux/of.h> 16 #include <linux/bitfield.h> 17 #include <linux/blk-pm.h> 18 #include <linux/blkdev.h> 19 #include <linux/clk.h> 20 #include <linux/delay.h> 21 #include <linux/interrupt.h> 22 #include <linux/module.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/sched/clock.h> 25 #include <linux/iopoll.h> 26 #include <scsi/scsi_cmnd.h> 27 #include <scsi/scsi_dbg.h> 28 #include <scsi/scsi_driver.h> 29 #include <scsi/scsi_eh.h> 30 #include "ufshcd-priv.h" 31 #include <ufs/ufs_quirks.h> 32 #include <ufs/unipro.h> 33 #include "ufs-sysfs.h" 34 #include "ufs-debugfs.h" 35 #include "ufs-fault-injection.h" 36 #include "ufs_bsg.h" 37 #include "ufshcd-crypto.h" 38 #include <asm/unaligned.h> 39 40 #define CREATE_TRACE_POINTS 41 #include <trace/events/ufs.h> 42 43 #define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\ 44 UTP_TASK_REQ_COMPL |\ 45 UFSHCD_ERROR_MASK) 46 47 #define UFSHCD_ENABLE_MCQ_INTRS (UTP_TASK_REQ_COMPL |\ 48 UFSHCD_ERROR_MASK |\ 49 MCQ_CQ_EVENT_STATUS) 50 51 52 /* UIC command timeout, unit: ms */ 53 #define UIC_CMD_TIMEOUT 500 54 55 /* NOP OUT retries waiting for NOP IN response */ 56 #define NOP_OUT_RETRIES 10 57 /* Timeout after 50 msecs if NOP OUT hangs without response */ 58 #define NOP_OUT_TIMEOUT 50 /* msecs */ 59 60 /* Query request retries */ 61 #define QUERY_REQ_RETRIES 3 62 /* Query request timeout */ 63 #define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */ 64 65 /* Advanced RPMB request timeout */ 66 #define ADVANCED_RPMB_REQ_TIMEOUT 3000 /* 3 seconds */ 67 68 /* Task management command timeout */ 69 #define TM_CMD_TIMEOUT 100 /* msecs */ 70 71 /* maximum number of retries for a general UIC command */ 72 #define UFS_UIC_COMMAND_RETRIES 3 73 74 /* maximum number of link-startup retries */ 75 #define DME_LINKSTARTUP_RETRIES 3 76 77 /* maximum number of reset retries before giving up */ 78 #define MAX_HOST_RESET_RETRIES 5 79 80 /* Maximum number of error handler retries before giving up */ 81 #define MAX_ERR_HANDLER_RETRIES 5 82 83 /* Expose the flag value from utp_upiu_query.value */ 84 #define MASK_QUERY_UPIU_FLAG_LOC 0xFF 85 86 /* Interrupt aggregation default timeout, unit: 40us */ 87 #define INT_AGGR_DEF_TO 0x02 88 89 /* default delay of autosuspend: 2000 ms */ 90 #define RPM_AUTOSUSPEND_DELAY_MS 2000 91 92 /* Default delay of RPM device flush delayed work */ 93 #define RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS 5000 94 95 /* Default value of wait time before gating device ref clock */ 96 #define UFSHCD_REF_CLK_GATING_WAIT_US 0xFF /* microsecs */ 97 98 /* Polling time to wait for fDeviceInit */ 99 #define FDEVICEINIT_COMPL_TIMEOUT 1500 /* millisecs */ 100 101 /* UFSHC 4.0 compliant HC support this mode. */ 102 static bool use_mcq_mode = true; 103 104 static bool is_mcq_supported(struct ufs_hba *hba) 105 { 106 return hba->mcq_sup && use_mcq_mode; 107 } 108 109 module_param(use_mcq_mode, bool, 0644); 110 MODULE_PARM_DESC(use_mcq_mode, "Control MCQ mode for controllers starting from UFSHCI 4.0. 1 - enable MCQ, 0 - disable MCQ. MCQ is enabled by default"); 111 112 #define ufshcd_toggle_vreg(_dev, _vreg, _on) \ 113 ({ \ 114 int _ret; \ 115 if (_on) \ 116 _ret = ufshcd_enable_vreg(_dev, _vreg); \ 117 else \ 118 _ret = ufshcd_disable_vreg(_dev, _vreg); \ 119 _ret; \ 120 }) 121 122 #define ufshcd_hex_dump(prefix_str, buf, len) do { \ 123 size_t __len = (len); \ 124 print_hex_dump(KERN_ERR, prefix_str, \ 125 __len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE,\ 126 16, 4, buf, __len, false); \ 127 } while (0) 128 129 int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len, 130 const char *prefix) 131 { 132 u32 *regs; 133 size_t pos; 134 135 if (offset % 4 != 0 || len % 4 != 0) /* keep readl happy */ 136 return -EINVAL; 137 138 regs = kzalloc(len, GFP_ATOMIC); 139 if (!regs) 140 return -ENOMEM; 141 142 for (pos = 0; pos < len; pos += 4) { 143 if (offset == 0 && 144 pos >= REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER && 145 pos <= REG_UIC_ERROR_CODE_DME) 146 continue; 147 regs[pos / 4] = ufshcd_readl(hba, offset + pos); 148 } 149 150 ufshcd_hex_dump(prefix, regs, len); 151 kfree(regs); 152 153 return 0; 154 } 155 EXPORT_SYMBOL_GPL(ufshcd_dump_regs); 156 157 enum { 158 UFSHCD_MAX_CHANNEL = 0, 159 UFSHCD_MAX_ID = 1, 160 UFSHCD_CMD_PER_LUN = 32 - UFSHCD_NUM_RESERVED, 161 UFSHCD_CAN_QUEUE = 32 - UFSHCD_NUM_RESERVED, 162 }; 163 164 static const char *const ufshcd_state_name[] = { 165 [UFSHCD_STATE_RESET] = "reset", 166 [UFSHCD_STATE_OPERATIONAL] = "operational", 167 [UFSHCD_STATE_ERROR] = "error", 168 [UFSHCD_STATE_EH_SCHEDULED_FATAL] = "eh_fatal", 169 [UFSHCD_STATE_EH_SCHEDULED_NON_FATAL] = "eh_non_fatal", 170 }; 171 172 /* UFSHCD error handling flags */ 173 enum { 174 UFSHCD_EH_IN_PROGRESS = (1 << 0), 175 }; 176 177 /* UFSHCD UIC layer error flags */ 178 enum { 179 UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */ 180 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR = (1 << 1), /* Data link layer error */ 181 UFSHCD_UIC_DL_TCx_REPLAY_ERROR = (1 << 2), /* Data link layer error */ 182 UFSHCD_UIC_NL_ERROR = (1 << 3), /* Network layer error */ 183 UFSHCD_UIC_TL_ERROR = (1 << 4), /* Transport Layer error */ 184 UFSHCD_UIC_DME_ERROR = (1 << 5), /* DME error */ 185 UFSHCD_UIC_PA_GENERIC_ERROR = (1 << 6), /* Generic PA error */ 186 }; 187 188 #define ufshcd_set_eh_in_progress(h) \ 189 ((h)->eh_flags |= UFSHCD_EH_IN_PROGRESS) 190 #define ufshcd_eh_in_progress(h) \ 191 ((h)->eh_flags & UFSHCD_EH_IN_PROGRESS) 192 #define ufshcd_clear_eh_in_progress(h) \ 193 ((h)->eh_flags &= ~UFSHCD_EH_IN_PROGRESS) 194 195 const struct ufs_pm_lvl_states ufs_pm_lvl_states[] = { 196 [UFS_PM_LVL_0] = {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE}, 197 [UFS_PM_LVL_1] = {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE}, 198 [UFS_PM_LVL_2] = {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE}, 199 [UFS_PM_LVL_3] = {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE}, 200 [UFS_PM_LVL_4] = {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE}, 201 [UFS_PM_LVL_5] = {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE}, 202 /* 203 * For DeepSleep, the link is first put in hibern8 and then off. 204 * Leaving the link in hibern8 is not supported. 205 */ 206 [UFS_PM_LVL_6] = {UFS_DEEPSLEEP_PWR_MODE, UIC_LINK_OFF_STATE}, 207 }; 208 209 static inline enum ufs_dev_pwr_mode 210 ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl) 211 { 212 return ufs_pm_lvl_states[lvl].dev_state; 213 } 214 215 static inline enum uic_link_state 216 ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl) 217 { 218 return ufs_pm_lvl_states[lvl].link_state; 219 } 220 221 static inline enum ufs_pm_level 222 ufs_get_desired_pm_lvl_for_dev_link_state(enum ufs_dev_pwr_mode dev_state, 223 enum uic_link_state link_state) 224 { 225 enum ufs_pm_level lvl; 226 227 for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++) { 228 if ((ufs_pm_lvl_states[lvl].dev_state == dev_state) && 229 (ufs_pm_lvl_states[lvl].link_state == link_state)) 230 return lvl; 231 } 232 233 /* if no match found, return the level 0 */ 234 return UFS_PM_LVL_0; 235 } 236 237 static const struct ufs_dev_quirk ufs_fixups[] = { 238 /* UFS cards deviations table */ 239 { .wmanufacturerid = UFS_VENDOR_MICRON, 240 .model = UFS_ANY_MODEL, 241 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM }, 242 { .wmanufacturerid = UFS_VENDOR_SAMSUNG, 243 .model = UFS_ANY_MODEL, 244 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM | 245 UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE | 246 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS }, 247 { .wmanufacturerid = UFS_VENDOR_SKHYNIX, 248 .model = UFS_ANY_MODEL, 249 .quirk = UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME }, 250 { .wmanufacturerid = UFS_VENDOR_SKHYNIX, 251 .model = "hB8aL1" /*H28U62301AMR*/, 252 .quirk = UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME }, 253 { .wmanufacturerid = UFS_VENDOR_TOSHIBA, 254 .model = UFS_ANY_MODEL, 255 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM }, 256 { .wmanufacturerid = UFS_VENDOR_TOSHIBA, 257 .model = "THGLF2G9C8KBADG", 258 .quirk = UFS_DEVICE_QUIRK_PA_TACTIVATE }, 259 { .wmanufacturerid = UFS_VENDOR_TOSHIBA, 260 .model = "THGLF2G9D8KBADG", 261 .quirk = UFS_DEVICE_QUIRK_PA_TACTIVATE }, 262 {} 263 }; 264 265 static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba); 266 static void ufshcd_async_scan(void *data, async_cookie_t cookie); 267 static int ufshcd_reset_and_restore(struct ufs_hba *hba); 268 static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd); 269 static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag); 270 static void ufshcd_hba_exit(struct ufs_hba *hba); 271 static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params); 272 static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on); 273 static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba); 274 static int ufshcd_host_reset_and_restore(struct ufs_hba *hba); 275 static void ufshcd_resume_clkscaling(struct ufs_hba *hba); 276 static void ufshcd_suspend_clkscaling(struct ufs_hba *hba); 277 static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba); 278 static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up); 279 static irqreturn_t ufshcd_intr(int irq, void *__hba); 280 static int ufshcd_change_power_mode(struct ufs_hba *hba, 281 struct ufs_pa_layer_attr *pwr_mode); 282 static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on); 283 static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on); 284 static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba, 285 struct ufs_vreg *vreg); 286 static void ufshcd_wb_toggle_buf_flush_during_h8(struct ufs_hba *hba, 287 bool enable); 288 static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba); 289 static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba); 290 291 static inline void ufshcd_enable_irq(struct ufs_hba *hba) 292 { 293 if (!hba->is_irq_enabled) { 294 enable_irq(hba->irq); 295 hba->is_irq_enabled = true; 296 } 297 } 298 299 static inline void ufshcd_disable_irq(struct ufs_hba *hba) 300 { 301 if (hba->is_irq_enabled) { 302 disable_irq(hba->irq); 303 hba->is_irq_enabled = false; 304 } 305 } 306 307 static void ufshcd_configure_wb(struct ufs_hba *hba) 308 { 309 if (!ufshcd_is_wb_allowed(hba)) 310 return; 311 312 ufshcd_wb_toggle(hba, true); 313 314 ufshcd_wb_toggle_buf_flush_during_h8(hba, true); 315 316 if (ufshcd_is_wb_buf_flush_allowed(hba)) 317 ufshcd_wb_toggle_buf_flush(hba, true); 318 } 319 320 static void ufshcd_scsi_unblock_requests(struct ufs_hba *hba) 321 { 322 if (atomic_dec_and_test(&hba->scsi_block_reqs_cnt)) 323 scsi_unblock_requests(hba->host); 324 } 325 326 static void ufshcd_scsi_block_requests(struct ufs_hba *hba) 327 { 328 if (atomic_inc_return(&hba->scsi_block_reqs_cnt) == 1) 329 scsi_block_requests(hba->host); 330 } 331 332 static void ufshcd_add_cmd_upiu_trace(struct ufs_hba *hba, unsigned int tag, 333 enum ufs_trace_str_t str_t) 334 { 335 struct utp_upiu_req *rq = hba->lrb[tag].ucd_req_ptr; 336 struct utp_upiu_header *header; 337 338 if (!trace_ufshcd_upiu_enabled()) 339 return; 340 341 if (str_t == UFS_CMD_SEND) 342 header = &rq->header; 343 else 344 header = &hba->lrb[tag].ucd_rsp_ptr->header; 345 346 trace_ufshcd_upiu(dev_name(hba->dev), str_t, header, &rq->sc.cdb, 347 UFS_TSF_CDB); 348 } 349 350 static void ufshcd_add_query_upiu_trace(struct ufs_hba *hba, 351 enum ufs_trace_str_t str_t, 352 struct utp_upiu_req *rq_rsp) 353 { 354 if (!trace_ufshcd_upiu_enabled()) 355 return; 356 357 trace_ufshcd_upiu(dev_name(hba->dev), str_t, &rq_rsp->header, 358 &rq_rsp->qr, UFS_TSF_OSF); 359 } 360 361 static void ufshcd_add_tm_upiu_trace(struct ufs_hba *hba, unsigned int tag, 362 enum ufs_trace_str_t str_t) 363 { 364 struct utp_task_req_desc *descp = &hba->utmrdl_base_addr[tag]; 365 366 if (!trace_ufshcd_upiu_enabled()) 367 return; 368 369 if (str_t == UFS_TM_SEND) 370 trace_ufshcd_upiu(dev_name(hba->dev), str_t, 371 &descp->upiu_req.req_header, 372 &descp->upiu_req.input_param1, 373 UFS_TSF_TM_INPUT); 374 else 375 trace_ufshcd_upiu(dev_name(hba->dev), str_t, 376 &descp->upiu_rsp.rsp_header, 377 &descp->upiu_rsp.output_param1, 378 UFS_TSF_TM_OUTPUT); 379 } 380 381 static void ufshcd_add_uic_command_trace(struct ufs_hba *hba, 382 const struct uic_command *ucmd, 383 enum ufs_trace_str_t str_t) 384 { 385 u32 cmd; 386 387 if (!trace_ufshcd_uic_command_enabled()) 388 return; 389 390 if (str_t == UFS_CMD_SEND) 391 cmd = ucmd->command; 392 else 393 cmd = ufshcd_readl(hba, REG_UIC_COMMAND); 394 395 trace_ufshcd_uic_command(dev_name(hba->dev), str_t, cmd, 396 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_1), 397 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2), 398 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3)); 399 } 400 401 static void ufshcd_add_command_trace(struct ufs_hba *hba, unsigned int tag, 402 enum ufs_trace_str_t str_t) 403 { 404 u64 lba = 0; 405 u8 opcode = 0, group_id = 0; 406 u32 doorbell = 0; 407 u32 intr; 408 int hwq_id = -1; 409 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 410 struct scsi_cmnd *cmd = lrbp->cmd; 411 struct request *rq = scsi_cmd_to_rq(cmd); 412 int transfer_len = -1; 413 414 if (!cmd) 415 return; 416 417 /* trace UPIU also */ 418 ufshcd_add_cmd_upiu_trace(hba, tag, str_t); 419 if (!trace_ufshcd_command_enabled()) 420 return; 421 422 opcode = cmd->cmnd[0]; 423 424 if (opcode == READ_10 || opcode == WRITE_10) { 425 /* 426 * Currently we only fully trace read(10) and write(10) commands 427 */ 428 transfer_len = 429 be32_to_cpu(lrbp->ucd_req_ptr->sc.exp_data_transfer_len); 430 lba = scsi_get_lba(cmd); 431 if (opcode == WRITE_10) 432 group_id = lrbp->cmd->cmnd[6]; 433 } else if (opcode == UNMAP) { 434 /* 435 * The number of Bytes to be unmapped beginning with the lba. 436 */ 437 transfer_len = blk_rq_bytes(rq); 438 lba = scsi_get_lba(cmd); 439 } 440 441 intr = ufshcd_readl(hba, REG_INTERRUPT_STATUS); 442 443 if (is_mcq_enabled(hba)) { 444 struct ufs_hw_queue *hwq = ufshcd_mcq_req_to_hwq(hba, rq); 445 446 hwq_id = hwq->id; 447 } else { 448 doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 449 } 450 trace_ufshcd_command(dev_name(hba->dev), str_t, tag, 451 doorbell, hwq_id, transfer_len, intr, lba, opcode, group_id); 452 } 453 454 static void ufshcd_print_clk_freqs(struct ufs_hba *hba) 455 { 456 struct ufs_clk_info *clki; 457 struct list_head *head = &hba->clk_list_head; 458 459 if (list_empty(head)) 460 return; 461 462 list_for_each_entry(clki, head, list) { 463 if (!IS_ERR_OR_NULL(clki->clk) && clki->min_freq && 464 clki->max_freq) 465 dev_err(hba->dev, "clk: %s, rate: %u\n", 466 clki->name, clki->curr_freq); 467 } 468 } 469 470 static void ufshcd_print_evt(struct ufs_hba *hba, u32 id, 471 const char *err_name) 472 { 473 int i; 474 bool found = false; 475 const struct ufs_event_hist *e; 476 477 if (id >= UFS_EVT_CNT) 478 return; 479 480 e = &hba->ufs_stats.event[id]; 481 482 for (i = 0; i < UFS_EVENT_HIST_LENGTH; i++) { 483 int p = (i + e->pos) % UFS_EVENT_HIST_LENGTH; 484 485 if (e->tstamp[p] == 0) 486 continue; 487 dev_err(hba->dev, "%s[%d] = 0x%x at %lld us\n", err_name, p, 488 e->val[p], div_u64(e->tstamp[p], 1000)); 489 found = true; 490 } 491 492 if (!found) 493 dev_err(hba->dev, "No record of %s\n", err_name); 494 else 495 dev_err(hba->dev, "%s: total cnt=%llu\n", err_name, e->cnt); 496 } 497 498 static void ufshcd_print_evt_hist(struct ufs_hba *hba) 499 { 500 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: "); 501 502 ufshcd_print_evt(hba, UFS_EVT_PA_ERR, "pa_err"); 503 ufshcd_print_evt(hba, UFS_EVT_DL_ERR, "dl_err"); 504 ufshcd_print_evt(hba, UFS_EVT_NL_ERR, "nl_err"); 505 ufshcd_print_evt(hba, UFS_EVT_TL_ERR, "tl_err"); 506 ufshcd_print_evt(hba, UFS_EVT_DME_ERR, "dme_err"); 507 ufshcd_print_evt(hba, UFS_EVT_AUTO_HIBERN8_ERR, 508 "auto_hibern8_err"); 509 ufshcd_print_evt(hba, UFS_EVT_FATAL_ERR, "fatal_err"); 510 ufshcd_print_evt(hba, UFS_EVT_LINK_STARTUP_FAIL, 511 "link_startup_fail"); 512 ufshcd_print_evt(hba, UFS_EVT_RESUME_ERR, "resume_fail"); 513 ufshcd_print_evt(hba, UFS_EVT_SUSPEND_ERR, 514 "suspend_fail"); 515 ufshcd_print_evt(hba, UFS_EVT_WL_RES_ERR, "wlun resume_fail"); 516 ufshcd_print_evt(hba, UFS_EVT_WL_SUSP_ERR, 517 "wlun suspend_fail"); 518 ufshcd_print_evt(hba, UFS_EVT_DEV_RESET, "dev_reset"); 519 ufshcd_print_evt(hba, UFS_EVT_HOST_RESET, "host_reset"); 520 ufshcd_print_evt(hba, UFS_EVT_ABORT, "task_abort"); 521 522 ufshcd_vops_dbg_register_dump(hba); 523 } 524 525 static 526 void ufshcd_print_tr(struct ufs_hba *hba, int tag, bool pr_prdt) 527 { 528 const struct ufshcd_lrb *lrbp; 529 int prdt_length; 530 531 lrbp = &hba->lrb[tag]; 532 533 dev_err(hba->dev, "UPIU[%d] - issue time %lld us\n", 534 tag, div_u64(lrbp->issue_time_stamp_local_clock, 1000)); 535 dev_err(hba->dev, "UPIU[%d] - complete time %lld us\n", 536 tag, div_u64(lrbp->compl_time_stamp_local_clock, 1000)); 537 dev_err(hba->dev, 538 "UPIU[%d] - Transfer Request Descriptor phys@0x%llx\n", 539 tag, (u64)lrbp->utrd_dma_addr); 540 541 ufshcd_hex_dump("UPIU TRD: ", lrbp->utr_descriptor_ptr, 542 sizeof(struct utp_transfer_req_desc)); 543 dev_err(hba->dev, "UPIU[%d] - Request UPIU phys@0x%llx\n", tag, 544 (u64)lrbp->ucd_req_dma_addr); 545 ufshcd_hex_dump("UPIU REQ: ", lrbp->ucd_req_ptr, 546 sizeof(struct utp_upiu_req)); 547 dev_err(hba->dev, "UPIU[%d] - Response UPIU phys@0x%llx\n", tag, 548 (u64)lrbp->ucd_rsp_dma_addr); 549 ufshcd_hex_dump("UPIU RSP: ", lrbp->ucd_rsp_ptr, 550 sizeof(struct utp_upiu_rsp)); 551 552 prdt_length = le16_to_cpu( 553 lrbp->utr_descriptor_ptr->prd_table_length); 554 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) 555 prdt_length /= ufshcd_sg_entry_size(hba); 556 557 dev_err(hba->dev, 558 "UPIU[%d] - PRDT - %d entries phys@0x%llx\n", 559 tag, prdt_length, 560 (u64)lrbp->ucd_prdt_dma_addr); 561 562 if (pr_prdt) 563 ufshcd_hex_dump("UPIU PRDT: ", lrbp->ucd_prdt_ptr, 564 ufshcd_sg_entry_size(hba) * prdt_length); 565 } 566 567 static bool ufshcd_print_tr_iter(struct request *req, void *priv) 568 { 569 struct scsi_device *sdev = req->q->queuedata; 570 struct Scsi_Host *shost = sdev->host; 571 struct ufs_hba *hba = shost_priv(shost); 572 573 ufshcd_print_tr(hba, req->tag, *(bool *)priv); 574 575 return true; 576 } 577 578 /** 579 * ufshcd_print_trs_all - print trs for all started requests. 580 * @hba: per-adapter instance. 581 * @pr_prdt: need to print prdt or not. 582 */ 583 static void ufshcd_print_trs_all(struct ufs_hba *hba, bool pr_prdt) 584 { 585 blk_mq_tagset_busy_iter(&hba->host->tag_set, ufshcd_print_tr_iter, &pr_prdt); 586 } 587 588 static void ufshcd_print_tmrs(struct ufs_hba *hba, unsigned long bitmap) 589 { 590 int tag; 591 592 for_each_set_bit(tag, &bitmap, hba->nutmrs) { 593 struct utp_task_req_desc *tmrdp = &hba->utmrdl_base_addr[tag]; 594 595 dev_err(hba->dev, "TM[%d] - Task Management Header\n", tag); 596 ufshcd_hex_dump("", tmrdp, sizeof(*tmrdp)); 597 } 598 } 599 600 static void ufshcd_print_host_state(struct ufs_hba *hba) 601 { 602 const struct scsi_device *sdev_ufs = hba->ufs_device_wlun; 603 604 dev_err(hba->dev, "UFS Host state=%d\n", hba->ufshcd_state); 605 dev_err(hba->dev, "outstanding reqs=0x%lx tasks=0x%lx\n", 606 hba->outstanding_reqs, hba->outstanding_tasks); 607 dev_err(hba->dev, "saved_err=0x%x, saved_uic_err=0x%x\n", 608 hba->saved_err, hba->saved_uic_err); 609 dev_err(hba->dev, "Device power mode=%d, UIC link state=%d\n", 610 hba->curr_dev_pwr_mode, hba->uic_link_state); 611 dev_err(hba->dev, "PM in progress=%d, sys. suspended=%d\n", 612 hba->pm_op_in_progress, hba->is_sys_suspended); 613 dev_err(hba->dev, "Auto BKOPS=%d, Host self-block=%d\n", 614 hba->auto_bkops_enabled, hba->host->host_self_blocked); 615 dev_err(hba->dev, "Clk gate=%d\n", hba->clk_gating.state); 616 dev_err(hba->dev, 617 "last_hibern8_exit_tstamp at %lld us, hibern8_exit_cnt=%d\n", 618 div_u64(hba->ufs_stats.last_hibern8_exit_tstamp, 1000), 619 hba->ufs_stats.hibern8_exit_cnt); 620 dev_err(hba->dev, "last intr at %lld us, last intr status=0x%x\n", 621 div_u64(hba->ufs_stats.last_intr_ts, 1000), 622 hba->ufs_stats.last_intr_status); 623 dev_err(hba->dev, "error handling flags=0x%x, req. abort count=%d\n", 624 hba->eh_flags, hba->req_abort_count); 625 dev_err(hba->dev, "hba->ufs_version=0x%x, Host capabilities=0x%x, caps=0x%x\n", 626 hba->ufs_version, hba->capabilities, hba->caps); 627 dev_err(hba->dev, "quirks=0x%x, dev. quirks=0x%x\n", hba->quirks, 628 hba->dev_quirks); 629 if (sdev_ufs) 630 dev_err(hba->dev, "UFS dev info: %.8s %.16s rev %.4s\n", 631 sdev_ufs->vendor, sdev_ufs->model, sdev_ufs->rev); 632 633 ufshcd_print_clk_freqs(hba); 634 } 635 636 /** 637 * ufshcd_print_pwr_info - print power params as saved in hba 638 * power info 639 * @hba: per-adapter instance 640 */ 641 static void ufshcd_print_pwr_info(struct ufs_hba *hba) 642 { 643 static const char * const names[] = { 644 "INVALID MODE", 645 "FAST MODE", 646 "SLOW_MODE", 647 "INVALID MODE", 648 "FASTAUTO_MODE", 649 "SLOWAUTO_MODE", 650 "INVALID MODE", 651 }; 652 653 /* 654 * Using dev_dbg to avoid messages during runtime PM to avoid 655 * never-ending cycles of messages written back to storage by user space 656 * causing runtime resume, causing more messages and so on. 657 */ 658 dev_dbg(hba->dev, "%s:[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n", 659 __func__, 660 hba->pwr_info.gear_rx, hba->pwr_info.gear_tx, 661 hba->pwr_info.lane_rx, hba->pwr_info.lane_tx, 662 names[hba->pwr_info.pwr_rx], 663 names[hba->pwr_info.pwr_tx], 664 hba->pwr_info.hs_rate); 665 } 666 667 static void ufshcd_device_reset(struct ufs_hba *hba) 668 { 669 int err; 670 671 err = ufshcd_vops_device_reset(hba); 672 673 if (!err) { 674 ufshcd_set_ufs_dev_active(hba); 675 if (ufshcd_is_wb_allowed(hba)) { 676 hba->dev_info.wb_enabled = false; 677 hba->dev_info.wb_buf_flush_enabled = false; 678 } 679 } 680 if (err != -EOPNOTSUPP) 681 ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, err); 682 } 683 684 void ufshcd_delay_us(unsigned long us, unsigned long tolerance) 685 { 686 if (!us) 687 return; 688 689 if (us < 10) 690 udelay(us); 691 else 692 usleep_range(us, us + tolerance); 693 } 694 EXPORT_SYMBOL_GPL(ufshcd_delay_us); 695 696 /** 697 * ufshcd_wait_for_register - wait for register value to change 698 * @hba: per-adapter interface 699 * @reg: mmio register offset 700 * @mask: mask to apply to the read register value 701 * @val: value to wait for 702 * @interval_us: polling interval in microseconds 703 * @timeout_ms: timeout in milliseconds 704 * 705 * Return: -ETIMEDOUT on error, zero on success. 706 */ 707 static int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask, 708 u32 val, unsigned long interval_us, 709 unsigned long timeout_ms) 710 { 711 int err = 0; 712 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms); 713 714 /* ignore bits that we don't intend to wait on */ 715 val = val & mask; 716 717 while ((ufshcd_readl(hba, reg) & mask) != val) { 718 usleep_range(interval_us, interval_us + 50); 719 if (time_after(jiffies, timeout)) { 720 if ((ufshcd_readl(hba, reg) & mask) != val) 721 err = -ETIMEDOUT; 722 break; 723 } 724 } 725 726 return err; 727 } 728 729 /** 730 * ufshcd_get_intr_mask - Get the interrupt bit mask 731 * @hba: Pointer to adapter instance 732 * 733 * Return: interrupt bit mask per version 734 */ 735 static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba) 736 { 737 if (hba->ufs_version == ufshci_version(1, 0)) 738 return INTERRUPT_MASK_ALL_VER_10; 739 if (hba->ufs_version <= ufshci_version(2, 0)) 740 return INTERRUPT_MASK_ALL_VER_11; 741 742 return INTERRUPT_MASK_ALL_VER_21; 743 } 744 745 /** 746 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA 747 * @hba: Pointer to adapter instance 748 * 749 * Return: UFSHCI version supported by the controller 750 */ 751 static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba) 752 { 753 u32 ufshci_ver; 754 755 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION) 756 ufshci_ver = ufshcd_vops_get_ufs_hci_version(hba); 757 else 758 ufshci_ver = ufshcd_readl(hba, REG_UFS_VERSION); 759 760 /* 761 * UFSHCI v1.x uses a different version scheme, in order 762 * to allow the use of comparisons with the ufshci_version 763 * function, we convert it to the same scheme as ufs 2.0+. 764 */ 765 if (ufshci_ver & 0x00010000) 766 return ufshci_version(1, ufshci_ver & 0x00000100); 767 768 return ufshci_ver; 769 } 770 771 /** 772 * ufshcd_is_device_present - Check if any device connected to 773 * the host controller 774 * @hba: pointer to adapter instance 775 * 776 * Return: true if device present, false if no device detected 777 */ 778 static inline bool ufshcd_is_device_present(struct ufs_hba *hba) 779 { 780 return ufshcd_readl(hba, REG_CONTROLLER_STATUS) & DEVICE_PRESENT; 781 } 782 783 /** 784 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status 785 * @lrbp: pointer to local command reference block 786 * @cqe: pointer to the completion queue entry 787 * 788 * This function is used to get the OCS field from UTRD 789 * 790 * Return: the OCS field in the UTRD. 791 */ 792 static enum utp_ocs ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp, 793 struct cq_entry *cqe) 794 { 795 if (cqe) 796 return le32_to_cpu(cqe->status) & MASK_OCS; 797 798 return lrbp->utr_descriptor_ptr->header.ocs & MASK_OCS; 799 } 800 801 /** 802 * ufshcd_utrl_clear() - Clear requests from the controller request list. 803 * @hba: per adapter instance 804 * @mask: mask with one bit set for each request to be cleared 805 */ 806 static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 mask) 807 { 808 if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR) 809 mask = ~mask; 810 /* 811 * From the UFSHCI specification: "UTP Transfer Request List CLear 812 * Register (UTRLCLR): This field is bit significant. Each bit 813 * corresponds to a slot in the UTP Transfer Request List, where bit 0 814 * corresponds to request slot 0. A bit in this field is set to ‘0’ 815 * by host software to indicate to the host controller that a transfer 816 * request slot is cleared. The host controller 817 * shall free up any resources associated to the request slot 818 * immediately, and shall set the associated bit in UTRLDBR to ‘0’. The 819 * host software indicates no change to request slots by setting the 820 * associated bits in this field to ‘1’. Bits in this field shall only 821 * be set ‘1’ or ‘0’ by host software when UTRLRSR is set to ‘1’." 822 */ 823 ufshcd_writel(hba, ~mask, REG_UTP_TRANSFER_REQ_LIST_CLEAR); 824 } 825 826 /** 827 * ufshcd_utmrl_clear - Clear a bit in UTMRLCLR register 828 * @hba: per adapter instance 829 * @pos: position of the bit to be cleared 830 */ 831 static inline void ufshcd_utmrl_clear(struct ufs_hba *hba, u32 pos) 832 { 833 if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR) 834 ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR); 835 else 836 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR); 837 } 838 839 /** 840 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY 841 * @reg: Register value of host controller status 842 * 843 * Return: 0 on success; a positive value if failed. 844 */ 845 static inline int ufshcd_get_lists_status(u32 reg) 846 { 847 return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY); 848 } 849 850 /** 851 * ufshcd_get_uic_cmd_result - Get the UIC command result 852 * @hba: Pointer to adapter instance 853 * 854 * This function gets the result of UIC command completion 855 * 856 * Return: 0 on success; non-zero value on error. 857 */ 858 static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba) 859 { 860 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) & 861 MASK_UIC_COMMAND_RESULT; 862 } 863 864 /** 865 * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command 866 * @hba: Pointer to adapter instance 867 * 868 * This function gets UIC command argument3 869 * 870 * Return: 0 on success; non-zero value on error. 871 */ 872 static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba) 873 { 874 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3); 875 } 876 877 /** 878 * ufshcd_get_req_rsp - returns the TR response transaction type 879 * @ucd_rsp_ptr: pointer to response UPIU 880 * 881 * Return: UPIU type. 882 */ 883 static inline enum upiu_response_transaction 884 ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr) 885 { 886 return ucd_rsp_ptr->header.transaction_code; 887 } 888 889 /** 890 * ufshcd_is_exception_event - Check if the device raised an exception event 891 * @ucd_rsp_ptr: pointer to response UPIU 892 * 893 * The function checks if the device raised an exception event indicated in 894 * the Device Information field of response UPIU. 895 * 896 * Return: true if exception is raised, false otherwise. 897 */ 898 static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr) 899 { 900 return ucd_rsp_ptr->header.device_information & 1; 901 } 902 903 /** 904 * ufshcd_reset_intr_aggr - Reset interrupt aggregation values. 905 * @hba: per adapter instance 906 */ 907 static inline void 908 ufshcd_reset_intr_aggr(struct ufs_hba *hba) 909 { 910 ufshcd_writel(hba, INT_AGGR_ENABLE | 911 INT_AGGR_COUNTER_AND_TIMER_RESET, 912 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL); 913 } 914 915 /** 916 * ufshcd_config_intr_aggr - Configure interrupt aggregation values. 917 * @hba: per adapter instance 918 * @cnt: Interrupt aggregation counter threshold 919 * @tmout: Interrupt aggregation timeout value 920 */ 921 static inline void 922 ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout) 923 { 924 ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE | 925 INT_AGGR_COUNTER_THLD_VAL(cnt) | 926 INT_AGGR_TIMEOUT_VAL(tmout), 927 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL); 928 } 929 930 /** 931 * ufshcd_disable_intr_aggr - Disables interrupt aggregation. 932 * @hba: per adapter instance 933 */ 934 static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba) 935 { 936 ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL); 937 } 938 939 /** 940 * ufshcd_enable_run_stop_reg - Enable run-stop registers, 941 * When run-stop registers are set to 1, it indicates the 942 * host controller that it can process the requests 943 * @hba: per adapter instance 944 */ 945 static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba) 946 { 947 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT, 948 REG_UTP_TASK_REQ_LIST_RUN_STOP); 949 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT, 950 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP); 951 } 952 953 /** 954 * ufshcd_hba_start - Start controller initialization sequence 955 * @hba: per adapter instance 956 */ 957 static inline void ufshcd_hba_start(struct ufs_hba *hba) 958 { 959 u32 val = CONTROLLER_ENABLE; 960 961 if (ufshcd_crypto_enable(hba)) 962 val |= CRYPTO_GENERAL_ENABLE; 963 964 ufshcd_writel(hba, val, REG_CONTROLLER_ENABLE); 965 } 966 967 /** 968 * ufshcd_is_hba_active - Get controller state 969 * @hba: per adapter instance 970 * 971 * Return: true if and only if the controller is active. 972 */ 973 bool ufshcd_is_hba_active(struct ufs_hba *hba) 974 { 975 return ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE; 976 } 977 EXPORT_SYMBOL_GPL(ufshcd_is_hba_active); 978 979 u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba) 980 { 981 /* HCI version 1.0 and 1.1 supports UniPro 1.41 */ 982 if (hba->ufs_version <= ufshci_version(1, 1)) 983 return UFS_UNIPRO_VER_1_41; 984 else 985 return UFS_UNIPRO_VER_1_6; 986 } 987 EXPORT_SYMBOL(ufshcd_get_local_unipro_ver); 988 989 static bool ufshcd_is_unipro_pa_params_tuning_req(struct ufs_hba *hba) 990 { 991 /* 992 * If both host and device support UniPro ver1.6 or later, PA layer 993 * parameters tuning happens during link startup itself. 994 * 995 * We can manually tune PA layer parameters if either host or device 996 * doesn't support UniPro ver 1.6 or later. But to keep manual tuning 997 * logic simple, we will only do manual tuning if local unipro version 998 * doesn't support ver1.6 or later. 999 */ 1000 return ufshcd_get_local_unipro_ver(hba) < UFS_UNIPRO_VER_1_6; 1001 } 1002 1003 /** 1004 * ufshcd_set_clk_freq - set UFS controller clock frequencies 1005 * @hba: per adapter instance 1006 * @scale_up: If True, set max possible frequency othewise set low frequency 1007 * 1008 * Return: 0 if successful; < 0 upon failure. 1009 */ 1010 static int ufshcd_set_clk_freq(struct ufs_hba *hba, bool scale_up) 1011 { 1012 int ret = 0; 1013 struct ufs_clk_info *clki; 1014 struct list_head *head = &hba->clk_list_head; 1015 1016 if (list_empty(head)) 1017 goto out; 1018 1019 list_for_each_entry(clki, head, list) { 1020 if (!IS_ERR_OR_NULL(clki->clk)) { 1021 if (scale_up && clki->max_freq) { 1022 if (clki->curr_freq == clki->max_freq) 1023 continue; 1024 1025 ret = clk_set_rate(clki->clk, clki->max_freq); 1026 if (ret) { 1027 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n", 1028 __func__, clki->name, 1029 clki->max_freq, ret); 1030 break; 1031 } 1032 trace_ufshcd_clk_scaling(dev_name(hba->dev), 1033 "scaled up", clki->name, 1034 clki->curr_freq, 1035 clki->max_freq); 1036 1037 clki->curr_freq = clki->max_freq; 1038 1039 } else if (!scale_up && clki->min_freq) { 1040 if (clki->curr_freq == clki->min_freq) 1041 continue; 1042 1043 ret = clk_set_rate(clki->clk, clki->min_freq); 1044 if (ret) { 1045 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n", 1046 __func__, clki->name, 1047 clki->min_freq, ret); 1048 break; 1049 } 1050 trace_ufshcd_clk_scaling(dev_name(hba->dev), 1051 "scaled down", clki->name, 1052 clki->curr_freq, 1053 clki->min_freq); 1054 clki->curr_freq = clki->min_freq; 1055 } 1056 } 1057 dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__, 1058 clki->name, clk_get_rate(clki->clk)); 1059 } 1060 1061 out: 1062 return ret; 1063 } 1064 1065 /** 1066 * ufshcd_scale_clks - scale up or scale down UFS controller clocks 1067 * @hba: per adapter instance 1068 * @scale_up: True if scaling up and false if scaling down 1069 * 1070 * Return: 0 if successful; < 0 upon failure. 1071 */ 1072 static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up) 1073 { 1074 int ret = 0; 1075 ktime_t start = ktime_get(); 1076 1077 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE); 1078 if (ret) 1079 goto out; 1080 1081 ret = ufshcd_set_clk_freq(hba, scale_up); 1082 if (ret) 1083 goto out; 1084 1085 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE); 1086 if (ret) 1087 ufshcd_set_clk_freq(hba, !scale_up); 1088 1089 out: 1090 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev), 1091 (scale_up ? "up" : "down"), 1092 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 1093 return ret; 1094 } 1095 1096 /** 1097 * ufshcd_is_devfreq_scaling_required - check if scaling is required or not 1098 * @hba: per adapter instance 1099 * @scale_up: True if scaling up and false if scaling down 1100 * 1101 * Return: true if scaling is required, false otherwise. 1102 */ 1103 static bool ufshcd_is_devfreq_scaling_required(struct ufs_hba *hba, 1104 bool scale_up) 1105 { 1106 struct ufs_clk_info *clki; 1107 struct list_head *head = &hba->clk_list_head; 1108 1109 if (list_empty(head)) 1110 return false; 1111 1112 list_for_each_entry(clki, head, list) { 1113 if (!IS_ERR_OR_NULL(clki->clk)) { 1114 if (scale_up && clki->max_freq) { 1115 if (clki->curr_freq == clki->max_freq) 1116 continue; 1117 return true; 1118 } else if (!scale_up && clki->min_freq) { 1119 if (clki->curr_freq == clki->min_freq) 1120 continue; 1121 return true; 1122 } 1123 } 1124 } 1125 1126 return false; 1127 } 1128 1129 /* 1130 * Determine the number of pending commands by counting the bits in the SCSI 1131 * device budget maps. This approach has been selected because a bit is set in 1132 * the budget map before scsi_host_queue_ready() checks the host_self_blocked 1133 * flag. The host_self_blocked flag can be modified by calling 1134 * scsi_block_requests() or scsi_unblock_requests(). 1135 */ 1136 static u32 ufshcd_pending_cmds(struct ufs_hba *hba) 1137 { 1138 const struct scsi_device *sdev; 1139 u32 pending = 0; 1140 1141 lockdep_assert_held(hba->host->host_lock); 1142 __shost_for_each_device(sdev, hba->host) 1143 pending += sbitmap_weight(&sdev->budget_map); 1144 1145 return pending; 1146 } 1147 1148 /* 1149 * Wait until all pending SCSI commands and TMFs have finished or the timeout 1150 * has expired. 1151 * 1152 * Return: 0 upon success; -EBUSY upon timeout. 1153 */ 1154 static int ufshcd_wait_for_doorbell_clr(struct ufs_hba *hba, 1155 u64 wait_timeout_us) 1156 { 1157 unsigned long flags; 1158 int ret = 0; 1159 u32 tm_doorbell; 1160 u32 tr_pending; 1161 bool timeout = false, do_last_check = false; 1162 ktime_t start; 1163 1164 ufshcd_hold(hba); 1165 spin_lock_irqsave(hba->host->host_lock, flags); 1166 /* 1167 * Wait for all the outstanding tasks/transfer requests. 1168 * Verify by checking the doorbell registers are clear. 1169 */ 1170 start = ktime_get(); 1171 do { 1172 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) { 1173 ret = -EBUSY; 1174 goto out; 1175 } 1176 1177 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL); 1178 tr_pending = ufshcd_pending_cmds(hba); 1179 if (!tm_doorbell && !tr_pending) { 1180 timeout = false; 1181 break; 1182 } else if (do_last_check) { 1183 break; 1184 } 1185 1186 spin_unlock_irqrestore(hba->host->host_lock, flags); 1187 io_schedule_timeout(msecs_to_jiffies(20)); 1188 if (ktime_to_us(ktime_sub(ktime_get(), start)) > 1189 wait_timeout_us) { 1190 timeout = true; 1191 /* 1192 * We might have scheduled out for long time so make 1193 * sure to check if doorbells are cleared by this time 1194 * or not. 1195 */ 1196 do_last_check = true; 1197 } 1198 spin_lock_irqsave(hba->host->host_lock, flags); 1199 } while (tm_doorbell || tr_pending); 1200 1201 if (timeout) { 1202 dev_err(hba->dev, 1203 "%s: timedout waiting for doorbell to clear (tm=0x%x, tr=0x%x)\n", 1204 __func__, tm_doorbell, tr_pending); 1205 ret = -EBUSY; 1206 } 1207 out: 1208 spin_unlock_irqrestore(hba->host->host_lock, flags); 1209 ufshcd_release(hba); 1210 return ret; 1211 } 1212 1213 /** 1214 * ufshcd_scale_gear - scale up/down UFS gear 1215 * @hba: per adapter instance 1216 * @scale_up: True for scaling up gear and false for scaling down 1217 * 1218 * Return: 0 for success; -EBUSY if scaling can't happen at this time; 1219 * non-zero for any other errors. 1220 */ 1221 static int ufshcd_scale_gear(struct ufs_hba *hba, bool scale_up) 1222 { 1223 int ret = 0; 1224 struct ufs_pa_layer_attr new_pwr_info; 1225 1226 if (scale_up) { 1227 memcpy(&new_pwr_info, &hba->clk_scaling.saved_pwr_info, 1228 sizeof(struct ufs_pa_layer_attr)); 1229 } else { 1230 memcpy(&new_pwr_info, &hba->pwr_info, 1231 sizeof(struct ufs_pa_layer_attr)); 1232 1233 if (hba->pwr_info.gear_tx > hba->clk_scaling.min_gear || 1234 hba->pwr_info.gear_rx > hba->clk_scaling.min_gear) { 1235 /* save the current power mode */ 1236 memcpy(&hba->clk_scaling.saved_pwr_info, 1237 &hba->pwr_info, 1238 sizeof(struct ufs_pa_layer_attr)); 1239 1240 /* scale down gear */ 1241 new_pwr_info.gear_tx = hba->clk_scaling.min_gear; 1242 new_pwr_info.gear_rx = hba->clk_scaling.min_gear; 1243 } 1244 } 1245 1246 /* check if the power mode needs to be changed or not? */ 1247 ret = ufshcd_config_pwr_mode(hba, &new_pwr_info); 1248 if (ret) 1249 dev_err(hba->dev, "%s: failed err %d, old gear: (tx %d rx %d), new gear: (tx %d rx %d)", 1250 __func__, ret, 1251 hba->pwr_info.gear_tx, hba->pwr_info.gear_rx, 1252 new_pwr_info.gear_tx, new_pwr_info.gear_rx); 1253 1254 return ret; 1255 } 1256 1257 /* 1258 * Wait until all pending SCSI commands and TMFs have finished or the timeout 1259 * has expired. 1260 * 1261 * Return: 0 upon success; -EBUSY upon timeout. 1262 */ 1263 static int ufshcd_clock_scaling_prepare(struct ufs_hba *hba, u64 timeout_us) 1264 { 1265 int ret = 0; 1266 /* 1267 * make sure that there are no outstanding requests when 1268 * clock scaling is in progress 1269 */ 1270 ufshcd_scsi_block_requests(hba); 1271 mutex_lock(&hba->wb_mutex); 1272 down_write(&hba->clk_scaling_lock); 1273 1274 if (!hba->clk_scaling.is_allowed || 1275 ufshcd_wait_for_doorbell_clr(hba, timeout_us)) { 1276 ret = -EBUSY; 1277 up_write(&hba->clk_scaling_lock); 1278 mutex_unlock(&hba->wb_mutex); 1279 ufshcd_scsi_unblock_requests(hba); 1280 goto out; 1281 } 1282 1283 /* let's not get into low power until clock scaling is completed */ 1284 ufshcd_hold(hba); 1285 1286 out: 1287 return ret; 1288 } 1289 1290 static void ufshcd_clock_scaling_unprepare(struct ufs_hba *hba, int err, bool scale_up) 1291 { 1292 up_write(&hba->clk_scaling_lock); 1293 1294 /* Enable Write Booster if we have scaled up else disable it */ 1295 if (ufshcd_enable_wb_if_scaling_up(hba) && !err) 1296 ufshcd_wb_toggle(hba, scale_up); 1297 1298 mutex_unlock(&hba->wb_mutex); 1299 1300 ufshcd_scsi_unblock_requests(hba); 1301 ufshcd_release(hba); 1302 } 1303 1304 /** 1305 * ufshcd_devfreq_scale - scale up/down UFS clocks and gear 1306 * @hba: per adapter instance 1307 * @scale_up: True for scaling up and false for scalin down 1308 * 1309 * Return: 0 for success; -EBUSY if scaling can't happen at this time; non-zero 1310 * for any other errors. 1311 */ 1312 static int ufshcd_devfreq_scale(struct ufs_hba *hba, bool scale_up) 1313 { 1314 int ret = 0; 1315 1316 ret = ufshcd_clock_scaling_prepare(hba, 1 * USEC_PER_SEC); 1317 if (ret) 1318 return ret; 1319 1320 /* scale down the gear before scaling down clocks */ 1321 if (!scale_up) { 1322 ret = ufshcd_scale_gear(hba, false); 1323 if (ret) 1324 goto out_unprepare; 1325 } 1326 1327 ret = ufshcd_scale_clks(hba, scale_up); 1328 if (ret) { 1329 if (!scale_up) 1330 ufshcd_scale_gear(hba, true); 1331 goto out_unprepare; 1332 } 1333 1334 /* scale up the gear after scaling up clocks */ 1335 if (scale_up) { 1336 ret = ufshcd_scale_gear(hba, true); 1337 if (ret) { 1338 ufshcd_scale_clks(hba, false); 1339 goto out_unprepare; 1340 } 1341 } 1342 1343 out_unprepare: 1344 ufshcd_clock_scaling_unprepare(hba, ret, scale_up); 1345 return ret; 1346 } 1347 1348 static void ufshcd_clk_scaling_suspend_work(struct work_struct *work) 1349 { 1350 struct ufs_hba *hba = container_of(work, struct ufs_hba, 1351 clk_scaling.suspend_work); 1352 unsigned long irq_flags; 1353 1354 spin_lock_irqsave(hba->host->host_lock, irq_flags); 1355 if (hba->clk_scaling.active_reqs || hba->clk_scaling.is_suspended) { 1356 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1357 return; 1358 } 1359 hba->clk_scaling.is_suspended = true; 1360 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1361 1362 __ufshcd_suspend_clkscaling(hba); 1363 } 1364 1365 static void ufshcd_clk_scaling_resume_work(struct work_struct *work) 1366 { 1367 struct ufs_hba *hba = container_of(work, struct ufs_hba, 1368 clk_scaling.resume_work); 1369 unsigned long irq_flags; 1370 1371 spin_lock_irqsave(hba->host->host_lock, irq_flags); 1372 if (!hba->clk_scaling.is_suspended) { 1373 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1374 return; 1375 } 1376 hba->clk_scaling.is_suspended = false; 1377 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1378 1379 devfreq_resume_device(hba->devfreq); 1380 } 1381 1382 static int ufshcd_devfreq_target(struct device *dev, 1383 unsigned long *freq, u32 flags) 1384 { 1385 int ret = 0; 1386 struct ufs_hba *hba = dev_get_drvdata(dev); 1387 ktime_t start; 1388 bool scale_up, sched_clk_scaling_suspend_work = false; 1389 struct list_head *clk_list = &hba->clk_list_head; 1390 struct ufs_clk_info *clki; 1391 unsigned long irq_flags; 1392 1393 if (!ufshcd_is_clkscaling_supported(hba)) 1394 return -EINVAL; 1395 1396 clki = list_first_entry(&hba->clk_list_head, struct ufs_clk_info, list); 1397 /* Override with the closest supported frequency */ 1398 *freq = (unsigned long) clk_round_rate(clki->clk, *freq); 1399 spin_lock_irqsave(hba->host->host_lock, irq_flags); 1400 if (ufshcd_eh_in_progress(hba)) { 1401 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1402 return 0; 1403 } 1404 1405 if (!hba->clk_scaling.active_reqs) 1406 sched_clk_scaling_suspend_work = true; 1407 1408 if (list_empty(clk_list)) { 1409 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1410 goto out; 1411 } 1412 1413 /* Decide based on the rounded-off frequency and update */ 1414 scale_up = *freq == clki->max_freq; 1415 if (!scale_up) 1416 *freq = clki->min_freq; 1417 /* Update the frequency */ 1418 if (!ufshcd_is_devfreq_scaling_required(hba, scale_up)) { 1419 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1420 ret = 0; 1421 goto out; /* no state change required */ 1422 } 1423 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1424 1425 start = ktime_get(); 1426 ret = ufshcd_devfreq_scale(hba, scale_up); 1427 1428 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev), 1429 (scale_up ? "up" : "down"), 1430 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 1431 1432 out: 1433 if (sched_clk_scaling_suspend_work) 1434 queue_work(hba->clk_scaling.workq, 1435 &hba->clk_scaling.suspend_work); 1436 1437 return ret; 1438 } 1439 1440 static int ufshcd_devfreq_get_dev_status(struct device *dev, 1441 struct devfreq_dev_status *stat) 1442 { 1443 struct ufs_hba *hba = dev_get_drvdata(dev); 1444 struct ufs_clk_scaling *scaling = &hba->clk_scaling; 1445 unsigned long flags; 1446 struct list_head *clk_list = &hba->clk_list_head; 1447 struct ufs_clk_info *clki; 1448 ktime_t curr_t; 1449 1450 if (!ufshcd_is_clkscaling_supported(hba)) 1451 return -EINVAL; 1452 1453 memset(stat, 0, sizeof(*stat)); 1454 1455 spin_lock_irqsave(hba->host->host_lock, flags); 1456 curr_t = ktime_get(); 1457 if (!scaling->window_start_t) 1458 goto start_window; 1459 1460 clki = list_first_entry(clk_list, struct ufs_clk_info, list); 1461 /* 1462 * If current frequency is 0, then the ondemand governor considers 1463 * there's no initial frequency set. And it always requests to set 1464 * to max. frequency. 1465 */ 1466 stat->current_frequency = clki->curr_freq; 1467 if (scaling->is_busy_started) 1468 scaling->tot_busy_t += ktime_us_delta(curr_t, 1469 scaling->busy_start_t); 1470 1471 stat->total_time = ktime_us_delta(curr_t, scaling->window_start_t); 1472 stat->busy_time = scaling->tot_busy_t; 1473 start_window: 1474 scaling->window_start_t = curr_t; 1475 scaling->tot_busy_t = 0; 1476 1477 if (scaling->active_reqs) { 1478 scaling->busy_start_t = curr_t; 1479 scaling->is_busy_started = true; 1480 } else { 1481 scaling->busy_start_t = 0; 1482 scaling->is_busy_started = false; 1483 } 1484 spin_unlock_irqrestore(hba->host->host_lock, flags); 1485 return 0; 1486 } 1487 1488 static int ufshcd_devfreq_init(struct ufs_hba *hba) 1489 { 1490 struct list_head *clk_list = &hba->clk_list_head; 1491 struct ufs_clk_info *clki; 1492 struct devfreq *devfreq; 1493 int ret; 1494 1495 /* Skip devfreq if we don't have any clocks in the list */ 1496 if (list_empty(clk_list)) 1497 return 0; 1498 1499 clki = list_first_entry(clk_list, struct ufs_clk_info, list); 1500 dev_pm_opp_add(hba->dev, clki->min_freq, 0); 1501 dev_pm_opp_add(hba->dev, clki->max_freq, 0); 1502 1503 ufshcd_vops_config_scaling_param(hba, &hba->vps->devfreq_profile, 1504 &hba->vps->ondemand_data); 1505 devfreq = devfreq_add_device(hba->dev, 1506 &hba->vps->devfreq_profile, 1507 DEVFREQ_GOV_SIMPLE_ONDEMAND, 1508 &hba->vps->ondemand_data); 1509 if (IS_ERR(devfreq)) { 1510 ret = PTR_ERR(devfreq); 1511 dev_err(hba->dev, "Unable to register with devfreq %d\n", ret); 1512 1513 dev_pm_opp_remove(hba->dev, clki->min_freq); 1514 dev_pm_opp_remove(hba->dev, clki->max_freq); 1515 return ret; 1516 } 1517 1518 hba->devfreq = devfreq; 1519 1520 return 0; 1521 } 1522 1523 static void ufshcd_devfreq_remove(struct ufs_hba *hba) 1524 { 1525 struct list_head *clk_list = &hba->clk_list_head; 1526 struct ufs_clk_info *clki; 1527 1528 if (!hba->devfreq) 1529 return; 1530 1531 devfreq_remove_device(hba->devfreq); 1532 hba->devfreq = NULL; 1533 1534 clki = list_first_entry(clk_list, struct ufs_clk_info, list); 1535 dev_pm_opp_remove(hba->dev, clki->min_freq); 1536 dev_pm_opp_remove(hba->dev, clki->max_freq); 1537 } 1538 1539 static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba) 1540 { 1541 unsigned long flags; 1542 1543 devfreq_suspend_device(hba->devfreq); 1544 spin_lock_irqsave(hba->host->host_lock, flags); 1545 hba->clk_scaling.window_start_t = 0; 1546 spin_unlock_irqrestore(hba->host->host_lock, flags); 1547 } 1548 1549 static void ufshcd_suspend_clkscaling(struct ufs_hba *hba) 1550 { 1551 unsigned long flags; 1552 bool suspend = false; 1553 1554 cancel_work_sync(&hba->clk_scaling.suspend_work); 1555 cancel_work_sync(&hba->clk_scaling.resume_work); 1556 1557 spin_lock_irqsave(hba->host->host_lock, flags); 1558 if (!hba->clk_scaling.is_suspended) { 1559 suspend = true; 1560 hba->clk_scaling.is_suspended = true; 1561 } 1562 spin_unlock_irqrestore(hba->host->host_lock, flags); 1563 1564 if (suspend) 1565 __ufshcd_suspend_clkscaling(hba); 1566 } 1567 1568 static void ufshcd_resume_clkscaling(struct ufs_hba *hba) 1569 { 1570 unsigned long flags; 1571 bool resume = false; 1572 1573 spin_lock_irqsave(hba->host->host_lock, flags); 1574 if (hba->clk_scaling.is_suspended) { 1575 resume = true; 1576 hba->clk_scaling.is_suspended = false; 1577 } 1578 spin_unlock_irqrestore(hba->host->host_lock, flags); 1579 1580 if (resume) 1581 devfreq_resume_device(hba->devfreq); 1582 } 1583 1584 static ssize_t ufshcd_clkscale_enable_show(struct device *dev, 1585 struct device_attribute *attr, char *buf) 1586 { 1587 struct ufs_hba *hba = dev_get_drvdata(dev); 1588 1589 return sysfs_emit(buf, "%d\n", hba->clk_scaling.is_enabled); 1590 } 1591 1592 static ssize_t ufshcd_clkscale_enable_store(struct device *dev, 1593 struct device_attribute *attr, const char *buf, size_t count) 1594 { 1595 struct ufs_hba *hba = dev_get_drvdata(dev); 1596 u32 value; 1597 int err = 0; 1598 1599 if (kstrtou32(buf, 0, &value)) 1600 return -EINVAL; 1601 1602 down(&hba->host_sem); 1603 if (!ufshcd_is_user_access_allowed(hba)) { 1604 err = -EBUSY; 1605 goto out; 1606 } 1607 1608 value = !!value; 1609 if (value == hba->clk_scaling.is_enabled) 1610 goto out; 1611 1612 ufshcd_rpm_get_sync(hba); 1613 ufshcd_hold(hba); 1614 1615 hba->clk_scaling.is_enabled = value; 1616 1617 if (value) { 1618 ufshcd_resume_clkscaling(hba); 1619 } else { 1620 ufshcd_suspend_clkscaling(hba); 1621 err = ufshcd_devfreq_scale(hba, true); 1622 if (err) 1623 dev_err(hba->dev, "%s: failed to scale clocks up %d\n", 1624 __func__, err); 1625 } 1626 1627 ufshcd_release(hba); 1628 ufshcd_rpm_put_sync(hba); 1629 out: 1630 up(&hba->host_sem); 1631 return err ? err : count; 1632 } 1633 1634 static void ufshcd_init_clk_scaling_sysfs(struct ufs_hba *hba) 1635 { 1636 hba->clk_scaling.enable_attr.show = ufshcd_clkscale_enable_show; 1637 hba->clk_scaling.enable_attr.store = ufshcd_clkscale_enable_store; 1638 sysfs_attr_init(&hba->clk_scaling.enable_attr.attr); 1639 hba->clk_scaling.enable_attr.attr.name = "clkscale_enable"; 1640 hba->clk_scaling.enable_attr.attr.mode = 0644; 1641 if (device_create_file(hba->dev, &hba->clk_scaling.enable_attr)) 1642 dev_err(hba->dev, "Failed to create sysfs for clkscale_enable\n"); 1643 } 1644 1645 static void ufshcd_remove_clk_scaling_sysfs(struct ufs_hba *hba) 1646 { 1647 if (hba->clk_scaling.enable_attr.attr.name) 1648 device_remove_file(hba->dev, &hba->clk_scaling.enable_attr); 1649 } 1650 1651 static void ufshcd_init_clk_scaling(struct ufs_hba *hba) 1652 { 1653 char wq_name[sizeof("ufs_clkscaling_00")]; 1654 1655 if (!ufshcd_is_clkscaling_supported(hba)) 1656 return; 1657 1658 if (!hba->clk_scaling.min_gear) 1659 hba->clk_scaling.min_gear = UFS_HS_G1; 1660 1661 INIT_WORK(&hba->clk_scaling.suspend_work, 1662 ufshcd_clk_scaling_suspend_work); 1663 INIT_WORK(&hba->clk_scaling.resume_work, 1664 ufshcd_clk_scaling_resume_work); 1665 1666 snprintf(wq_name, sizeof(wq_name), "ufs_clkscaling_%d", 1667 hba->host->host_no); 1668 hba->clk_scaling.workq = create_singlethread_workqueue(wq_name); 1669 1670 hba->clk_scaling.is_initialized = true; 1671 } 1672 1673 static void ufshcd_exit_clk_scaling(struct ufs_hba *hba) 1674 { 1675 if (!hba->clk_scaling.is_initialized) 1676 return; 1677 1678 ufshcd_remove_clk_scaling_sysfs(hba); 1679 destroy_workqueue(hba->clk_scaling.workq); 1680 ufshcd_devfreq_remove(hba); 1681 hba->clk_scaling.is_initialized = false; 1682 } 1683 1684 static void ufshcd_ungate_work(struct work_struct *work) 1685 { 1686 int ret; 1687 unsigned long flags; 1688 struct ufs_hba *hba = container_of(work, struct ufs_hba, 1689 clk_gating.ungate_work); 1690 1691 cancel_delayed_work_sync(&hba->clk_gating.gate_work); 1692 1693 spin_lock_irqsave(hba->host->host_lock, flags); 1694 if (hba->clk_gating.state == CLKS_ON) { 1695 spin_unlock_irqrestore(hba->host->host_lock, flags); 1696 return; 1697 } 1698 1699 spin_unlock_irqrestore(hba->host->host_lock, flags); 1700 ufshcd_hba_vreg_set_hpm(hba); 1701 ufshcd_setup_clocks(hba, true); 1702 1703 ufshcd_enable_irq(hba); 1704 1705 /* Exit from hibern8 */ 1706 if (ufshcd_can_hibern8_during_gating(hba)) { 1707 /* Prevent gating in this path */ 1708 hba->clk_gating.is_suspended = true; 1709 if (ufshcd_is_link_hibern8(hba)) { 1710 ret = ufshcd_uic_hibern8_exit(hba); 1711 if (ret) 1712 dev_err(hba->dev, "%s: hibern8 exit failed %d\n", 1713 __func__, ret); 1714 else 1715 ufshcd_set_link_active(hba); 1716 } 1717 hba->clk_gating.is_suspended = false; 1718 } 1719 } 1720 1721 /** 1722 * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release. 1723 * Also, exit from hibern8 mode and set the link as active. 1724 * @hba: per adapter instance 1725 */ 1726 void ufshcd_hold(struct ufs_hba *hba) 1727 { 1728 bool flush_result; 1729 unsigned long flags; 1730 1731 if (!ufshcd_is_clkgating_allowed(hba) || 1732 !hba->clk_gating.is_initialized) 1733 return; 1734 spin_lock_irqsave(hba->host->host_lock, flags); 1735 hba->clk_gating.active_reqs++; 1736 1737 start: 1738 switch (hba->clk_gating.state) { 1739 case CLKS_ON: 1740 /* 1741 * Wait for the ungate work to complete if in progress. 1742 * Though the clocks may be in ON state, the link could 1743 * still be in hibner8 state if hibern8 is allowed 1744 * during clock gating. 1745 * Make sure we exit hibern8 state also in addition to 1746 * clocks being ON. 1747 */ 1748 if (ufshcd_can_hibern8_during_gating(hba) && 1749 ufshcd_is_link_hibern8(hba)) { 1750 spin_unlock_irqrestore(hba->host->host_lock, flags); 1751 flush_result = flush_work(&hba->clk_gating.ungate_work); 1752 if (hba->clk_gating.is_suspended && !flush_result) 1753 return; 1754 spin_lock_irqsave(hba->host->host_lock, flags); 1755 goto start; 1756 } 1757 break; 1758 case REQ_CLKS_OFF: 1759 if (cancel_delayed_work(&hba->clk_gating.gate_work)) { 1760 hba->clk_gating.state = CLKS_ON; 1761 trace_ufshcd_clk_gating(dev_name(hba->dev), 1762 hba->clk_gating.state); 1763 break; 1764 } 1765 /* 1766 * If we are here, it means gating work is either done or 1767 * currently running. Hence, fall through to cancel gating 1768 * work and to enable clocks. 1769 */ 1770 fallthrough; 1771 case CLKS_OFF: 1772 hba->clk_gating.state = REQ_CLKS_ON; 1773 trace_ufshcd_clk_gating(dev_name(hba->dev), 1774 hba->clk_gating.state); 1775 queue_work(hba->clk_gating.clk_gating_workq, 1776 &hba->clk_gating.ungate_work); 1777 /* 1778 * fall through to check if we should wait for this 1779 * work to be done or not. 1780 */ 1781 fallthrough; 1782 case REQ_CLKS_ON: 1783 spin_unlock_irqrestore(hba->host->host_lock, flags); 1784 flush_work(&hba->clk_gating.ungate_work); 1785 /* Make sure state is CLKS_ON before returning */ 1786 spin_lock_irqsave(hba->host->host_lock, flags); 1787 goto start; 1788 default: 1789 dev_err(hba->dev, "%s: clk gating is in invalid state %d\n", 1790 __func__, hba->clk_gating.state); 1791 break; 1792 } 1793 spin_unlock_irqrestore(hba->host->host_lock, flags); 1794 } 1795 EXPORT_SYMBOL_GPL(ufshcd_hold); 1796 1797 static void ufshcd_gate_work(struct work_struct *work) 1798 { 1799 struct ufs_hba *hba = container_of(work, struct ufs_hba, 1800 clk_gating.gate_work.work); 1801 unsigned long flags; 1802 int ret; 1803 1804 spin_lock_irqsave(hba->host->host_lock, flags); 1805 /* 1806 * In case you are here to cancel this work the gating state 1807 * would be marked as REQ_CLKS_ON. In this case save time by 1808 * skipping the gating work and exit after changing the clock 1809 * state to CLKS_ON. 1810 */ 1811 if (hba->clk_gating.is_suspended || 1812 (hba->clk_gating.state != REQ_CLKS_OFF)) { 1813 hba->clk_gating.state = CLKS_ON; 1814 trace_ufshcd_clk_gating(dev_name(hba->dev), 1815 hba->clk_gating.state); 1816 goto rel_lock; 1817 } 1818 1819 if (hba->clk_gating.active_reqs 1820 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL 1821 || hba->outstanding_reqs || hba->outstanding_tasks 1822 || hba->active_uic_cmd || hba->uic_async_done) 1823 goto rel_lock; 1824 1825 spin_unlock_irqrestore(hba->host->host_lock, flags); 1826 1827 /* put the link into hibern8 mode before turning off clocks */ 1828 if (ufshcd_can_hibern8_during_gating(hba)) { 1829 ret = ufshcd_uic_hibern8_enter(hba); 1830 if (ret) { 1831 hba->clk_gating.state = CLKS_ON; 1832 dev_err(hba->dev, "%s: hibern8 enter failed %d\n", 1833 __func__, ret); 1834 trace_ufshcd_clk_gating(dev_name(hba->dev), 1835 hba->clk_gating.state); 1836 goto out; 1837 } 1838 ufshcd_set_link_hibern8(hba); 1839 } 1840 1841 ufshcd_disable_irq(hba); 1842 1843 ufshcd_setup_clocks(hba, false); 1844 1845 /* Put the host controller in low power mode if possible */ 1846 ufshcd_hba_vreg_set_lpm(hba); 1847 /* 1848 * In case you are here to cancel this work the gating state 1849 * would be marked as REQ_CLKS_ON. In this case keep the state 1850 * as REQ_CLKS_ON which would anyway imply that clocks are off 1851 * and a request to turn them on is pending. By doing this way, 1852 * we keep the state machine in tact and this would ultimately 1853 * prevent from doing cancel work multiple times when there are 1854 * new requests arriving before the current cancel work is done. 1855 */ 1856 spin_lock_irqsave(hba->host->host_lock, flags); 1857 if (hba->clk_gating.state == REQ_CLKS_OFF) { 1858 hba->clk_gating.state = CLKS_OFF; 1859 trace_ufshcd_clk_gating(dev_name(hba->dev), 1860 hba->clk_gating.state); 1861 } 1862 rel_lock: 1863 spin_unlock_irqrestore(hba->host->host_lock, flags); 1864 out: 1865 return; 1866 } 1867 1868 /* host lock must be held before calling this variant */ 1869 static void __ufshcd_release(struct ufs_hba *hba) 1870 { 1871 if (!ufshcd_is_clkgating_allowed(hba)) 1872 return; 1873 1874 hba->clk_gating.active_reqs--; 1875 1876 if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended || 1877 hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL || 1878 hba->outstanding_tasks || !hba->clk_gating.is_initialized || 1879 hba->active_uic_cmd || hba->uic_async_done || 1880 hba->clk_gating.state == CLKS_OFF) 1881 return; 1882 1883 hba->clk_gating.state = REQ_CLKS_OFF; 1884 trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state); 1885 queue_delayed_work(hba->clk_gating.clk_gating_workq, 1886 &hba->clk_gating.gate_work, 1887 msecs_to_jiffies(hba->clk_gating.delay_ms)); 1888 } 1889 1890 void ufshcd_release(struct ufs_hba *hba) 1891 { 1892 unsigned long flags; 1893 1894 spin_lock_irqsave(hba->host->host_lock, flags); 1895 __ufshcd_release(hba); 1896 spin_unlock_irqrestore(hba->host->host_lock, flags); 1897 } 1898 EXPORT_SYMBOL_GPL(ufshcd_release); 1899 1900 static ssize_t ufshcd_clkgate_delay_show(struct device *dev, 1901 struct device_attribute *attr, char *buf) 1902 { 1903 struct ufs_hba *hba = dev_get_drvdata(dev); 1904 1905 return sysfs_emit(buf, "%lu\n", hba->clk_gating.delay_ms); 1906 } 1907 1908 void ufshcd_clkgate_delay_set(struct device *dev, unsigned long value) 1909 { 1910 struct ufs_hba *hba = dev_get_drvdata(dev); 1911 unsigned long flags; 1912 1913 spin_lock_irqsave(hba->host->host_lock, flags); 1914 hba->clk_gating.delay_ms = value; 1915 spin_unlock_irqrestore(hba->host->host_lock, flags); 1916 } 1917 EXPORT_SYMBOL_GPL(ufshcd_clkgate_delay_set); 1918 1919 static ssize_t ufshcd_clkgate_delay_store(struct device *dev, 1920 struct device_attribute *attr, const char *buf, size_t count) 1921 { 1922 unsigned long value; 1923 1924 if (kstrtoul(buf, 0, &value)) 1925 return -EINVAL; 1926 1927 ufshcd_clkgate_delay_set(dev, value); 1928 return count; 1929 } 1930 1931 static ssize_t ufshcd_clkgate_enable_show(struct device *dev, 1932 struct device_attribute *attr, char *buf) 1933 { 1934 struct ufs_hba *hba = dev_get_drvdata(dev); 1935 1936 return sysfs_emit(buf, "%d\n", hba->clk_gating.is_enabled); 1937 } 1938 1939 static ssize_t ufshcd_clkgate_enable_store(struct device *dev, 1940 struct device_attribute *attr, const char *buf, size_t count) 1941 { 1942 struct ufs_hba *hba = dev_get_drvdata(dev); 1943 unsigned long flags; 1944 u32 value; 1945 1946 if (kstrtou32(buf, 0, &value)) 1947 return -EINVAL; 1948 1949 value = !!value; 1950 1951 spin_lock_irqsave(hba->host->host_lock, flags); 1952 if (value == hba->clk_gating.is_enabled) 1953 goto out; 1954 1955 if (value) 1956 __ufshcd_release(hba); 1957 else 1958 hba->clk_gating.active_reqs++; 1959 1960 hba->clk_gating.is_enabled = value; 1961 out: 1962 spin_unlock_irqrestore(hba->host->host_lock, flags); 1963 return count; 1964 } 1965 1966 static void ufshcd_init_clk_gating_sysfs(struct ufs_hba *hba) 1967 { 1968 hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show; 1969 hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store; 1970 sysfs_attr_init(&hba->clk_gating.delay_attr.attr); 1971 hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms"; 1972 hba->clk_gating.delay_attr.attr.mode = 0644; 1973 if (device_create_file(hba->dev, &hba->clk_gating.delay_attr)) 1974 dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n"); 1975 1976 hba->clk_gating.enable_attr.show = ufshcd_clkgate_enable_show; 1977 hba->clk_gating.enable_attr.store = ufshcd_clkgate_enable_store; 1978 sysfs_attr_init(&hba->clk_gating.enable_attr.attr); 1979 hba->clk_gating.enable_attr.attr.name = "clkgate_enable"; 1980 hba->clk_gating.enable_attr.attr.mode = 0644; 1981 if (device_create_file(hba->dev, &hba->clk_gating.enable_attr)) 1982 dev_err(hba->dev, "Failed to create sysfs for clkgate_enable\n"); 1983 } 1984 1985 static void ufshcd_remove_clk_gating_sysfs(struct ufs_hba *hba) 1986 { 1987 if (hba->clk_gating.delay_attr.attr.name) 1988 device_remove_file(hba->dev, &hba->clk_gating.delay_attr); 1989 if (hba->clk_gating.enable_attr.attr.name) 1990 device_remove_file(hba->dev, &hba->clk_gating.enable_attr); 1991 } 1992 1993 static void ufshcd_init_clk_gating(struct ufs_hba *hba) 1994 { 1995 char wq_name[sizeof("ufs_clk_gating_00")]; 1996 1997 if (!ufshcd_is_clkgating_allowed(hba)) 1998 return; 1999 2000 hba->clk_gating.state = CLKS_ON; 2001 2002 hba->clk_gating.delay_ms = 150; 2003 INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work); 2004 INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work); 2005 2006 snprintf(wq_name, ARRAY_SIZE(wq_name), "ufs_clk_gating_%d", 2007 hba->host->host_no); 2008 hba->clk_gating.clk_gating_workq = alloc_ordered_workqueue(wq_name, 2009 WQ_MEM_RECLAIM | WQ_HIGHPRI); 2010 2011 ufshcd_init_clk_gating_sysfs(hba); 2012 2013 hba->clk_gating.is_enabled = true; 2014 hba->clk_gating.is_initialized = true; 2015 } 2016 2017 static void ufshcd_exit_clk_gating(struct ufs_hba *hba) 2018 { 2019 if (!hba->clk_gating.is_initialized) 2020 return; 2021 2022 ufshcd_remove_clk_gating_sysfs(hba); 2023 2024 /* Ungate the clock if necessary. */ 2025 ufshcd_hold(hba); 2026 hba->clk_gating.is_initialized = false; 2027 ufshcd_release(hba); 2028 2029 destroy_workqueue(hba->clk_gating.clk_gating_workq); 2030 } 2031 2032 static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba) 2033 { 2034 bool queue_resume_work = false; 2035 ktime_t curr_t = ktime_get(); 2036 unsigned long flags; 2037 2038 if (!ufshcd_is_clkscaling_supported(hba)) 2039 return; 2040 2041 spin_lock_irqsave(hba->host->host_lock, flags); 2042 if (!hba->clk_scaling.active_reqs++) 2043 queue_resume_work = true; 2044 2045 if (!hba->clk_scaling.is_enabled || hba->pm_op_in_progress) { 2046 spin_unlock_irqrestore(hba->host->host_lock, flags); 2047 return; 2048 } 2049 2050 if (queue_resume_work) 2051 queue_work(hba->clk_scaling.workq, 2052 &hba->clk_scaling.resume_work); 2053 2054 if (!hba->clk_scaling.window_start_t) { 2055 hba->clk_scaling.window_start_t = curr_t; 2056 hba->clk_scaling.tot_busy_t = 0; 2057 hba->clk_scaling.is_busy_started = false; 2058 } 2059 2060 if (!hba->clk_scaling.is_busy_started) { 2061 hba->clk_scaling.busy_start_t = curr_t; 2062 hba->clk_scaling.is_busy_started = true; 2063 } 2064 spin_unlock_irqrestore(hba->host->host_lock, flags); 2065 } 2066 2067 static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba) 2068 { 2069 struct ufs_clk_scaling *scaling = &hba->clk_scaling; 2070 unsigned long flags; 2071 2072 if (!ufshcd_is_clkscaling_supported(hba)) 2073 return; 2074 2075 spin_lock_irqsave(hba->host->host_lock, flags); 2076 hba->clk_scaling.active_reqs--; 2077 if (!scaling->active_reqs && scaling->is_busy_started) { 2078 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(), 2079 scaling->busy_start_t)); 2080 scaling->busy_start_t = 0; 2081 scaling->is_busy_started = false; 2082 } 2083 spin_unlock_irqrestore(hba->host->host_lock, flags); 2084 } 2085 2086 static inline int ufshcd_monitor_opcode2dir(u8 opcode) 2087 { 2088 if (opcode == READ_6 || opcode == READ_10 || opcode == READ_16) 2089 return READ; 2090 else if (opcode == WRITE_6 || opcode == WRITE_10 || opcode == WRITE_16) 2091 return WRITE; 2092 else 2093 return -EINVAL; 2094 } 2095 2096 static inline bool ufshcd_should_inform_monitor(struct ufs_hba *hba, 2097 struct ufshcd_lrb *lrbp) 2098 { 2099 const struct ufs_hba_monitor *m = &hba->monitor; 2100 2101 return (m->enabled && lrbp && lrbp->cmd && 2102 (!m->chunk_size || m->chunk_size == lrbp->cmd->sdb.length) && 2103 ktime_before(hba->monitor.enabled_ts, lrbp->issue_time_stamp)); 2104 } 2105 2106 static void ufshcd_start_monitor(struct ufs_hba *hba, 2107 const struct ufshcd_lrb *lrbp) 2108 { 2109 int dir = ufshcd_monitor_opcode2dir(*lrbp->cmd->cmnd); 2110 unsigned long flags; 2111 2112 spin_lock_irqsave(hba->host->host_lock, flags); 2113 if (dir >= 0 && hba->monitor.nr_queued[dir]++ == 0) 2114 hba->monitor.busy_start_ts[dir] = ktime_get(); 2115 spin_unlock_irqrestore(hba->host->host_lock, flags); 2116 } 2117 2118 static void ufshcd_update_monitor(struct ufs_hba *hba, const struct ufshcd_lrb *lrbp) 2119 { 2120 int dir = ufshcd_monitor_opcode2dir(*lrbp->cmd->cmnd); 2121 unsigned long flags; 2122 2123 spin_lock_irqsave(hba->host->host_lock, flags); 2124 if (dir >= 0 && hba->monitor.nr_queued[dir] > 0) { 2125 const struct request *req = scsi_cmd_to_rq(lrbp->cmd); 2126 struct ufs_hba_monitor *m = &hba->monitor; 2127 ktime_t now, inc, lat; 2128 2129 now = lrbp->compl_time_stamp; 2130 inc = ktime_sub(now, m->busy_start_ts[dir]); 2131 m->total_busy[dir] = ktime_add(m->total_busy[dir], inc); 2132 m->nr_sec_rw[dir] += blk_rq_sectors(req); 2133 2134 /* Update latencies */ 2135 m->nr_req[dir]++; 2136 lat = ktime_sub(now, lrbp->issue_time_stamp); 2137 m->lat_sum[dir] += lat; 2138 if (m->lat_max[dir] < lat || !m->lat_max[dir]) 2139 m->lat_max[dir] = lat; 2140 if (m->lat_min[dir] > lat || !m->lat_min[dir]) 2141 m->lat_min[dir] = lat; 2142 2143 m->nr_queued[dir]--; 2144 /* Push forward the busy start of monitor */ 2145 m->busy_start_ts[dir] = now; 2146 } 2147 spin_unlock_irqrestore(hba->host->host_lock, flags); 2148 } 2149 2150 /** 2151 * ufshcd_send_command - Send SCSI or device management commands 2152 * @hba: per adapter instance 2153 * @task_tag: Task tag of the command 2154 * @hwq: pointer to hardware queue instance 2155 */ 2156 static inline 2157 void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag, 2158 struct ufs_hw_queue *hwq) 2159 { 2160 struct ufshcd_lrb *lrbp = &hba->lrb[task_tag]; 2161 unsigned long flags; 2162 2163 lrbp->issue_time_stamp = ktime_get(); 2164 lrbp->issue_time_stamp_local_clock = local_clock(); 2165 lrbp->compl_time_stamp = ktime_set(0, 0); 2166 lrbp->compl_time_stamp_local_clock = 0; 2167 ufshcd_add_command_trace(hba, task_tag, UFS_CMD_SEND); 2168 ufshcd_clk_scaling_start_busy(hba); 2169 if (unlikely(ufshcd_should_inform_monitor(hba, lrbp))) 2170 ufshcd_start_monitor(hba, lrbp); 2171 2172 if (is_mcq_enabled(hba)) { 2173 int utrd_size = sizeof(struct utp_transfer_req_desc); 2174 struct utp_transfer_req_desc *src = lrbp->utr_descriptor_ptr; 2175 struct utp_transfer_req_desc *dest; 2176 2177 spin_lock(&hwq->sq_lock); 2178 dest = hwq->sqe_base_addr + hwq->sq_tail_slot; 2179 memcpy(dest, src, utrd_size); 2180 ufshcd_inc_sq_tail(hwq); 2181 spin_unlock(&hwq->sq_lock); 2182 } else { 2183 spin_lock_irqsave(&hba->outstanding_lock, flags); 2184 if (hba->vops && hba->vops->setup_xfer_req) 2185 hba->vops->setup_xfer_req(hba, lrbp->task_tag, 2186 !!lrbp->cmd); 2187 __set_bit(lrbp->task_tag, &hba->outstanding_reqs); 2188 ufshcd_writel(hba, 1 << lrbp->task_tag, 2189 REG_UTP_TRANSFER_REQ_DOOR_BELL); 2190 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 2191 } 2192 } 2193 2194 /** 2195 * ufshcd_copy_sense_data - Copy sense data in case of check condition 2196 * @lrbp: pointer to local reference block 2197 */ 2198 static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp) 2199 { 2200 u8 *const sense_buffer = lrbp->cmd->sense_buffer; 2201 u16 resp_len; 2202 int len; 2203 2204 resp_len = be16_to_cpu(lrbp->ucd_rsp_ptr->header.data_segment_length); 2205 if (sense_buffer && resp_len) { 2206 int len_to_copy; 2207 2208 len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len); 2209 len_to_copy = min_t(int, UFS_SENSE_SIZE, len); 2210 2211 memcpy(sense_buffer, lrbp->ucd_rsp_ptr->sr.sense_data, 2212 len_to_copy); 2213 } 2214 } 2215 2216 /** 2217 * ufshcd_copy_query_response() - Copy the Query Response and the data 2218 * descriptor 2219 * @hba: per adapter instance 2220 * @lrbp: pointer to local reference block 2221 * 2222 * Return: 0 upon success; < 0 upon failure. 2223 */ 2224 static 2225 int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) 2226 { 2227 struct ufs_query_res *query_res = &hba->dev_cmd.query.response; 2228 2229 memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE); 2230 2231 /* Get the descriptor */ 2232 if (hba->dev_cmd.query.descriptor && 2233 lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) { 2234 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr + 2235 GENERAL_UPIU_REQUEST_SIZE; 2236 u16 resp_len; 2237 u16 buf_len; 2238 2239 /* data segment length */ 2240 resp_len = be16_to_cpu(lrbp->ucd_rsp_ptr->header 2241 .data_segment_length); 2242 buf_len = be16_to_cpu( 2243 hba->dev_cmd.query.request.upiu_req.length); 2244 if (likely(buf_len >= resp_len)) { 2245 memcpy(hba->dev_cmd.query.descriptor, descp, resp_len); 2246 } else { 2247 dev_warn(hba->dev, 2248 "%s: rsp size %d is bigger than buffer size %d", 2249 __func__, resp_len, buf_len); 2250 return -EINVAL; 2251 } 2252 } 2253 2254 return 0; 2255 } 2256 2257 /** 2258 * ufshcd_hba_capabilities - Read controller capabilities 2259 * @hba: per adapter instance 2260 * 2261 * Return: 0 on success, negative on error. 2262 */ 2263 static inline int ufshcd_hba_capabilities(struct ufs_hba *hba) 2264 { 2265 int err; 2266 2267 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES); 2268 if (hba->quirks & UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS) 2269 hba->capabilities &= ~MASK_64_ADDRESSING_SUPPORT; 2270 2271 /* nutrs and nutmrs are 0 based values */ 2272 hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1; 2273 hba->nutmrs = 2274 ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1; 2275 hba->reserved_slot = hba->nutrs - 1; 2276 2277 /* Read crypto capabilities */ 2278 err = ufshcd_hba_init_crypto_capabilities(hba); 2279 if (err) { 2280 dev_err(hba->dev, "crypto setup failed\n"); 2281 return err; 2282 } 2283 2284 hba->mcq_sup = FIELD_GET(MASK_MCQ_SUPPORT, hba->capabilities); 2285 if (!hba->mcq_sup) 2286 return 0; 2287 2288 hba->mcq_capabilities = ufshcd_readl(hba, REG_MCQCAP); 2289 hba->ext_iid_sup = FIELD_GET(MASK_EXT_IID_SUPPORT, 2290 hba->mcq_capabilities); 2291 2292 return 0; 2293 } 2294 2295 /** 2296 * ufshcd_ready_for_uic_cmd - Check if controller is ready 2297 * to accept UIC commands 2298 * @hba: per adapter instance 2299 * 2300 * Return: true on success, else false. 2301 */ 2302 static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba) 2303 { 2304 u32 val; 2305 int ret = read_poll_timeout(ufshcd_readl, val, val & UIC_COMMAND_READY, 2306 500, UIC_CMD_TIMEOUT * 1000, false, hba, 2307 REG_CONTROLLER_STATUS); 2308 return ret == 0 ? true : false; 2309 } 2310 2311 /** 2312 * ufshcd_get_upmcrs - Get the power mode change request status 2313 * @hba: Pointer to adapter instance 2314 * 2315 * This function gets the UPMCRS field of HCS register 2316 * 2317 * Return: value of UPMCRS field. 2318 */ 2319 static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba) 2320 { 2321 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7; 2322 } 2323 2324 /** 2325 * ufshcd_dispatch_uic_cmd - Dispatch an UIC command to the Unipro layer 2326 * @hba: per adapter instance 2327 * @uic_cmd: UIC command 2328 */ 2329 static inline void 2330 ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) 2331 { 2332 lockdep_assert_held(&hba->uic_cmd_mutex); 2333 2334 WARN_ON(hba->active_uic_cmd); 2335 2336 hba->active_uic_cmd = uic_cmd; 2337 2338 /* Write Args */ 2339 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1); 2340 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2); 2341 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3); 2342 2343 ufshcd_add_uic_command_trace(hba, uic_cmd, UFS_CMD_SEND); 2344 2345 /* Write UIC Cmd */ 2346 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK, 2347 REG_UIC_COMMAND); 2348 } 2349 2350 /** 2351 * ufshcd_wait_for_uic_cmd - Wait for completion of an UIC command 2352 * @hba: per adapter instance 2353 * @uic_cmd: UIC command 2354 * 2355 * Return: 0 only if success. 2356 */ 2357 static int 2358 ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) 2359 { 2360 int ret; 2361 unsigned long flags; 2362 2363 lockdep_assert_held(&hba->uic_cmd_mutex); 2364 2365 if (wait_for_completion_timeout(&uic_cmd->done, 2366 msecs_to_jiffies(UIC_CMD_TIMEOUT))) { 2367 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT; 2368 } else { 2369 ret = -ETIMEDOUT; 2370 dev_err(hba->dev, 2371 "uic cmd 0x%x with arg3 0x%x completion timeout\n", 2372 uic_cmd->command, uic_cmd->argument3); 2373 2374 if (!uic_cmd->cmd_active) { 2375 dev_err(hba->dev, "%s: UIC cmd has been completed, return the result\n", 2376 __func__); 2377 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT; 2378 } 2379 } 2380 2381 spin_lock_irqsave(hba->host->host_lock, flags); 2382 hba->active_uic_cmd = NULL; 2383 spin_unlock_irqrestore(hba->host->host_lock, flags); 2384 2385 return ret; 2386 } 2387 2388 /** 2389 * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result 2390 * @hba: per adapter instance 2391 * @uic_cmd: UIC command 2392 * @completion: initialize the completion only if this is set to true 2393 * 2394 * Return: 0 only if success. 2395 */ 2396 static int 2397 __ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd, 2398 bool completion) 2399 { 2400 lockdep_assert_held(&hba->uic_cmd_mutex); 2401 2402 if (!ufshcd_ready_for_uic_cmd(hba)) { 2403 dev_err(hba->dev, 2404 "Controller not ready to accept UIC commands\n"); 2405 return -EIO; 2406 } 2407 2408 if (completion) 2409 init_completion(&uic_cmd->done); 2410 2411 uic_cmd->cmd_active = 1; 2412 ufshcd_dispatch_uic_cmd(hba, uic_cmd); 2413 2414 return 0; 2415 } 2416 2417 /** 2418 * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result 2419 * @hba: per adapter instance 2420 * @uic_cmd: UIC command 2421 * 2422 * Return: 0 only if success. 2423 */ 2424 int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) 2425 { 2426 int ret; 2427 2428 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UIC_CMD) 2429 return 0; 2430 2431 ufshcd_hold(hba); 2432 mutex_lock(&hba->uic_cmd_mutex); 2433 ufshcd_add_delay_before_dme_cmd(hba); 2434 2435 ret = __ufshcd_send_uic_cmd(hba, uic_cmd, true); 2436 if (!ret) 2437 ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd); 2438 2439 mutex_unlock(&hba->uic_cmd_mutex); 2440 2441 ufshcd_release(hba); 2442 return ret; 2443 } 2444 2445 /** 2446 * ufshcd_sgl_to_prdt - SG list to PRTD (Physical Region Description Table, 4DW format) 2447 * @hba: per-adapter instance 2448 * @lrbp: pointer to local reference block 2449 * @sg_entries: The number of sg lists actually used 2450 * @sg_list: Pointer to SG list 2451 */ 2452 static void ufshcd_sgl_to_prdt(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, int sg_entries, 2453 struct scatterlist *sg_list) 2454 { 2455 struct ufshcd_sg_entry *prd; 2456 struct scatterlist *sg; 2457 int i; 2458 2459 if (sg_entries) { 2460 2461 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) 2462 lrbp->utr_descriptor_ptr->prd_table_length = 2463 cpu_to_le16(sg_entries * ufshcd_sg_entry_size(hba)); 2464 else 2465 lrbp->utr_descriptor_ptr->prd_table_length = cpu_to_le16(sg_entries); 2466 2467 prd = lrbp->ucd_prdt_ptr; 2468 2469 for_each_sg(sg_list, sg, sg_entries, i) { 2470 const unsigned int len = sg_dma_len(sg); 2471 2472 /* 2473 * From the UFSHCI spec: "Data Byte Count (DBC): A '0' 2474 * based value that indicates the length, in bytes, of 2475 * the data block. A maximum of length of 256KB may 2476 * exist for any entry. Bits 1:0 of this field shall be 2477 * 11b to indicate Dword granularity. A value of '3' 2478 * indicates 4 bytes, '7' indicates 8 bytes, etc." 2479 */ 2480 WARN_ONCE(len > SZ_256K, "len = %#x\n", len); 2481 prd->size = cpu_to_le32(len - 1); 2482 prd->addr = cpu_to_le64(sg->dma_address); 2483 prd->reserved = 0; 2484 prd = (void *)prd + ufshcd_sg_entry_size(hba); 2485 } 2486 } else { 2487 lrbp->utr_descriptor_ptr->prd_table_length = 0; 2488 } 2489 } 2490 2491 /** 2492 * ufshcd_map_sg - Map scatter-gather list to prdt 2493 * @hba: per adapter instance 2494 * @lrbp: pointer to local reference block 2495 * 2496 * Return: 0 in case of success, non-zero value in case of failure. 2497 */ 2498 static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) 2499 { 2500 struct scsi_cmnd *cmd = lrbp->cmd; 2501 int sg_segments = scsi_dma_map(cmd); 2502 2503 if (sg_segments < 0) 2504 return sg_segments; 2505 2506 ufshcd_sgl_to_prdt(hba, lrbp, sg_segments, scsi_sglist(cmd)); 2507 2508 return 0; 2509 } 2510 2511 /** 2512 * ufshcd_enable_intr - enable interrupts 2513 * @hba: per adapter instance 2514 * @intrs: interrupt bits 2515 */ 2516 static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs) 2517 { 2518 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 2519 2520 if (hba->ufs_version == ufshci_version(1, 0)) { 2521 u32 rw; 2522 rw = set & INTERRUPT_MASK_RW_VER_10; 2523 set = rw | ((set ^ intrs) & intrs); 2524 } else { 2525 set |= intrs; 2526 } 2527 2528 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE); 2529 } 2530 2531 /** 2532 * ufshcd_disable_intr - disable interrupts 2533 * @hba: per adapter instance 2534 * @intrs: interrupt bits 2535 */ 2536 static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs) 2537 { 2538 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 2539 2540 if (hba->ufs_version == ufshci_version(1, 0)) { 2541 u32 rw; 2542 rw = (set & INTERRUPT_MASK_RW_VER_10) & 2543 ~(intrs & INTERRUPT_MASK_RW_VER_10); 2544 set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10); 2545 2546 } else { 2547 set &= ~intrs; 2548 } 2549 2550 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE); 2551 } 2552 2553 /** 2554 * ufshcd_prepare_req_desc_hdr - Fill UTP Transfer request descriptor header according to request 2555 * descriptor according to request 2556 * @lrbp: pointer to local reference block 2557 * @upiu_flags: flags required in the header 2558 * @cmd_dir: requests data direction 2559 * @ehs_length: Total EHS Length (in 32‐bytes units of all Extra Header Segments) 2560 */ 2561 static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp, u8 *upiu_flags, 2562 enum dma_data_direction cmd_dir, int ehs_length) 2563 { 2564 struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr; 2565 struct request_desc_header *h = &req_desc->header; 2566 enum utp_data_direction data_direction; 2567 2568 *h = (typeof(*h)){ }; 2569 2570 if (cmd_dir == DMA_FROM_DEVICE) { 2571 data_direction = UTP_DEVICE_TO_HOST; 2572 *upiu_flags = UPIU_CMD_FLAGS_READ; 2573 } else if (cmd_dir == DMA_TO_DEVICE) { 2574 data_direction = UTP_HOST_TO_DEVICE; 2575 *upiu_flags = UPIU_CMD_FLAGS_WRITE; 2576 } else { 2577 data_direction = UTP_NO_DATA_TRANSFER; 2578 *upiu_flags = UPIU_CMD_FLAGS_NONE; 2579 } 2580 2581 h->command_type = lrbp->command_type; 2582 h->data_direction = data_direction; 2583 h->ehs_length = ehs_length; 2584 2585 if (lrbp->intr_cmd) 2586 h->interrupt = 1; 2587 2588 /* Prepare crypto related dwords */ 2589 ufshcd_prepare_req_desc_hdr_crypto(lrbp, h); 2590 2591 /* 2592 * assigning invalid value for command status. Controller 2593 * updates OCS on command completion, with the command 2594 * status 2595 */ 2596 h->ocs = OCS_INVALID_COMMAND_STATUS; 2597 2598 req_desc->prd_table_length = 0; 2599 } 2600 2601 /** 2602 * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc, 2603 * for scsi commands 2604 * @lrbp: local reference block pointer 2605 * @upiu_flags: flags 2606 */ 2607 static 2608 void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u8 upiu_flags) 2609 { 2610 struct scsi_cmnd *cmd = lrbp->cmd; 2611 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr; 2612 unsigned short cdb_len; 2613 2614 ucd_req_ptr->header = (struct utp_upiu_header){ 2615 .transaction_code = UPIU_TRANSACTION_COMMAND, 2616 .flags = upiu_flags, 2617 .lun = lrbp->lun, 2618 .task_tag = lrbp->task_tag, 2619 .command_set_type = UPIU_COMMAND_SET_TYPE_SCSI, 2620 }; 2621 2622 ucd_req_ptr->sc.exp_data_transfer_len = cpu_to_be32(cmd->sdb.length); 2623 2624 cdb_len = min_t(unsigned short, cmd->cmd_len, UFS_CDB_SIZE); 2625 memset(ucd_req_ptr->sc.cdb, 0, UFS_CDB_SIZE); 2626 memcpy(ucd_req_ptr->sc.cdb, cmd->cmnd, cdb_len); 2627 2628 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 2629 } 2630 2631 /** 2632 * ufshcd_prepare_utp_query_req_upiu() - fill the utp_transfer_req_desc for query request 2633 * @hba: UFS hba 2634 * @lrbp: local reference block pointer 2635 * @upiu_flags: flags 2636 */ 2637 static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba, 2638 struct ufshcd_lrb *lrbp, u8 upiu_flags) 2639 { 2640 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr; 2641 struct ufs_query *query = &hba->dev_cmd.query; 2642 u16 len = be16_to_cpu(query->request.upiu_req.length); 2643 2644 /* Query request header */ 2645 ucd_req_ptr->header = (struct utp_upiu_header){ 2646 .transaction_code = UPIU_TRANSACTION_QUERY_REQ, 2647 .flags = upiu_flags, 2648 .lun = lrbp->lun, 2649 .task_tag = lrbp->task_tag, 2650 .query_function = query->request.query_func, 2651 /* Data segment length only need for WRITE_DESC */ 2652 .data_segment_length = 2653 query->request.upiu_req.opcode == 2654 UPIU_QUERY_OPCODE_WRITE_DESC ? 2655 cpu_to_be16(len) : 2656 0, 2657 }; 2658 2659 /* Copy the Query Request buffer as is */ 2660 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req, 2661 QUERY_OSF_SIZE); 2662 2663 /* Copy the Descriptor */ 2664 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC) 2665 memcpy(ucd_req_ptr + 1, query->descriptor, len); 2666 2667 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 2668 } 2669 2670 static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp) 2671 { 2672 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr; 2673 2674 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req)); 2675 2676 ucd_req_ptr->header = (struct utp_upiu_header){ 2677 .transaction_code = UPIU_TRANSACTION_NOP_OUT, 2678 .task_tag = lrbp->task_tag, 2679 }; 2680 2681 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 2682 } 2683 2684 /** 2685 * ufshcd_compose_devman_upiu - UFS Protocol Information Unit(UPIU) 2686 * for Device Management Purposes 2687 * @hba: per adapter instance 2688 * @lrbp: pointer to local reference block 2689 * 2690 * Return: 0 upon success; < 0 upon failure. 2691 */ 2692 static int ufshcd_compose_devman_upiu(struct ufs_hba *hba, 2693 struct ufshcd_lrb *lrbp) 2694 { 2695 u8 upiu_flags; 2696 int ret = 0; 2697 2698 if (hba->ufs_version <= ufshci_version(1, 1)) 2699 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE; 2700 else 2701 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE; 2702 2703 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE, 0); 2704 if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY) 2705 ufshcd_prepare_utp_query_req_upiu(hba, lrbp, upiu_flags); 2706 else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP) 2707 ufshcd_prepare_utp_nop_upiu(lrbp); 2708 else 2709 ret = -EINVAL; 2710 2711 return ret; 2712 } 2713 2714 /** 2715 * ufshcd_comp_scsi_upiu - UFS Protocol Information Unit(UPIU) 2716 * for SCSI Purposes 2717 * @hba: per adapter instance 2718 * @lrbp: pointer to local reference block 2719 * 2720 * Return: 0 upon success; < 0 upon failure. 2721 */ 2722 static int ufshcd_comp_scsi_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) 2723 { 2724 u8 upiu_flags; 2725 int ret = 0; 2726 2727 if (hba->ufs_version <= ufshci_version(1, 1)) 2728 lrbp->command_type = UTP_CMD_TYPE_SCSI; 2729 else 2730 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE; 2731 2732 if (likely(lrbp->cmd)) { 2733 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, lrbp->cmd->sc_data_direction, 0); 2734 ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags); 2735 } else { 2736 ret = -EINVAL; 2737 } 2738 2739 return ret; 2740 } 2741 2742 /** 2743 * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID 2744 * @upiu_wlun_id: UPIU W-LUN id 2745 * 2746 * Return: SCSI W-LUN id. 2747 */ 2748 static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id) 2749 { 2750 return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE; 2751 } 2752 2753 static inline bool is_device_wlun(struct scsi_device *sdev) 2754 { 2755 return sdev->lun == 2756 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN); 2757 } 2758 2759 /* 2760 * Associate the UFS controller queue with the default and poll HCTX types. 2761 * Initialize the mq_map[] arrays. 2762 */ 2763 static void ufshcd_map_queues(struct Scsi_Host *shost) 2764 { 2765 struct ufs_hba *hba = shost_priv(shost); 2766 int i, queue_offset = 0; 2767 2768 if (!is_mcq_supported(hba)) { 2769 hba->nr_queues[HCTX_TYPE_DEFAULT] = 1; 2770 hba->nr_queues[HCTX_TYPE_READ] = 0; 2771 hba->nr_queues[HCTX_TYPE_POLL] = 1; 2772 hba->nr_hw_queues = 1; 2773 } 2774 2775 for (i = 0; i < shost->nr_maps; i++) { 2776 struct blk_mq_queue_map *map = &shost->tag_set.map[i]; 2777 2778 map->nr_queues = hba->nr_queues[i]; 2779 if (!map->nr_queues) 2780 continue; 2781 map->queue_offset = queue_offset; 2782 if (i == HCTX_TYPE_POLL && !is_mcq_supported(hba)) 2783 map->queue_offset = 0; 2784 2785 blk_mq_map_queues(map); 2786 queue_offset += map->nr_queues; 2787 } 2788 } 2789 2790 static void ufshcd_init_lrb(struct ufs_hba *hba, struct ufshcd_lrb *lrb, int i) 2791 { 2792 struct utp_transfer_cmd_desc *cmd_descp = (void *)hba->ucdl_base_addr + 2793 i * ufshcd_get_ucd_size(hba); 2794 struct utp_transfer_req_desc *utrdlp = hba->utrdl_base_addr; 2795 dma_addr_t cmd_desc_element_addr = hba->ucdl_dma_addr + 2796 i * ufshcd_get_ucd_size(hba); 2797 u16 response_offset = offsetof(struct utp_transfer_cmd_desc, 2798 response_upiu); 2799 u16 prdt_offset = offsetof(struct utp_transfer_cmd_desc, prd_table); 2800 2801 lrb->utr_descriptor_ptr = utrdlp + i; 2802 lrb->utrd_dma_addr = hba->utrdl_dma_addr + 2803 i * sizeof(struct utp_transfer_req_desc); 2804 lrb->ucd_req_ptr = (struct utp_upiu_req *)cmd_descp->command_upiu; 2805 lrb->ucd_req_dma_addr = cmd_desc_element_addr; 2806 lrb->ucd_rsp_ptr = (struct utp_upiu_rsp *)cmd_descp->response_upiu; 2807 lrb->ucd_rsp_dma_addr = cmd_desc_element_addr + response_offset; 2808 lrb->ucd_prdt_ptr = (struct ufshcd_sg_entry *)cmd_descp->prd_table; 2809 lrb->ucd_prdt_dma_addr = cmd_desc_element_addr + prdt_offset; 2810 } 2811 2812 /** 2813 * ufshcd_queuecommand - main entry point for SCSI requests 2814 * @host: SCSI host pointer 2815 * @cmd: command from SCSI Midlayer 2816 * 2817 * Return: 0 for success, non-zero in case of failure. 2818 */ 2819 static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) 2820 { 2821 struct ufs_hba *hba = shost_priv(host); 2822 int tag = scsi_cmd_to_rq(cmd)->tag; 2823 struct ufshcd_lrb *lrbp; 2824 int err = 0; 2825 struct ufs_hw_queue *hwq = NULL; 2826 2827 WARN_ONCE(tag < 0 || tag >= hba->nutrs, "Invalid tag %d\n", tag); 2828 2829 switch (hba->ufshcd_state) { 2830 case UFSHCD_STATE_OPERATIONAL: 2831 break; 2832 case UFSHCD_STATE_EH_SCHEDULED_NON_FATAL: 2833 /* 2834 * SCSI error handler can call ->queuecommand() while UFS error 2835 * handler is in progress. Error interrupts could change the 2836 * state from UFSHCD_STATE_RESET to 2837 * UFSHCD_STATE_EH_SCHEDULED_NON_FATAL. Prevent requests 2838 * being issued in that case. 2839 */ 2840 if (ufshcd_eh_in_progress(hba)) { 2841 err = SCSI_MLQUEUE_HOST_BUSY; 2842 goto out; 2843 } 2844 break; 2845 case UFSHCD_STATE_EH_SCHEDULED_FATAL: 2846 /* 2847 * pm_runtime_get_sync() is used at error handling preparation 2848 * stage. If a scsi cmd, e.g. the SSU cmd, is sent from hba's 2849 * PM ops, it can never be finished if we let SCSI layer keep 2850 * retrying it, which gets err handler stuck forever. Neither 2851 * can we let the scsi cmd pass through, because UFS is in bad 2852 * state, the scsi cmd may eventually time out, which will get 2853 * err handler blocked for too long. So, just fail the scsi cmd 2854 * sent from PM ops, err handler can recover PM error anyways. 2855 */ 2856 if (hba->pm_op_in_progress) { 2857 hba->force_reset = true; 2858 set_host_byte(cmd, DID_BAD_TARGET); 2859 scsi_done(cmd); 2860 goto out; 2861 } 2862 fallthrough; 2863 case UFSHCD_STATE_RESET: 2864 err = SCSI_MLQUEUE_HOST_BUSY; 2865 goto out; 2866 case UFSHCD_STATE_ERROR: 2867 set_host_byte(cmd, DID_ERROR); 2868 scsi_done(cmd); 2869 goto out; 2870 } 2871 2872 hba->req_abort_count = 0; 2873 2874 ufshcd_hold(hba); 2875 2876 lrbp = &hba->lrb[tag]; 2877 lrbp->cmd = cmd; 2878 lrbp->task_tag = tag; 2879 lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun); 2880 lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba); 2881 2882 ufshcd_prepare_lrbp_crypto(scsi_cmd_to_rq(cmd), lrbp); 2883 2884 lrbp->req_abort_skip = false; 2885 2886 ufshcd_comp_scsi_upiu(hba, lrbp); 2887 2888 err = ufshcd_map_sg(hba, lrbp); 2889 if (err) { 2890 ufshcd_release(hba); 2891 goto out; 2892 } 2893 2894 if (is_mcq_enabled(hba)) 2895 hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(cmd)); 2896 2897 ufshcd_send_command(hba, tag, hwq); 2898 2899 out: 2900 if (ufs_trigger_eh()) { 2901 unsigned long flags; 2902 2903 spin_lock_irqsave(hba->host->host_lock, flags); 2904 ufshcd_schedule_eh_work(hba); 2905 spin_unlock_irqrestore(hba->host->host_lock, flags); 2906 } 2907 2908 return err; 2909 } 2910 2911 static int ufshcd_compose_dev_cmd(struct ufs_hba *hba, 2912 struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag) 2913 { 2914 lrbp->cmd = NULL; 2915 lrbp->task_tag = tag; 2916 lrbp->lun = 0; /* device management cmd is not specific to any LUN */ 2917 lrbp->intr_cmd = true; /* No interrupt aggregation */ 2918 ufshcd_prepare_lrbp_crypto(NULL, lrbp); 2919 hba->dev_cmd.type = cmd_type; 2920 2921 return ufshcd_compose_devman_upiu(hba, lrbp); 2922 } 2923 2924 /* 2925 * Check with the block layer if the command is inflight 2926 * @cmd: command to check. 2927 * 2928 * Return: true if command is inflight; false if not. 2929 */ 2930 bool ufshcd_cmd_inflight(struct scsi_cmnd *cmd) 2931 { 2932 struct request *rq; 2933 2934 if (!cmd) 2935 return false; 2936 2937 rq = scsi_cmd_to_rq(cmd); 2938 if (!blk_mq_request_started(rq)) 2939 return false; 2940 2941 return true; 2942 } 2943 2944 /* 2945 * Clear the pending command in the controller and wait until 2946 * the controller confirms that the command has been cleared. 2947 * @hba: per adapter instance 2948 * @task_tag: The tag number of the command to be cleared. 2949 */ 2950 static int ufshcd_clear_cmd(struct ufs_hba *hba, u32 task_tag) 2951 { 2952 u32 mask = 1U << task_tag; 2953 unsigned long flags; 2954 int err; 2955 2956 if (is_mcq_enabled(hba)) { 2957 /* 2958 * MCQ mode. Clean up the MCQ resources similar to 2959 * what the ufshcd_utrl_clear() does for SDB mode. 2960 */ 2961 err = ufshcd_mcq_sq_cleanup(hba, task_tag); 2962 if (err) { 2963 dev_err(hba->dev, "%s: failed tag=%d. err=%d\n", 2964 __func__, task_tag, err); 2965 return err; 2966 } 2967 return 0; 2968 } 2969 2970 /* clear outstanding transaction before retry */ 2971 spin_lock_irqsave(hba->host->host_lock, flags); 2972 ufshcd_utrl_clear(hba, mask); 2973 spin_unlock_irqrestore(hba->host->host_lock, flags); 2974 2975 /* 2976 * wait for h/w to clear corresponding bit in door-bell. 2977 * max. wait is 1 sec. 2978 */ 2979 return ufshcd_wait_for_register(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL, 2980 mask, ~mask, 1000, 1000); 2981 } 2982 2983 /** 2984 * ufshcd_dev_cmd_completion() - handles device management command responses 2985 * @hba: per adapter instance 2986 * @lrbp: pointer to local reference block 2987 * 2988 * Return: 0 upon success; < 0 upon failure. 2989 */ 2990 static int 2991 ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) 2992 { 2993 enum upiu_response_transaction resp; 2994 int err = 0; 2995 2996 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0); 2997 resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr); 2998 2999 switch (resp) { 3000 case UPIU_TRANSACTION_NOP_IN: 3001 if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) { 3002 err = -EINVAL; 3003 dev_err(hba->dev, "%s: unexpected response %x\n", 3004 __func__, resp); 3005 } 3006 break; 3007 case UPIU_TRANSACTION_QUERY_RSP: { 3008 u8 response = lrbp->ucd_rsp_ptr->header.response; 3009 3010 if (response == 0) 3011 err = ufshcd_copy_query_response(hba, lrbp); 3012 break; 3013 } 3014 case UPIU_TRANSACTION_REJECT_UPIU: 3015 /* TODO: handle Reject UPIU Response */ 3016 err = -EPERM; 3017 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n", 3018 __func__); 3019 break; 3020 case UPIU_TRANSACTION_RESPONSE: 3021 if (hba->dev_cmd.type != DEV_CMD_TYPE_RPMB) { 3022 err = -EINVAL; 3023 dev_err(hba->dev, "%s: unexpected response %x\n", __func__, resp); 3024 } 3025 break; 3026 default: 3027 err = -EINVAL; 3028 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n", 3029 __func__, resp); 3030 break; 3031 } 3032 3033 return err; 3034 } 3035 3036 static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba, 3037 struct ufshcd_lrb *lrbp, int max_timeout) 3038 { 3039 unsigned long time_left = msecs_to_jiffies(max_timeout); 3040 unsigned long flags; 3041 bool pending; 3042 int err; 3043 3044 retry: 3045 time_left = wait_for_completion_timeout(hba->dev_cmd.complete, 3046 time_left); 3047 3048 if (likely(time_left)) { 3049 /* 3050 * The completion handler called complete() and the caller of 3051 * this function still owns the @lrbp tag so the code below does 3052 * not trigger any race conditions. 3053 */ 3054 hba->dev_cmd.complete = NULL; 3055 err = ufshcd_get_tr_ocs(lrbp, NULL); 3056 if (!err) 3057 err = ufshcd_dev_cmd_completion(hba, lrbp); 3058 } else { 3059 err = -ETIMEDOUT; 3060 dev_dbg(hba->dev, "%s: dev_cmd request timedout, tag %d\n", 3061 __func__, lrbp->task_tag); 3062 3063 /* MCQ mode */ 3064 if (is_mcq_enabled(hba)) { 3065 err = ufshcd_clear_cmd(hba, lrbp->task_tag); 3066 hba->dev_cmd.complete = NULL; 3067 return err; 3068 } 3069 3070 /* SDB mode */ 3071 if (ufshcd_clear_cmd(hba, lrbp->task_tag) == 0) { 3072 /* successfully cleared the command, retry if needed */ 3073 err = -EAGAIN; 3074 /* 3075 * Since clearing the command succeeded we also need to 3076 * clear the task tag bit from the outstanding_reqs 3077 * variable. 3078 */ 3079 spin_lock_irqsave(&hba->outstanding_lock, flags); 3080 pending = test_bit(lrbp->task_tag, 3081 &hba->outstanding_reqs); 3082 if (pending) { 3083 hba->dev_cmd.complete = NULL; 3084 __clear_bit(lrbp->task_tag, 3085 &hba->outstanding_reqs); 3086 } 3087 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 3088 3089 if (!pending) { 3090 /* 3091 * The completion handler ran while we tried to 3092 * clear the command. 3093 */ 3094 time_left = 1; 3095 goto retry; 3096 } 3097 } else { 3098 dev_err(hba->dev, "%s: failed to clear tag %d\n", 3099 __func__, lrbp->task_tag); 3100 3101 spin_lock_irqsave(&hba->outstanding_lock, flags); 3102 pending = test_bit(lrbp->task_tag, 3103 &hba->outstanding_reqs); 3104 if (pending) 3105 hba->dev_cmd.complete = NULL; 3106 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 3107 3108 if (!pending) { 3109 /* 3110 * The completion handler ran while we tried to 3111 * clear the command. 3112 */ 3113 time_left = 1; 3114 goto retry; 3115 } 3116 } 3117 } 3118 3119 return err; 3120 } 3121 3122 /** 3123 * ufshcd_exec_dev_cmd - API for sending device management requests 3124 * @hba: UFS hba 3125 * @cmd_type: specifies the type (NOP, Query...) 3126 * @timeout: timeout in milliseconds 3127 * 3128 * Return: 0 upon success; < 0 upon failure. 3129 * 3130 * NOTE: Since there is only one available tag for device management commands, 3131 * it is expected you hold the hba->dev_cmd.lock mutex. 3132 */ 3133 static int ufshcd_exec_dev_cmd(struct ufs_hba *hba, 3134 enum dev_cmd_type cmd_type, int timeout) 3135 { 3136 DECLARE_COMPLETION_ONSTACK(wait); 3137 const u32 tag = hba->reserved_slot; 3138 struct ufshcd_lrb *lrbp; 3139 int err; 3140 3141 /* Protects use of hba->reserved_slot. */ 3142 lockdep_assert_held(&hba->dev_cmd.lock); 3143 3144 down_read(&hba->clk_scaling_lock); 3145 3146 lrbp = &hba->lrb[tag]; 3147 lrbp->cmd = NULL; 3148 err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag); 3149 if (unlikely(err)) 3150 goto out; 3151 3152 hba->dev_cmd.complete = &wait; 3153 3154 ufshcd_add_query_upiu_trace(hba, UFS_QUERY_SEND, lrbp->ucd_req_ptr); 3155 3156 ufshcd_send_command(hba, tag, hba->dev_cmd_queue); 3157 err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout); 3158 ufshcd_add_query_upiu_trace(hba, err ? UFS_QUERY_ERR : UFS_QUERY_COMP, 3159 (struct utp_upiu_req *)lrbp->ucd_rsp_ptr); 3160 3161 out: 3162 up_read(&hba->clk_scaling_lock); 3163 return err; 3164 } 3165 3166 /** 3167 * ufshcd_init_query() - init the query response and request parameters 3168 * @hba: per-adapter instance 3169 * @request: address of the request pointer to be initialized 3170 * @response: address of the response pointer to be initialized 3171 * @opcode: operation to perform 3172 * @idn: flag idn to access 3173 * @index: LU number to access 3174 * @selector: query/flag/descriptor further identification 3175 */ 3176 static inline void ufshcd_init_query(struct ufs_hba *hba, 3177 struct ufs_query_req **request, struct ufs_query_res **response, 3178 enum query_opcode opcode, u8 idn, u8 index, u8 selector) 3179 { 3180 *request = &hba->dev_cmd.query.request; 3181 *response = &hba->dev_cmd.query.response; 3182 memset(*request, 0, sizeof(struct ufs_query_req)); 3183 memset(*response, 0, sizeof(struct ufs_query_res)); 3184 (*request)->upiu_req.opcode = opcode; 3185 (*request)->upiu_req.idn = idn; 3186 (*request)->upiu_req.index = index; 3187 (*request)->upiu_req.selector = selector; 3188 } 3189 3190 static int ufshcd_query_flag_retry(struct ufs_hba *hba, 3191 enum query_opcode opcode, enum flag_idn idn, u8 index, bool *flag_res) 3192 { 3193 int ret; 3194 int retries; 3195 3196 for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) { 3197 ret = ufshcd_query_flag(hba, opcode, idn, index, flag_res); 3198 if (ret) 3199 dev_dbg(hba->dev, 3200 "%s: failed with error %d, retries %d\n", 3201 __func__, ret, retries); 3202 else 3203 break; 3204 } 3205 3206 if (ret) 3207 dev_err(hba->dev, 3208 "%s: query flag, opcode %d, idn %d, failed with error %d after %d retries\n", 3209 __func__, opcode, idn, ret, retries); 3210 return ret; 3211 } 3212 3213 /** 3214 * ufshcd_query_flag() - API function for sending flag query requests 3215 * @hba: per-adapter instance 3216 * @opcode: flag query to perform 3217 * @idn: flag idn to access 3218 * @index: flag index to access 3219 * @flag_res: the flag value after the query request completes 3220 * 3221 * Return: 0 for success, non-zero in case of failure. 3222 */ 3223 int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode, 3224 enum flag_idn idn, u8 index, bool *flag_res) 3225 { 3226 struct ufs_query_req *request = NULL; 3227 struct ufs_query_res *response = NULL; 3228 int err, selector = 0; 3229 int timeout = QUERY_REQ_TIMEOUT; 3230 3231 BUG_ON(!hba); 3232 3233 ufshcd_hold(hba); 3234 mutex_lock(&hba->dev_cmd.lock); 3235 ufshcd_init_query(hba, &request, &response, opcode, idn, index, 3236 selector); 3237 3238 switch (opcode) { 3239 case UPIU_QUERY_OPCODE_SET_FLAG: 3240 case UPIU_QUERY_OPCODE_CLEAR_FLAG: 3241 case UPIU_QUERY_OPCODE_TOGGLE_FLAG: 3242 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 3243 break; 3244 case UPIU_QUERY_OPCODE_READ_FLAG: 3245 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; 3246 if (!flag_res) { 3247 /* No dummy reads */ 3248 dev_err(hba->dev, "%s: Invalid argument for read request\n", 3249 __func__); 3250 err = -EINVAL; 3251 goto out_unlock; 3252 } 3253 break; 3254 default: 3255 dev_err(hba->dev, 3256 "%s: Expected query flag opcode but got = %d\n", 3257 __func__, opcode); 3258 err = -EINVAL; 3259 goto out_unlock; 3260 } 3261 3262 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout); 3263 3264 if (err) { 3265 dev_err(hba->dev, 3266 "%s: Sending flag query for idn %d failed, err = %d\n", 3267 __func__, idn, err); 3268 goto out_unlock; 3269 } 3270 3271 if (flag_res) 3272 *flag_res = (be32_to_cpu(response->upiu_res.value) & 3273 MASK_QUERY_UPIU_FLAG_LOC) & 0x1; 3274 3275 out_unlock: 3276 mutex_unlock(&hba->dev_cmd.lock); 3277 ufshcd_release(hba); 3278 return err; 3279 } 3280 3281 /** 3282 * ufshcd_query_attr - API function for sending attribute requests 3283 * @hba: per-adapter instance 3284 * @opcode: attribute opcode 3285 * @idn: attribute idn to access 3286 * @index: index field 3287 * @selector: selector field 3288 * @attr_val: the attribute value after the query request completes 3289 * 3290 * Return: 0 for success, non-zero in case of failure. 3291 */ 3292 int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode, 3293 enum attr_idn idn, u8 index, u8 selector, u32 *attr_val) 3294 { 3295 struct ufs_query_req *request = NULL; 3296 struct ufs_query_res *response = NULL; 3297 int err; 3298 3299 BUG_ON(!hba); 3300 3301 if (!attr_val) { 3302 dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n", 3303 __func__, opcode); 3304 return -EINVAL; 3305 } 3306 3307 ufshcd_hold(hba); 3308 3309 mutex_lock(&hba->dev_cmd.lock); 3310 ufshcd_init_query(hba, &request, &response, opcode, idn, index, 3311 selector); 3312 3313 switch (opcode) { 3314 case UPIU_QUERY_OPCODE_WRITE_ATTR: 3315 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 3316 request->upiu_req.value = cpu_to_be32(*attr_val); 3317 break; 3318 case UPIU_QUERY_OPCODE_READ_ATTR: 3319 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; 3320 break; 3321 default: 3322 dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n", 3323 __func__, opcode); 3324 err = -EINVAL; 3325 goto out_unlock; 3326 } 3327 3328 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT); 3329 3330 if (err) { 3331 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n", 3332 __func__, opcode, idn, index, err); 3333 goto out_unlock; 3334 } 3335 3336 *attr_val = be32_to_cpu(response->upiu_res.value); 3337 3338 out_unlock: 3339 mutex_unlock(&hba->dev_cmd.lock); 3340 ufshcd_release(hba); 3341 return err; 3342 } 3343 3344 /** 3345 * ufshcd_query_attr_retry() - API function for sending query 3346 * attribute with retries 3347 * @hba: per-adapter instance 3348 * @opcode: attribute opcode 3349 * @idn: attribute idn to access 3350 * @index: index field 3351 * @selector: selector field 3352 * @attr_val: the attribute value after the query request 3353 * completes 3354 * 3355 * Return: 0 for success, non-zero in case of failure. 3356 */ 3357 int ufshcd_query_attr_retry(struct ufs_hba *hba, 3358 enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector, 3359 u32 *attr_val) 3360 { 3361 int ret = 0; 3362 u32 retries; 3363 3364 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) { 3365 ret = ufshcd_query_attr(hba, opcode, idn, index, 3366 selector, attr_val); 3367 if (ret) 3368 dev_dbg(hba->dev, "%s: failed with error %d, retries %d\n", 3369 __func__, ret, retries); 3370 else 3371 break; 3372 } 3373 3374 if (ret) 3375 dev_err(hba->dev, 3376 "%s: query attribute, idn %d, failed with error %d after %d retries\n", 3377 __func__, idn, ret, QUERY_REQ_RETRIES); 3378 return ret; 3379 } 3380 3381 static int __ufshcd_query_descriptor(struct ufs_hba *hba, 3382 enum query_opcode opcode, enum desc_idn idn, u8 index, 3383 u8 selector, u8 *desc_buf, int *buf_len) 3384 { 3385 struct ufs_query_req *request = NULL; 3386 struct ufs_query_res *response = NULL; 3387 int err; 3388 3389 BUG_ON(!hba); 3390 3391 if (!desc_buf) { 3392 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n", 3393 __func__, opcode); 3394 return -EINVAL; 3395 } 3396 3397 if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) { 3398 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n", 3399 __func__, *buf_len); 3400 return -EINVAL; 3401 } 3402 3403 ufshcd_hold(hba); 3404 3405 mutex_lock(&hba->dev_cmd.lock); 3406 ufshcd_init_query(hba, &request, &response, opcode, idn, index, 3407 selector); 3408 hba->dev_cmd.query.descriptor = desc_buf; 3409 request->upiu_req.length = cpu_to_be16(*buf_len); 3410 3411 switch (opcode) { 3412 case UPIU_QUERY_OPCODE_WRITE_DESC: 3413 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 3414 break; 3415 case UPIU_QUERY_OPCODE_READ_DESC: 3416 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; 3417 break; 3418 default: 3419 dev_err(hba->dev, 3420 "%s: Expected query descriptor opcode but got = 0x%.2x\n", 3421 __func__, opcode); 3422 err = -EINVAL; 3423 goto out_unlock; 3424 } 3425 3426 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT); 3427 3428 if (err) { 3429 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n", 3430 __func__, opcode, idn, index, err); 3431 goto out_unlock; 3432 } 3433 3434 *buf_len = be16_to_cpu(response->upiu_res.length); 3435 3436 out_unlock: 3437 hba->dev_cmd.query.descriptor = NULL; 3438 mutex_unlock(&hba->dev_cmd.lock); 3439 ufshcd_release(hba); 3440 return err; 3441 } 3442 3443 /** 3444 * ufshcd_query_descriptor_retry - API function for sending descriptor requests 3445 * @hba: per-adapter instance 3446 * @opcode: attribute opcode 3447 * @idn: attribute idn to access 3448 * @index: index field 3449 * @selector: selector field 3450 * @desc_buf: the buffer that contains the descriptor 3451 * @buf_len: length parameter passed to the device 3452 * 3453 * The buf_len parameter will contain, on return, the length parameter 3454 * received on the response. 3455 * 3456 * Return: 0 for success, non-zero in case of failure. 3457 */ 3458 int ufshcd_query_descriptor_retry(struct ufs_hba *hba, 3459 enum query_opcode opcode, 3460 enum desc_idn idn, u8 index, 3461 u8 selector, 3462 u8 *desc_buf, int *buf_len) 3463 { 3464 int err; 3465 int retries; 3466 3467 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) { 3468 err = __ufshcd_query_descriptor(hba, opcode, idn, index, 3469 selector, desc_buf, buf_len); 3470 if (!err || err == -EINVAL) 3471 break; 3472 } 3473 3474 return err; 3475 } 3476 3477 /** 3478 * ufshcd_read_desc_param - read the specified descriptor parameter 3479 * @hba: Pointer to adapter instance 3480 * @desc_id: descriptor idn value 3481 * @desc_index: descriptor index 3482 * @param_offset: offset of the parameter to read 3483 * @param_read_buf: pointer to buffer where parameter would be read 3484 * @param_size: sizeof(param_read_buf) 3485 * 3486 * Return: 0 in case of success, non-zero otherwise. 3487 */ 3488 int ufshcd_read_desc_param(struct ufs_hba *hba, 3489 enum desc_idn desc_id, 3490 int desc_index, 3491 u8 param_offset, 3492 u8 *param_read_buf, 3493 u8 param_size) 3494 { 3495 int ret; 3496 u8 *desc_buf; 3497 int buff_len = QUERY_DESC_MAX_SIZE; 3498 bool is_kmalloc = true; 3499 3500 /* Safety check */ 3501 if (desc_id >= QUERY_DESC_IDN_MAX || !param_size) 3502 return -EINVAL; 3503 3504 /* Check whether we need temp memory */ 3505 if (param_offset != 0 || param_size < buff_len) { 3506 desc_buf = kzalloc(buff_len, GFP_KERNEL); 3507 if (!desc_buf) 3508 return -ENOMEM; 3509 } else { 3510 desc_buf = param_read_buf; 3511 is_kmalloc = false; 3512 } 3513 3514 /* Request for full descriptor */ 3515 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC, 3516 desc_id, desc_index, 0, 3517 desc_buf, &buff_len); 3518 if (ret) { 3519 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d\n", 3520 __func__, desc_id, desc_index, param_offset, ret); 3521 goto out; 3522 } 3523 3524 /* Update descriptor length */ 3525 buff_len = desc_buf[QUERY_DESC_LENGTH_OFFSET]; 3526 3527 if (param_offset >= buff_len) { 3528 dev_err(hba->dev, "%s: Invalid offset 0x%x in descriptor IDN 0x%x, length 0x%x\n", 3529 __func__, param_offset, desc_id, buff_len); 3530 ret = -EINVAL; 3531 goto out; 3532 } 3533 3534 /* Sanity check */ 3535 if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) { 3536 dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header\n", 3537 __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]); 3538 ret = -EINVAL; 3539 goto out; 3540 } 3541 3542 if (is_kmalloc) { 3543 /* Make sure we don't copy more data than available */ 3544 if (param_offset >= buff_len) 3545 ret = -EINVAL; 3546 else 3547 memcpy(param_read_buf, &desc_buf[param_offset], 3548 min_t(u32, param_size, buff_len - param_offset)); 3549 } 3550 out: 3551 if (is_kmalloc) 3552 kfree(desc_buf); 3553 return ret; 3554 } 3555 3556 /** 3557 * struct uc_string_id - unicode string 3558 * 3559 * @len: size of this descriptor inclusive 3560 * @type: descriptor type 3561 * @uc: unicode string character 3562 */ 3563 struct uc_string_id { 3564 u8 len; 3565 u8 type; 3566 wchar_t uc[]; 3567 } __packed; 3568 3569 /* replace non-printable or non-ASCII characters with spaces */ 3570 static inline char ufshcd_remove_non_printable(u8 ch) 3571 { 3572 return (ch >= 0x20 && ch <= 0x7e) ? ch : ' '; 3573 } 3574 3575 /** 3576 * ufshcd_read_string_desc - read string descriptor 3577 * @hba: pointer to adapter instance 3578 * @desc_index: descriptor index 3579 * @buf: pointer to buffer where descriptor would be read, 3580 * the caller should free the memory. 3581 * @ascii: if true convert from unicode to ascii characters 3582 * null terminated string. 3583 * 3584 * Return: 3585 * * string size on success. 3586 * * -ENOMEM: on allocation failure 3587 * * -EINVAL: on a wrong parameter 3588 */ 3589 int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index, 3590 u8 **buf, bool ascii) 3591 { 3592 struct uc_string_id *uc_str; 3593 u8 *str; 3594 int ret; 3595 3596 if (!buf) 3597 return -EINVAL; 3598 3599 uc_str = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL); 3600 if (!uc_str) 3601 return -ENOMEM; 3602 3603 ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_STRING, desc_index, 0, 3604 (u8 *)uc_str, QUERY_DESC_MAX_SIZE); 3605 if (ret < 0) { 3606 dev_err(hba->dev, "Reading String Desc failed after %d retries. err = %d\n", 3607 QUERY_REQ_RETRIES, ret); 3608 str = NULL; 3609 goto out; 3610 } 3611 3612 if (uc_str->len <= QUERY_DESC_HDR_SIZE) { 3613 dev_dbg(hba->dev, "String Desc is of zero length\n"); 3614 str = NULL; 3615 ret = 0; 3616 goto out; 3617 } 3618 3619 if (ascii) { 3620 ssize_t ascii_len; 3621 int i; 3622 /* remove header and divide by 2 to move from UTF16 to UTF8 */ 3623 ascii_len = (uc_str->len - QUERY_DESC_HDR_SIZE) / 2 + 1; 3624 str = kzalloc(ascii_len, GFP_KERNEL); 3625 if (!str) { 3626 ret = -ENOMEM; 3627 goto out; 3628 } 3629 3630 /* 3631 * the descriptor contains string in UTF16 format 3632 * we need to convert to utf-8 so it can be displayed 3633 */ 3634 ret = utf16s_to_utf8s(uc_str->uc, 3635 uc_str->len - QUERY_DESC_HDR_SIZE, 3636 UTF16_BIG_ENDIAN, str, ascii_len - 1); 3637 3638 /* replace non-printable or non-ASCII characters with spaces */ 3639 for (i = 0; i < ret; i++) 3640 str[i] = ufshcd_remove_non_printable(str[i]); 3641 3642 str[ret++] = '\0'; 3643 3644 } else { 3645 str = kmemdup(uc_str, uc_str->len, GFP_KERNEL); 3646 if (!str) { 3647 ret = -ENOMEM; 3648 goto out; 3649 } 3650 ret = uc_str->len; 3651 } 3652 out: 3653 *buf = str; 3654 kfree(uc_str); 3655 return ret; 3656 } 3657 3658 /** 3659 * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter 3660 * @hba: Pointer to adapter instance 3661 * @lun: lun id 3662 * @param_offset: offset of the parameter to read 3663 * @param_read_buf: pointer to buffer where parameter would be read 3664 * @param_size: sizeof(param_read_buf) 3665 * 3666 * Return: 0 in case of success, non-zero otherwise. 3667 */ 3668 static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba, 3669 int lun, 3670 enum unit_desc_param param_offset, 3671 u8 *param_read_buf, 3672 u32 param_size) 3673 { 3674 /* 3675 * Unit descriptors are only available for general purpose LUs (LUN id 3676 * from 0 to 7) and RPMB Well known LU. 3677 */ 3678 if (!ufs_is_valid_unit_desc_lun(&hba->dev_info, lun)) 3679 return -EOPNOTSUPP; 3680 3681 return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun, 3682 param_offset, param_read_buf, param_size); 3683 } 3684 3685 static int ufshcd_get_ref_clk_gating_wait(struct ufs_hba *hba) 3686 { 3687 int err = 0; 3688 u32 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US; 3689 3690 if (hba->dev_info.wspecversion >= 0x300) { 3691 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 3692 QUERY_ATTR_IDN_REF_CLK_GATING_WAIT_TIME, 0, 0, 3693 &gating_wait); 3694 if (err) 3695 dev_err(hba->dev, "Failed reading bRefClkGatingWait. err = %d, use default %uus\n", 3696 err, gating_wait); 3697 3698 if (gating_wait == 0) { 3699 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US; 3700 dev_err(hba->dev, "Undefined ref clk gating wait time, use default %uus\n", 3701 gating_wait); 3702 } 3703 3704 hba->dev_info.clk_gating_wait_us = gating_wait; 3705 } 3706 3707 return err; 3708 } 3709 3710 /** 3711 * ufshcd_memory_alloc - allocate memory for host memory space data structures 3712 * @hba: per adapter instance 3713 * 3714 * 1. Allocate DMA memory for Command Descriptor array 3715 * Each command descriptor consist of Command UPIU, Response UPIU and PRDT 3716 * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL). 3717 * 3. Allocate DMA memory for UTP Task Management Request Descriptor List 3718 * (UTMRDL) 3719 * 4. Allocate memory for local reference block(lrb). 3720 * 3721 * Return: 0 for success, non-zero in case of failure. 3722 */ 3723 static int ufshcd_memory_alloc(struct ufs_hba *hba) 3724 { 3725 size_t utmrdl_size, utrdl_size, ucdl_size; 3726 3727 /* Allocate memory for UTP command descriptors */ 3728 ucdl_size = ufshcd_get_ucd_size(hba) * hba->nutrs; 3729 hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev, 3730 ucdl_size, 3731 &hba->ucdl_dma_addr, 3732 GFP_KERNEL); 3733 3734 /* 3735 * UFSHCI requires UTP command descriptor to be 128 byte aligned. 3736 */ 3737 if (!hba->ucdl_base_addr || 3738 WARN_ON(hba->ucdl_dma_addr & (128 - 1))) { 3739 dev_err(hba->dev, 3740 "Command Descriptor Memory allocation failed\n"); 3741 goto out; 3742 } 3743 3744 /* 3745 * Allocate memory for UTP Transfer descriptors 3746 * UFSHCI requires 1KB alignment of UTRD 3747 */ 3748 utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs); 3749 hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev, 3750 utrdl_size, 3751 &hba->utrdl_dma_addr, 3752 GFP_KERNEL); 3753 if (!hba->utrdl_base_addr || 3754 WARN_ON(hba->utrdl_dma_addr & (SZ_1K - 1))) { 3755 dev_err(hba->dev, 3756 "Transfer Descriptor Memory allocation failed\n"); 3757 goto out; 3758 } 3759 3760 /* 3761 * Skip utmrdl allocation; it may have been 3762 * allocated during first pass and not released during 3763 * MCQ memory allocation. 3764 * See ufshcd_release_sdb_queue() and ufshcd_config_mcq() 3765 */ 3766 if (hba->utmrdl_base_addr) 3767 goto skip_utmrdl; 3768 /* 3769 * Allocate memory for UTP Task Management descriptors 3770 * UFSHCI requires 1KB alignment of UTMRD 3771 */ 3772 utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs; 3773 hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev, 3774 utmrdl_size, 3775 &hba->utmrdl_dma_addr, 3776 GFP_KERNEL); 3777 if (!hba->utmrdl_base_addr || 3778 WARN_ON(hba->utmrdl_dma_addr & (SZ_1K - 1))) { 3779 dev_err(hba->dev, 3780 "Task Management Descriptor Memory allocation failed\n"); 3781 goto out; 3782 } 3783 3784 skip_utmrdl: 3785 /* Allocate memory for local reference block */ 3786 hba->lrb = devm_kcalloc(hba->dev, 3787 hba->nutrs, sizeof(struct ufshcd_lrb), 3788 GFP_KERNEL); 3789 if (!hba->lrb) { 3790 dev_err(hba->dev, "LRB Memory allocation failed\n"); 3791 goto out; 3792 } 3793 return 0; 3794 out: 3795 return -ENOMEM; 3796 } 3797 3798 /** 3799 * ufshcd_host_memory_configure - configure local reference block with 3800 * memory offsets 3801 * @hba: per adapter instance 3802 * 3803 * Configure Host memory space 3804 * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA 3805 * address. 3806 * 2. Update each UTRD with Response UPIU offset, Response UPIU length 3807 * and PRDT offset. 3808 * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT 3809 * into local reference block. 3810 */ 3811 static void ufshcd_host_memory_configure(struct ufs_hba *hba) 3812 { 3813 struct utp_transfer_req_desc *utrdlp; 3814 dma_addr_t cmd_desc_dma_addr; 3815 dma_addr_t cmd_desc_element_addr; 3816 u16 response_offset; 3817 u16 prdt_offset; 3818 int cmd_desc_size; 3819 int i; 3820 3821 utrdlp = hba->utrdl_base_addr; 3822 3823 response_offset = 3824 offsetof(struct utp_transfer_cmd_desc, response_upiu); 3825 prdt_offset = 3826 offsetof(struct utp_transfer_cmd_desc, prd_table); 3827 3828 cmd_desc_size = ufshcd_get_ucd_size(hba); 3829 cmd_desc_dma_addr = hba->ucdl_dma_addr; 3830 3831 for (i = 0; i < hba->nutrs; i++) { 3832 /* Configure UTRD with command descriptor base address */ 3833 cmd_desc_element_addr = 3834 (cmd_desc_dma_addr + (cmd_desc_size * i)); 3835 utrdlp[i].command_desc_base_addr = 3836 cpu_to_le64(cmd_desc_element_addr); 3837 3838 /* Response upiu and prdt offset should be in double words */ 3839 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) { 3840 utrdlp[i].response_upiu_offset = 3841 cpu_to_le16(response_offset); 3842 utrdlp[i].prd_table_offset = 3843 cpu_to_le16(prdt_offset); 3844 utrdlp[i].response_upiu_length = 3845 cpu_to_le16(ALIGNED_UPIU_SIZE); 3846 } else { 3847 utrdlp[i].response_upiu_offset = 3848 cpu_to_le16(response_offset >> 2); 3849 utrdlp[i].prd_table_offset = 3850 cpu_to_le16(prdt_offset >> 2); 3851 utrdlp[i].response_upiu_length = 3852 cpu_to_le16(ALIGNED_UPIU_SIZE >> 2); 3853 } 3854 3855 ufshcd_init_lrb(hba, &hba->lrb[i], i); 3856 } 3857 } 3858 3859 /** 3860 * ufshcd_dme_link_startup - Notify Unipro to perform link startup 3861 * @hba: per adapter instance 3862 * 3863 * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer, 3864 * in order to initialize the Unipro link startup procedure. 3865 * Once the Unipro links are up, the device connected to the controller 3866 * is detected. 3867 * 3868 * Return: 0 on success, non-zero value on failure. 3869 */ 3870 static int ufshcd_dme_link_startup(struct ufs_hba *hba) 3871 { 3872 struct uic_command uic_cmd = {0}; 3873 int ret; 3874 3875 uic_cmd.command = UIC_CMD_DME_LINK_STARTUP; 3876 3877 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 3878 if (ret) 3879 dev_dbg(hba->dev, 3880 "dme-link-startup: error code %d\n", ret); 3881 return ret; 3882 } 3883 /** 3884 * ufshcd_dme_reset - UIC command for DME_RESET 3885 * @hba: per adapter instance 3886 * 3887 * DME_RESET command is issued in order to reset UniPro stack. 3888 * This function now deals with cold reset. 3889 * 3890 * Return: 0 on success, non-zero value on failure. 3891 */ 3892 static int ufshcd_dme_reset(struct ufs_hba *hba) 3893 { 3894 struct uic_command uic_cmd = {0}; 3895 int ret; 3896 3897 uic_cmd.command = UIC_CMD_DME_RESET; 3898 3899 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 3900 if (ret) 3901 dev_err(hba->dev, 3902 "dme-reset: error code %d\n", ret); 3903 3904 return ret; 3905 } 3906 3907 int ufshcd_dme_configure_adapt(struct ufs_hba *hba, 3908 int agreed_gear, 3909 int adapt_val) 3910 { 3911 int ret; 3912 3913 if (agreed_gear < UFS_HS_G4) 3914 adapt_val = PA_NO_ADAPT; 3915 3916 ret = ufshcd_dme_set(hba, 3917 UIC_ARG_MIB(PA_TXHSADAPTTYPE), 3918 adapt_val); 3919 return ret; 3920 } 3921 EXPORT_SYMBOL_GPL(ufshcd_dme_configure_adapt); 3922 3923 /** 3924 * ufshcd_dme_enable - UIC command for DME_ENABLE 3925 * @hba: per adapter instance 3926 * 3927 * DME_ENABLE command is issued in order to enable UniPro stack. 3928 * 3929 * Return: 0 on success, non-zero value on failure. 3930 */ 3931 static int ufshcd_dme_enable(struct ufs_hba *hba) 3932 { 3933 struct uic_command uic_cmd = {0}; 3934 int ret; 3935 3936 uic_cmd.command = UIC_CMD_DME_ENABLE; 3937 3938 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 3939 if (ret) 3940 dev_err(hba->dev, 3941 "dme-enable: error code %d\n", ret); 3942 3943 return ret; 3944 } 3945 3946 static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba) 3947 { 3948 #define MIN_DELAY_BEFORE_DME_CMDS_US 1000 3949 unsigned long min_sleep_time_us; 3950 3951 if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS)) 3952 return; 3953 3954 /* 3955 * last_dme_cmd_tstamp will be 0 only for 1st call to 3956 * this function 3957 */ 3958 if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) { 3959 min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US; 3960 } else { 3961 unsigned long delta = 3962 (unsigned long) ktime_to_us( 3963 ktime_sub(ktime_get(), 3964 hba->last_dme_cmd_tstamp)); 3965 3966 if (delta < MIN_DELAY_BEFORE_DME_CMDS_US) 3967 min_sleep_time_us = 3968 MIN_DELAY_BEFORE_DME_CMDS_US - delta; 3969 else 3970 return; /* no more delay required */ 3971 } 3972 3973 /* allow sleep for extra 50us if needed */ 3974 usleep_range(min_sleep_time_us, min_sleep_time_us + 50); 3975 } 3976 3977 /** 3978 * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET 3979 * @hba: per adapter instance 3980 * @attr_sel: uic command argument1 3981 * @attr_set: attribute set type as uic command argument2 3982 * @mib_val: setting value as uic command argument3 3983 * @peer: indicate whether peer or local 3984 * 3985 * Return: 0 on success, non-zero value on failure. 3986 */ 3987 int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel, 3988 u8 attr_set, u32 mib_val, u8 peer) 3989 { 3990 struct uic_command uic_cmd = {0}; 3991 static const char *const action[] = { 3992 "dme-set", 3993 "dme-peer-set" 3994 }; 3995 const char *set = action[!!peer]; 3996 int ret; 3997 int retries = UFS_UIC_COMMAND_RETRIES; 3998 3999 uic_cmd.command = peer ? 4000 UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET; 4001 uic_cmd.argument1 = attr_sel; 4002 uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set); 4003 uic_cmd.argument3 = mib_val; 4004 4005 do { 4006 /* for peer attributes we retry upon failure */ 4007 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 4008 if (ret) 4009 dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n", 4010 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret); 4011 } while (ret && peer && --retries); 4012 4013 if (ret) 4014 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n", 4015 set, UIC_GET_ATTR_ID(attr_sel), mib_val, 4016 UFS_UIC_COMMAND_RETRIES - retries); 4017 4018 return ret; 4019 } 4020 EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr); 4021 4022 /** 4023 * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET 4024 * @hba: per adapter instance 4025 * @attr_sel: uic command argument1 4026 * @mib_val: the value of the attribute as returned by the UIC command 4027 * @peer: indicate whether peer or local 4028 * 4029 * Return: 0 on success, non-zero value on failure. 4030 */ 4031 int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel, 4032 u32 *mib_val, u8 peer) 4033 { 4034 struct uic_command uic_cmd = {0}; 4035 static const char *const action[] = { 4036 "dme-get", 4037 "dme-peer-get" 4038 }; 4039 const char *get = action[!!peer]; 4040 int ret; 4041 int retries = UFS_UIC_COMMAND_RETRIES; 4042 struct ufs_pa_layer_attr orig_pwr_info; 4043 struct ufs_pa_layer_attr temp_pwr_info; 4044 bool pwr_mode_change = false; 4045 4046 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) { 4047 orig_pwr_info = hba->pwr_info; 4048 temp_pwr_info = orig_pwr_info; 4049 4050 if (orig_pwr_info.pwr_tx == FAST_MODE || 4051 orig_pwr_info.pwr_rx == FAST_MODE) { 4052 temp_pwr_info.pwr_tx = FASTAUTO_MODE; 4053 temp_pwr_info.pwr_rx = FASTAUTO_MODE; 4054 pwr_mode_change = true; 4055 } else if (orig_pwr_info.pwr_tx == SLOW_MODE || 4056 orig_pwr_info.pwr_rx == SLOW_MODE) { 4057 temp_pwr_info.pwr_tx = SLOWAUTO_MODE; 4058 temp_pwr_info.pwr_rx = SLOWAUTO_MODE; 4059 pwr_mode_change = true; 4060 } 4061 if (pwr_mode_change) { 4062 ret = ufshcd_change_power_mode(hba, &temp_pwr_info); 4063 if (ret) 4064 goto out; 4065 } 4066 } 4067 4068 uic_cmd.command = peer ? 4069 UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET; 4070 uic_cmd.argument1 = attr_sel; 4071 4072 do { 4073 /* for peer attributes we retry upon failure */ 4074 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 4075 if (ret) 4076 dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n", 4077 get, UIC_GET_ATTR_ID(attr_sel), ret); 4078 } while (ret && peer && --retries); 4079 4080 if (ret) 4081 dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n", 4082 get, UIC_GET_ATTR_ID(attr_sel), 4083 UFS_UIC_COMMAND_RETRIES - retries); 4084 4085 if (mib_val && !ret) 4086 *mib_val = uic_cmd.argument3; 4087 4088 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE) 4089 && pwr_mode_change) 4090 ufshcd_change_power_mode(hba, &orig_pwr_info); 4091 out: 4092 return ret; 4093 } 4094 EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr); 4095 4096 /** 4097 * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power 4098 * state) and waits for it to take effect. 4099 * 4100 * @hba: per adapter instance 4101 * @cmd: UIC command to execute 4102 * 4103 * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER & 4104 * DME_HIBERNATE_EXIT commands take some time to take its effect on both host 4105 * and device UniPro link and hence it's final completion would be indicated by 4106 * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in 4107 * addition to normal UIC command completion Status (UCCS). This function only 4108 * returns after the relevant status bits indicate the completion. 4109 * 4110 * Return: 0 on success, non-zero value on failure. 4111 */ 4112 static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd) 4113 { 4114 DECLARE_COMPLETION_ONSTACK(uic_async_done); 4115 unsigned long flags; 4116 u8 status; 4117 int ret; 4118 bool reenable_intr = false; 4119 4120 mutex_lock(&hba->uic_cmd_mutex); 4121 ufshcd_add_delay_before_dme_cmd(hba); 4122 4123 spin_lock_irqsave(hba->host->host_lock, flags); 4124 if (ufshcd_is_link_broken(hba)) { 4125 ret = -ENOLINK; 4126 goto out_unlock; 4127 } 4128 hba->uic_async_done = &uic_async_done; 4129 if (ufshcd_readl(hba, REG_INTERRUPT_ENABLE) & UIC_COMMAND_COMPL) { 4130 ufshcd_disable_intr(hba, UIC_COMMAND_COMPL); 4131 /* 4132 * Make sure UIC command completion interrupt is disabled before 4133 * issuing UIC command. 4134 */ 4135 wmb(); 4136 reenable_intr = true; 4137 } 4138 spin_unlock_irqrestore(hba->host->host_lock, flags); 4139 ret = __ufshcd_send_uic_cmd(hba, cmd, false); 4140 if (ret) { 4141 dev_err(hba->dev, 4142 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n", 4143 cmd->command, cmd->argument3, ret); 4144 goto out; 4145 } 4146 4147 if (!wait_for_completion_timeout(hba->uic_async_done, 4148 msecs_to_jiffies(UIC_CMD_TIMEOUT))) { 4149 dev_err(hba->dev, 4150 "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n", 4151 cmd->command, cmd->argument3); 4152 4153 if (!cmd->cmd_active) { 4154 dev_err(hba->dev, "%s: Power Mode Change operation has been completed, go check UPMCRS\n", 4155 __func__); 4156 goto check_upmcrs; 4157 } 4158 4159 ret = -ETIMEDOUT; 4160 goto out; 4161 } 4162 4163 check_upmcrs: 4164 status = ufshcd_get_upmcrs(hba); 4165 if (status != PWR_LOCAL) { 4166 dev_err(hba->dev, 4167 "pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n", 4168 cmd->command, status); 4169 ret = (status != PWR_OK) ? status : -1; 4170 } 4171 out: 4172 if (ret) { 4173 ufshcd_print_host_state(hba); 4174 ufshcd_print_pwr_info(hba); 4175 ufshcd_print_evt_hist(hba); 4176 } 4177 4178 spin_lock_irqsave(hba->host->host_lock, flags); 4179 hba->active_uic_cmd = NULL; 4180 hba->uic_async_done = NULL; 4181 if (reenable_intr) 4182 ufshcd_enable_intr(hba, UIC_COMMAND_COMPL); 4183 if (ret) { 4184 ufshcd_set_link_broken(hba); 4185 ufshcd_schedule_eh_work(hba); 4186 } 4187 out_unlock: 4188 spin_unlock_irqrestore(hba->host->host_lock, flags); 4189 mutex_unlock(&hba->uic_cmd_mutex); 4190 4191 return ret; 4192 } 4193 4194 /** 4195 * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage 4196 * using DME_SET primitives. 4197 * @hba: per adapter instance 4198 * @mode: powr mode value 4199 * 4200 * Return: 0 on success, non-zero value on failure. 4201 */ 4202 int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode) 4203 { 4204 struct uic_command uic_cmd = {0}; 4205 int ret; 4206 4207 if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) { 4208 ret = ufshcd_dme_set(hba, 4209 UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1); 4210 if (ret) { 4211 dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n", 4212 __func__, ret); 4213 goto out; 4214 } 4215 } 4216 4217 uic_cmd.command = UIC_CMD_DME_SET; 4218 uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE); 4219 uic_cmd.argument3 = mode; 4220 ufshcd_hold(hba); 4221 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd); 4222 ufshcd_release(hba); 4223 4224 out: 4225 return ret; 4226 } 4227 EXPORT_SYMBOL_GPL(ufshcd_uic_change_pwr_mode); 4228 4229 int ufshcd_link_recovery(struct ufs_hba *hba) 4230 { 4231 int ret; 4232 unsigned long flags; 4233 4234 spin_lock_irqsave(hba->host->host_lock, flags); 4235 hba->ufshcd_state = UFSHCD_STATE_RESET; 4236 ufshcd_set_eh_in_progress(hba); 4237 spin_unlock_irqrestore(hba->host->host_lock, flags); 4238 4239 /* Reset the attached device */ 4240 ufshcd_device_reset(hba); 4241 4242 ret = ufshcd_host_reset_and_restore(hba); 4243 4244 spin_lock_irqsave(hba->host->host_lock, flags); 4245 if (ret) 4246 hba->ufshcd_state = UFSHCD_STATE_ERROR; 4247 ufshcd_clear_eh_in_progress(hba); 4248 spin_unlock_irqrestore(hba->host->host_lock, flags); 4249 4250 if (ret) 4251 dev_err(hba->dev, "%s: link recovery failed, err %d", 4252 __func__, ret); 4253 4254 return ret; 4255 } 4256 EXPORT_SYMBOL_GPL(ufshcd_link_recovery); 4257 4258 int ufshcd_uic_hibern8_enter(struct ufs_hba *hba) 4259 { 4260 int ret; 4261 struct uic_command uic_cmd = {0}; 4262 ktime_t start = ktime_get(); 4263 4264 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, PRE_CHANGE); 4265 4266 uic_cmd.command = UIC_CMD_DME_HIBER_ENTER; 4267 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd); 4268 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "enter", 4269 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 4270 4271 if (ret) 4272 dev_err(hba->dev, "%s: hibern8 enter failed. ret = %d\n", 4273 __func__, ret); 4274 else 4275 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, 4276 POST_CHANGE); 4277 4278 return ret; 4279 } 4280 EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_enter); 4281 4282 int ufshcd_uic_hibern8_exit(struct ufs_hba *hba) 4283 { 4284 struct uic_command uic_cmd = {0}; 4285 int ret; 4286 ktime_t start = ktime_get(); 4287 4288 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, PRE_CHANGE); 4289 4290 uic_cmd.command = UIC_CMD_DME_HIBER_EXIT; 4291 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd); 4292 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "exit", 4293 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 4294 4295 if (ret) { 4296 dev_err(hba->dev, "%s: hibern8 exit failed. ret = %d\n", 4297 __func__, ret); 4298 } else { 4299 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, 4300 POST_CHANGE); 4301 hba->ufs_stats.last_hibern8_exit_tstamp = local_clock(); 4302 hba->ufs_stats.hibern8_exit_cnt++; 4303 } 4304 4305 return ret; 4306 } 4307 EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_exit); 4308 4309 void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit) 4310 { 4311 unsigned long flags; 4312 bool update = false; 4313 4314 if (!ufshcd_is_auto_hibern8_supported(hba)) 4315 return; 4316 4317 spin_lock_irqsave(hba->host->host_lock, flags); 4318 if (hba->ahit != ahit) { 4319 hba->ahit = ahit; 4320 update = true; 4321 } 4322 spin_unlock_irqrestore(hba->host->host_lock, flags); 4323 4324 if (update && 4325 !pm_runtime_suspended(&hba->ufs_device_wlun->sdev_gendev)) { 4326 ufshcd_rpm_get_sync(hba); 4327 ufshcd_hold(hba); 4328 ufshcd_auto_hibern8_enable(hba); 4329 ufshcd_release(hba); 4330 ufshcd_rpm_put_sync(hba); 4331 } 4332 } 4333 EXPORT_SYMBOL_GPL(ufshcd_auto_hibern8_update); 4334 4335 void ufshcd_auto_hibern8_enable(struct ufs_hba *hba) 4336 { 4337 if (!ufshcd_is_auto_hibern8_supported(hba)) 4338 return; 4339 4340 ufshcd_writel(hba, hba->ahit, REG_AUTO_HIBERNATE_IDLE_TIMER); 4341 } 4342 4343 /** 4344 * ufshcd_init_pwr_info - setting the POR (power on reset) 4345 * values in hba power info 4346 * @hba: per-adapter instance 4347 */ 4348 static void ufshcd_init_pwr_info(struct ufs_hba *hba) 4349 { 4350 hba->pwr_info.gear_rx = UFS_PWM_G1; 4351 hba->pwr_info.gear_tx = UFS_PWM_G1; 4352 hba->pwr_info.lane_rx = UFS_LANE_1; 4353 hba->pwr_info.lane_tx = UFS_LANE_1; 4354 hba->pwr_info.pwr_rx = SLOWAUTO_MODE; 4355 hba->pwr_info.pwr_tx = SLOWAUTO_MODE; 4356 hba->pwr_info.hs_rate = 0; 4357 } 4358 4359 /** 4360 * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device 4361 * @hba: per-adapter instance 4362 * 4363 * Return: 0 upon success; < 0 upon failure. 4364 */ 4365 static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba) 4366 { 4367 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info; 4368 4369 if (hba->max_pwr_info.is_valid) 4370 return 0; 4371 4372 if (hba->quirks & UFSHCD_QUIRK_HIBERN_FASTAUTO) { 4373 pwr_info->pwr_tx = FASTAUTO_MODE; 4374 pwr_info->pwr_rx = FASTAUTO_MODE; 4375 } else { 4376 pwr_info->pwr_tx = FAST_MODE; 4377 pwr_info->pwr_rx = FAST_MODE; 4378 } 4379 pwr_info->hs_rate = PA_HS_MODE_B; 4380 4381 /* Get the connected lane count */ 4382 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES), 4383 &pwr_info->lane_rx); 4384 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 4385 &pwr_info->lane_tx); 4386 4387 if (!pwr_info->lane_rx || !pwr_info->lane_tx) { 4388 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n", 4389 __func__, 4390 pwr_info->lane_rx, 4391 pwr_info->lane_tx); 4392 return -EINVAL; 4393 } 4394 4395 /* 4396 * First, get the maximum gears of HS speed. 4397 * If a zero value, it means there is no HSGEAR capability. 4398 * Then, get the maximum gears of PWM speed. 4399 */ 4400 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx); 4401 if (!pwr_info->gear_rx) { 4402 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR), 4403 &pwr_info->gear_rx); 4404 if (!pwr_info->gear_rx) { 4405 dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n", 4406 __func__, pwr_info->gear_rx); 4407 return -EINVAL; 4408 } 4409 pwr_info->pwr_rx = SLOW_MODE; 4410 } 4411 4412 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), 4413 &pwr_info->gear_tx); 4414 if (!pwr_info->gear_tx) { 4415 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR), 4416 &pwr_info->gear_tx); 4417 if (!pwr_info->gear_tx) { 4418 dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n", 4419 __func__, pwr_info->gear_tx); 4420 return -EINVAL; 4421 } 4422 pwr_info->pwr_tx = SLOW_MODE; 4423 } 4424 4425 hba->max_pwr_info.is_valid = true; 4426 return 0; 4427 } 4428 4429 static int ufshcd_change_power_mode(struct ufs_hba *hba, 4430 struct ufs_pa_layer_attr *pwr_mode) 4431 { 4432 int ret; 4433 4434 /* if already configured to the requested pwr_mode */ 4435 if (!hba->force_pmc && 4436 pwr_mode->gear_rx == hba->pwr_info.gear_rx && 4437 pwr_mode->gear_tx == hba->pwr_info.gear_tx && 4438 pwr_mode->lane_rx == hba->pwr_info.lane_rx && 4439 pwr_mode->lane_tx == hba->pwr_info.lane_tx && 4440 pwr_mode->pwr_rx == hba->pwr_info.pwr_rx && 4441 pwr_mode->pwr_tx == hba->pwr_info.pwr_tx && 4442 pwr_mode->hs_rate == hba->pwr_info.hs_rate) { 4443 dev_dbg(hba->dev, "%s: power already configured\n", __func__); 4444 return 0; 4445 } 4446 4447 /* 4448 * Configure attributes for power mode change with below. 4449 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION, 4450 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION, 4451 * - PA_HSSERIES 4452 */ 4453 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx); 4454 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES), 4455 pwr_mode->lane_rx); 4456 if (pwr_mode->pwr_rx == FASTAUTO_MODE || 4457 pwr_mode->pwr_rx == FAST_MODE) 4458 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), true); 4459 else 4460 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), false); 4461 4462 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx); 4463 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES), 4464 pwr_mode->lane_tx); 4465 if (pwr_mode->pwr_tx == FASTAUTO_MODE || 4466 pwr_mode->pwr_tx == FAST_MODE) 4467 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), true); 4468 else 4469 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), false); 4470 4471 if (pwr_mode->pwr_rx == FASTAUTO_MODE || 4472 pwr_mode->pwr_tx == FASTAUTO_MODE || 4473 pwr_mode->pwr_rx == FAST_MODE || 4474 pwr_mode->pwr_tx == FAST_MODE) 4475 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES), 4476 pwr_mode->hs_rate); 4477 4478 if (!(hba->quirks & UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING)) { 4479 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 4480 DL_FC0ProtectionTimeOutVal_Default); 4481 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 4482 DL_TC0ReplayTimeOutVal_Default); 4483 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 4484 DL_AFC0ReqTimeOutVal_Default); 4485 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA3), 4486 DL_FC1ProtectionTimeOutVal_Default); 4487 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA4), 4488 DL_TC1ReplayTimeOutVal_Default); 4489 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA5), 4490 DL_AFC1ReqTimeOutVal_Default); 4491 4492 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalFC0ProtectionTimeOutVal), 4493 DL_FC0ProtectionTimeOutVal_Default); 4494 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalTC0ReplayTimeOutVal), 4495 DL_TC0ReplayTimeOutVal_Default); 4496 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalAFC0ReqTimeOutVal), 4497 DL_AFC0ReqTimeOutVal_Default); 4498 } 4499 4500 ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4 4501 | pwr_mode->pwr_tx); 4502 4503 if (ret) { 4504 dev_err(hba->dev, 4505 "%s: power mode change failed %d\n", __func__, ret); 4506 } else { 4507 ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL, 4508 pwr_mode); 4509 4510 memcpy(&hba->pwr_info, pwr_mode, 4511 sizeof(struct ufs_pa_layer_attr)); 4512 } 4513 4514 return ret; 4515 } 4516 4517 /** 4518 * ufshcd_config_pwr_mode - configure a new power mode 4519 * @hba: per-adapter instance 4520 * @desired_pwr_mode: desired power configuration 4521 * 4522 * Return: 0 upon success; < 0 upon failure. 4523 */ 4524 int ufshcd_config_pwr_mode(struct ufs_hba *hba, 4525 struct ufs_pa_layer_attr *desired_pwr_mode) 4526 { 4527 struct ufs_pa_layer_attr final_params = { 0 }; 4528 int ret; 4529 4530 ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE, 4531 desired_pwr_mode, &final_params); 4532 4533 if (ret) 4534 memcpy(&final_params, desired_pwr_mode, sizeof(final_params)); 4535 4536 ret = ufshcd_change_power_mode(hba, &final_params); 4537 4538 return ret; 4539 } 4540 EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode); 4541 4542 /** 4543 * ufshcd_complete_dev_init() - checks device readiness 4544 * @hba: per-adapter instance 4545 * 4546 * Set fDeviceInit flag and poll until device toggles it. 4547 * 4548 * Return: 0 upon success; < 0 upon failure. 4549 */ 4550 static int ufshcd_complete_dev_init(struct ufs_hba *hba) 4551 { 4552 int err; 4553 bool flag_res = true; 4554 ktime_t timeout; 4555 4556 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG, 4557 QUERY_FLAG_IDN_FDEVICEINIT, 0, NULL); 4558 if (err) { 4559 dev_err(hba->dev, 4560 "%s: setting fDeviceInit flag failed with error %d\n", 4561 __func__, err); 4562 goto out; 4563 } 4564 4565 /* Poll fDeviceInit flag to be cleared */ 4566 timeout = ktime_add_ms(ktime_get(), FDEVICEINIT_COMPL_TIMEOUT); 4567 do { 4568 err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_READ_FLAG, 4569 QUERY_FLAG_IDN_FDEVICEINIT, 0, &flag_res); 4570 if (!flag_res) 4571 break; 4572 usleep_range(500, 1000); 4573 } while (ktime_before(ktime_get(), timeout)); 4574 4575 if (err) { 4576 dev_err(hba->dev, 4577 "%s: reading fDeviceInit flag failed with error %d\n", 4578 __func__, err); 4579 } else if (flag_res) { 4580 dev_err(hba->dev, 4581 "%s: fDeviceInit was not cleared by the device\n", 4582 __func__); 4583 err = -EBUSY; 4584 } 4585 out: 4586 return err; 4587 } 4588 4589 /** 4590 * ufshcd_make_hba_operational - Make UFS controller operational 4591 * @hba: per adapter instance 4592 * 4593 * To bring UFS host controller to operational state, 4594 * 1. Enable required interrupts 4595 * 2. Configure interrupt aggregation 4596 * 3. Program UTRL and UTMRL base address 4597 * 4. Configure run-stop-registers 4598 * 4599 * Return: 0 on success, non-zero value on failure. 4600 */ 4601 int ufshcd_make_hba_operational(struct ufs_hba *hba) 4602 { 4603 int err = 0; 4604 u32 reg; 4605 4606 /* Enable required interrupts */ 4607 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS); 4608 4609 /* Configure interrupt aggregation */ 4610 if (ufshcd_is_intr_aggr_allowed(hba)) 4611 ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO); 4612 else 4613 ufshcd_disable_intr_aggr(hba); 4614 4615 /* Configure UTRL and UTMRL base address registers */ 4616 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr), 4617 REG_UTP_TRANSFER_REQ_LIST_BASE_L); 4618 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr), 4619 REG_UTP_TRANSFER_REQ_LIST_BASE_H); 4620 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr), 4621 REG_UTP_TASK_REQ_LIST_BASE_L); 4622 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr), 4623 REG_UTP_TASK_REQ_LIST_BASE_H); 4624 4625 /* 4626 * Make sure base address and interrupt setup are updated before 4627 * enabling the run/stop registers below. 4628 */ 4629 wmb(); 4630 4631 /* 4632 * UCRDY, UTMRLDY and UTRLRDY bits must be 1 4633 */ 4634 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS); 4635 if (!(ufshcd_get_lists_status(reg))) { 4636 ufshcd_enable_run_stop_reg(hba); 4637 } else { 4638 dev_err(hba->dev, 4639 "Host controller not ready to process requests"); 4640 err = -EIO; 4641 } 4642 4643 return err; 4644 } 4645 EXPORT_SYMBOL_GPL(ufshcd_make_hba_operational); 4646 4647 /** 4648 * ufshcd_hba_stop - Send controller to reset state 4649 * @hba: per adapter instance 4650 */ 4651 void ufshcd_hba_stop(struct ufs_hba *hba) 4652 { 4653 unsigned long flags; 4654 int err; 4655 4656 /* 4657 * Obtain the host lock to prevent that the controller is disabled 4658 * while the UFS interrupt handler is active on another CPU. 4659 */ 4660 spin_lock_irqsave(hba->host->host_lock, flags); 4661 ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE); 4662 spin_unlock_irqrestore(hba->host->host_lock, flags); 4663 4664 err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE, 4665 CONTROLLER_ENABLE, CONTROLLER_DISABLE, 4666 10, 1); 4667 if (err) 4668 dev_err(hba->dev, "%s: Controller disable failed\n", __func__); 4669 } 4670 EXPORT_SYMBOL_GPL(ufshcd_hba_stop); 4671 4672 /** 4673 * ufshcd_hba_execute_hce - initialize the controller 4674 * @hba: per adapter instance 4675 * 4676 * The controller resets itself and controller firmware initialization 4677 * sequence kicks off. When controller is ready it will set 4678 * the Host Controller Enable bit to 1. 4679 * 4680 * Return: 0 on success, non-zero value on failure. 4681 */ 4682 static int ufshcd_hba_execute_hce(struct ufs_hba *hba) 4683 { 4684 int retry_outer = 3; 4685 int retry_inner; 4686 4687 start: 4688 if (ufshcd_is_hba_active(hba)) 4689 /* change controller state to "reset state" */ 4690 ufshcd_hba_stop(hba); 4691 4692 /* UniPro link is disabled at this point */ 4693 ufshcd_set_link_off(hba); 4694 4695 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE); 4696 4697 /* start controller initialization sequence */ 4698 ufshcd_hba_start(hba); 4699 4700 /* 4701 * To initialize a UFS host controller HCE bit must be set to 1. 4702 * During initialization the HCE bit value changes from 1->0->1. 4703 * When the host controller completes initialization sequence 4704 * it sets the value of HCE bit to 1. The same HCE bit is read back 4705 * to check if the controller has completed initialization sequence. 4706 * So without this delay the value HCE = 1, set in the previous 4707 * instruction might be read back. 4708 * This delay can be changed based on the controller. 4709 */ 4710 ufshcd_delay_us(hba->vps->hba_enable_delay_us, 100); 4711 4712 /* wait for the host controller to complete initialization */ 4713 retry_inner = 50; 4714 while (!ufshcd_is_hba_active(hba)) { 4715 if (retry_inner) { 4716 retry_inner--; 4717 } else { 4718 dev_err(hba->dev, 4719 "Controller enable failed\n"); 4720 if (retry_outer) { 4721 retry_outer--; 4722 goto start; 4723 } 4724 return -EIO; 4725 } 4726 usleep_range(1000, 1100); 4727 } 4728 4729 /* enable UIC related interrupts */ 4730 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK); 4731 4732 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE); 4733 4734 return 0; 4735 } 4736 4737 int ufshcd_hba_enable(struct ufs_hba *hba) 4738 { 4739 int ret; 4740 4741 if (hba->quirks & UFSHCI_QUIRK_BROKEN_HCE) { 4742 ufshcd_set_link_off(hba); 4743 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE); 4744 4745 /* enable UIC related interrupts */ 4746 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK); 4747 ret = ufshcd_dme_reset(hba); 4748 if (ret) { 4749 dev_err(hba->dev, "DME_RESET failed\n"); 4750 return ret; 4751 } 4752 4753 ret = ufshcd_dme_enable(hba); 4754 if (ret) { 4755 dev_err(hba->dev, "Enabling DME failed\n"); 4756 return ret; 4757 } 4758 4759 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE); 4760 } else { 4761 ret = ufshcd_hba_execute_hce(hba); 4762 } 4763 4764 return ret; 4765 } 4766 EXPORT_SYMBOL_GPL(ufshcd_hba_enable); 4767 4768 static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer) 4769 { 4770 int tx_lanes = 0, i, err = 0; 4771 4772 if (!peer) 4773 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 4774 &tx_lanes); 4775 else 4776 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 4777 &tx_lanes); 4778 for (i = 0; i < tx_lanes; i++) { 4779 if (!peer) 4780 err = ufshcd_dme_set(hba, 4781 UIC_ARG_MIB_SEL(TX_LCC_ENABLE, 4782 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)), 4783 0); 4784 else 4785 err = ufshcd_dme_peer_set(hba, 4786 UIC_ARG_MIB_SEL(TX_LCC_ENABLE, 4787 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)), 4788 0); 4789 if (err) { 4790 dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d", 4791 __func__, peer, i, err); 4792 break; 4793 } 4794 } 4795 4796 return err; 4797 } 4798 4799 static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba) 4800 { 4801 return ufshcd_disable_tx_lcc(hba, true); 4802 } 4803 4804 void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val) 4805 { 4806 struct ufs_event_hist *e; 4807 4808 if (id >= UFS_EVT_CNT) 4809 return; 4810 4811 e = &hba->ufs_stats.event[id]; 4812 e->val[e->pos] = val; 4813 e->tstamp[e->pos] = local_clock(); 4814 e->cnt += 1; 4815 e->pos = (e->pos + 1) % UFS_EVENT_HIST_LENGTH; 4816 4817 ufshcd_vops_event_notify(hba, id, &val); 4818 } 4819 EXPORT_SYMBOL_GPL(ufshcd_update_evt_hist); 4820 4821 /** 4822 * ufshcd_link_startup - Initialize unipro link startup 4823 * @hba: per adapter instance 4824 * 4825 * Return: 0 for success, non-zero in case of failure. 4826 */ 4827 static int ufshcd_link_startup(struct ufs_hba *hba) 4828 { 4829 int ret; 4830 int retries = DME_LINKSTARTUP_RETRIES; 4831 bool link_startup_again = false; 4832 4833 /* 4834 * If UFS device isn't active then we will have to issue link startup 4835 * 2 times to make sure the device state move to active. 4836 */ 4837 if (!ufshcd_is_ufs_dev_active(hba)) 4838 link_startup_again = true; 4839 4840 link_startup: 4841 do { 4842 ufshcd_vops_link_startup_notify(hba, PRE_CHANGE); 4843 4844 ret = ufshcd_dme_link_startup(hba); 4845 4846 /* check if device is detected by inter-connect layer */ 4847 if (!ret && !ufshcd_is_device_present(hba)) { 4848 ufshcd_update_evt_hist(hba, 4849 UFS_EVT_LINK_STARTUP_FAIL, 4850 0); 4851 dev_err(hba->dev, "%s: Device not present\n", __func__); 4852 ret = -ENXIO; 4853 goto out; 4854 } 4855 4856 /* 4857 * DME link lost indication is only received when link is up, 4858 * but we can't be sure if the link is up until link startup 4859 * succeeds. So reset the local Uni-Pro and try again. 4860 */ 4861 if (ret && retries && ufshcd_hba_enable(hba)) { 4862 ufshcd_update_evt_hist(hba, 4863 UFS_EVT_LINK_STARTUP_FAIL, 4864 (u32)ret); 4865 goto out; 4866 } 4867 } while (ret && retries--); 4868 4869 if (ret) { 4870 /* failed to get the link up... retire */ 4871 ufshcd_update_evt_hist(hba, 4872 UFS_EVT_LINK_STARTUP_FAIL, 4873 (u32)ret); 4874 goto out; 4875 } 4876 4877 if (link_startup_again) { 4878 link_startup_again = false; 4879 retries = DME_LINKSTARTUP_RETRIES; 4880 goto link_startup; 4881 } 4882 4883 /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */ 4884 ufshcd_init_pwr_info(hba); 4885 ufshcd_print_pwr_info(hba); 4886 4887 if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) { 4888 ret = ufshcd_disable_device_tx_lcc(hba); 4889 if (ret) 4890 goto out; 4891 } 4892 4893 /* Include any host controller configuration via UIC commands */ 4894 ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE); 4895 if (ret) 4896 goto out; 4897 4898 /* Clear UECPA once due to LINERESET has happened during LINK_STARTUP */ 4899 ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER); 4900 ret = ufshcd_make_hba_operational(hba); 4901 out: 4902 if (ret) { 4903 dev_err(hba->dev, "link startup failed %d\n", ret); 4904 ufshcd_print_host_state(hba); 4905 ufshcd_print_pwr_info(hba); 4906 ufshcd_print_evt_hist(hba); 4907 } 4908 return ret; 4909 } 4910 4911 /** 4912 * ufshcd_verify_dev_init() - Verify device initialization 4913 * @hba: per-adapter instance 4914 * 4915 * Send NOP OUT UPIU and wait for NOP IN response to check whether the 4916 * device Transport Protocol (UTP) layer is ready after a reset. 4917 * If the UTP layer at the device side is not initialized, it may 4918 * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT 4919 * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations. 4920 * 4921 * Return: 0 upon success; < 0 upon failure. 4922 */ 4923 static int ufshcd_verify_dev_init(struct ufs_hba *hba) 4924 { 4925 int err = 0; 4926 int retries; 4927 4928 ufshcd_hold(hba); 4929 mutex_lock(&hba->dev_cmd.lock); 4930 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) { 4931 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP, 4932 hba->nop_out_timeout); 4933 4934 if (!err || err == -ETIMEDOUT) 4935 break; 4936 4937 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err); 4938 } 4939 mutex_unlock(&hba->dev_cmd.lock); 4940 ufshcd_release(hba); 4941 4942 if (err) 4943 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err); 4944 return err; 4945 } 4946 4947 /** 4948 * ufshcd_setup_links - associate link b/w device wlun and other luns 4949 * @sdev: pointer to SCSI device 4950 * @hba: pointer to ufs hba 4951 */ 4952 static void ufshcd_setup_links(struct ufs_hba *hba, struct scsi_device *sdev) 4953 { 4954 struct device_link *link; 4955 4956 /* 4957 * Device wlun is the supplier & rest of the luns are consumers. 4958 * This ensures that device wlun suspends after all other luns. 4959 */ 4960 if (hba->ufs_device_wlun) { 4961 link = device_link_add(&sdev->sdev_gendev, 4962 &hba->ufs_device_wlun->sdev_gendev, 4963 DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE); 4964 if (!link) { 4965 dev_err(&sdev->sdev_gendev, "Failed establishing link - %s\n", 4966 dev_name(&hba->ufs_device_wlun->sdev_gendev)); 4967 return; 4968 } 4969 hba->luns_avail--; 4970 /* Ignore REPORT_LUN wlun probing */ 4971 if (hba->luns_avail == 1) { 4972 ufshcd_rpm_put(hba); 4973 return; 4974 } 4975 } else { 4976 /* 4977 * Device wlun is probed. The assumption is that WLUNs are 4978 * scanned before other LUNs. 4979 */ 4980 hba->luns_avail--; 4981 } 4982 } 4983 4984 /** 4985 * ufshcd_lu_init - Initialize the relevant parameters of the LU 4986 * @hba: per-adapter instance 4987 * @sdev: pointer to SCSI device 4988 */ 4989 static void ufshcd_lu_init(struct ufs_hba *hba, struct scsi_device *sdev) 4990 { 4991 int len = QUERY_DESC_MAX_SIZE; 4992 u8 lun = ufshcd_scsi_to_upiu_lun(sdev->lun); 4993 u8 lun_qdepth = hba->nutrs; 4994 u8 *desc_buf; 4995 int ret; 4996 4997 desc_buf = kzalloc(len, GFP_KERNEL); 4998 if (!desc_buf) 4999 goto set_qdepth; 5000 5001 ret = ufshcd_read_unit_desc_param(hba, lun, 0, desc_buf, len); 5002 if (ret < 0) { 5003 if (ret == -EOPNOTSUPP) 5004 /* If LU doesn't support unit descriptor, its queue depth is set to 1 */ 5005 lun_qdepth = 1; 5006 kfree(desc_buf); 5007 goto set_qdepth; 5008 } 5009 5010 if (desc_buf[UNIT_DESC_PARAM_LU_Q_DEPTH]) { 5011 /* 5012 * In per-LU queueing architecture, bLUQueueDepth will not be 0, then we will 5013 * use the smaller between UFSHCI CAP.NUTRS and UFS LU bLUQueueDepth 5014 */ 5015 lun_qdepth = min_t(int, desc_buf[UNIT_DESC_PARAM_LU_Q_DEPTH], hba->nutrs); 5016 } 5017 /* 5018 * According to UFS device specification, the write protection mode is only supported by 5019 * normal LU, not supported by WLUN. 5020 */ 5021 if (hba->dev_info.f_power_on_wp_en && lun < hba->dev_info.max_lu_supported && 5022 !hba->dev_info.is_lu_power_on_wp && 5023 desc_buf[UNIT_DESC_PARAM_LU_WR_PROTECT] == UFS_LU_POWER_ON_WP) 5024 hba->dev_info.is_lu_power_on_wp = true; 5025 5026 /* In case of RPMB LU, check if advanced RPMB mode is enabled */ 5027 if (desc_buf[UNIT_DESC_PARAM_UNIT_INDEX] == UFS_UPIU_RPMB_WLUN && 5028 desc_buf[RPMB_UNIT_DESC_PARAM_REGION_EN] & BIT(4)) 5029 hba->dev_info.b_advanced_rpmb_en = true; 5030 5031 5032 kfree(desc_buf); 5033 set_qdepth: 5034 /* 5035 * For WLUNs that don't support unit descriptor, queue depth is set to 1. For LUs whose 5036 * bLUQueueDepth == 0, the queue depth is set to a maximum value that host can queue. 5037 */ 5038 dev_dbg(hba->dev, "Set LU %x queue depth %d\n", lun, lun_qdepth); 5039 scsi_change_queue_depth(sdev, lun_qdepth); 5040 } 5041 5042 /** 5043 * ufshcd_slave_alloc - handle initial SCSI device configurations 5044 * @sdev: pointer to SCSI device 5045 * 5046 * Return: success. 5047 */ 5048 static int ufshcd_slave_alloc(struct scsi_device *sdev) 5049 { 5050 struct ufs_hba *hba; 5051 5052 hba = shost_priv(sdev->host); 5053 5054 /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */ 5055 sdev->use_10_for_ms = 1; 5056 5057 /* DBD field should be set to 1 in mode sense(10) */ 5058 sdev->set_dbd_for_ms = 1; 5059 5060 /* allow SCSI layer to restart the device in case of errors */ 5061 sdev->allow_restart = 1; 5062 5063 /* REPORT SUPPORTED OPERATION CODES is not supported */ 5064 sdev->no_report_opcodes = 1; 5065 5066 /* WRITE_SAME command is not supported */ 5067 sdev->no_write_same = 1; 5068 5069 ufshcd_lu_init(hba, sdev); 5070 5071 ufshcd_setup_links(hba, sdev); 5072 5073 return 0; 5074 } 5075 5076 /** 5077 * ufshcd_change_queue_depth - change queue depth 5078 * @sdev: pointer to SCSI device 5079 * @depth: required depth to set 5080 * 5081 * Change queue depth and make sure the max. limits are not crossed. 5082 * 5083 * Return: new queue depth. 5084 */ 5085 static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth) 5086 { 5087 return scsi_change_queue_depth(sdev, min(depth, sdev->host->can_queue)); 5088 } 5089 5090 /** 5091 * ufshcd_slave_configure - adjust SCSI device configurations 5092 * @sdev: pointer to SCSI device 5093 * 5094 * Return: 0 (success). 5095 */ 5096 static int ufshcd_slave_configure(struct scsi_device *sdev) 5097 { 5098 struct ufs_hba *hba = shost_priv(sdev->host); 5099 struct request_queue *q = sdev->request_queue; 5100 5101 blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1); 5102 if (hba->quirks & UFSHCD_QUIRK_4KB_DMA_ALIGNMENT) 5103 blk_queue_update_dma_alignment(q, SZ_4K - 1); 5104 /* 5105 * Block runtime-pm until all consumers are added. 5106 * Refer ufshcd_setup_links(). 5107 */ 5108 if (is_device_wlun(sdev)) 5109 pm_runtime_get_noresume(&sdev->sdev_gendev); 5110 else if (ufshcd_is_rpm_autosuspend_allowed(hba)) 5111 sdev->rpm_autosuspend = 1; 5112 /* 5113 * Do not print messages during runtime PM to avoid never-ending cycles 5114 * of messages written back to storage by user space causing runtime 5115 * resume, causing more messages and so on. 5116 */ 5117 sdev->silence_suspend = 1; 5118 5119 ufshcd_crypto_register(hba, q); 5120 5121 return 0; 5122 } 5123 5124 /** 5125 * ufshcd_slave_destroy - remove SCSI device configurations 5126 * @sdev: pointer to SCSI device 5127 */ 5128 static void ufshcd_slave_destroy(struct scsi_device *sdev) 5129 { 5130 struct ufs_hba *hba; 5131 unsigned long flags; 5132 5133 hba = shost_priv(sdev->host); 5134 5135 /* Drop the reference as it won't be needed anymore */ 5136 if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) { 5137 spin_lock_irqsave(hba->host->host_lock, flags); 5138 hba->ufs_device_wlun = NULL; 5139 spin_unlock_irqrestore(hba->host->host_lock, flags); 5140 } else if (hba->ufs_device_wlun) { 5141 struct device *supplier = NULL; 5142 5143 /* Ensure UFS Device WLUN exists and does not disappear */ 5144 spin_lock_irqsave(hba->host->host_lock, flags); 5145 if (hba->ufs_device_wlun) { 5146 supplier = &hba->ufs_device_wlun->sdev_gendev; 5147 get_device(supplier); 5148 } 5149 spin_unlock_irqrestore(hba->host->host_lock, flags); 5150 5151 if (supplier) { 5152 /* 5153 * If a LUN fails to probe (e.g. absent BOOT WLUN), the 5154 * device will not have been registered but can still 5155 * have a device link holding a reference to the device. 5156 */ 5157 device_link_remove(&sdev->sdev_gendev, supplier); 5158 put_device(supplier); 5159 } 5160 } 5161 } 5162 5163 /** 5164 * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status 5165 * @lrbp: pointer to local reference block of completed command 5166 * @scsi_status: SCSI command status 5167 * 5168 * Return: value base on SCSI command status. 5169 */ 5170 static inline int 5171 ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status) 5172 { 5173 int result = 0; 5174 5175 switch (scsi_status) { 5176 case SAM_STAT_CHECK_CONDITION: 5177 ufshcd_copy_sense_data(lrbp); 5178 fallthrough; 5179 case SAM_STAT_GOOD: 5180 result |= DID_OK << 16 | scsi_status; 5181 break; 5182 case SAM_STAT_TASK_SET_FULL: 5183 case SAM_STAT_BUSY: 5184 case SAM_STAT_TASK_ABORTED: 5185 ufshcd_copy_sense_data(lrbp); 5186 result |= scsi_status; 5187 break; 5188 default: 5189 result |= DID_ERROR << 16; 5190 break; 5191 } /* end of switch */ 5192 5193 return result; 5194 } 5195 5196 /** 5197 * ufshcd_transfer_rsp_status - Get overall status of the response 5198 * @hba: per adapter instance 5199 * @lrbp: pointer to local reference block of completed command 5200 * @cqe: pointer to the completion queue entry 5201 * 5202 * Return: result of the command to notify SCSI midlayer. 5203 */ 5204 static inline int 5205 ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, 5206 struct cq_entry *cqe) 5207 { 5208 int result = 0; 5209 int scsi_status; 5210 enum utp_ocs ocs; 5211 u8 upiu_flags; 5212 u32 resid; 5213 5214 upiu_flags = lrbp->ucd_rsp_ptr->header.flags; 5215 resid = be32_to_cpu(lrbp->ucd_rsp_ptr->sr.residual_transfer_count); 5216 /* 5217 * Test !overflow instead of underflow to support UFS devices that do 5218 * not set either flag. 5219 */ 5220 if (resid && !(upiu_flags & UPIU_RSP_FLAG_OVERFLOW)) 5221 scsi_set_resid(lrbp->cmd, resid); 5222 5223 /* overall command status of utrd */ 5224 ocs = ufshcd_get_tr_ocs(lrbp, cqe); 5225 5226 if (hba->quirks & UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR) { 5227 if (lrbp->ucd_rsp_ptr->header.response || 5228 lrbp->ucd_rsp_ptr->header.status) 5229 ocs = OCS_SUCCESS; 5230 } 5231 5232 switch (ocs) { 5233 case OCS_SUCCESS: 5234 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0); 5235 switch (ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr)) { 5236 case UPIU_TRANSACTION_RESPONSE: 5237 /* 5238 * get the result based on SCSI status response 5239 * to notify the SCSI midlayer of the command status 5240 */ 5241 scsi_status = lrbp->ucd_rsp_ptr->header.status; 5242 result = ufshcd_scsi_cmd_status(lrbp, scsi_status); 5243 5244 /* 5245 * Currently we are only supporting BKOPs exception 5246 * events hence we can ignore BKOPs exception event 5247 * during power management callbacks. BKOPs exception 5248 * event is not expected to be raised in runtime suspend 5249 * callback as it allows the urgent bkops. 5250 * During system suspend, we are anyway forcefully 5251 * disabling the bkops and if urgent bkops is needed 5252 * it will be enabled on system resume. Long term 5253 * solution could be to abort the system suspend if 5254 * UFS device needs urgent BKOPs. 5255 */ 5256 if (!hba->pm_op_in_progress && 5257 !ufshcd_eh_in_progress(hba) && 5258 ufshcd_is_exception_event(lrbp->ucd_rsp_ptr)) 5259 /* Flushed in suspend */ 5260 schedule_work(&hba->eeh_work); 5261 break; 5262 case UPIU_TRANSACTION_REJECT_UPIU: 5263 /* TODO: handle Reject UPIU Response */ 5264 result = DID_ERROR << 16; 5265 dev_err(hba->dev, 5266 "Reject UPIU not fully implemented\n"); 5267 break; 5268 default: 5269 dev_err(hba->dev, 5270 "Unexpected request response code = %x\n", 5271 result); 5272 result = DID_ERROR << 16; 5273 break; 5274 } 5275 break; 5276 case OCS_ABORTED: 5277 result |= DID_ABORT << 16; 5278 break; 5279 case OCS_INVALID_COMMAND_STATUS: 5280 result |= DID_REQUEUE << 16; 5281 break; 5282 case OCS_INVALID_CMD_TABLE_ATTR: 5283 case OCS_INVALID_PRDT_ATTR: 5284 case OCS_MISMATCH_DATA_BUF_SIZE: 5285 case OCS_MISMATCH_RESP_UPIU_SIZE: 5286 case OCS_PEER_COMM_FAILURE: 5287 case OCS_FATAL_ERROR: 5288 case OCS_DEVICE_FATAL_ERROR: 5289 case OCS_INVALID_CRYPTO_CONFIG: 5290 case OCS_GENERAL_CRYPTO_ERROR: 5291 default: 5292 result |= DID_ERROR << 16; 5293 dev_err(hba->dev, 5294 "OCS error from controller = %x for tag %d\n", 5295 ocs, lrbp->task_tag); 5296 ufshcd_print_evt_hist(hba); 5297 ufshcd_print_host_state(hba); 5298 break; 5299 } /* end of switch */ 5300 5301 if ((host_byte(result) != DID_OK) && 5302 (host_byte(result) != DID_REQUEUE) && !hba->silence_err_logs) 5303 ufshcd_print_tr(hba, lrbp->task_tag, true); 5304 return result; 5305 } 5306 5307 static bool ufshcd_is_auto_hibern8_error(struct ufs_hba *hba, 5308 u32 intr_mask) 5309 { 5310 if (!ufshcd_is_auto_hibern8_supported(hba) || 5311 !ufshcd_is_auto_hibern8_enabled(hba)) 5312 return false; 5313 5314 if (!(intr_mask & UFSHCD_UIC_HIBERN8_MASK)) 5315 return false; 5316 5317 if (hba->active_uic_cmd && 5318 (hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_ENTER || 5319 hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_EXIT)) 5320 return false; 5321 5322 return true; 5323 } 5324 5325 /** 5326 * ufshcd_uic_cmd_compl - handle completion of uic command 5327 * @hba: per adapter instance 5328 * @intr_status: interrupt status generated by the controller 5329 * 5330 * Return: 5331 * IRQ_HANDLED - If interrupt is valid 5332 * IRQ_NONE - If invalid interrupt 5333 */ 5334 static irqreturn_t ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status) 5335 { 5336 irqreturn_t retval = IRQ_NONE; 5337 5338 spin_lock(hba->host->host_lock); 5339 if (ufshcd_is_auto_hibern8_error(hba, intr_status)) 5340 hba->errors |= (UFSHCD_UIC_HIBERN8_MASK & intr_status); 5341 5342 if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) { 5343 hba->active_uic_cmd->argument2 |= 5344 ufshcd_get_uic_cmd_result(hba); 5345 hba->active_uic_cmd->argument3 = 5346 ufshcd_get_dme_attr_val(hba); 5347 if (!hba->uic_async_done) 5348 hba->active_uic_cmd->cmd_active = 0; 5349 complete(&hba->active_uic_cmd->done); 5350 retval = IRQ_HANDLED; 5351 } 5352 5353 if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done) { 5354 hba->active_uic_cmd->cmd_active = 0; 5355 complete(hba->uic_async_done); 5356 retval = IRQ_HANDLED; 5357 } 5358 5359 if (retval == IRQ_HANDLED) 5360 ufshcd_add_uic_command_trace(hba, hba->active_uic_cmd, 5361 UFS_CMD_COMP); 5362 spin_unlock(hba->host->host_lock); 5363 return retval; 5364 } 5365 5366 /* Release the resources allocated for processing a SCSI command. */ 5367 void ufshcd_release_scsi_cmd(struct ufs_hba *hba, 5368 struct ufshcd_lrb *lrbp) 5369 { 5370 struct scsi_cmnd *cmd = lrbp->cmd; 5371 5372 scsi_dma_unmap(cmd); 5373 ufshcd_release(hba); 5374 ufshcd_clk_scaling_update_busy(hba); 5375 } 5376 5377 /** 5378 * ufshcd_compl_one_cqe - handle a completion queue entry 5379 * @hba: per adapter instance 5380 * @task_tag: the task tag of the request to be completed 5381 * @cqe: pointer to the completion queue entry 5382 */ 5383 void ufshcd_compl_one_cqe(struct ufs_hba *hba, int task_tag, 5384 struct cq_entry *cqe) 5385 { 5386 struct ufshcd_lrb *lrbp; 5387 struct scsi_cmnd *cmd; 5388 enum utp_ocs ocs; 5389 5390 lrbp = &hba->lrb[task_tag]; 5391 lrbp->compl_time_stamp = ktime_get(); 5392 cmd = lrbp->cmd; 5393 if (cmd) { 5394 if (unlikely(ufshcd_should_inform_monitor(hba, lrbp))) 5395 ufshcd_update_monitor(hba, lrbp); 5396 ufshcd_add_command_trace(hba, task_tag, UFS_CMD_COMP); 5397 cmd->result = ufshcd_transfer_rsp_status(hba, lrbp, cqe); 5398 ufshcd_release_scsi_cmd(hba, lrbp); 5399 /* Do not touch lrbp after scsi done */ 5400 scsi_done(cmd); 5401 } else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE || 5402 lrbp->command_type == UTP_CMD_TYPE_UFS_STORAGE) { 5403 if (hba->dev_cmd.complete) { 5404 if (cqe) { 5405 ocs = le32_to_cpu(cqe->status) & MASK_OCS; 5406 lrbp->utr_descriptor_ptr->header.ocs = ocs; 5407 } 5408 complete(hba->dev_cmd.complete); 5409 ufshcd_clk_scaling_update_busy(hba); 5410 } 5411 } 5412 } 5413 5414 /** 5415 * __ufshcd_transfer_req_compl - handle SCSI and query command completion 5416 * @hba: per adapter instance 5417 * @completed_reqs: bitmask that indicates which requests to complete 5418 */ 5419 static void __ufshcd_transfer_req_compl(struct ufs_hba *hba, 5420 unsigned long completed_reqs) 5421 { 5422 int tag; 5423 5424 for_each_set_bit(tag, &completed_reqs, hba->nutrs) 5425 ufshcd_compl_one_cqe(hba, tag, NULL); 5426 } 5427 5428 /* Any value that is not an existing queue number is fine for this constant. */ 5429 enum { 5430 UFSHCD_POLL_FROM_INTERRUPT_CONTEXT = -1 5431 }; 5432 5433 static void ufshcd_clear_polled(struct ufs_hba *hba, 5434 unsigned long *completed_reqs) 5435 { 5436 int tag; 5437 5438 for_each_set_bit(tag, completed_reqs, hba->nutrs) { 5439 struct scsi_cmnd *cmd = hba->lrb[tag].cmd; 5440 5441 if (!cmd) 5442 continue; 5443 if (scsi_cmd_to_rq(cmd)->cmd_flags & REQ_POLLED) 5444 __clear_bit(tag, completed_reqs); 5445 } 5446 } 5447 5448 /* 5449 * Return: > 0 if one or more commands have been completed or 0 if no 5450 * requests have been completed. 5451 */ 5452 static int ufshcd_poll(struct Scsi_Host *shost, unsigned int queue_num) 5453 { 5454 struct ufs_hba *hba = shost_priv(shost); 5455 unsigned long completed_reqs, flags; 5456 u32 tr_doorbell; 5457 struct ufs_hw_queue *hwq; 5458 5459 if (is_mcq_enabled(hba)) { 5460 hwq = &hba->uhq[queue_num]; 5461 5462 return ufshcd_mcq_poll_cqe_lock(hba, hwq); 5463 } 5464 5465 spin_lock_irqsave(&hba->outstanding_lock, flags); 5466 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 5467 completed_reqs = ~tr_doorbell & hba->outstanding_reqs; 5468 WARN_ONCE(completed_reqs & ~hba->outstanding_reqs, 5469 "completed: %#lx; outstanding: %#lx\n", completed_reqs, 5470 hba->outstanding_reqs); 5471 if (queue_num == UFSHCD_POLL_FROM_INTERRUPT_CONTEXT) { 5472 /* Do not complete polled requests from interrupt context. */ 5473 ufshcd_clear_polled(hba, &completed_reqs); 5474 } 5475 hba->outstanding_reqs &= ~completed_reqs; 5476 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 5477 5478 if (completed_reqs) 5479 __ufshcd_transfer_req_compl(hba, completed_reqs); 5480 5481 return completed_reqs != 0; 5482 } 5483 5484 /** 5485 * ufshcd_mcq_compl_pending_transfer - MCQ mode function. It is 5486 * invoked from the error handler context or ufshcd_host_reset_and_restore() 5487 * to complete the pending transfers and free the resources associated with 5488 * the scsi command. 5489 * 5490 * @hba: per adapter instance 5491 * @force_compl: This flag is set to true when invoked 5492 * from ufshcd_host_reset_and_restore() in which case it requires special 5493 * handling because the host controller has been reset by ufshcd_hba_stop(). 5494 */ 5495 static void ufshcd_mcq_compl_pending_transfer(struct ufs_hba *hba, 5496 bool force_compl) 5497 { 5498 struct ufs_hw_queue *hwq; 5499 struct ufshcd_lrb *lrbp; 5500 struct scsi_cmnd *cmd; 5501 unsigned long flags; 5502 u32 hwq_num, utag; 5503 int tag; 5504 5505 for (tag = 0; tag < hba->nutrs; tag++) { 5506 lrbp = &hba->lrb[tag]; 5507 cmd = lrbp->cmd; 5508 if (!ufshcd_cmd_inflight(cmd) || 5509 test_bit(SCMD_STATE_COMPLETE, &cmd->state)) 5510 continue; 5511 5512 utag = blk_mq_unique_tag(scsi_cmd_to_rq(cmd)); 5513 hwq_num = blk_mq_unique_tag_to_hwq(utag); 5514 hwq = &hba->uhq[hwq_num]; 5515 5516 if (force_compl) { 5517 ufshcd_mcq_compl_all_cqes_lock(hba, hwq); 5518 /* 5519 * For those cmds of which the cqes are not present 5520 * in the cq, complete them explicitly. 5521 */ 5522 if (cmd && !test_bit(SCMD_STATE_COMPLETE, &cmd->state)) { 5523 spin_lock_irqsave(&hwq->cq_lock, flags); 5524 set_host_byte(cmd, DID_REQUEUE); 5525 ufshcd_release_scsi_cmd(hba, lrbp); 5526 scsi_done(cmd); 5527 spin_unlock_irqrestore(&hwq->cq_lock, flags); 5528 } 5529 } else { 5530 ufshcd_mcq_poll_cqe_lock(hba, hwq); 5531 } 5532 } 5533 } 5534 5535 /** 5536 * ufshcd_transfer_req_compl - handle SCSI and query command completion 5537 * @hba: per adapter instance 5538 * 5539 * Return: 5540 * IRQ_HANDLED - If interrupt is valid 5541 * IRQ_NONE - If invalid interrupt 5542 */ 5543 static irqreturn_t ufshcd_transfer_req_compl(struct ufs_hba *hba) 5544 { 5545 /* Resetting interrupt aggregation counters first and reading the 5546 * DOOR_BELL afterward allows us to handle all the completed requests. 5547 * In order to prevent other interrupts starvation the DB is read once 5548 * after reset. The down side of this solution is the possibility of 5549 * false interrupt if device completes another request after resetting 5550 * aggregation and before reading the DB. 5551 */ 5552 if (ufshcd_is_intr_aggr_allowed(hba) && 5553 !(hba->quirks & UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR)) 5554 ufshcd_reset_intr_aggr(hba); 5555 5556 if (ufs_fail_completion()) 5557 return IRQ_HANDLED; 5558 5559 /* 5560 * Ignore the ufshcd_poll() return value and return IRQ_HANDLED since we 5561 * do not want polling to trigger spurious interrupt complaints. 5562 */ 5563 ufshcd_poll(hba->host, UFSHCD_POLL_FROM_INTERRUPT_CONTEXT); 5564 5565 return IRQ_HANDLED; 5566 } 5567 5568 int __ufshcd_write_ee_control(struct ufs_hba *hba, u32 ee_ctrl_mask) 5569 { 5570 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, 5571 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, 5572 &ee_ctrl_mask); 5573 } 5574 5575 int ufshcd_write_ee_control(struct ufs_hba *hba) 5576 { 5577 int err; 5578 5579 mutex_lock(&hba->ee_ctrl_mutex); 5580 err = __ufshcd_write_ee_control(hba, hba->ee_ctrl_mask); 5581 mutex_unlock(&hba->ee_ctrl_mutex); 5582 if (err) 5583 dev_err(hba->dev, "%s: failed to write ee control %d\n", 5584 __func__, err); 5585 return err; 5586 } 5587 5588 int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask, 5589 const u16 *other_mask, u16 set, u16 clr) 5590 { 5591 u16 new_mask, ee_ctrl_mask; 5592 int err = 0; 5593 5594 mutex_lock(&hba->ee_ctrl_mutex); 5595 new_mask = (*mask & ~clr) | set; 5596 ee_ctrl_mask = new_mask | *other_mask; 5597 if (ee_ctrl_mask != hba->ee_ctrl_mask) 5598 err = __ufshcd_write_ee_control(hba, ee_ctrl_mask); 5599 /* Still need to update 'mask' even if 'ee_ctrl_mask' was unchanged */ 5600 if (!err) { 5601 hba->ee_ctrl_mask = ee_ctrl_mask; 5602 *mask = new_mask; 5603 } 5604 mutex_unlock(&hba->ee_ctrl_mutex); 5605 return err; 5606 } 5607 5608 /** 5609 * ufshcd_disable_ee - disable exception event 5610 * @hba: per-adapter instance 5611 * @mask: exception event to disable 5612 * 5613 * Disables exception event in the device so that the EVENT_ALERT 5614 * bit is not set. 5615 * 5616 * Return: zero on success, non-zero error value on failure. 5617 */ 5618 static inline int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask) 5619 { 5620 return ufshcd_update_ee_drv_mask(hba, 0, mask); 5621 } 5622 5623 /** 5624 * ufshcd_enable_ee - enable exception event 5625 * @hba: per-adapter instance 5626 * @mask: exception event to enable 5627 * 5628 * Enable corresponding exception event in the device to allow 5629 * device to alert host in critical scenarios. 5630 * 5631 * Return: zero on success, non-zero error value on failure. 5632 */ 5633 static inline int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask) 5634 { 5635 return ufshcd_update_ee_drv_mask(hba, mask, 0); 5636 } 5637 5638 /** 5639 * ufshcd_enable_auto_bkops - Allow device managed BKOPS 5640 * @hba: per-adapter instance 5641 * 5642 * Allow device to manage background operations on its own. Enabling 5643 * this might lead to inconsistent latencies during normal data transfers 5644 * as the device is allowed to manage its own way of handling background 5645 * operations. 5646 * 5647 * Return: zero on success, non-zero on failure. 5648 */ 5649 static int ufshcd_enable_auto_bkops(struct ufs_hba *hba) 5650 { 5651 int err = 0; 5652 5653 if (hba->auto_bkops_enabled) 5654 goto out; 5655 5656 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG, 5657 QUERY_FLAG_IDN_BKOPS_EN, 0, NULL); 5658 if (err) { 5659 dev_err(hba->dev, "%s: failed to enable bkops %d\n", 5660 __func__, err); 5661 goto out; 5662 } 5663 5664 hba->auto_bkops_enabled = true; 5665 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Enabled"); 5666 5667 /* No need of URGENT_BKOPS exception from the device */ 5668 err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS); 5669 if (err) 5670 dev_err(hba->dev, "%s: failed to disable exception event %d\n", 5671 __func__, err); 5672 out: 5673 return err; 5674 } 5675 5676 /** 5677 * ufshcd_disable_auto_bkops - block device in doing background operations 5678 * @hba: per-adapter instance 5679 * 5680 * Disabling background operations improves command response latency but 5681 * has drawback of device moving into critical state where the device is 5682 * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the 5683 * host is idle so that BKOPS are managed effectively without any negative 5684 * impacts. 5685 * 5686 * Return: zero on success, non-zero on failure. 5687 */ 5688 static int ufshcd_disable_auto_bkops(struct ufs_hba *hba) 5689 { 5690 int err = 0; 5691 5692 if (!hba->auto_bkops_enabled) 5693 goto out; 5694 5695 /* 5696 * If host assisted BKOPs is to be enabled, make sure 5697 * urgent bkops exception is allowed. 5698 */ 5699 err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS); 5700 if (err) { 5701 dev_err(hba->dev, "%s: failed to enable exception event %d\n", 5702 __func__, err); 5703 goto out; 5704 } 5705 5706 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG, 5707 QUERY_FLAG_IDN_BKOPS_EN, 0, NULL); 5708 if (err) { 5709 dev_err(hba->dev, "%s: failed to disable bkops %d\n", 5710 __func__, err); 5711 ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS); 5712 goto out; 5713 } 5714 5715 hba->auto_bkops_enabled = false; 5716 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Disabled"); 5717 hba->is_urgent_bkops_lvl_checked = false; 5718 out: 5719 return err; 5720 } 5721 5722 /** 5723 * ufshcd_force_reset_auto_bkops - force reset auto bkops state 5724 * @hba: per adapter instance 5725 * 5726 * After a device reset the device may toggle the BKOPS_EN flag 5727 * to default value. The s/w tracking variables should be updated 5728 * as well. This function would change the auto-bkops state based on 5729 * UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND. 5730 */ 5731 static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba) 5732 { 5733 if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) { 5734 hba->auto_bkops_enabled = false; 5735 hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS; 5736 ufshcd_enable_auto_bkops(hba); 5737 } else { 5738 hba->auto_bkops_enabled = true; 5739 hba->ee_ctrl_mask &= ~MASK_EE_URGENT_BKOPS; 5740 ufshcd_disable_auto_bkops(hba); 5741 } 5742 hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT; 5743 hba->is_urgent_bkops_lvl_checked = false; 5744 } 5745 5746 static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status) 5747 { 5748 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 5749 QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status); 5750 } 5751 5752 /** 5753 * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status 5754 * @hba: per-adapter instance 5755 * @status: bkops_status value 5756 * 5757 * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn 5758 * flag in the device to permit background operations if the device 5759 * bkops_status is greater than or equal to "status" argument passed to 5760 * this function, disable otherwise. 5761 * 5762 * Return: 0 for success, non-zero in case of failure. 5763 * 5764 * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag 5765 * to know whether auto bkops is enabled or disabled after this function 5766 * returns control to it. 5767 */ 5768 static int ufshcd_bkops_ctrl(struct ufs_hba *hba, 5769 enum bkops_status status) 5770 { 5771 int err; 5772 u32 curr_status = 0; 5773 5774 err = ufshcd_get_bkops_status(hba, &curr_status); 5775 if (err) { 5776 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n", 5777 __func__, err); 5778 goto out; 5779 } else if (curr_status > BKOPS_STATUS_MAX) { 5780 dev_err(hba->dev, "%s: invalid BKOPS status %d\n", 5781 __func__, curr_status); 5782 err = -EINVAL; 5783 goto out; 5784 } 5785 5786 if (curr_status >= status) 5787 err = ufshcd_enable_auto_bkops(hba); 5788 else 5789 err = ufshcd_disable_auto_bkops(hba); 5790 out: 5791 return err; 5792 } 5793 5794 /** 5795 * ufshcd_urgent_bkops - handle urgent bkops exception event 5796 * @hba: per-adapter instance 5797 * 5798 * Enable fBackgroundOpsEn flag in the device to permit background 5799 * operations. 5800 * 5801 * If BKOPs is enabled, this function returns 0, 1 if the bkops in not enabled 5802 * and negative error value for any other failure. 5803 * 5804 * Return: 0 upon success; < 0 upon failure. 5805 */ 5806 static int ufshcd_urgent_bkops(struct ufs_hba *hba) 5807 { 5808 return ufshcd_bkops_ctrl(hba, hba->urgent_bkops_lvl); 5809 } 5810 5811 static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status) 5812 { 5813 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 5814 QUERY_ATTR_IDN_EE_STATUS, 0, 0, status); 5815 } 5816 5817 static void ufshcd_bkops_exception_event_handler(struct ufs_hba *hba) 5818 { 5819 int err; 5820 u32 curr_status = 0; 5821 5822 if (hba->is_urgent_bkops_lvl_checked) 5823 goto enable_auto_bkops; 5824 5825 err = ufshcd_get_bkops_status(hba, &curr_status); 5826 if (err) { 5827 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n", 5828 __func__, err); 5829 goto out; 5830 } 5831 5832 /* 5833 * We are seeing that some devices are raising the urgent bkops 5834 * exception events even when BKOPS status doesn't indicate performace 5835 * impacted or critical. Handle these device by determining their urgent 5836 * bkops status at runtime. 5837 */ 5838 if (curr_status < BKOPS_STATUS_PERF_IMPACT) { 5839 dev_err(hba->dev, "%s: device raised urgent BKOPS exception for bkops status %d\n", 5840 __func__, curr_status); 5841 /* update the current status as the urgent bkops level */ 5842 hba->urgent_bkops_lvl = curr_status; 5843 hba->is_urgent_bkops_lvl_checked = true; 5844 } 5845 5846 enable_auto_bkops: 5847 err = ufshcd_enable_auto_bkops(hba); 5848 out: 5849 if (err < 0) 5850 dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n", 5851 __func__, err); 5852 } 5853 5854 static void ufshcd_temp_exception_event_handler(struct ufs_hba *hba, u16 status) 5855 { 5856 u32 value; 5857 5858 if (ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 5859 QUERY_ATTR_IDN_CASE_ROUGH_TEMP, 0, 0, &value)) 5860 return; 5861 5862 dev_info(hba->dev, "exception Tcase %d\n", value - 80); 5863 5864 ufs_hwmon_notify_event(hba, status & MASK_EE_URGENT_TEMP); 5865 5866 /* 5867 * A placeholder for the platform vendors to add whatever additional 5868 * steps required 5869 */ 5870 } 5871 5872 static int __ufshcd_wb_toggle(struct ufs_hba *hba, bool set, enum flag_idn idn) 5873 { 5874 u8 index; 5875 enum query_opcode opcode = set ? UPIU_QUERY_OPCODE_SET_FLAG : 5876 UPIU_QUERY_OPCODE_CLEAR_FLAG; 5877 5878 index = ufshcd_wb_get_query_index(hba); 5879 return ufshcd_query_flag_retry(hba, opcode, idn, index, NULL); 5880 } 5881 5882 int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable) 5883 { 5884 int ret; 5885 5886 if (!ufshcd_is_wb_allowed(hba) || 5887 hba->dev_info.wb_enabled == enable) 5888 return 0; 5889 5890 ret = __ufshcd_wb_toggle(hba, enable, QUERY_FLAG_IDN_WB_EN); 5891 if (ret) { 5892 dev_err(hba->dev, "%s: Write Booster %s failed %d\n", 5893 __func__, enable ? "enabling" : "disabling", ret); 5894 return ret; 5895 } 5896 5897 hba->dev_info.wb_enabled = enable; 5898 dev_dbg(hba->dev, "%s: Write Booster %s\n", 5899 __func__, enable ? "enabled" : "disabled"); 5900 5901 return ret; 5902 } 5903 5904 static void ufshcd_wb_toggle_buf_flush_during_h8(struct ufs_hba *hba, 5905 bool enable) 5906 { 5907 int ret; 5908 5909 ret = __ufshcd_wb_toggle(hba, enable, 5910 QUERY_FLAG_IDN_WB_BUFF_FLUSH_DURING_HIBERN8); 5911 if (ret) { 5912 dev_err(hba->dev, "%s: WB-Buf Flush during H8 %s failed %d\n", 5913 __func__, enable ? "enabling" : "disabling", ret); 5914 return; 5915 } 5916 dev_dbg(hba->dev, "%s: WB-Buf Flush during H8 %s\n", 5917 __func__, enable ? "enabled" : "disabled"); 5918 } 5919 5920 int ufshcd_wb_toggle_buf_flush(struct ufs_hba *hba, bool enable) 5921 { 5922 int ret; 5923 5924 if (!ufshcd_is_wb_allowed(hba) || 5925 hba->dev_info.wb_buf_flush_enabled == enable) 5926 return 0; 5927 5928 ret = __ufshcd_wb_toggle(hba, enable, QUERY_FLAG_IDN_WB_BUFF_FLUSH_EN); 5929 if (ret) { 5930 dev_err(hba->dev, "%s: WB-Buf Flush %s failed %d\n", 5931 __func__, enable ? "enabling" : "disabling", ret); 5932 return ret; 5933 } 5934 5935 hba->dev_info.wb_buf_flush_enabled = enable; 5936 dev_dbg(hba->dev, "%s: WB-Buf Flush %s\n", 5937 __func__, enable ? "enabled" : "disabled"); 5938 5939 return ret; 5940 } 5941 5942 static bool ufshcd_wb_presrv_usrspc_keep_vcc_on(struct ufs_hba *hba, 5943 u32 avail_buf) 5944 { 5945 u32 cur_buf; 5946 int ret; 5947 u8 index; 5948 5949 index = ufshcd_wb_get_query_index(hba); 5950 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 5951 QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE, 5952 index, 0, &cur_buf); 5953 if (ret) { 5954 dev_err(hba->dev, "%s: dCurWriteBoosterBufferSize read failed %d\n", 5955 __func__, ret); 5956 return false; 5957 } 5958 5959 if (!cur_buf) { 5960 dev_info(hba->dev, "dCurWBBuf: %d WB disabled until free-space is available\n", 5961 cur_buf); 5962 return false; 5963 } 5964 /* Let it continue to flush when available buffer exceeds threshold */ 5965 return avail_buf < hba->vps->wb_flush_threshold; 5966 } 5967 5968 static void ufshcd_wb_force_disable(struct ufs_hba *hba) 5969 { 5970 if (ufshcd_is_wb_buf_flush_allowed(hba)) 5971 ufshcd_wb_toggle_buf_flush(hba, false); 5972 5973 ufshcd_wb_toggle_buf_flush_during_h8(hba, false); 5974 ufshcd_wb_toggle(hba, false); 5975 hba->caps &= ~UFSHCD_CAP_WB_EN; 5976 5977 dev_info(hba->dev, "%s: WB force disabled\n", __func__); 5978 } 5979 5980 static bool ufshcd_is_wb_buf_lifetime_available(struct ufs_hba *hba) 5981 { 5982 u32 lifetime; 5983 int ret; 5984 u8 index; 5985 5986 index = ufshcd_wb_get_query_index(hba); 5987 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 5988 QUERY_ATTR_IDN_WB_BUFF_LIFE_TIME_EST, 5989 index, 0, &lifetime); 5990 if (ret) { 5991 dev_err(hba->dev, 5992 "%s: bWriteBoosterBufferLifeTimeEst read failed %d\n", 5993 __func__, ret); 5994 return false; 5995 } 5996 5997 if (lifetime == UFS_WB_EXCEED_LIFETIME) { 5998 dev_err(hba->dev, "%s: WB buf lifetime is exhausted 0x%02X\n", 5999 __func__, lifetime); 6000 return false; 6001 } 6002 6003 dev_dbg(hba->dev, "%s: WB buf lifetime is 0x%02X\n", 6004 __func__, lifetime); 6005 6006 return true; 6007 } 6008 6009 static bool ufshcd_wb_need_flush(struct ufs_hba *hba) 6010 { 6011 int ret; 6012 u32 avail_buf; 6013 u8 index; 6014 6015 if (!ufshcd_is_wb_allowed(hba)) 6016 return false; 6017 6018 if (!ufshcd_is_wb_buf_lifetime_available(hba)) { 6019 ufshcd_wb_force_disable(hba); 6020 return false; 6021 } 6022 6023 /* 6024 * The ufs device needs the vcc to be ON to flush. 6025 * With user-space reduction enabled, it's enough to enable flush 6026 * by checking only the available buffer. The threshold 6027 * defined here is > 90% full. 6028 * With user-space preserved enabled, the current-buffer 6029 * should be checked too because the wb buffer size can reduce 6030 * when disk tends to be full. This info is provided by current 6031 * buffer (dCurrentWriteBoosterBufferSize). There's no point in 6032 * keeping vcc on when current buffer is empty. 6033 */ 6034 index = ufshcd_wb_get_query_index(hba); 6035 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 6036 QUERY_ATTR_IDN_AVAIL_WB_BUFF_SIZE, 6037 index, 0, &avail_buf); 6038 if (ret) { 6039 dev_warn(hba->dev, "%s: dAvailableWriteBoosterBufferSize read failed %d\n", 6040 __func__, ret); 6041 return false; 6042 } 6043 6044 if (!hba->dev_info.b_presrv_uspc_en) 6045 return avail_buf <= UFS_WB_BUF_REMAIN_PERCENT(10); 6046 6047 return ufshcd_wb_presrv_usrspc_keep_vcc_on(hba, avail_buf); 6048 } 6049 6050 static void ufshcd_rpm_dev_flush_recheck_work(struct work_struct *work) 6051 { 6052 struct ufs_hba *hba = container_of(to_delayed_work(work), 6053 struct ufs_hba, 6054 rpm_dev_flush_recheck_work); 6055 /* 6056 * To prevent unnecessary VCC power drain after device finishes 6057 * WriteBooster buffer flush or Auto BKOPs, force runtime resume 6058 * after a certain delay to recheck the threshold by next runtime 6059 * suspend. 6060 */ 6061 ufshcd_rpm_get_sync(hba); 6062 ufshcd_rpm_put_sync(hba); 6063 } 6064 6065 /** 6066 * ufshcd_exception_event_handler - handle exceptions raised by device 6067 * @work: pointer to work data 6068 * 6069 * Read bExceptionEventStatus attribute from the device and handle the 6070 * exception event accordingly. 6071 */ 6072 static void ufshcd_exception_event_handler(struct work_struct *work) 6073 { 6074 struct ufs_hba *hba; 6075 int err; 6076 u32 status = 0; 6077 hba = container_of(work, struct ufs_hba, eeh_work); 6078 6079 ufshcd_scsi_block_requests(hba); 6080 err = ufshcd_get_ee_status(hba, &status); 6081 if (err) { 6082 dev_err(hba->dev, "%s: failed to get exception status %d\n", 6083 __func__, err); 6084 goto out; 6085 } 6086 6087 trace_ufshcd_exception_event(dev_name(hba->dev), status); 6088 6089 if (status & hba->ee_drv_mask & MASK_EE_URGENT_BKOPS) 6090 ufshcd_bkops_exception_event_handler(hba); 6091 6092 if (status & hba->ee_drv_mask & MASK_EE_URGENT_TEMP) 6093 ufshcd_temp_exception_event_handler(hba, status); 6094 6095 ufs_debugfs_exception_event(hba, status); 6096 out: 6097 ufshcd_scsi_unblock_requests(hba); 6098 } 6099 6100 /* Complete requests that have door-bell cleared */ 6101 static void ufshcd_complete_requests(struct ufs_hba *hba, bool force_compl) 6102 { 6103 if (is_mcq_enabled(hba)) 6104 ufshcd_mcq_compl_pending_transfer(hba, force_compl); 6105 else 6106 ufshcd_transfer_req_compl(hba); 6107 6108 ufshcd_tmc_handler(hba); 6109 } 6110 6111 /** 6112 * ufshcd_quirk_dl_nac_errors - This function checks if error handling is 6113 * to recover from the DL NAC errors or not. 6114 * @hba: per-adapter instance 6115 * 6116 * Return: true if error handling is required, false otherwise. 6117 */ 6118 static bool ufshcd_quirk_dl_nac_errors(struct ufs_hba *hba) 6119 { 6120 unsigned long flags; 6121 bool err_handling = true; 6122 6123 spin_lock_irqsave(hba->host->host_lock, flags); 6124 /* 6125 * UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS only workaround the 6126 * device fatal error and/or DL NAC & REPLAY timeout errors. 6127 */ 6128 if (hba->saved_err & (CONTROLLER_FATAL_ERROR | SYSTEM_BUS_FATAL_ERROR)) 6129 goto out; 6130 6131 if ((hba->saved_err & DEVICE_FATAL_ERROR) || 6132 ((hba->saved_err & UIC_ERROR) && 6133 (hba->saved_uic_err & UFSHCD_UIC_DL_TCx_REPLAY_ERROR))) 6134 goto out; 6135 6136 if ((hba->saved_err & UIC_ERROR) && 6137 (hba->saved_uic_err & UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)) { 6138 int err; 6139 /* 6140 * wait for 50ms to see if we can get any other errors or not. 6141 */ 6142 spin_unlock_irqrestore(hba->host->host_lock, flags); 6143 msleep(50); 6144 spin_lock_irqsave(hba->host->host_lock, flags); 6145 6146 /* 6147 * now check if we have got any other severe errors other than 6148 * DL NAC error? 6149 */ 6150 if ((hba->saved_err & INT_FATAL_ERRORS) || 6151 ((hba->saved_err & UIC_ERROR) && 6152 (hba->saved_uic_err & ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR))) 6153 goto out; 6154 6155 /* 6156 * As DL NAC is the only error received so far, send out NOP 6157 * command to confirm if link is still active or not. 6158 * - If we don't get any response then do error recovery. 6159 * - If we get response then clear the DL NAC error bit. 6160 */ 6161 6162 spin_unlock_irqrestore(hba->host->host_lock, flags); 6163 err = ufshcd_verify_dev_init(hba); 6164 spin_lock_irqsave(hba->host->host_lock, flags); 6165 6166 if (err) 6167 goto out; 6168 6169 /* Link seems to be alive hence ignore the DL NAC errors */ 6170 if (hba->saved_uic_err == UFSHCD_UIC_DL_NAC_RECEIVED_ERROR) 6171 hba->saved_err &= ~UIC_ERROR; 6172 /* clear NAC error */ 6173 hba->saved_uic_err &= ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR; 6174 if (!hba->saved_uic_err) 6175 err_handling = false; 6176 } 6177 out: 6178 spin_unlock_irqrestore(hba->host->host_lock, flags); 6179 return err_handling; 6180 } 6181 6182 /* host lock must be held before calling this func */ 6183 static inline bool ufshcd_is_saved_err_fatal(struct ufs_hba *hba) 6184 { 6185 return (hba->saved_uic_err & UFSHCD_UIC_DL_PA_INIT_ERROR) || 6186 (hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)); 6187 } 6188 6189 void ufshcd_schedule_eh_work(struct ufs_hba *hba) 6190 { 6191 lockdep_assert_held(hba->host->host_lock); 6192 6193 /* handle fatal errors only when link is not in error state */ 6194 if (hba->ufshcd_state != UFSHCD_STATE_ERROR) { 6195 if (hba->force_reset || ufshcd_is_link_broken(hba) || 6196 ufshcd_is_saved_err_fatal(hba)) 6197 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_FATAL; 6198 else 6199 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_NON_FATAL; 6200 queue_work(hba->eh_wq, &hba->eh_work); 6201 } 6202 } 6203 6204 static void ufshcd_force_error_recovery(struct ufs_hba *hba) 6205 { 6206 spin_lock_irq(hba->host->host_lock); 6207 hba->force_reset = true; 6208 ufshcd_schedule_eh_work(hba); 6209 spin_unlock_irq(hba->host->host_lock); 6210 } 6211 6212 static void ufshcd_clk_scaling_allow(struct ufs_hba *hba, bool allow) 6213 { 6214 mutex_lock(&hba->wb_mutex); 6215 down_write(&hba->clk_scaling_lock); 6216 hba->clk_scaling.is_allowed = allow; 6217 up_write(&hba->clk_scaling_lock); 6218 mutex_unlock(&hba->wb_mutex); 6219 } 6220 6221 static void ufshcd_clk_scaling_suspend(struct ufs_hba *hba, bool suspend) 6222 { 6223 if (suspend) { 6224 if (hba->clk_scaling.is_enabled) 6225 ufshcd_suspend_clkscaling(hba); 6226 ufshcd_clk_scaling_allow(hba, false); 6227 } else { 6228 ufshcd_clk_scaling_allow(hba, true); 6229 if (hba->clk_scaling.is_enabled) 6230 ufshcd_resume_clkscaling(hba); 6231 } 6232 } 6233 6234 static void ufshcd_err_handling_prepare(struct ufs_hba *hba) 6235 { 6236 ufshcd_rpm_get_sync(hba); 6237 if (pm_runtime_status_suspended(&hba->ufs_device_wlun->sdev_gendev) || 6238 hba->is_sys_suspended) { 6239 enum ufs_pm_op pm_op; 6240 6241 /* 6242 * Don't assume anything of resume, if 6243 * resume fails, irq and clocks can be OFF, and powers 6244 * can be OFF or in LPM. 6245 */ 6246 ufshcd_setup_hba_vreg(hba, true); 6247 ufshcd_enable_irq(hba); 6248 ufshcd_setup_vreg(hba, true); 6249 ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq); 6250 ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2); 6251 ufshcd_hold(hba); 6252 if (!ufshcd_is_clkgating_allowed(hba)) 6253 ufshcd_setup_clocks(hba, true); 6254 ufshcd_release(hba); 6255 pm_op = hba->is_sys_suspended ? UFS_SYSTEM_PM : UFS_RUNTIME_PM; 6256 ufshcd_vops_resume(hba, pm_op); 6257 } else { 6258 ufshcd_hold(hba); 6259 if (ufshcd_is_clkscaling_supported(hba) && 6260 hba->clk_scaling.is_enabled) 6261 ufshcd_suspend_clkscaling(hba); 6262 ufshcd_clk_scaling_allow(hba, false); 6263 } 6264 ufshcd_scsi_block_requests(hba); 6265 /* Wait for ongoing ufshcd_queuecommand() calls to finish. */ 6266 blk_mq_wait_quiesce_done(&hba->host->tag_set); 6267 cancel_work_sync(&hba->eeh_work); 6268 } 6269 6270 static void ufshcd_err_handling_unprepare(struct ufs_hba *hba) 6271 { 6272 ufshcd_scsi_unblock_requests(hba); 6273 ufshcd_release(hba); 6274 if (ufshcd_is_clkscaling_supported(hba)) 6275 ufshcd_clk_scaling_suspend(hba, false); 6276 ufshcd_rpm_put(hba); 6277 } 6278 6279 static inline bool ufshcd_err_handling_should_stop(struct ufs_hba *hba) 6280 { 6281 return (!hba->is_powered || hba->shutting_down || 6282 !hba->ufs_device_wlun || 6283 hba->ufshcd_state == UFSHCD_STATE_ERROR || 6284 (!(hba->saved_err || hba->saved_uic_err || hba->force_reset || 6285 ufshcd_is_link_broken(hba)))); 6286 } 6287 6288 #ifdef CONFIG_PM 6289 static void ufshcd_recover_pm_error(struct ufs_hba *hba) 6290 { 6291 struct Scsi_Host *shost = hba->host; 6292 struct scsi_device *sdev; 6293 struct request_queue *q; 6294 int ret; 6295 6296 hba->is_sys_suspended = false; 6297 /* 6298 * Set RPM status of wlun device to RPM_ACTIVE, 6299 * this also clears its runtime error. 6300 */ 6301 ret = pm_runtime_set_active(&hba->ufs_device_wlun->sdev_gendev); 6302 6303 /* hba device might have a runtime error otherwise */ 6304 if (ret) 6305 ret = pm_runtime_set_active(hba->dev); 6306 /* 6307 * If wlun device had runtime error, we also need to resume those 6308 * consumer scsi devices in case any of them has failed to be 6309 * resumed due to supplier runtime resume failure. This is to unblock 6310 * blk_queue_enter in case there are bios waiting inside it. 6311 */ 6312 if (!ret) { 6313 shost_for_each_device(sdev, shost) { 6314 q = sdev->request_queue; 6315 if (q->dev && (q->rpm_status == RPM_SUSPENDED || 6316 q->rpm_status == RPM_SUSPENDING)) 6317 pm_request_resume(q->dev); 6318 } 6319 } 6320 } 6321 #else 6322 static inline void ufshcd_recover_pm_error(struct ufs_hba *hba) 6323 { 6324 } 6325 #endif 6326 6327 static bool ufshcd_is_pwr_mode_restore_needed(struct ufs_hba *hba) 6328 { 6329 struct ufs_pa_layer_attr *pwr_info = &hba->pwr_info; 6330 u32 mode; 6331 6332 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PWRMODE), &mode); 6333 6334 if (pwr_info->pwr_rx != ((mode >> PWRMODE_RX_OFFSET) & PWRMODE_MASK)) 6335 return true; 6336 6337 if (pwr_info->pwr_tx != (mode & PWRMODE_MASK)) 6338 return true; 6339 6340 return false; 6341 } 6342 6343 static bool ufshcd_abort_one(struct request *rq, void *priv) 6344 { 6345 int *ret = priv; 6346 u32 tag = rq->tag; 6347 struct scsi_cmnd *cmd = blk_mq_rq_to_pdu(rq); 6348 struct scsi_device *sdev = cmd->device; 6349 struct Scsi_Host *shost = sdev->host; 6350 struct ufs_hba *hba = shost_priv(shost); 6351 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 6352 struct ufs_hw_queue *hwq; 6353 unsigned long flags; 6354 6355 *ret = ufshcd_try_to_abort_task(hba, tag); 6356 dev_err(hba->dev, "Aborting tag %d / CDB %#02x %s\n", tag, 6357 hba->lrb[tag].cmd ? hba->lrb[tag].cmd->cmnd[0] : -1, 6358 *ret ? "failed" : "succeeded"); 6359 6360 /* Release cmd in MCQ mode if abort succeeds */ 6361 if (is_mcq_enabled(hba) && (*ret == 0)) { 6362 hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(lrbp->cmd)); 6363 spin_lock_irqsave(&hwq->cq_lock, flags); 6364 if (ufshcd_cmd_inflight(lrbp->cmd)) 6365 ufshcd_release_scsi_cmd(hba, lrbp); 6366 spin_unlock_irqrestore(&hwq->cq_lock, flags); 6367 } 6368 6369 return *ret == 0; 6370 } 6371 6372 /** 6373 * ufshcd_abort_all - Abort all pending commands. 6374 * @hba: Host bus adapter pointer. 6375 * 6376 * Return: true if and only if the host controller needs to be reset. 6377 */ 6378 static bool ufshcd_abort_all(struct ufs_hba *hba) 6379 { 6380 int tag, ret = 0; 6381 6382 blk_mq_tagset_busy_iter(&hba->host->tag_set, ufshcd_abort_one, &ret); 6383 if (ret) 6384 goto out; 6385 6386 /* Clear pending task management requests */ 6387 for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) { 6388 ret = ufshcd_clear_tm_cmd(hba, tag); 6389 if (ret) 6390 goto out; 6391 } 6392 6393 out: 6394 /* Complete the requests that are cleared by s/w */ 6395 ufshcd_complete_requests(hba, false); 6396 6397 return ret != 0; 6398 } 6399 6400 /** 6401 * ufshcd_err_handler - handle UFS errors that require s/w attention 6402 * @work: pointer to work structure 6403 */ 6404 static void ufshcd_err_handler(struct work_struct *work) 6405 { 6406 int retries = MAX_ERR_HANDLER_RETRIES; 6407 struct ufs_hba *hba; 6408 unsigned long flags; 6409 bool needs_restore; 6410 bool needs_reset; 6411 int pmc_err; 6412 6413 hba = container_of(work, struct ufs_hba, eh_work); 6414 6415 dev_info(hba->dev, 6416 "%s started; HBA state %s; powered %d; shutting down %d; saved_err = %d; saved_uic_err = %d; force_reset = %d%s\n", 6417 __func__, ufshcd_state_name[hba->ufshcd_state], 6418 hba->is_powered, hba->shutting_down, hba->saved_err, 6419 hba->saved_uic_err, hba->force_reset, 6420 ufshcd_is_link_broken(hba) ? "; link is broken" : ""); 6421 6422 down(&hba->host_sem); 6423 spin_lock_irqsave(hba->host->host_lock, flags); 6424 if (ufshcd_err_handling_should_stop(hba)) { 6425 if (hba->ufshcd_state != UFSHCD_STATE_ERROR) 6426 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL; 6427 spin_unlock_irqrestore(hba->host->host_lock, flags); 6428 up(&hba->host_sem); 6429 return; 6430 } 6431 ufshcd_set_eh_in_progress(hba); 6432 spin_unlock_irqrestore(hba->host->host_lock, flags); 6433 ufshcd_err_handling_prepare(hba); 6434 /* Complete requests that have door-bell cleared by h/w */ 6435 ufshcd_complete_requests(hba, false); 6436 spin_lock_irqsave(hba->host->host_lock, flags); 6437 again: 6438 needs_restore = false; 6439 needs_reset = false; 6440 6441 if (hba->ufshcd_state != UFSHCD_STATE_ERROR) 6442 hba->ufshcd_state = UFSHCD_STATE_RESET; 6443 /* 6444 * A full reset and restore might have happened after preparation 6445 * is finished, double check whether we should stop. 6446 */ 6447 if (ufshcd_err_handling_should_stop(hba)) 6448 goto skip_err_handling; 6449 6450 if (hba->dev_quirks & UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) { 6451 bool ret; 6452 6453 spin_unlock_irqrestore(hba->host->host_lock, flags); 6454 /* release the lock as ufshcd_quirk_dl_nac_errors() may sleep */ 6455 ret = ufshcd_quirk_dl_nac_errors(hba); 6456 spin_lock_irqsave(hba->host->host_lock, flags); 6457 if (!ret && ufshcd_err_handling_should_stop(hba)) 6458 goto skip_err_handling; 6459 } 6460 6461 if ((hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) || 6462 (hba->saved_uic_err && 6463 (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) { 6464 bool pr_prdt = !!(hba->saved_err & SYSTEM_BUS_FATAL_ERROR); 6465 6466 spin_unlock_irqrestore(hba->host->host_lock, flags); 6467 ufshcd_print_host_state(hba); 6468 ufshcd_print_pwr_info(hba); 6469 ufshcd_print_evt_hist(hba); 6470 ufshcd_print_tmrs(hba, hba->outstanding_tasks); 6471 ufshcd_print_trs_all(hba, pr_prdt); 6472 spin_lock_irqsave(hba->host->host_lock, flags); 6473 } 6474 6475 /* 6476 * if host reset is required then skip clearing the pending 6477 * transfers forcefully because they will get cleared during 6478 * host reset and restore 6479 */ 6480 if (hba->force_reset || ufshcd_is_link_broken(hba) || 6481 ufshcd_is_saved_err_fatal(hba) || 6482 ((hba->saved_err & UIC_ERROR) && 6483 (hba->saved_uic_err & (UFSHCD_UIC_DL_NAC_RECEIVED_ERROR | 6484 UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))) { 6485 needs_reset = true; 6486 goto do_reset; 6487 } 6488 6489 /* 6490 * If LINERESET was caught, UFS might have been put to PWM mode, 6491 * check if power mode restore is needed. 6492 */ 6493 if (hba->saved_uic_err & UFSHCD_UIC_PA_GENERIC_ERROR) { 6494 hba->saved_uic_err &= ~UFSHCD_UIC_PA_GENERIC_ERROR; 6495 if (!hba->saved_uic_err) 6496 hba->saved_err &= ~UIC_ERROR; 6497 spin_unlock_irqrestore(hba->host->host_lock, flags); 6498 if (ufshcd_is_pwr_mode_restore_needed(hba)) 6499 needs_restore = true; 6500 spin_lock_irqsave(hba->host->host_lock, flags); 6501 if (!hba->saved_err && !needs_restore) 6502 goto skip_err_handling; 6503 } 6504 6505 hba->silence_err_logs = true; 6506 /* release lock as clear command might sleep */ 6507 spin_unlock_irqrestore(hba->host->host_lock, flags); 6508 6509 needs_reset = ufshcd_abort_all(hba); 6510 6511 spin_lock_irqsave(hba->host->host_lock, flags); 6512 hba->silence_err_logs = false; 6513 if (needs_reset) 6514 goto do_reset; 6515 6516 /* 6517 * After all reqs and tasks are cleared from doorbell, 6518 * now it is safe to retore power mode. 6519 */ 6520 if (needs_restore) { 6521 spin_unlock_irqrestore(hba->host->host_lock, flags); 6522 /* 6523 * Hold the scaling lock just in case dev cmds 6524 * are sent via bsg and/or sysfs. 6525 */ 6526 down_write(&hba->clk_scaling_lock); 6527 hba->force_pmc = true; 6528 pmc_err = ufshcd_config_pwr_mode(hba, &(hba->pwr_info)); 6529 if (pmc_err) { 6530 needs_reset = true; 6531 dev_err(hba->dev, "%s: Failed to restore power mode, err = %d\n", 6532 __func__, pmc_err); 6533 } 6534 hba->force_pmc = false; 6535 ufshcd_print_pwr_info(hba); 6536 up_write(&hba->clk_scaling_lock); 6537 spin_lock_irqsave(hba->host->host_lock, flags); 6538 } 6539 6540 do_reset: 6541 /* Fatal errors need reset */ 6542 if (needs_reset) { 6543 int err; 6544 6545 hba->force_reset = false; 6546 spin_unlock_irqrestore(hba->host->host_lock, flags); 6547 err = ufshcd_reset_and_restore(hba); 6548 if (err) 6549 dev_err(hba->dev, "%s: reset and restore failed with err %d\n", 6550 __func__, err); 6551 else 6552 ufshcd_recover_pm_error(hba); 6553 spin_lock_irqsave(hba->host->host_lock, flags); 6554 } 6555 6556 skip_err_handling: 6557 if (!needs_reset) { 6558 if (hba->ufshcd_state == UFSHCD_STATE_RESET) 6559 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL; 6560 if (hba->saved_err || hba->saved_uic_err) 6561 dev_err_ratelimited(hba->dev, "%s: exit: saved_err 0x%x saved_uic_err 0x%x", 6562 __func__, hba->saved_err, hba->saved_uic_err); 6563 } 6564 /* Exit in an operational state or dead */ 6565 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL && 6566 hba->ufshcd_state != UFSHCD_STATE_ERROR) { 6567 if (--retries) 6568 goto again; 6569 hba->ufshcd_state = UFSHCD_STATE_ERROR; 6570 } 6571 ufshcd_clear_eh_in_progress(hba); 6572 spin_unlock_irqrestore(hba->host->host_lock, flags); 6573 ufshcd_err_handling_unprepare(hba); 6574 up(&hba->host_sem); 6575 6576 dev_info(hba->dev, "%s finished; HBA state %s\n", __func__, 6577 ufshcd_state_name[hba->ufshcd_state]); 6578 } 6579 6580 /** 6581 * ufshcd_update_uic_error - check and set fatal UIC error flags. 6582 * @hba: per-adapter instance 6583 * 6584 * Return: 6585 * IRQ_HANDLED - If interrupt is valid 6586 * IRQ_NONE - If invalid interrupt 6587 */ 6588 static irqreturn_t ufshcd_update_uic_error(struct ufs_hba *hba) 6589 { 6590 u32 reg; 6591 irqreturn_t retval = IRQ_NONE; 6592 6593 /* PHY layer error */ 6594 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER); 6595 if ((reg & UIC_PHY_ADAPTER_LAYER_ERROR) && 6596 (reg & UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK)) { 6597 ufshcd_update_evt_hist(hba, UFS_EVT_PA_ERR, reg); 6598 /* 6599 * To know whether this error is fatal or not, DB timeout 6600 * must be checked but this error is handled separately. 6601 */ 6602 if (reg & UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK) 6603 dev_dbg(hba->dev, "%s: UIC Lane error reported\n", 6604 __func__); 6605 6606 /* Got a LINERESET indication. */ 6607 if (reg & UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR) { 6608 struct uic_command *cmd = NULL; 6609 6610 hba->uic_error |= UFSHCD_UIC_PA_GENERIC_ERROR; 6611 if (hba->uic_async_done && hba->active_uic_cmd) 6612 cmd = hba->active_uic_cmd; 6613 /* 6614 * Ignore the LINERESET during power mode change 6615 * operation via DME_SET command. 6616 */ 6617 if (cmd && (cmd->command == UIC_CMD_DME_SET)) 6618 hba->uic_error &= ~UFSHCD_UIC_PA_GENERIC_ERROR; 6619 } 6620 retval |= IRQ_HANDLED; 6621 } 6622 6623 /* PA_INIT_ERROR is fatal and needs UIC reset */ 6624 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER); 6625 if ((reg & UIC_DATA_LINK_LAYER_ERROR) && 6626 (reg & UIC_DATA_LINK_LAYER_ERROR_CODE_MASK)) { 6627 ufshcd_update_evt_hist(hba, UFS_EVT_DL_ERR, reg); 6628 6629 if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT) 6630 hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR; 6631 else if (hba->dev_quirks & 6632 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) { 6633 if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED) 6634 hba->uic_error |= 6635 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR; 6636 else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT) 6637 hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR; 6638 } 6639 retval |= IRQ_HANDLED; 6640 } 6641 6642 /* UIC NL/TL/DME errors needs software retry */ 6643 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER); 6644 if ((reg & UIC_NETWORK_LAYER_ERROR) && 6645 (reg & UIC_NETWORK_LAYER_ERROR_CODE_MASK)) { 6646 ufshcd_update_evt_hist(hba, UFS_EVT_NL_ERR, reg); 6647 hba->uic_error |= UFSHCD_UIC_NL_ERROR; 6648 retval |= IRQ_HANDLED; 6649 } 6650 6651 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER); 6652 if ((reg & UIC_TRANSPORT_LAYER_ERROR) && 6653 (reg & UIC_TRANSPORT_LAYER_ERROR_CODE_MASK)) { 6654 ufshcd_update_evt_hist(hba, UFS_EVT_TL_ERR, reg); 6655 hba->uic_error |= UFSHCD_UIC_TL_ERROR; 6656 retval |= IRQ_HANDLED; 6657 } 6658 6659 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME); 6660 if ((reg & UIC_DME_ERROR) && 6661 (reg & UIC_DME_ERROR_CODE_MASK)) { 6662 ufshcd_update_evt_hist(hba, UFS_EVT_DME_ERR, reg); 6663 hba->uic_error |= UFSHCD_UIC_DME_ERROR; 6664 retval |= IRQ_HANDLED; 6665 } 6666 6667 dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n", 6668 __func__, hba->uic_error); 6669 return retval; 6670 } 6671 6672 /** 6673 * ufshcd_check_errors - Check for errors that need s/w attention 6674 * @hba: per-adapter instance 6675 * @intr_status: interrupt status generated by the controller 6676 * 6677 * Return: 6678 * IRQ_HANDLED - If interrupt is valid 6679 * IRQ_NONE - If invalid interrupt 6680 */ 6681 static irqreturn_t ufshcd_check_errors(struct ufs_hba *hba, u32 intr_status) 6682 { 6683 bool queue_eh_work = false; 6684 irqreturn_t retval = IRQ_NONE; 6685 6686 spin_lock(hba->host->host_lock); 6687 hba->errors |= UFSHCD_ERROR_MASK & intr_status; 6688 6689 if (hba->errors & INT_FATAL_ERRORS) { 6690 ufshcd_update_evt_hist(hba, UFS_EVT_FATAL_ERR, 6691 hba->errors); 6692 queue_eh_work = true; 6693 } 6694 6695 if (hba->errors & UIC_ERROR) { 6696 hba->uic_error = 0; 6697 retval = ufshcd_update_uic_error(hba); 6698 if (hba->uic_error) 6699 queue_eh_work = true; 6700 } 6701 6702 if (hba->errors & UFSHCD_UIC_HIBERN8_MASK) { 6703 dev_err(hba->dev, 6704 "%s: Auto Hibern8 %s failed - status: 0x%08x, upmcrs: 0x%08x\n", 6705 __func__, (hba->errors & UIC_HIBERNATE_ENTER) ? 6706 "Enter" : "Exit", 6707 hba->errors, ufshcd_get_upmcrs(hba)); 6708 ufshcd_update_evt_hist(hba, UFS_EVT_AUTO_HIBERN8_ERR, 6709 hba->errors); 6710 ufshcd_set_link_broken(hba); 6711 queue_eh_work = true; 6712 } 6713 6714 if (queue_eh_work) { 6715 /* 6716 * update the transfer error masks to sticky bits, let's do this 6717 * irrespective of current ufshcd_state. 6718 */ 6719 hba->saved_err |= hba->errors; 6720 hba->saved_uic_err |= hba->uic_error; 6721 6722 /* dump controller state before resetting */ 6723 if ((hba->saved_err & 6724 (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) || 6725 (hba->saved_uic_err && 6726 (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) { 6727 dev_err(hba->dev, "%s: saved_err 0x%x saved_uic_err 0x%x\n", 6728 __func__, hba->saved_err, 6729 hba->saved_uic_err); 6730 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, 6731 "host_regs: "); 6732 ufshcd_print_pwr_info(hba); 6733 } 6734 ufshcd_schedule_eh_work(hba); 6735 retval |= IRQ_HANDLED; 6736 } 6737 /* 6738 * if (!queue_eh_work) - 6739 * Other errors are either non-fatal where host recovers 6740 * itself without s/w intervention or errors that will be 6741 * handled by the SCSI core layer. 6742 */ 6743 hba->errors = 0; 6744 hba->uic_error = 0; 6745 spin_unlock(hba->host->host_lock); 6746 return retval; 6747 } 6748 6749 /** 6750 * ufshcd_tmc_handler - handle task management function completion 6751 * @hba: per adapter instance 6752 * 6753 * Return: 6754 * IRQ_HANDLED - If interrupt is valid 6755 * IRQ_NONE - If invalid interrupt 6756 */ 6757 static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba) 6758 { 6759 unsigned long flags, pending, issued; 6760 irqreturn_t ret = IRQ_NONE; 6761 int tag; 6762 6763 spin_lock_irqsave(hba->host->host_lock, flags); 6764 pending = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL); 6765 issued = hba->outstanding_tasks & ~pending; 6766 for_each_set_bit(tag, &issued, hba->nutmrs) { 6767 struct request *req = hba->tmf_rqs[tag]; 6768 struct completion *c = req->end_io_data; 6769 6770 complete(c); 6771 ret = IRQ_HANDLED; 6772 } 6773 spin_unlock_irqrestore(hba->host->host_lock, flags); 6774 6775 return ret; 6776 } 6777 6778 /** 6779 * ufshcd_handle_mcq_cq_events - handle MCQ completion queue events 6780 * @hba: per adapter instance 6781 * 6782 * Return: IRQ_HANDLED if interrupt is handled. 6783 */ 6784 static irqreturn_t ufshcd_handle_mcq_cq_events(struct ufs_hba *hba) 6785 { 6786 struct ufs_hw_queue *hwq; 6787 unsigned long outstanding_cqs; 6788 unsigned int nr_queues; 6789 int i, ret; 6790 u32 events; 6791 6792 ret = ufshcd_vops_get_outstanding_cqs(hba, &outstanding_cqs); 6793 if (ret) 6794 outstanding_cqs = (1U << hba->nr_hw_queues) - 1; 6795 6796 /* Exclude the poll queues */ 6797 nr_queues = hba->nr_hw_queues - hba->nr_queues[HCTX_TYPE_POLL]; 6798 for_each_set_bit(i, &outstanding_cqs, nr_queues) { 6799 hwq = &hba->uhq[i]; 6800 6801 events = ufshcd_mcq_read_cqis(hba, i); 6802 if (events) 6803 ufshcd_mcq_write_cqis(hba, events, i); 6804 6805 if (events & UFSHCD_MCQ_CQIS_TAIL_ENT_PUSH_STS) 6806 ufshcd_mcq_poll_cqe_lock(hba, hwq); 6807 } 6808 6809 return IRQ_HANDLED; 6810 } 6811 6812 /** 6813 * ufshcd_sl_intr - Interrupt service routine 6814 * @hba: per adapter instance 6815 * @intr_status: contains interrupts generated by the controller 6816 * 6817 * Return: 6818 * IRQ_HANDLED - If interrupt is valid 6819 * IRQ_NONE - If invalid interrupt 6820 */ 6821 static irqreturn_t ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status) 6822 { 6823 irqreturn_t retval = IRQ_NONE; 6824 6825 if (intr_status & UFSHCD_UIC_MASK) 6826 retval |= ufshcd_uic_cmd_compl(hba, intr_status); 6827 6828 if (intr_status & UFSHCD_ERROR_MASK || hba->errors) 6829 retval |= ufshcd_check_errors(hba, intr_status); 6830 6831 if (intr_status & UTP_TASK_REQ_COMPL) 6832 retval |= ufshcd_tmc_handler(hba); 6833 6834 if (intr_status & UTP_TRANSFER_REQ_COMPL) 6835 retval |= ufshcd_transfer_req_compl(hba); 6836 6837 if (intr_status & MCQ_CQ_EVENT_STATUS) 6838 retval |= ufshcd_handle_mcq_cq_events(hba); 6839 6840 return retval; 6841 } 6842 6843 /** 6844 * ufshcd_intr - Main interrupt service routine 6845 * @irq: irq number 6846 * @__hba: pointer to adapter instance 6847 * 6848 * Return: 6849 * IRQ_HANDLED - If interrupt is valid 6850 * IRQ_NONE - If invalid interrupt 6851 */ 6852 static irqreturn_t ufshcd_intr(int irq, void *__hba) 6853 { 6854 u32 intr_status, enabled_intr_status = 0; 6855 irqreturn_t retval = IRQ_NONE; 6856 struct ufs_hba *hba = __hba; 6857 int retries = hba->nutrs; 6858 6859 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS); 6860 hba->ufs_stats.last_intr_status = intr_status; 6861 hba->ufs_stats.last_intr_ts = local_clock(); 6862 6863 /* 6864 * There could be max of hba->nutrs reqs in flight and in worst case 6865 * if the reqs get finished 1 by 1 after the interrupt status is 6866 * read, make sure we handle them by checking the interrupt status 6867 * again in a loop until we process all of the reqs before returning. 6868 */ 6869 while (intr_status && retries--) { 6870 enabled_intr_status = 6871 intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 6872 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS); 6873 if (enabled_intr_status) 6874 retval |= ufshcd_sl_intr(hba, enabled_intr_status); 6875 6876 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS); 6877 } 6878 6879 if (enabled_intr_status && retval == IRQ_NONE && 6880 (!(enabled_intr_status & UTP_TRANSFER_REQ_COMPL) || 6881 hba->outstanding_reqs) && !ufshcd_eh_in_progress(hba)) { 6882 dev_err(hba->dev, "%s: Unhandled interrupt 0x%08x (0x%08x, 0x%08x)\n", 6883 __func__, 6884 intr_status, 6885 hba->ufs_stats.last_intr_status, 6886 enabled_intr_status); 6887 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: "); 6888 } 6889 6890 return retval; 6891 } 6892 6893 static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag) 6894 { 6895 int err = 0; 6896 u32 mask = 1 << tag; 6897 unsigned long flags; 6898 6899 if (!test_bit(tag, &hba->outstanding_tasks)) 6900 goto out; 6901 6902 spin_lock_irqsave(hba->host->host_lock, flags); 6903 ufshcd_utmrl_clear(hba, tag); 6904 spin_unlock_irqrestore(hba->host->host_lock, flags); 6905 6906 /* poll for max. 1 sec to clear door bell register by h/w */ 6907 err = ufshcd_wait_for_register(hba, 6908 REG_UTP_TASK_REQ_DOOR_BELL, 6909 mask, 0, 1000, 1000); 6910 6911 dev_err(hba->dev, "Clearing task management function with tag %d %s\n", 6912 tag, err < 0 ? "failed" : "succeeded"); 6913 6914 out: 6915 return err; 6916 } 6917 6918 static int __ufshcd_issue_tm_cmd(struct ufs_hba *hba, 6919 struct utp_task_req_desc *treq, u8 tm_function) 6920 { 6921 struct request_queue *q = hba->tmf_queue; 6922 struct Scsi_Host *host = hba->host; 6923 DECLARE_COMPLETION_ONSTACK(wait); 6924 struct request *req; 6925 unsigned long flags; 6926 int task_tag, err; 6927 6928 /* 6929 * blk_mq_alloc_request() is used here only to get a free tag. 6930 */ 6931 req = blk_mq_alloc_request(q, REQ_OP_DRV_OUT, 0); 6932 if (IS_ERR(req)) 6933 return PTR_ERR(req); 6934 6935 req->end_io_data = &wait; 6936 ufshcd_hold(hba); 6937 6938 spin_lock_irqsave(host->host_lock, flags); 6939 6940 task_tag = req->tag; 6941 WARN_ONCE(task_tag < 0 || task_tag >= hba->nutmrs, "Invalid tag %d\n", 6942 task_tag); 6943 hba->tmf_rqs[req->tag] = req; 6944 treq->upiu_req.req_header.task_tag = task_tag; 6945 6946 memcpy(hba->utmrdl_base_addr + task_tag, treq, sizeof(*treq)); 6947 ufshcd_vops_setup_task_mgmt(hba, task_tag, tm_function); 6948 6949 /* send command to the controller */ 6950 __set_bit(task_tag, &hba->outstanding_tasks); 6951 6952 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TASK_REQ_DOOR_BELL); 6953 /* Make sure that doorbell is committed immediately */ 6954 wmb(); 6955 6956 spin_unlock_irqrestore(host->host_lock, flags); 6957 6958 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_SEND); 6959 6960 /* wait until the task management command is completed */ 6961 err = wait_for_completion_io_timeout(&wait, 6962 msecs_to_jiffies(TM_CMD_TIMEOUT)); 6963 if (!err) { 6964 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_ERR); 6965 dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n", 6966 __func__, tm_function); 6967 if (ufshcd_clear_tm_cmd(hba, task_tag)) 6968 dev_WARN(hba->dev, "%s: unable to clear tm cmd (slot %d) after timeout\n", 6969 __func__, task_tag); 6970 err = -ETIMEDOUT; 6971 } else { 6972 err = 0; 6973 memcpy(treq, hba->utmrdl_base_addr + task_tag, sizeof(*treq)); 6974 6975 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_COMP); 6976 } 6977 6978 spin_lock_irqsave(hba->host->host_lock, flags); 6979 hba->tmf_rqs[req->tag] = NULL; 6980 __clear_bit(task_tag, &hba->outstanding_tasks); 6981 spin_unlock_irqrestore(hba->host->host_lock, flags); 6982 6983 ufshcd_release(hba); 6984 blk_mq_free_request(req); 6985 6986 return err; 6987 } 6988 6989 /** 6990 * ufshcd_issue_tm_cmd - issues task management commands to controller 6991 * @hba: per adapter instance 6992 * @lun_id: LUN ID to which TM command is sent 6993 * @task_id: task ID to which the TM command is applicable 6994 * @tm_function: task management function opcode 6995 * @tm_response: task management service response return value 6996 * 6997 * Return: non-zero value on error, zero on success. 6998 */ 6999 static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id, 7000 u8 tm_function, u8 *tm_response) 7001 { 7002 struct utp_task_req_desc treq = { }; 7003 enum utp_ocs ocs_value; 7004 int err; 7005 7006 /* Configure task request descriptor */ 7007 treq.header.interrupt = 1; 7008 treq.header.ocs = OCS_INVALID_COMMAND_STATUS; 7009 7010 /* Configure task request UPIU */ 7011 treq.upiu_req.req_header.transaction_code = UPIU_TRANSACTION_TASK_REQ; 7012 treq.upiu_req.req_header.lun = lun_id; 7013 treq.upiu_req.req_header.tm_function = tm_function; 7014 7015 /* 7016 * The host shall provide the same value for LUN field in the basic 7017 * header and for Input Parameter. 7018 */ 7019 treq.upiu_req.input_param1 = cpu_to_be32(lun_id); 7020 treq.upiu_req.input_param2 = cpu_to_be32(task_id); 7021 7022 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_function); 7023 if (err == -ETIMEDOUT) 7024 return err; 7025 7026 ocs_value = treq.header.ocs & MASK_OCS; 7027 if (ocs_value != OCS_SUCCESS) 7028 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n", 7029 __func__, ocs_value); 7030 else if (tm_response) 7031 *tm_response = be32_to_cpu(treq.upiu_rsp.output_param1) & 7032 MASK_TM_SERVICE_RESP; 7033 return err; 7034 } 7035 7036 /** 7037 * ufshcd_issue_devman_upiu_cmd - API for sending "utrd" type requests 7038 * @hba: per-adapter instance 7039 * @req_upiu: upiu request 7040 * @rsp_upiu: upiu reply 7041 * @desc_buff: pointer to descriptor buffer, NULL if NA 7042 * @buff_len: descriptor size, 0 if NA 7043 * @cmd_type: specifies the type (NOP, Query...) 7044 * @desc_op: descriptor operation 7045 * 7046 * Those type of requests uses UTP Transfer Request Descriptor - utrd. 7047 * Therefore, it "rides" the device management infrastructure: uses its tag and 7048 * tasks work queues. 7049 * 7050 * Since there is only one available tag for device management commands, 7051 * the caller is expected to hold the hba->dev_cmd.lock mutex. 7052 * 7053 * Return: 0 upon success; < 0 upon failure. 7054 */ 7055 static int ufshcd_issue_devman_upiu_cmd(struct ufs_hba *hba, 7056 struct utp_upiu_req *req_upiu, 7057 struct utp_upiu_req *rsp_upiu, 7058 u8 *desc_buff, int *buff_len, 7059 enum dev_cmd_type cmd_type, 7060 enum query_opcode desc_op) 7061 { 7062 DECLARE_COMPLETION_ONSTACK(wait); 7063 const u32 tag = hba->reserved_slot; 7064 struct ufshcd_lrb *lrbp; 7065 int err = 0; 7066 u8 upiu_flags; 7067 7068 /* Protects use of hba->reserved_slot. */ 7069 lockdep_assert_held(&hba->dev_cmd.lock); 7070 7071 down_read(&hba->clk_scaling_lock); 7072 7073 lrbp = &hba->lrb[tag]; 7074 lrbp->cmd = NULL; 7075 lrbp->task_tag = tag; 7076 lrbp->lun = 0; 7077 lrbp->intr_cmd = true; 7078 ufshcd_prepare_lrbp_crypto(NULL, lrbp); 7079 hba->dev_cmd.type = cmd_type; 7080 7081 if (hba->ufs_version <= ufshci_version(1, 1)) 7082 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE; 7083 else 7084 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE; 7085 7086 /* update the task tag in the request upiu */ 7087 req_upiu->header.task_tag = tag; 7088 7089 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE, 0); 7090 7091 /* just copy the upiu request as it is */ 7092 memcpy(lrbp->ucd_req_ptr, req_upiu, sizeof(*lrbp->ucd_req_ptr)); 7093 if (desc_buff && desc_op == UPIU_QUERY_OPCODE_WRITE_DESC) { 7094 /* The Data Segment Area is optional depending upon the query 7095 * function value. for WRITE DESCRIPTOR, the data segment 7096 * follows right after the tsf. 7097 */ 7098 memcpy(lrbp->ucd_req_ptr + 1, desc_buff, *buff_len); 7099 *buff_len = 0; 7100 } 7101 7102 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 7103 7104 hba->dev_cmd.complete = &wait; 7105 7106 ufshcd_add_query_upiu_trace(hba, UFS_QUERY_SEND, lrbp->ucd_req_ptr); 7107 7108 ufshcd_send_command(hba, tag, hba->dev_cmd_queue); 7109 /* 7110 * ignore the returning value here - ufshcd_check_query_response is 7111 * bound to fail since dev_cmd.query and dev_cmd.type were left empty. 7112 * read the response directly ignoring all errors. 7113 */ 7114 ufshcd_wait_for_dev_cmd(hba, lrbp, QUERY_REQ_TIMEOUT); 7115 7116 /* just copy the upiu response as it is */ 7117 memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu)); 7118 if (desc_buff && desc_op == UPIU_QUERY_OPCODE_READ_DESC) { 7119 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr + sizeof(*rsp_upiu); 7120 u16 resp_len = be16_to_cpu(lrbp->ucd_rsp_ptr->header 7121 .data_segment_length); 7122 7123 if (*buff_len >= resp_len) { 7124 memcpy(desc_buff, descp, resp_len); 7125 *buff_len = resp_len; 7126 } else { 7127 dev_warn(hba->dev, 7128 "%s: rsp size %d is bigger than buffer size %d", 7129 __func__, resp_len, *buff_len); 7130 *buff_len = 0; 7131 err = -EINVAL; 7132 } 7133 } 7134 ufshcd_add_query_upiu_trace(hba, err ? UFS_QUERY_ERR : UFS_QUERY_COMP, 7135 (struct utp_upiu_req *)lrbp->ucd_rsp_ptr); 7136 7137 up_read(&hba->clk_scaling_lock); 7138 return err; 7139 } 7140 7141 /** 7142 * ufshcd_exec_raw_upiu_cmd - API function for sending raw upiu commands 7143 * @hba: per-adapter instance 7144 * @req_upiu: upiu request 7145 * @rsp_upiu: upiu reply - only 8 DW as we do not support scsi commands 7146 * @msgcode: message code, one of UPIU Transaction Codes Initiator to Target 7147 * @desc_buff: pointer to descriptor buffer, NULL if NA 7148 * @buff_len: descriptor size, 0 if NA 7149 * @desc_op: descriptor operation 7150 * 7151 * Supports UTP Transfer requests (nop and query), and UTP Task 7152 * Management requests. 7153 * It is up to the caller to fill the upiu conent properly, as it will 7154 * be copied without any further input validations. 7155 * 7156 * Return: 0 upon success; < 0 upon failure. 7157 */ 7158 int ufshcd_exec_raw_upiu_cmd(struct ufs_hba *hba, 7159 struct utp_upiu_req *req_upiu, 7160 struct utp_upiu_req *rsp_upiu, 7161 enum upiu_request_transaction msgcode, 7162 u8 *desc_buff, int *buff_len, 7163 enum query_opcode desc_op) 7164 { 7165 int err; 7166 enum dev_cmd_type cmd_type = DEV_CMD_TYPE_QUERY; 7167 struct utp_task_req_desc treq = { }; 7168 enum utp_ocs ocs_value; 7169 u8 tm_f = req_upiu->header.tm_function; 7170 7171 switch (msgcode) { 7172 case UPIU_TRANSACTION_NOP_OUT: 7173 cmd_type = DEV_CMD_TYPE_NOP; 7174 fallthrough; 7175 case UPIU_TRANSACTION_QUERY_REQ: 7176 ufshcd_hold(hba); 7177 mutex_lock(&hba->dev_cmd.lock); 7178 err = ufshcd_issue_devman_upiu_cmd(hba, req_upiu, rsp_upiu, 7179 desc_buff, buff_len, 7180 cmd_type, desc_op); 7181 mutex_unlock(&hba->dev_cmd.lock); 7182 ufshcd_release(hba); 7183 7184 break; 7185 case UPIU_TRANSACTION_TASK_REQ: 7186 treq.header.interrupt = 1; 7187 treq.header.ocs = OCS_INVALID_COMMAND_STATUS; 7188 7189 memcpy(&treq.upiu_req, req_upiu, sizeof(*req_upiu)); 7190 7191 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_f); 7192 if (err == -ETIMEDOUT) 7193 break; 7194 7195 ocs_value = treq.header.ocs & MASK_OCS; 7196 if (ocs_value != OCS_SUCCESS) { 7197 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n", __func__, 7198 ocs_value); 7199 break; 7200 } 7201 7202 memcpy(rsp_upiu, &treq.upiu_rsp, sizeof(*rsp_upiu)); 7203 7204 break; 7205 default: 7206 err = -EINVAL; 7207 7208 break; 7209 } 7210 7211 return err; 7212 } 7213 7214 /** 7215 * ufshcd_advanced_rpmb_req_handler - handle advanced RPMB request 7216 * @hba: per adapter instance 7217 * @req_upiu: upiu request 7218 * @rsp_upiu: upiu reply 7219 * @req_ehs: EHS field which contains Advanced RPMB Request Message 7220 * @rsp_ehs: EHS field which returns Advanced RPMB Response Message 7221 * @sg_cnt: The number of sg lists actually used 7222 * @sg_list: Pointer to SG list when DATA IN/OUT UPIU is required in ARPMB operation 7223 * @dir: DMA direction 7224 * 7225 * Return: zero on success, non-zero on failure. 7226 */ 7227 int ufshcd_advanced_rpmb_req_handler(struct ufs_hba *hba, struct utp_upiu_req *req_upiu, 7228 struct utp_upiu_req *rsp_upiu, struct ufs_ehs *req_ehs, 7229 struct ufs_ehs *rsp_ehs, int sg_cnt, struct scatterlist *sg_list, 7230 enum dma_data_direction dir) 7231 { 7232 DECLARE_COMPLETION_ONSTACK(wait); 7233 const u32 tag = hba->reserved_slot; 7234 struct ufshcd_lrb *lrbp; 7235 int err = 0; 7236 int result; 7237 u8 upiu_flags; 7238 u8 *ehs_data; 7239 u16 ehs_len; 7240 7241 /* Protects use of hba->reserved_slot. */ 7242 ufshcd_hold(hba); 7243 mutex_lock(&hba->dev_cmd.lock); 7244 down_read(&hba->clk_scaling_lock); 7245 7246 lrbp = &hba->lrb[tag]; 7247 lrbp->cmd = NULL; 7248 lrbp->task_tag = tag; 7249 lrbp->lun = UFS_UPIU_RPMB_WLUN; 7250 7251 lrbp->intr_cmd = true; 7252 ufshcd_prepare_lrbp_crypto(NULL, lrbp); 7253 hba->dev_cmd.type = DEV_CMD_TYPE_RPMB; 7254 7255 /* Advanced RPMB starts from UFS 4.0, so its command type is UTP_CMD_TYPE_UFS_STORAGE */ 7256 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE; 7257 7258 /* 7259 * According to UFSHCI 4.0 specification page 24, if EHSLUTRDS is 0, host controller takes 7260 * EHS length from CMD UPIU, and SW driver use EHS Length field in CMD UPIU. if it is 1, 7261 * HW controller takes EHS length from UTRD. 7262 */ 7263 if (hba->capabilities & MASK_EHSLUTRD_SUPPORTED) 7264 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, dir, 2); 7265 else 7266 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, dir, 0); 7267 7268 /* update the task tag */ 7269 req_upiu->header.task_tag = tag; 7270 7271 /* copy the UPIU(contains CDB) request as it is */ 7272 memcpy(lrbp->ucd_req_ptr, req_upiu, sizeof(*lrbp->ucd_req_ptr)); 7273 /* Copy EHS, starting with byte32, immediately after the CDB package */ 7274 memcpy(lrbp->ucd_req_ptr + 1, req_ehs, sizeof(*req_ehs)); 7275 7276 if (dir != DMA_NONE && sg_list) 7277 ufshcd_sgl_to_prdt(hba, lrbp, sg_cnt, sg_list); 7278 7279 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 7280 7281 hba->dev_cmd.complete = &wait; 7282 7283 ufshcd_send_command(hba, tag, hba->dev_cmd_queue); 7284 7285 err = ufshcd_wait_for_dev_cmd(hba, lrbp, ADVANCED_RPMB_REQ_TIMEOUT); 7286 7287 if (!err) { 7288 /* Just copy the upiu response as it is */ 7289 memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu)); 7290 /* Get the response UPIU result */ 7291 result = (lrbp->ucd_rsp_ptr->header.response << 8) | 7292 lrbp->ucd_rsp_ptr->header.status; 7293 7294 ehs_len = lrbp->ucd_rsp_ptr->header.ehs_length; 7295 /* 7296 * Since the bLength in EHS indicates the total size of the EHS Header and EHS Data 7297 * in 32 Byte units, the value of the bLength Request/Response for Advanced RPMB 7298 * Message is 02h 7299 */ 7300 if (ehs_len == 2 && rsp_ehs) { 7301 /* 7302 * ucd_rsp_ptr points to a buffer with a length of 512 bytes 7303 * (ALIGNED_UPIU_SIZE = 512), and the EHS data just starts from byte32 7304 */ 7305 ehs_data = (u8 *)lrbp->ucd_rsp_ptr + EHS_OFFSET_IN_RESPONSE; 7306 memcpy(rsp_ehs, ehs_data, ehs_len * 32); 7307 } 7308 } 7309 7310 up_read(&hba->clk_scaling_lock); 7311 mutex_unlock(&hba->dev_cmd.lock); 7312 ufshcd_release(hba); 7313 return err ? : result; 7314 } 7315 7316 /** 7317 * ufshcd_eh_device_reset_handler() - Reset a single logical unit. 7318 * @cmd: SCSI command pointer 7319 * 7320 * Return: SUCCESS or FAILED. 7321 */ 7322 static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd) 7323 { 7324 unsigned long flags, pending_reqs = 0, not_cleared = 0; 7325 struct Scsi_Host *host; 7326 struct ufs_hba *hba; 7327 struct ufs_hw_queue *hwq; 7328 struct ufshcd_lrb *lrbp; 7329 u32 pos, not_cleared_mask = 0; 7330 int err; 7331 u8 resp = 0xF, lun; 7332 7333 host = cmd->device->host; 7334 hba = shost_priv(host); 7335 7336 lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun); 7337 err = ufshcd_issue_tm_cmd(hba, lun, 0, UFS_LOGICAL_RESET, &resp); 7338 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) { 7339 if (!err) 7340 err = resp; 7341 goto out; 7342 } 7343 7344 if (is_mcq_enabled(hba)) { 7345 for (pos = 0; pos < hba->nutrs; pos++) { 7346 lrbp = &hba->lrb[pos]; 7347 if (ufshcd_cmd_inflight(lrbp->cmd) && 7348 lrbp->lun == lun) { 7349 ufshcd_clear_cmd(hba, pos); 7350 hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(lrbp->cmd)); 7351 ufshcd_mcq_poll_cqe_lock(hba, hwq); 7352 } 7353 } 7354 err = 0; 7355 goto out; 7356 } 7357 7358 /* clear the commands that were pending for corresponding LUN */ 7359 spin_lock_irqsave(&hba->outstanding_lock, flags); 7360 for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) 7361 if (hba->lrb[pos].lun == lun) 7362 __set_bit(pos, &pending_reqs); 7363 hba->outstanding_reqs &= ~pending_reqs; 7364 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 7365 7366 for_each_set_bit(pos, &pending_reqs, hba->nutrs) { 7367 if (ufshcd_clear_cmd(hba, pos) < 0) { 7368 spin_lock_irqsave(&hba->outstanding_lock, flags); 7369 not_cleared = 1U << pos & 7370 ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 7371 hba->outstanding_reqs |= not_cleared; 7372 not_cleared_mask |= not_cleared; 7373 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 7374 7375 dev_err(hba->dev, "%s: failed to clear request %d\n", 7376 __func__, pos); 7377 } 7378 } 7379 __ufshcd_transfer_req_compl(hba, pending_reqs & ~not_cleared_mask); 7380 7381 out: 7382 hba->req_abort_count = 0; 7383 ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, (u32)err); 7384 if (!err) { 7385 err = SUCCESS; 7386 } else { 7387 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err); 7388 err = FAILED; 7389 } 7390 return err; 7391 } 7392 7393 static void ufshcd_set_req_abort_skip(struct ufs_hba *hba, unsigned long bitmap) 7394 { 7395 struct ufshcd_lrb *lrbp; 7396 int tag; 7397 7398 for_each_set_bit(tag, &bitmap, hba->nutrs) { 7399 lrbp = &hba->lrb[tag]; 7400 lrbp->req_abort_skip = true; 7401 } 7402 } 7403 7404 /** 7405 * ufshcd_try_to_abort_task - abort a specific task 7406 * @hba: Pointer to adapter instance 7407 * @tag: Task tag/index to be aborted 7408 * 7409 * Abort the pending command in device by sending UFS_ABORT_TASK task management 7410 * command, and in host controller by clearing the door-bell register. There can 7411 * be race between controller sending the command to the device while abort is 7412 * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is 7413 * really issued and then try to abort it. 7414 * 7415 * Return: zero on success, non-zero on failure. 7416 */ 7417 int ufshcd_try_to_abort_task(struct ufs_hba *hba, int tag) 7418 { 7419 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 7420 int err = 0; 7421 int poll_cnt; 7422 u8 resp = 0xF; 7423 u32 reg; 7424 7425 for (poll_cnt = 100; poll_cnt; poll_cnt--) { 7426 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag, 7427 UFS_QUERY_TASK, &resp); 7428 if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) { 7429 /* cmd pending in the device */ 7430 dev_err(hba->dev, "%s: cmd pending in the device. tag = %d\n", 7431 __func__, tag); 7432 break; 7433 } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) { 7434 /* 7435 * cmd not pending in the device, check if it is 7436 * in transition. 7437 */ 7438 dev_err(hba->dev, "%s: cmd at tag %d not pending in the device.\n", 7439 __func__, tag); 7440 if (is_mcq_enabled(hba)) { 7441 /* MCQ mode */ 7442 if (ufshcd_cmd_inflight(lrbp->cmd)) { 7443 /* sleep for max. 200us same delay as in SDB mode */ 7444 usleep_range(100, 200); 7445 continue; 7446 } 7447 /* command completed already */ 7448 dev_err(hba->dev, "%s: cmd at tag=%d is cleared.\n", 7449 __func__, tag); 7450 goto out; 7451 } 7452 7453 /* Single Doorbell Mode */ 7454 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 7455 if (reg & (1 << tag)) { 7456 /* sleep for max. 200us to stabilize */ 7457 usleep_range(100, 200); 7458 continue; 7459 } 7460 /* command completed already */ 7461 dev_err(hba->dev, "%s: cmd at tag %d successfully cleared from DB.\n", 7462 __func__, tag); 7463 goto out; 7464 } else { 7465 dev_err(hba->dev, 7466 "%s: no response from device. tag = %d, err %d\n", 7467 __func__, tag, err); 7468 if (!err) 7469 err = resp; /* service response error */ 7470 goto out; 7471 } 7472 } 7473 7474 if (!poll_cnt) { 7475 err = -EBUSY; 7476 goto out; 7477 } 7478 7479 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag, 7480 UFS_ABORT_TASK, &resp); 7481 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) { 7482 if (!err) { 7483 err = resp; /* service response error */ 7484 dev_err(hba->dev, "%s: issued. tag = %d, err %d\n", 7485 __func__, tag, err); 7486 } 7487 goto out; 7488 } 7489 7490 err = ufshcd_clear_cmd(hba, tag); 7491 if (err) 7492 dev_err(hba->dev, "%s: Failed clearing cmd at tag %d, err %d\n", 7493 __func__, tag, err); 7494 7495 out: 7496 return err; 7497 } 7498 7499 /** 7500 * ufshcd_abort - scsi host template eh_abort_handler callback 7501 * @cmd: SCSI command pointer 7502 * 7503 * Return: SUCCESS or FAILED. 7504 */ 7505 static int ufshcd_abort(struct scsi_cmnd *cmd) 7506 { 7507 struct Scsi_Host *host = cmd->device->host; 7508 struct ufs_hba *hba = shost_priv(host); 7509 int tag = scsi_cmd_to_rq(cmd)->tag; 7510 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 7511 unsigned long flags; 7512 int err = FAILED; 7513 bool outstanding; 7514 u32 reg; 7515 7516 WARN_ONCE(tag < 0, "Invalid tag %d\n", tag); 7517 7518 ufshcd_hold(hba); 7519 7520 if (!is_mcq_enabled(hba)) { 7521 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 7522 if (!test_bit(tag, &hba->outstanding_reqs)) { 7523 /* If command is already aborted/completed, return FAILED. */ 7524 dev_err(hba->dev, 7525 "%s: cmd at tag %d already completed, outstanding=0x%lx, doorbell=0x%x\n", 7526 __func__, tag, hba->outstanding_reqs, reg); 7527 goto release; 7528 } 7529 } 7530 7531 /* Print Transfer Request of aborted task */ 7532 dev_info(hba->dev, "%s: Device abort task at tag %d\n", __func__, tag); 7533 7534 /* 7535 * Print detailed info about aborted request. 7536 * As more than one request might get aborted at the same time, 7537 * print full information only for the first aborted request in order 7538 * to reduce repeated printouts. For other aborted requests only print 7539 * basic details. 7540 */ 7541 scsi_print_command(cmd); 7542 if (!hba->req_abort_count) { 7543 ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, tag); 7544 ufshcd_print_evt_hist(hba); 7545 ufshcd_print_host_state(hba); 7546 ufshcd_print_pwr_info(hba); 7547 ufshcd_print_tr(hba, tag, true); 7548 } else { 7549 ufshcd_print_tr(hba, tag, false); 7550 } 7551 hba->req_abort_count++; 7552 7553 if (!is_mcq_enabled(hba) && !(reg & (1 << tag))) { 7554 /* only execute this code in single doorbell mode */ 7555 dev_err(hba->dev, 7556 "%s: cmd was completed, but without a notifying intr, tag = %d", 7557 __func__, tag); 7558 __ufshcd_transfer_req_compl(hba, 1UL << tag); 7559 goto release; 7560 } 7561 7562 /* 7563 * Task abort to the device W-LUN is illegal. When this command 7564 * will fail, due to spec violation, scsi err handling next step 7565 * will be to send LU reset which, again, is a spec violation. 7566 * To avoid these unnecessary/illegal steps, first we clean up 7567 * the lrb taken by this cmd and re-set it in outstanding_reqs, 7568 * then queue the eh_work and bail. 7569 */ 7570 if (lrbp->lun == UFS_UPIU_UFS_DEVICE_WLUN) { 7571 ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, lrbp->lun); 7572 7573 spin_lock_irqsave(host->host_lock, flags); 7574 hba->force_reset = true; 7575 ufshcd_schedule_eh_work(hba); 7576 spin_unlock_irqrestore(host->host_lock, flags); 7577 goto release; 7578 } 7579 7580 if (is_mcq_enabled(hba)) { 7581 /* MCQ mode. Branch off to handle abort for mcq mode */ 7582 err = ufshcd_mcq_abort(cmd); 7583 goto release; 7584 } 7585 7586 /* Skip task abort in case previous aborts failed and report failure */ 7587 if (lrbp->req_abort_skip) { 7588 dev_err(hba->dev, "%s: skipping abort\n", __func__); 7589 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs); 7590 goto release; 7591 } 7592 7593 err = ufshcd_try_to_abort_task(hba, tag); 7594 if (err) { 7595 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err); 7596 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs); 7597 err = FAILED; 7598 goto release; 7599 } 7600 7601 /* 7602 * Clear the corresponding bit from outstanding_reqs since the command 7603 * has been aborted successfully. 7604 */ 7605 spin_lock_irqsave(&hba->outstanding_lock, flags); 7606 outstanding = __test_and_clear_bit(tag, &hba->outstanding_reqs); 7607 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 7608 7609 if (outstanding) 7610 ufshcd_release_scsi_cmd(hba, lrbp); 7611 7612 err = SUCCESS; 7613 7614 release: 7615 /* Matches the ufshcd_hold() call at the start of this function. */ 7616 ufshcd_release(hba); 7617 return err; 7618 } 7619 7620 /** 7621 * ufshcd_host_reset_and_restore - reset and restore host controller 7622 * @hba: per-adapter instance 7623 * 7624 * Note that host controller reset may issue DME_RESET to 7625 * local and remote (device) Uni-Pro stack and the attributes 7626 * are reset to default state. 7627 * 7628 * Return: zero on success, non-zero on failure. 7629 */ 7630 static int ufshcd_host_reset_and_restore(struct ufs_hba *hba) 7631 { 7632 int err; 7633 7634 /* 7635 * Stop the host controller and complete the requests 7636 * cleared by h/w 7637 */ 7638 ufshcd_hba_stop(hba); 7639 hba->silence_err_logs = true; 7640 ufshcd_complete_requests(hba, true); 7641 hba->silence_err_logs = false; 7642 7643 /* scale up clocks to max frequency before full reinitialization */ 7644 ufshcd_scale_clks(hba, true); 7645 7646 err = ufshcd_hba_enable(hba); 7647 7648 /* Establish the link again and restore the device */ 7649 if (!err) 7650 err = ufshcd_probe_hba(hba, false); 7651 7652 if (err) 7653 dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err); 7654 ufshcd_update_evt_hist(hba, UFS_EVT_HOST_RESET, (u32)err); 7655 return err; 7656 } 7657 7658 /** 7659 * ufshcd_reset_and_restore - reset and re-initialize host/device 7660 * @hba: per-adapter instance 7661 * 7662 * Reset and recover device, host and re-establish link. This 7663 * is helpful to recover the communication in fatal error conditions. 7664 * 7665 * Return: zero on success, non-zero on failure. 7666 */ 7667 static int ufshcd_reset_and_restore(struct ufs_hba *hba) 7668 { 7669 u32 saved_err = 0; 7670 u32 saved_uic_err = 0; 7671 int err = 0; 7672 unsigned long flags; 7673 int retries = MAX_HOST_RESET_RETRIES; 7674 7675 spin_lock_irqsave(hba->host->host_lock, flags); 7676 do { 7677 /* 7678 * This is a fresh start, cache and clear saved error first, 7679 * in case new error generated during reset and restore. 7680 */ 7681 saved_err |= hba->saved_err; 7682 saved_uic_err |= hba->saved_uic_err; 7683 hba->saved_err = 0; 7684 hba->saved_uic_err = 0; 7685 hba->force_reset = false; 7686 hba->ufshcd_state = UFSHCD_STATE_RESET; 7687 spin_unlock_irqrestore(hba->host->host_lock, flags); 7688 7689 /* Reset the attached device */ 7690 ufshcd_device_reset(hba); 7691 7692 err = ufshcd_host_reset_and_restore(hba); 7693 7694 spin_lock_irqsave(hba->host->host_lock, flags); 7695 if (err) 7696 continue; 7697 /* Do not exit unless operational or dead */ 7698 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL && 7699 hba->ufshcd_state != UFSHCD_STATE_ERROR && 7700 hba->ufshcd_state != UFSHCD_STATE_EH_SCHEDULED_NON_FATAL) 7701 err = -EAGAIN; 7702 } while (err && --retries); 7703 7704 /* 7705 * Inform scsi mid-layer that we did reset and allow to handle 7706 * Unit Attention properly. 7707 */ 7708 scsi_report_bus_reset(hba->host, 0); 7709 if (err) { 7710 hba->ufshcd_state = UFSHCD_STATE_ERROR; 7711 hba->saved_err |= saved_err; 7712 hba->saved_uic_err |= saved_uic_err; 7713 } 7714 spin_unlock_irqrestore(hba->host->host_lock, flags); 7715 7716 return err; 7717 } 7718 7719 /** 7720 * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer 7721 * @cmd: SCSI command pointer 7722 * 7723 * Return: SUCCESS or FAILED. 7724 */ 7725 static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd) 7726 { 7727 int err = SUCCESS; 7728 unsigned long flags; 7729 struct ufs_hba *hba; 7730 7731 hba = shost_priv(cmd->device->host); 7732 7733 spin_lock_irqsave(hba->host->host_lock, flags); 7734 hba->force_reset = true; 7735 ufshcd_schedule_eh_work(hba); 7736 dev_err(hba->dev, "%s: reset in progress - 1\n", __func__); 7737 spin_unlock_irqrestore(hba->host->host_lock, flags); 7738 7739 flush_work(&hba->eh_work); 7740 7741 spin_lock_irqsave(hba->host->host_lock, flags); 7742 if (hba->ufshcd_state == UFSHCD_STATE_ERROR) 7743 err = FAILED; 7744 spin_unlock_irqrestore(hba->host->host_lock, flags); 7745 7746 return err; 7747 } 7748 7749 /** 7750 * ufshcd_get_max_icc_level - calculate the ICC level 7751 * @sup_curr_uA: max. current supported by the regulator 7752 * @start_scan: row at the desc table to start scan from 7753 * @buff: power descriptor buffer 7754 * 7755 * Return: calculated max ICC level for specific regulator. 7756 */ 7757 static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan, 7758 const char *buff) 7759 { 7760 int i; 7761 int curr_uA; 7762 u16 data; 7763 u16 unit; 7764 7765 for (i = start_scan; i >= 0; i--) { 7766 data = get_unaligned_be16(&buff[2 * i]); 7767 unit = (data & ATTR_ICC_LVL_UNIT_MASK) >> 7768 ATTR_ICC_LVL_UNIT_OFFSET; 7769 curr_uA = data & ATTR_ICC_LVL_VALUE_MASK; 7770 switch (unit) { 7771 case UFSHCD_NANO_AMP: 7772 curr_uA = curr_uA / 1000; 7773 break; 7774 case UFSHCD_MILI_AMP: 7775 curr_uA = curr_uA * 1000; 7776 break; 7777 case UFSHCD_AMP: 7778 curr_uA = curr_uA * 1000 * 1000; 7779 break; 7780 case UFSHCD_MICRO_AMP: 7781 default: 7782 break; 7783 } 7784 if (sup_curr_uA >= curr_uA) 7785 break; 7786 } 7787 if (i < 0) { 7788 i = 0; 7789 pr_err("%s: Couldn't find valid icc_level = %d", __func__, i); 7790 } 7791 7792 return (u32)i; 7793 } 7794 7795 /** 7796 * ufshcd_find_max_sup_active_icc_level - calculate the max ICC level 7797 * In case regulators are not initialized we'll return 0 7798 * @hba: per-adapter instance 7799 * @desc_buf: power descriptor buffer to extract ICC levels from. 7800 * 7801 * Return: calculated ICC level. 7802 */ 7803 static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba, 7804 const u8 *desc_buf) 7805 { 7806 u32 icc_level = 0; 7807 7808 if (!hba->vreg_info.vcc || !hba->vreg_info.vccq || 7809 !hba->vreg_info.vccq2) { 7810 /* 7811 * Using dev_dbg to avoid messages during runtime PM to avoid 7812 * never-ending cycles of messages written back to storage by 7813 * user space causing runtime resume, causing more messages and 7814 * so on. 7815 */ 7816 dev_dbg(hba->dev, 7817 "%s: Regulator capability was not set, actvIccLevel=%d", 7818 __func__, icc_level); 7819 goto out; 7820 } 7821 7822 if (hba->vreg_info.vcc->max_uA) 7823 icc_level = ufshcd_get_max_icc_level( 7824 hba->vreg_info.vcc->max_uA, 7825 POWER_DESC_MAX_ACTV_ICC_LVLS - 1, 7826 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]); 7827 7828 if (hba->vreg_info.vccq->max_uA) 7829 icc_level = ufshcd_get_max_icc_level( 7830 hba->vreg_info.vccq->max_uA, 7831 icc_level, 7832 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]); 7833 7834 if (hba->vreg_info.vccq2->max_uA) 7835 icc_level = ufshcd_get_max_icc_level( 7836 hba->vreg_info.vccq2->max_uA, 7837 icc_level, 7838 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]); 7839 out: 7840 return icc_level; 7841 } 7842 7843 static void ufshcd_set_active_icc_lvl(struct ufs_hba *hba) 7844 { 7845 int ret; 7846 u8 *desc_buf; 7847 u32 icc_level; 7848 7849 desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL); 7850 if (!desc_buf) 7851 return; 7852 7853 ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_POWER, 0, 0, 7854 desc_buf, QUERY_DESC_MAX_SIZE); 7855 if (ret) { 7856 dev_err(hba->dev, 7857 "%s: Failed reading power descriptor ret = %d", 7858 __func__, ret); 7859 goto out; 7860 } 7861 7862 icc_level = ufshcd_find_max_sup_active_icc_level(hba, desc_buf); 7863 dev_dbg(hba->dev, "%s: setting icc_level 0x%x", __func__, icc_level); 7864 7865 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, 7866 QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0, &icc_level); 7867 7868 if (ret) 7869 dev_err(hba->dev, 7870 "%s: Failed configuring bActiveICCLevel = %d ret = %d", 7871 __func__, icc_level, ret); 7872 7873 out: 7874 kfree(desc_buf); 7875 } 7876 7877 static inline void ufshcd_blk_pm_runtime_init(struct scsi_device *sdev) 7878 { 7879 scsi_autopm_get_device(sdev); 7880 blk_pm_runtime_init(sdev->request_queue, &sdev->sdev_gendev); 7881 if (sdev->rpm_autosuspend) 7882 pm_runtime_set_autosuspend_delay(&sdev->sdev_gendev, 7883 RPM_AUTOSUSPEND_DELAY_MS); 7884 scsi_autopm_put_device(sdev); 7885 } 7886 7887 /** 7888 * ufshcd_scsi_add_wlus - Adds required W-LUs 7889 * @hba: per-adapter instance 7890 * 7891 * UFS device specification requires the UFS devices to support 4 well known 7892 * logical units: 7893 * "REPORT_LUNS" (address: 01h) 7894 * "UFS Device" (address: 50h) 7895 * "RPMB" (address: 44h) 7896 * "BOOT" (address: 30h) 7897 * UFS device's power management needs to be controlled by "POWER CONDITION" 7898 * field of SSU (START STOP UNIT) command. But this "power condition" field 7899 * will take effect only when its sent to "UFS device" well known logical unit 7900 * hence we require the scsi_device instance to represent this logical unit in 7901 * order for the UFS host driver to send the SSU command for power management. 7902 * 7903 * We also require the scsi_device instance for "RPMB" (Replay Protected Memory 7904 * Block) LU so user space process can control this LU. User space may also 7905 * want to have access to BOOT LU. 7906 * 7907 * This function adds scsi device instances for each of all well known LUs 7908 * (except "REPORT LUNS" LU). 7909 * 7910 * Return: zero on success (all required W-LUs are added successfully), 7911 * non-zero error value on failure (if failed to add any of the required W-LU). 7912 */ 7913 static int ufshcd_scsi_add_wlus(struct ufs_hba *hba) 7914 { 7915 int ret = 0; 7916 struct scsi_device *sdev_boot, *sdev_rpmb; 7917 7918 hba->ufs_device_wlun = __scsi_add_device(hba->host, 0, 0, 7919 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL); 7920 if (IS_ERR(hba->ufs_device_wlun)) { 7921 ret = PTR_ERR(hba->ufs_device_wlun); 7922 hba->ufs_device_wlun = NULL; 7923 goto out; 7924 } 7925 scsi_device_put(hba->ufs_device_wlun); 7926 7927 sdev_rpmb = __scsi_add_device(hba->host, 0, 0, 7928 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL); 7929 if (IS_ERR(sdev_rpmb)) { 7930 ret = PTR_ERR(sdev_rpmb); 7931 goto remove_ufs_device_wlun; 7932 } 7933 ufshcd_blk_pm_runtime_init(sdev_rpmb); 7934 scsi_device_put(sdev_rpmb); 7935 7936 sdev_boot = __scsi_add_device(hba->host, 0, 0, 7937 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL); 7938 if (IS_ERR(sdev_boot)) { 7939 dev_err(hba->dev, "%s: BOOT WLUN not found\n", __func__); 7940 } else { 7941 ufshcd_blk_pm_runtime_init(sdev_boot); 7942 scsi_device_put(sdev_boot); 7943 } 7944 goto out; 7945 7946 remove_ufs_device_wlun: 7947 scsi_remove_device(hba->ufs_device_wlun); 7948 out: 7949 return ret; 7950 } 7951 7952 static void ufshcd_wb_probe(struct ufs_hba *hba, const u8 *desc_buf) 7953 { 7954 struct ufs_dev_info *dev_info = &hba->dev_info; 7955 u8 lun; 7956 u32 d_lu_wb_buf_alloc; 7957 u32 ext_ufs_feature; 7958 7959 if (!ufshcd_is_wb_allowed(hba)) 7960 return; 7961 7962 /* 7963 * Probe WB only for UFS-2.2 and UFS-3.1 (and later) devices or 7964 * UFS devices with quirk UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES 7965 * enabled 7966 */ 7967 if (!(dev_info->wspecversion >= 0x310 || 7968 dev_info->wspecversion == 0x220 || 7969 (hba->dev_quirks & UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES))) 7970 goto wb_disabled; 7971 7972 ext_ufs_feature = get_unaligned_be32(desc_buf + 7973 DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP); 7974 7975 if (!(ext_ufs_feature & UFS_DEV_WRITE_BOOSTER_SUP)) 7976 goto wb_disabled; 7977 7978 /* 7979 * WB may be supported but not configured while provisioning. The spec 7980 * says, in dedicated wb buffer mode, a max of 1 lun would have wb 7981 * buffer configured. 7982 */ 7983 dev_info->wb_buffer_type = desc_buf[DEVICE_DESC_PARAM_WB_TYPE]; 7984 7985 dev_info->b_presrv_uspc_en = 7986 desc_buf[DEVICE_DESC_PARAM_WB_PRESRV_USRSPC_EN]; 7987 7988 if (dev_info->wb_buffer_type == WB_BUF_MODE_SHARED) { 7989 if (!get_unaligned_be32(desc_buf + 7990 DEVICE_DESC_PARAM_WB_SHARED_ALLOC_UNITS)) 7991 goto wb_disabled; 7992 } else { 7993 for (lun = 0; lun < UFS_UPIU_MAX_WB_LUN_ID; lun++) { 7994 d_lu_wb_buf_alloc = 0; 7995 ufshcd_read_unit_desc_param(hba, 7996 lun, 7997 UNIT_DESC_PARAM_WB_BUF_ALLOC_UNITS, 7998 (u8 *)&d_lu_wb_buf_alloc, 7999 sizeof(d_lu_wb_buf_alloc)); 8000 if (d_lu_wb_buf_alloc) { 8001 dev_info->wb_dedicated_lu = lun; 8002 break; 8003 } 8004 } 8005 8006 if (!d_lu_wb_buf_alloc) 8007 goto wb_disabled; 8008 } 8009 8010 if (!ufshcd_is_wb_buf_lifetime_available(hba)) 8011 goto wb_disabled; 8012 8013 return; 8014 8015 wb_disabled: 8016 hba->caps &= ~UFSHCD_CAP_WB_EN; 8017 } 8018 8019 static void ufshcd_temp_notif_probe(struct ufs_hba *hba, const u8 *desc_buf) 8020 { 8021 struct ufs_dev_info *dev_info = &hba->dev_info; 8022 u32 ext_ufs_feature; 8023 u8 mask = 0; 8024 8025 if (!(hba->caps & UFSHCD_CAP_TEMP_NOTIF) || dev_info->wspecversion < 0x300) 8026 return; 8027 8028 ext_ufs_feature = get_unaligned_be32(desc_buf + DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP); 8029 8030 if (ext_ufs_feature & UFS_DEV_LOW_TEMP_NOTIF) 8031 mask |= MASK_EE_TOO_LOW_TEMP; 8032 8033 if (ext_ufs_feature & UFS_DEV_HIGH_TEMP_NOTIF) 8034 mask |= MASK_EE_TOO_HIGH_TEMP; 8035 8036 if (mask) { 8037 ufshcd_enable_ee(hba, mask); 8038 ufs_hwmon_probe(hba, mask); 8039 } 8040 } 8041 8042 static void ufshcd_ext_iid_probe(struct ufs_hba *hba, u8 *desc_buf) 8043 { 8044 struct ufs_dev_info *dev_info = &hba->dev_info; 8045 u32 ext_ufs_feature; 8046 u32 ext_iid_en = 0; 8047 int err; 8048 8049 /* Only UFS-4.0 and above may support EXT_IID */ 8050 if (dev_info->wspecversion < 0x400) 8051 goto out; 8052 8053 ext_ufs_feature = get_unaligned_be32(desc_buf + 8054 DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP); 8055 if (!(ext_ufs_feature & UFS_DEV_EXT_IID_SUP)) 8056 goto out; 8057 8058 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 8059 QUERY_ATTR_IDN_EXT_IID_EN, 0, 0, &ext_iid_en); 8060 if (err) 8061 dev_err(hba->dev, "failed reading bEXTIIDEn. err = %d\n", err); 8062 8063 out: 8064 dev_info->b_ext_iid_en = ext_iid_en; 8065 } 8066 8067 void ufshcd_fixup_dev_quirks(struct ufs_hba *hba, 8068 const struct ufs_dev_quirk *fixups) 8069 { 8070 const struct ufs_dev_quirk *f; 8071 struct ufs_dev_info *dev_info = &hba->dev_info; 8072 8073 if (!fixups) 8074 return; 8075 8076 for (f = fixups; f->quirk; f++) { 8077 if ((f->wmanufacturerid == dev_info->wmanufacturerid || 8078 f->wmanufacturerid == UFS_ANY_VENDOR) && 8079 ((dev_info->model && 8080 STR_PRFX_EQUAL(f->model, dev_info->model)) || 8081 !strcmp(f->model, UFS_ANY_MODEL))) 8082 hba->dev_quirks |= f->quirk; 8083 } 8084 } 8085 EXPORT_SYMBOL_GPL(ufshcd_fixup_dev_quirks); 8086 8087 static void ufs_fixup_device_setup(struct ufs_hba *hba) 8088 { 8089 /* fix by general quirk table */ 8090 ufshcd_fixup_dev_quirks(hba, ufs_fixups); 8091 8092 /* allow vendors to fix quirks */ 8093 ufshcd_vops_fixup_dev_quirks(hba); 8094 } 8095 8096 static int ufs_get_device_desc(struct ufs_hba *hba) 8097 { 8098 int err; 8099 u8 model_index; 8100 u8 *desc_buf; 8101 struct ufs_dev_info *dev_info = &hba->dev_info; 8102 8103 desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL); 8104 if (!desc_buf) { 8105 err = -ENOMEM; 8106 goto out; 8107 } 8108 8109 err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_DEVICE, 0, 0, desc_buf, 8110 QUERY_DESC_MAX_SIZE); 8111 if (err) { 8112 dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n", 8113 __func__, err); 8114 goto out; 8115 } 8116 8117 /* 8118 * getting vendor (manufacturerID) and Bank Index in big endian 8119 * format 8120 */ 8121 dev_info->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 | 8122 desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1]; 8123 8124 /* getting Specification Version in big endian format */ 8125 dev_info->wspecversion = desc_buf[DEVICE_DESC_PARAM_SPEC_VER] << 8 | 8126 desc_buf[DEVICE_DESC_PARAM_SPEC_VER + 1]; 8127 dev_info->bqueuedepth = desc_buf[DEVICE_DESC_PARAM_Q_DPTH]; 8128 8129 model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME]; 8130 8131 err = ufshcd_read_string_desc(hba, model_index, 8132 &dev_info->model, SD_ASCII_STD); 8133 if (err < 0) { 8134 dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n", 8135 __func__, err); 8136 goto out; 8137 } 8138 8139 hba->luns_avail = desc_buf[DEVICE_DESC_PARAM_NUM_LU] + 8140 desc_buf[DEVICE_DESC_PARAM_NUM_WLU]; 8141 8142 ufs_fixup_device_setup(hba); 8143 8144 ufshcd_wb_probe(hba, desc_buf); 8145 8146 ufshcd_temp_notif_probe(hba, desc_buf); 8147 8148 if (hba->ext_iid_sup) 8149 ufshcd_ext_iid_probe(hba, desc_buf); 8150 8151 /* 8152 * ufshcd_read_string_desc returns size of the string 8153 * reset the error value 8154 */ 8155 err = 0; 8156 8157 out: 8158 kfree(desc_buf); 8159 return err; 8160 } 8161 8162 static void ufs_put_device_desc(struct ufs_hba *hba) 8163 { 8164 struct ufs_dev_info *dev_info = &hba->dev_info; 8165 8166 kfree(dev_info->model); 8167 dev_info->model = NULL; 8168 } 8169 8170 /** 8171 * ufshcd_tune_pa_tactivate - Tunes PA_TActivate of local UniPro 8172 * @hba: per-adapter instance 8173 * 8174 * PA_TActivate parameter can be tuned manually if UniPro version is less than 8175 * 1.61. PA_TActivate needs to be greater than or equal to peerM-PHY's 8176 * RX_MIN_ACTIVATETIME_CAPABILITY attribute. This optimal value can help reduce 8177 * the hibern8 exit latency. 8178 * 8179 * Return: zero on success, non-zero error value on failure. 8180 */ 8181 static int ufshcd_tune_pa_tactivate(struct ufs_hba *hba) 8182 { 8183 int ret = 0; 8184 u32 peer_rx_min_activatetime = 0, tuned_pa_tactivate; 8185 8186 ret = ufshcd_dme_peer_get(hba, 8187 UIC_ARG_MIB_SEL( 8188 RX_MIN_ACTIVATETIME_CAPABILITY, 8189 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)), 8190 &peer_rx_min_activatetime); 8191 if (ret) 8192 goto out; 8193 8194 /* make sure proper unit conversion is applied */ 8195 tuned_pa_tactivate = 8196 ((peer_rx_min_activatetime * RX_MIN_ACTIVATETIME_UNIT_US) 8197 / PA_TACTIVATE_TIME_UNIT_US); 8198 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 8199 tuned_pa_tactivate); 8200 8201 out: 8202 return ret; 8203 } 8204 8205 /** 8206 * ufshcd_tune_pa_hibern8time - Tunes PA_Hibern8Time of local UniPro 8207 * @hba: per-adapter instance 8208 * 8209 * PA_Hibern8Time parameter can be tuned manually if UniPro version is less than 8210 * 1.61. PA_Hibern8Time needs to be maximum of local M-PHY's 8211 * TX_HIBERN8TIME_CAPABILITY & peer M-PHY's RX_HIBERN8TIME_CAPABILITY. 8212 * This optimal value can help reduce the hibern8 exit latency. 8213 * 8214 * Return: zero on success, non-zero error value on failure. 8215 */ 8216 static int ufshcd_tune_pa_hibern8time(struct ufs_hba *hba) 8217 { 8218 int ret = 0; 8219 u32 local_tx_hibern8_time_cap = 0, peer_rx_hibern8_time_cap = 0; 8220 u32 max_hibern8_time, tuned_pa_hibern8time; 8221 8222 ret = ufshcd_dme_get(hba, 8223 UIC_ARG_MIB_SEL(TX_HIBERN8TIME_CAPABILITY, 8224 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), 8225 &local_tx_hibern8_time_cap); 8226 if (ret) 8227 goto out; 8228 8229 ret = ufshcd_dme_peer_get(hba, 8230 UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAPABILITY, 8231 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)), 8232 &peer_rx_hibern8_time_cap); 8233 if (ret) 8234 goto out; 8235 8236 max_hibern8_time = max(local_tx_hibern8_time_cap, 8237 peer_rx_hibern8_time_cap); 8238 /* make sure proper unit conversion is applied */ 8239 tuned_pa_hibern8time = ((max_hibern8_time * HIBERN8TIME_UNIT_US) 8240 / PA_HIBERN8_TIME_UNIT_US); 8241 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME), 8242 tuned_pa_hibern8time); 8243 out: 8244 return ret; 8245 } 8246 8247 /** 8248 * ufshcd_quirk_tune_host_pa_tactivate - Ensures that host PA_TACTIVATE is 8249 * less than device PA_TACTIVATE time. 8250 * @hba: per-adapter instance 8251 * 8252 * Some UFS devices require host PA_TACTIVATE to be lower than device 8253 * PA_TACTIVATE, we need to enable UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE quirk 8254 * for such devices. 8255 * 8256 * Return: zero on success, non-zero error value on failure. 8257 */ 8258 static int ufshcd_quirk_tune_host_pa_tactivate(struct ufs_hba *hba) 8259 { 8260 int ret = 0; 8261 u32 granularity, peer_granularity; 8262 u32 pa_tactivate, peer_pa_tactivate; 8263 u32 pa_tactivate_us, peer_pa_tactivate_us; 8264 static const u8 gran_to_us_table[] = {1, 4, 8, 16, 32, 100}; 8265 8266 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY), 8267 &granularity); 8268 if (ret) 8269 goto out; 8270 8271 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY), 8272 &peer_granularity); 8273 if (ret) 8274 goto out; 8275 8276 if ((granularity < PA_GRANULARITY_MIN_VAL) || 8277 (granularity > PA_GRANULARITY_MAX_VAL)) { 8278 dev_err(hba->dev, "%s: invalid host PA_GRANULARITY %d", 8279 __func__, granularity); 8280 return -EINVAL; 8281 } 8282 8283 if ((peer_granularity < PA_GRANULARITY_MIN_VAL) || 8284 (peer_granularity > PA_GRANULARITY_MAX_VAL)) { 8285 dev_err(hba->dev, "%s: invalid device PA_GRANULARITY %d", 8286 __func__, peer_granularity); 8287 return -EINVAL; 8288 } 8289 8290 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate); 8291 if (ret) 8292 goto out; 8293 8294 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE), 8295 &peer_pa_tactivate); 8296 if (ret) 8297 goto out; 8298 8299 pa_tactivate_us = pa_tactivate * gran_to_us_table[granularity - 1]; 8300 peer_pa_tactivate_us = peer_pa_tactivate * 8301 gran_to_us_table[peer_granularity - 1]; 8302 8303 if (pa_tactivate_us >= peer_pa_tactivate_us) { 8304 u32 new_peer_pa_tactivate; 8305 8306 new_peer_pa_tactivate = pa_tactivate_us / 8307 gran_to_us_table[peer_granularity - 1]; 8308 new_peer_pa_tactivate++; 8309 ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 8310 new_peer_pa_tactivate); 8311 } 8312 8313 out: 8314 return ret; 8315 } 8316 8317 static void ufshcd_tune_unipro_params(struct ufs_hba *hba) 8318 { 8319 if (ufshcd_is_unipro_pa_params_tuning_req(hba)) { 8320 ufshcd_tune_pa_tactivate(hba); 8321 ufshcd_tune_pa_hibern8time(hba); 8322 } 8323 8324 ufshcd_vops_apply_dev_quirks(hba); 8325 8326 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TACTIVATE) 8327 /* set 1ms timeout for PA_TACTIVATE */ 8328 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 10); 8329 8330 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE) 8331 ufshcd_quirk_tune_host_pa_tactivate(hba); 8332 } 8333 8334 static void ufshcd_clear_dbg_ufs_stats(struct ufs_hba *hba) 8335 { 8336 hba->ufs_stats.hibern8_exit_cnt = 0; 8337 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0); 8338 hba->req_abort_count = 0; 8339 } 8340 8341 static int ufshcd_device_geo_params_init(struct ufs_hba *hba) 8342 { 8343 int err; 8344 u8 *desc_buf; 8345 8346 desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL); 8347 if (!desc_buf) { 8348 err = -ENOMEM; 8349 goto out; 8350 } 8351 8352 err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_GEOMETRY, 0, 0, 8353 desc_buf, QUERY_DESC_MAX_SIZE); 8354 if (err) { 8355 dev_err(hba->dev, "%s: Failed reading Geometry Desc. err = %d\n", 8356 __func__, err); 8357 goto out; 8358 } 8359 8360 if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 1) 8361 hba->dev_info.max_lu_supported = 32; 8362 else if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 0) 8363 hba->dev_info.max_lu_supported = 8; 8364 8365 out: 8366 kfree(desc_buf); 8367 return err; 8368 } 8369 8370 struct ufs_ref_clk { 8371 unsigned long freq_hz; 8372 enum ufs_ref_clk_freq val; 8373 }; 8374 8375 static const struct ufs_ref_clk ufs_ref_clk_freqs[] = { 8376 {19200000, REF_CLK_FREQ_19_2_MHZ}, 8377 {26000000, REF_CLK_FREQ_26_MHZ}, 8378 {38400000, REF_CLK_FREQ_38_4_MHZ}, 8379 {52000000, REF_CLK_FREQ_52_MHZ}, 8380 {0, REF_CLK_FREQ_INVAL}, 8381 }; 8382 8383 static enum ufs_ref_clk_freq 8384 ufs_get_bref_clk_from_hz(unsigned long freq) 8385 { 8386 int i; 8387 8388 for (i = 0; ufs_ref_clk_freqs[i].freq_hz; i++) 8389 if (ufs_ref_clk_freqs[i].freq_hz == freq) 8390 return ufs_ref_clk_freqs[i].val; 8391 8392 return REF_CLK_FREQ_INVAL; 8393 } 8394 8395 void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk) 8396 { 8397 unsigned long freq; 8398 8399 freq = clk_get_rate(refclk); 8400 8401 hba->dev_ref_clk_freq = 8402 ufs_get_bref_clk_from_hz(freq); 8403 8404 if (hba->dev_ref_clk_freq == REF_CLK_FREQ_INVAL) 8405 dev_err(hba->dev, 8406 "invalid ref_clk setting = %ld\n", freq); 8407 } 8408 8409 static int ufshcd_set_dev_ref_clk(struct ufs_hba *hba) 8410 { 8411 int err; 8412 u32 ref_clk; 8413 u32 freq = hba->dev_ref_clk_freq; 8414 8415 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 8416 QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &ref_clk); 8417 8418 if (err) { 8419 dev_err(hba->dev, "failed reading bRefClkFreq. err = %d\n", 8420 err); 8421 goto out; 8422 } 8423 8424 if (ref_clk == freq) 8425 goto out; /* nothing to update */ 8426 8427 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, 8428 QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &freq); 8429 8430 if (err) { 8431 dev_err(hba->dev, "bRefClkFreq setting to %lu Hz failed\n", 8432 ufs_ref_clk_freqs[freq].freq_hz); 8433 goto out; 8434 } 8435 8436 dev_dbg(hba->dev, "bRefClkFreq setting to %lu Hz succeeded\n", 8437 ufs_ref_clk_freqs[freq].freq_hz); 8438 8439 out: 8440 return err; 8441 } 8442 8443 static int ufshcd_device_params_init(struct ufs_hba *hba) 8444 { 8445 bool flag; 8446 int ret; 8447 8448 /* Init UFS geometry descriptor related parameters */ 8449 ret = ufshcd_device_geo_params_init(hba); 8450 if (ret) 8451 goto out; 8452 8453 /* Check and apply UFS device quirks */ 8454 ret = ufs_get_device_desc(hba); 8455 if (ret) { 8456 dev_err(hba->dev, "%s: Failed getting device info. err = %d\n", 8457 __func__, ret); 8458 goto out; 8459 } 8460 8461 ufshcd_get_ref_clk_gating_wait(hba); 8462 8463 if (!ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG, 8464 QUERY_FLAG_IDN_PWR_ON_WPE, 0, &flag)) 8465 hba->dev_info.f_power_on_wp_en = flag; 8466 8467 /* Probe maximum power mode co-supported by both UFS host and device */ 8468 if (ufshcd_get_max_pwr_mode(hba)) 8469 dev_err(hba->dev, 8470 "%s: Failed getting max supported power mode\n", 8471 __func__); 8472 out: 8473 return ret; 8474 } 8475 8476 static void ufshcd_set_timestamp_attr(struct ufs_hba *hba) 8477 { 8478 int err; 8479 struct ufs_query_req *request = NULL; 8480 struct ufs_query_res *response = NULL; 8481 struct ufs_dev_info *dev_info = &hba->dev_info; 8482 struct utp_upiu_query_v4_0 *upiu_data; 8483 8484 if (dev_info->wspecversion < 0x400) 8485 return; 8486 8487 ufshcd_hold(hba); 8488 8489 mutex_lock(&hba->dev_cmd.lock); 8490 8491 ufshcd_init_query(hba, &request, &response, 8492 UPIU_QUERY_OPCODE_WRITE_ATTR, 8493 QUERY_ATTR_IDN_TIMESTAMP, 0, 0); 8494 8495 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 8496 8497 upiu_data = (struct utp_upiu_query_v4_0 *)&request->upiu_req; 8498 8499 put_unaligned_be64(ktime_get_real_ns(), &upiu_data->osf3); 8500 8501 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT); 8502 8503 if (err) 8504 dev_err(hba->dev, "%s: failed to set timestamp %d\n", 8505 __func__, err); 8506 8507 mutex_unlock(&hba->dev_cmd.lock); 8508 ufshcd_release(hba); 8509 } 8510 8511 /** 8512 * ufshcd_add_lus - probe and add UFS logical units 8513 * @hba: per-adapter instance 8514 * 8515 * Return: 0 upon success; < 0 upon failure. 8516 */ 8517 static int ufshcd_add_lus(struct ufs_hba *hba) 8518 { 8519 int ret; 8520 8521 /* Add required well known logical units to scsi mid layer */ 8522 ret = ufshcd_scsi_add_wlus(hba); 8523 if (ret) 8524 goto out; 8525 8526 /* Initialize devfreq after UFS device is detected */ 8527 if (ufshcd_is_clkscaling_supported(hba)) { 8528 memcpy(&hba->clk_scaling.saved_pwr_info, 8529 &hba->pwr_info, 8530 sizeof(struct ufs_pa_layer_attr)); 8531 hba->clk_scaling.is_allowed = true; 8532 8533 ret = ufshcd_devfreq_init(hba); 8534 if (ret) 8535 goto out; 8536 8537 hba->clk_scaling.is_enabled = true; 8538 ufshcd_init_clk_scaling_sysfs(hba); 8539 } 8540 8541 ufs_bsg_probe(hba); 8542 scsi_scan_host(hba->host); 8543 pm_runtime_put_sync(hba->dev); 8544 8545 out: 8546 return ret; 8547 } 8548 8549 /* SDB - Single Doorbell */ 8550 static void ufshcd_release_sdb_queue(struct ufs_hba *hba, int nutrs) 8551 { 8552 size_t ucdl_size, utrdl_size; 8553 8554 ucdl_size = ufshcd_get_ucd_size(hba) * nutrs; 8555 dmam_free_coherent(hba->dev, ucdl_size, hba->ucdl_base_addr, 8556 hba->ucdl_dma_addr); 8557 8558 utrdl_size = sizeof(struct utp_transfer_req_desc) * nutrs; 8559 dmam_free_coherent(hba->dev, utrdl_size, hba->utrdl_base_addr, 8560 hba->utrdl_dma_addr); 8561 8562 devm_kfree(hba->dev, hba->lrb); 8563 } 8564 8565 static int ufshcd_alloc_mcq(struct ufs_hba *hba) 8566 { 8567 int ret; 8568 int old_nutrs = hba->nutrs; 8569 8570 ret = ufshcd_mcq_decide_queue_depth(hba); 8571 if (ret < 0) 8572 return ret; 8573 8574 hba->nutrs = ret; 8575 ret = ufshcd_mcq_init(hba); 8576 if (ret) 8577 goto err; 8578 8579 /* 8580 * Previously allocated memory for nutrs may not be enough in MCQ mode. 8581 * Number of supported tags in MCQ mode may be larger than SDB mode. 8582 */ 8583 if (hba->nutrs != old_nutrs) { 8584 ufshcd_release_sdb_queue(hba, old_nutrs); 8585 ret = ufshcd_memory_alloc(hba); 8586 if (ret) 8587 goto err; 8588 ufshcd_host_memory_configure(hba); 8589 } 8590 8591 ret = ufshcd_mcq_memory_alloc(hba); 8592 if (ret) 8593 goto err; 8594 8595 return 0; 8596 err: 8597 hba->nutrs = old_nutrs; 8598 return ret; 8599 } 8600 8601 static void ufshcd_config_mcq(struct ufs_hba *hba) 8602 { 8603 int ret; 8604 u32 intrs; 8605 8606 ret = ufshcd_mcq_vops_config_esi(hba); 8607 dev_info(hba->dev, "ESI %sconfigured\n", ret ? "is not " : ""); 8608 8609 intrs = UFSHCD_ENABLE_MCQ_INTRS; 8610 if (hba->quirks & UFSHCD_QUIRK_MCQ_BROKEN_INTR) 8611 intrs &= ~MCQ_CQ_EVENT_STATUS; 8612 ufshcd_enable_intr(hba, intrs); 8613 ufshcd_mcq_make_queues_operational(hba); 8614 ufshcd_mcq_config_mac(hba, hba->nutrs); 8615 8616 hba->host->can_queue = hba->nutrs - UFSHCD_NUM_RESERVED; 8617 hba->reserved_slot = hba->nutrs - UFSHCD_NUM_RESERVED; 8618 8619 /* Select MCQ mode */ 8620 ufshcd_writel(hba, ufshcd_readl(hba, REG_UFS_MEM_CFG) | 0x1, 8621 REG_UFS_MEM_CFG); 8622 hba->mcq_enabled = true; 8623 8624 dev_info(hba->dev, "MCQ configured, nr_queues=%d, io_queues=%d, read_queue=%d, poll_queues=%d, queue_depth=%d\n", 8625 hba->nr_hw_queues, hba->nr_queues[HCTX_TYPE_DEFAULT], 8626 hba->nr_queues[HCTX_TYPE_READ], hba->nr_queues[HCTX_TYPE_POLL], 8627 hba->nutrs); 8628 } 8629 8630 static int ufshcd_device_init(struct ufs_hba *hba, bool init_dev_params) 8631 { 8632 int ret; 8633 struct Scsi_Host *host = hba->host; 8634 8635 hba->ufshcd_state = UFSHCD_STATE_RESET; 8636 8637 ret = ufshcd_link_startup(hba); 8638 if (ret) 8639 return ret; 8640 8641 if (hba->quirks & UFSHCD_QUIRK_SKIP_PH_CONFIGURATION) 8642 return ret; 8643 8644 /* Debug counters initialization */ 8645 ufshcd_clear_dbg_ufs_stats(hba); 8646 8647 /* UniPro link is active now */ 8648 ufshcd_set_link_active(hba); 8649 8650 /* Reconfigure MCQ upon reset */ 8651 if (is_mcq_enabled(hba) && !init_dev_params) 8652 ufshcd_config_mcq(hba); 8653 8654 /* Verify device initialization by sending NOP OUT UPIU */ 8655 ret = ufshcd_verify_dev_init(hba); 8656 if (ret) 8657 return ret; 8658 8659 /* Initiate UFS initialization, and waiting until completion */ 8660 ret = ufshcd_complete_dev_init(hba); 8661 if (ret) 8662 return ret; 8663 8664 /* 8665 * Initialize UFS device parameters used by driver, these 8666 * parameters are associated with UFS descriptors. 8667 */ 8668 if (init_dev_params) { 8669 ret = ufshcd_device_params_init(hba); 8670 if (ret) 8671 return ret; 8672 if (is_mcq_supported(hba) && !hba->scsi_host_added) { 8673 ret = ufshcd_alloc_mcq(hba); 8674 if (!ret) { 8675 ufshcd_config_mcq(hba); 8676 } else { 8677 /* Continue with SDB mode */ 8678 use_mcq_mode = false; 8679 dev_err(hba->dev, "MCQ mode is disabled, err=%d\n", 8680 ret); 8681 } 8682 ret = scsi_add_host(host, hba->dev); 8683 if (ret) { 8684 dev_err(hba->dev, "scsi_add_host failed\n"); 8685 return ret; 8686 } 8687 hba->scsi_host_added = true; 8688 } else if (is_mcq_supported(hba)) { 8689 /* UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH is set */ 8690 ufshcd_config_mcq(hba); 8691 } 8692 } 8693 8694 ufshcd_tune_unipro_params(hba); 8695 8696 /* UFS device is also active now */ 8697 ufshcd_set_ufs_dev_active(hba); 8698 ufshcd_force_reset_auto_bkops(hba); 8699 8700 ufshcd_set_timestamp_attr(hba); 8701 8702 /* Gear up to HS gear if supported */ 8703 if (hba->max_pwr_info.is_valid) { 8704 /* 8705 * Set the right value to bRefClkFreq before attempting to 8706 * switch to HS gears. 8707 */ 8708 if (hba->dev_ref_clk_freq != REF_CLK_FREQ_INVAL) 8709 ufshcd_set_dev_ref_clk(hba); 8710 ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info); 8711 if (ret) { 8712 dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n", 8713 __func__, ret); 8714 return ret; 8715 } 8716 } 8717 8718 return 0; 8719 } 8720 8721 /** 8722 * ufshcd_probe_hba - probe hba to detect device and initialize it 8723 * @hba: per-adapter instance 8724 * @init_dev_params: whether or not to call ufshcd_device_params_init(). 8725 * 8726 * Execute link-startup and verify device initialization 8727 * 8728 * Return: 0 upon success; < 0 upon failure. 8729 */ 8730 static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params) 8731 { 8732 ktime_t start = ktime_get(); 8733 unsigned long flags; 8734 int ret; 8735 8736 ret = ufshcd_device_init(hba, init_dev_params); 8737 if (ret) 8738 goto out; 8739 8740 if (!hba->pm_op_in_progress && 8741 (hba->quirks & UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH)) { 8742 /* Reset the device and controller before doing reinit */ 8743 ufshcd_device_reset(hba); 8744 ufshcd_hba_stop(hba); 8745 ufshcd_vops_reinit_notify(hba); 8746 ret = ufshcd_hba_enable(hba); 8747 if (ret) { 8748 dev_err(hba->dev, "Host controller enable failed\n"); 8749 ufshcd_print_evt_hist(hba); 8750 ufshcd_print_host_state(hba); 8751 goto out; 8752 } 8753 8754 /* Reinit the device */ 8755 ret = ufshcd_device_init(hba, init_dev_params); 8756 if (ret) 8757 goto out; 8758 } 8759 8760 ufshcd_print_pwr_info(hba); 8761 8762 /* 8763 * bActiveICCLevel is volatile for UFS device (as per latest v2.1 spec) 8764 * and for removable UFS card as well, hence always set the parameter. 8765 * Note: Error handler may issue the device reset hence resetting 8766 * bActiveICCLevel as well so it is always safe to set this here. 8767 */ 8768 ufshcd_set_active_icc_lvl(hba); 8769 8770 /* Enable UFS Write Booster if supported */ 8771 ufshcd_configure_wb(hba); 8772 8773 if (hba->ee_usr_mask) 8774 ufshcd_write_ee_control(hba); 8775 /* Enable Auto-Hibernate if configured */ 8776 ufshcd_auto_hibern8_enable(hba); 8777 8778 out: 8779 spin_lock_irqsave(hba->host->host_lock, flags); 8780 if (ret) 8781 hba->ufshcd_state = UFSHCD_STATE_ERROR; 8782 else if (hba->ufshcd_state == UFSHCD_STATE_RESET) 8783 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL; 8784 spin_unlock_irqrestore(hba->host->host_lock, flags); 8785 8786 trace_ufshcd_init(dev_name(hba->dev), ret, 8787 ktime_to_us(ktime_sub(ktime_get(), start)), 8788 hba->curr_dev_pwr_mode, hba->uic_link_state); 8789 return ret; 8790 } 8791 8792 /** 8793 * ufshcd_async_scan - asynchronous execution for probing hba 8794 * @data: data pointer to pass to this function 8795 * @cookie: cookie data 8796 */ 8797 static void ufshcd_async_scan(void *data, async_cookie_t cookie) 8798 { 8799 struct ufs_hba *hba = (struct ufs_hba *)data; 8800 int ret; 8801 8802 down(&hba->host_sem); 8803 /* Initialize hba, detect and initialize UFS device */ 8804 ret = ufshcd_probe_hba(hba, true); 8805 up(&hba->host_sem); 8806 if (ret) 8807 goto out; 8808 8809 /* Probe and add UFS logical units */ 8810 ret = ufshcd_add_lus(hba); 8811 out: 8812 /* 8813 * If we failed to initialize the device or the device is not 8814 * present, turn off the power/clocks etc. 8815 */ 8816 if (ret) { 8817 pm_runtime_put_sync(hba->dev); 8818 ufshcd_hba_exit(hba); 8819 } 8820 } 8821 8822 static enum scsi_timeout_action ufshcd_eh_timed_out(struct scsi_cmnd *scmd) 8823 { 8824 struct ufs_hba *hba = shost_priv(scmd->device->host); 8825 8826 if (!hba->system_suspending) { 8827 /* Activate the error handler in the SCSI core. */ 8828 return SCSI_EH_NOT_HANDLED; 8829 } 8830 8831 /* 8832 * If we get here we know that no TMFs are outstanding and also that 8833 * the only pending command is a START STOP UNIT command. Handle the 8834 * timeout of that command directly to prevent a deadlock between 8835 * ufshcd_set_dev_pwr_mode() and ufshcd_err_handler(). 8836 */ 8837 ufshcd_link_recovery(hba); 8838 dev_info(hba->dev, "%s() finished; outstanding_tasks = %#lx.\n", 8839 __func__, hba->outstanding_tasks); 8840 8841 return hba->outstanding_reqs ? SCSI_EH_RESET_TIMER : SCSI_EH_DONE; 8842 } 8843 8844 static const struct attribute_group *ufshcd_driver_groups[] = { 8845 &ufs_sysfs_unit_descriptor_group, 8846 &ufs_sysfs_lun_attributes_group, 8847 NULL, 8848 }; 8849 8850 static struct ufs_hba_variant_params ufs_hba_vps = { 8851 .hba_enable_delay_us = 1000, 8852 .wb_flush_threshold = UFS_WB_BUF_REMAIN_PERCENT(40), 8853 .devfreq_profile.polling_ms = 100, 8854 .devfreq_profile.target = ufshcd_devfreq_target, 8855 .devfreq_profile.get_dev_status = ufshcd_devfreq_get_dev_status, 8856 .ondemand_data.upthreshold = 70, 8857 .ondemand_data.downdifferential = 5, 8858 }; 8859 8860 static const struct scsi_host_template ufshcd_driver_template = { 8861 .module = THIS_MODULE, 8862 .name = UFSHCD, 8863 .proc_name = UFSHCD, 8864 .map_queues = ufshcd_map_queues, 8865 .queuecommand = ufshcd_queuecommand, 8866 .mq_poll = ufshcd_poll, 8867 .slave_alloc = ufshcd_slave_alloc, 8868 .slave_configure = ufshcd_slave_configure, 8869 .slave_destroy = ufshcd_slave_destroy, 8870 .change_queue_depth = ufshcd_change_queue_depth, 8871 .eh_abort_handler = ufshcd_abort, 8872 .eh_device_reset_handler = ufshcd_eh_device_reset_handler, 8873 .eh_host_reset_handler = ufshcd_eh_host_reset_handler, 8874 .eh_timed_out = ufshcd_eh_timed_out, 8875 .this_id = -1, 8876 .sg_tablesize = SG_ALL, 8877 .cmd_per_lun = UFSHCD_CMD_PER_LUN, 8878 .can_queue = UFSHCD_CAN_QUEUE, 8879 .max_segment_size = PRDT_DATA_BYTE_COUNT_MAX, 8880 .max_sectors = SZ_1M / SECTOR_SIZE, 8881 .max_host_blocked = 1, 8882 .track_queue_depth = 1, 8883 .skip_settle_delay = 1, 8884 .sdev_groups = ufshcd_driver_groups, 8885 .rpm_autosuspend_delay = RPM_AUTOSUSPEND_DELAY_MS, 8886 }; 8887 8888 static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg, 8889 int ua) 8890 { 8891 int ret; 8892 8893 if (!vreg) 8894 return 0; 8895 8896 /* 8897 * "set_load" operation shall be required on those regulators 8898 * which specifically configured current limitation. Otherwise 8899 * zero max_uA may cause unexpected behavior when regulator is 8900 * enabled or set as high power mode. 8901 */ 8902 if (!vreg->max_uA) 8903 return 0; 8904 8905 ret = regulator_set_load(vreg->reg, ua); 8906 if (ret < 0) { 8907 dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n", 8908 __func__, vreg->name, ua, ret); 8909 } 8910 8911 return ret; 8912 } 8913 8914 static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba, 8915 struct ufs_vreg *vreg) 8916 { 8917 return ufshcd_config_vreg_load(hba->dev, vreg, UFS_VREG_LPM_LOAD_UA); 8918 } 8919 8920 static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba, 8921 struct ufs_vreg *vreg) 8922 { 8923 if (!vreg) 8924 return 0; 8925 8926 return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA); 8927 } 8928 8929 static int ufshcd_config_vreg(struct device *dev, 8930 struct ufs_vreg *vreg, bool on) 8931 { 8932 if (regulator_count_voltages(vreg->reg) <= 0) 8933 return 0; 8934 8935 return ufshcd_config_vreg_load(dev, vreg, on ? vreg->max_uA : 0); 8936 } 8937 8938 static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg) 8939 { 8940 int ret = 0; 8941 8942 if (!vreg || vreg->enabled) 8943 goto out; 8944 8945 ret = ufshcd_config_vreg(dev, vreg, true); 8946 if (!ret) 8947 ret = regulator_enable(vreg->reg); 8948 8949 if (!ret) 8950 vreg->enabled = true; 8951 else 8952 dev_err(dev, "%s: %s enable failed, err=%d\n", 8953 __func__, vreg->name, ret); 8954 out: 8955 return ret; 8956 } 8957 8958 static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg) 8959 { 8960 int ret = 0; 8961 8962 if (!vreg || !vreg->enabled || vreg->always_on) 8963 goto out; 8964 8965 ret = regulator_disable(vreg->reg); 8966 8967 if (!ret) { 8968 /* ignore errors on applying disable config */ 8969 ufshcd_config_vreg(dev, vreg, false); 8970 vreg->enabled = false; 8971 } else { 8972 dev_err(dev, "%s: %s disable failed, err=%d\n", 8973 __func__, vreg->name, ret); 8974 } 8975 out: 8976 return ret; 8977 } 8978 8979 static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on) 8980 { 8981 int ret = 0; 8982 struct device *dev = hba->dev; 8983 struct ufs_vreg_info *info = &hba->vreg_info; 8984 8985 ret = ufshcd_toggle_vreg(dev, info->vcc, on); 8986 if (ret) 8987 goto out; 8988 8989 ret = ufshcd_toggle_vreg(dev, info->vccq, on); 8990 if (ret) 8991 goto out; 8992 8993 ret = ufshcd_toggle_vreg(dev, info->vccq2, on); 8994 8995 out: 8996 if (ret) { 8997 ufshcd_toggle_vreg(dev, info->vccq2, false); 8998 ufshcd_toggle_vreg(dev, info->vccq, false); 8999 ufshcd_toggle_vreg(dev, info->vcc, false); 9000 } 9001 return ret; 9002 } 9003 9004 static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on) 9005 { 9006 struct ufs_vreg_info *info = &hba->vreg_info; 9007 9008 return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on); 9009 } 9010 9011 int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg) 9012 { 9013 int ret = 0; 9014 9015 if (!vreg) 9016 goto out; 9017 9018 vreg->reg = devm_regulator_get(dev, vreg->name); 9019 if (IS_ERR(vreg->reg)) { 9020 ret = PTR_ERR(vreg->reg); 9021 dev_err(dev, "%s: %s get failed, err=%d\n", 9022 __func__, vreg->name, ret); 9023 } 9024 out: 9025 return ret; 9026 } 9027 EXPORT_SYMBOL_GPL(ufshcd_get_vreg); 9028 9029 static int ufshcd_init_vreg(struct ufs_hba *hba) 9030 { 9031 int ret = 0; 9032 struct device *dev = hba->dev; 9033 struct ufs_vreg_info *info = &hba->vreg_info; 9034 9035 ret = ufshcd_get_vreg(dev, info->vcc); 9036 if (ret) 9037 goto out; 9038 9039 ret = ufshcd_get_vreg(dev, info->vccq); 9040 if (!ret) 9041 ret = ufshcd_get_vreg(dev, info->vccq2); 9042 out: 9043 return ret; 9044 } 9045 9046 static int ufshcd_init_hba_vreg(struct ufs_hba *hba) 9047 { 9048 struct ufs_vreg_info *info = &hba->vreg_info; 9049 9050 return ufshcd_get_vreg(hba->dev, info->vdd_hba); 9051 } 9052 9053 static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on) 9054 { 9055 int ret = 0; 9056 struct ufs_clk_info *clki; 9057 struct list_head *head = &hba->clk_list_head; 9058 unsigned long flags; 9059 ktime_t start = ktime_get(); 9060 bool clk_state_changed = false; 9061 9062 if (list_empty(head)) 9063 goto out; 9064 9065 ret = ufshcd_vops_setup_clocks(hba, on, PRE_CHANGE); 9066 if (ret) 9067 return ret; 9068 9069 list_for_each_entry(clki, head, list) { 9070 if (!IS_ERR_OR_NULL(clki->clk)) { 9071 /* 9072 * Don't disable clocks which are needed 9073 * to keep the link active. 9074 */ 9075 if (ufshcd_is_link_active(hba) && 9076 clki->keep_link_active) 9077 continue; 9078 9079 clk_state_changed = on ^ clki->enabled; 9080 if (on && !clki->enabled) { 9081 ret = clk_prepare_enable(clki->clk); 9082 if (ret) { 9083 dev_err(hba->dev, "%s: %s prepare enable failed, %d\n", 9084 __func__, clki->name, ret); 9085 goto out; 9086 } 9087 } else if (!on && clki->enabled) { 9088 clk_disable_unprepare(clki->clk); 9089 } 9090 clki->enabled = on; 9091 dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__, 9092 clki->name, on ? "en" : "dis"); 9093 } 9094 } 9095 9096 ret = ufshcd_vops_setup_clocks(hba, on, POST_CHANGE); 9097 if (ret) 9098 return ret; 9099 9100 out: 9101 if (ret) { 9102 list_for_each_entry(clki, head, list) { 9103 if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled) 9104 clk_disable_unprepare(clki->clk); 9105 } 9106 } else if (!ret && on) { 9107 spin_lock_irqsave(hba->host->host_lock, flags); 9108 hba->clk_gating.state = CLKS_ON; 9109 trace_ufshcd_clk_gating(dev_name(hba->dev), 9110 hba->clk_gating.state); 9111 spin_unlock_irqrestore(hba->host->host_lock, flags); 9112 } 9113 9114 if (clk_state_changed) 9115 trace_ufshcd_profile_clk_gating(dev_name(hba->dev), 9116 (on ? "on" : "off"), 9117 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 9118 return ret; 9119 } 9120 9121 static enum ufs_ref_clk_freq ufshcd_parse_ref_clk_property(struct ufs_hba *hba) 9122 { 9123 u32 freq; 9124 int ret = device_property_read_u32(hba->dev, "ref-clk-freq", &freq); 9125 9126 if (ret) { 9127 dev_dbg(hba->dev, "Cannot query 'ref-clk-freq' property = %d", ret); 9128 return REF_CLK_FREQ_INVAL; 9129 } 9130 9131 return ufs_get_bref_clk_from_hz(freq); 9132 } 9133 9134 static int ufshcd_init_clocks(struct ufs_hba *hba) 9135 { 9136 int ret = 0; 9137 struct ufs_clk_info *clki; 9138 struct device *dev = hba->dev; 9139 struct list_head *head = &hba->clk_list_head; 9140 9141 if (list_empty(head)) 9142 goto out; 9143 9144 list_for_each_entry(clki, head, list) { 9145 if (!clki->name) 9146 continue; 9147 9148 clki->clk = devm_clk_get(dev, clki->name); 9149 if (IS_ERR(clki->clk)) { 9150 ret = PTR_ERR(clki->clk); 9151 dev_err(dev, "%s: %s clk get failed, %d\n", 9152 __func__, clki->name, ret); 9153 goto out; 9154 } 9155 9156 /* 9157 * Parse device ref clk freq as per device tree "ref_clk". 9158 * Default dev_ref_clk_freq is set to REF_CLK_FREQ_INVAL 9159 * in ufshcd_alloc_host(). 9160 */ 9161 if (!strcmp(clki->name, "ref_clk")) 9162 ufshcd_parse_dev_ref_clk_freq(hba, clki->clk); 9163 9164 if (clki->max_freq) { 9165 ret = clk_set_rate(clki->clk, clki->max_freq); 9166 if (ret) { 9167 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n", 9168 __func__, clki->name, 9169 clki->max_freq, ret); 9170 goto out; 9171 } 9172 clki->curr_freq = clki->max_freq; 9173 } 9174 dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__, 9175 clki->name, clk_get_rate(clki->clk)); 9176 } 9177 out: 9178 return ret; 9179 } 9180 9181 static int ufshcd_variant_hba_init(struct ufs_hba *hba) 9182 { 9183 int err = 0; 9184 9185 if (!hba->vops) 9186 goto out; 9187 9188 err = ufshcd_vops_init(hba); 9189 if (err) 9190 dev_err_probe(hba->dev, err, 9191 "%s: variant %s init failed with err %d\n", 9192 __func__, ufshcd_get_var_name(hba), err); 9193 out: 9194 return err; 9195 } 9196 9197 static void ufshcd_variant_hba_exit(struct ufs_hba *hba) 9198 { 9199 if (!hba->vops) 9200 return; 9201 9202 ufshcd_vops_exit(hba); 9203 } 9204 9205 static int ufshcd_hba_init(struct ufs_hba *hba) 9206 { 9207 int err; 9208 9209 /* 9210 * Handle host controller power separately from the UFS device power 9211 * rails as it will help controlling the UFS host controller power 9212 * collapse easily which is different than UFS device power collapse. 9213 * Also, enable the host controller power before we go ahead with rest 9214 * of the initialization here. 9215 */ 9216 err = ufshcd_init_hba_vreg(hba); 9217 if (err) 9218 goto out; 9219 9220 err = ufshcd_setup_hba_vreg(hba, true); 9221 if (err) 9222 goto out; 9223 9224 err = ufshcd_init_clocks(hba); 9225 if (err) 9226 goto out_disable_hba_vreg; 9227 9228 if (hba->dev_ref_clk_freq == REF_CLK_FREQ_INVAL) 9229 hba->dev_ref_clk_freq = ufshcd_parse_ref_clk_property(hba); 9230 9231 err = ufshcd_setup_clocks(hba, true); 9232 if (err) 9233 goto out_disable_hba_vreg; 9234 9235 err = ufshcd_init_vreg(hba); 9236 if (err) 9237 goto out_disable_clks; 9238 9239 err = ufshcd_setup_vreg(hba, true); 9240 if (err) 9241 goto out_disable_clks; 9242 9243 err = ufshcd_variant_hba_init(hba); 9244 if (err) 9245 goto out_disable_vreg; 9246 9247 ufs_debugfs_hba_init(hba); 9248 9249 hba->is_powered = true; 9250 goto out; 9251 9252 out_disable_vreg: 9253 ufshcd_setup_vreg(hba, false); 9254 out_disable_clks: 9255 ufshcd_setup_clocks(hba, false); 9256 out_disable_hba_vreg: 9257 ufshcd_setup_hba_vreg(hba, false); 9258 out: 9259 return err; 9260 } 9261 9262 static void ufshcd_hba_exit(struct ufs_hba *hba) 9263 { 9264 if (hba->is_powered) { 9265 ufshcd_exit_clk_scaling(hba); 9266 ufshcd_exit_clk_gating(hba); 9267 if (hba->eh_wq) 9268 destroy_workqueue(hba->eh_wq); 9269 ufs_debugfs_hba_exit(hba); 9270 ufshcd_variant_hba_exit(hba); 9271 ufshcd_setup_vreg(hba, false); 9272 ufshcd_setup_clocks(hba, false); 9273 ufshcd_setup_hba_vreg(hba, false); 9274 hba->is_powered = false; 9275 ufs_put_device_desc(hba); 9276 } 9277 } 9278 9279 static int ufshcd_execute_start_stop(struct scsi_device *sdev, 9280 enum ufs_dev_pwr_mode pwr_mode, 9281 struct scsi_sense_hdr *sshdr) 9282 { 9283 const unsigned char cdb[6] = { START_STOP, 0, 0, 0, pwr_mode << 4, 0 }; 9284 const struct scsi_exec_args args = { 9285 .sshdr = sshdr, 9286 .req_flags = BLK_MQ_REQ_PM, 9287 .scmd_flags = SCMD_FAIL_IF_RECOVERING, 9288 }; 9289 9290 return scsi_execute_cmd(sdev, cdb, REQ_OP_DRV_IN, /*buffer=*/NULL, 9291 /*bufflen=*/0, /*timeout=*/10 * HZ, /*retries=*/0, 9292 &args); 9293 } 9294 9295 /** 9296 * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device 9297 * power mode 9298 * @hba: per adapter instance 9299 * @pwr_mode: device power mode to set 9300 * 9301 * Return: 0 if requested power mode is set successfully; 9302 * < 0 if failed to set the requested power mode. 9303 */ 9304 static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba, 9305 enum ufs_dev_pwr_mode pwr_mode) 9306 { 9307 struct scsi_sense_hdr sshdr; 9308 struct scsi_device *sdp; 9309 unsigned long flags; 9310 int ret, retries; 9311 9312 spin_lock_irqsave(hba->host->host_lock, flags); 9313 sdp = hba->ufs_device_wlun; 9314 if (sdp && scsi_device_online(sdp)) 9315 ret = scsi_device_get(sdp); 9316 else 9317 ret = -ENODEV; 9318 spin_unlock_irqrestore(hba->host->host_lock, flags); 9319 9320 if (ret) 9321 return ret; 9322 9323 /* 9324 * If scsi commands fail, the scsi mid-layer schedules scsi error- 9325 * handling, which would wait for host to be resumed. Since we know 9326 * we are functional while we are here, skip host resume in error 9327 * handling context. 9328 */ 9329 hba->host->eh_noresume = 1; 9330 9331 /* 9332 * Current function would be generally called from the power management 9333 * callbacks hence set the RQF_PM flag so that it doesn't resume the 9334 * already suspended childs. 9335 */ 9336 for (retries = 3; retries > 0; --retries) { 9337 ret = ufshcd_execute_start_stop(sdp, pwr_mode, &sshdr); 9338 /* 9339 * scsi_execute() only returns a negative value if the request 9340 * queue is dying. 9341 */ 9342 if (ret <= 0) 9343 break; 9344 } 9345 if (ret) { 9346 sdev_printk(KERN_WARNING, sdp, 9347 "START_STOP failed for power mode: %d, result %x\n", 9348 pwr_mode, ret); 9349 if (ret > 0) { 9350 if (scsi_sense_valid(&sshdr)) 9351 scsi_print_sense_hdr(sdp, NULL, &sshdr); 9352 ret = -EIO; 9353 } 9354 } else { 9355 hba->curr_dev_pwr_mode = pwr_mode; 9356 } 9357 9358 scsi_device_put(sdp); 9359 hba->host->eh_noresume = 0; 9360 return ret; 9361 } 9362 9363 static int ufshcd_link_state_transition(struct ufs_hba *hba, 9364 enum uic_link_state req_link_state, 9365 bool check_for_bkops) 9366 { 9367 int ret = 0; 9368 9369 if (req_link_state == hba->uic_link_state) 9370 return 0; 9371 9372 if (req_link_state == UIC_LINK_HIBERN8_STATE) { 9373 ret = ufshcd_uic_hibern8_enter(hba); 9374 if (!ret) { 9375 ufshcd_set_link_hibern8(hba); 9376 } else { 9377 dev_err(hba->dev, "%s: hibern8 enter failed %d\n", 9378 __func__, ret); 9379 goto out; 9380 } 9381 } 9382 /* 9383 * If autobkops is enabled, link can't be turned off because 9384 * turning off the link would also turn off the device, except in the 9385 * case of DeepSleep where the device is expected to remain powered. 9386 */ 9387 else if ((req_link_state == UIC_LINK_OFF_STATE) && 9388 (!check_for_bkops || !hba->auto_bkops_enabled)) { 9389 /* 9390 * Let's make sure that link is in low power mode, we are doing 9391 * this currently by putting the link in Hibern8. Otherway to 9392 * put the link in low power mode is to send the DME end point 9393 * to device and then send the DME reset command to local 9394 * unipro. But putting the link in hibern8 is much faster. 9395 * 9396 * Note also that putting the link in Hibern8 is a requirement 9397 * for entering DeepSleep. 9398 */ 9399 ret = ufshcd_uic_hibern8_enter(hba); 9400 if (ret) { 9401 dev_err(hba->dev, "%s: hibern8 enter failed %d\n", 9402 __func__, ret); 9403 goto out; 9404 } 9405 /* 9406 * Change controller state to "reset state" which 9407 * should also put the link in off/reset state 9408 */ 9409 ufshcd_hba_stop(hba); 9410 /* 9411 * TODO: Check if we need any delay to make sure that 9412 * controller is reset 9413 */ 9414 ufshcd_set_link_off(hba); 9415 } 9416 9417 out: 9418 return ret; 9419 } 9420 9421 static void ufshcd_vreg_set_lpm(struct ufs_hba *hba) 9422 { 9423 bool vcc_off = false; 9424 9425 /* 9426 * It seems some UFS devices may keep drawing more than sleep current 9427 * (atleast for 500us) from UFS rails (especially from VCCQ rail). 9428 * To avoid this situation, add 2ms delay before putting these UFS 9429 * rails in LPM mode. 9430 */ 9431 if (!ufshcd_is_link_active(hba) && 9432 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM) 9433 usleep_range(2000, 2100); 9434 9435 /* 9436 * If UFS device is either in UFS_Sleep turn off VCC rail to save some 9437 * power. 9438 * 9439 * If UFS device and link is in OFF state, all power supplies (VCC, 9440 * VCCQ, VCCQ2) can be turned off if power on write protect is not 9441 * required. If UFS link is inactive (Hibern8 or OFF state) and device 9442 * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode. 9443 * 9444 * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway 9445 * in low power state which would save some power. 9446 * 9447 * If Write Booster is enabled and the device needs to flush the WB 9448 * buffer OR if bkops status is urgent for WB, keep Vcc on. 9449 */ 9450 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) && 9451 !hba->dev_info.is_lu_power_on_wp) { 9452 ufshcd_setup_vreg(hba, false); 9453 vcc_off = true; 9454 } else if (!ufshcd_is_ufs_dev_active(hba)) { 9455 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false); 9456 vcc_off = true; 9457 if (ufshcd_is_link_hibern8(hba) || ufshcd_is_link_off(hba)) { 9458 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq); 9459 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2); 9460 } 9461 } 9462 9463 /* 9464 * Some UFS devices require delay after VCC power rail is turned-off. 9465 */ 9466 if (vcc_off && hba->vreg_info.vcc && 9467 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_AFTER_LPM) 9468 usleep_range(5000, 5100); 9469 } 9470 9471 #ifdef CONFIG_PM 9472 static int ufshcd_vreg_set_hpm(struct ufs_hba *hba) 9473 { 9474 int ret = 0; 9475 9476 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) && 9477 !hba->dev_info.is_lu_power_on_wp) { 9478 ret = ufshcd_setup_vreg(hba, true); 9479 } else if (!ufshcd_is_ufs_dev_active(hba)) { 9480 if (!ufshcd_is_link_active(hba)) { 9481 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq); 9482 if (ret) 9483 goto vcc_disable; 9484 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2); 9485 if (ret) 9486 goto vccq_lpm; 9487 } 9488 ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true); 9489 } 9490 goto out; 9491 9492 vccq_lpm: 9493 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq); 9494 vcc_disable: 9495 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false); 9496 out: 9497 return ret; 9498 } 9499 #endif /* CONFIG_PM */ 9500 9501 static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba) 9502 { 9503 if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba)) 9504 ufshcd_setup_hba_vreg(hba, false); 9505 } 9506 9507 static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba) 9508 { 9509 if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba)) 9510 ufshcd_setup_hba_vreg(hba, true); 9511 } 9512 9513 static int __ufshcd_wl_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op) 9514 { 9515 int ret = 0; 9516 bool check_for_bkops; 9517 enum ufs_pm_level pm_lvl; 9518 enum ufs_dev_pwr_mode req_dev_pwr_mode; 9519 enum uic_link_state req_link_state; 9520 9521 hba->pm_op_in_progress = true; 9522 if (pm_op != UFS_SHUTDOWN_PM) { 9523 pm_lvl = pm_op == UFS_RUNTIME_PM ? 9524 hba->rpm_lvl : hba->spm_lvl; 9525 req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl); 9526 req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl); 9527 } else { 9528 req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE; 9529 req_link_state = UIC_LINK_OFF_STATE; 9530 } 9531 9532 /* 9533 * If we can't transition into any of the low power modes 9534 * just gate the clocks. 9535 */ 9536 ufshcd_hold(hba); 9537 hba->clk_gating.is_suspended = true; 9538 9539 if (ufshcd_is_clkscaling_supported(hba)) 9540 ufshcd_clk_scaling_suspend(hba, true); 9541 9542 if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE && 9543 req_link_state == UIC_LINK_ACTIVE_STATE) { 9544 goto vops_suspend; 9545 } 9546 9547 if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) && 9548 (req_link_state == hba->uic_link_state)) 9549 goto enable_scaling; 9550 9551 /* UFS device & link must be active before we enter in this function */ 9552 if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) { 9553 ret = -EINVAL; 9554 goto enable_scaling; 9555 } 9556 9557 if (pm_op == UFS_RUNTIME_PM) { 9558 if (ufshcd_can_autobkops_during_suspend(hba)) { 9559 /* 9560 * The device is idle with no requests in the queue, 9561 * allow background operations if bkops status shows 9562 * that performance might be impacted. 9563 */ 9564 ret = ufshcd_urgent_bkops(hba); 9565 if (ret) { 9566 /* 9567 * If return err in suspend flow, IO will hang. 9568 * Trigger error handler and break suspend for 9569 * error recovery. 9570 */ 9571 ufshcd_force_error_recovery(hba); 9572 ret = -EBUSY; 9573 goto enable_scaling; 9574 } 9575 } else { 9576 /* make sure that auto bkops is disabled */ 9577 ufshcd_disable_auto_bkops(hba); 9578 } 9579 /* 9580 * If device needs to do BKOP or WB buffer flush during 9581 * Hibern8, keep device power mode as "active power mode" 9582 * and VCC supply. 9583 */ 9584 hba->dev_info.b_rpm_dev_flush_capable = 9585 hba->auto_bkops_enabled || 9586 (((req_link_state == UIC_LINK_HIBERN8_STATE) || 9587 ((req_link_state == UIC_LINK_ACTIVE_STATE) && 9588 ufshcd_is_auto_hibern8_enabled(hba))) && 9589 ufshcd_wb_need_flush(hba)); 9590 } 9591 9592 flush_work(&hba->eeh_work); 9593 9594 ret = ufshcd_vops_suspend(hba, pm_op, PRE_CHANGE); 9595 if (ret) 9596 goto enable_scaling; 9597 9598 if (req_dev_pwr_mode != hba->curr_dev_pwr_mode) { 9599 if (pm_op != UFS_RUNTIME_PM) 9600 /* ensure that bkops is disabled */ 9601 ufshcd_disable_auto_bkops(hba); 9602 9603 if (!hba->dev_info.b_rpm_dev_flush_capable) { 9604 ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode); 9605 if (ret && pm_op != UFS_SHUTDOWN_PM) { 9606 /* 9607 * If return err in suspend flow, IO will hang. 9608 * Trigger error handler and break suspend for 9609 * error recovery. 9610 */ 9611 ufshcd_force_error_recovery(hba); 9612 ret = -EBUSY; 9613 } 9614 if (ret) 9615 goto enable_scaling; 9616 } 9617 } 9618 9619 /* 9620 * In the case of DeepSleep, the device is expected to remain powered 9621 * with the link off, so do not check for bkops. 9622 */ 9623 check_for_bkops = !ufshcd_is_ufs_dev_deepsleep(hba); 9624 ret = ufshcd_link_state_transition(hba, req_link_state, check_for_bkops); 9625 if (ret && pm_op != UFS_SHUTDOWN_PM) { 9626 /* 9627 * If return err in suspend flow, IO will hang. 9628 * Trigger error handler and break suspend for 9629 * error recovery. 9630 */ 9631 ufshcd_force_error_recovery(hba); 9632 ret = -EBUSY; 9633 } 9634 if (ret) 9635 goto set_dev_active; 9636 9637 vops_suspend: 9638 /* 9639 * Call vendor specific suspend callback. As these callbacks may access 9640 * vendor specific host controller register space call them before the 9641 * host clocks are ON. 9642 */ 9643 ret = ufshcd_vops_suspend(hba, pm_op, POST_CHANGE); 9644 if (ret) 9645 goto set_link_active; 9646 goto out; 9647 9648 set_link_active: 9649 /* 9650 * Device hardware reset is required to exit DeepSleep. Also, for 9651 * DeepSleep, the link is off so host reset and restore will be done 9652 * further below. 9653 */ 9654 if (ufshcd_is_ufs_dev_deepsleep(hba)) { 9655 ufshcd_device_reset(hba); 9656 WARN_ON(!ufshcd_is_link_off(hba)); 9657 } 9658 if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba)) 9659 ufshcd_set_link_active(hba); 9660 else if (ufshcd_is_link_off(hba)) 9661 ufshcd_host_reset_and_restore(hba); 9662 set_dev_active: 9663 /* Can also get here needing to exit DeepSleep */ 9664 if (ufshcd_is_ufs_dev_deepsleep(hba)) { 9665 ufshcd_device_reset(hba); 9666 ufshcd_host_reset_and_restore(hba); 9667 } 9668 if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE)) 9669 ufshcd_disable_auto_bkops(hba); 9670 enable_scaling: 9671 if (ufshcd_is_clkscaling_supported(hba)) 9672 ufshcd_clk_scaling_suspend(hba, false); 9673 9674 hba->dev_info.b_rpm_dev_flush_capable = false; 9675 out: 9676 if (hba->dev_info.b_rpm_dev_flush_capable) { 9677 schedule_delayed_work(&hba->rpm_dev_flush_recheck_work, 9678 msecs_to_jiffies(RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS)); 9679 } 9680 9681 if (ret) { 9682 ufshcd_update_evt_hist(hba, UFS_EVT_WL_SUSP_ERR, (u32)ret); 9683 hba->clk_gating.is_suspended = false; 9684 ufshcd_release(hba); 9685 } 9686 hba->pm_op_in_progress = false; 9687 return ret; 9688 } 9689 9690 #ifdef CONFIG_PM 9691 static int __ufshcd_wl_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) 9692 { 9693 int ret; 9694 enum uic_link_state old_link_state = hba->uic_link_state; 9695 9696 hba->pm_op_in_progress = true; 9697 9698 /* 9699 * Call vendor specific resume callback. As these callbacks may access 9700 * vendor specific host controller register space call them when the 9701 * host clocks are ON. 9702 */ 9703 ret = ufshcd_vops_resume(hba, pm_op); 9704 if (ret) 9705 goto out; 9706 9707 /* For DeepSleep, the only supported option is to have the link off */ 9708 WARN_ON(ufshcd_is_ufs_dev_deepsleep(hba) && !ufshcd_is_link_off(hba)); 9709 9710 if (ufshcd_is_link_hibern8(hba)) { 9711 ret = ufshcd_uic_hibern8_exit(hba); 9712 if (!ret) { 9713 ufshcd_set_link_active(hba); 9714 } else { 9715 dev_err(hba->dev, "%s: hibern8 exit failed %d\n", 9716 __func__, ret); 9717 goto vendor_suspend; 9718 } 9719 } else if (ufshcd_is_link_off(hba)) { 9720 /* 9721 * A full initialization of the host and the device is 9722 * required since the link was put to off during suspend. 9723 * Note, in the case of DeepSleep, the device will exit 9724 * DeepSleep due to device reset. 9725 */ 9726 ret = ufshcd_reset_and_restore(hba); 9727 /* 9728 * ufshcd_reset_and_restore() should have already 9729 * set the link state as active 9730 */ 9731 if (ret || !ufshcd_is_link_active(hba)) 9732 goto vendor_suspend; 9733 } 9734 9735 if (!ufshcd_is_ufs_dev_active(hba)) { 9736 ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE); 9737 if (ret) 9738 goto set_old_link_state; 9739 ufshcd_set_timestamp_attr(hba); 9740 } 9741 9742 if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) 9743 ufshcd_enable_auto_bkops(hba); 9744 else 9745 /* 9746 * If BKOPs operations are urgently needed at this moment then 9747 * keep auto-bkops enabled or else disable it. 9748 */ 9749 ufshcd_urgent_bkops(hba); 9750 9751 if (hba->ee_usr_mask) 9752 ufshcd_write_ee_control(hba); 9753 9754 if (ufshcd_is_clkscaling_supported(hba)) 9755 ufshcd_clk_scaling_suspend(hba, false); 9756 9757 if (hba->dev_info.b_rpm_dev_flush_capable) { 9758 hba->dev_info.b_rpm_dev_flush_capable = false; 9759 cancel_delayed_work(&hba->rpm_dev_flush_recheck_work); 9760 } 9761 9762 /* Enable Auto-Hibernate if configured */ 9763 ufshcd_auto_hibern8_enable(hba); 9764 9765 goto out; 9766 9767 set_old_link_state: 9768 ufshcd_link_state_transition(hba, old_link_state, 0); 9769 vendor_suspend: 9770 ufshcd_vops_suspend(hba, pm_op, PRE_CHANGE); 9771 ufshcd_vops_suspend(hba, pm_op, POST_CHANGE); 9772 out: 9773 if (ret) 9774 ufshcd_update_evt_hist(hba, UFS_EVT_WL_RES_ERR, (u32)ret); 9775 hba->clk_gating.is_suspended = false; 9776 ufshcd_release(hba); 9777 hba->pm_op_in_progress = false; 9778 return ret; 9779 } 9780 9781 static int ufshcd_wl_runtime_suspend(struct device *dev) 9782 { 9783 struct scsi_device *sdev = to_scsi_device(dev); 9784 struct ufs_hba *hba; 9785 int ret; 9786 ktime_t start = ktime_get(); 9787 9788 hba = shost_priv(sdev->host); 9789 9790 ret = __ufshcd_wl_suspend(hba, UFS_RUNTIME_PM); 9791 if (ret) 9792 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret); 9793 9794 trace_ufshcd_wl_runtime_suspend(dev_name(dev), ret, 9795 ktime_to_us(ktime_sub(ktime_get(), start)), 9796 hba->curr_dev_pwr_mode, hba->uic_link_state); 9797 9798 return ret; 9799 } 9800 9801 static int ufshcd_wl_runtime_resume(struct device *dev) 9802 { 9803 struct scsi_device *sdev = to_scsi_device(dev); 9804 struct ufs_hba *hba; 9805 int ret = 0; 9806 ktime_t start = ktime_get(); 9807 9808 hba = shost_priv(sdev->host); 9809 9810 ret = __ufshcd_wl_resume(hba, UFS_RUNTIME_PM); 9811 if (ret) 9812 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret); 9813 9814 trace_ufshcd_wl_runtime_resume(dev_name(dev), ret, 9815 ktime_to_us(ktime_sub(ktime_get(), start)), 9816 hba->curr_dev_pwr_mode, hba->uic_link_state); 9817 9818 return ret; 9819 } 9820 #endif 9821 9822 #ifdef CONFIG_PM_SLEEP 9823 static int ufshcd_wl_suspend(struct device *dev) 9824 { 9825 struct scsi_device *sdev = to_scsi_device(dev); 9826 struct ufs_hba *hba; 9827 int ret = 0; 9828 ktime_t start = ktime_get(); 9829 9830 hba = shost_priv(sdev->host); 9831 down(&hba->host_sem); 9832 hba->system_suspending = true; 9833 9834 if (pm_runtime_suspended(dev)) 9835 goto out; 9836 9837 ret = __ufshcd_wl_suspend(hba, UFS_SYSTEM_PM); 9838 if (ret) { 9839 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret); 9840 up(&hba->host_sem); 9841 } 9842 9843 out: 9844 if (!ret) 9845 hba->is_sys_suspended = true; 9846 trace_ufshcd_wl_suspend(dev_name(dev), ret, 9847 ktime_to_us(ktime_sub(ktime_get(), start)), 9848 hba->curr_dev_pwr_mode, hba->uic_link_state); 9849 9850 return ret; 9851 } 9852 9853 static int ufshcd_wl_resume(struct device *dev) 9854 { 9855 struct scsi_device *sdev = to_scsi_device(dev); 9856 struct ufs_hba *hba; 9857 int ret = 0; 9858 ktime_t start = ktime_get(); 9859 9860 hba = shost_priv(sdev->host); 9861 9862 if (pm_runtime_suspended(dev)) 9863 goto out; 9864 9865 ret = __ufshcd_wl_resume(hba, UFS_SYSTEM_PM); 9866 if (ret) 9867 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret); 9868 out: 9869 trace_ufshcd_wl_resume(dev_name(dev), ret, 9870 ktime_to_us(ktime_sub(ktime_get(), start)), 9871 hba->curr_dev_pwr_mode, hba->uic_link_state); 9872 if (!ret) 9873 hba->is_sys_suspended = false; 9874 hba->system_suspending = false; 9875 up(&hba->host_sem); 9876 return ret; 9877 } 9878 #endif 9879 9880 /** 9881 * ufshcd_suspend - helper function for suspend operations 9882 * @hba: per adapter instance 9883 * 9884 * This function will put disable irqs, turn off clocks 9885 * and set vreg and hba-vreg in lpm mode. 9886 * 9887 * Return: 0 upon success; < 0 upon failure. 9888 */ 9889 static int ufshcd_suspend(struct ufs_hba *hba) 9890 { 9891 int ret; 9892 9893 if (!hba->is_powered) 9894 return 0; 9895 /* 9896 * Disable the host irq as host controller as there won't be any 9897 * host controller transaction expected till resume. 9898 */ 9899 ufshcd_disable_irq(hba); 9900 ret = ufshcd_setup_clocks(hba, false); 9901 if (ret) { 9902 ufshcd_enable_irq(hba); 9903 return ret; 9904 } 9905 if (ufshcd_is_clkgating_allowed(hba)) { 9906 hba->clk_gating.state = CLKS_OFF; 9907 trace_ufshcd_clk_gating(dev_name(hba->dev), 9908 hba->clk_gating.state); 9909 } 9910 9911 ufshcd_vreg_set_lpm(hba); 9912 /* Put the host controller in low power mode if possible */ 9913 ufshcd_hba_vreg_set_lpm(hba); 9914 return ret; 9915 } 9916 9917 #ifdef CONFIG_PM 9918 /** 9919 * ufshcd_resume - helper function for resume operations 9920 * @hba: per adapter instance 9921 * 9922 * This function basically turns on the regulators, clocks and 9923 * irqs of the hba. 9924 * 9925 * Return: 0 for success and non-zero for failure. 9926 */ 9927 static int ufshcd_resume(struct ufs_hba *hba) 9928 { 9929 int ret; 9930 9931 if (!hba->is_powered) 9932 return 0; 9933 9934 ufshcd_hba_vreg_set_hpm(hba); 9935 ret = ufshcd_vreg_set_hpm(hba); 9936 if (ret) 9937 goto out; 9938 9939 /* Make sure clocks are enabled before accessing controller */ 9940 ret = ufshcd_setup_clocks(hba, true); 9941 if (ret) 9942 goto disable_vreg; 9943 9944 /* enable the host irq as host controller would be active soon */ 9945 ufshcd_enable_irq(hba); 9946 9947 goto out; 9948 9949 disable_vreg: 9950 ufshcd_vreg_set_lpm(hba); 9951 out: 9952 if (ret) 9953 ufshcd_update_evt_hist(hba, UFS_EVT_RESUME_ERR, (u32)ret); 9954 return ret; 9955 } 9956 #endif /* CONFIG_PM */ 9957 9958 #ifdef CONFIG_PM_SLEEP 9959 /** 9960 * ufshcd_system_suspend - system suspend callback 9961 * @dev: Device associated with the UFS controller. 9962 * 9963 * Executed before putting the system into a sleep state in which the contents 9964 * of main memory are preserved. 9965 * 9966 * Return: 0 for success and non-zero for failure. 9967 */ 9968 int ufshcd_system_suspend(struct device *dev) 9969 { 9970 struct ufs_hba *hba = dev_get_drvdata(dev); 9971 int ret = 0; 9972 ktime_t start = ktime_get(); 9973 9974 if (pm_runtime_suspended(hba->dev)) 9975 goto out; 9976 9977 ret = ufshcd_suspend(hba); 9978 out: 9979 trace_ufshcd_system_suspend(dev_name(hba->dev), ret, 9980 ktime_to_us(ktime_sub(ktime_get(), start)), 9981 hba->curr_dev_pwr_mode, hba->uic_link_state); 9982 return ret; 9983 } 9984 EXPORT_SYMBOL(ufshcd_system_suspend); 9985 9986 /** 9987 * ufshcd_system_resume - system resume callback 9988 * @dev: Device associated with the UFS controller. 9989 * 9990 * Executed after waking the system up from a sleep state in which the contents 9991 * of main memory were preserved. 9992 * 9993 * Return: 0 for success and non-zero for failure. 9994 */ 9995 int ufshcd_system_resume(struct device *dev) 9996 { 9997 struct ufs_hba *hba = dev_get_drvdata(dev); 9998 ktime_t start = ktime_get(); 9999 int ret = 0; 10000 10001 if (pm_runtime_suspended(hba->dev)) 10002 goto out; 10003 10004 ret = ufshcd_resume(hba); 10005 10006 out: 10007 trace_ufshcd_system_resume(dev_name(hba->dev), ret, 10008 ktime_to_us(ktime_sub(ktime_get(), start)), 10009 hba->curr_dev_pwr_mode, hba->uic_link_state); 10010 10011 return ret; 10012 } 10013 EXPORT_SYMBOL(ufshcd_system_resume); 10014 #endif /* CONFIG_PM_SLEEP */ 10015 10016 #ifdef CONFIG_PM 10017 /** 10018 * ufshcd_runtime_suspend - runtime suspend callback 10019 * @dev: Device associated with the UFS controller. 10020 * 10021 * Check the description of ufshcd_suspend() function for more details. 10022 * 10023 * Return: 0 for success and non-zero for failure. 10024 */ 10025 int ufshcd_runtime_suspend(struct device *dev) 10026 { 10027 struct ufs_hba *hba = dev_get_drvdata(dev); 10028 int ret; 10029 ktime_t start = ktime_get(); 10030 10031 ret = ufshcd_suspend(hba); 10032 10033 trace_ufshcd_runtime_suspend(dev_name(hba->dev), ret, 10034 ktime_to_us(ktime_sub(ktime_get(), start)), 10035 hba->curr_dev_pwr_mode, hba->uic_link_state); 10036 return ret; 10037 } 10038 EXPORT_SYMBOL(ufshcd_runtime_suspend); 10039 10040 /** 10041 * ufshcd_runtime_resume - runtime resume routine 10042 * @dev: Device associated with the UFS controller. 10043 * 10044 * This function basically brings controller 10045 * to active state. Following operations are done in this function: 10046 * 10047 * 1. Turn on all the controller related clocks 10048 * 2. Turn ON VCC rail 10049 * 10050 * Return: 0 upon success; < 0 upon failure. 10051 */ 10052 int ufshcd_runtime_resume(struct device *dev) 10053 { 10054 struct ufs_hba *hba = dev_get_drvdata(dev); 10055 int ret; 10056 ktime_t start = ktime_get(); 10057 10058 ret = ufshcd_resume(hba); 10059 10060 trace_ufshcd_runtime_resume(dev_name(hba->dev), ret, 10061 ktime_to_us(ktime_sub(ktime_get(), start)), 10062 hba->curr_dev_pwr_mode, hba->uic_link_state); 10063 return ret; 10064 } 10065 EXPORT_SYMBOL(ufshcd_runtime_resume); 10066 #endif /* CONFIG_PM */ 10067 10068 static void ufshcd_wl_shutdown(struct device *dev) 10069 { 10070 struct scsi_device *sdev = to_scsi_device(dev); 10071 struct ufs_hba *hba = shost_priv(sdev->host); 10072 10073 down(&hba->host_sem); 10074 hba->shutting_down = true; 10075 up(&hba->host_sem); 10076 10077 /* Turn on everything while shutting down */ 10078 ufshcd_rpm_get_sync(hba); 10079 scsi_device_quiesce(sdev); 10080 shost_for_each_device(sdev, hba->host) { 10081 if (sdev == hba->ufs_device_wlun) 10082 continue; 10083 scsi_device_quiesce(sdev); 10084 } 10085 __ufshcd_wl_suspend(hba, UFS_SHUTDOWN_PM); 10086 10087 /* 10088 * Next, turn off the UFS controller and the UFS regulators. Disable 10089 * clocks. 10090 */ 10091 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba)) 10092 ufshcd_suspend(hba); 10093 10094 hba->is_powered = false; 10095 } 10096 10097 /** 10098 * ufshcd_remove - de-allocate SCSI host and host memory space 10099 * data structure memory 10100 * @hba: per adapter instance 10101 */ 10102 void ufshcd_remove(struct ufs_hba *hba) 10103 { 10104 if (hba->ufs_device_wlun) 10105 ufshcd_rpm_get_sync(hba); 10106 ufs_hwmon_remove(hba); 10107 ufs_bsg_remove(hba); 10108 ufs_sysfs_remove_nodes(hba->dev); 10109 blk_mq_destroy_queue(hba->tmf_queue); 10110 blk_put_queue(hba->tmf_queue); 10111 blk_mq_free_tag_set(&hba->tmf_tag_set); 10112 scsi_remove_host(hba->host); 10113 /* disable interrupts */ 10114 ufshcd_disable_intr(hba, hba->intr_mask); 10115 ufshcd_hba_stop(hba); 10116 ufshcd_hba_exit(hba); 10117 } 10118 EXPORT_SYMBOL_GPL(ufshcd_remove); 10119 10120 #ifdef CONFIG_PM_SLEEP 10121 int ufshcd_system_freeze(struct device *dev) 10122 { 10123 10124 return ufshcd_system_suspend(dev); 10125 10126 } 10127 EXPORT_SYMBOL_GPL(ufshcd_system_freeze); 10128 10129 int ufshcd_system_restore(struct device *dev) 10130 { 10131 10132 struct ufs_hba *hba = dev_get_drvdata(dev); 10133 int ret; 10134 10135 ret = ufshcd_system_resume(dev); 10136 if (ret) 10137 return ret; 10138 10139 /* Configure UTRL and UTMRL base address registers */ 10140 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr), 10141 REG_UTP_TRANSFER_REQ_LIST_BASE_L); 10142 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr), 10143 REG_UTP_TRANSFER_REQ_LIST_BASE_H); 10144 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr), 10145 REG_UTP_TASK_REQ_LIST_BASE_L); 10146 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr), 10147 REG_UTP_TASK_REQ_LIST_BASE_H); 10148 /* 10149 * Make sure that UTRL and UTMRL base address registers 10150 * are updated with the latest queue addresses. Only after 10151 * updating these addresses, we can queue the new commands. 10152 */ 10153 mb(); 10154 10155 /* Resuming from hibernate, assume that link was OFF */ 10156 ufshcd_set_link_off(hba); 10157 10158 return 0; 10159 10160 } 10161 EXPORT_SYMBOL_GPL(ufshcd_system_restore); 10162 10163 int ufshcd_system_thaw(struct device *dev) 10164 { 10165 return ufshcd_system_resume(dev); 10166 } 10167 EXPORT_SYMBOL_GPL(ufshcd_system_thaw); 10168 #endif /* CONFIG_PM_SLEEP */ 10169 10170 /** 10171 * ufshcd_dealloc_host - deallocate Host Bus Adapter (HBA) 10172 * @hba: pointer to Host Bus Adapter (HBA) 10173 */ 10174 void ufshcd_dealloc_host(struct ufs_hba *hba) 10175 { 10176 scsi_host_put(hba->host); 10177 } 10178 EXPORT_SYMBOL_GPL(ufshcd_dealloc_host); 10179 10180 /** 10181 * ufshcd_set_dma_mask - Set dma mask based on the controller 10182 * addressing capability 10183 * @hba: per adapter instance 10184 * 10185 * Return: 0 for success, non-zero for failure. 10186 */ 10187 static int ufshcd_set_dma_mask(struct ufs_hba *hba) 10188 { 10189 if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) { 10190 if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64))) 10191 return 0; 10192 } 10193 return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32)); 10194 } 10195 10196 /** 10197 * ufshcd_alloc_host - allocate Host Bus Adapter (HBA) 10198 * @dev: pointer to device handle 10199 * @hba_handle: driver private handle 10200 * 10201 * Return: 0 on success, non-zero value on failure. 10202 */ 10203 int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle) 10204 { 10205 struct Scsi_Host *host; 10206 struct ufs_hba *hba; 10207 int err = 0; 10208 10209 if (!dev) { 10210 dev_err(dev, 10211 "Invalid memory reference for dev is NULL\n"); 10212 err = -ENODEV; 10213 goto out_error; 10214 } 10215 10216 host = scsi_host_alloc(&ufshcd_driver_template, 10217 sizeof(struct ufs_hba)); 10218 if (!host) { 10219 dev_err(dev, "scsi_host_alloc failed\n"); 10220 err = -ENOMEM; 10221 goto out_error; 10222 } 10223 host->nr_maps = HCTX_TYPE_POLL + 1; 10224 hba = shost_priv(host); 10225 hba->host = host; 10226 hba->dev = dev; 10227 hba->dev_ref_clk_freq = REF_CLK_FREQ_INVAL; 10228 hba->nop_out_timeout = NOP_OUT_TIMEOUT; 10229 ufshcd_set_sg_entry_size(hba, sizeof(struct ufshcd_sg_entry)); 10230 INIT_LIST_HEAD(&hba->clk_list_head); 10231 spin_lock_init(&hba->outstanding_lock); 10232 10233 *hba_handle = hba; 10234 10235 out_error: 10236 return err; 10237 } 10238 EXPORT_SYMBOL(ufshcd_alloc_host); 10239 10240 /* This function exists because blk_mq_alloc_tag_set() requires this. */ 10241 static blk_status_t ufshcd_queue_tmf(struct blk_mq_hw_ctx *hctx, 10242 const struct blk_mq_queue_data *qd) 10243 { 10244 WARN_ON_ONCE(true); 10245 return BLK_STS_NOTSUPP; 10246 } 10247 10248 static const struct blk_mq_ops ufshcd_tmf_ops = { 10249 .queue_rq = ufshcd_queue_tmf, 10250 }; 10251 10252 /** 10253 * ufshcd_init - Driver initialization routine 10254 * @hba: per-adapter instance 10255 * @mmio_base: base register address 10256 * @irq: Interrupt line of device 10257 * 10258 * Return: 0 on success, non-zero value on failure. 10259 */ 10260 int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq) 10261 { 10262 int err; 10263 struct Scsi_Host *host = hba->host; 10264 struct device *dev = hba->dev; 10265 char eh_wq_name[sizeof("ufs_eh_wq_00")]; 10266 10267 /* 10268 * dev_set_drvdata() must be called before any callbacks are registered 10269 * that use dev_get_drvdata() (frequency scaling, clock scaling, hwmon, 10270 * sysfs). 10271 */ 10272 dev_set_drvdata(dev, hba); 10273 10274 if (!mmio_base) { 10275 dev_err(hba->dev, 10276 "Invalid memory reference for mmio_base is NULL\n"); 10277 err = -ENODEV; 10278 goto out_error; 10279 } 10280 10281 hba->mmio_base = mmio_base; 10282 hba->irq = irq; 10283 hba->vps = &ufs_hba_vps; 10284 10285 err = ufshcd_hba_init(hba); 10286 if (err) 10287 goto out_error; 10288 10289 /* Read capabilities registers */ 10290 err = ufshcd_hba_capabilities(hba); 10291 if (err) 10292 goto out_disable; 10293 10294 /* Get UFS version supported by the controller */ 10295 hba->ufs_version = ufshcd_get_ufs_version(hba); 10296 10297 /* Get Interrupt bit mask per version */ 10298 hba->intr_mask = ufshcd_get_intr_mask(hba); 10299 10300 err = ufshcd_set_dma_mask(hba); 10301 if (err) { 10302 dev_err(hba->dev, "set dma mask failed\n"); 10303 goto out_disable; 10304 } 10305 10306 /* Allocate memory for host memory space */ 10307 err = ufshcd_memory_alloc(hba); 10308 if (err) { 10309 dev_err(hba->dev, "Memory allocation failed\n"); 10310 goto out_disable; 10311 } 10312 10313 /* Configure LRB */ 10314 ufshcd_host_memory_configure(hba); 10315 10316 host->can_queue = hba->nutrs - UFSHCD_NUM_RESERVED; 10317 host->cmd_per_lun = hba->nutrs - UFSHCD_NUM_RESERVED; 10318 host->max_id = UFSHCD_MAX_ID; 10319 host->max_lun = UFS_MAX_LUNS; 10320 host->max_channel = UFSHCD_MAX_CHANNEL; 10321 host->unique_id = host->host_no; 10322 host->max_cmd_len = UFS_CDB_SIZE; 10323 host->queuecommand_may_block = !!(hba->caps & UFSHCD_CAP_CLK_GATING); 10324 10325 hba->max_pwr_info.is_valid = false; 10326 10327 /* Initialize work queues */ 10328 snprintf(eh_wq_name, sizeof(eh_wq_name), "ufs_eh_wq_%d", 10329 hba->host->host_no); 10330 hba->eh_wq = create_singlethread_workqueue(eh_wq_name); 10331 if (!hba->eh_wq) { 10332 dev_err(hba->dev, "%s: failed to create eh workqueue\n", 10333 __func__); 10334 err = -ENOMEM; 10335 goto out_disable; 10336 } 10337 INIT_WORK(&hba->eh_work, ufshcd_err_handler); 10338 INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler); 10339 10340 sema_init(&hba->host_sem, 1); 10341 10342 /* Initialize UIC command mutex */ 10343 mutex_init(&hba->uic_cmd_mutex); 10344 10345 /* Initialize mutex for device management commands */ 10346 mutex_init(&hba->dev_cmd.lock); 10347 10348 /* Initialize mutex for exception event control */ 10349 mutex_init(&hba->ee_ctrl_mutex); 10350 10351 mutex_init(&hba->wb_mutex); 10352 init_rwsem(&hba->clk_scaling_lock); 10353 10354 ufshcd_init_clk_gating(hba); 10355 10356 ufshcd_init_clk_scaling(hba); 10357 10358 /* 10359 * In order to avoid any spurious interrupt immediately after 10360 * registering UFS controller interrupt handler, clear any pending UFS 10361 * interrupt status and disable all the UFS interrupts. 10362 */ 10363 ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS), 10364 REG_INTERRUPT_STATUS); 10365 ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE); 10366 /* 10367 * Make sure that UFS interrupts are disabled and any pending interrupt 10368 * status is cleared before registering UFS interrupt handler. 10369 */ 10370 mb(); 10371 10372 /* IRQ registration */ 10373 err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba); 10374 if (err) { 10375 dev_err(hba->dev, "request irq failed\n"); 10376 goto out_disable; 10377 } else { 10378 hba->is_irq_enabled = true; 10379 } 10380 10381 if (!is_mcq_supported(hba)) { 10382 err = scsi_add_host(host, hba->dev); 10383 if (err) { 10384 dev_err(hba->dev, "scsi_add_host failed\n"); 10385 goto out_disable; 10386 } 10387 } 10388 10389 hba->tmf_tag_set = (struct blk_mq_tag_set) { 10390 .nr_hw_queues = 1, 10391 .queue_depth = hba->nutmrs, 10392 .ops = &ufshcd_tmf_ops, 10393 .flags = BLK_MQ_F_NO_SCHED, 10394 }; 10395 err = blk_mq_alloc_tag_set(&hba->tmf_tag_set); 10396 if (err < 0) 10397 goto out_remove_scsi_host; 10398 hba->tmf_queue = blk_mq_init_queue(&hba->tmf_tag_set); 10399 if (IS_ERR(hba->tmf_queue)) { 10400 err = PTR_ERR(hba->tmf_queue); 10401 goto free_tmf_tag_set; 10402 } 10403 hba->tmf_rqs = devm_kcalloc(hba->dev, hba->nutmrs, 10404 sizeof(*hba->tmf_rqs), GFP_KERNEL); 10405 if (!hba->tmf_rqs) { 10406 err = -ENOMEM; 10407 goto free_tmf_queue; 10408 } 10409 10410 /* Reset the attached device */ 10411 ufshcd_device_reset(hba); 10412 10413 ufshcd_init_crypto(hba); 10414 10415 /* Host controller enable */ 10416 err = ufshcd_hba_enable(hba); 10417 if (err) { 10418 dev_err(hba->dev, "Host controller enable failed\n"); 10419 ufshcd_print_evt_hist(hba); 10420 ufshcd_print_host_state(hba); 10421 goto free_tmf_queue; 10422 } 10423 10424 /* 10425 * Set the default power management level for runtime and system PM. 10426 * Default power saving mode is to keep UFS link in Hibern8 state 10427 * and UFS device in sleep state. 10428 */ 10429 hba->rpm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state( 10430 UFS_SLEEP_PWR_MODE, 10431 UIC_LINK_HIBERN8_STATE); 10432 hba->spm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state( 10433 UFS_SLEEP_PWR_MODE, 10434 UIC_LINK_HIBERN8_STATE); 10435 10436 INIT_DELAYED_WORK(&hba->rpm_dev_flush_recheck_work, 10437 ufshcd_rpm_dev_flush_recheck_work); 10438 10439 /* Set the default auto-hiberate idle timer value to 150 ms */ 10440 if (ufshcd_is_auto_hibern8_supported(hba) && !hba->ahit) { 10441 hba->ahit = FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, 150) | 10442 FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3); 10443 } 10444 10445 /* Hold auto suspend until async scan completes */ 10446 pm_runtime_get_sync(dev); 10447 atomic_set(&hba->scsi_block_reqs_cnt, 0); 10448 /* 10449 * We are assuming that device wasn't put in sleep/power-down 10450 * state exclusively during the boot stage before kernel. 10451 * This assumption helps avoid doing link startup twice during 10452 * ufshcd_probe_hba(). 10453 */ 10454 ufshcd_set_ufs_dev_active(hba); 10455 10456 async_schedule(ufshcd_async_scan, hba); 10457 ufs_sysfs_add_nodes(hba->dev); 10458 10459 device_enable_async_suspend(dev); 10460 return 0; 10461 10462 free_tmf_queue: 10463 blk_mq_destroy_queue(hba->tmf_queue); 10464 blk_put_queue(hba->tmf_queue); 10465 free_tmf_tag_set: 10466 blk_mq_free_tag_set(&hba->tmf_tag_set); 10467 out_remove_scsi_host: 10468 scsi_remove_host(hba->host); 10469 out_disable: 10470 hba->is_irq_enabled = false; 10471 ufshcd_hba_exit(hba); 10472 out_error: 10473 return err; 10474 } 10475 EXPORT_SYMBOL_GPL(ufshcd_init); 10476 10477 void ufshcd_resume_complete(struct device *dev) 10478 { 10479 struct ufs_hba *hba = dev_get_drvdata(dev); 10480 10481 if (hba->complete_put) { 10482 ufshcd_rpm_put(hba); 10483 hba->complete_put = false; 10484 } 10485 } 10486 EXPORT_SYMBOL_GPL(ufshcd_resume_complete); 10487 10488 static bool ufshcd_rpm_ok_for_spm(struct ufs_hba *hba) 10489 { 10490 struct device *dev = &hba->ufs_device_wlun->sdev_gendev; 10491 enum ufs_dev_pwr_mode dev_pwr_mode; 10492 enum uic_link_state link_state; 10493 unsigned long flags; 10494 bool res; 10495 10496 spin_lock_irqsave(&dev->power.lock, flags); 10497 dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl); 10498 link_state = ufs_get_pm_lvl_to_link_pwr_state(hba->spm_lvl); 10499 res = pm_runtime_suspended(dev) && 10500 hba->curr_dev_pwr_mode == dev_pwr_mode && 10501 hba->uic_link_state == link_state && 10502 !hba->dev_info.b_rpm_dev_flush_capable; 10503 spin_unlock_irqrestore(&dev->power.lock, flags); 10504 10505 return res; 10506 } 10507 10508 int __ufshcd_suspend_prepare(struct device *dev, bool rpm_ok_for_spm) 10509 { 10510 struct ufs_hba *hba = dev_get_drvdata(dev); 10511 int ret; 10512 10513 /* 10514 * SCSI assumes that runtime-pm and system-pm for scsi drivers 10515 * are same. And it doesn't wake up the device for system-suspend 10516 * if it's runtime suspended. But ufs doesn't follow that. 10517 * Refer ufshcd_resume_complete() 10518 */ 10519 if (hba->ufs_device_wlun) { 10520 /* Prevent runtime suspend */ 10521 ufshcd_rpm_get_noresume(hba); 10522 /* 10523 * Check if already runtime suspended in same state as system 10524 * suspend would be. 10525 */ 10526 if (!rpm_ok_for_spm || !ufshcd_rpm_ok_for_spm(hba)) { 10527 /* RPM state is not ok for SPM, so runtime resume */ 10528 ret = ufshcd_rpm_resume(hba); 10529 if (ret < 0 && ret != -EACCES) { 10530 ufshcd_rpm_put(hba); 10531 return ret; 10532 } 10533 } 10534 hba->complete_put = true; 10535 } 10536 return 0; 10537 } 10538 EXPORT_SYMBOL_GPL(__ufshcd_suspend_prepare); 10539 10540 int ufshcd_suspend_prepare(struct device *dev) 10541 { 10542 return __ufshcd_suspend_prepare(dev, true); 10543 } 10544 EXPORT_SYMBOL_GPL(ufshcd_suspend_prepare); 10545 10546 #ifdef CONFIG_PM_SLEEP 10547 static int ufshcd_wl_poweroff(struct device *dev) 10548 { 10549 struct scsi_device *sdev = to_scsi_device(dev); 10550 struct ufs_hba *hba = shost_priv(sdev->host); 10551 10552 __ufshcd_wl_suspend(hba, UFS_SHUTDOWN_PM); 10553 return 0; 10554 } 10555 #endif 10556 10557 static int ufshcd_wl_probe(struct device *dev) 10558 { 10559 struct scsi_device *sdev = to_scsi_device(dev); 10560 10561 if (!is_device_wlun(sdev)) 10562 return -ENODEV; 10563 10564 blk_pm_runtime_init(sdev->request_queue, dev); 10565 pm_runtime_set_autosuspend_delay(dev, 0); 10566 pm_runtime_allow(dev); 10567 10568 return 0; 10569 } 10570 10571 static int ufshcd_wl_remove(struct device *dev) 10572 { 10573 pm_runtime_forbid(dev); 10574 return 0; 10575 } 10576 10577 static const struct dev_pm_ops ufshcd_wl_pm_ops = { 10578 #ifdef CONFIG_PM_SLEEP 10579 .suspend = ufshcd_wl_suspend, 10580 .resume = ufshcd_wl_resume, 10581 .freeze = ufshcd_wl_suspend, 10582 .thaw = ufshcd_wl_resume, 10583 .poweroff = ufshcd_wl_poweroff, 10584 .restore = ufshcd_wl_resume, 10585 #endif 10586 SET_RUNTIME_PM_OPS(ufshcd_wl_runtime_suspend, ufshcd_wl_runtime_resume, NULL) 10587 }; 10588 10589 static void ufshcd_check_header_layout(void) 10590 { 10591 /* 10592 * gcc compilers before version 10 cannot do constant-folding for 10593 * sub-byte bitfields. Hence skip the layout checks for gcc 9 and 10594 * before. 10595 */ 10596 if (IS_ENABLED(CONFIG_CC_IS_GCC) && CONFIG_GCC_VERSION < 100000) 10597 return; 10598 10599 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10600 .cci = 3})[0] != 3); 10601 10602 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10603 .ehs_length = 2})[1] != 2); 10604 10605 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10606 .enable_crypto = 1})[2] 10607 != 0x80); 10608 10609 BUILD_BUG_ON((((u8 *)&(struct request_desc_header){ 10610 .command_type = 5, 10611 .data_direction = 3, 10612 .interrupt = 1, 10613 })[3]) != ((5 << 4) | (3 << 1) | 1)); 10614 10615 BUILD_BUG_ON(((__le32 *)&(struct request_desc_header){ 10616 .dunl = cpu_to_le32(0xdeadbeef)})[1] != 10617 cpu_to_le32(0xdeadbeef)); 10618 10619 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10620 .ocs = 4})[8] != 4); 10621 10622 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10623 .cds = 5})[9] != 5); 10624 10625 BUILD_BUG_ON(((__le32 *)&(struct request_desc_header){ 10626 .dunu = cpu_to_le32(0xbadcafe)})[3] != 10627 cpu_to_le32(0xbadcafe)); 10628 10629 BUILD_BUG_ON(((u8 *)&(struct utp_upiu_header){ 10630 .iid = 0xf })[4] != 0xf0); 10631 10632 BUILD_BUG_ON(((u8 *)&(struct utp_upiu_header){ 10633 .command_set_type = 0xf })[4] != 0xf); 10634 } 10635 10636 /* 10637 * ufs_dev_wlun_template - describes ufs device wlun 10638 * ufs-device wlun - used to send pm commands 10639 * All luns are consumers of ufs-device wlun. 10640 * 10641 * Currently, no sd driver is present for wluns. 10642 * Hence the no specific pm operations are performed. 10643 * With ufs design, SSU should be sent to ufs-device wlun. 10644 * Hence register a scsi driver for ufs wluns only. 10645 */ 10646 static struct scsi_driver ufs_dev_wlun_template = { 10647 .gendrv = { 10648 .name = "ufs_device_wlun", 10649 .owner = THIS_MODULE, 10650 .probe = ufshcd_wl_probe, 10651 .remove = ufshcd_wl_remove, 10652 .pm = &ufshcd_wl_pm_ops, 10653 .shutdown = ufshcd_wl_shutdown, 10654 }, 10655 }; 10656 10657 static int __init ufshcd_core_init(void) 10658 { 10659 int ret; 10660 10661 ufshcd_check_header_layout(); 10662 10663 ufs_debugfs_init(); 10664 10665 ret = scsi_register_driver(&ufs_dev_wlun_template.gendrv); 10666 if (ret) 10667 ufs_debugfs_exit(); 10668 return ret; 10669 } 10670 10671 static void __exit ufshcd_core_exit(void) 10672 { 10673 ufs_debugfs_exit(); 10674 scsi_unregister_driver(&ufs_dev_wlun_template.gendrv); 10675 } 10676 10677 module_init(ufshcd_core_init); 10678 module_exit(ufshcd_core_exit); 10679 10680 MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>"); 10681 MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>"); 10682 MODULE_DESCRIPTION("Generic UFS host controller driver Core"); 10683 MODULE_SOFTDEP("pre: governor_simpleondemand"); 10684 MODULE_LICENSE("GPL"); 10685