1 // SPDX-License-Identifier: GPL-1.0+ 2 /* 3 * Device driver for Microgate SyncLink GT serial adapters. 4 * 5 * written by Paul Fulghum for Microgate Corporation 6 * paulkf@microgate.com 7 * 8 * Microgate and SyncLink are trademarks of Microgate Corporation 9 * 10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 12 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 13 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 14 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 15 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 16 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 17 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 18 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 19 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 20 * OF THE POSSIBILITY OF SUCH DAMAGE. 21 */ 22 23 /* 24 * DEBUG OUTPUT DEFINITIONS 25 * 26 * uncomment lines below to enable specific types of debug output 27 * 28 * DBGINFO information - most verbose output 29 * DBGERR serious errors 30 * DBGBH bottom half service routine debugging 31 * DBGISR interrupt service routine debugging 32 * DBGDATA output receive and transmit data 33 * DBGTBUF output transmit DMA buffers and registers 34 * DBGRBUF output receive DMA buffers and registers 35 */ 36 37 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt 38 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt 39 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt 40 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt 41 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label)) 42 /*#define DBGTBUF(info) dump_tbufs(info)*/ 43 /*#define DBGRBUF(info) dump_rbufs(info)*/ 44 45 46 #include <linux/module.h> 47 #include <linux/errno.h> 48 #include <linux/signal.h> 49 #include <linux/sched.h> 50 #include <linux/timer.h> 51 #include <linux/interrupt.h> 52 #include <linux/pci.h> 53 #include <linux/tty.h> 54 #include <linux/tty_flip.h> 55 #include <linux/serial.h> 56 #include <linux/major.h> 57 #include <linux/string.h> 58 #include <linux/fcntl.h> 59 #include <linux/ptrace.h> 60 #include <linux/ioport.h> 61 #include <linux/mm.h> 62 #include <linux/seq_file.h> 63 #include <linux/slab.h> 64 #include <linux/netdevice.h> 65 #include <linux/vmalloc.h> 66 #include <linux/init.h> 67 #include <linux/delay.h> 68 #include <linux/ioctl.h> 69 #include <linux/termios.h> 70 #include <linux/bitops.h> 71 #include <linux/workqueue.h> 72 #include <linux/hdlc.h> 73 #include <linux/synclink.h> 74 75 #include <asm/io.h> 76 #include <asm/irq.h> 77 #include <asm/dma.h> 78 #include <asm/types.h> 79 #include <linux/uaccess.h> 80 81 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE)) 82 #define SYNCLINK_GENERIC_HDLC 1 83 #else 84 #define SYNCLINK_GENERIC_HDLC 0 85 #endif 86 87 /* 88 * module identification 89 */ 90 static char *driver_name = "SyncLink GT"; 91 static char *slgt_driver_name = "synclink_gt"; 92 static char *tty_dev_prefix = "ttySLG"; 93 MODULE_LICENSE("GPL"); 94 #define MGSL_MAGIC 0x5401 95 #define MAX_DEVICES 32 96 97 static const struct pci_device_id pci_table[] = { 98 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, 99 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, 100 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, 101 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, 102 {0,}, /* terminate list */ 103 }; 104 MODULE_DEVICE_TABLE(pci, pci_table); 105 106 static int init_one(struct pci_dev *dev,const struct pci_device_id *ent); 107 static void remove_one(struct pci_dev *dev); 108 static struct pci_driver pci_driver = { 109 .name = "synclink_gt", 110 .id_table = pci_table, 111 .probe = init_one, 112 .remove = remove_one, 113 }; 114 115 static bool pci_registered; 116 117 /* 118 * module configuration and status 119 */ 120 static struct slgt_info *slgt_device_list; 121 static int slgt_device_count; 122 123 static int ttymajor; 124 static int debug_level; 125 static int maxframe[MAX_DEVICES]; 126 127 module_param(ttymajor, int, 0); 128 module_param(debug_level, int, 0); 129 module_param_array(maxframe, int, NULL, 0); 130 131 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned"); 132 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail"); 133 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)"); 134 135 /* 136 * tty support and callbacks 137 */ 138 static struct tty_driver *serial_driver; 139 140 static int open(struct tty_struct *tty, struct file * filp); 141 static void close(struct tty_struct *tty, struct file * filp); 142 static void hangup(struct tty_struct *tty); 143 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios); 144 145 static int write(struct tty_struct *tty, const unsigned char *buf, int count); 146 static int put_char(struct tty_struct *tty, unsigned char ch); 147 static void send_xchar(struct tty_struct *tty, char ch); 148 static void wait_until_sent(struct tty_struct *tty, int timeout); 149 static int write_room(struct tty_struct *tty); 150 static void flush_chars(struct tty_struct *tty); 151 static void flush_buffer(struct tty_struct *tty); 152 static void tx_hold(struct tty_struct *tty); 153 static void tx_release(struct tty_struct *tty); 154 155 static int ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg); 156 static int chars_in_buffer(struct tty_struct *tty); 157 static void throttle(struct tty_struct * tty); 158 static void unthrottle(struct tty_struct * tty); 159 static int set_break(struct tty_struct *tty, int break_state); 160 161 /* 162 * generic HDLC support and callbacks 163 */ 164 #if SYNCLINK_GENERIC_HDLC 165 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 166 static void hdlcdev_tx_done(struct slgt_info *info); 167 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size); 168 static int hdlcdev_init(struct slgt_info *info); 169 static void hdlcdev_exit(struct slgt_info *info); 170 #endif 171 172 173 /* 174 * device specific structures, macros and functions 175 */ 176 177 #define SLGT_MAX_PORTS 4 178 #define SLGT_REG_SIZE 256 179 180 /* 181 * conditional wait facility 182 */ 183 struct cond_wait { 184 struct cond_wait *next; 185 wait_queue_head_t q; 186 wait_queue_entry_t wait; 187 unsigned int data; 188 }; 189 static void init_cond_wait(struct cond_wait *w, unsigned int data); 190 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w); 191 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w); 192 static void flush_cond_wait(struct cond_wait **head); 193 194 /* 195 * DMA buffer descriptor and access macros 196 */ 197 struct slgt_desc 198 { 199 __le16 count; 200 __le16 status; 201 __le32 pbuf; /* physical address of data buffer */ 202 __le32 next; /* physical address of next descriptor */ 203 204 /* driver book keeping */ 205 char *buf; /* virtual address of data buffer */ 206 unsigned int pdesc; /* physical address of this descriptor */ 207 dma_addr_t buf_dma_addr; 208 unsigned short buf_count; 209 }; 210 211 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b)) 212 #define set_desc_next(a,b) (a).next = cpu_to_le32((unsigned int)(b)) 213 #define set_desc_count(a,b)(a).count = cpu_to_le16((unsigned short)(b)) 214 #define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0)) 215 #define set_desc_status(a, b) (a).status = cpu_to_le16((unsigned short)(b)) 216 #define desc_count(a) (le16_to_cpu((a).count)) 217 #define desc_status(a) (le16_to_cpu((a).status)) 218 #define desc_complete(a) (le16_to_cpu((a).status) & BIT15) 219 #define desc_eof(a) (le16_to_cpu((a).status) & BIT2) 220 #define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1) 221 #define desc_abort(a) (le16_to_cpu((a).status) & BIT0) 222 #define desc_residue(a) ((le16_to_cpu((a).status) & 0x38) >> 3) 223 224 struct _input_signal_events { 225 int ri_up; 226 int ri_down; 227 int dsr_up; 228 int dsr_down; 229 int dcd_up; 230 int dcd_down; 231 int cts_up; 232 int cts_down; 233 }; 234 235 /* 236 * device instance data structure 237 */ 238 struct slgt_info { 239 void *if_ptr; /* General purpose pointer (used by SPPP) */ 240 struct tty_port port; 241 242 struct slgt_info *next_device; /* device list link */ 243 244 int magic; 245 246 char device_name[25]; 247 struct pci_dev *pdev; 248 249 int port_count; /* count of ports on adapter */ 250 int adapter_num; /* adapter instance number */ 251 int port_num; /* port instance number */ 252 253 /* array of pointers to port contexts on this adapter */ 254 struct slgt_info *port_array[SLGT_MAX_PORTS]; 255 256 int line; /* tty line instance number */ 257 258 struct mgsl_icount icount; 259 260 int timeout; 261 int x_char; /* xon/xoff character */ 262 unsigned int read_status_mask; 263 unsigned int ignore_status_mask; 264 265 wait_queue_head_t status_event_wait_q; 266 wait_queue_head_t event_wait_q; 267 struct timer_list tx_timer; 268 struct timer_list rx_timer; 269 270 unsigned int gpio_present; 271 struct cond_wait *gpio_wait_q; 272 273 spinlock_t lock; /* spinlock for synchronizing with ISR */ 274 275 struct work_struct task; 276 u32 pending_bh; 277 bool bh_requested; 278 bool bh_running; 279 280 int isr_overflow; 281 bool irq_requested; /* true if IRQ requested */ 282 bool irq_occurred; /* for diagnostics use */ 283 284 /* device configuration */ 285 286 unsigned int bus_type; 287 unsigned int irq_level; 288 unsigned long irq_flags; 289 290 unsigned char __iomem * reg_addr; /* memory mapped registers address */ 291 u32 phys_reg_addr; 292 bool reg_addr_requested; 293 294 MGSL_PARAMS params; /* communications parameters */ 295 u32 idle_mode; 296 u32 max_frame_size; /* as set by device config */ 297 298 unsigned int rbuf_fill_level; 299 unsigned int rx_pio; 300 unsigned int if_mode; 301 unsigned int base_clock; 302 unsigned int xsync; 303 unsigned int xctrl; 304 305 /* device status */ 306 307 bool rx_enabled; 308 bool rx_restart; 309 310 bool tx_enabled; 311 bool tx_active; 312 313 unsigned char signals; /* serial signal states */ 314 int init_error; /* initialization error */ 315 316 unsigned char *tx_buf; 317 int tx_count; 318 319 char *flag_buf; 320 bool drop_rts_on_tx_done; 321 struct _input_signal_events input_signal_events; 322 323 int dcd_chkcount; /* check counts to prevent */ 324 int cts_chkcount; /* too many IRQs if a signal */ 325 int dsr_chkcount; /* is floating */ 326 int ri_chkcount; 327 328 char *bufs; /* virtual address of DMA buffer lists */ 329 dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */ 330 331 unsigned int rbuf_count; 332 struct slgt_desc *rbufs; 333 unsigned int rbuf_current; 334 unsigned int rbuf_index; 335 unsigned int rbuf_fill_index; 336 unsigned short rbuf_fill_count; 337 338 unsigned int tbuf_count; 339 struct slgt_desc *tbufs; 340 unsigned int tbuf_current; 341 unsigned int tbuf_start; 342 343 unsigned char *tmp_rbuf; 344 unsigned int tmp_rbuf_count; 345 346 /* SPPP/Cisco HDLC device parts */ 347 348 int netcount; 349 spinlock_t netlock; 350 #if SYNCLINK_GENERIC_HDLC 351 struct net_device *netdev; 352 #endif 353 354 }; 355 356 static MGSL_PARAMS default_params = { 357 .mode = MGSL_MODE_HDLC, 358 .loopback = 0, 359 .flags = HDLC_FLAG_UNDERRUN_ABORT15, 360 .encoding = HDLC_ENCODING_NRZI_SPACE, 361 .clock_speed = 0, 362 .addr_filter = 0xff, 363 .crc_type = HDLC_CRC_16_CCITT, 364 .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS, 365 .preamble = HDLC_PREAMBLE_PATTERN_NONE, 366 .data_rate = 9600, 367 .data_bits = 8, 368 .stop_bits = 1, 369 .parity = ASYNC_PARITY_NONE 370 }; 371 372 373 #define BH_RECEIVE 1 374 #define BH_TRANSMIT 2 375 #define BH_STATUS 4 376 #define IO_PIN_SHUTDOWN_LIMIT 100 377 378 #define DMABUFSIZE 256 379 #define DESC_LIST_SIZE 4096 380 381 #define MASK_PARITY BIT1 382 #define MASK_FRAMING BIT0 383 #define MASK_BREAK BIT14 384 #define MASK_OVERRUN BIT4 385 386 #define GSR 0x00 /* global status */ 387 #define JCR 0x04 /* JTAG control */ 388 #define IODR 0x08 /* GPIO direction */ 389 #define IOER 0x0c /* GPIO interrupt enable */ 390 #define IOVR 0x10 /* GPIO value */ 391 #define IOSR 0x14 /* GPIO interrupt status */ 392 #define TDR 0x80 /* tx data */ 393 #define RDR 0x80 /* rx data */ 394 #define TCR 0x82 /* tx control */ 395 #define TIR 0x84 /* tx idle */ 396 #define TPR 0x85 /* tx preamble */ 397 #define RCR 0x86 /* rx control */ 398 #define VCR 0x88 /* V.24 control */ 399 #define CCR 0x89 /* clock control */ 400 #define BDR 0x8a /* baud divisor */ 401 #define SCR 0x8c /* serial control */ 402 #define SSR 0x8e /* serial status */ 403 #define RDCSR 0x90 /* rx DMA control/status */ 404 #define TDCSR 0x94 /* tx DMA control/status */ 405 #define RDDAR 0x98 /* rx DMA descriptor address */ 406 #define TDDAR 0x9c /* tx DMA descriptor address */ 407 #define XSR 0x40 /* extended sync pattern */ 408 #define XCR 0x44 /* extended control */ 409 410 #define RXIDLE BIT14 411 #define RXBREAK BIT14 412 #define IRQ_TXDATA BIT13 413 #define IRQ_TXIDLE BIT12 414 #define IRQ_TXUNDER BIT11 /* HDLC */ 415 #define IRQ_RXDATA BIT10 416 #define IRQ_RXIDLE BIT9 /* HDLC */ 417 #define IRQ_RXBREAK BIT9 /* async */ 418 #define IRQ_RXOVER BIT8 419 #define IRQ_DSR BIT7 420 #define IRQ_CTS BIT6 421 #define IRQ_DCD BIT5 422 #define IRQ_RI BIT4 423 #define IRQ_ALL 0x3ff0 424 #define IRQ_MASTER BIT0 425 426 #define slgt_irq_on(info, mask) \ 427 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask))) 428 #define slgt_irq_off(info, mask) \ 429 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask))) 430 431 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr); 432 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value); 433 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr); 434 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value); 435 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr); 436 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value); 437 438 static void msc_set_vcr(struct slgt_info *info); 439 440 static int startup(struct slgt_info *info); 441 static int block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info); 442 static void shutdown(struct slgt_info *info); 443 static void program_hw(struct slgt_info *info); 444 static void change_params(struct slgt_info *info); 445 446 static int register_test(struct slgt_info *info); 447 static int irq_test(struct slgt_info *info); 448 static int loopback_test(struct slgt_info *info); 449 static int adapter_test(struct slgt_info *info); 450 451 static void reset_adapter(struct slgt_info *info); 452 static void reset_port(struct slgt_info *info); 453 static void async_mode(struct slgt_info *info); 454 static void sync_mode(struct slgt_info *info); 455 456 static void rx_stop(struct slgt_info *info); 457 static void rx_start(struct slgt_info *info); 458 static void reset_rbufs(struct slgt_info *info); 459 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last); 460 static void rdma_reset(struct slgt_info *info); 461 static bool rx_get_frame(struct slgt_info *info); 462 static bool rx_get_buf(struct slgt_info *info); 463 464 static void tx_start(struct slgt_info *info); 465 static void tx_stop(struct slgt_info *info); 466 static void tx_set_idle(struct slgt_info *info); 467 static unsigned int free_tbuf_count(struct slgt_info *info); 468 static unsigned int tbuf_bytes(struct slgt_info *info); 469 static void reset_tbufs(struct slgt_info *info); 470 static void tdma_reset(struct slgt_info *info); 471 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int count); 472 473 static void get_signals(struct slgt_info *info); 474 static void set_signals(struct slgt_info *info); 475 static void enable_loopback(struct slgt_info *info); 476 static void set_rate(struct slgt_info *info, u32 data_rate); 477 478 static int bh_action(struct slgt_info *info); 479 static void bh_handler(struct work_struct *work); 480 static void bh_transmit(struct slgt_info *info); 481 static void isr_serial(struct slgt_info *info); 482 static void isr_rdma(struct slgt_info *info); 483 static void isr_txeom(struct slgt_info *info, unsigned short status); 484 static void isr_tdma(struct slgt_info *info); 485 486 static int alloc_dma_bufs(struct slgt_info *info); 487 static void free_dma_bufs(struct slgt_info *info); 488 static int alloc_desc(struct slgt_info *info); 489 static void free_desc(struct slgt_info *info); 490 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count); 491 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count); 492 493 static int alloc_tmp_rbuf(struct slgt_info *info); 494 static void free_tmp_rbuf(struct slgt_info *info); 495 496 static void tx_timeout(struct timer_list *t); 497 static void rx_timeout(struct timer_list *t); 498 499 /* 500 * ioctl handlers 501 */ 502 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount); 503 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *params); 504 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *params); 505 static int get_txidle(struct slgt_info *info, int __user *idle_mode); 506 static int set_txidle(struct slgt_info *info, int idle_mode); 507 static int tx_enable(struct slgt_info *info, int enable); 508 static int tx_abort(struct slgt_info *info); 509 static int rx_enable(struct slgt_info *info, int enable); 510 static int modem_input_wait(struct slgt_info *info,int arg); 511 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr); 512 static int tiocmget(struct tty_struct *tty); 513 static int tiocmset(struct tty_struct *tty, 514 unsigned int set, unsigned int clear); 515 static int set_break(struct tty_struct *tty, int break_state); 516 static int get_interface(struct slgt_info *info, int __user *if_mode); 517 static int set_interface(struct slgt_info *info, int if_mode); 518 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio); 519 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio); 520 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio); 521 static int get_xsync(struct slgt_info *info, int __user *if_mode); 522 static int set_xsync(struct slgt_info *info, int if_mode); 523 static int get_xctrl(struct slgt_info *info, int __user *if_mode); 524 static int set_xctrl(struct slgt_info *info, int if_mode); 525 526 /* 527 * driver functions 528 */ 529 static void add_device(struct slgt_info *info); 530 static void device_init(int adapter_num, struct pci_dev *pdev); 531 static int claim_resources(struct slgt_info *info); 532 static void release_resources(struct slgt_info *info); 533 534 /* 535 * DEBUG OUTPUT CODE 536 */ 537 #ifndef DBGINFO 538 #define DBGINFO(fmt) 539 #endif 540 #ifndef DBGERR 541 #define DBGERR(fmt) 542 #endif 543 #ifndef DBGBH 544 #define DBGBH(fmt) 545 #endif 546 #ifndef DBGISR 547 #define DBGISR(fmt) 548 #endif 549 550 #ifdef DBGDATA 551 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label) 552 { 553 int i; 554 int linecount; 555 printk("%s %s data:\n",info->device_name, label); 556 while(count) { 557 linecount = (count > 16) ? 16 : count; 558 for(i=0; i < linecount; i++) 559 printk("%02X ",(unsigned char)data[i]); 560 for(;i<17;i++) 561 printk(" "); 562 for(i=0;i<linecount;i++) { 563 if (data[i]>=040 && data[i]<=0176) 564 printk("%c",data[i]); 565 else 566 printk("."); 567 } 568 printk("\n"); 569 data += linecount; 570 count -= linecount; 571 } 572 } 573 #else 574 #define DBGDATA(info, buf, size, label) 575 #endif 576 577 #ifdef DBGTBUF 578 static void dump_tbufs(struct slgt_info *info) 579 { 580 int i; 581 printk("tbuf_current=%d\n", info->tbuf_current); 582 for (i=0 ; i < info->tbuf_count ; i++) { 583 printk("%d: count=%04X status=%04X\n", 584 i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status)); 585 } 586 } 587 #else 588 #define DBGTBUF(info) 589 #endif 590 591 #ifdef DBGRBUF 592 static void dump_rbufs(struct slgt_info *info) 593 { 594 int i; 595 printk("rbuf_current=%d\n", info->rbuf_current); 596 for (i=0 ; i < info->rbuf_count ; i++) { 597 printk("%d: count=%04X status=%04X\n", 598 i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status)); 599 } 600 } 601 #else 602 #define DBGRBUF(info) 603 #endif 604 605 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name) 606 { 607 #ifdef SANITY_CHECK 608 if (!info) { 609 printk("null struct slgt_info for (%s) in %s\n", devname, name); 610 return 1; 611 } 612 if (info->magic != MGSL_MAGIC) { 613 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name); 614 return 1; 615 } 616 #else 617 if (!info) 618 return 1; 619 #endif 620 return 0; 621 } 622 623 /* 624 * line discipline callback wrappers 625 * 626 * The wrappers maintain line discipline references 627 * while calling into the line discipline. 628 * 629 * ldisc_receive_buf - pass receive data to line discipline 630 */ 631 static void ldisc_receive_buf(struct tty_struct *tty, 632 const __u8 *data, char *flags, int count) 633 { 634 struct tty_ldisc *ld; 635 if (!tty) 636 return; 637 ld = tty_ldisc_ref(tty); 638 if (ld) { 639 if (ld->ops->receive_buf) 640 ld->ops->receive_buf(tty, data, flags, count); 641 tty_ldisc_deref(ld); 642 } 643 } 644 645 /* tty callbacks */ 646 647 static int open(struct tty_struct *tty, struct file *filp) 648 { 649 struct slgt_info *info; 650 int retval, line; 651 unsigned long flags; 652 653 line = tty->index; 654 if (line >= slgt_device_count) { 655 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line)); 656 return -ENODEV; 657 } 658 659 info = slgt_device_list; 660 while(info && info->line != line) 661 info = info->next_device; 662 if (sanity_check(info, tty->name, "open")) 663 return -ENODEV; 664 if (info->init_error) { 665 DBGERR(("%s init error=%d\n", info->device_name, info->init_error)); 666 return -ENODEV; 667 } 668 669 tty->driver_data = info; 670 info->port.tty = tty; 671 672 DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count)); 673 674 mutex_lock(&info->port.mutex); 675 info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0; 676 677 spin_lock_irqsave(&info->netlock, flags); 678 if (info->netcount) { 679 retval = -EBUSY; 680 spin_unlock_irqrestore(&info->netlock, flags); 681 mutex_unlock(&info->port.mutex); 682 goto cleanup; 683 } 684 info->port.count++; 685 spin_unlock_irqrestore(&info->netlock, flags); 686 687 if (info->port.count == 1) { 688 /* 1st open on this device, init hardware */ 689 retval = startup(info); 690 if (retval < 0) { 691 mutex_unlock(&info->port.mutex); 692 goto cleanup; 693 } 694 } 695 mutex_unlock(&info->port.mutex); 696 retval = block_til_ready(tty, filp, info); 697 if (retval) { 698 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval)); 699 goto cleanup; 700 } 701 702 retval = 0; 703 704 cleanup: 705 if (retval) { 706 if (tty->count == 1) 707 info->port.tty = NULL; /* tty layer will release tty struct */ 708 if(info->port.count) 709 info->port.count--; 710 } 711 712 DBGINFO(("%s open rc=%d\n", info->device_name, retval)); 713 return retval; 714 } 715 716 static void close(struct tty_struct *tty, struct file *filp) 717 { 718 struct slgt_info *info = tty->driver_data; 719 720 if (sanity_check(info, tty->name, "close")) 721 return; 722 DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count)); 723 724 if (tty_port_close_start(&info->port, tty, filp) == 0) 725 goto cleanup; 726 727 mutex_lock(&info->port.mutex); 728 if (tty_port_initialized(&info->port)) 729 wait_until_sent(tty, info->timeout); 730 flush_buffer(tty); 731 tty_ldisc_flush(tty); 732 733 shutdown(info); 734 mutex_unlock(&info->port.mutex); 735 736 tty_port_close_end(&info->port, tty); 737 info->port.tty = NULL; 738 cleanup: 739 DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count)); 740 } 741 742 static void hangup(struct tty_struct *tty) 743 { 744 struct slgt_info *info = tty->driver_data; 745 unsigned long flags; 746 747 if (sanity_check(info, tty->name, "hangup")) 748 return; 749 DBGINFO(("%s hangup\n", info->device_name)); 750 751 flush_buffer(tty); 752 753 mutex_lock(&info->port.mutex); 754 shutdown(info); 755 756 spin_lock_irqsave(&info->port.lock, flags); 757 info->port.count = 0; 758 info->port.tty = NULL; 759 spin_unlock_irqrestore(&info->port.lock, flags); 760 tty_port_set_active(&info->port, 0); 761 mutex_unlock(&info->port.mutex); 762 763 wake_up_interruptible(&info->port.open_wait); 764 } 765 766 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios) 767 { 768 struct slgt_info *info = tty->driver_data; 769 unsigned long flags; 770 771 DBGINFO(("%s set_termios\n", tty->driver->name)); 772 773 change_params(info); 774 775 /* Handle transition to B0 status */ 776 if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) { 777 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR); 778 spin_lock_irqsave(&info->lock,flags); 779 set_signals(info); 780 spin_unlock_irqrestore(&info->lock,flags); 781 } 782 783 /* Handle transition away from B0 status */ 784 if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) { 785 info->signals |= SerialSignal_DTR; 786 if (!C_CRTSCTS(tty) || !tty_throttled(tty)) 787 info->signals |= SerialSignal_RTS; 788 spin_lock_irqsave(&info->lock,flags); 789 set_signals(info); 790 spin_unlock_irqrestore(&info->lock,flags); 791 } 792 793 /* Handle turning off CRTSCTS */ 794 if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty)) { 795 tty->hw_stopped = 0; 796 tx_release(tty); 797 } 798 } 799 800 static void update_tx_timer(struct slgt_info *info) 801 { 802 /* 803 * use worst case speed of 1200bps to calculate transmit timeout 804 * based on data in buffers (tbuf_bytes) and FIFO (128 bytes) 805 */ 806 if (info->params.mode == MGSL_MODE_HDLC) { 807 int timeout = (tbuf_bytes(info) * 7) + 1000; 808 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(timeout)); 809 } 810 } 811 812 static int write(struct tty_struct *tty, 813 const unsigned char *buf, int count) 814 { 815 int ret = 0; 816 struct slgt_info *info = tty->driver_data; 817 unsigned long flags; 818 819 if (sanity_check(info, tty->name, "write")) 820 return -EIO; 821 822 DBGINFO(("%s write count=%d\n", info->device_name, count)); 823 824 if (!info->tx_buf || (count > info->max_frame_size)) 825 return -EIO; 826 827 if (!count || tty->stopped || tty->hw_stopped) 828 return 0; 829 830 spin_lock_irqsave(&info->lock, flags); 831 832 if (info->tx_count) { 833 /* send accumulated data from send_char() */ 834 if (!tx_load(info, info->tx_buf, info->tx_count)) 835 goto cleanup; 836 info->tx_count = 0; 837 } 838 839 if (tx_load(info, buf, count)) 840 ret = count; 841 842 cleanup: 843 spin_unlock_irqrestore(&info->lock, flags); 844 DBGINFO(("%s write rc=%d\n", info->device_name, ret)); 845 return ret; 846 } 847 848 static int put_char(struct tty_struct *tty, unsigned char ch) 849 { 850 struct slgt_info *info = tty->driver_data; 851 unsigned long flags; 852 int ret = 0; 853 854 if (sanity_check(info, tty->name, "put_char")) 855 return 0; 856 DBGINFO(("%s put_char(%d)\n", info->device_name, ch)); 857 if (!info->tx_buf) 858 return 0; 859 spin_lock_irqsave(&info->lock,flags); 860 if (info->tx_count < info->max_frame_size) { 861 info->tx_buf[info->tx_count++] = ch; 862 ret = 1; 863 } 864 spin_unlock_irqrestore(&info->lock,flags); 865 return ret; 866 } 867 868 static void send_xchar(struct tty_struct *tty, char ch) 869 { 870 struct slgt_info *info = tty->driver_data; 871 unsigned long flags; 872 873 if (sanity_check(info, tty->name, "send_xchar")) 874 return; 875 DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch)); 876 info->x_char = ch; 877 if (ch) { 878 spin_lock_irqsave(&info->lock,flags); 879 if (!info->tx_enabled) 880 tx_start(info); 881 spin_unlock_irqrestore(&info->lock,flags); 882 } 883 } 884 885 static void wait_until_sent(struct tty_struct *tty, int timeout) 886 { 887 struct slgt_info *info = tty->driver_data; 888 unsigned long orig_jiffies, char_time; 889 890 if (!info ) 891 return; 892 if (sanity_check(info, tty->name, "wait_until_sent")) 893 return; 894 DBGINFO(("%s wait_until_sent entry\n", info->device_name)); 895 if (!tty_port_initialized(&info->port)) 896 goto exit; 897 898 orig_jiffies = jiffies; 899 900 /* Set check interval to 1/5 of estimated time to 901 * send a character, and make it at least 1. The check 902 * interval should also be less than the timeout. 903 * Note: use tight timings here to satisfy the NIST-PCTS. 904 */ 905 906 if (info->params.data_rate) { 907 char_time = info->timeout/(32 * 5); 908 if (!char_time) 909 char_time++; 910 } else 911 char_time = 1; 912 913 if (timeout) 914 char_time = min_t(unsigned long, char_time, timeout); 915 916 while (info->tx_active) { 917 msleep_interruptible(jiffies_to_msecs(char_time)); 918 if (signal_pending(current)) 919 break; 920 if (timeout && time_after(jiffies, orig_jiffies + timeout)) 921 break; 922 } 923 exit: 924 DBGINFO(("%s wait_until_sent exit\n", info->device_name)); 925 } 926 927 static int write_room(struct tty_struct *tty) 928 { 929 struct slgt_info *info = tty->driver_data; 930 int ret; 931 932 if (sanity_check(info, tty->name, "write_room")) 933 return 0; 934 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE; 935 DBGINFO(("%s write_room=%d\n", info->device_name, ret)); 936 return ret; 937 } 938 939 static void flush_chars(struct tty_struct *tty) 940 { 941 struct slgt_info *info = tty->driver_data; 942 unsigned long flags; 943 944 if (sanity_check(info, tty->name, "flush_chars")) 945 return; 946 DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count)); 947 948 if (info->tx_count <= 0 || tty->stopped || 949 tty->hw_stopped || !info->tx_buf) 950 return; 951 952 DBGINFO(("%s flush_chars start transmit\n", info->device_name)); 953 954 spin_lock_irqsave(&info->lock,flags); 955 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count)) 956 info->tx_count = 0; 957 spin_unlock_irqrestore(&info->lock,flags); 958 } 959 960 static void flush_buffer(struct tty_struct *tty) 961 { 962 struct slgt_info *info = tty->driver_data; 963 unsigned long flags; 964 965 if (sanity_check(info, tty->name, "flush_buffer")) 966 return; 967 DBGINFO(("%s flush_buffer\n", info->device_name)); 968 969 spin_lock_irqsave(&info->lock, flags); 970 info->tx_count = 0; 971 spin_unlock_irqrestore(&info->lock, flags); 972 973 tty_wakeup(tty); 974 } 975 976 /* 977 * throttle (stop) transmitter 978 */ 979 static void tx_hold(struct tty_struct *tty) 980 { 981 struct slgt_info *info = tty->driver_data; 982 unsigned long flags; 983 984 if (sanity_check(info, tty->name, "tx_hold")) 985 return; 986 DBGINFO(("%s tx_hold\n", info->device_name)); 987 spin_lock_irqsave(&info->lock,flags); 988 if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC) 989 tx_stop(info); 990 spin_unlock_irqrestore(&info->lock,flags); 991 } 992 993 /* 994 * release (start) transmitter 995 */ 996 static void tx_release(struct tty_struct *tty) 997 { 998 struct slgt_info *info = tty->driver_data; 999 unsigned long flags; 1000 1001 if (sanity_check(info, tty->name, "tx_release")) 1002 return; 1003 DBGINFO(("%s tx_release\n", info->device_name)); 1004 spin_lock_irqsave(&info->lock, flags); 1005 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count)) 1006 info->tx_count = 0; 1007 spin_unlock_irqrestore(&info->lock, flags); 1008 } 1009 1010 /* 1011 * Service an IOCTL request 1012 * 1013 * Arguments 1014 * 1015 * tty pointer to tty instance data 1016 * cmd IOCTL command code 1017 * arg command argument/context 1018 * 1019 * Return 0 if success, otherwise error code 1020 */ 1021 static int ioctl(struct tty_struct *tty, 1022 unsigned int cmd, unsigned long arg) 1023 { 1024 struct slgt_info *info = tty->driver_data; 1025 void __user *argp = (void __user *)arg; 1026 int ret; 1027 1028 if (sanity_check(info, tty->name, "ioctl")) 1029 return -ENODEV; 1030 DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd)); 1031 1032 if (cmd != TIOCMIWAIT) { 1033 if (tty_io_error(tty)) 1034 return -EIO; 1035 } 1036 1037 switch (cmd) { 1038 case MGSL_IOCWAITEVENT: 1039 return wait_mgsl_event(info, argp); 1040 case TIOCMIWAIT: 1041 return modem_input_wait(info,(int)arg); 1042 case MGSL_IOCSGPIO: 1043 return set_gpio(info, argp); 1044 case MGSL_IOCGGPIO: 1045 return get_gpio(info, argp); 1046 case MGSL_IOCWAITGPIO: 1047 return wait_gpio(info, argp); 1048 case MGSL_IOCGXSYNC: 1049 return get_xsync(info, argp); 1050 case MGSL_IOCSXSYNC: 1051 return set_xsync(info, (int)arg); 1052 case MGSL_IOCGXCTRL: 1053 return get_xctrl(info, argp); 1054 case MGSL_IOCSXCTRL: 1055 return set_xctrl(info, (int)arg); 1056 } 1057 mutex_lock(&info->port.mutex); 1058 switch (cmd) { 1059 case MGSL_IOCGPARAMS: 1060 ret = get_params(info, argp); 1061 break; 1062 case MGSL_IOCSPARAMS: 1063 ret = set_params(info, argp); 1064 break; 1065 case MGSL_IOCGTXIDLE: 1066 ret = get_txidle(info, argp); 1067 break; 1068 case MGSL_IOCSTXIDLE: 1069 ret = set_txidle(info, (int)arg); 1070 break; 1071 case MGSL_IOCTXENABLE: 1072 ret = tx_enable(info, (int)arg); 1073 break; 1074 case MGSL_IOCRXENABLE: 1075 ret = rx_enable(info, (int)arg); 1076 break; 1077 case MGSL_IOCTXABORT: 1078 ret = tx_abort(info); 1079 break; 1080 case MGSL_IOCGSTATS: 1081 ret = get_stats(info, argp); 1082 break; 1083 case MGSL_IOCGIF: 1084 ret = get_interface(info, argp); 1085 break; 1086 case MGSL_IOCSIF: 1087 ret = set_interface(info,(int)arg); 1088 break; 1089 default: 1090 ret = -ENOIOCTLCMD; 1091 } 1092 mutex_unlock(&info->port.mutex); 1093 return ret; 1094 } 1095 1096 static int get_icount(struct tty_struct *tty, 1097 struct serial_icounter_struct *icount) 1098 1099 { 1100 struct slgt_info *info = tty->driver_data; 1101 struct mgsl_icount cnow; /* kernel counter temps */ 1102 unsigned long flags; 1103 1104 spin_lock_irqsave(&info->lock,flags); 1105 cnow = info->icount; 1106 spin_unlock_irqrestore(&info->lock,flags); 1107 1108 icount->cts = cnow.cts; 1109 icount->dsr = cnow.dsr; 1110 icount->rng = cnow.rng; 1111 icount->dcd = cnow.dcd; 1112 icount->rx = cnow.rx; 1113 icount->tx = cnow.tx; 1114 icount->frame = cnow.frame; 1115 icount->overrun = cnow.overrun; 1116 icount->parity = cnow.parity; 1117 icount->brk = cnow.brk; 1118 icount->buf_overrun = cnow.buf_overrun; 1119 1120 return 0; 1121 } 1122 1123 /* 1124 * support for 32 bit ioctl calls on 64 bit systems 1125 */ 1126 #ifdef CONFIG_COMPAT 1127 static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params) 1128 { 1129 struct MGSL_PARAMS32 tmp_params; 1130 1131 DBGINFO(("%s get_params32\n", info->device_name)); 1132 memset(&tmp_params, 0, sizeof(tmp_params)); 1133 tmp_params.mode = (compat_ulong_t)info->params.mode; 1134 tmp_params.loopback = info->params.loopback; 1135 tmp_params.flags = info->params.flags; 1136 tmp_params.encoding = info->params.encoding; 1137 tmp_params.clock_speed = (compat_ulong_t)info->params.clock_speed; 1138 tmp_params.addr_filter = info->params.addr_filter; 1139 tmp_params.crc_type = info->params.crc_type; 1140 tmp_params.preamble_length = info->params.preamble_length; 1141 tmp_params.preamble = info->params.preamble; 1142 tmp_params.data_rate = (compat_ulong_t)info->params.data_rate; 1143 tmp_params.data_bits = info->params.data_bits; 1144 tmp_params.stop_bits = info->params.stop_bits; 1145 tmp_params.parity = info->params.parity; 1146 if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32))) 1147 return -EFAULT; 1148 return 0; 1149 } 1150 1151 static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params) 1152 { 1153 struct MGSL_PARAMS32 tmp_params; 1154 1155 DBGINFO(("%s set_params32\n", info->device_name)); 1156 if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32))) 1157 return -EFAULT; 1158 1159 spin_lock(&info->lock); 1160 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) { 1161 info->base_clock = tmp_params.clock_speed; 1162 } else { 1163 info->params.mode = tmp_params.mode; 1164 info->params.loopback = tmp_params.loopback; 1165 info->params.flags = tmp_params.flags; 1166 info->params.encoding = tmp_params.encoding; 1167 info->params.clock_speed = tmp_params.clock_speed; 1168 info->params.addr_filter = tmp_params.addr_filter; 1169 info->params.crc_type = tmp_params.crc_type; 1170 info->params.preamble_length = tmp_params.preamble_length; 1171 info->params.preamble = tmp_params.preamble; 1172 info->params.data_rate = tmp_params.data_rate; 1173 info->params.data_bits = tmp_params.data_bits; 1174 info->params.stop_bits = tmp_params.stop_bits; 1175 info->params.parity = tmp_params.parity; 1176 } 1177 spin_unlock(&info->lock); 1178 1179 program_hw(info); 1180 1181 return 0; 1182 } 1183 1184 static long slgt_compat_ioctl(struct tty_struct *tty, 1185 unsigned int cmd, unsigned long arg) 1186 { 1187 struct slgt_info *info = tty->driver_data; 1188 int rc; 1189 1190 if (sanity_check(info, tty->name, "compat_ioctl")) 1191 return -ENODEV; 1192 DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd)); 1193 1194 switch (cmd) { 1195 case MGSL_IOCSPARAMS32: 1196 rc = set_params32(info, compat_ptr(arg)); 1197 break; 1198 1199 case MGSL_IOCGPARAMS32: 1200 rc = get_params32(info, compat_ptr(arg)); 1201 break; 1202 1203 case MGSL_IOCGPARAMS: 1204 case MGSL_IOCSPARAMS: 1205 case MGSL_IOCGTXIDLE: 1206 case MGSL_IOCGSTATS: 1207 case MGSL_IOCWAITEVENT: 1208 case MGSL_IOCGIF: 1209 case MGSL_IOCSGPIO: 1210 case MGSL_IOCGGPIO: 1211 case MGSL_IOCWAITGPIO: 1212 case MGSL_IOCGXSYNC: 1213 case MGSL_IOCGXCTRL: 1214 rc = ioctl(tty, cmd, (unsigned long)compat_ptr(arg)); 1215 break; 1216 default: 1217 rc = ioctl(tty, cmd, arg); 1218 } 1219 DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc)); 1220 return rc; 1221 } 1222 #else 1223 #define slgt_compat_ioctl NULL 1224 #endif /* ifdef CONFIG_COMPAT */ 1225 1226 /* 1227 * proc fs support 1228 */ 1229 static inline void line_info(struct seq_file *m, struct slgt_info *info) 1230 { 1231 char stat_buf[30]; 1232 unsigned long flags; 1233 1234 seq_printf(m, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n", 1235 info->device_name, info->phys_reg_addr, 1236 info->irq_level, info->max_frame_size); 1237 1238 /* output current serial signal states */ 1239 spin_lock_irqsave(&info->lock,flags); 1240 get_signals(info); 1241 spin_unlock_irqrestore(&info->lock,flags); 1242 1243 stat_buf[0] = 0; 1244 stat_buf[1] = 0; 1245 if (info->signals & SerialSignal_RTS) 1246 strcat(stat_buf, "|RTS"); 1247 if (info->signals & SerialSignal_CTS) 1248 strcat(stat_buf, "|CTS"); 1249 if (info->signals & SerialSignal_DTR) 1250 strcat(stat_buf, "|DTR"); 1251 if (info->signals & SerialSignal_DSR) 1252 strcat(stat_buf, "|DSR"); 1253 if (info->signals & SerialSignal_DCD) 1254 strcat(stat_buf, "|CD"); 1255 if (info->signals & SerialSignal_RI) 1256 strcat(stat_buf, "|RI"); 1257 1258 if (info->params.mode != MGSL_MODE_ASYNC) { 1259 seq_printf(m, "\tHDLC txok:%d rxok:%d", 1260 info->icount.txok, info->icount.rxok); 1261 if (info->icount.txunder) 1262 seq_printf(m, " txunder:%d", info->icount.txunder); 1263 if (info->icount.txabort) 1264 seq_printf(m, " txabort:%d", info->icount.txabort); 1265 if (info->icount.rxshort) 1266 seq_printf(m, " rxshort:%d", info->icount.rxshort); 1267 if (info->icount.rxlong) 1268 seq_printf(m, " rxlong:%d", info->icount.rxlong); 1269 if (info->icount.rxover) 1270 seq_printf(m, " rxover:%d", info->icount.rxover); 1271 if (info->icount.rxcrc) 1272 seq_printf(m, " rxcrc:%d", info->icount.rxcrc); 1273 } else { 1274 seq_printf(m, "\tASYNC tx:%d rx:%d", 1275 info->icount.tx, info->icount.rx); 1276 if (info->icount.frame) 1277 seq_printf(m, " fe:%d", info->icount.frame); 1278 if (info->icount.parity) 1279 seq_printf(m, " pe:%d", info->icount.parity); 1280 if (info->icount.brk) 1281 seq_printf(m, " brk:%d", info->icount.brk); 1282 if (info->icount.overrun) 1283 seq_printf(m, " oe:%d", info->icount.overrun); 1284 } 1285 1286 /* Append serial signal status to end */ 1287 seq_printf(m, " %s\n", stat_buf+1); 1288 1289 seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n", 1290 info->tx_active,info->bh_requested,info->bh_running, 1291 info->pending_bh); 1292 } 1293 1294 /* Called to print information about devices 1295 */ 1296 static int synclink_gt_proc_show(struct seq_file *m, void *v) 1297 { 1298 struct slgt_info *info; 1299 1300 seq_puts(m, "synclink_gt driver\n"); 1301 1302 info = slgt_device_list; 1303 while( info ) { 1304 line_info(m, info); 1305 info = info->next_device; 1306 } 1307 return 0; 1308 } 1309 1310 /* 1311 * return count of bytes in transmit buffer 1312 */ 1313 static int chars_in_buffer(struct tty_struct *tty) 1314 { 1315 struct slgt_info *info = tty->driver_data; 1316 int count; 1317 if (sanity_check(info, tty->name, "chars_in_buffer")) 1318 return 0; 1319 count = tbuf_bytes(info); 1320 DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, count)); 1321 return count; 1322 } 1323 1324 /* 1325 * signal remote device to throttle send data (our receive data) 1326 */ 1327 static void throttle(struct tty_struct * tty) 1328 { 1329 struct slgt_info *info = tty->driver_data; 1330 unsigned long flags; 1331 1332 if (sanity_check(info, tty->name, "throttle")) 1333 return; 1334 DBGINFO(("%s throttle\n", info->device_name)); 1335 if (I_IXOFF(tty)) 1336 send_xchar(tty, STOP_CHAR(tty)); 1337 if (C_CRTSCTS(tty)) { 1338 spin_lock_irqsave(&info->lock,flags); 1339 info->signals &= ~SerialSignal_RTS; 1340 set_signals(info); 1341 spin_unlock_irqrestore(&info->lock,flags); 1342 } 1343 } 1344 1345 /* 1346 * signal remote device to stop throttling send data (our receive data) 1347 */ 1348 static void unthrottle(struct tty_struct * tty) 1349 { 1350 struct slgt_info *info = tty->driver_data; 1351 unsigned long flags; 1352 1353 if (sanity_check(info, tty->name, "unthrottle")) 1354 return; 1355 DBGINFO(("%s unthrottle\n", info->device_name)); 1356 if (I_IXOFF(tty)) { 1357 if (info->x_char) 1358 info->x_char = 0; 1359 else 1360 send_xchar(tty, START_CHAR(tty)); 1361 } 1362 if (C_CRTSCTS(tty)) { 1363 spin_lock_irqsave(&info->lock,flags); 1364 info->signals |= SerialSignal_RTS; 1365 set_signals(info); 1366 spin_unlock_irqrestore(&info->lock,flags); 1367 } 1368 } 1369 1370 /* 1371 * set or clear transmit break condition 1372 * break_state -1=set break condition, 0=clear 1373 */ 1374 static int set_break(struct tty_struct *tty, int break_state) 1375 { 1376 struct slgt_info *info = tty->driver_data; 1377 unsigned short value; 1378 unsigned long flags; 1379 1380 if (sanity_check(info, tty->name, "set_break")) 1381 return -EINVAL; 1382 DBGINFO(("%s set_break(%d)\n", info->device_name, break_state)); 1383 1384 spin_lock_irqsave(&info->lock,flags); 1385 value = rd_reg16(info, TCR); 1386 if (break_state == -1) 1387 value |= BIT6; 1388 else 1389 value &= ~BIT6; 1390 wr_reg16(info, TCR, value); 1391 spin_unlock_irqrestore(&info->lock,flags); 1392 return 0; 1393 } 1394 1395 #if SYNCLINK_GENERIC_HDLC 1396 1397 /** 1398 * hdlcdev_attach - called by generic HDLC layer when protocol selected (PPP, frame relay, etc.) 1399 * @dev: pointer to network device structure 1400 * @encoding: serial encoding setting 1401 * @parity: FCS setting 1402 * 1403 * Set encoding and frame check sequence (FCS) options. 1404 * 1405 * Return: 0 if success, otherwise error code 1406 */ 1407 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding, 1408 unsigned short parity) 1409 { 1410 struct slgt_info *info = dev_to_port(dev); 1411 unsigned char new_encoding; 1412 unsigned short new_crctype; 1413 1414 /* return error if TTY interface open */ 1415 if (info->port.count) 1416 return -EBUSY; 1417 1418 DBGINFO(("%s hdlcdev_attach\n", info->device_name)); 1419 1420 switch (encoding) 1421 { 1422 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break; 1423 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break; 1424 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break; 1425 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break; 1426 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break; 1427 default: return -EINVAL; 1428 } 1429 1430 switch (parity) 1431 { 1432 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break; 1433 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break; 1434 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break; 1435 default: return -EINVAL; 1436 } 1437 1438 info->params.encoding = new_encoding; 1439 info->params.crc_type = new_crctype; 1440 1441 /* if network interface up, reprogram hardware */ 1442 if (info->netcount) 1443 program_hw(info); 1444 1445 return 0; 1446 } 1447 1448 /** 1449 * hdlcdev_xmit - called by generic HDLC layer to send a frame 1450 * @skb: socket buffer containing HDLC frame 1451 * @dev: pointer to network device structure 1452 */ 1453 static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb, 1454 struct net_device *dev) 1455 { 1456 struct slgt_info *info = dev_to_port(dev); 1457 unsigned long flags; 1458 1459 DBGINFO(("%s hdlc_xmit\n", dev->name)); 1460 1461 if (!skb->len) 1462 return NETDEV_TX_OK; 1463 1464 /* stop sending until this frame completes */ 1465 netif_stop_queue(dev); 1466 1467 /* update network statistics */ 1468 dev->stats.tx_packets++; 1469 dev->stats.tx_bytes += skb->len; 1470 1471 /* save start time for transmit timeout detection */ 1472 netif_trans_update(dev); 1473 1474 spin_lock_irqsave(&info->lock, flags); 1475 tx_load(info, skb->data, skb->len); 1476 spin_unlock_irqrestore(&info->lock, flags); 1477 1478 /* done with socket buffer, so free it */ 1479 dev_kfree_skb(skb); 1480 1481 return NETDEV_TX_OK; 1482 } 1483 1484 /** 1485 * hdlcdev_open - called by network layer when interface enabled 1486 * @dev: pointer to network device structure 1487 * 1488 * Claim resources and initialize hardware. 1489 * 1490 * Return: 0 if success, otherwise error code 1491 */ 1492 static int hdlcdev_open(struct net_device *dev) 1493 { 1494 struct slgt_info *info = dev_to_port(dev); 1495 int rc; 1496 unsigned long flags; 1497 1498 if (!try_module_get(THIS_MODULE)) 1499 return -EBUSY; 1500 1501 DBGINFO(("%s hdlcdev_open\n", dev->name)); 1502 1503 /* generic HDLC layer open processing */ 1504 rc = hdlc_open(dev); 1505 if (rc) 1506 return rc; 1507 1508 /* arbitrate between network and tty opens */ 1509 spin_lock_irqsave(&info->netlock, flags); 1510 if (info->port.count != 0 || info->netcount != 0) { 1511 DBGINFO(("%s hdlc_open busy\n", dev->name)); 1512 spin_unlock_irqrestore(&info->netlock, flags); 1513 return -EBUSY; 1514 } 1515 info->netcount=1; 1516 spin_unlock_irqrestore(&info->netlock, flags); 1517 1518 /* claim resources and init adapter */ 1519 if ((rc = startup(info)) != 0) { 1520 spin_lock_irqsave(&info->netlock, flags); 1521 info->netcount=0; 1522 spin_unlock_irqrestore(&info->netlock, flags); 1523 return rc; 1524 } 1525 1526 /* assert RTS and DTR, apply hardware settings */ 1527 info->signals |= SerialSignal_RTS | SerialSignal_DTR; 1528 program_hw(info); 1529 1530 /* enable network layer transmit */ 1531 netif_trans_update(dev); 1532 netif_start_queue(dev); 1533 1534 /* inform generic HDLC layer of current DCD status */ 1535 spin_lock_irqsave(&info->lock, flags); 1536 get_signals(info); 1537 spin_unlock_irqrestore(&info->lock, flags); 1538 if (info->signals & SerialSignal_DCD) 1539 netif_carrier_on(dev); 1540 else 1541 netif_carrier_off(dev); 1542 return 0; 1543 } 1544 1545 /** 1546 * hdlcdev_close - called by network layer when interface is disabled 1547 * @dev: pointer to network device structure 1548 * 1549 * Shutdown hardware and release resources. 1550 * 1551 * Return: 0 if success, otherwise error code 1552 */ 1553 static int hdlcdev_close(struct net_device *dev) 1554 { 1555 struct slgt_info *info = dev_to_port(dev); 1556 unsigned long flags; 1557 1558 DBGINFO(("%s hdlcdev_close\n", dev->name)); 1559 1560 netif_stop_queue(dev); 1561 1562 /* shutdown adapter and release resources */ 1563 shutdown(info); 1564 1565 hdlc_close(dev); 1566 1567 spin_lock_irqsave(&info->netlock, flags); 1568 info->netcount=0; 1569 spin_unlock_irqrestore(&info->netlock, flags); 1570 1571 module_put(THIS_MODULE); 1572 return 0; 1573 } 1574 1575 /** 1576 * hdlcdev_ioctl - called by network layer to process IOCTL call to network device 1577 * @dev: pointer to network device structure 1578 * @ifr: pointer to network interface request structure 1579 * @cmd: IOCTL command code 1580 * 1581 * Return: 0 if success, otherwise error code 1582 */ 1583 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 1584 { 1585 const size_t size = sizeof(sync_serial_settings); 1586 sync_serial_settings new_line; 1587 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync; 1588 struct slgt_info *info = dev_to_port(dev); 1589 unsigned int flags; 1590 1591 DBGINFO(("%s hdlcdev_ioctl\n", dev->name)); 1592 1593 /* return error if TTY interface open */ 1594 if (info->port.count) 1595 return -EBUSY; 1596 1597 if (cmd != SIOCWANDEV) 1598 return hdlc_ioctl(dev, ifr, cmd); 1599 1600 memset(&new_line, 0, sizeof(new_line)); 1601 1602 switch(ifr->ifr_settings.type) { 1603 case IF_GET_IFACE: /* return current sync_serial_settings */ 1604 1605 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL; 1606 if (ifr->ifr_settings.size < size) { 1607 ifr->ifr_settings.size = size; /* data size wanted */ 1608 return -ENOBUFS; 1609 } 1610 1611 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL | 1612 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN | 1613 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL | 1614 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); 1615 1616 switch (flags){ 1617 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break; 1618 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break; 1619 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break; 1620 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break; 1621 default: new_line.clock_type = CLOCK_DEFAULT; 1622 } 1623 1624 new_line.clock_rate = info->params.clock_speed; 1625 new_line.loopback = info->params.loopback ? 1:0; 1626 1627 if (copy_to_user(line, &new_line, size)) 1628 return -EFAULT; 1629 return 0; 1630 1631 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */ 1632 1633 if(!capable(CAP_NET_ADMIN)) 1634 return -EPERM; 1635 if (copy_from_user(&new_line, line, size)) 1636 return -EFAULT; 1637 1638 switch (new_line.clock_type) 1639 { 1640 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break; 1641 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break; 1642 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break; 1643 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break; 1644 case CLOCK_DEFAULT: flags = info->params.flags & 1645 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL | 1646 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN | 1647 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL | 1648 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break; 1649 default: return -EINVAL; 1650 } 1651 1652 if (new_line.loopback != 0 && new_line.loopback != 1) 1653 return -EINVAL; 1654 1655 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL | 1656 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN | 1657 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL | 1658 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); 1659 info->params.flags |= flags; 1660 1661 info->params.loopback = new_line.loopback; 1662 1663 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG)) 1664 info->params.clock_speed = new_line.clock_rate; 1665 else 1666 info->params.clock_speed = 0; 1667 1668 /* if network interface up, reprogram hardware */ 1669 if (info->netcount) 1670 program_hw(info); 1671 return 0; 1672 1673 default: 1674 return hdlc_ioctl(dev, ifr, cmd); 1675 } 1676 } 1677 1678 /** 1679 * hdlcdev_tx_timeout - called by network layer when transmit timeout is detected 1680 * @dev: pointer to network device structure 1681 * @txqueue: unused 1682 */ 1683 static void hdlcdev_tx_timeout(struct net_device *dev, unsigned int txqueue) 1684 { 1685 struct slgt_info *info = dev_to_port(dev); 1686 unsigned long flags; 1687 1688 DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name)); 1689 1690 dev->stats.tx_errors++; 1691 dev->stats.tx_aborted_errors++; 1692 1693 spin_lock_irqsave(&info->lock,flags); 1694 tx_stop(info); 1695 spin_unlock_irqrestore(&info->lock,flags); 1696 1697 netif_wake_queue(dev); 1698 } 1699 1700 /** 1701 * hdlcdev_tx_done - called by device driver when transmit completes 1702 * @info: pointer to device instance information 1703 * 1704 * Reenable network layer transmit if stopped. 1705 */ 1706 static void hdlcdev_tx_done(struct slgt_info *info) 1707 { 1708 if (netif_queue_stopped(info->netdev)) 1709 netif_wake_queue(info->netdev); 1710 } 1711 1712 /** 1713 * hdlcdev_rx - called by device driver when frame received 1714 * @info: pointer to device instance information 1715 * @buf: pointer to buffer contianing frame data 1716 * @size: count of data bytes in buf 1717 * 1718 * Pass frame to network layer. 1719 */ 1720 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size) 1721 { 1722 struct sk_buff *skb = dev_alloc_skb(size); 1723 struct net_device *dev = info->netdev; 1724 1725 DBGINFO(("%s hdlcdev_rx\n", dev->name)); 1726 1727 if (skb == NULL) { 1728 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name)); 1729 dev->stats.rx_dropped++; 1730 return; 1731 } 1732 1733 skb_put_data(skb, buf, size); 1734 1735 skb->protocol = hdlc_type_trans(skb, dev); 1736 1737 dev->stats.rx_packets++; 1738 dev->stats.rx_bytes += size; 1739 1740 netif_rx(skb); 1741 } 1742 1743 static const struct net_device_ops hdlcdev_ops = { 1744 .ndo_open = hdlcdev_open, 1745 .ndo_stop = hdlcdev_close, 1746 .ndo_start_xmit = hdlc_start_xmit, 1747 .ndo_do_ioctl = hdlcdev_ioctl, 1748 .ndo_tx_timeout = hdlcdev_tx_timeout, 1749 }; 1750 1751 /** 1752 * hdlcdev_init - called by device driver when adding device instance 1753 * @info: pointer to device instance information 1754 * 1755 * Do generic HDLC initialization. 1756 * 1757 * Return: 0 if success, otherwise error code 1758 */ 1759 static int hdlcdev_init(struct slgt_info *info) 1760 { 1761 int rc; 1762 struct net_device *dev; 1763 hdlc_device *hdlc; 1764 1765 /* allocate and initialize network and HDLC layer objects */ 1766 1767 dev = alloc_hdlcdev(info); 1768 if (!dev) { 1769 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name); 1770 return -ENOMEM; 1771 } 1772 1773 /* for network layer reporting purposes only */ 1774 dev->mem_start = info->phys_reg_addr; 1775 dev->mem_end = info->phys_reg_addr + SLGT_REG_SIZE - 1; 1776 dev->irq = info->irq_level; 1777 1778 /* network layer callbacks and settings */ 1779 dev->netdev_ops = &hdlcdev_ops; 1780 dev->watchdog_timeo = 10 * HZ; 1781 dev->tx_queue_len = 50; 1782 1783 /* generic HDLC layer callbacks and settings */ 1784 hdlc = dev_to_hdlc(dev); 1785 hdlc->attach = hdlcdev_attach; 1786 hdlc->xmit = hdlcdev_xmit; 1787 1788 /* register objects with HDLC layer */ 1789 rc = register_hdlc_device(dev); 1790 if (rc) { 1791 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__); 1792 free_netdev(dev); 1793 return rc; 1794 } 1795 1796 info->netdev = dev; 1797 return 0; 1798 } 1799 1800 /** 1801 * hdlcdev_exit - called by device driver when removing device instance 1802 * @info: pointer to device instance information 1803 * 1804 * Do generic HDLC cleanup. 1805 */ 1806 static void hdlcdev_exit(struct slgt_info *info) 1807 { 1808 unregister_hdlc_device(info->netdev); 1809 free_netdev(info->netdev); 1810 info->netdev = NULL; 1811 } 1812 1813 #endif /* ifdef CONFIG_HDLC */ 1814 1815 /* 1816 * get async data from rx DMA buffers 1817 */ 1818 static void rx_async(struct slgt_info *info) 1819 { 1820 struct mgsl_icount *icount = &info->icount; 1821 unsigned int start, end; 1822 unsigned char *p; 1823 unsigned char status; 1824 struct slgt_desc *bufs = info->rbufs; 1825 int i, count; 1826 int chars = 0; 1827 int stat; 1828 unsigned char ch; 1829 1830 start = end = info->rbuf_current; 1831 1832 while(desc_complete(bufs[end])) { 1833 count = desc_count(bufs[end]) - info->rbuf_index; 1834 p = bufs[end].buf + info->rbuf_index; 1835 1836 DBGISR(("%s rx_async count=%d\n", info->device_name, count)); 1837 DBGDATA(info, p, count, "rx"); 1838 1839 for(i=0 ; i < count; i+=2, p+=2) { 1840 ch = *p; 1841 icount->rx++; 1842 1843 stat = 0; 1844 1845 status = *(p + 1) & (BIT1 + BIT0); 1846 if (status) { 1847 if (status & BIT1) 1848 icount->parity++; 1849 else if (status & BIT0) 1850 icount->frame++; 1851 /* discard char if tty control flags say so */ 1852 if (status & info->ignore_status_mask) 1853 continue; 1854 if (status & BIT1) 1855 stat = TTY_PARITY; 1856 else if (status & BIT0) 1857 stat = TTY_FRAME; 1858 } 1859 tty_insert_flip_char(&info->port, ch, stat); 1860 chars++; 1861 } 1862 1863 if (i < count) { 1864 /* receive buffer not completed */ 1865 info->rbuf_index += i; 1866 mod_timer(&info->rx_timer, jiffies + 1); 1867 break; 1868 } 1869 1870 info->rbuf_index = 0; 1871 free_rbufs(info, end, end); 1872 1873 if (++end == info->rbuf_count) 1874 end = 0; 1875 1876 /* if entire list searched then no frame available */ 1877 if (end == start) 1878 break; 1879 } 1880 1881 if (chars) 1882 tty_flip_buffer_push(&info->port); 1883 } 1884 1885 /* 1886 * return next bottom half action to perform 1887 */ 1888 static int bh_action(struct slgt_info *info) 1889 { 1890 unsigned long flags; 1891 int rc; 1892 1893 spin_lock_irqsave(&info->lock,flags); 1894 1895 if (info->pending_bh & BH_RECEIVE) { 1896 info->pending_bh &= ~BH_RECEIVE; 1897 rc = BH_RECEIVE; 1898 } else if (info->pending_bh & BH_TRANSMIT) { 1899 info->pending_bh &= ~BH_TRANSMIT; 1900 rc = BH_TRANSMIT; 1901 } else if (info->pending_bh & BH_STATUS) { 1902 info->pending_bh &= ~BH_STATUS; 1903 rc = BH_STATUS; 1904 } else { 1905 /* Mark BH routine as complete */ 1906 info->bh_running = false; 1907 info->bh_requested = false; 1908 rc = 0; 1909 } 1910 1911 spin_unlock_irqrestore(&info->lock,flags); 1912 1913 return rc; 1914 } 1915 1916 /* 1917 * perform bottom half processing 1918 */ 1919 static void bh_handler(struct work_struct *work) 1920 { 1921 struct slgt_info *info = container_of(work, struct slgt_info, task); 1922 int action; 1923 1924 info->bh_running = true; 1925 1926 while((action = bh_action(info))) { 1927 switch (action) { 1928 case BH_RECEIVE: 1929 DBGBH(("%s bh receive\n", info->device_name)); 1930 switch(info->params.mode) { 1931 case MGSL_MODE_ASYNC: 1932 rx_async(info); 1933 break; 1934 case MGSL_MODE_HDLC: 1935 while(rx_get_frame(info)); 1936 break; 1937 case MGSL_MODE_RAW: 1938 case MGSL_MODE_MONOSYNC: 1939 case MGSL_MODE_BISYNC: 1940 case MGSL_MODE_XSYNC: 1941 while(rx_get_buf(info)); 1942 break; 1943 } 1944 /* restart receiver if rx DMA buffers exhausted */ 1945 if (info->rx_restart) 1946 rx_start(info); 1947 break; 1948 case BH_TRANSMIT: 1949 bh_transmit(info); 1950 break; 1951 case BH_STATUS: 1952 DBGBH(("%s bh status\n", info->device_name)); 1953 info->ri_chkcount = 0; 1954 info->dsr_chkcount = 0; 1955 info->dcd_chkcount = 0; 1956 info->cts_chkcount = 0; 1957 break; 1958 default: 1959 DBGBH(("%s unknown action\n", info->device_name)); 1960 break; 1961 } 1962 } 1963 DBGBH(("%s bh_handler exit\n", info->device_name)); 1964 } 1965 1966 static void bh_transmit(struct slgt_info *info) 1967 { 1968 struct tty_struct *tty = info->port.tty; 1969 1970 DBGBH(("%s bh_transmit\n", info->device_name)); 1971 if (tty) 1972 tty_wakeup(tty); 1973 } 1974 1975 static void dsr_change(struct slgt_info *info, unsigned short status) 1976 { 1977 if (status & BIT3) { 1978 info->signals |= SerialSignal_DSR; 1979 info->input_signal_events.dsr_up++; 1980 } else { 1981 info->signals &= ~SerialSignal_DSR; 1982 info->input_signal_events.dsr_down++; 1983 } 1984 DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals)); 1985 if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) { 1986 slgt_irq_off(info, IRQ_DSR); 1987 return; 1988 } 1989 info->icount.dsr++; 1990 wake_up_interruptible(&info->status_event_wait_q); 1991 wake_up_interruptible(&info->event_wait_q); 1992 info->pending_bh |= BH_STATUS; 1993 } 1994 1995 static void cts_change(struct slgt_info *info, unsigned short status) 1996 { 1997 if (status & BIT2) { 1998 info->signals |= SerialSignal_CTS; 1999 info->input_signal_events.cts_up++; 2000 } else { 2001 info->signals &= ~SerialSignal_CTS; 2002 info->input_signal_events.cts_down++; 2003 } 2004 DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals)); 2005 if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) { 2006 slgt_irq_off(info, IRQ_CTS); 2007 return; 2008 } 2009 info->icount.cts++; 2010 wake_up_interruptible(&info->status_event_wait_q); 2011 wake_up_interruptible(&info->event_wait_q); 2012 info->pending_bh |= BH_STATUS; 2013 2014 if (tty_port_cts_enabled(&info->port)) { 2015 if (info->port.tty) { 2016 if (info->port.tty->hw_stopped) { 2017 if (info->signals & SerialSignal_CTS) { 2018 info->port.tty->hw_stopped = 0; 2019 info->pending_bh |= BH_TRANSMIT; 2020 return; 2021 } 2022 } else { 2023 if (!(info->signals & SerialSignal_CTS)) 2024 info->port.tty->hw_stopped = 1; 2025 } 2026 } 2027 } 2028 } 2029 2030 static void dcd_change(struct slgt_info *info, unsigned short status) 2031 { 2032 if (status & BIT1) { 2033 info->signals |= SerialSignal_DCD; 2034 info->input_signal_events.dcd_up++; 2035 } else { 2036 info->signals &= ~SerialSignal_DCD; 2037 info->input_signal_events.dcd_down++; 2038 } 2039 DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals)); 2040 if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) { 2041 slgt_irq_off(info, IRQ_DCD); 2042 return; 2043 } 2044 info->icount.dcd++; 2045 #if SYNCLINK_GENERIC_HDLC 2046 if (info->netcount) { 2047 if (info->signals & SerialSignal_DCD) 2048 netif_carrier_on(info->netdev); 2049 else 2050 netif_carrier_off(info->netdev); 2051 } 2052 #endif 2053 wake_up_interruptible(&info->status_event_wait_q); 2054 wake_up_interruptible(&info->event_wait_q); 2055 info->pending_bh |= BH_STATUS; 2056 2057 if (tty_port_check_carrier(&info->port)) { 2058 if (info->signals & SerialSignal_DCD) 2059 wake_up_interruptible(&info->port.open_wait); 2060 else { 2061 if (info->port.tty) 2062 tty_hangup(info->port.tty); 2063 } 2064 } 2065 } 2066 2067 static void ri_change(struct slgt_info *info, unsigned short status) 2068 { 2069 if (status & BIT0) { 2070 info->signals |= SerialSignal_RI; 2071 info->input_signal_events.ri_up++; 2072 } else { 2073 info->signals &= ~SerialSignal_RI; 2074 info->input_signal_events.ri_down++; 2075 } 2076 DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals)); 2077 if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) { 2078 slgt_irq_off(info, IRQ_RI); 2079 return; 2080 } 2081 info->icount.rng++; 2082 wake_up_interruptible(&info->status_event_wait_q); 2083 wake_up_interruptible(&info->event_wait_q); 2084 info->pending_bh |= BH_STATUS; 2085 } 2086 2087 static void isr_rxdata(struct slgt_info *info) 2088 { 2089 unsigned int count = info->rbuf_fill_count; 2090 unsigned int i = info->rbuf_fill_index; 2091 unsigned short reg; 2092 2093 while (rd_reg16(info, SSR) & IRQ_RXDATA) { 2094 reg = rd_reg16(info, RDR); 2095 DBGISR(("isr_rxdata %s RDR=%04X\n", info->device_name, reg)); 2096 if (desc_complete(info->rbufs[i])) { 2097 /* all buffers full */ 2098 rx_stop(info); 2099 info->rx_restart = true; 2100 continue; 2101 } 2102 info->rbufs[i].buf[count++] = (unsigned char)reg; 2103 /* async mode saves status byte to buffer for each data byte */ 2104 if (info->params.mode == MGSL_MODE_ASYNC) 2105 info->rbufs[i].buf[count++] = (unsigned char)(reg >> 8); 2106 if (count == info->rbuf_fill_level || (reg & BIT10)) { 2107 /* buffer full or end of frame */ 2108 set_desc_count(info->rbufs[i], count); 2109 set_desc_status(info->rbufs[i], BIT15 | (reg >> 8)); 2110 info->rbuf_fill_count = count = 0; 2111 if (++i == info->rbuf_count) 2112 i = 0; 2113 info->pending_bh |= BH_RECEIVE; 2114 } 2115 } 2116 2117 info->rbuf_fill_index = i; 2118 info->rbuf_fill_count = count; 2119 } 2120 2121 static void isr_serial(struct slgt_info *info) 2122 { 2123 unsigned short status = rd_reg16(info, SSR); 2124 2125 DBGISR(("%s isr_serial status=%04X\n", info->device_name, status)); 2126 2127 wr_reg16(info, SSR, status); /* clear pending */ 2128 2129 info->irq_occurred = true; 2130 2131 if (info->params.mode == MGSL_MODE_ASYNC) { 2132 if (status & IRQ_TXIDLE) { 2133 if (info->tx_active) 2134 isr_txeom(info, status); 2135 } 2136 if (info->rx_pio && (status & IRQ_RXDATA)) 2137 isr_rxdata(info); 2138 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) { 2139 info->icount.brk++; 2140 /* process break detection if tty control allows */ 2141 if (info->port.tty) { 2142 if (!(status & info->ignore_status_mask)) { 2143 if (info->read_status_mask & MASK_BREAK) { 2144 tty_insert_flip_char(&info->port, 0, TTY_BREAK); 2145 if (info->port.flags & ASYNC_SAK) 2146 do_SAK(info->port.tty); 2147 } 2148 } 2149 } 2150 } 2151 } else { 2152 if (status & (IRQ_TXIDLE + IRQ_TXUNDER)) 2153 isr_txeom(info, status); 2154 if (info->rx_pio && (status & IRQ_RXDATA)) 2155 isr_rxdata(info); 2156 if (status & IRQ_RXIDLE) { 2157 if (status & RXIDLE) 2158 info->icount.rxidle++; 2159 else 2160 info->icount.exithunt++; 2161 wake_up_interruptible(&info->event_wait_q); 2162 } 2163 2164 if (status & IRQ_RXOVER) 2165 rx_start(info); 2166 } 2167 2168 if (status & IRQ_DSR) 2169 dsr_change(info, status); 2170 if (status & IRQ_CTS) 2171 cts_change(info, status); 2172 if (status & IRQ_DCD) 2173 dcd_change(info, status); 2174 if (status & IRQ_RI) 2175 ri_change(info, status); 2176 } 2177 2178 static void isr_rdma(struct slgt_info *info) 2179 { 2180 unsigned int status = rd_reg32(info, RDCSR); 2181 2182 DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status)); 2183 2184 /* RDCSR (rx DMA control/status) 2185 * 2186 * 31..07 reserved 2187 * 06 save status byte to DMA buffer 2188 * 05 error 2189 * 04 eol (end of list) 2190 * 03 eob (end of buffer) 2191 * 02 IRQ enable 2192 * 01 reset 2193 * 00 enable 2194 */ 2195 wr_reg32(info, RDCSR, status); /* clear pending */ 2196 2197 if (status & (BIT5 + BIT4)) { 2198 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name)); 2199 info->rx_restart = true; 2200 } 2201 info->pending_bh |= BH_RECEIVE; 2202 } 2203 2204 static void isr_tdma(struct slgt_info *info) 2205 { 2206 unsigned int status = rd_reg32(info, TDCSR); 2207 2208 DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status)); 2209 2210 /* TDCSR (tx DMA control/status) 2211 * 2212 * 31..06 reserved 2213 * 05 error 2214 * 04 eol (end of list) 2215 * 03 eob (end of buffer) 2216 * 02 IRQ enable 2217 * 01 reset 2218 * 00 enable 2219 */ 2220 wr_reg32(info, TDCSR, status); /* clear pending */ 2221 2222 if (status & (BIT5 + BIT4 + BIT3)) { 2223 // another transmit buffer has completed 2224 // run bottom half to get more send data from user 2225 info->pending_bh |= BH_TRANSMIT; 2226 } 2227 } 2228 2229 /* 2230 * return true if there are unsent tx DMA buffers, otherwise false 2231 * 2232 * if there are unsent buffers then info->tbuf_start 2233 * is set to index of first unsent buffer 2234 */ 2235 static bool unsent_tbufs(struct slgt_info *info) 2236 { 2237 unsigned int i = info->tbuf_current; 2238 bool rc = false; 2239 2240 /* 2241 * search backwards from last loaded buffer (precedes tbuf_current) 2242 * for first unsent buffer (desc_count > 0) 2243 */ 2244 2245 do { 2246 if (i) 2247 i--; 2248 else 2249 i = info->tbuf_count - 1; 2250 if (!desc_count(info->tbufs[i])) 2251 break; 2252 info->tbuf_start = i; 2253 rc = true; 2254 } while (i != info->tbuf_current); 2255 2256 return rc; 2257 } 2258 2259 static void isr_txeom(struct slgt_info *info, unsigned short status) 2260 { 2261 DBGISR(("%s txeom status=%04x\n", info->device_name, status)); 2262 2263 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER); 2264 tdma_reset(info); 2265 if (status & IRQ_TXUNDER) { 2266 unsigned short val = rd_reg16(info, TCR); 2267 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */ 2268 wr_reg16(info, TCR, val); /* clear reset bit */ 2269 } 2270 2271 if (info->tx_active) { 2272 if (info->params.mode != MGSL_MODE_ASYNC) { 2273 if (status & IRQ_TXUNDER) 2274 info->icount.txunder++; 2275 else if (status & IRQ_TXIDLE) 2276 info->icount.txok++; 2277 } 2278 2279 if (unsent_tbufs(info)) { 2280 tx_start(info); 2281 update_tx_timer(info); 2282 return; 2283 } 2284 info->tx_active = false; 2285 2286 del_timer(&info->tx_timer); 2287 2288 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) { 2289 info->signals &= ~SerialSignal_RTS; 2290 info->drop_rts_on_tx_done = false; 2291 set_signals(info); 2292 } 2293 2294 #if SYNCLINK_GENERIC_HDLC 2295 if (info->netcount) 2296 hdlcdev_tx_done(info); 2297 else 2298 #endif 2299 { 2300 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) { 2301 tx_stop(info); 2302 return; 2303 } 2304 info->pending_bh |= BH_TRANSMIT; 2305 } 2306 } 2307 } 2308 2309 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state) 2310 { 2311 struct cond_wait *w, *prev; 2312 2313 /* wake processes waiting for specific transitions */ 2314 for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) { 2315 if (w->data & changed) { 2316 w->data = state; 2317 wake_up_interruptible(&w->q); 2318 if (prev != NULL) 2319 prev->next = w->next; 2320 else 2321 info->gpio_wait_q = w->next; 2322 } else 2323 prev = w; 2324 } 2325 } 2326 2327 /* interrupt service routine 2328 * 2329 * irq interrupt number 2330 * dev_id device ID supplied during interrupt registration 2331 */ 2332 static irqreturn_t slgt_interrupt(int dummy, void *dev_id) 2333 { 2334 struct slgt_info *info = dev_id; 2335 unsigned int gsr; 2336 unsigned int i; 2337 2338 DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level)); 2339 2340 while((gsr = rd_reg32(info, GSR) & 0xffffff00)) { 2341 DBGISR(("%s gsr=%08x\n", info->device_name, gsr)); 2342 info->irq_occurred = true; 2343 for(i=0; i < info->port_count ; i++) { 2344 if (info->port_array[i] == NULL) 2345 continue; 2346 spin_lock(&info->port_array[i]->lock); 2347 if (gsr & (BIT8 << i)) 2348 isr_serial(info->port_array[i]); 2349 if (gsr & (BIT16 << (i*2))) 2350 isr_rdma(info->port_array[i]); 2351 if (gsr & (BIT17 << (i*2))) 2352 isr_tdma(info->port_array[i]); 2353 spin_unlock(&info->port_array[i]->lock); 2354 } 2355 } 2356 2357 if (info->gpio_present) { 2358 unsigned int state; 2359 unsigned int changed; 2360 spin_lock(&info->lock); 2361 while ((changed = rd_reg32(info, IOSR)) != 0) { 2362 DBGISR(("%s iosr=%08x\n", info->device_name, changed)); 2363 /* read latched state of GPIO signals */ 2364 state = rd_reg32(info, IOVR); 2365 /* clear pending GPIO interrupt bits */ 2366 wr_reg32(info, IOSR, changed); 2367 for (i=0 ; i < info->port_count ; i++) { 2368 if (info->port_array[i] != NULL) 2369 isr_gpio(info->port_array[i], changed, state); 2370 } 2371 } 2372 spin_unlock(&info->lock); 2373 } 2374 2375 for(i=0; i < info->port_count ; i++) { 2376 struct slgt_info *port = info->port_array[i]; 2377 if (port == NULL) 2378 continue; 2379 spin_lock(&port->lock); 2380 if ((port->port.count || port->netcount) && 2381 port->pending_bh && !port->bh_running && 2382 !port->bh_requested) { 2383 DBGISR(("%s bh queued\n", port->device_name)); 2384 schedule_work(&port->task); 2385 port->bh_requested = true; 2386 } 2387 spin_unlock(&port->lock); 2388 } 2389 2390 DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level)); 2391 return IRQ_HANDLED; 2392 } 2393 2394 static int startup(struct slgt_info *info) 2395 { 2396 DBGINFO(("%s startup\n", info->device_name)); 2397 2398 if (tty_port_initialized(&info->port)) 2399 return 0; 2400 2401 if (!info->tx_buf) { 2402 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL); 2403 if (!info->tx_buf) { 2404 DBGERR(("%s can't allocate tx buffer\n", info->device_name)); 2405 return -ENOMEM; 2406 } 2407 } 2408 2409 info->pending_bh = 0; 2410 2411 memset(&info->icount, 0, sizeof(info->icount)); 2412 2413 /* program hardware for current parameters */ 2414 change_params(info); 2415 2416 if (info->port.tty) 2417 clear_bit(TTY_IO_ERROR, &info->port.tty->flags); 2418 2419 tty_port_set_initialized(&info->port, 1); 2420 2421 return 0; 2422 } 2423 2424 /* 2425 * called by close() and hangup() to shutdown hardware 2426 */ 2427 static void shutdown(struct slgt_info *info) 2428 { 2429 unsigned long flags; 2430 2431 if (!tty_port_initialized(&info->port)) 2432 return; 2433 2434 DBGINFO(("%s shutdown\n", info->device_name)); 2435 2436 /* clear status wait queue because status changes */ 2437 /* can't happen after shutting down the hardware */ 2438 wake_up_interruptible(&info->status_event_wait_q); 2439 wake_up_interruptible(&info->event_wait_q); 2440 2441 del_timer_sync(&info->tx_timer); 2442 del_timer_sync(&info->rx_timer); 2443 2444 kfree(info->tx_buf); 2445 info->tx_buf = NULL; 2446 2447 spin_lock_irqsave(&info->lock,flags); 2448 2449 tx_stop(info); 2450 rx_stop(info); 2451 2452 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER); 2453 2454 if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) { 2455 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR); 2456 set_signals(info); 2457 } 2458 2459 flush_cond_wait(&info->gpio_wait_q); 2460 2461 spin_unlock_irqrestore(&info->lock,flags); 2462 2463 if (info->port.tty) 2464 set_bit(TTY_IO_ERROR, &info->port.tty->flags); 2465 2466 tty_port_set_initialized(&info->port, 0); 2467 } 2468 2469 static void program_hw(struct slgt_info *info) 2470 { 2471 unsigned long flags; 2472 2473 spin_lock_irqsave(&info->lock,flags); 2474 2475 rx_stop(info); 2476 tx_stop(info); 2477 2478 if (info->params.mode != MGSL_MODE_ASYNC || 2479 info->netcount) 2480 sync_mode(info); 2481 else 2482 async_mode(info); 2483 2484 set_signals(info); 2485 2486 info->dcd_chkcount = 0; 2487 info->cts_chkcount = 0; 2488 info->ri_chkcount = 0; 2489 info->dsr_chkcount = 0; 2490 2491 slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI); 2492 get_signals(info); 2493 2494 if (info->netcount || 2495 (info->port.tty && info->port.tty->termios.c_cflag & CREAD)) 2496 rx_start(info); 2497 2498 spin_unlock_irqrestore(&info->lock,flags); 2499 } 2500 2501 /* 2502 * reconfigure adapter based on new parameters 2503 */ 2504 static void change_params(struct slgt_info *info) 2505 { 2506 unsigned cflag; 2507 int bits_per_char; 2508 2509 if (!info->port.tty) 2510 return; 2511 DBGINFO(("%s change_params\n", info->device_name)); 2512 2513 cflag = info->port.tty->termios.c_cflag; 2514 2515 /* if B0 rate (hangup) specified then negate RTS and DTR */ 2516 /* otherwise assert RTS and DTR */ 2517 if (cflag & CBAUD) 2518 info->signals |= SerialSignal_RTS | SerialSignal_DTR; 2519 else 2520 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR); 2521 2522 /* byte size and parity */ 2523 2524 switch (cflag & CSIZE) { 2525 case CS5: info->params.data_bits = 5; break; 2526 case CS6: info->params.data_bits = 6; break; 2527 case CS7: info->params.data_bits = 7; break; 2528 case CS8: info->params.data_bits = 8; break; 2529 default: info->params.data_bits = 7; break; 2530 } 2531 2532 info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1; 2533 2534 if (cflag & PARENB) 2535 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN; 2536 else 2537 info->params.parity = ASYNC_PARITY_NONE; 2538 2539 /* calculate number of jiffies to transmit a full 2540 * FIFO (32 bytes) at specified data rate 2541 */ 2542 bits_per_char = info->params.data_bits + 2543 info->params.stop_bits + 1; 2544 2545 info->params.data_rate = tty_get_baud_rate(info->port.tty); 2546 2547 if (info->params.data_rate) { 2548 info->timeout = (32*HZ*bits_per_char) / 2549 info->params.data_rate; 2550 } 2551 info->timeout += HZ/50; /* Add .02 seconds of slop */ 2552 2553 tty_port_set_cts_flow(&info->port, cflag & CRTSCTS); 2554 tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL); 2555 2556 /* process tty input control flags */ 2557 2558 info->read_status_mask = IRQ_RXOVER; 2559 if (I_INPCK(info->port.tty)) 2560 info->read_status_mask |= MASK_PARITY | MASK_FRAMING; 2561 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty)) 2562 info->read_status_mask |= MASK_BREAK; 2563 if (I_IGNPAR(info->port.tty)) 2564 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING; 2565 if (I_IGNBRK(info->port.tty)) { 2566 info->ignore_status_mask |= MASK_BREAK; 2567 /* If ignoring parity and break indicators, ignore 2568 * overruns too. (For real raw support). 2569 */ 2570 if (I_IGNPAR(info->port.tty)) 2571 info->ignore_status_mask |= MASK_OVERRUN; 2572 } 2573 2574 program_hw(info); 2575 } 2576 2577 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount) 2578 { 2579 DBGINFO(("%s get_stats\n", info->device_name)); 2580 if (!user_icount) { 2581 memset(&info->icount, 0, sizeof(info->icount)); 2582 } else { 2583 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount))) 2584 return -EFAULT; 2585 } 2586 return 0; 2587 } 2588 2589 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params) 2590 { 2591 DBGINFO(("%s get_params\n", info->device_name)); 2592 if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS))) 2593 return -EFAULT; 2594 return 0; 2595 } 2596 2597 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params) 2598 { 2599 unsigned long flags; 2600 MGSL_PARAMS tmp_params; 2601 2602 DBGINFO(("%s set_params\n", info->device_name)); 2603 if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS))) 2604 return -EFAULT; 2605 2606 spin_lock_irqsave(&info->lock, flags); 2607 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) 2608 info->base_clock = tmp_params.clock_speed; 2609 else 2610 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS)); 2611 spin_unlock_irqrestore(&info->lock, flags); 2612 2613 program_hw(info); 2614 2615 return 0; 2616 } 2617 2618 static int get_txidle(struct slgt_info *info, int __user *idle_mode) 2619 { 2620 DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode)); 2621 if (put_user(info->idle_mode, idle_mode)) 2622 return -EFAULT; 2623 return 0; 2624 } 2625 2626 static int set_txidle(struct slgt_info *info, int idle_mode) 2627 { 2628 unsigned long flags; 2629 DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode)); 2630 spin_lock_irqsave(&info->lock,flags); 2631 info->idle_mode = idle_mode; 2632 if (info->params.mode != MGSL_MODE_ASYNC) 2633 tx_set_idle(info); 2634 spin_unlock_irqrestore(&info->lock,flags); 2635 return 0; 2636 } 2637 2638 static int tx_enable(struct slgt_info *info, int enable) 2639 { 2640 unsigned long flags; 2641 DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable)); 2642 spin_lock_irqsave(&info->lock,flags); 2643 if (enable) { 2644 if (!info->tx_enabled) 2645 tx_start(info); 2646 } else { 2647 if (info->tx_enabled) 2648 tx_stop(info); 2649 } 2650 spin_unlock_irqrestore(&info->lock,flags); 2651 return 0; 2652 } 2653 2654 /* 2655 * abort transmit HDLC frame 2656 */ 2657 static int tx_abort(struct slgt_info *info) 2658 { 2659 unsigned long flags; 2660 DBGINFO(("%s tx_abort\n", info->device_name)); 2661 spin_lock_irqsave(&info->lock,flags); 2662 tdma_reset(info); 2663 spin_unlock_irqrestore(&info->lock,flags); 2664 return 0; 2665 } 2666 2667 static int rx_enable(struct slgt_info *info, int enable) 2668 { 2669 unsigned long flags; 2670 unsigned int rbuf_fill_level; 2671 DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable)); 2672 spin_lock_irqsave(&info->lock,flags); 2673 /* 2674 * enable[31..16] = receive DMA buffer fill level 2675 * 0 = noop (leave fill level unchanged) 2676 * fill level must be multiple of 4 and <= buffer size 2677 */ 2678 rbuf_fill_level = ((unsigned int)enable) >> 16; 2679 if (rbuf_fill_level) { 2680 if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) { 2681 spin_unlock_irqrestore(&info->lock, flags); 2682 return -EINVAL; 2683 } 2684 info->rbuf_fill_level = rbuf_fill_level; 2685 if (rbuf_fill_level < 128) 2686 info->rx_pio = 1; /* PIO mode */ 2687 else 2688 info->rx_pio = 0; /* DMA mode */ 2689 rx_stop(info); /* restart receiver to use new fill level */ 2690 } 2691 2692 /* 2693 * enable[1..0] = receiver enable command 2694 * 0 = disable 2695 * 1 = enable 2696 * 2 = enable or force hunt mode if already enabled 2697 */ 2698 enable &= 3; 2699 if (enable) { 2700 if (!info->rx_enabled) 2701 rx_start(info); 2702 else if (enable == 2) { 2703 /* force hunt mode (write 1 to RCR[3]) */ 2704 wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3); 2705 } 2706 } else { 2707 if (info->rx_enabled) 2708 rx_stop(info); 2709 } 2710 spin_unlock_irqrestore(&info->lock,flags); 2711 return 0; 2712 } 2713 2714 /* 2715 * wait for specified event to occur 2716 */ 2717 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr) 2718 { 2719 unsigned long flags; 2720 int s; 2721 int rc=0; 2722 struct mgsl_icount cprev, cnow; 2723 int events; 2724 int mask; 2725 struct _input_signal_events oldsigs, newsigs; 2726 DECLARE_WAITQUEUE(wait, current); 2727 2728 if (get_user(mask, mask_ptr)) 2729 return -EFAULT; 2730 2731 DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask)); 2732 2733 spin_lock_irqsave(&info->lock,flags); 2734 2735 /* return immediately if state matches requested events */ 2736 get_signals(info); 2737 s = info->signals; 2738 2739 events = mask & 2740 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) + 2741 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) + 2742 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) + 2743 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) ); 2744 if (events) { 2745 spin_unlock_irqrestore(&info->lock,flags); 2746 goto exit; 2747 } 2748 2749 /* save current irq counts */ 2750 cprev = info->icount; 2751 oldsigs = info->input_signal_events; 2752 2753 /* enable hunt and idle irqs if needed */ 2754 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) { 2755 unsigned short val = rd_reg16(info, SCR); 2756 if (!(val & IRQ_RXIDLE)) 2757 wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE)); 2758 } 2759 2760 set_current_state(TASK_INTERRUPTIBLE); 2761 add_wait_queue(&info->event_wait_q, &wait); 2762 2763 spin_unlock_irqrestore(&info->lock,flags); 2764 2765 for(;;) { 2766 schedule(); 2767 if (signal_pending(current)) { 2768 rc = -ERESTARTSYS; 2769 break; 2770 } 2771 2772 /* get current irq counts */ 2773 spin_lock_irqsave(&info->lock,flags); 2774 cnow = info->icount; 2775 newsigs = info->input_signal_events; 2776 set_current_state(TASK_INTERRUPTIBLE); 2777 spin_unlock_irqrestore(&info->lock,flags); 2778 2779 /* if no change, wait aborted for some reason */ 2780 if (newsigs.dsr_up == oldsigs.dsr_up && 2781 newsigs.dsr_down == oldsigs.dsr_down && 2782 newsigs.dcd_up == oldsigs.dcd_up && 2783 newsigs.dcd_down == oldsigs.dcd_down && 2784 newsigs.cts_up == oldsigs.cts_up && 2785 newsigs.cts_down == oldsigs.cts_down && 2786 newsigs.ri_up == oldsigs.ri_up && 2787 newsigs.ri_down == oldsigs.ri_down && 2788 cnow.exithunt == cprev.exithunt && 2789 cnow.rxidle == cprev.rxidle) { 2790 rc = -EIO; 2791 break; 2792 } 2793 2794 events = mask & 2795 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) + 2796 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) + 2797 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) + 2798 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) + 2799 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) + 2800 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) + 2801 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) + 2802 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) + 2803 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) + 2804 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) ); 2805 if (events) 2806 break; 2807 2808 cprev = cnow; 2809 oldsigs = newsigs; 2810 } 2811 2812 remove_wait_queue(&info->event_wait_q, &wait); 2813 set_current_state(TASK_RUNNING); 2814 2815 2816 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) { 2817 spin_lock_irqsave(&info->lock,flags); 2818 if (!waitqueue_active(&info->event_wait_q)) { 2819 /* disable enable exit hunt mode/idle rcvd IRQs */ 2820 wr_reg16(info, SCR, 2821 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE)); 2822 } 2823 spin_unlock_irqrestore(&info->lock,flags); 2824 } 2825 exit: 2826 if (rc == 0) 2827 rc = put_user(events, mask_ptr); 2828 return rc; 2829 } 2830 2831 static int get_interface(struct slgt_info *info, int __user *if_mode) 2832 { 2833 DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode)); 2834 if (put_user(info->if_mode, if_mode)) 2835 return -EFAULT; 2836 return 0; 2837 } 2838 2839 static int set_interface(struct slgt_info *info, int if_mode) 2840 { 2841 unsigned long flags; 2842 unsigned short val; 2843 2844 DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode)); 2845 spin_lock_irqsave(&info->lock,flags); 2846 info->if_mode = if_mode; 2847 2848 msc_set_vcr(info); 2849 2850 /* TCR (tx control) 07 1=RTS driver control */ 2851 val = rd_reg16(info, TCR); 2852 if (info->if_mode & MGSL_INTERFACE_RTS_EN) 2853 val |= BIT7; 2854 else 2855 val &= ~BIT7; 2856 wr_reg16(info, TCR, val); 2857 2858 spin_unlock_irqrestore(&info->lock,flags); 2859 return 0; 2860 } 2861 2862 static int get_xsync(struct slgt_info *info, int __user *xsync) 2863 { 2864 DBGINFO(("%s get_xsync=%x\n", info->device_name, info->xsync)); 2865 if (put_user(info->xsync, xsync)) 2866 return -EFAULT; 2867 return 0; 2868 } 2869 2870 /* 2871 * set extended sync pattern (1 to 4 bytes) for extended sync mode 2872 * 2873 * sync pattern is contained in least significant bytes of value 2874 * most significant byte of sync pattern is oldest (1st sent/detected) 2875 */ 2876 static int set_xsync(struct slgt_info *info, int xsync) 2877 { 2878 unsigned long flags; 2879 2880 DBGINFO(("%s set_xsync=%x)\n", info->device_name, xsync)); 2881 spin_lock_irqsave(&info->lock, flags); 2882 info->xsync = xsync; 2883 wr_reg32(info, XSR, xsync); 2884 spin_unlock_irqrestore(&info->lock, flags); 2885 return 0; 2886 } 2887 2888 static int get_xctrl(struct slgt_info *info, int __user *xctrl) 2889 { 2890 DBGINFO(("%s get_xctrl=%x\n", info->device_name, info->xctrl)); 2891 if (put_user(info->xctrl, xctrl)) 2892 return -EFAULT; 2893 return 0; 2894 } 2895 2896 /* 2897 * set extended control options 2898 * 2899 * xctrl[31:19] reserved, must be zero 2900 * xctrl[18:17] extended sync pattern length in bytes 2901 * 00 = 1 byte in xsr[7:0] 2902 * 01 = 2 bytes in xsr[15:0] 2903 * 10 = 3 bytes in xsr[23:0] 2904 * 11 = 4 bytes in xsr[31:0] 2905 * xctrl[16] 1 = enable terminal count, 0=disabled 2906 * xctrl[15:0] receive terminal count for fixed length packets 2907 * value is count minus one (0 = 1 byte packet) 2908 * when terminal count is reached, receiver 2909 * automatically returns to hunt mode and receive 2910 * FIFO contents are flushed to DMA buffers with 2911 * end of frame (EOF) status 2912 */ 2913 static int set_xctrl(struct slgt_info *info, int xctrl) 2914 { 2915 unsigned long flags; 2916 2917 DBGINFO(("%s set_xctrl=%x)\n", info->device_name, xctrl)); 2918 spin_lock_irqsave(&info->lock, flags); 2919 info->xctrl = xctrl; 2920 wr_reg32(info, XCR, xctrl); 2921 spin_unlock_irqrestore(&info->lock, flags); 2922 return 0; 2923 } 2924 2925 /* 2926 * set general purpose IO pin state and direction 2927 * 2928 * user_gpio fields: 2929 * state each bit indicates a pin state 2930 * smask set bit indicates pin state to set 2931 * dir each bit indicates a pin direction (0=input, 1=output) 2932 * dmask set bit indicates pin direction to set 2933 */ 2934 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio) 2935 { 2936 unsigned long flags; 2937 struct gpio_desc gpio; 2938 __u32 data; 2939 2940 if (!info->gpio_present) 2941 return -EINVAL; 2942 if (copy_from_user(&gpio, user_gpio, sizeof(gpio))) 2943 return -EFAULT; 2944 DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n", 2945 info->device_name, gpio.state, gpio.smask, 2946 gpio.dir, gpio.dmask)); 2947 2948 spin_lock_irqsave(&info->port_array[0]->lock, flags); 2949 if (gpio.dmask) { 2950 data = rd_reg32(info, IODR); 2951 data |= gpio.dmask & gpio.dir; 2952 data &= ~(gpio.dmask & ~gpio.dir); 2953 wr_reg32(info, IODR, data); 2954 } 2955 if (gpio.smask) { 2956 data = rd_reg32(info, IOVR); 2957 data |= gpio.smask & gpio.state; 2958 data &= ~(gpio.smask & ~gpio.state); 2959 wr_reg32(info, IOVR, data); 2960 } 2961 spin_unlock_irqrestore(&info->port_array[0]->lock, flags); 2962 2963 return 0; 2964 } 2965 2966 /* 2967 * get general purpose IO pin state and direction 2968 */ 2969 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio) 2970 { 2971 struct gpio_desc gpio; 2972 if (!info->gpio_present) 2973 return -EINVAL; 2974 gpio.state = rd_reg32(info, IOVR); 2975 gpio.smask = 0xffffffff; 2976 gpio.dir = rd_reg32(info, IODR); 2977 gpio.dmask = 0xffffffff; 2978 if (copy_to_user(user_gpio, &gpio, sizeof(gpio))) 2979 return -EFAULT; 2980 DBGINFO(("%s get_gpio state=%08x dir=%08x\n", 2981 info->device_name, gpio.state, gpio.dir)); 2982 return 0; 2983 } 2984 2985 /* 2986 * conditional wait facility 2987 */ 2988 static void init_cond_wait(struct cond_wait *w, unsigned int data) 2989 { 2990 init_waitqueue_head(&w->q); 2991 init_waitqueue_entry(&w->wait, current); 2992 w->data = data; 2993 } 2994 2995 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w) 2996 { 2997 set_current_state(TASK_INTERRUPTIBLE); 2998 add_wait_queue(&w->q, &w->wait); 2999 w->next = *head; 3000 *head = w; 3001 } 3002 3003 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw) 3004 { 3005 struct cond_wait *w, *prev; 3006 remove_wait_queue(&cw->q, &cw->wait); 3007 set_current_state(TASK_RUNNING); 3008 for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) { 3009 if (w == cw) { 3010 if (prev != NULL) 3011 prev->next = w->next; 3012 else 3013 *head = w->next; 3014 break; 3015 } 3016 } 3017 } 3018 3019 static void flush_cond_wait(struct cond_wait **head) 3020 { 3021 while (*head != NULL) { 3022 wake_up_interruptible(&(*head)->q); 3023 *head = (*head)->next; 3024 } 3025 } 3026 3027 /* 3028 * wait for general purpose I/O pin(s) to enter specified state 3029 * 3030 * user_gpio fields: 3031 * state - bit indicates target pin state 3032 * smask - set bit indicates watched pin 3033 * 3034 * The wait ends when at least one watched pin enters the specified 3035 * state. When 0 (no error) is returned, user_gpio->state is set to the 3036 * state of all GPIO pins when the wait ends. 3037 * 3038 * Note: Each pin may be a dedicated input, dedicated output, or 3039 * configurable input/output. The number and configuration of pins 3040 * varies with the specific adapter model. Only input pins (dedicated 3041 * or configured) can be monitored with this function. 3042 */ 3043 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio) 3044 { 3045 unsigned long flags; 3046 int rc = 0; 3047 struct gpio_desc gpio; 3048 struct cond_wait wait; 3049 u32 state; 3050 3051 if (!info->gpio_present) 3052 return -EINVAL; 3053 if (copy_from_user(&gpio, user_gpio, sizeof(gpio))) 3054 return -EFAULT; 3055 DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n", 3056 info->device_name, gpio.state, gpio.smask)); 3057 /* ignore output pins identified by set IODR bit */ 3058 if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0) 3059 return -EINVAL; 3060 init_cond_wait(&wait, gpio.smask); 3061 3062 spin_lock_irqsave(&info->port_array[0]->lock, flags); 3063 /* enable interrupts for watched pins */ 3064 wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask); 3065 /* get current pin states */ 3066 state = rd_reg32(info, IOVR); 3067 3068 if (gpio.smask & ~(state ^ gpio.state)) { 3069 /* already in target state */ 3070 gpio.state = state; 3071 } else { 3072 /* wait for target state */ 3073 add_cond_wait(&info->gpio_wait_q, &wait); 3074 spin_unlock_irqrestore(&info->port_array[0]->lock, flags); 3075 schedule(); 3076 if (signal_pending(current)) 3077 rc = -ERESTARTSYS; 3078 else 3079 gpio.state = wait.data; 3080 spin_lock_irqsave(&info->port_array[0]->lock, flags); 3081 remove_cond_wait(&info->gpio_wait_q, &wait); 3082 } 3083 3084 /* disable all GPIO interrupts if no waiting processes */ 3085 if (info->gpio_wait_q == NULL) 3086 wr_reg32(info, IOER, 0); 3087 spin_unlock_irqrestore(&info->port_array[0]->lock, flags); 3088 3089 if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio))) 3090 rc = -EFAULT; 3091 return rc; 3092 } 3093 3094 static int modem_input_wait(struct slgt_info *info,int arg) 3095 { 3096 unsigned long flags; 3097 int rc; 3098 struct mgsl_icount cprev, cnow; 3099 DECLARE_WAITQUEUE(wait, current); 3100 3101 /* save current irq counts */ 3102 spin_lock_irqsave(&info->lock,flags); 3103 cprev = info->icount; 3104 add_wait_queue(&info->status_event_wait_q, &wait); 3105 set_current_state(TASK_INTERRUPTIBLE); 3106 spin_unlock_irqrestore(&info->lock,flags); 3107 3108 for(;;) { 3109 schedule(); 3110 if (signal_pending(current)) { 3111 rc = -ERESTARTSYS; 3112 break; 3113 } 3114 3115 /* get new irq counts */ 3116 spin_lock_irqsave(&info->lock,flags); 3117 cnow = info->icount; 3118 set_current_state(TASK_INTERRUPTIBLE); 3119 spin_unlock_irqrestore(&info->lock,flags); 3120 3121 /* if no change, wait aborted for some reason */ 3122 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr && 3123 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) { 3124 rc = -EIO; 3125 break; 3126 } 3127 3128 /* check for change in caller specified modem input */ 3129 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) || 3130 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) || 3131 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) || 3132 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) { 3133 rc = 0; 3134 break; 3135 } 3136 3137 cprev = cnow; 3138 } 3139 remove_wait_queue(&info->status_event_wait_q, &wait); 3140 set_current_state(TASK_RUNNING); 3141 return rc; 3142 } 3143 3144 /* 3145 * return state of serial control and status signals 3146 */ 3147 static int tiocmget(struct tty_struct *tty) 3148 { 3149 struct slgt_info *info = tty->driver_data; 3150 unsigned int result; 3151 unsigned long flags; 3152 3153 spin_lock_irqsave(&info->lock,flags); 3154 get_signals(info); 3155 spin_unlock_irqrestore(&info->lock,flags); 3156 3157 result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) + 3158 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) + 3159 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) + 3160 ((info->signals & SerialSignal_RI) ? TIOCM_RNG:0) + 3161 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) + 3162 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0); 3163 3164 DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result)); 3165 return result; 3166 } 3167 3168 /* 3169 * set modem control signals (DTR/RTS) 3170 * 3171 * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit 3172 * TIOCMSET = set/clear signal values 3173 * value bit mask for command 3174 */ 3175 static int tiocmset(struct tty_struct *tty, 3176 unsigned int set, unsigned int clear) 3177 { 3178 struct slgt_info *info = tty->driver_data; 3179 unsigned long flags; 3180 3181 DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear)); 3182 3183 if (set & TIOCM_RTS) 3184 info->signals |= SerialSignal_RTS; 3185 if (set & TIOCM_DTR) 3186 info->signals |= SerialSignal_DTR; 3187 if (clear & TIOCM_RTS) 3188 info->signals &= ~SerialSignal_RTS; 3189 if (clear & TIOCM_DTR) 3190 info->signals &= ~SerialSignal_DTR; 3191 3192 spin_lock_irqsave(&info->lock,flags); 3193 set_signals(info); 3194 spin_unlock_irqrestore(&info->lock,flags); 3195 return 0; 3196 } 3197 3198 static int carrier_raised(struct tty_port *port) 3199 { 3200 unsigned long flags; 3201 struct slgt_info *info = container_of(port, struct slgt_info, port); 3202 3203 spin_lock_irqsave(&info->lock,flags); 3204 get_signals(info); 3205 spin_unlock_irqrestore(&info->lock,flags); 3206 return (info->signals & SerialSignal_DCD) ? 1 : 0; 3207 } 3208 3209 static void dtr_rts(struct tty_port *port, int on) 3210 { 3211 unsigned long flags; 3212 struct slgt_info *info = container_of(port, struct slgt_info, port); 3213 3214 spin_lock_irqsave(&info->lock,flags); 3215 if (on) 3216 info->signals |= SerialSignal_RTS | SerialSignal_DTR; 3217 else 3218 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR); 3219 set_signals(info); 3220 spin_unlock_irqrestore(&info->lock,flags); 3221 } 3222 3223 3224 /* 3225 * block current process until the device is ready to open 3226 */ 3227 static int block_til_ready(struct tty_struct *tty, struct file *filp, 3228 struct slgt_info *info) 3229 { 3230 DECLARE_WAITQUEUE(wait, current); 3231 int retval; 3232 bool do_clocal = false; 3233 unsigned long flags; 3234 int cd; 3235 struct tty_port *port = &info->port; 3236 3237 DBGINFO(("%s block_til_ready\n", tty->driver->name)); 3238 3239 if (filp->f_flags & O_NONBLOCK || tty_io_error(tty)) { 3240 /* nonblock mode is set or port is not enabled */ 3241 tty_port_set_active(port, 1); 3242 return 0; 3243 } 3244 3245 if (C_CLOCAL(tty)) 3246 do_clocal = true; 3247 3248 /* Wait for carrier detect and the line to become 3249 * free (i.e., not in use by the callout). While we are in 3250 * this loop, port->count is dropped by one, so that 3251 * close() knows when to free things. We restore it upon 3252 * exit, either normal or abnormal. 3253 */ 3254 3255 retval = 0; 3256 add_wait_queue(&port->open_wait, &wait); 3257 3258 spin_lock_irqsave(&info->lock, flags); 3259 port->count--; 3260 spin_unlock_irqrestore(&info->lock, flags); 3261 port->blocked_open++; 3262 3263 while (1) { 3264 if (C_BAUD(tty) && tty_port_initialized(port)) 3265 tty_port_raise_dtr_rts(port); 3266 3267 set_current_state(TASK_INTERRUPTIBLE); 3268 3269 if (tty_hung_up_p(filp) || !tty_port_initialized(port)) { 3270 retval = (port->flags & ASYNC_HUP_NOTIFY) ? 3271 -EAGAIN : -ERESTARTSYS; 3272 break; 3273 } 3274 3275 cd = tty_port_carrier_raised(port); 3276 if (do_clocal || cd) 3277 break; 3278 3279 if (signal_pending(current)) { 3280 retval = -ERESTARTSYS; 3281 break; 3282 } 3283 3284 DBGINFO(("%s block_til_ready wait\n", tty->driver->name)); 3285 tty_unlock(tty); 3286 schedule(); 3287 tty_lock(tty); 3288 } 3289 3290 set_current_state(TASK_RUNNING); 3291 remove_wait_queue(&port->open_wait, &wait); 3292 3293 if (!tty_hung_up_p(filp)) 3294 port->count++; 3295 port->blocked_open--; 3296 3297 if (!retval) 3298 tty_port_set_active(port, 1); 3299 3300 DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval)); 3301 return retval; 3302 } 3303 3304 /* 3305 * allocate buffers used for calling line discipline receive_buf 3306 * directly in synchronous mode 3307 * note: add 5 bytes to max frame size to allow appending 3308 * 32-bit CRC and status byte when configured to do so 3309 */ 3310 static int alloc_tmp_rbuf(struct slgt_info *info) 3311 { 3312 info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL); 3313 if (info->tmp_rbuf == NULL) 3314 return -ENOMEM; 3315 /* unused flag buffer to satisfy receive_buf calling interface */ 3316 info->flag_buf = kzalloc(info->max_frame_size + 5, GFP_KERNEL); 3317 if (!info->flag_buf) { 3318 kfree(info->tmp_rbuf); 3319 info->tmp_rbuf = NULL; 3320 return -ENOMEM; 3321 } 3322 return 0; 3323 } 3324 3325 static void free_tmp_rbuf(struct slgt_info *info) 3326 { 3327 kfree(info->tmp_rbuf); 3328 info->tmp_rbuf = NULL; 3329 kfree(info->flag_buf); 3330 info->flag_buf = NULL; 3331 } 3332 3333 /* 3334 * allocate DMA descriptor lists. 3335 */ 3336 static int alloc_desc(struct slgt_info *info) 3337 { 3338 unsigned int i; 3339 unsigned int pbufs; 3340 3341 /* allocate memory to hold descriptor lists */ 3342 info->bufs = dma_alloc_coherent(&info->pdev->dev, DESC_LIST_SIZE, 3343 &info->bufs_dma_addr, GFP_KERNEL); 3344 if (info->bufs == NULL) 3345 return -ENOMEM; 3346 3347 info->rbufs = (struct slgt_desc*)info->bufs; 3348 info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count; 3349 3350 pbufs = (unsigned int)info->bufs_dma_addr; 3351 3352 /* 3353 * Build circular lists of descriptors 3354 */ 3355 3356 for (i=0; i < info->rbuf_count; i++) { 3357 /* physical address of this descriptor */ 3358 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc)); 3359 3360 /* physical address of next descriptor */ 3361 if (i == info->rbuf_count - 1) 3362 info->rbufs[i].next = cpu_to_le32(pbufs); 3363 else 3364 info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc))); 3365 set_desc_count(info->rbufs[i], DMABUFSIZE); 3366 } 3367 3368 for (i=0; i < info->tbuf_count; i++) { 3369 /* physical address of this descriptor */ 3370 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc)); 3371 3372 /* physical address of next descriptor */ 3373 if (i == info->tbuf_count - 1) 3374 info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc)); 3375 else 3376 info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc))); 3377 } 3378 3379 return 0; 3380 } 3381 3382 static void free_desc(struct slgt_info *info) 3383 { 3384 if (info->bufs != NULL) { 3385 dma_free_coherent(&info->pdev->dev, DESC_LIST_SIZE, 3386 info->bufs, info->bufs_dma_addr); 3387 info->bufs = NULL; 3388 info->rbufs = NULL; 3389 info->tbufs = NULL; 3390 } 3391 } 3392 3393 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count) 3394 { 3395 int i; 3396 for (i=0; i < count; i++) { 3397 bufs[i].buf = dma_alloc_coherent(&info->pdev->dev, DMABUFSIZE, 3398 &bufs[i].buf_dma_addr, GFP_KERNEL); 3399 if (!bufs[i].buf) 3400 return -ENOMEM; 3401 bufs[i].pbuf = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr); 3402 } 3403 return 0; 3404 } 3405 3406 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count) 3407 { 3408 int i; 3409 for (i=0; i < count; i++) { 3410 if (bufs[i].buf == NULL) 3411 continue; 3412 dma_free_coherent(&info->pdev->dev, DMABUFSIZE, bufs[i].buf, 3413 bufs[i].buf_dma_addr); 3414 bufs[i].buf = NULL; 3415 } 3416 } 3417 3418 static int alloc_dma_bufs(struct slgt_info *info) 3419 { 3420 info->rbuf_count = 32; 3421 info->tbuf_count = 32; 3422 3423 if (alloc_desc(info) < 0 || 3424 alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 || 3425 alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 || 3426 alloc_tmp_rbuf(info) < 0) { 3427 DBGERR(("%s DMA buffer alloc fail\n", info->device_name)); 3428 return -ENOMEM; 3429 } 3430 reset_rbufs(info); 3431 return 0; 3432 } 3433 3434 static void free_dma_bufs(struct slgt_info *info) 3435 { 3436 if (info->bufs) { 3437 free_bufs(info, info->rbufs, info->rbuf_count); 3438 free_bufs(info, info->tbufs, info->tbuf_count); 3439 free_desc(info); 3440 } 3441 free_tmp_rbuf(info); 3442 } 3443 3444 static int claim_resources(struct slgt_info *info) 3445 { 3446 if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) { 3447 DBGERR(("%s reg addr conflict, addr=%08X\n", 3448 info->device_name, info->phys_reg_addr)); 3449 info->init_error = DiagStatus_AddressConflict; 3450 goto errout; 3451 } 3452 else 3453 info->reg_addr_requested = true; 3454 3455 info->reg_addr = ioremap(info->phys_reg_addr, SLGT_REG_SIZE); 3456 if (!info->reg_addr) { 3457 DBGERR(("%s can't map device registers, addr=%08X\n", 3458 info->device_name, info->phys_reg_addr)); 3459 info->init_error = DiagStatus_CantAssignPciResources; 3460 goto errout; 3461 } 3462 return 0; 3463 3464 errout: 3465 release_resources(info); 3466 return -ENODEV; 3467 } 3468 3469 static void release_resources(struct slgt_info *info) 3470 { 3471 if (info->irq_requested) { 3472 free_irq(info->irq_level, info); 3473 info->irq_requested = false; 3474 } 3475 3476 if (info->reg_addr_requested) { 3477 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE); 3478 info->reg_addr_requested = false; 3479 } 3480 3481 if (info->reg_addr) { 3482 iounmap(info->reg_addr); 3483 info->reg_addr = NULL; 3484 } 3485 } 3486 3487 /* Add the specified device instance data structure to the 3488 * global linked list of devices and increment the device count. 3489 */ 3490 static void add_device(struct slgt_info *info) 3491 { 3492 char *devstr; 3493 3494 info->next_device = NULL; 3495 info->line = slgt_device_count; 3496 sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line); 3497 3498 if (info->line < MAX_DEVICES) { 3499 if (maxframe[info->line]) 3500 info->max_frame_size = maxframe[info->line]; 3501 } 3502 3503 slgt_device_count++; 3504 3505 if (!slgt_device_list) 3506 slgt_device_list = info; 3507 else { 3508 struct slgt_info *current_dev = slgt_device_list; 3509 while(current_dev->next_device) 3510 current_dev = current_dev->next_device; 3511 current_dev->next_device = info; 3512 } 3513 3514 if (info->max_frame_size < 4096) 3515 info->max_frame_size = 4096; 3516 else if (info->max_frame_size > 65535) 3517 info->max_frame_size = 65535; 3518 3519 switch(info->pdev->device) { 3520 case SYNCLINK_GT_DEVICE_ID: 3521 devstr = "GT"; 3522 break; 3523 case SYNCLINK_GT2_DEVICE_ID: 3524 devstr = "GT2"; 3525 break; 3526 case SYNCLINK_GT4_DEVICE_ID: 3527 devstr = "GT4"; 3528 break; 3529 case SYNCLINK_AC_DEVICE_ID: 3530 devstr = "AC"; 3531 info->params.mode = MGSL_MODE_ASYNC; 3532 break; 3533 default: 3534 devstr = "(unknown model)"; 3535 } 3536 printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n", 3537 devstr, info->device_name, info->phys_reg_addr, 3538 info->irq_level, info->max_frame_size); 3539 3540 #if SYNCLINK_GENERIC_HDLC 3541 hdlcdev_init(info); 3542 #endif 3543 } 3544 3545 static const struct tty_port_operations slgt_port_ops = { 3546 .carrier_raised = carrier_raised, 3547 .dtr_rts = dtr_rts, 3548 }; 3549 3550 /* 3551 * allocate device instance structure, return NULL on failure 3552 */ 3553 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev) 3554 { 3555 struct slgt_info *info; 3556 3557 info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL); 3558 3559 if (!info) { 3560 DBGERR(("%s device alloc failed adapter=%d port=%d\n", 3561 driver_name, adapter_num, port_num)); 3562 } else { 3563 tty_port_init(&info->port); 3564 info->port.ops = &slgt_port_ops; 3565 info->magic = MGSL_MAGIC; 3566 INIT_WORK(&info->task, bh_handler); 3567 info->max_frame_size = 4096; 3568 info->base_clock = 14745600; 3569 info->rbuf_fill_level = DMABUFSIZE; 3570 info->port.close_delay = 5*HZ/10; 3571 info->port.closing_wait = 30*HZ; 3572 init_waitqueue_head(&info->status_event_wait_q); 3573 init_waitqueue_head(&info->event_wait_q); 3574 spin_lock_init(&info->netlock); 3575 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS)); 3576 info->idle_mode = HDLC_TXIDLE_FLAGS; 3577 info->adapter_num = adapter_num; 3578 info->port_num = port_num; 3579 3580 timer_setup(&info->tx_timer, tx_timeout, 0); 3581 timer_setup(&info->rx_timer, rx_timeout, 0); 3582 3583 /* Copy configuration info to device instance data */ 3584 info->pdev = pdev; 3585 info->irq_level = pdev->irq; 3586 info->phys_reg_addr = pci_resource_start(pdev,0); 3587 3588 info->bus_type = MGSL_BUS_TYPE_PCI; 3589 info->irq_flags = IRQF_SHARED; 3590 3591 info->init_error = -1; /* assume error, set to 0 on successful init */ 3592 } 3593 3594 return info; 3595 } 3596 3597 static void device_init(int adapter_num, struct pci_dev *pdev) 3598 { 3599 struct slgt_info *port_array[SLGT_MAX_PORTS]; 3600 int i; 3601 int port_count = 1; 3602 3603 if (pdev->device == SYNCLINK_GT2_DEVICE_ID) 3604 port_count = 2; 3605 else if (pdev->device == SYNCLINK_GT4_DEVICE_ID) 3606 port_count = 4; 3607 3608 /* allocate device instances for all ports */ 3609 for (i=0; i < port_count; ++i) { 3610 port_array[i] = alloc_dev(adapter_num, i, pdev); 3611 if (port_array[i] == NULL) { 3612 for (--i; i >= 0; --i) { 3613 tty_port_destroy(&port_array[i]->port); 3614 kfree(port_array[i]); 3615 } 3616 return; 3617 } 3618 } 3619 3620 /* give copy of port_array to all ports and add to device list */ 3621 for (i=0; i < port_count; ++i) { 3622 memcpy(port_array[i]->port_array, port_array, sizeof(port_array)); 3623 add_device(port_array[i]); 3624 port_array[i]->port_count = port_count; 3625 spin_lock_init(&port_array[i]->lock); 3626 } 3627 3628 /* Allocate and claim adapter resources */ 3629 if (!claim_resources(port_array[0])) { 3630 3631 alloc_dma_bufs(port_array[0]); 3632 3633 /* copy resource information from first port to others */ 3634 for (i = 1; i < port_count; ++i) { 3635 port_array[i]->irq_level = port_array[0]->irq_level; 3636 port_array[i]->reg_addr = port_array[0]->reg_addr; 3637 alloc_dma_bufs(port_array[i]); 3638 } 3639 3640 if (request_irq(port_array[0]->irq_level, 3641 slgt_interrupt, 3642 port_array[0]->irq_flags, 3643 port_array[0]->device_name, 3644 port_array[0]) < 0) { 3645 DBGERR(("%s request_irq failed IRQ=%d\n", 3646 port_array[0]->device_name, 3647 port_array[0]->irq_level)); 3648 } else { 3649 port_array[0]->irq_requested = true; 3650 adapter_test(port_array[0]); 3651 for (i=1 ; i < port_count ; i++) { 3652 port_array[i]->init_error = port_array[0]->init_error; 3653 port_array[i]->gpio_present = port_array[0]->gpio_present; 3654 } 3655 } 3656 } 3657 3658 for (i = 0; i < port_count; ++i) { 3659 struct slgt_info *info = port_array[i]; 3660 tty_port_register_device(&info->port, serial_driver, info->line, 3661 &info->pdev->dev); 3662 } 3663 } 3664 3665 static int init_one(struct pci_dev *dev, 3666 const struct pci_device_id *ent) 3667 { 3668 if (pci_enable_device(dev)) { 3669 printk("error enabling pci device %p\n", dev); 3670 return -EIO; 3671 } 3672 pci_set_master(dev); 3673 device_init(slgt_device_count, dev); 3674 return 0; 3675 } 3676 3677 static void remove_one(struct pci_dev *dev) 3678 { 3679 } 3680 3681 static const struct tty_operations ops = { 3682 .open = open, 3683 .close = close, 3684 .write = write, 3685 .put_char = put_char, 3686 .flush_chars = flush_chars, 3687 .write_room = write_room, 3688 .chars_in_buffer = chars_in_buffer, 3689 .flush_buffer = flush_buffer, 3690 .ioctl = ioctl, 3691 .compat_ioctl = slgt_compat_ioctl, 3692 .throttle = throttle, 3693 .unthrottle = unthrottle, 3694 .send_xchar = send_xchar, 3695 .break_ctl = set_break, 3696 .wait_until_sent = wait_until_sent, 3697 .set_termios = set_termios, 3698 .stop = tx_hold, 3699 .start = tx_release, 3700 .hangup = hangup, 3701 .tiocmget = tiocmget, 3702 .tiocmset = tiocmset, 3703 .get_icount = get_icount, 3704 .proc_show = synclink_gt_proc_show, 3705 }; 3706 3707 static void slgt_cleanup(void) 3708 { 3709 int rc; 3710 struct slgt_info *info; 3711 struct slgt_info *tmp; 3712 3713 printk(KERN_INFO "unload %s\n", driver_name); 3714 3715 if (serial_driver) { 3716 for (info=slgt_device_list ; info != NULL ; info=info->next_device) 3717 tty_unregister_device(serial_driver, info->line); 3718 rc = tty_unregister_driver(serial_driver); 3719 if (rc) 3720 DBGERR(("tty_unregister_driver error=%d\n", rc)); 3721 put_tty_driver(serial_driver); 3722 } 3723 3724 /* reset devices */ 3725 info = slgt_device_list; 3726 while(info) { 3727 reset_port(info); 3728 info = info->next_device; 3729 } 3730 3731 /* release devices */ 3732 info = slgt_device_list; 3733 while(info) { 3734 #if SYNCLINK_GENERIC_HDLC 3735 hdlcdev_exit(info); 3736 #endif 3737 free_dma_bufs(info); 3738 free_tmp_rbuf(info); 3739 if (info->port_num == 0) 3740 release_resources(info); 3741 tmp = info; 3742 info = info->next_device; 3743 tty_port_destroy(&tmp->port); 3744 kfree(tmp); 3745 } 3746 3747 if (pci_registered) 3748 pci_unregister_driver(&pci_driver); 3749 } 3750 3751 /* 3752 * Driver initialization entry point. 3753 */ 3754 static int __init slgt_init(void) 3755 { 3756 int rc; 3757 3758 printk(KERN_INFO "%s\n", driver_name); 3759 3760 serial_driver = alloc_tty_driver(MAX_DEVICES); 3761 if (!serial_driver) { 3762 printk("%s can't allocate tty driver\n", driver_name); 3763 return -ENOMEM; 3764 } 3765 3766 /* Initialize the tty_driver structure */ 3767 3768 serial_driver->driver_name = slgt_driver_name; 3769 serial_driver->name = tty_dev_prefix; 3770 serial_driver->major = ttymajor; 3771 serial_driver->minor_start = 64; 3772 serial_driver->type = TTY_DRIVER_TYPE_SERIAL; 3773 serial_driver->subtype = SERIAL_TYPE_NORMAL; 3774 serial_driver->init_termios = tty_std_termios; 3775 serial_driver->init_termios.c_cflag = 3776 B9600 | CS8 | CREAD | HUPCL | CLOCAL; 3777 serial_driver->init_termios.c_ispeed = 9600; 3778 serial_driver->init_termios.c_ospeed = 9600; 3779 serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV; 3780 tty_set_operations(serial_driver, &ops); 3781 if ((rc = tty_register_driver(serial_driver)) < 0) { 3782 DBGERR(("%s can't register serial driver\n", driver_name)); 3783 put_tty_driver(serial_driver); 3784 serial_driver = NULL; 3785 goto error; 3786 } 3787 3788 printk(KERN_INFO "%s, tty major#%d\n", 3789 driver_name, serial_driver->major); 3790 3791 slgt_device_count = 0; 3792 if ((rc = pci_register_driver(&pci_driver)) < 0) { 3793 printk("%s pci_register_driver error=%d\n", driver_name, rc); 3794 goto error; 3795 } 3796 pci_registered = true; 3797 3798 if (!slgt_device_list) 3799 printk("%s no devices found\n",driver_name); 3800 3801 return 0; 3802 3803 error: 3804 slgt_cleanup(); 3805 return rc; 3806 } 3807 3808 static void __exit slgt_exit(void) 3809 { 3810 slgt_cleanup(); 3811 } 3812 3813 module_init(slgt_init); 3814 module_exit(slgt_exit); 3815 3816 /* 3817 * register access routines 3818 */ 3819 3820 #define CALC_REGADDR() \ 3821 unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \ 3822 if (addr >= 0x80) \ 3823 reg_addr += (info->port_num) * 32; \ 3824 else if (addr >= 0x40) \ 3825 reg_addr += (info->port_num) * 16; 3826 3827 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr) 3828 { 3829 CALC_REGADDR(); 3830 return readb((void __iomem *)reg_addr); 3831 } 3832 3833 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value) 3834 { 3835 CALC_REGADDR(); 3836 writeb(value, (void __iomem *)reg_addr); 3837 } 3838 3839 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr) 3840 { 3841 CALC_REGADDR(); 3842 return readw((void __iomem *)reg_addr); 3843 } 3844 3845 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value) 3846 { 3847 CALC_REGADDR(); 3848 writew(value, (void __iomem *)reg_addr); 3849 } 3850 3851 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr) 3852 { 3853 CALC_REGADDR(); 3854 return readl((void __iomem *)reg_addr); 3855 } 3856 3857 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value) 3858 { 3859 CALC_REGADDR(); 3860 writel(value, (void __iomem *)reg_addr); 3861 } 3862 3863 static void rdma_reset(struct slgt_info *info) 3864 { 3865 unsigned int i; 3866 3867 /* set reset bit */ 3868 wr_reg32(info, RDCSR, BIT1); 3869 3870 /* wait for enable bit cleared */ 3871 for(i=0 ; i < 1000 ; i++) 3872 if (!(rd_reg32(info, RDCSR) & BIT0)) 3873 break; 3874 } 3875 3876 static void tdma_reset(struct slgt_info *info) 3877 { 3878 unsigned int i; 3879 3880 /* set reset bit */ 3881 wr_reg32(info, TDCSR, BIT1); 3882 3883 /* wait for enable bit cleared */ 3884 for(i=0 ; i < 1000 ; i++) 3885 if (!(rd_reg32(info, TDCSR) & BIT0)) 3886 break; 3887 } 3888 3889 /* 3890 * enable internal loopback 3891 * TxCLK and RxCLK are generated from BRG 3892 * and TxD is looped back to RxD internally. 3893 */ 3894 static void enable_loopback(struct slgt_info *info) 3895 { 3896 /* SCR (serial control) BIT2=loopback enable */ 3897 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2)); 3898 3899 if (info->params.mode != MGSL_MODE_ASYNC) { 3900 /* CCR (clock control) 3901 * 07..05 tx clock source (010 = BRG) 3902 * 04..02 rx clock source (010 = BRG) 3903 * 01 auxclk enable (0 = disable) 3904 * 00 BRG enable (1 = enable) 3905 * 3906 * 0100 1001 3907 */ 3908 wr_reg8(info, CCR, 0x49); 3909 3910 /* set speed if available, otherwise use default */ 3911 if (info->params.clock_speed) 3912 set_rate(info, info->params.clock_speed); 3913 else 3914 set_rate(info, 3686400); 3915 } 3916 } 3917 3918 /* 3919 * set baud rate generator to specified rate 3920 */ 3921 static void set_rate(struct slgt_info *info, u32 rate) 3922 { 3923 unsigned int div; 3924 unsigned int osc = info->base_clock; 3925 3926 /* div = osc/rate - 1 3927 * 3928 * Round div up if osc/rate is not integer to 3929 * force to next slowest rate. 3930 */ 3931 3932 if (rate) { 3933 div = osc/rate; 3934 if (!(osc % rate) && div) 3935 div--; 3936 wr_reg16(info, BDR, (unsigned short)div); 3937 } 3938 } 3939 3940 static void rx_stop(struct slgt_info *info) 3941 { 3942 unsigned short val; 3943 3944 /* disable and reset receiver */ 3945 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */ 3946 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */ 3947 wr_reg16(info, RCR, val); /* clear reset bit */ 3948 3949 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE); 3950 3951 /* clear pending rx interrupts */ 3952 wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER); 3953 3954 rdma_reset(info); 3955 3956 info->rx_enabled = false; 3957 info->rx_restart = false; 3958 } 3959 3960 static void rx_start(struct slgt_info *info) 3961 { 3962 unsigned short val; 3963 3964 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA); 3965 3966 /* clear pending rx overrun IRQ */ 3967 wr_reg16(info, SSR, IRQ_RXOVER); 3968 3969 /* reset and disable receiver */ 3970 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */ 3971 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */ 3972 wr_reg16(info, RCR, val); /* clear reset bit */ 3973 3974 rdma_reset(info); 3975 reset_rbufs(info); 3976 3977 if (info->rx_pio) { 3978 /* rx request when rx FIFO not empty */ 3979 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14)); 3980 slgt_irq_on(info, IRQ_RXDATA); 3981 if (info->params.mode == MGSL_MODE_ASYNC) { 3982 /* enable saving of rx status */ 3983 wr_reg32(info, RDCSR, BIT6); 3984 } 3985 } else { 3986 /* rx request when rx FIFO half full */ 3987 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14)); 3988 /* set 1st descriptor address */ 3989 wr_reg32(info, RDDAR, info->rbufs[0].pdesc); 3990 3991 if (info->params.mode != MGSL_MODE_ASYNC) { 3992 /* enable rx DMA and DMA interrupt */ 3993 wr_reg32(info, RDCSR, (BIT2 + BIT0)); 3994 } else { 3995 /* enable saving of rx status, rx DMA and DMA interrupt */ 3996 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0)); 3997 } 3998 } 3999 4000 slgt_irq_on(info, IRQ_RXOVER); 4001 4002 /* enable receiver */ 4003 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1)); 4004 4005 info->rx_restart = false; 4006 info->rx_enabled = true; 4007 } 4008 4009 static void tx_start(struct slgt_info *info) 4010 { 4011 if (!info->tx_enabled) { 4012 wr_reg16(info, TCR, 4013 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2)); 4014 info->tx_enabled = true; 4015 } 4016 4017 if (desc_count(info->tbufs[info->tbuf_start])) { 4018 info->drop_rts_on_tx_done = false; 4019 4020 if (info->params.mode != MGSL_MODE_ASYNC) { 4021 if (info->params.flags & HDLC_FLAG_AUTO_RTS) { 4022 get_signals(info); 4023 if (!(info->signals & SerialSignal_RTS)) { 4024 info->signals |= SerialSignal_RTS; 4025 set_signals(info); 4026 info->drop_rts_on_tx_done = true; 4027 } 4028 } 4029 4030 slgt_irq_off(info, IRQ_TXDATA); 4031 slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE); 4032 /* clear tx idle and underrun status bits */ 4033 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER)); 4034 } else { 4035 slgt_irq_off(info, IRQ_TXDATA); 4036 slgt_irq_on(info, IRQ_TXIDLE); 4037 /* clear tx idle status bit */ 4038 wr_reg16(info, SSR, IRQ_TXIDLE); 4039 } 4040 /* set 1st descriptor address and start DMA */ 4041 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc); 4042 wr_reg32(info, TDCSR, BIT2 + BIT0); 4043 info->tx_active = true; 4044 } 4045 } 4046 4047 static void tx_stop(struct slgt_info *info) 4048 { 4049 unsigned short val; 4050 4051 del_timer(&info->tx_timer); 4052 4053 tdma_reset(info); 4054 4055 /* reset and disable transmitter */ 4056 val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */ 4057 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */ 4058 4059 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER); 4060 4061 /* clear tx idle and underrun status bit */ 4062 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER)); 4063 4064 reset_tbufs(info); 4065 4066 info->tx_enabled = false; 4067 info->tx_active = false; 4068 } 4069 4070 static void reset_port(struct slgt_info *info) 4071 { 4072 if (!info->reg_addr) 4073 return; 4074 4075 tx_stop(info); 4076 rx_stop(info); 4077 4078 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR); 4079 set_signals(info); 4080 4081 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER); 4082 } 4083 4084 static void reset_adapter(struct slgt_info *info) 4085 { 4086 int i; 4087 for (i=0; i < info->port_count; ++i) { 4088 if (info->port_array[i]) 4089 reset_port(info->port_array[i]); 4090 } 4091 } 4092 4093 static void async_mode(struct slgt_info *info) 4094 { 4095 unsigned short val; 4096 4097 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER); 4098 tx_stop(info); 4099 rx_stop(info); 4100 4101 /* TCR (tx control) 4102 * 4103 * 15..13 mode, 010=async 4104 * 12..10 encoding, 000=NRZ 4105 * 09 parity enable 4106 * 08 1=odd parity, 0=even parity 4107 * 07 1=RTS driver control 4108 * 06 1=break enable 4109 * 05..04 character length 4110 * 00=5 bits 4111 * 01=6 bits 4112 * 10=7 bits 4113 * 11=8 bits 4114 * 03 0=1 stop bit, 1=2 stop bits 4115 * 02 reset 4116 * 01 enable 4117 * 00 auto-CTS enable 4118 */ 4119 val = 0x4000; 4120 4121 if (info->if_mode & MGSL_INTERFACE_RTS_EN) 4122 val |= BIT7; 4123 4124 if (info->params.parity != ASYNC_PARITY_NONE) { 4125 val |= BIT9; 4126 if (info->params.parity == ASYNC_PARITY_ODD) 4127 val |= BIT8; 4128 } 4129 4130 switch (info->params.data_bits) 4131 { 4132 case 6: val |= BIT4; break; 4133 case 7: val |= BIT5; break; 4134 case 8: val |= BIT5 + BIT4; break; 4135 } 4136 4137 if (info->params.stop_bits != 1) 4138 val |= BIT3; 4139 4140 if (info->params.flags & HDLC_FLAG_AUTO_CTS) 4141 val |= BIT0; 4142 4143 wr_reg16(info, TCR, val); 4144 4145 /* RCR (rx control) 4146 * 4147 * 15..13 mode, 010=async 4148 * 12..10 encoding, 000=NRZ 4149 * 09 parity enable 4150 * 08 1=odd parity, 0=even parity 4151 * 07..06 reserved, must be 0 4152 * 05..04 character length 4153 * 00=5 bits 4154 * 01=6 bits 4155 * 10=7 bits 4156 * 11=8 bits 4157 * 03 reserved, must be zero 4158 * 02 reset 4159 * 01 enable 4160 * 00 auto-DCD enable 4161 */ 4162 val = 0x4000; 4163 4164 if (info->params.parity != ASYNC_PARITY_NONE) { 4165 val |= BIT9; 4166 if (info->params.parity == ASYNC_PARITY_ODD) 4167 val |= BIT8; 4168 } 4169 4170 switch (info->params.data_bits) 4171 { 4172 case 6: val |= BIT4; break; 4173 case 7: val |= BIT5; break; 4174 case 8: val |= BIT5 + BIT4; break; 4175 } 4176 4177 if (info->params.flags & HDLC_FLAG_AUTO_DCD) 4178 val |= BIT0; 4179 4180 wr_reg16(info, RCR, val); 4181 4182 /* CCR (clock control) 4183 * 4184 * 07..05 011 = tx clock source is BRG/16 4185 * 04..02 010 = rx clock source is BRG 4186 * 01 0 = auxclk disabled 4187 * 00 1 = BRG enabled 4188 * 4189 * 0110 1001 4190 */ 4191 wr_reg8(info, CCR, 0x69); 4192 4193 msc_set_vcr(info); 4194 4195 /* SCR (serial control) 4196 * 4197 * 15 1=tx req on FIFO half empty 4198 * 14 1=rx req on FIFO half full 4199 * 13 tx data IRQ enable 4200 * 12 tx idle IRQ enable 4201 * 11 rx break on IRQ enable 4202 * 10 rx data IRQ enable 4203 * 09 rx break off IRQ enable 4204 * 08 overrun IRQ enable 4205 * 07 DSR IRQ enable 4206 * 06 CTS IRQ enable 4207 * 05 DCD IRQ enable 4208 * 04 RI IRQ enable 4209 * 03 0=16x sampling, 1=8x sampling 4210 * 02 1=txd->rxd internal loopback enable 4211 * 01 reserved, must be zero 4212 * 00 1=master IRQ enable 4213 */ 4214 val = BIT15 + BIT14 + BIT0; 4215 /* JCR[8] : 1 = x8 async mode feature available */ 4216 if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate && 4217 ((info->base_clock < (info->params.data_rate * 16)) || 4218 (info->base_clock % (info->params.data_rate * 16)))) { 4219 /* use 8x sampling */ 4220 val |= BIT3; 4221 set_rate(info, info->params.data_rate * 8); 4222 } else { 4223 /* use 16x sampling */ 4224 set_rate(info, info->params.data_rate * 16); 4225 } 4226 wr_reg16(info, SCR, val); 4227 4228 slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER); 4229 4230 if (info->params.loopback) 4231 enable_loopback(info); 4232 } 4233 4234 static void sync_mode(struct slgt_info *info) 4235 { 4236 unsigned short val; 4237 4238 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER); 4239 tx_stop(info); 4240 rx_stop(info); 4241 4242 /* TCR (tx control) 4243 * 4244 * 15..13 mode 4245 * 000=HDLC/SDLC 4246 * 001=raw bit synchronous 4247 * 010=asynchronous/isochronous 4248 * 011=monosync byte synchronous 4249 * 100=bisync byte synchronous 4250 * 101=xsync byte synchronous 4251 * 12..10 encoding 4252 * 09 CRC enable 4253 * 08 CRC32 4254 * 07 1=RTS driver control 4255 * 06 preamble enable 4256 * 05..04 preamble length 4257 * 03 share open/close flag 4258 * 02 reset 4259 * 01 enable 4260 * 00 auto-CTS enable 4261 */ 4262 val = BIT2; 4263 4264 switch(info->params.mode) { 4265 case MGSL_MODE_XSYNC: 4266 val |= BIT15 + BIT13; 4267 break; 4268 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break; 4269 case MGSL_MODE_BISYNC: val |= BIT15; break; 4270 case MGSL_MODE_RAW: val |= BIT13; break; 4271 } 4272 if (info->if_mode & MGSL_INTERFACE_RTS_EN) 4273 val |= BIT7; 4274 4275 switch(info->params.encoding) 4276 { 4277 case HDLC_ENCODING_NRZB: val |= BIT10; break; 4278 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break; 4279 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break; 4280 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break; 4281 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break; 4282 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break; 4283 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; 4284 } 4285 4286 switch (info->params.crc_type & HDLC_CRC_MASK) 4287 { 4288 case HDLC_CRC_16_CCITT: val |= BIT9; break; 4289 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break; 4290 } 4291 4292 if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE) 4293 val |= BIT6; 4294 4295 switch (info->params.preamble_length) 4296 { 4297 case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break; 4298 case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break; 4299 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break; 4300 } 4301 4302 if (info->params.flags & HDLC_FLAG_AUTO_CTS) 4303 val |= BIT0; 4304 4305 wr_reg16(info, TCR, val); 4306 4307 /* TPR (transmit preamble) */ 4308 4309 switch (info->params.preamble) 4310 { 4311 case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break; 4312 case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break; 4313 case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break; 4314 case HDLC_PREAMBLE_PATTERN_10: val = 0x55; break; 4315 case HDLC_PREAMBLE_PATTERN_01: val = 0xaa; break; 4316 default: val = 0x7e; break; 4317 } 4318 wr_reg8(info, TPR, (unsigned char)val); 4319 4320 /* RCR (rx control) 4321 * 4322 * 15..13 mode 4323 * 000=HDLC/SDLC 4324 * 001=raw bit synchronous 4325 * 010=asynchronous/isochronous 4326 * 011=monosync byte synchronous 4327 * 100=bisync byte synchronous 4328 * 101=xsync byte synchronous 4329 * 12..10 encoding 4330 * 09 CRC enable 4331 * 08 CRC32 4332 * 07..03 reserved, must be 0 4333 * 02 reset 4334 * 01 enable 4335 * 00 auto-DCD enable 4336 */ 4337 val = 0; 4338 4339 switch(info->params.mode) { 4340 case MGSL_MODE_XSYNC: 4341 val |= BIT15 + BIT13; 4342 break; 4343 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break; 4344 case MGSL_MODE_BISYNC: val |= BIT15; break; 4345 case MGSL_MODE_RAW: val |= BIT13; break; 4346 } 4347 4348 switch(info->params.encoding) 4349 { 4350 case HDLC_ENCODING_NRZB: val |= BIT10; break; 4351 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break; 4352 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break; 4353 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break; 4354 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break; 4355 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break; 4356 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; 4357 } 4358 4359 switch (info->params.crc_type & HDLC_CRC_MASK) 4360 { 4361 case HDLC_CRC_16_CCITT: val |= BIT9; break; 4362 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break; 4363 } 4364 4365 if (info->params.flags & HDLC_FLAG_AUTO_DCD) 4366 val |= BIT0; 4367 4368 wr_reg16(info, RCR, val); 4369 4370 /* CCR (clock control) 4371 * 4372 * 07..05 tx clock source 4373 * 04..02 rx clock source 4374 * 01 auxclk enable 4375 * 00 BRG enable 4376 */ 4377 val = 0; 4378 4379 if (info->params.flags & HDLC_FLAG_TXC_BRG) 4380 { 4381 // when RxC source is DPLL, BRG generates 16X DPLL 4382 // reference clock, so take TxC from BRG/16 to get 4383 // transmit clock at actual data rate 4384 if (info->params.flags & HDLC_FLAG_RXC_DPLL) 4385 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */ 4386 else 4387 val |= BIT6; /* 010, txclk = BRG */ 4388 } 4389 else if (info->params.flags & HDLC_FLAG_TXC_DPLL) 4390 val |= BIT7; /* 100, txclk = DPLL Input */ 4391 else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN) 4392 val |= BIT5; /* 001, txclk = RXC Input */ 4393 4394 if (info->params.flags & HDLC_FLAG_RXC_BRG) 4395 val |= BIT3; /* 010, rxclk = BRG */ 4396 else if (info->params.flags & HDLC_FLAG_RXC_DPLL) 4397 val |= BIT4; /* 100, rxclk = DPLL */ 4398 else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN) 4399 val |= BIT2; /* 001, rxclk = TXC Input */ 4400 4401 if (info->params.clock_speed) 4402 val |= BIT1 + BIT0; 4403 4404 wr_reg8(info, CCR, (unsigned char)val); 4405 4406 if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL)) 4407 { 4408 // program DPLL mode 4409 switch(info->params.encoding) 4410 { 4411 case HDLC_ENCODING_BIPHASE_MARK: 4412 case HDLC_ENCODING_BIPHASE_SPACE: 4413 val = BIT7; break; 4414 case HDLC_ENCODING_BIPHASE_LEVEL: 4415 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: 4416 val = BIT7 + BIT6; break; 4417 default: val = BIT6; // NRZ encodings 4418 } 4419 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val)); 4420 4421 // DPLL requires a 16X reference clock from BRG 4422 set_rate(info, info->params.clock_speed * 16); 4423 } 4424 else 4425 set_rate(info, info->params.clock_speed); 4426 4427 tx_set_idle(info); 4428 4429 msc_set_vcr(info); 4430 4431 /* SCR (serial control) 4432 * 4433 * 15 1=tx req on FIFO half empty 4434 * 14 1=rx req on FIFO half full 4435 * 13 tx data IRQ enable 4436 * 12 tx idle IRQ enable 4437 * 11 underrun IRQ enable 4438 * 10 rx data IRQ enable 4439 * 09 rx idle IRQ enable 4440 * 08 overrun IRQ enable 4441 * 07 DSR IRQ enable 4442 * 06 CTS IRQ enable 4443 * 05 DCD IRQ enable 4444 * 04 RI IRQ enable 4445 * 03 reserved, must be zero 4446 * 02 1=txd->rxd internal loopback enable 4447 * 01 reserved, must be zero 4448 * 00 1=master IRQ enable 4449 */ 4450 wr_reg16(info, SCR, BIT15 + BIT14 + BIT0); 4451 4452 if (info->params.loopback) 4453 enable_loopback(info); 4454 } 4455 4456 /* 4457 * set transmit idle mode 4458 */ 4459 static void tx_set_idle(struct slgt_info *info) 4460 { 4461 unsigned char val; 4462 unsigned short tcr; 4463 4464 /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits 4465 * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits 4466 */ 4467 tcr = rd_reg16(info, TCR); 4468 if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) { 4469 /* disable preamble, set idle size to 16 bits */ 4470 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4; 4471 /* MSB of 16 bit idle specified in tx preamble register (TPR) */ 4472 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff)); 4473 } else if (!(tcr & BIT6)) { 4474 /* preamble is disabled, set idle size to 8 bits */ 4475 tcr &= ~(BIT5 + BIT4); 4476 } 4477 wr_reg16(info, TCR, tcr); 4478 4479 if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) { 4480 /* LSB of custom tx idle specified in tx idle register */ 4481 val = (unsigned char)(info->idle_mode & 0xff); 4482 } else { 4483 /* standard 8 bit idle patterns */ 4484 switch(info->idle_mode) 4485 { 4486 case HDLC_TXIDLE_FLAGS: val = 0x7e; break; 4487 case HDLC_TXIDLE_ALT_ZEROS_ONES: 4488 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break; 4489 case HDLC_TXIDLE_ZEROS: 4490 case HDLC_TXIDLE_SPACE: val = 0x00; break; 4491 default: val = 0xff; 4492 } 4493 } 4494 4495 wr_reg8(info, TIR, val); 4496 } 4497 4498 /* 4499 * get state of V24 status (input) signals 4500 */ 4501 static void get_signals(struct slgt_info *info) 4502 { 4503 unsigned short status = rd_reg16(info, SSR); 4504 4505 /* clear all serial signals except RTS and DTR */ 4506 info->signals &= SerialSignal_RTS | SerialSignal_DTR; 4507 4508 if (status & BIT3) 4509 info->signals |= SerialSignal_DSR; 4510 if (status & BIT2) 4511 info->signals |= SerialSignal_CTS; 4512 if (status & BIT1) 4513 info->signals |= SerialSignal_DCD; 4514 if (status & BIT0) 4515 info->signals |= SerialSignal_RI; 4516 } 4517 4518 /* 4519 * set V.24 Control Register based on current configuration 4520 */ 4521 static void msc_set_vcr(struct slgt_info *info) 4522 { 4523 unsigned char val = 0; 4524 4525 /* VCR (V.24 control) 4526 * 4527 * 07..04 serial IF select 4528 * 03 DTR 4529 * 02 RTS 4530 * 01 LL 4531 * 00 RL 4532 */ 4533 4534 switch(info->if_mode & MGSL_INTERFACE_MASK) 4535 { 4536 case MGSL_INTERFACE_RS232: 4537 val |= BIT5; /* 0010 */ 4538 break; 4539 case MGSL_INTERFACE_V35: 4540 val |= BIT7 + BIT6 + BIT5; /* 1110 */ 4541 break; 4542 case MGSL_INTERFACE_RS422: 4543 val |= BIT6; /* 0100 */ 4544 break; 4545 } 4546 4547 if (info->if_mode & MGSL_INTERFACE_MSB_FIRST) 4548 val |= BIT4; 4549 if (info->signals & SerialSignal_DTR) 4550 val |= BIT3; 4551 if (info->signals & SerialSignal_RTS) 4552 val |= BIT2; 4553 if (info->if_mode & MGSL_INTERFACE_LL) 4554 val |= BIT1; 4555 if (info->if_mode & MGSL_INTERFACE_RL) 4556 val |= BIT0; 4557 wr_reg8(info, VCR, val); 4558 } 4559 4560 /* 4561 * set state of V24 control (output) signals 4562 */ 4563 static void set_signals(struct slgt_info *info) 4564 { 4565 unsigned char val = rd_reg8(info, VCR); 4566 if (info->signals & SerialSignal_DTR) 4567 val |= BIT3; 4568 else 4569 val &= ~BIT3; 4570 if (info->signals & SerialSignal_RTS) 4571 val |= BIT2; 4572 else 4573 val &= ~BIT2; 4574 wr_reg8(info, VCR, val); 4575 } 4576 4577 /* 4578 * free range of receive DMA buffers (i to last) 4579 */ 4580 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last) 4581 { 4582 int done = 0; 4583 4584 while(!done) { 4585 /* reset current buffer for reuse */ 4586 info->rbufs[i].status = 0; 4587 set_desc_count(info->rbufs[i], info->rbuf_fill_level); 4588 if (i == last) 4589 done = 1; 4590 if (++i == info->rbuf_count) 4591 i = 0; 4592 } 4593 info->rbuf_current = i; 4594 } 4595 4596 /* 4597 * mark all receive DMA buffers as free 4598 */ 4599 static void reset_rbufs(struct slgt_info *info) 4600 { 4601 free_rbufs(info, 0, info->rbuf_count - 1); 4602 info->rbuf_fill_index = 0; 4603 info->rbuf_fill_count = 0; 4604 } 4605 4606 /* 4607 * pass receive HDLC frame to upper layer 4608 * 4609 * return true if frame available, otherwise false 4610 */ 4611 static bool rx_get_frame(struct slgt_info *info) 4612 { 4613 unsigned int start, end; 4614 unsigned short status; 4615 unsigned int framesize = 0; 4616 unsigned long flags; 4617 struct tty_struct *tty = info->port.tty; 4618 unsigned char addr_field = 0xff; 4619 unsigned int crc_size = 0; 4620 4621 switch (info->params.crc_type & HDLC_CRC_MASK) { 4622 case HDLC_CRC_16_CCITT: crc_size = 2; break; 4623 case HDLC_CRC_32_CCITT: crc_size = 4; break; 4624 } 4625 4626 check_again: 4627 4628 framesize = 0; 4629 addr_field = 0xff; 4630 start = end = info->rbuf_current; 4631 4632 for (;;) { 4633 if (!desc_complete(info->rbufs[end])) 4634 goto cleanup; 4635 4636 if (framesize == 0 && info->params.addr_filter != 0xff) 4637 addr_field = info->rbufs[end].buf[0]; 4638 4639 framesize += desc_count(info->rbufs[end]); 4640 4641 if (desc_eof(info->rbufs[end])) 4642 break; 4643 4644 if (++end == info->rbuf_count) 4645 end = 0; 4646 4647 if (end == info->rbuf_current) { 4648 if (info->rx_enabled){ 4649 spin_lock_irqsave(&info->lock,flags); 4650 rx_start(info); 4651 spin_unlock_irqrestore(&info->lock,flags); 4652 } 4653 goto cleanup; 4654 } 4655 } 4656 4657 /* status 4658 * 4659 * 15 buffer complete 4660 * 14..06 reserved 4661 * 05..04 residue 4662 * 02 eof (end of frame) 4663 * 01 CRC error 4664 * 00 abort 4665 */ 4666 status = desc_status(info->rbufs[end]); 4667 4668 /* ignore CRC bit if not using CRC (bit is undefined) */ 4669 if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE) 4670 status &= ~BIT1; 4671 4672 if (framesize == 0 || 4673 (addr_field != 0xff && addr_field != info->params.addr_filter)) { 4674 free_rbufs(info, start, end); 4675 goto check_again; 4676 } 4677 4678 if (framesize < (2 + crc_size) || status & BIT0) { 4679 info->icount.rxshort++; 4680 framesize = 0; 4681 } else if (status & BIT1) { 4682 info->icount.rxcrc++; 4683 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) 4684 framesize = 0; 4685 } 4686 4687 #if SYNCLINK_GENERIC_HDLC 4688 if (framesize == 0) { 4689 info->netdev->stats.rx_errors++; 4690 info->netdev->stats.rx_frame_errors++; 4691 } 4692 #endif 4693 4694 DBGBH(("%s rx frame status=%04X size=%d\n", 4695 info->device_name, status, framesize)); 4696 DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx"); 4697 4698 if (framesize) { 4699 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) { 4700 framesize -= crc_size; 4701 crc_size = 0; 4702 } 4703 4704 if (framesize > info->max_frame_size + crc_size) 4705 info->icount.rxlong++; 4706 else { 4707 /* copy dma buffer(s) to contiguous temp buffer */ 4708 int copy_count = framesize; 4709 int i = start; 4710 unsigned char *p = info->tmp_rbuf; 4711 info->tmp_rbuf_count = framesize; 4712 4713 info->icount.rxok++; 4714 4715 while(copy_count) { 4716 int partial_count = min_t(int, copy_count, info->rbuf_fill_level); 4717 memcpy(p, info->rbufs[i].buf, partial_count); 4718 p += partial_count; 4719 copy_count -= partial_count; 4720 if (++i == info->rbuf_count) 4721 i = 0; 4722 } 4723 4724 if (info->params.crc_type & HDLC_CRC_RETURN_EX) { 4725 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK; 4726 framesize++; 4727 } 4728 4729 #if SYNCLINK_GENERIC_HDLC 4730 if (info->netcount) 4731 hdlcdev_rx(info,info->tmp_rbuf, framesize); 4732 else 4733 #endif 4734 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize); 4735 } 4736 } 4737 free_rbufs(info, start, end); 4738 return true; 4739 4740 cleanup: 4741 return false; 4742 } 4743 4744 /* 4745 * pass receive buffer (RAW synchronous mode) to tty layer 4746 * return true if buffer available, otherwise false 4747 */ 4748 static bool rx_get_buf(struct slgt_info *info) 4749 { 4750 unsigned int i = info->rbuf_current; 4751 unsigned int count; 4752 4753 if (!desc_complete(info->rbufs[i])) 4754 return false; 4755 count = desc_count(info->rbufs[i]); 4756 switch(info->params.mode) { 4757 case MGSL_MODE_MONOSYNC: 4758 case MGSL_MODE_BISYNC: 4759 case MGSL_MODE_XSYNC: 4760 /* ignore residue in byte synchronous modes */ 4761 if (desc_residue(info->rbufs[i])) 4762 count--; 4763 break; 4764 } 4765 DBGDATA(info, info->rbufs[i].buf, count, "rx"); 4766 DBGINFO(("rx_get_buf size=%d\n", count)); 4767 if (count) 4768 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf, 4769 info->flag_buf, count); 4770 free_rbufs(info, i, i); 4771 return true; 4772 } 4773 4774 static void reset_tbufs(struct slgt_info *info) 4775 { 4776 unsigned int i; 4777 info->tbuf_current = 0; 4778 for (i=0 ; i < info->tbuf_count ; i++) { 4779 info->tbufs[i].status = 0; 4780 info->tbufs[i].count = 0; 4781 } 4782 } 4783 4784 /* 4785 * return number of free transmit DMA buffers 4786 */ 4787 static unsigned int free_tbuf_count(struct slgt_info *info) 4788 { 4789 unsigned int count = 0; 4790 unsigned int i = info->tbuf_current; 4791 4792 do 4793 { 4794 if (desc_count(info->tbufs[i])) 4795 break; /* buffer in use */ 4796 ++count; 4797 if (++i == info->tbuf_count) 4798 i=0; 4799 } while (i != info->tbuf_current); 4800 4801 /* if tx DMA active, last zero count buffer is in use */ 4802 if (count && (rd_reg32(info, TDCSR) & BIT0)) 4803 --count; 4804 4805 return count; 4806 } 4807 4808 /* 4809 * return number of bytes in unsent transmit DMA buffers 4810 * and the serial controller tx FIFO 4811 */ 4812 static unsigned int tbuf_bytes(struct slgt_info *info) 4813 { 4814 unsigned int total_count = 0; 4815 unsigned int i = info->tbuf_current; 4816 unsigned int reg_value; 4817 unsigned int count; 4818 unsigned int active_buf_count = 0; 4819 4820 /* 4821 * Add descriptor counts for all tx DMA buffers. 4822 * If count is zero (cleared by DMA controller after read), 4823 * the buffer is complete or is actively being read from. 4824 * 4825 * Record buf_count of last buffer with zero count starting 4826 * from current ring position. buf_count is mirror 4827 * copy of count and is not cleared by serial controller. 4828 * If DMA controller is active, that buffer is actively 4829 * being read so add to total. 4830 */ 4831 do { 4832 count = desc_count(info->tbufs[i]); 4833 if (count) 4834 total_count += count; 4835 else if (!total_count) 4836 active_buf_count = info->tbufs[i].buf_count; 4837 if (++i == info->tbuf_count) 4838 i = 0; 4839 } while (i != info->tbuf_current); 4840 4841 /* read tx DMA status register */ 4842 reg_value = rd_reg32(info, TDCSR); 4843 4844 /* if tx DMA active, last zero count buffer is in use */ 4845 if (reg_value & BIT0) 4846 total_count += active_buf_count; 4847 4848 /* add tx FIFO count = reg_value[15..8] */ 4849 total_count += (reg_value >> 8) & 0xff; 4850 4851 /* if transmitter active add one byte for shift register */ 4852 if (info->tx_active) 4853 total_count++; 4854 4855 return total_count; 4856 } 4857 4858 /* 4859 * load data into transmit DMA buffer ring and start transmitter if needed 4860 * return true if data accepted, otherwise false (buffers full) 4861 */ 4862 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int size) 4863 { 4864 unsigned short count; 4865 unsigned int i; 4866 struct slgt_desc *d; 4867 4868 /* check required buffer space */ 4869 if (DIV_ROUND_UP(size, DMABUFSIZE) > free_tbuf_count(info)) 4870 return false; 4871 4872 DBGDATA(info, buf, size, "tx"); 4873 4874 /* 4875 * copy data to one or more DMA buffers in circular ring 4876 * tbuf_start = first buffer for this data 4877 * tbuf_current = next free buffer 4878 * 4879 * Copy all data before making data visible to DMA controller by 4880 * setting descriptor count of the first buffer. 4881 * This prevents an active DMA controller from reading the first DMA 4882 * buffers of a frame and stopping before the final buffers are filled. 4883 */ 4884 4885 info->tbuf_start = i = info->tbuf_current; 4886 4887 while (size) { 4888 d = &info->tbufs[i]; 4889 4890 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size); 4891 memcpy(d->buf, buf, count); 4892 4893 size -= count; 4894 buf += count; 4895 4896 /* 4897 * set EOF bit for last buffer of HDLC frame or 4898 * for every buffer in raw mode 4899 */ 4900 if ((!size && info->params.mode == MGSL_MODE_HDLC) || 4901 info->params.mode == MGSL_MODE_RAW) 4902 set_desc_eof(*d, 1); 4903 else 4904 set_desc_eof(*d, 0); 4905 4906 /* set descriptor count for all but first buffer */ 4907 if (i != info->tbuf_start) 4908 set_desc_count(*d, count); 4909 d->buf_count = count; 4910 4911 if (++i == info->tbuf_count) 4912 i = 0; 4913 } 4914 4915 info->tbuf_current = i; 4916 4917 /* set first buffer count to make new data visible to DMA controller */ 4918 d = &info->tbufs[info->tbuf_start]; 4919 set_desc_count(*d, d->buf_count); 4920 4921 /* start transmitter if needed and update transmit timeout */ 4922 if (!info->tx_active) 4923 tx_start(info); 4924 update_tx_timer(info); 4925 4926 return true; 4927 } 4928 4929 static int register_test(struct slgt_info *info) 4930 { 4931 static unsigned short patterns[] = 4932 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696}; 4933 static unsigned int count = ARRAY_SIZE(patterns); 4934 unsigned int i; 4935 int rc = 0; 4936 4937 for (i=0 ; i < count ; i++) { 4938 wr_reg16(info, TIR, patterns[i]); 4939 wr_reg16(info, BDR, patterns[(i+1)%count]); 4940 if ((rd_reg16(info, TIR) != patterns[i]) || 4941 (rd_reg16(info, BDR) != patterns[(i+1)%count])) { 4942 rc = -ENODEV; 4943 break; 4944 } 4945 } 4946 info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0; 4947 info->init_error = rc ? 0 : DiagStatus_AddressFailure; 4948 return rc; 4949 } 4950 4951 static int irq_test(struct slgt_info *info) 4952 { 4953 unsigned long timeout; 4954 unsigned long flags; 4955 struct tty_struct *oldtty = info->port.tty; 4956 u32 speed = info->params.data_rate; 4957 4958 info->params.data_rate = 921600; 4959 info->port.tty = NULL; 4960 4961 spin_lock_irqsave(&info->lock, flags); 4962 async_mode(info); 4963 slgt_irq_on(info, IRQ_TXIDLE); 4964 4965 /* enable transmitter */ 4966 wr_reg16(info, TCR, 4967 (unsigned short)(rd_reg16(info, TCR) | BIT1)); 4968 4969 /* write one byte and wait for tx idle */ 4970 wr_reg16(info, TDR, 0); 4971 4972 /* assume failure */ 4973 info->init_error = DiagStatus_IrqFailure; 4974 info->irq_occurred = false; 4975 4976 spin_unlock_irqrestore(&info->lock, flags); 4977 4978 timeout=100; 4979 while(timeout-- && !info->irq_occurred) 4980 msleep_interruptible(10); 4981 4982 spin_lock_irqsave(&info->lock,flags); 4983 reset_port(info); 4984 spin_unlock_irqrestore(&info->lock,flags); 4985 4986 info->params.data_rate = speed; 4987 info->port.tty = oldtty; 4988 4989 info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure; 4990 return info->irq_occurred ? 0 : -ENODEV; 4991 } 4992 4993 static int loopback_test_rx(struct slgt_info *info) 4994 { 4995 unsigned char *src, *dest; 4996 int count; 4997 4998 if (desc_complete(info->rbufs[0])) { 4999 count = desc_count(info->rbufs[0]); 5000 src = info->rbufs[0].buf; 5001 dest = info->tmp_rbuf; 5002 5003 for( ; count ; count-=2, src+=2) { 5004 /* src=data byte (src+1)=status byte */ 5005 if (!(*(src+1) & (BIT9 + BIT8))) { 5006 *dest = *src; 5007 dest++; 5008 info->tmp_rbuf_count++; 5009 } 5010 } 5011 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx"); 5012 return 1; 5013 } 5014 return 0; 5015 } 5016 5017 static int loopback_test(struct slgt_info *info) 5018 { 5019 #define TESTFRAMESIZE 20 5020 5021 unsigned long timeout; 5022 u16 count = TESTFRAMESIZE; 5023 unsigned char buf[TESTFRAMESIZE]; 5024 int rc = -ENODEV; 5025 unsigned long flags; 5026 5027 struct tty_struct *oldtty = info->port.tty; 5028 MGSL_PARAMS params; 5029 5030 memcpy(¶ms, &info->params, sizeof(params)); 5031 5032 info->params.mode = MGSL_MODE_ASYNC; 5033 info->params.data_rate = 921600; 5034 info->params.loopback = 1; 5035 info->port.tty = NULL; 5036 5037 /* build and send transmit frame */ 5038 for (count = 0; count < TESTFRAMESIZE; ++count) 5039 buf[count] = (unsigned char)count; 5040 5041 info->tmp_rbuf_count = 0; 5042 memset(info->tmp_rbuf, 0, TESTFRAMESIZE); 5043 5044 /* program hardware for HDLC and enabled receiver */ 5045 spin_lock_irqsave(&info->lock,flags); 5046 async_mode(info); 5047 rx_start(info); 5048 tx_load(info, buf, count); 5049 spin_unlock_irqrestore(&info->lock, flags); 5050 5051 /* wait for receive complete */ 5052 for (timeout = 100; timeout; --timeout) { 5053 msleep_interruptible(10); 5054 if (loopback_test_rx(info)) { 5055 rc = 0; 5056 break; 5057 } 5058 } 5059 5060 /* verify received frame length and contents */ 5061 if (!rc && (info->tmp_rbuf_count != count || 5062 memcmp(buf, info->tmp_rbuf, count))) { 5063 rc = -ENODEV; 5064 } 5065 5066 spin_lock_irqsave(&info->lock,flags); 5067 reset_adapter(info); 5068 spin_unlock_irqrestore(&info->lock,flags); 5069 5070 memcpy(&info->params, ¶ms, sizeof(info->params)); 5071 info->port.tty = oldtty; 5072 5073 info->init_error = rc ? DiagStatus_DmaFailure : 0; 5074 return rc; 5075 } 5076 5077 static int adapter_test(struct slgt_info *info) 5078 { 5079 DBGINFO(("testing %s\n", info->device_name)); 5080 if (register_test(info) < 0) { 5081 printk("register test failure %s addr=%08X\n", 5082 info->device_name, info->phys_reg_addr); 5083 } else if (irq_test(info) < 0) { 5084 printk("IRQ test failure %s IRQ=%d\n", 5085 info->device_name, info->irq_level); 5086 } else if (loopback_test(info) < 0) { 5087 printk("loopback test failure %s\n", info->device_name); 5088 } 5089 return info->init_error; 5090 } 5091 5092 /* 5093 * transmit timeout handler 5094 */ 5095 static void tx_timeout(struct timer_list *t) 5096 { 5097 struct slgt_info *info = from_timer(info, t, tx_timer); 5098 unsigned long flags; 5099 5100 DBGINFO(("%s tx_timeout\n", info->device_name)); 5101 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) { 5102 info->icount.txtimeout++; 5103 } 5104 spin_lock_irqsave(&info->lock,flags); 5105 tx_stop(info); 5106 spin_unlock_irqrestore(&info->lock,flags); 5107 5108 #if SYNCLINK_GENERIC_HDLC 5109 if (info->netcount) 5110 hdlcdev_tx_done(info); 5111 else 5112 #endif 5113 bh_transmit(info); 5114 } 5115 5116 /* 5117 * receive buffer polling timer 5118 */ 5119 static void rx_timeout(struct timer_list *t) 5120 { 5121 struct slgt_info *info = from_timer(info, t, rx_timer); 5122 unsigned long flags; 5123 5124 DBGINFO(("%s rx_timeout\n", info->device_name)); 5125 spin_lock_irqsave(&info->lock, flags); 5126 info->pending_bh |= BH_RECEIVE; 5127 spin_unlock_irqrestore(&info->lock, flags); 5128 bh_handler(&info->task); 5129 } 5130 5131