1 /* 2 * Device driver for Microgate SyncLink GT serial adapters. 3 * 4 * written by Paul Fulghum for Microgate Corporation 5 * paulkf@microgate.com 6 * 7 * Microgate and SyncLink are trademarks of Microgate Corporation 8 * 9 * This code is released under the GNU General Public License (GPL) 10 * 11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 13 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 14 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 15 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 16 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 17 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 18 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 19 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 20 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 21 * OF THE POSSIBILITY OF SUCH DAMAGE. 22 */ 23 24 /* 25 * DEBUG OUTPUT DEFINITIONS 26 * 27 * uncomment lines below to enable specific types of debug output 28 * 29 * DBGINFO information - most verbose output 30 * DBGERR serious errors 31 * DBGBH bottom half service routine debugging 32 * DBGISR interrupt service routine debugging 33 * DBGDATA output receive and transmit data 34 * DBGTBUF output transmit DMA buffers and registers 35 * DBGRBUF output receive DMA buffers and registers 36 */ 37 38 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt 39 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt 40 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt 41 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt 42 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label)) 43 /*#define DBGTBUF(info) dump_tbufs(info)*/ 44 /*#define DBGRBUF(info) dump_rbufs(info)*/ 45 46 47 #include <linux/module.h> 48 #include <linux/errno.h> 49 #include <linux/signal.h> 50 #include <linux/sched.h> 51 #include <linux/timer.h> 52 #include <linux/interrupt.h> 53 #include <linux/pci.h> 54 #include <linux/tty.h> 55 #include <linux/tty_flip.h> 56 #include <linux/serial.h> 57 #include <linux/major.h> 58 #include <linux/string.h> 59 #include <linux/fcntl.h> 60 #include <linux/ptrace.h> 61 #include <linux/ioport.h> 62 #include <linux/mm.h> 63 #include <linux/seq_file.h> 64 #include <linux/slab.h> 65 #include <linux/netdevice.h> 66 #include <linux/vmalloc.h> 67 #include <linux/init.h> 68 #include <linux/delay.h> 69 #include <linux/ioctl.h> 70 #include <linux/termios.h> 71 #include <linux/bitops.h> 72 #include <linux/workqueue.h> 73 #include <linux/hdlc.h> 74 #include <linux/synclink.h> 75 76 #include <asm/io.h> 77 #include <asm/irq.h> 78 #include <asm/dma.h> 79 #include <asm/types.h> 80 #include <asm/uaccess.h> 81 82 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE)) 83 #define SYNCLINK_GENERIC_HDLC 1 84 #else 85 #define SYNCLINK_GENERIC_HDLC 0 86 #endif 87 88 /* 89 * module identification 90 */ 91 static char *driver_name = "SyncLink GT"; 92 static char *slgt_driver_name = "synclink_gt"; 93 static char *tty_dev_prefix = "ttySLG"; 94 MODULE_LICENSE("GPL"); 95 #define MGSL_MAGIC 0x5401 96 #define MAX_DEVICES 32 97 98 static struct pci_device_id pci_table[] = { 99 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, 100 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, 101 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, 102 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, 103 {0,}, /* terminate list */ 104 }; 105 MODULE_DEVICE_TABLE(pci, pci_table); 106 107 static int init_one(struct pci_dev *dev,const struct pci_device_id *ent); 108 static void remove_one(struct pci_dev *dev); 109 static struct pci_driver pci_driver = { 110 .name = "synclink_gt", 111 .id_table = pci_table, 112 .probe = init_one, 113 .remove = remove_one, 114 }; 115 116 static bool pci_registered; 117 118 /* 119 * module configuration and status 120 */ 121 static struct slgt_info *slgt_device_list; 122 static int slgt_device_count; 123 124 static int ttymajor; 125 static int debug_level; 126 static int maxframe[MAX_DEVICES]; 127 128 module_param(ttymajor, int, 0); 129 module_param(debug_level, int, 0); 130 module_param_array(maxframe, int, NULL, 0); 131 132 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned"); 133 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail"); 134 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)"); 135 136 /* 137 * tty support and callbacks 138 */ 139 static struct tty_driver *serial_driver; 140 141 static int open(struct tty_struct *tty, struct file * filp); 142 static void close(struct tty_struct *tty, struct file * filp); 143 static void hangup(struct tty_struct *tty); 144 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios); 145 146 static int write(struct tty_struct *tty, const unsigned char *buf, int count); 147 static int put_char(struct tty_struct *tty, unsigned char ch); 148 static void send_xchar(struct tty_struct *tty, char ch); 149 static void wait_until_sent(struct tty_struct *tty, int timeout); 150 static int write_room(struct tty_struct *tty); 151 static void flush_chars(struct tty_struct *tty); 152 static void flush_buffer(struct tty_struct *tty); 153 static void tx_hold(struct tty_struct *tty); 154 static void tx_release(struct tty_struct *tty); 155 156 static int ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg); 157 static int chars_in_buffer(struct tty_struct *tty); 158 static void throttle(struct tty_struct * tty); 159 static void unthrottle(struct tty_struct * tty); 160 static int set_break(struct tty_struct *tty, int break_state); 161 162 /* 163 * generic HDLC support and callbacks 164 */ 165 #if SYNCLINK_GENERIC_HDLC 166 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 167 static void hdlcdev_tx_done(struct slgt_info *info); 168 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size); 169 static int hdlcdev_init(struct slgt_info *info); 170 static void hdlcdev_exit(struct slgt_info *info); 171 #endif 172 173 174 /* 175 * device specific structures, macros and functions 176 */ 177 178 #define SLGT_MAX_PORTS 4 179 #define SLGT_REG_SIZE 256 180 181 /* 182 * conditional wait facility 183 */ 184 struct cond_wait { 185 struct cond_wait *next; 186 wait_queue_head_t q; 187 wait_queue_t wait; 188 unsigned int data; 189 }; 190 static void init_cond_wait(struct cond_wait *w, unsigned int data); 191 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w); 192 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w); 193 static void flush_cond_wait(struct cond_wait **head); 194 195 /* 196 * DMA buffer descriptor and access macros 197 */ 198 struct slgt_desc 199 { 200 __le16 count; 201 __le16 status; 202 __le32 pbuf; /* physical address of data buffer */ 203 __le32 next; /* physical address of next descriptor */ 204 205 /* driver book keeping */ 206 char *buf; /* virtual address of data buffer */ 207 unsigned int pdesc; /* physical address of this descriptor */ 208 dma_addr_t buf_dma_addr; 209 unsigned short buf_count; 210 }; 211 212 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b)) 213 #define set_desc_next(a,b) (a).next = cpu_to_le32((unsigned int)(b)) 214 #define set_desc_count(a,b)(a).count = cpu_to_le16((unsigned short)(b)) 215 #define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0)) 216 #define set_desc_status(a, b) (a).status = cpu_to_le16((unsigned short)(b)) 217 #define desc_count(a) (le16_to_cpu((a).count)) 218 #define desc_status(a) (le16_to_cpu((a).status)) 219 #define desc_complete(a) (le16_to_cpu((a).status) & BIT15) 220 #define desc_eof(a) (le16_to_cpu((a).status) & BIT2) 221 #define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1) 222 #define desc_abort(a) (le16_to_cpu((a).status) & BIT0) 223 #define desc_residue(a) ((le16_to_cpu((a).status) & 0x38) >> 3) 224 225 struct _input_signal_events { 226 int ri_up; 227 int ri_down; 228 int dsr_up; 229 int dsr_down; 230 int dcd_up; 231 int dcd_down; 232 int cts_up; 233 int cts_down; 234 }; 235 236 /* 237 * device instance data structure 238 */ 239 struct slgt_info { 240 void *if_ptr; /* General purpose pointer (used by SPPP) */ 241 struct tty_port port; 242 243 struct slgt_info *next_device; /* device list link */ 244 245 int magic; 246 247 char device_name[25]; 248 struct pci_dev *pdev; 249 250 int port_count; /* count of ports on adapter */ 251 int adapter_num; /* adapter instance number */ 252 int port_num; /* port instance number */ 253 254 /* array of pointers to port contexts on this adapter */ 255 struct slgt_info *port_array[SLGT_MAX_PORTS]; 256 257 int line; /* tty line instance number */ 258 259 struct mgsl_icount icount; 260 261 int timeout; 262 int x_char; /* xon/xoff character */ 263 unsigned int read_status_mask; 264 unsigned int ignore_status_mask; 265 266 wait_queue_head_t status_event_wait_q; 267 wait_queue_head_t event_wait_q; 268 struct timer_list tx_timer; 269 struct timer_list rx_timer; 270 271 unsigned int gpio_present; 272 struct cond_wait *gpio_wait_q; 273 274 spinlock_t lock; /* spinlock for synchronizing with ISR */ 275 276 struct work_struct task; 277 u32 pending_bh; 278 bool bh_requested; 279 bool bh_running; 280 281 int isr_overflow; 282 bool irq_requested; /* true if IRQ requested */ 283 bool irq_occurred; /* for diagnostics use */ 284 285 /* device configuration */ 286 287 unsigned int bus_type; 288 unsigned int irq_level; 289 unsigned long irq_flags; 290 291 unsigned char __iomem * reg_addr; /* memory mapped registers address */ 292 u32 phys_reg_addr; 293 bool reg_addr_requested; 294 295 MGSL_PARAMS params; /* communications parameters */ 296 u32 idle_mode; 297 u32 max_frame_size; /* as set by device config */ 298 299 unsigned int rbuf_fill_level; 300 unsigned int rx_pio; 301 unsigned int if_mode; 302 unsigned int base_clock; 303 unsigned int xsync; 304 unsigned int xctrl; 305 306 /* device status */ 307 308 bool rx_enabled; 309 bool rx_restart; 310 311 bool tx_enabled; 312 bool tx_active; 313 314 unsigned char signals; /* serial signal states */ 315 int init_error; /* initialization error */ 316 317 unsigned char *tx_buf; 318 int tx_count; 319 320 char *flag_buf; 321 bool drop_rts_on_tx_done; 322 struct _input_signal_events input_signal_events; 323 324 int dcd_chkcount; /* check counts to prevent */ 325 int cts_chkcount; /* too many IRQs if a signal */ 326 int dsr_chkcount; /* is floating */ 327 int ri_chkcount; 328 329 char *bufs; /* virtual address of DMA buffer lists */ 330 dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */ 331 332 unsigned int rbuf_count; 333 struct slgt_desc *rbufs; 334 unsigned int rbuf_current; 335 unsigned int rbuf_index; 336 unsigned int rbuf_fill_index; 337 unsigned short rbuf_fill_count; 338 339 unsigned int tbuf_count; 340 struct slgt_desc *tbufs; 341 unsigned int tbuf_current; 342 unsigned int tbuf_start; 343 344 unsigned char *tmp_rbuf; 345 unsigned int tmp_rbuf_count; 346 347 /* SPPP/Cisco HDLC device parts */ 348 349 int netcount; 350 spinlock_t netlock; 351 #if SYNCLINK_GENERIC_HDLC 352 struct net_device *netdev; 353 #endif 354 355 }; 356 357 static MGSL_PARAMS default_params = { 358 .mode = MGSL_MODE_HDLC, 359 .loopback = 0, 360 .flags = HDLC_FLAG_UNDERRUN_ABORT15, 361 .encoding = HDLC_ENCODING_NRZI_SPACE, 362 .clock_speed = 0, 363 .addr_filter = 0xff, 364 .crc_type = HDLC_CRC_16_CCITT, 365 .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS, 366 .preamble = HDLC_PREAMBLE_PATTERN_NONE, 367 .data_rate = 9600, 368 .data_bits = 8, 369 .stop_bits = 1, 370 .parity = ASYNC_PARITY_NONE 371 }; 372 373 374 #define BH_RECEIVE 1 375 #define BH_TRANSMIT 2 376 #define BH_STATUS 4 377 #define IO_PIN_SHUTDOWN_LIMIT 100 378 379 #define DMABUFSIZE 256 380 #define DESC_LIST_SIZE 4096 381 382 #define MASK_PARITY BIT1 383 #define MASK_FRAMING BIT0 384 #define MASK_BREAK BIT14 385 #define MASK_OVERRUN BIT4 386 387 #define GSR 0x00 /* global status */ 388 #define JCR 0x04 /* JTAG control */ 389 #define IODR 0x08 /* GPIO direction */ 390 #define IOER 0x0c /* GPIO interrupt enable */ 391 #define IOVR 0x10 /* GPIO value */ 392 #define IOSR 0x14 /* GPIO interrupt status */ 393 #define TDR 0x80 /* tx data */ 394 #define RDR 0x80 /* rx data */ 395 #define TCR 0x82 /* tx control */ 396 #define TIR 0x84 /* tx idle */ 397 #define TPR 0x85 /* tx preamble */ 398 #define RCR 0x86 /* rx control */ 399 #define VCR 0x88 /* V.24 control */ 400 #define CCR 0x89 /* clock control */ 401 #define BDR 0x8a /* baud divisor */ 402 #define SCR 0x8c /* serial control */ 403 #define SSR 0x8e /* serial status */ 404 #define RDCSR 0x90 /* rx DMA control/status */ 405 #define TDCSR 0x94 /* tx DMA control/status */ 406 #define RDDAR 0x98 /* rx DMA descriptor address */ 407 #define TDDAR 0x9c /* tx DMA descriptor address */ 408 #define XSR 0x40 /* extended sync pattern */ 409 #define XCR 0x44 /* extended control */ 410 411 #define RXIDLE BIT14 412 #define RXBREAK BIT14 413 #define IRQ_TXDATA BIT13 414 #define IRQ_TXIDLE BIT12 415 #define IRQ_TXUNDER BIT11 /* HDLC */ 416 #define IRQ_RXDATA BIT10 417 #define IRQ_RXIDLE BIT9 /* HDLC */ 418 #define IRQ_RXBREAK BIT9 /* async */ 419 #define IRQ_RXOVER BIT8 420 #define IRQ_DSR BIT7 421 #define IRQ_CTS BIT6 422 #define IRQ_DCD BIT5 423 #define IRQ_RI BIT4 424 #define IRQ_ALL 0x3ff0 425 #define IRQ_MASTER BIT0 426 427 #define slgt_irq_on(info, mask) \ 428 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask))) 429 #define slgt_irq_off(info, mask) \ 430 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask))) 431 432 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr); 433 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value); 434 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr); 435 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value); 436 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr); 437 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value); 438 439 static void msc_set_vcr(struct slgt_info *info); 440 441 static int startup(struct slgt_info *info); 442 static int block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info); 443 static void shutdown(struct slgt_info *info); 444 static void program_hw(struct slgt_info *info); 445 static void change_params(struct slgt_info *info); 446 447 static int register_test(struct slgt_info *info); 448 static int irq_test(struct slgt_info *info); 449 static int loopback_test(struct slgt_info *info); 450 static int adapter_test(struct slgt_info *info); 451 452 static void reset_adapter(struct slgt_info *info); 453 static void reset_port(struct slgt_info *info); 454 static void async_mode(struct slgt_info *info); 455 static void sync_mode(struct slgt_info *info); 456 457 static void rx_stop(struct slgt_info *info); 458 static void rx_start(struct slgt_info *info); 459 static void reset_rbufs(struct slgt_info *info); 460 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last); 461 static void rdma_reset(struct slgt_info *info); 462 static bool rx_get_frame(struct slgt_info *info); 463 static bool rx_get_buf(struct slgt_info *info); 464 465 static void tx_start(struct slgt_info *info); 466 static void tx_stop(struct slgt_info *info); 467 static void tx_set_idle(struct slgt_info *info); 468 static unsigned int free_tbuf_count(struct slgt_info *info); 469 static unsigned int tbuf_bytes(struct slgt_info *info); 470 static void reset_tbufs(struct slgt_info *info); 471 static void tdma_reset(struct slgt_info *info); 472 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int count); 473 474 static void get_signals(struct slgt_info *info); 475 static void set_signals(struct slgt_info *info); 476 static void enable_loopback(struct slgt_info *info); 477 static void set_rate(struct slgt_info *info, u32 data_rate); 478 479 static int bh_action(struct slgt_info *info); 480 static void bh_handler(struct work_struct *work); 481 static void bh_transmit(struct slgt_info *info); 482 static void isr_serial(struct slgt_info *info); 483 static void isr_rdma(struct slgt_info *info); 484 static void isr_txeom(struct slgt_info *info, unsigned short status); 485 static void isr_tdma(struct slgt_info *info); 486 487 static int alloc_dma_bufs(struct slgt_info *info); 488 static void free_dma_bufs(struct slgt_info *info); 489 static int alloc_desc(struct slgt_info *info); 490 static void free_desc(struct slgt_info *info); 491 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count); 492 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count); 493 494 static int alloc_tmp_rbuf(struct slgt_info *info); 495 static void free_tmp_rbuf(struct slgt_info *info); 496 497 static void tx_timeout(unsigned long context); 498 static void rx_timeout(unsigned long context); 499 500 /* 501 * ioctl handlers 502 */ 503 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount); 504 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *params); 505 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *params); 506 static int get_txidle(struct slgt_info *info, int __user *idle_mode); 507 static int set_txidle(struct slgt_info *info, int idle_mode); 508 static int tx_enable(struct slgt_info *info, int enable); 509 static int tx_abort(struct slgt_info *info); 510 static int rx_enable(struct slgt_info *info, int enable); 511 static int modem_input_wait(struct slgt_info *info,int arg); 512 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr); 513 static int tiocmget(struct tty_struct *tty); 514 static int tiocmset(struct tty_struct *tty, 515 unsigned int set, unsigned int clear); 516 static int set_break(struct tty_struct *tty, int break_state); 517 static int get_interface(struct slgt_info *info, int __user *if_mode); 518 static int set_interface(struct slgt_info *info, int if_mode); 519 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio); 520 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio); 521 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio); 522 static int get_xsync(struct slgt_info *info, int __user *if_mode); 523 static int set_xsync(struct slgt_info *info, int if_mode); 524 static int get_xctrl(struct slgt_info *info, int __user *if_mode); 525 static int set_xctrl(struct slgt_info *info, int if_mode); 526 527 /* 528 * driver functions 529 */ 530 static void add_device(struct slgt_info *info); 531 static void device_init(int adapter_num, struct pci_dev *pdev); 532 static int claim_resources(struct slgt_info *info); 533 static void release_resources(struct slgt_info *info); 534 535 /* 536 * DEBUG OUTPUT CODE 537 */ 538 #ifndef DBGINFO 539 #define DBGINFO(fmt) 540 #endif 541 #ifndef DBGERR 542 #define DBGERR(fmt) 543 #endif 544 #ifndef DBGBH 545 #define DBGBH(fmt) 546 #endif 547 #ifndef DBGISR 548 #define DBGISR(fmt) 549 #endif 550 551 #ifdef DBGDATA 552 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label) 553 { 554 int i; 555 int linecount; 556 printk("%s %s data:\n",info->device_name, label); 557 while(count) { 558 linecount = (count > 16) ? 16 : count; 559 for(i=0; i < linecount; i++) 560 printk("%02X ",(unsigned char)data[i]); 561 for(;i<17;i++) 562 printk(" "); 563 for(i=0;i<linecount;i++) { 564 if (data[i]>=040 && data[i]<=0176) 565 printk("%c",data[i]); 566 else 567 printk("."); 568 } 569 printk("\n"); 570 data += linecount; 571 count -= linecount; 572 } 573 } 574 #else 575 #define DBGDATA(info, buf, size, label) 576 #endif 577 578 #ifdef DBGTBUF 579 static void dump_tbufs(struct slgt_info *info) 580 { 581 int i; 582 printk("tbuf_current=%d\n", info->tbuf_current); 583 for (i=0 ; i < info->tbuf_count ; i++) { 584 printk("%d: count=%04X status=%04X\n", 585 i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status)); 586 } 587 } 588 #else 589 #define DBGTBUF(info) 590 #endif 591 592 #ifdef DBGRBUF 593 static void dump_rbufs(struct slgt_info *info) 594 { 595 int i; 596 printk("rbuf_current=%d\n", info->rbuf_current); 597 for (i=0 ; i < info->rbuf_count ; i++) { 598 printk("%d: count=%04X status=%04X\n", 599 i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status)); 600 } 601 } 602 #else 603 #define DBGRBUF(info) 604 #endif 605 606 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name) 607 { 608 #ifdef SANITY_CHECK 609 if (!info) { 610 printk("null struct slgt_info for (%s) in %s\n", devname, name); 611 return 1; 612 } 613 if (info->magic != MGSL_MAGIC) { 614 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name); 615 return 1; 616 } 617 #else 618 if (!info) 619 return 1; 620 #endif 621 return 0; 622 } 623 624 /** 625 * line discipline callback wrappers 626 * 627 * The wrappers maintain line discipline references 628 * while calling into the line discipline. 629 * 630 * ldisc_receive_buf - pass receive data to line discipline 631 */ 632 static void ldisc_receive_buf(struct tty_struct *tty, 633 const __u8 *data, char *flags, int count) 634 { 635 struct tty_ldisc *ld; 636 if (!tty) 637 return; 638 ld = tty_ldisc_ref(tty); 639 if (ld) { 640 if (ld->ops->receive_buf) 641 ld->ops->receive_buf(tty, data, flags, count); 642 tty_ldisc_deref(ld); 643 } 644 } 645 646 /* tty callbacks */ 647 648 static int open(struct tty_struct *tty, struct file *filp) 649 { 650 struct slgt_info *info; 651 int retval, line; 652 unsigned long flags; 653 654 line = tty->index; 655 if (line >= slgt_device_count) { 656 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line)); 657 return -ENODEV; 658 } 659 660 info = slgt_device_list; 661 while(info && info->line != line) 662 info = info->next_device; 663 if (sanity_check(info, tty->name, "open")) 664 return -ENODEV; 665 if (info->init_error) { 666 DBGERR(("%s init error=%d\n", info->device_name, info->init_error)); 667 return -ENODEV; 668 } 669 670 tty->driver_data = info; 671 info->port.tty = tty; 672 673 DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count)); 674 675 mutex_lock(&info->port.mutex); 676 info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0; 677 678 spin_lock_irqsave(&info->netlock, flags); 679 if (info->netcount) { 680 retval = -EBUSY; 681 spin_unlock_irqrestore(&info->netlock, flags); 682 mutex_unlock(&info->port.mutex); 683 goto cleanup; 684 } 685 info->port.count++; 686 spin_unlock_irqrestore(&info->netlock, flags); 687 688 if (info->port.count == 1) { 689 /* 1st open on this device, init hardware */ 690 retval = startup(info); 691 if (retval < 0) { 692 mutex_unlock(&info->port.mutex); 693 goto cleanup; 694 } 695 } 696 mutex_unlock(&info->port.mutex); 697 retval = block_til_ready(tty, filp, info); 698 if (retval) { 699 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval)); 700 goto cleanup; 701 } 702 703 retval = 0; 704 705 cleanup: 706 if (retval) { 707 if (tty->count == 1) 708 info->port.tty = NULL; /* tty layer will release tty struct */ 709 if(info->port.count) 710 info->port.count--; 711 } 712 713 DBGINFO(("%s open rc=%d\n", info->device_name, retval)); 714 return retval; 715 } 716 717 static void close(struct tty_struct *tty, struct file *filp) 718 { 719 struct slgt_info *info = tty->driver_data; 720 721 if (sanity_check(info, tty->name, "close")) 722 return; 723 DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count)); 724 725 if (tty_port_close_start(&info->port, tty, filp) == 0) 726 goto cleanup; 727 728 mutex_lock(&info->port.mutex); 729 if (info->port.flags & ASYNC_INITIALIZED) 730 wait_until_sent(tty, info->timeout); 731 flush_buffer(tty); 732 tty_ldisc_flush(tty); 733 734 shutdown(info); 735 mutex_unlock(&info->port.mutex); 736 737 tty_port_close_end(&info->port, tty); 738 info->port.tty = NULL; 739 cleanup: 740 DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count)); 741 } 742 743 static void hangup(struct tty_struct *tty) 744 { 745 struct slgt_info *info = tty->driver_data; 746 unsigned long flags; 747 748 if (sanity_check(info, tty->name, "hangup")) 749 return; 750 DBGINFO(("%s hangup\n", info->device_name)); 751 752 flush_buffer(tty); 753 754 mutex_lock(&info->port.mutex); 755 shutdown(info); 756 757 spin_lock_irqsave(&info->port.lock, flags); 758 info->port.count = 0; 759 info->port.flags &= ~ASYNC_NORMAL_ACTIVE; 760 info->port.tty = NULL; 761 spin_unlock_irqrestore(&info->port.lock, flags); 762 mutex_unlock(&info->port.mutex); 763 764 wake_up_interruptible(&info->port.open_wait); 765 } 766 767 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios) 768 { 769 struct slgt_info *info = tty->driver_data; 770 unsigned long flags; 771 772 DBGINFO(("%s set_termios\n", tty->driver->name)); 773 774 change_params(info); 775 776 /* Handle transition to B0 status */ 777 if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) { 778 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR); 779 spin_lock_irqsave(&info->lock,flags); 780 set_signals(info); 781 spin_unlock_irqrestore(&info->lock,flags); 782 } 783 784 /* Handle transition away from B0 status */ 785 if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) { 786 info->signals |= SerialSignal_DTR; 787 if (!C_CRTSCTS(tty) || !test_bit(TTY_THROTTLED, &tty->flags)) 788 info->signals |= SerialSignal_RTS; 789 spin_lock_irqsave(&info->lock,flags); 790 set_signals(info); 791 spin_unlock_irqrestore(&info->lock,flags); 792 } 793 794 /* Handle turning off CRTSCTS */ 795 if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty)) { 796 tty->hw_stopped = 0; 797 tx_release(tty); 798 } 799 } 800 801 static void update_tx_timer(struct slgt_info *info) 802 { 803 /* 804 * use worst case speed of 1200bps to calculate transmit timeout 805 * based on data in buffers (tbuf_bytes) and FIFO (128 bytes) 806 */ 807 if (info->params.mode == MGSL_MODE_HDLC) { 808 int timeout = (tbuf_bytes(info) * 7) + 1000; 809 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(timeout)); 810 } 811 } 812 813 static int write(struct tty_struct *tty, 814 const unsigned char *buf, int count) 815 { 816 int ret = 0; 817 struct slgt_info *info = tty->driver_data; 818 unsigned long flags; 819 820 if (sanity_check(info, tty->name, "write")) 821 return -EIO; 822 823 DBGINFO(("%s write count=%d\n", info->device_name, count)); 824 825 if (!info->tx_buf || (count > info->max_frame_size)) 826 return -EIO; 827 828 if (!count || tty->stopped || tty->hw_stopped) 829 return 0; 830 831 spin_lock_irqsave(&info->lock, flags); 832 833 if (info->tx_count) { 834 /* send accumulated data from send_char() */ 835 if (!tx_load(info, info->tx_buf, info->tx_count)) 836 goto cleanup; 837 info->tx_count = 0; 838 } 839 840 if (tx_load(info, buf, count)) 841 ret = count; 842 843 cleanup: 844 spin_unlock_irqrestore(&info->lock, flags); 845 DBGINFO(("%s write rc=%d\n", info->device_name, ret)); 846 return ret; 847 } 848 849 static int put_char(struct tty_struct *tty, unsigned char ch) 850 { 851 struct slgt_info *info = tty->driver_data; 852 unsigned long flags; 853 int ret = 0; 854 855 if (sanity_check(info, tty->name, "put_char")) 856 return 0; 857 DBGINFO(("%s put_char(%d)\n", info->device_name, ch)); 858 if (!info->tx_buf) 859 return 0; 860 spin_lock_irqsave(&info->lock,flags); 861 if (info->tx_count < info->max_frame_size) { 862 info->tx_buf[info->tx_count++] = ch; 863 ret = 1; 864 } 865 spin_unlock_irqrestore(&info->lock,flags); 866 return ret; 867 } 868 869 static void send_xchar(struct tty_struct *tty, char ch) 870 { 871 struct slgt_info *info = tty->driver_data; 872 unsigned long flags; 873 874 if (sanity_check(info, tty->name, "send_xchar")) 875 return; 876 DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch)); 877 info->x_char = ch; 878 if (ch) { 879 spin_lock_irqsave(&info->lock,flags); 880 if (!info->tx_enabled) 881 tx_start(info); 882 spin_unlock_irqrestore(&info->lock,flags); 883 } 884 } 885 886 static void wait_until_sent(struct tty_struct *tty, int timeout) 887 { 888 struct slgt_info *info = tty->driver_data; 889 unsigned long orig_jiffies, char_time; 890 891 if (!info ) 892 return; 893 if (sanity_check(info, tty->name, "wait_until_sent")) 894 return; 895 DBGINFO(("%s wait_until_sent entry\n", info->device_name)); 896 if (!(info->port.flags & ASYNC_INITIALIZED)) 897 goto exit; 898 899 orig_jiffies = jiffies; 900 901 /* Set check interval to 1/5 of estimated time to 902 * send a character, and make it at least 1. The check 903 * interval should also be less than the timeout. 904 * Note: use tight timings here to satisfy the NIST-PCTS. 905 */ 906 907 if (info->params.data_rate) { 908 char_time = info->timeout/(32 * 5); 909 if (!char_time) 910 char_time++; 911 } else 912 char_time = 1; 913 914 if (timeout) 915 char_time = min_t(unsigned long, char_time, timeout); 916 917 while (info->tx_active) { 918 msleep_interruptible(jiffies_to_msecs(char_time)); 919 if (signal_pending(current)) 920 break; 921 if (timeout && time_after(jiffies, orig_jiffies + timeout)) 922 break; 923 } 924 exit: 925 DBGINFO(("%s wait_until_sent exit\n", info->device_name)); 926 } 927 928 static int write_room(struct tty_struct *tty) 929 { 930 struct slgt_info *info = tty->driver_data; 931 int ret; 932 933 if (sanity_check(info, tty->name, "write_room")) 934 return 0; 935 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE; 936 DBGINFO(("%s write_room=%d\n", info->device_name, ret)); 937 return ret; 938 } 939 940 static void flush_chars(struct tty_struct *tty) 941 { 942 struct slgt_info *info = tty->driver_data; 943 unsigned long flags; 944 945 if (sanity_check(info, tty->name, "flush_chars")) 946 return; 947 DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count)); 948 949 if (info->tx_count <= 0 || tty->stopped || 950 tty->hw_stopped || !info->tx_buf) 951 return; 952 953 DBGINFO(("%s flush_chars start transmit\n", info->device_name)); 954 955 spin_lock_irqsave(&info->lock,flags); 956 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count)) 957 info->tx_count = 0; 958 spin_unlock_irqrestore(&info->lock,flags); 959 } 960 961 static void flush_buffer(struct tty_struct *tty) 962 { 963 struct slgt_info *info = tty->driver_data; 964 unsigned long flags; 965 966 if (sanity_check(info, tty->name, "flush_buffer")) 967 return; 968 DBGINFO(("%s flush_buffer\n", info->device_name)); 969 970 spin_lock_irqsave(&info->lock, flags); 971 info->tx_count = 0; 972 spin_unlock_irqrestore(&info->lock, flags); 973 974 tty_wakeup(tty); 975 } 976 977 /* 978 * throttle (stop) transmitter 979 */ 980 static void tx_hold(struct tty_struct *tty) 981 { 982 struct slgt_info *info = tty->driver_data; 983 unsigned long flags; 984 985 if (sanity_check(info, tty->name, "tx_hold")) 986 return; 987 DBGINFO(("%s tx_hold\n", info->device_name)); 988 spin_lock_irqsave(&info->lock,flags); 989 if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC) 990 tx_stop(info); 991 spin_unlock_irqrestore(&info->lock,flags); 992 } 993 994 /* 995 * release (start) transmitter 996 */ 997 static void tx_release(struct tty_struct *tty) 998 { 999 struct slgt_info *info = tty->driver_data; 1000 unsigned long flags; 1001 1002 if (sanity_check(info, tty->name, "tx_release")) 1003 return; 1004 DBGINFO(("%s tx_release\n", info->device_name)); 1005 spin_lock_irqsave(&info->lock, flags); 1006 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count)) 1007 info->tx_count = 0; 1008 spin_unlock_irqrestore(&info->lock, flags); 1009 } 1010 1011 /* 1012 * Service an IOCTL request 1013 * 1014 * Arguments 1015 * 1016 * tty pointer to tty instance data 1017 * cmd IOCTL command code 1018 * arg command argument/context 1019 * 1020 * Return 0 if success, otherwise error code 1021 */ 1022 static int ioctl(struct tty_struct *tty, 1023 unsigned int cmd, unsigned long arg) 1024 { 1025 struct slgt_info *info = tty->driver_data; 1026 void __user *argp = (void __user *)arg; 1027 int ret; 1028 1029 if (sanity_check(info, tty->name, "ioctl")) 1030 return -ENODEV; 1031 DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd)); 1032 1033 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) && 1034 (cmd != TIOCMIWAIT)) { 1035 if (tty->flags & (1 << TTY_IO_ERROR)) 1036 return -EIO; 1037 } 1038 1039 switch (cmd) { 1040 case MGSL_IOCWAITEVENT: 1041 return wait_mgsl_event(info, argp); 1042 case TIOCMIWAIT: 1043 return modem_input_wait(info,(int)arg); 1044 case MGSL_IOCSGPIO: 1045 return set_gpio(info, argp); 1046 case MGSL_IOCGGPIO: 1047 return get_gpio(info, argp); 1048 case MGSL_IOCWAITGPIO: 1049 return wait_gpio(info, argp); 1050 case MGSL_IOCGXSYNC: 1051 return get_xsync(info, argp); 1052 case MGSL_IOCSXSYNC: 1053 return set_xsync(info, (int)arg); 1054 case MGSL_IOCGXCTRL: 1055 return get_xctrl(info, argp); 1056 case MGSL_IOCSXCTRL: 1057 return set_xctrl(info, (int)arg); 1058 } 1059 mutex_lock(&info->port.mutex); 1060 switch (cmd) { 1061 case MGSL_IOCGPARAMS: 1062 ret = get_params(info, argp); 1063 break; 1064 case MGSL_IOCSPARAMS: 1065 ret = set_params(info, argp); 1066 break; 1067 case MGSL_IOCGTXIDLE: 1068 ret = get_txidle(info, argp); 1069 break; 1070 case MGSL_IOCSTXIDLE: 1071 ret = set_txidle(info, (int)arg); 1072 break; 1073 case MGSL_IOCTXENABLE: 1074 ret = tx_enable(info, (int)arg); 1075 break; 1076 case MGSL_IOCRXENABLE: 1077 ret = rx_enable(info, (int)arg); 1078 break; 1079 case MGSL_IOCTXABORT: 1080 ret = tx_abort(info); 1081 break; 1082 case MGSL_IOCGSTATS: 1083 ret = get_stats(info, argp); 1084 break; 1085 case MGSL_IOCGIF: 1086 ret = get_interface(info, argp); 1087 break; 1088 case MGSL_IOCSIF: 1089 ret = set_interface(info,(int)arg); 1090 break; 1091 default: 1092 ret = -ENOIOCTLCMD; 1093 } 1094 mutex_unlock(&info->port.mutex); 1095 return ret; 1096 } 1097 1098 static int get_icount(struct tty_struct *tty, 1099 struct serial_icounter_struct *icount) 1100 1101 { 1102 struct slgt_info *info = tty->driver_data; 1103 struct mgsl_icount cnow; /* kernel counter temps */ 1104 unsigned long flags; 1105 1106 spin_lock_irqsave(&info->lock,flags); 1107 cnow = info->icount; 1108 spin_unlock_irqrestore(&info->lock,flags); 1109 1110 icount->cts = cnow.cts; 1111 icount->dsr = cnow.dsr; 1112 icount->rng = cnow.rng; 1113 icount->dcd = cnow.dcd; 1114 icount->rx = cnow.rx; 1115 icount->tx = cnow.tx; 1116 icount->frame = cnow.frame; 1117 icount->overrun = cnow.overrun; 1118 icount->parity = cnow.parity; 1119 icount->brk = cnow.brk; 1120 icount->buf_overrun = cnow.buf_overrun; 1121 1122 return 0; 1123 } 1124 1125 /* 1126 * support for 32 bit ioctl calls on 64 bit systems 1127 */ 1128 #ifdef CONFIG_COMPAT 1129 static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params) 1130 { 1131 struct MGSL_PARAMS32 tmp_params; 1132 1133 DBGINFO(("%s get_params32\n", info->device_name)); 1134 memset(&tmp_params, 0, sizeof(tmp_params)); 1135 tmp_params.mode = (compat_ulong_t)info->params.mode; 1136 tmp_params.loopback = info->params.loopback; 1137 tmp_params.flags = info->params.flags; 1138 tmp_params.encoding = info->params.encoding; 1139 tmp_params.clock_speed = (compat_ulong_t)info->params.clock_speed; 1140 tmp_params.addr_filter = info->params.addr_filter; 1141 tmp_params.crc_type = info->params.crc_type; 1142 tmp_params.preamble_length = info->params.preamble_length; 1143 tmp_params.preamble = info->params.preamble; 1144 tmp_params.data_rate = (compat_ulong_t)info->params.data_rate; 1145 tmp_params.data_bits = info->params.data_bits; 1146 tmp_params.stop_bits = info->params.stop_bits; 1147 tmp_params.parity = info->params.parity; 1148 if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32))) 1149 return -EFAULT; 1150 return 0; 1151 } 1152 1153 static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params) 1154 { 1155 struct MGSL_PARAMS32 tmp_params; 1156 1157 DBGINFO(("%s set_params32\n", info->device_name)); 1158 if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32))) 1159 return -EFAULT; 1160 1161 spin_lock(&info->lock); 1162 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) { 1163 info->base_clock = tmp_params.clock_speed; 1164 } else { 1165 info->params.mode = tmp_params.mode; 1166 info->params.loopback = tmp_params.loopback; 1167 info->params.flags = tmp_params.flags; 1168 info->params.encoding = tmp_params.encoding; 1169 info->params.clock_speed = tmp_params.clock_speed; 1170 info->params.addr_filter = tmp_params.addr_filter; 1171 info->params.crc_type = tmp_params.crc_type; 1172 info->params.preamble_length = tmp_params.preamble_length; 1173 info->params.preamble = tmp_params.preamble; 1174 info->params.data_rate = tmp_params.data_rate; 1175 info->params.data_bits = tmp_params.data_bits; 1176 info->params.stop_bits = tmp_params.stop_bits; 1177 info->params.parity = tmp_params.parity; 1178 } 1179 spin_unlock(&info->lock); 1180 1181 program_hw(info); 1182 1183 return 0; 1184 } 1185 1186 static long slgt_compat_ioctl(struct tty_struct *tty, 1187 unsigned int cmd, unsigned long arg) 1188 { 1189 struct slgt_info *info = tty->driver_data; 1190 int rc = -ENOIOCTLCMD; 1191 1192 if (sanity_check(info, tty->name, "compat_ioctl")) 1193 return -ENODEV; 1194 DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd)); 1195 1196 switch (cmd) { 1197 1198 case MGSL_IOCSPARAMS32: 1199 rc = set_params32(info, compat_ptr(arg)); 1200 break; 1201 1202 case MGSL_IOCGPARAMS32: 1203 rc = get_params32(info, compat_ptr(arg)); 1204 break; 1205 1206 case MGSL_IOCGPARAMS: 1207 case MGSL_IOCSPARAMS: 1208 case MGSL_IOCGTXIDLE: 1209 case MGSL_IOCGSTATS: 1210 case MGSL_IOCWAITEVENT: 1211 case MGSL_IOCGIF: 1212 case MGSL_IOCSGPIO: 1213 case MGSL_IOCGGPIO: 1214 case MGSL_IOCWAITGPIO: 1215 case MGSL_IOCGXSYNC: 1216 case MGSL_IOCGXCTRL: 1217 case MGSL_IOCSTXIDLE: 1218 case MGSL_IOCTXENABLE: 1219 case MGSL_IOCRXENABLE: 1220 case MGSL_IOCTXABORT: 1221 case TIOCMIWAIT: 1222 case MGSL_IOCSIF: 1223 case MGSL_IOCSXSYNC: 1224 case MGSL_IOCSXCTRL: 1225 rc = ioctl(tty, cmd, arg); 1226 break; 1227 } 1228 1229 DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc)); 1230 return rc; 1231 } 1232 #else 1233 #define slgt_compat_ioctl NULL 1234 #endif /* ifdef CONFIG_COMPAT */ 1235 1236 /* 1237 * proc fs support 1238 */ 1239 static inline void line_info(struct seq_file *m, struct slgt_info *info) 1240 { 1241 char stat_buf[30]; 1242 unsigned long flags; 1243 1244 seq_printf(m, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n", 1245 info->device_name, info->phys_reg_addr, 1246 info->irq_level, info->max_frame_size); 1247 1248 /* output current serial signal states */ 1249 spin_lock_irqsave(&info->lock,flags); 1250 get_signals(info); 1251 spin_unlock_irqrestore(&info->lock,flags); 1252 1253 stat_buf[0] = 0; 1254 stat_buf[1] = 0; 1255 if (info->signals & SerialSignal_RTS) 1256 strcat(stat_buf, "|RTS"); 1257 if (info->signals & SerialSignal_CTS) 1258 strcat(stat_buf, "|CTS"); 1259 if (info->signals & SerialSignal_DTR) 1260 strcat(stat_buf, "|DTR"); 1261 if (info->signals & SerialSignal_DSR) 1262 strcat(stat_buf, "|DSR"); 1263 if (info->signals & SerialSignal_DCD) 1264 strcat(stat_buf, "|CD"); 1265 if (info->signals & SerialSignal_RI) 1266 strcat(stat_buf, "|RI"); 1267 1268 if (info->params.mode != MGSL_MODE_ASYNC) { 1269 seq_printf(m, "\tHDLC txok:%d rxok:%d", 1270 info->icount.txok, info->icount.rxok); 1271 if (info->icount.txunder) 1272 seq_printf(m, " txunder:%d", info->icount.txunder); 1273 if (info->icount.txabort) 1274 seq_printf(m, " txabort:%d", info->icount.txabort); 1275 if (info->icount.rxshort) 1276 seq_printf(m, " rxshort:%d", info->icount.rxshort); 1277 if (info->icount.rxlong) 1278 seq_printf(m, " rxlong:%d", info->icount.rxlong); 1279 if (info->icount.rxover) 1280 seq_printf(m, " rxover:%d", info->icount.rxover); 1281 if (info->icount.rxcrc) 1282 seq_printf(m, " rxcrc:%d", info->icount.rxcrc); 1283 } else { 1284 seq_printf(m, "\tASYNC tx:%d rx:%d", 1285 info->icount.tx, info->icount.rx); 1286 if (info->icount.frame) 1287 seq_printf(m, " fe:%d", info->icount.frame); 1288 if (info->icount.parity) 1289 seq_printf(m, " pe:%d", info->icount.parity); 1290 if (info->icount.brk) 1291 seq_printf(m, " brk:%d", info->icount.brk); 1292 if (info->icount.overrun) 1293 seq_printf(m, " oe:%d", info->icount.overrun); 1294 } 1295 1296 /* Append serial signal status to end */ 1297 seq_printf(m, " %s\n", stat_buf+1); 1298 1299 seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n", 1300 info->tx_active,info->bh_requested,info->bh_running, 1301 info->pending_bh); 1302 } 1303 1304 /* Called to print information about devices 1305 */ 1306 static int synclink_gt_proc_show(struct seq_file *m, void *v) 1307 { 1308 struct slgt_info *info; 1309 1310 seq_puts(m, "synclink_gt driver\n"); 1311 1312 info = slgt_device_list; 1313 while( info ) { 1314 line_info(m, info); 1315 info = info->next_device; 1316 } 1317 return 0; 1318 } 1319 1320 static int synclink_gt_proc_open(struct inode *inode, struct file *file) 1321 { 1322 return single_open(file, synclink_gt_proc_show, NULL); 1323 } 1324 1325 static const struct file_operations synclink_gt_proc_fops = { 1326 .owner = THIS_MODULE, 1327 .open = synclink_gt_proc_open, 1328 .read = seq_read, 1329 .llseek = seq_lseek, 1330 .release = single_release, 1331 }; 1332 1333 /* 1334 * return count of bytes in transmit buffer 1335 */ 1336 static int chars_in_buffer(struct tty_struct *tty) 1337 { 1338 struct slgt_info *info = tty->driver_data; 1339 int count; 1340 if (sanity_check(info, tty->name, "chars_in_buffer")) 1341 return 0; 1342 count = tbuf_bytes(info); 1343 DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, count)); 1344 return count; 1345 } 1346 1347 /* 1348 * signal remote device to throttle send data (our receive data) 1349 */ 1350 static void throttle(struct tty_struct * tty) 1351 { 1352 struct slgt_info *info = tty->driver_data; 1353 unsigned long flags; 1354 1355 if (sanity_check(info, tty->name, "throttle")) 1356 return; 1357 DBGINFO(("%s throttle\n", info->device_name)); 1358 if (I_IXOFF(tty)) 1359 send_xchar(tty, STOP_CHAR(tty)); 1360 if (C_CRTSCTS(tty)) { 1361 spin_lock_irqsave(&info->lock,flags); 1362 info->signals &= ~SerialSignal_RTS; 1363 set_signals(info); 1364 spin_unlock_irqrestore(&info->lock,flags); 1365 } 1366 } 1367 1368 /* 1369 * signal remote device to stop throttling send data (our receive data) 1370 */ 1371 static void unthrottle(struct tty_struct * tty) 1372 { 1373 struct slgt_info *info = tty->driver_data; 1374 unsigned long flags; 1375 1376 if (sanity_check(info, tty->name, "unthrottle")) 1377 return; 1378 DBGINFO(("%s unthrottle\n", info->device_name)); 1379 if (I_IXOFF(tty)) { 1380 if (info->x_char) 1381 info->x_char = 0; 1382 else 1383 send_xchar(tty, START_CHAR(tty)); 1384 } 1385 if (C_CRTSCTS(tty)) { 1386 spin_lock_irqsave(&info->lock,flags); 1387 info->signals |= SerialSignal_RTS; 1388 set_signals(info); 1389 spin_unlock_irqrestore(&info->lock,flags); 1390 } 1391 } 1392 1393 /* 1394 * set or clear transmit break condition 1395 * break_state -1=set break condition, 0=clear 1396 */ 1397 static int set_break(struct tty_struct *tty, int break_state) 1398 { 1399 struct slgt_info *info = tty->driver_data; 1400 unsigned short value; 1401 unsigned long flags; 1402 1403 if (sanity_check(info, tty->name, "set_break")) 1404 return -EINVAL; 1405 DBGINFO(("%s set_break(%d)\n", info->device_name, break_state)); 1406 1407 spin_lock_irqsave(&info->lock,flags); 1408 value = rd_reg16(info, TCR); 1409 if (break_state == -1) 1410 value |= BIT6; 1411 else 1412 value &= ~BIT6; 1413 wr_reg16(info, TCR, value); 1414 spin_unlock_irqrestore(&info->lock,flags); 1415 return 0; 1416 } 1417 1418 #if SYNCLINK_GENERIC_HDLC 1419 1420 /** 1421 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.) 1422 * set encoding and frame check sequence (FCS) options 1423 * 1424 * dev pointer to network device structure 1425 * encoding serial encoding setting 1426 * parity FCS setting 1427 * 1428 * returns 0 if success, otherwise error code 1429 */ 1430 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding, 1431 unsigned short parity) 1432 { 1433 struct slgt_info *info = dev_to_port(dev); 1434 unsigned char new_encoding; 1435 unsigned short new_crctype; 1436 1437 /* return error if TTY interface open */ 1438 if (info->port.count) 1439 return -EBUSY; 1440 1441 DBGINFO(("%s hdlcdev_attach\n", info->device_name)); 1442 1443 switch (encoding) 1444 { 1445 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break; 1446 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break; 1447 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break; 1448 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break; 1449 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break; 1450 default: return -EINVAL; 1451 } 1452 1453 switch (parity) 1454 { 1455 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break; 1456 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break; 1457 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break; 1458 default: return -EINVAL; 1459 } 1460 1461 info->params.encoding = new_encoding; 1462 info->params.crc_type = new_crctype; 1463 1464 /* if network interface up, reprogram hardware */ 1465 if (info->netcount) 1466 program_hw(info); 1467 1468 return 0; 1469 } 1470 1471 /** 1472 * called by generic HDLC layer to send frame 1473 * 1474 * skb socket buffer containing HDLC frame 1475 * dev pointer to network device structure 1476 */ 1477 static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb, 1478 struct net_device *dev) 1479 { 1480 struct slgt_info *info = dev_to_port(dev); 1481 unsigned long flags; 1482 1483 DBGINFO(("%s hdlc_xmit\n", dev->name)); 1484 1485 if (!skb->len) 1486 return NETDEV_TX_OK; 1487 1488 /* stop sending until this frame completes */ 1489 netif_stop_queue(dev); 1490 1491 /* update network statistics */ 1492 dev->stats.tx_packets++; 1493 dev->stats.tx_bytes += skb->len; 1494 1495 /* save start time for transmit timeout detection */ 1496 dev->trans_start = jiffies; 1497 1498 spin_lock_irqsave(&info->lock, flags); 1499 tx_load(info, skb->data, skb->len); 1500 spin_unlock_irqrestore(&info->lock, flags); 1501 1502 /* done with socket buffer, so free it */ 1503 dev_kfree_skb(skb); 1504 1505 return NETDEV_TX_OK; 1506 } 1507 1508 /** 1509 * called by network layer when interface enabled 1510 * claim resources and initialize hardware 1511 * 1512 * dev pointer to network device structure 1513 * 1514 * returns 0 if success, otherwise error code 1515 */ 1516 static int hdlcdev_open(struct net_device *dev) 1517 { 1518 struct slgt_info *info = dev_to_port(dev); 1519 int rc; 1520 unsigned long flags; 1521 1522 if (!try_module_get(THIS_MODULE)) 1523 return -EBUSY; 1524 1525 DBGINFO(("%s hdlcdev_open\n", dev->name)); 1526 1527 /* generic HDLC layer open processing */ 1528 rc = hdlc_open(dev); 1529 if (rc) 1530 return rc; 1531 1532 /* arbitrate between network and tty opens */ 1533 spin_lock_irqsave(&info->netlock, flags); 1534 if (info->port.count != 0 || info->netcount != 0) { 1535 DBGINFO(("%s hdlc_open busy\n", dev->name)); 1536 spin_unlock_irqrestore(&info->netlock, flags); 1537 return -EBUSY; 1538 } 1539 info->netcount=1; 1540 spin_unlock_irqrestore(&info->netlock, flags); 1541 1542 /* claim resources and init adapter */ 1543 if ((rc = startup(info)) != 0) { 1544 spin_lock_irqsave(&info->netlock, flags); 1545 info->netcount=0; 1546 spin_unlock_irqrestore(&info->netlock, flags); 1547 return rc; 1548 } 1549 1550 /* assert RTS and DTR, apply hardware settings */ 1551 info->signals |= SerialSignal_RTS | SerialSignal_DTR; 1552 program_hw(info); 1553 1554 /* enable network layer transmit */ 1555 dev->trans_start = jiffies; 1556 netif_start_queue(dev); 1557 1558 /* inform generic HDLC layer of current DCD status */ 1559 spin_lock_irqsave(&info->lock, flags); 1560 get_signals(info); 1561 spin_unlock_irqrestore(&info->lock, flags); 1562 if (info->signals & SerialSignal_DCD) 1563 netif_carrier_on(dev); 1564 else 1565 netif_carrier_off(dev); 1566 return 0; 1567 } 1568 1569 /** 1570 * called by network layer when interface is disabled 1571 * shutdown hardware and release resources 1572 * 1573 * dev pointer to network device structure 1574 * 1575 * returns 0 if success, otherwise error code 1576 */ 1577 static int hdlcdev_close(struct net_device *dev) 1578 { 1579 struct slgt_info *info = dev_to_port(dev); 1580 unsigned long flags; 1581 1582 DBGINFO(("%s hdlcdev_close\n", dev->name)); 1583 1584 netif_stop_queue(dev); 1585 1586 /* shutdown adapter and release resources */ 1587 shutdown(info); 1588 1589 hdlc_close(dev); 1590 1591 spin_lock_irqsave(&info->netlock, flags); 1592 info->netcount=0; 1593 spin_unlock_irqrestore(&info->netlock, flags); 1594 1595 module_put(THIS_MODULE); 1596 return 0; 1597 } 1598 1599 /** 1600 * called by network layer to process IOCTL call to network device 1601 * 1602 * dev pointer to network device structure 1603 * ifr pointer to network interface request structure 1604 * cmd IOCTL command code 1605 * 1606 * returns 0 if success, otherwise error code 1607 */ 1608 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 1609 { 1610 const size_t size = sizeof(sync_serial_settings); 1611 sync_serial_settings new_line; 1612 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync; 1613 struct slgt_info *info = dev_to_port(dev); 1614 unsigned int flags; 1615 1616 DBGINFO(("%s hdlcdev_ioctl\n", dev->name)); 1617 1618 /* return error if TTY interface open */ 1619 if (info->port.count) 1620 return -EBUSY; 1621 1622 if (cmd != SIOCWANDEV) 1623 return hdlc_ioctl(dev, ifr, cmd); 1624 1625 memset(&new_line, 0, sizeof(new_line)); 1626 1627 switch(ifr->ifr_settings.type) { 1628 case IF_GET_IFACE: /* return current sync_serial_settings */ 1629 1630 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL; 1631 if (ifr->ifr_settings.size < size) { 1632 ifr->ifr_settings.size = size; /* data size wanted */ 1633 return -ENOBUFS; 1634 } 1635 1636 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL | 1637 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN | 1638 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL | 1639 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); 1640 1641 switch (flags){ 1642 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break; 1643 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break; 1644 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break; 1645 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break; 1646 default: new_line.clock_type = CLOCK_DEFAULT; 1647 } 1648 1649 new_line.clock_rate = info->params.clock_speed; 1650 new_line.loopback = info->params.loopback ? 1:0; 1651 1652 if (copy_to_user(line, &new_line, size)) 1653 return -EFAULT; 1654 return 0; 1655 1656 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */ 1657 1658 if(!capable(CAP_NET_ADMIN)) 1659 return -EPERM; 1660 if (copy_from_user(&new_line, line, size)) 1661 return -EFAULT; 1662 1663 switch (new_line.clock_type) 1664 { 1665 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break; 1666 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break; 1667 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break; 1668 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break; 1669 case CLOCK_DEFAULT: flags = info->params.flags & 1670 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL | 1671 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN | 1672 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL | 1673 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break; 1674 default: return -EINVAL; 1675 } 1676 1677 if (new_line.loopback != 0 && new_line.loopback != 1) 1678 return -EINVAL; 1679 1680 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL | 1681 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN | 1682 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL | 1683 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); 1684 info->params.flags |= flags; 1685 1686 info->params.loopback = new_line.loopback; 1687 1688 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG)) 1689 info->params.clock_speed = new_line.clock_rate; 1690 else 1691 info->params.clock_speed = 0; 1692 1693 /* if network interface up, reprogram hardware */ 1694 if (info->netcount) 1695 program_hw(info); 1696 return 0; 1697 1698 default: 1699 return hdlc_ioctl(dev, ifr, cmd); 1700 } 1701 } 1702 1703 /** 1704 * called by network layer when transmit timeout is detected 1705 * 1706 * dev pointer to network device structure 1707 */ 1708 static void hdlcdev_tx_timeout(struct net_device *dev) 1709 { 1710 struct slgt_info *info = dev_to_port(dev); 1711 unsigned long flags; 1712 1713 DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name)); 1714 1715 dev->stats.tx_errors++; 1716 dev->stats.tx_aborted_errors++; 1717 1718 spin_lock_irqsave(&info->lock,flags); 1719 tx_stop(info); 1720 spin_unlock_irqrestore(&info->lock,flags); 1721 1722 netif_wake_queue(dev); 1723 } 1724 1725 /** 1726 * called by device driver when transmit completes 1727 * reenable network layer transmit if stopped 1728 * 1729 * info pointer to device instance information 1730 */ 1731 static void hdlcdev_tx_done(struct slgt_info *info) 1732 { 1733 if (netif_queue_stopped(info->netdev)) 1734 netif_wake_queue(info->netdev); 1735 } 1736 1737 /** 1738 * called by device driver when frame received 1739 * pass frame to network layer 1740 * 1741 * info pointer to device instance information 1742 * buf pointer to buffer contianing frame data 1743 * size count of data bytes in buf 1744 */ 1745 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size) 1746 { 1747 struct sk_buff *skb = dev_alloc_skb(size); 1748 struct net_device *dev = info->netdev; 1749 1750 DBGINFO(("%s hdlcdev_rx\n", dev->name)); 1751 1752 if (skb == NULL) { 1753 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name)); 1754 dev->stats.rx_dropped++; 1755 return; 1756 } 1757 1758 memcpy(skb_put(skb, size), buf, size); 1759 1760 skb->protocol = hdlc_type_trans(skb, dev); 1761 1762 dev->stats.rx_packets++; 1763 dev->stats.rx_bytes += size; 1764 1765 netif_rx(skb); 1766 } 1767 1768 static const struct net_device_ops hdlcdev_ops = { 1769 .ndo_open = hdlcdev_open, 1770 .ndo_stop = hdlcdev_close, 1771 .ndo_change_mtu = hdlc_change_mtu, 1772 .ndo_start_xmit = hdlc_start_xmit, 1773 .ndo_do_ioctl = hdlcdev_ioctl, 1774 .ndo_tx_timeout = hdlcdev_tx_timeout, 1775 }; 1776 1777 /** 1778 * called by device driver when adding device instance 1779 * do generic HDLC initialization 1780 * 1781 * info pointer to device instance information 1782 * 1783 * returns 0 if success, otherwise error code 1784 */ 1785 static int hdlcdev_init(struct slgt_info *info) 1786 { 1787 int rc; 1788 struct net_device *dev; 1789 hdlc_device *hdlc; 1790 1791 /* allocate and initialize network and HDLC layer objects */ 1792 1793 dev = alloc_hdlcdev(info); 1794 if (!dev) { 1795 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name); 1796 return -ENOMEM; 1797 } 1798 1799 /* for network layer reporting purposes only */ 1800 dev->mem_start = info->phys_reg_addr; 1801 dev->mem_end = info->phys_reg_addr + SLGT_REG_SIZE - 1; 1802 dev->irq = info->irq_level; 1803 1804 /* network layer callbacks and settings */ 1805 dev->netdev_ops = &hdlcdev_ops; 1806 dev->watchdog_timeo = 10 * HZ; 1807 dev->tx_queue_len = 50; 1808 1809 /* generic HDLC layer callbacks and settings */ 1810 hdlc = dev_to_hdlc(dev); 1811 hdlc->attach = hdlcdev_attach; 1812 hdlc->xmit = hdlcdev_xmit; 1813 1814 /* register objects with HDLC layer */ 1815 rc = register_hdlc_device(dev); 1816 if (rc) { 1817 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__); 1818 free_netdev(dev); 1819 return rc; 1820 } 1821 1822 info->netdev = dev; 1823 return 0; 1824 } 1825 1826 /** 1827 * called by device driver when removing device instance 1828 * do generic HDLC cleanup 1829 * 1830 * info pointer to device instance information 1831 */ 1832 static void hdlcdev_exit(struct slgt_info *info) 1833 { 1834 unregister_hdlc_device(info->netdev); 1835 free_netdev(info->netdev); 1836 info->netdev = NULL; 1837 } 1838 1839 #endif /* ifdef CONFIG_HDLC */ 1840 1841 /* 1842 * get async data from rx DMA buffers 1843 */ 1844 static void rx_async(struct slgt_info *info) 1845 { 1846 struct mgsl_icount *icount = &info->icount; 1847 unsigned int start, end; 1848 unsigned char *p; 1849 unsigned char status; 1850 struct slgt_desc *bufs = info->rbufs; 1851 int i, count; 1852 int chars = 0; 1853 int stat; 1854 unsigned char ch; 1855 1856 start = end = info->rbuf_current; 1857 1858 while(desc_complete(bufs[end])) { 1859 count = desc_count(bufs[end]) - info->rbuf_index; 1860 p = bufs[end].buf + info->rbuf_index; 1861 1862 DBGISR(("%s rx_async count=%d\n", info->device_name, count)); 1863 DBGDATA(info, p, count, "rx"); 1864 1865 for(i=0 ; i < count; i+=2, p+=2) { 1866 ch = *p; 1867 icount->rx++; 1868 1869 stat = 0; 1870 1871 status = *(p + 1) & (BIT1 + BIT0); 1872 if (status) { 1873 if (status & BIT1) 1874 icount->parity++; 1875 else if (status & BIT0) 1876 icount->frame++; 1877 /* discard char if tty control flags say so */ 1878 if (status & info->ignore_status_mask) 1879 continue; 1880 if (status & BIT1) 1881 stat = TTY_PARITY; 1882 else if (status & BIT0) 1883 stat = TTY_FRAME; 1884 } 1885 tty_insert_flip_char(&info->port, ch, stat); 1886 chars++; 1887 } 1888 1889 if (i < count) { 1890 /* receive buffer not completed */ 1891 info->rbuf_index += i; 1892 mod_timer(&info->rx_timer, jiffies + 1); 1893 break; 1894 } 1895 1896 info->rbuf_index = 0; 1897 free_rbufs(info, end, end); 1898 1899 if (++end == info->rbuf_count) 1900 end = 0; 1901 1902 /* if entire list searched then no frame available */ 1903 if (end == start) 1904 break; 1905 } 1906 1907 if (chars) 1908 tty_flip_buffer_push(&info->port); 1909 } 1910 1911 /* 1912 * return next bottom half action to perform 1913 */ 1914 static int bh_action(struct slgt_info *info) 1915 { 1916 unsigned long flags; 1917 int rc; 1918 1919 spin_lock_irqsave(&info->lock,flags); 1920 1921 if (info->pending_bh & BH_RECEIVE) { 1922 info->pending_bh &= ~BH_RECEIVE; 1923 rc = BH_RECEIVE; 1924 } else if (info->pending_bh & BH_TRANSMIT) { 1925 info->pending_bh &= ~BH_TRANSMIT; 1926 rc = BH_TRANSMIT; 1927 } else if (info->pending_bh & BH_STATUS) { 1928 info->pending_bh &= ~BH_STATUS; 1929 rc = BH_STATUS; 1930 } else { 1931 /* Mark BH routine as complete */ 1932 info->bh_running = false; 1933 info->bh_requested = false; 1934 rc = 0; 1935 } 1936 1937 spin_unlock_irqrestore(&info->lock,flags); 1938 1939 return rc; 1940 } 1941 1942 /* 1943 * perform bottom half processing 1944 */ 1945 static void bh_handler(struct work_struct *work) 1946 { 1947 struct slgt_info *info = container_of(work, struct slgt_info, task); 1948 int action; 1949 1950 info->bh_running = true; 1951 1952 while((action = bh_action(info))) { 1953 switch (action) { 1954 case BH_RECEIVE: 1955 DBGBH(("%s bh receive\n", info->device_name)); 1956 switch(info->params.mode) { 1957 case MGSL_MODE_ASYNC: 1958 rx_async(info); 1959 break; 1960 case MGSL_MODE_HDLC: 1961 while(rx_get_frame(info)); 1962 break; 1963 case MGSL_MODE_RAW: 1964 case MGSL_MODE_MONOSYNC: 1965 case MGSL_MODE_BISYNC: 1966 case MGSL_MODE_XSYNC: 1967 while(rx_get_buf(info)); 1968 break; 1969 } 1970 /* restart receiver if rx DMA buffers exhausted */ 1971 if (info->rx_restart) 1972 rx_start(info); 1973 break; 1974 case BH_TRANSMIT: 1975 bh_transmit(info); 1976 break; 1977 case BH_STATUS: 1978 DBGBH(("%s bh status\n", info->device_name)); 1979 info->ri_chkcount = 0; 1980 info->dsr_chkcount = 0; 1981 info->dcd_chkcount = 0; 1982 info->cts_chkcount = 0; 1983 break; 1984 default: 1985 DBGBH(("%s unknown action\n", info->device_name)); 1986 break; 1987 } 1988 } 1989 DBGBH(("%s bh_handler exit\n", info->device_name)); 1990 } 1991 1992 static void bh_transmit(struct slgt_info *info) 1993 { 1994 struct tty_struct *tty = info->port.tty; 1995 1996 DBGBH(("%s bh_transmit\n", info->device_name)); 1997 if (tty) 1998 tty_wakeup(tty); 1999 } 2000 2001 static void dsr_change(struct slgt_info *info, unsigned short status) 2002 { 2003 if (status & BIT3) { 2004 info->signals |= SerialSignal_DSR; 2005 info->input_signal_events.dsr_up++; 2006 } else { 2007 info->signals &= ~SerialSignal_DSR; 2008 info->input_signal_events.dsr_down++; 2009 } 2010 DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals)); 2011 if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) { 2012 slgt_irq_off(info, IRQ_DSR); 2013 return; 2014 } 2015 info->icount.dsr++; 2016 wake_up_interruptible(&info->status_event_wait_q); 2017 wake_up_interruptible(&info->event_wait_q); 2018 info->pending_bh |= BH_STATUS; 2019 } 2020 2021 static void cts_change(struct slgt_info *info, unsigned short status) 2022 { 2023 if (status & BIT2) { 2024 info->signals |= SerialSignal_CTS; 2025 info->input_signal_events.cts_up++; 2026 } else { 2027 info->signals &= ~SerialSignal_CTS; 2028 info->input_signal_events.cts_down++; 2029 } 2030 DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals)); 2031 if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) { 2032 slgt_irq_off(info, IRQ_CTS); 2033 return; 2034 } 2035 info->icount.cts++; 2036 wake_up_interruptible(&info->status_event_wait_q); 2037 wake_up_interruptible(&info->event_wait_q); 2038 info->pending_bh |= BH_STATUS; 2039 2040 if (tty_port_cts_enabled(&info->port)) { 2041 if (info->port.tty) { 2042 if (info->port.tty->hw_stopped) { 2043 if (info->signals & SerialSignal_CTS) { 2044 info->port.tty->hw_stopped = 0; 2045 info->pending_bh |= BH_TRANSMIT; 2046 return; 2047 } 2048 } else { 2049 if (!(info->signals & SerialSignal_CTS)) 2050 info->port.tty->hw_stopped = 1; 2051 } 2052 } 2053 } 2054 } 2055 2056 static void dcd_change(struct slgt_info *info, unsigned short status) 2057 { 2058 if (status & BIT1) { 2059 info->signals |= SerialSignal_DCD; 2060 info->input_signal_events.dcd_up++; 2061 } else { 2062 info->signals &= ~SerialSignal_DCD; 2063 info->input_signal_events.dcd_down++; 2064 } 2065 DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals)); 2066 if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) { 2067 slgt_irq_off(info, IRQ_DCD); 2068 return; 2069 } 2070 info->icount.dcd++; 2071 #if SYNCLINK_GENERIC_HDLC 2072 if (info->netcount) { 2073 if (info->signals & SerialSignal_DCD) 2074 netif_carrier_on(info->netdev); 2075 else 2076 netif_carrier_off(info->netdev); 2077 } 2078 #endif 2079 wake_up_interruptible(&info->status_event_wait_q); 2080 wake_up_interruptible(&info->event_wait_q); 2081 info->pending_bh |= BH_STATUS; 2082 2083 if (info->port.flags & ASYNC_CHECK_CD) { 2084 if (info->signals & SerialSignal_DCD) 2085 wake_up_interruptible(&info->port.open_wait); 2086 else { 2087 if (info->port.tty) 2088 tty_hangup(info->port.tty); 2089 } 2090 } 2091 } 2092 2093 static void ri_change(struct slgt_info *info, unsigned short status) 2094 { 2095 if (status & BIT0) { 2096 info->signals |= SerialSignal_RI; 2097 info->input_signal_events.ri_up++; 2098 } else { 2099 info->signals &= ~SerialSignal_RI; 2100 info->input_signal_events.ri_down++; 2101 } 2102 DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals)); 2103 if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) { 2104 slgt_irq_off(info, IRQ_RI); 2105 return; 2106 } 2107 info->icount.rng++; 2108 wake_up_interruptible(&info->status_event_wait_q); 2109 wake_up_interruptible(&info->event_wait_q); 2110 info->pending_bh |= BH_STATUS; 2111 } 2112 2113 static void isr_rxdata(struct slgt_info *info) 2114 { 2115 unsigned int count = info->rbuf_fill_count; 2116 unsigned int i = info->rbuf_fill_index; 2117 unsigned short reg; 2118 2119 while (rd_reg16(info, SSR) & IRQ_RXDATA) { 2120 reg = rd_reg16(info, RDR); 2121 DBGISR(("isr_rxdata %s RDR=%04X\n", info->device_name, reg)); 2122 if (desc_complete(info->rbufs[i])) { 2123 /* all buffers full */ 2124 rx_stop(info); 2125 info->rx_restart = 1; 2126 continue; 2127 } 2128 info->rbufs[i].buf[count++] = (unsigned char)reg; 2129 /* async mode saves status byte to buffer for each data byte */ 2130 if (info->params.mode == MGSL_MODE_ASYNC) 2131 info->rbufs[i].buf[count++] = (unsigned char)(reg >> 8); 2132 if (count == info->rbuf_fill_level || (reg & BIT10)) { 2133 /* buffer full or end of frame */ 2134 set_desc_count(info->rbufs[i], count); 2135 set_desc_status(info->rbufs[i], BIT15 | (reg >> 8)); 2136 info->rbuf_fill_count = count = 0; 2137 if (++i == info->rbuf_count) 2138 i = 0; 2139 info->pending_bh |= BH_RECEIVE; 2140 } 2141 } 2142 2143 info->rbuf_fill_index = i; 2144 info->rbuf_fill_count = count; 2145 } 2146 2147 static void isr_serial(struct slgt_info *info) 2148 { 2149 unsigned short status = rd_reg16(info, SSR); 2150 2151 DBGISR(("%s isr_serial status=%04X\n", info->device_name, status)); 2152 2153 wr_reg16(info, SSR, status); /* clear pending */ 2154 2155 info->irq_occurred = true; 2156 2157 if (info->params.mode == MGSL_MODE_ASYNC) { 2158 if (status & IRQ_TXIDLE) { 2159 if (info->tx_active) 2160 isr_txeom(info, status); 2161 } 2162 if (info->rx_pio && (status & IRQ_RXDATA)) 2163 isr_rxdata(info); 2164 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) { 2165 info->icount.brk++; 2166 /* process break detection if tty control allows */ 2167 if (info->port.tty) { 2168 if (!(status & info->ignore_status_mask)) { 2169 if (info->read_status_mask & MASK_BREAK) { 2170 tty_insert_flip_char(&info->port, 0, TTY_BREAK); 2171 if (info->port.flags & ASYNC_SAK) 2172 do_SAK(info->port.tty); 2173 } 2174 } 2175 } 2176 } 2177 } else { 2178 if (status & (IRQ_TXIDLE + IRQ_TXUNDER)) 2179 isr_txeom(info, status); 2180 if (info->rx_pio && (status & IRQ_RXDATA)) 2181 isr_rxdata(info); 2182 if (status & IRQ_RXIDLE) { 2183 if (status & RXIDLE) 2184 info->icount.rxidle++; 2185 else 2186 info->icount.exithunt++; 2187 wake_up_interruptible(&info->event_wait_q); 2188 } 2189 2190 if (status & IRQ_RXOVER) 2191 rx_start(info); 2192 } 2193 2194 if (status & IRQ_DSR) 2195 dsr_change(info, status); 2196 if (status & IRQ_CTS) 2197 cts_change(info, status); 2198 if (status & IRQ_DCD) 2199 dcd_change(info, status); 2200 if (status & IRQ_RI) 2201 ri_change(info, status); 2202 } 2203 2204 static void isr_rdma(struct slgt_info *info) 2205 { 2206 unsigned int status = rd_reg32(info, RDCSR); 2207 2208 DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status)); 2209 2210 /* RDCSR (rx DMA control/status) 2211 * 2212 * 31..07 reserved 2213 * 06 save status byte to DMA buffer 2214 * 05 error 2215 * 04 eol (end of list) 2216 * 03 eob (end of buffer) 2217 * 02 IRQ enable 2218 * 01 reset 2219 * 00 enable 2220 */ 2221 wr_reg32(info, RDCSR, status); /* clear pending */ 2222 2223 if (status & (BIT5 + BIT4)) { 2224 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name)); 2225 info->rx_restart = true; 2226 } 2227 info->pending_bh |= BH_RECEIVE; 2228 } 2229 2230 static void isr_tdma(struct slgt_info *info) 2231 { 2232 unsigned int status = rd_reg32(info, TDCSR); 2233 2234 DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status)); 2235 2236 /* TDCSR (tx DMA control/status) 2237 * 2238 * 31..06 reserved 2239 * 05 error 2240 * 04 eol (end of list) 2241 * 03 eob (end of buffer) 2242 * 02 IRQ enable 2243 * 01 reset 2244 * 00 enable 2245 */ 2246 wr_reg32(info, TDCSR, status); /* clear pending */ 2247 2248 if (status & (BIT5 + BIT4 + BIT3)) { 2249 // another transmit buffer has completed 2250 // run bottom half to get more send data from user 2251 info->pending_bh |= BH_TRANSMIT; 2252 } 2253 } 2254 2255 /* 2256 * return true if there are unsent tx DMA buffers, otherwise false 2257 * 2258 * if there are unsent buffers then info->tbuf_start 2259 * is set to index of first unsent buffer 2260 */ 2261 static bool unsent_tbufs(struct slgt_info *info) 2262 { 2263 unsigned int i = info->tbuf_current; 2264 bool rc = false; 2265 2266 /* 2267 * search backwards from last loaded buffer (precedes tbuf_current) 2268 * for first unsent buffer (desc_count > 0) 2269 */ 2270 2271 do { 2272 if (i) 2273 i--; 2274 else 2275 i = info->tbuf_count - 1; 2276 if (!desc_count(info->tbufs[i])) 2277 break; 2278 info->tbuf_start = i; 2279 rc = true; 2280 } while (i != info->tbuf_current); 2281 2282 return rc; 2283 } 2284 2285 static void isr_txeom(struct slgt_info *info, unsigned short status) 2286 { 2287 DBGISR(("%s txeom status=%04x\n", info->device_name, status)); 2288 2289 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER); 2290 tdma_reset(info); 2291 if (status & IRQ_TXUNDER) { 2292 unsigned short val = rd_reg16(info, TCR); 2293 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */ 2294 wr_reg16(info, TCR, val); /* clear reset bit */ 2295 } 2296 2297 if (info->tx_active) { 2298 if (info->params.mode != MGSL_MODE_ASYNC) { 2299 if (status & IRQ_TXUNDER) 2300 info->icount.txunder++; 2301 else if (status & IRQ_TXIDLE) 2302 info->icount.txok++; 2303 } 2304 2305 if (unsent_tbufs(info)) { 2306 tx_start(info); 2307 update_tx_timer(info); 2308 return; 2309 } 2310 info->tx_active = false; 2311 2312 del_timer(&info->tx_timer); 2313 2314 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) { 2315 info->signals &= ~SerialSignal_RTS; 2316 info->drop_rts_on_tx_done = false; 2317 set_signals(info); 2318 } 2319 2320 #if SYNCLINK_GENERIC_HDLC 2321 if (info->netcount) 2322 hdlcdev_tx_done(info); 2323 else 2324 #endif 2325 { 2326 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) { 2327 tx_stop(info); 2328 return; 2329 } 2330 info->pending_bh |= BH_TRANSMIT; 2331 } 2332 } 2333 } 2334 2335 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state) 2336 { 2337 struct cond_wait *w, *prev; 2338 2339 /* wake processes waiting for specific transitions */ 2340 for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) { 2341 if (w->data & changed) { 2342 w->data = state; 2343 wake_up_interruptible(&w->q); 2344 if (prev != NULL) 2345 prev->next = w->next; 2346 else 2347 info->gpio_wait_q = w->next; 2348 } else 2349 prev = w; 2350 } 2351 } 2352 2353 /* interrupt service routine 2354 * 2355 * irq interrupt number 2356 * dev_id device ID supplied during interrupt registration 2357 */ 2358 static irqreturn_t slgt_interrupt(int dummy, void *dev_id) 2359 { 2360 struct slgt_info *info = dev_id; 2361 unsigned int gsr; 2362 unsigned int i; 2363 2364 DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level)); 2365 2366 while((gsr = rd_reg32(info, GSR) & 0xffffff00)) { 2367 DBGISR(("%s gsr=%08x\n", info->device_name, gsr)); 2368 info->irq_occurred = true; 2369 for(i=0; i < info->port_count ; i++) { 2370 if (info->port_array[i] == NULL) 2371 continue; 2372 spin_lock(&info->port_array[i]->lock); 2373 if (gsr & (BIT8 << i)) 2374 isr_serial(info->port_array[i]); 2375 if (gsr & (BIT16 << (i*2))) 2376 isr_rdma(info->port_array[i]); 2377 if (gsr & (BIT17 << (i*2))) 2378 isr_tdma(info->port_array[i]); 2379 spin_unlock(&info->port_array[i]->lock); 2380 } 2381 } 2382 2383 if (info->gpio_present) { 2384 unsigned int state; 2385 unsigned int changed; 2386 spin_lock(&info->lock); 2387 while ((changed = rd_reg32(info, IOSR)) != 0) { 2388 DBGISR(("%s iosr=%08x\n", info->device_name, changed)); 2389 /* read latched state of GPIO signals */ 2390 state = rd_reg32(info, IOVR); 2391 /* clear pending GPIO interrupt bits */ 2392 wr_reg32(info, IOSR, changed); 2393 for (i=0 ; i < info->port_count ; i++) { 2394 if (info->port_array[i] != NULL) 2395 isr_gpio(info->port_array[i], changed, state); 2396 } 2397 } 2398 spin_unlock(&info->lock); 2399 } 2400 2401 for(i=0; i < info->port_count ; i++) { 2402 struct slgt_info *port = info->port_array[i]; 2403 if (port == NULL) 2404 continue; 2405 spin_lock(&port->lock); 2406 if ((port->port.count || port->netcount) && 2407 port->pending_bh && !port->bh_running && 2408 !port->bh_requested) { 2409 DBGISR(("%s bh queued\n", port->device_name)); 2410 schedule_work(&port->task); 2411 port->bh_requested = true; 2412 } 2413 spin_unlock(&port->lock); 2414 } 2415 2416 DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level)); 2417 return IRQ_HANDLED; 2418 } 2419 2420 static int startup(struct slgt_info *info) 2421 { 2422 DBGINFO(("%s startup\n", info->device_name)); 2423 2424 if (info->port.flags & ASYNC_INITIALIZED) 2425 return 0; 2426 2427 if (!info->tx_buf) { 2428 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL); 2429 if (!info->tx_buf) { 2430 DBGERR(("%s can't allocate tx buffer\n", info->device_name)); 2431 return -ENOMEM; 2432 } 2433 } 2434 2435 info->pending_bh = 0; 2436 2437 memset(&info->icount, 0, sizeof(info->icount)); 2438 2439 /* program hardware for current parameters */ 2440 change_params(info); 2441 2442 if (info->port.tty) 2443 clear_bit(TTY_IO_ERROR, &info->port.tty->flags); 2444 2445 info->port.flags |= ASYNC_INITIALIZED; 2446 2447 return 0; 2448 } 2449 2450 /* 2451 * called by close() and hangup() to shutdown hardware 2452 */ 2453 static void shutdown(struct slgt_info *info) 2454 { 2455 unsigned long flags; 2456 2457 if (!(info->port.flags & ASYNC_INITIALIZED)) 2458 return; 2459 2460 DBGINFO(("%s shutdown\n", info->device_name)); 2461 2462 /* clear status wait queue because status changes */ 2463 /* can't happen after shutting down the hardware */ 2464 wake_up_interruptible(&info->status_event_wait_q); 2465 wake_up_interruptible(&info->event_wait_q); 2466 2467 del_timer_sync(&info->tx_timer); 2468 del_timer_sync(&info->rx_timer); 2469 2470 kfree(info->tx_buf); 2471 info->tx_buf = NULL; 2472 2473 spin_lock_irqsave(&info->lock,flags); 2474 2475 tx_stop(info); 2476 rx_stop(info); 2477 2478 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER); 2479 2480 if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) { 2481 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR); 2482 set_signals(info); 2483 } 2484 2485 flush_cond_wait(&info->gpio_wait_q); 2486 2487 spin_unlock_irqrestore(&info->lock,flags); 2488 2489 if (info->port.tty) 2490 set_bit(TTY_IO_ERROR, &info->port.tty->flags); 2491 2492 info->port.flags &= ~ASYNC_INITIALIZED; 2493 } 2494 2495 static void program_hw(struct slgt_info *info) 2496 { 2497 unsigned long flags; 2498 2499 spin_lock_irqsave(&info->lock,flags); 2500 2501 rx_stop(info); 2502 tx_stop(info); 2503 2504 if (info->params.mode != MGSL_MODE_ASYNC || 2505 info->netcount) 2506 sync_mode(info); 2507 else 2508 async_mode(info); 2509 2510 set_signals(info); 2511 2512 info->dcd_chkcount = 0; 2513 info->cts_chkcount = 0; 2514 info->ri_chkcount = 0; 2515 info->dsr_chkcount = 0; 2516 2517 slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI); 2518 get_signals(info); 2519 2520 if (info->netcount || 2521 (info->port.tty && info->port.tty->termios.c_cflag & CREAD)) 2522 rx_start(info); 2523 2524 spin_unlock_irqrestore(&info->lock,flags); 2525 } 2526 2527 /* 2528 * reconfigure adapter based on new parameters 2529 */ 2530 static void change_params(struct slgt_info *info) 2531 { 2532 unsigned cflag; 2533 int bits_per_char; 2534 2535 if (!info->port.tty) 2536 return; 2537 DBGINFO(("%s change_params\n", info->device_name)); 2538 2539 cflag = info->port.tty->termios.c_cflag; 2540 2541 /* if B0 rate (hangup) specified then negate RTS and DTR */ 2542 /* otherwise assert RTS and DTR */ 2543 if (cflag & CBAUD) 2544 info->signals |= SerialSignal_RTS | SerialSignal_DTR; 2545 else 2546 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR); 2547 2548 /* byte size and parity */ 2549 2550 switch (cflag & CSIZE) { 2551 case CS5: info->params.data_bits = 5; break; 2552 case CS6: info->params.data_bits = 6; break; 2553 case CS7: info->params.data_bits = 7; break; 2554 case CS8: info->params.data_bits = 8; break; 2555 default: info->params.data_bits = 7; break; 2556 } 2557 2558 info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1; 2559 2560 if (cflag & PARENB) 2561 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN; 2562 else 2563 info->params.parity = ASYNC_PARITY_NONE; 2564 2565 /* calculate number of jiffies to transmit a full 2566 * FIFO (32 bytes) at specified data rate 2567 */ 2568 bits_per_char = info->params.data_bits + 2569 info->params.stop_bits + 1; 2570 2571 info->params.data_rate = tty_get_baud_rate(info->port.tty); 2572 2573 if (info->params.data_rate) { 2574 info->timeout = (32*HZ*bits_per_char) / 2575 info->params.data_rate; 2576 } 2577 info->timeout += HZ/50; /* Add .02 seconds of slop */ 2578 2579 if (cflag & CRTSCTS) 2580 info->port.flags |= ASYNC_CTS_FLOW; 2581 else 2582 info->port.flags &= ~ASYNC_CTS_FLOW; 2583 2584 if (cflag & CLOCAL) 2585 info->port.flags &= ~ASYNC_CHECK_CD; 2586 else 2587 info->port.flags |= ASYNC_CHECK_CD; 2588 2589 /* process tty input control flags */ 2590 2591 info->read_status_mask = IRQ_RXOVER; 2592 if (I_INPCK(info->port.tty)) 2593 info->read_status_mask |= MASK_PARITY | MASK_FRAMING; 2594 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty)) 2595 info->read_status_mask |= MASK_BREAK; 2596 if (I_IGNPAR(info->port.tty)) 2597 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING; 2598 if (I_IGNBRK(info->port.tty)) { 2599 info->ignore_status_mask |= MASK_BREAK; 2600 /* If ignoring parity and break indicators, ignore 2601 * overruns too. (For real raw support). 2602 */ 2603 if (I_IGNPAR(info->port.tty)) 2604 info->ignore_status_mask |= MASK_OVERRUN; 2605 } 2606 2607 program_hw(info); 2608 } 2609 2610 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount) 2611 { 2612 DBGINFO(("%s get_stats\n", info->device_name)); 2613 if (!user_icount) { 2614 memset(&info->icount, 0, sizeof(info->icount)); 2615 } else { 2616 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount))) 2617 return -EFAULT; 2618 } 2619 return 0; 2620 } 2621 2622 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params) 2623 { 2624 DBGINFO(("%s get_params\n", info->device_name)); 2625 if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS))) 2626 return -EFAULT; 2627 return 0; 2628 } 2629 2630 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params) 2631 { 2632 unsigned long flags; 2633 MGSL_PARAMS tmp_params; 2634 2635 DBGINFO(("%s set_params\n", info->device_name)); 2636 if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS))) 2637 return -EFAULT; 2638 2639 spin_lock_irqsave(&info->lock, flags); 2640 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) 2641 info->base_clock = tmp_params.clock_speed; 2642 else 2643 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS)); 2644 spin_unlock_irqrestore(&info->lock, flags); 2645 2646 program_hw(info); 2647 2648 return 0; 2649 } 2650 2651 static int get_txidle(struct slgt_info *info, int __user *idle_mode) 2652 { 2653 DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode)); 2654 if (put_user(info->idle_mode, idle_mode)) 2655 return -EFAULT; 2656 return 0; 2657 } 2658 2659 static int set_txidle(struct slgt_info *info, int idle_mode) 2660 { 2661 unsigned long flags; 2662 DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode)); 2663 spin_lock_irqsave(&info->lock,flags); 2664 info->idle_mode = idle_mode; 2665 if (info->params.mode != MGSL_MODE_ASYNC) 2666 tx_set_idle(info); 2667 spin_unlock_irqrestore(&info->lock,flags); 2668 return 0; 2669 } 2670 2671 static int tx_enable(struct slgt_info *info, int enable) 2672 { 2673 unsigned long flags; 2674 DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable)); 2675 spin_lock_irqsave(&info->lock,flags); 2676 if (enable) { 2677 if (!info->tx_enabled) 2678 tx_start(info); 2679 } else { 2680 if (info->tx_enabled) 2681 tx_stop(info); 2682 } 2683 spin_unlock_irqrestore(&info->lock,flags); 2684 return 0; 2685 } 2686 2687 /* 2688 * abort transmit HDLC frame 2689 */ 2690 static int tx_abort(struct slgt_info *info) 2691 { 2692 unsigned long flags; 2693 DBGINFO(("%s tx_abort\n", info->device_name)); 2694 spin_lock_irqsave(&info->lock,flags); 2695 tdma_reset(info); 2696 spin_unlock_irqrestore(&info->lock,flags); 2697 return 0; 2698 } 2699 2700 static int rx_enable(struct slgt_info *info, int enable) 2701 { 2702 unsigned long flags; 2703 unsigned int rbuf_fill_level; 2704 DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable)); 2705 spin_lock_irqsave(&info->lock,flags); 2706 /* 2707 * enable[31..16] = receive DMA buffer fill level 2708 * 0 = noop (leave fill level unchanged) 2709 * fill level must be multiple of 4 and <= buffer size 2710 */ 2711 rbuf_fill_level = ((unsigned int)enable) >> 16; 2712 if (rbuf_fill_level) { 2713 if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) { 2714 spin_unlock_irqrestore(&info->lock, flags); 2715 return -EINVAL; 2716 } 2717 info->rbuf_fill_level = rbuf_fill_level; 2718 if (rbuf_fill_level < 128) 2719 info->rx_pio = 1; /* PIO mode */ 2720 else 2721 info->rx_pio = 0; /* DMA mode */ 2722 rx_stop(info); /* restart receiver to use new fill level */ 2723 } 2724 2725 /* 2726 * enable[1..0] = receiver enable command 2727 * 0 = disable 2728 * 1 = enable 2729 * 2 = enable or force hunt mode if already enabled 2730 */ 2731 enable &= 3; 2732 if (enable) { 2733 if (!info->rx_enabled) 2734 rx_start(info); 2735 else if (enable == 2) { 2736 /* force hunt mode (write 1 to RCR[3]) */ 2737 wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3); 2738 } 2739 } else { 2740 if (info->rx_enabled) 2741 rx_stop(info); 2742 } 2743 spin_unlock_irqrestore(&info->lock,flags); 2744 return 0; 2745 } 2746 2747 /* 2748 * wait for specified event to occur 2749 */ 2750 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr) 2751 { 2752 unsigned long flags; 2753 int s; 2754 int rc=0; 2755 struct mgsl_icount cprev, cnow; 2756 int events; 2757 int mask; 2758 struct _input_signal_events oldsigs, newsigs; 2759 DECLARE_WAITQUEUE(wait, current); 2760 2761 if (get_user(mask, mask_ptr)) 2762 return -EFAULT; 2763 2764 DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask)); 2765 2766 spin_lock_irqsave(&info->lock,flags); 2767 2768 /* return immediately if state matches requested events */ 2769 get_signals(info); 2770 s = info->signals; 2771 2772 events = mask & 2773 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) + 2774 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) + 2775 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) + 2776 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) ); 2777 if (events) { 2778 spin_unlock_irqrestore(&info->lock,flags); 2779 goto exit; 2780 } 2781 2782 /* save current irq counts */ 2783 cprev = info->icount; 2784 oldsigs = info->input_signal_events; 2785 2786 /* enable hunt and idle irqs if needed */ 2787 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) { 2788 unsigned short val = rd_reg16(info, SCR); 2789 if (!(val & IRQ_RXIDLE)) 2790 wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE)); 2791 } 2792 2793 set_current_state(TASK_INTERRUPTIBLE); 2794 add_wait_queue(&info->event_wait_q, &wait); 2795 2796 spin_unlock_irqrestore(&info->lock,flags); 2797 2798 for(;;) { 2799 schedule(); 2800 if (signal_pending(current)) { 2801 rc = -ERESTARTSYS; 2802 break; 2803 } 2804 2805 /* get current irq counts */ 2806 spin_lock_irqsave(&info->lock,flags); 2807 cnow = info->icount; 2808 newsigs = info->input_signal_events; 2809 set_current_state(TASK_INTERRUPTIBLE); 2810 spin_unlock_irqrestore(&info->lock,flags); 2811 2812 /* if no change, wait aborted for some reason */ 2813 if (newsigs.dsr_up == oldsigs.dsr_up && 2814 newsigs.dsr_down == oldsigs.dsr_down && 2815 newsigs.dcd_up == oldsigs.dcd_up && 2816 newsigs.dcd_down == oldsigs.dcd_down && 2817 newsigs.cts_up == oldsigs.cts_up && 2818 newsigs.cts_down == oldsigs.cts_down && 2819 newsigs.ri_up == oldsigs.ri_up && 2820 newsigs.ri_down == oldsigs.ri_down && 2821 cnow.exithunt == cprev.exithunt && 2822 cnow.rxidle == cprev.rxidle) { 2823 rc = -EIO; 2824 break; 2825 } 2826 2827 events = mask & 2828 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) + 2829 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) + 2830 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) + 2831 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) + 2832 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) + 2833 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) + 2834 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) + 2835 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) + 2836 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) + 2837 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) ); 2838 if (events) 2839 break; 2840 2841 cprev = cnow; 2842 oldsigs = newsigs; 2843 } 2844 2845 remove_wait_queue(&info->event_wait_q, &wait); 2846 set_current_state(TASK_RUNNING); 2847 2848 2849 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) { 2850 spin_lock_irqsave(&info->lock,flags); 2851 if (!waitqueue_active(&info->event_wait_q)) { 2852 /* disable enable exit hunt mode/idle rcvd IRQs */ 2853 wr_reg16(info, SCR, 2854 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE)); 2855 } 2856 spin_unlock_irqrestore(&info->lock,flags); 2857 } 2858 exit: 2859 if (rc == 0) 2860 rc = put_user(events, mask_ptr); 2861 return rc; 2862 } 2863 2864 static int get_interface(struct slgt_info *info, int __user *if_mode) 2865 { 2866 DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode)); 2867 if (put_user(info->if_mode, if_mode)) 2868 return -EFAULT; 2869 return 0; 2870 } 2871 2872 static int set_interface(struct slgt_info *info, int if_mode) 2873 { 2874 unsigned long flags; 2875 unsigned short val; 2876 2877 DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode)); 2878 spin_lock_irqsave(&info->lock,flags); 2879 info->if_mode = if_mode; 2880 2881 msc_set_vcr(info); 2882 2883 /* TCR (tx control) 07 1=RTS driver control */ 2884 val = rd_reg16(info, TCR); 2885 if (info->if_mode & MGSL_INTERFACE_RTS_EN) 2886 val |= BIT7; 2887 else 2888 val &= ~BIT7; 2889 wr_reg16(info, TCR, val); 2890 2891 spin_unlock_irqrestore(&info->lock,flags); 2892 return 0; 2893 } 2894 2895 static int get_xsync(struct slgt_info *info, int __user *xsync) 2896 { 2897 DBGINFO(("%s get_xsync=%x\n", info->device_name, info->xsync)); 2898 if (put_user(info->xsync, xsync)) 2899 return -EFAULT; 2900 return 0; 2901 } 2902 2903 /* 2904 * set extended sync pattern (1 to 4 bytes) for extended sync mode 2905 * 2906 * sync pattern is contained in least significant bytes of value 2907 * most significant byte of sync pattern is oldest (1st sent/detected) 2908 */ 2909 static int set_xsync(struct slgt_info *info, int xsync) 2910 { 2911 unsigned long flags; 2912 2913 DBGINFO(("%s set_xsync=%x)\n", info->device_name, xsync)); 2914 spin_lock_irqsave(&info->lock, flags); 2915 info->xsync = xsync; 2916 wr_reg32(info, XSR, xsync); 2917 spin_unlock_irqrestore(&info->lock, flags); 2918 return 0; 2919 } 2920 2921 static int get_xctrl(struct slgt_info *info, int __user *xctrl) 2922 { 2923 DBGINFO(("%s get_xctrl=%x\n", info->device_name, info->xctrl)); 2924 if (put_user(info->xctrl, xctrl)) 2925 return -EFAULT; 2926 return 0; 2927 } 2928 2929 /* 2930 * set extended control options 2931 * 2932 * xctrl[31:19] reserved, must be zero 2933 * xctrl[18:17] extended sync pattern length in bytes 2934 * 00 = 1 byte in xsr[7:0] 2935 * 01 = 2 bytes in xsr[15:0] 2936 * 10 = 3 bytes in xsr[23:0] 2937 * 11 = 4 bytes in xsr[31:0] 2938 * xctrl[16] 1 = enable terminal count, 0=disabled 2939 * xctrl[15:0] receive terminal count for fixed length packets 2940 * value is count minus one (0 = 1 byte packet) 2941 * when terminal count is reached, receiver 2942 * automatically returns to hunt mode and receive 2943 * FIFO contents are flushed to DMA buffers with 2944 * end of frame (EOF) status 2945 */ 2946 static int set_xctrl(struct slgt_info *info, int xctrl) 2947 { 2948 unsigned long flags; 2949 2950 DBGINFO(("%s set_xctrl=%x)\n", info->device_name, xctrl)); 2951 spin_lock_irqsave(&info->lock, flags); 2952 info->xctrl = xctrl; 2953 wr_reg32(info, XCR, xctrl); 2954 spin_unlock_irqrestore(&info->lock, flags); 2955 return 0; 2956 } 2957 2958 /* 2959 * set general purpose IO pin state and direction 2960 * 2961 * user_gpio fields: 2962 * state each bit indicates a pin state 2963 * smask set bit indicates pin state to set 2964 * dir each bit indicates a pin direction (0=input, 1=output) 2965 * dmask set bit indicates pin direction to set 2966 */ 2967 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio) 2968 { 2969 unsigned long flags; 2970 struct gpio_desc gpio; 2971 __u32 data; 2972 2973 if (!info->gpio_present) 2974 return -EINVAL; 2975 if (copy_from_user(&gpio, user_gpio, sizeof(gpio))) 2976 return -EFAULT; 2977 DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n", 2978 info->device_name, gpio.state, gpio.smask, 2979 gpio.dir, gpio.dmask)); 2980 2981 spin_lock_irqsave(&info->port_array[0]->lock, flags); 2982 if (gpio.dmask) { 2983 data = rd_reg32(info, IODR); 2984 data |= gpio.dmask & gpio.dir; 2985 data &= ~(gpio.dmask & ~gpio.dir); 2986 wr_reg32(info, IODR, data); 2987 } 2988 if (gpio.smask) { 2989 data = rd_reg32(info, IOVR); 2990 data |= gpio.smask & gpio.state; 2991 data &= ~(gpio.smask & ~gpio.state); 2992 wr_reg32(info, IOVR, data); 2993 } 2994 spin_unlock_irqrestore(&info->port_array[0]->lock, flags); 2995 2996 return 0; 2997 } 2998 2999 /* 3000 * get general purpose IO pin state and direction 3001 */ 3002 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio) 3003 { 3004 struct gpio_desc gpio; 3005 if (!info->gpio_present) 3006 return -EINVAL; 3007 gpio.state = rd_reg32(info, IOVR); 3008 gpio.smask = 0xffffffff; 3009 gpio.dir = rd_reg32(info, IODR); 3010 gpio.dmask = 0xffffffff; 3011 if (copy_to_user(user_gpio, &gpio, sizeof(gpio))) 3012 return -EFAULT; 3013 DBGINFO(("%s get_gpio state=%08x dir=%08x\n", 3014 info->device_name, gpio.state, gpio.dir)); 3015 return 0; 3016 } 3017 3018 /* 3019 * conditional wait facility 3020 */ 3021 static void init_cond_wait(struct cond_wait *w, unsigned int data) 3022 { 3023 init_waitqueue_head(&w->q); 3024 init_waitqueue_entry(&w->wait, current); 3025 w->data = data; 3026 } 3027 3028 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w) 3029 { 3030 set_current_state(TASK_INTERRUPTIBLE); 3031 add_wait_queue(&w->q, &w->wait); 3032 w->next = *head; 3033 *head = w; 3034 } 3035 3036 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw) 3037 { 3038 struct cond_wait *w, *prev; 3039 remove_wait_queue(&cw->q, &cw->wait); 3040 set_current_state(TASK_RUNNING); 3041 for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) { 3042 if (w == cw) { 3043 if (prev != NULL) 3044 prev->next = w->next; 3045 else 3046 *head = w->next; 3047 break; 3048 } 3049 } 3050 } 3051 3052 static void flush_cond_wait(struct cond_wait **head) 3053 { 3054 while (*head != NULL) { 3055 wake_up_interruptible(&(*head)->q); 3056 *head = (*head)->next; 3057 } 3058 } 3059 3060 /* 3061 * wait for general purpose I/O pin(s) to enter specified state 3062 * 3063 * user_gpio fields: 3064 * state - bit indicates target pin state 3065 * smask - set bit indicates watched pin 3066 * 3067 * The wait ends when at least one watched pin enters the specified 3068 * state. When 0 (no error) is returned, user_gpio->state is set to the 3069 * state of all GPIO pins when the wait ends. 3070 * 3071 * Note: Each pin may be a dedicated input, dedicated output, or 3072 * configurable input/output. The number and configuration of pins 3073 * varies with the specific adapter model. Only input pins (dedicated 3074 * or configured) can be monitored with this function. 3075 */ 3076 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio) 3077 { 3078 unsigned long flags; 3079 int rc = 0; 3080 struct gpio_desc gpio; 3081 struct cond_wait wait; 3082 u32 state; 3083 3084 if (!info->gpio_present) 3085 return -EINVAL; 3086 if (copy_from_user(&gpio, user_gpio, sizeof(gpio))) 3087 return -EFAULT; 3088 DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n", 3089 info->device_name, gpio.state, gpio.smask)); 3090 /* ignore output pins identified by set IODR bit */ 3091 if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0) 3092 return -EINVAL; 3093 init_cond_wait(&wait, gpio.smask); 3094 3095 spin_lock_irqsave(&info->port_array[0]->lock, flags); 3096 /* enable interrupts for watched pins */ 3097 wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask); 3098 /* get current pin states */ 3099 state = rd_reg32(info, IOVR); 3100 3101 if (gpio.smask & ~(state ^ gpio.state)) { 3102 /* already in target state */ 3103 gpio.state = state; 3104 } else { 3105 /* wait for target state */ 3106 add_cond_wait(&info->gpio_wait_q, &wait); 3107 spin_unlock_irqrestore(&info->port_array[0]->lock, flags); 3108 schedule(); 3109 if (signal_pending(current)) 3110 rc = -ERESTARTSYS; 3111 else 3112 gpio.state = wait.data; 3113 spin_lock_irqsave(&info->port_array[0]->lock, flags); 3114 remove_cond_wait(&info->gpio_wait_q, &wait); 3115 } 3116 3117 /* disable all GPIO interrupts if no waiting processes */ 3118 if (info->gpio_wait_q == NULL) 3119 wr_reg32(info, IOER, 0); 3120 spin_unlock_irqrestore(&info->port_array[0]->lock, flags); 3121 3122 if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio))) 3123 rc = -EFAULT; 3124 return rc; 3125 } 3126 3127 static int modem_input_wait(struct slgt_info *info,int arg) 3128 { 3129 unsigned long flags; 3130 int rc; 3131 struct mgsl_icount cprev, cnow; 3132 DECLARE_WAITQUEUE(wait, current); 3133 3134 /* save current irq counts */ 3135 spin_lock_irqsave(&info->lock,flags); 3136 cprev = info->icount; 3137 add_wait_queue(&info->status_event_wait_q, &wait); 3138 set_current_state(TASK_INTERRUPTIBLE); 3139 spin_unlock_irqrestore(&info->lock,flags); 3140 3141 for(;;) { 3142 schedule(); 3143 if (signal_pending(current)) { 3144 rc = -ERESTARTSYS; 3145 break; 3146 } 3147 3148 /* get new irq counts */ 3149 spin_lock_irqsave(&info->lock,flags); 3150 cnow = info->icount; 3151 set_current_state(TASK_INTERRUPTIBLE); 3152 spin_unlock_irqrestore(&info->lock,flags); 3153 3154 /* if no change, wait aborted for some reason */ 3155 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr && 3156 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) { 3157 rc = -EIO; 3158 break; 3159 } 3160 3161 /* check for change in caller specified modem input */ 3162 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) || 3163 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) || 3164 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) || 3165 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) { 3166 rc = 0; 3167 break; 3168 } 3169 3170 cprev = cnow; 3171 } 3172 remove_wait_queue(&info->status_event_wait_q, &wait); 3173 set_current_state(TASK_RUNNING); 3174 return rc; 3175 } 3176 3177 /* 3178 * return state of serial control and status signals 3179 */ 3180 static int tiocmget(struct tty_struct *tty) 3181 { 3182 struct slgt_info *info = tty->driver_data; 3183 unsigned int result; 3184 unsigned long flags; 3185 3186 spin_lock_irqsave(&info->lock,flags); 3187 get_signals(info); 3188 spin_unlock_irqrestore(&info->lock,flags); 3189 3190 result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) + 3191 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) + 3192 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) + 3193 ((info->signals & SerialSignal_RI) ? TIOCM_RNG:0) + 3194 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) + 3195 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0); 3196 3197 DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result)); 3198 return result; 3199 } 3200 3201 /* 3202 * set modem control signals (DTR/RTS) 3203 * 3204 * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit 3205 * TIOCMSET = set/clear signal values 3206 * value bit mask for command 3207 */ 3208 static int tiocmset(struct tty_struct *tty, 3209 unsigned int set, unsigned int clear) 3210 { 3211 struct slgt_info *info = tty->driver_data; 3212 unsigned long flags; 3213 3214 DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear)); 3215 3216 if (set & TIOCM_RTS) 3217 info->signals |= SerialSignal_RTS; 3218 if (set & TIOCM_DTR) 3219 info->signals |= SerialSignal_DTR; 3220 if (clear & TIOCM_RTS) 3221 info->signals &= ~SerialSignal_RTS; 3222 if (clear & TIOCM_DTR) 3223 info->signals &= ~SerialSignal_DTR; 3224 3225 spin_lock_irqsave(&info->lock,flags); 3226 set_signals(info); 3227 spin_unlock_irqrestore(&info->lock,flags); 3228 return 0; 3229 } 3230 3231 static int carrier_raised(struct tty_port *port) 3232 { 3233 unsigned long flags; 3234 struct slgt_info *info = container_of(port, struct slgt_info, port); 3235 3236 spin_lock_irqsave(&info->lock,flags); 3237 get_signals(info); 3238 spin_unlock_irqrestore(&info->lock,flags); 3239 return (info->signals & SerialSignal_DCD) ? 1 : 0; 3240 } 3241 3242 static void dtr_rts(struct tty_port *port, int on) 3243 { 3244 unsigned long flags; 3245 struct slgt_info *info = container_of(port, struct slgt_info, port); 3246 3247 spin_lock_irqsave(&info->lock,flags); 3248 if (on) 3249 info->signals |= SerialSignal_RTS | SerialSignal_DTR; 3250 else 3251 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR); 3252 set_signals(info); 3253 spin_unlock_irqrestore(&info->lock,flags); 3254 } 3255 3256 3257 /* 3258 * block current process until the device is ready to open 3259 */ 3260 static int block_til_ready(struct tty_struct *tty, struct file *filp, 3261 struct slgt_info *info) 3262 { 3263 DECLARE_WAITQUEUE(wait, current); 3264 int retval; 3265 bool do_clocal = false; 3266 unsigned long flags; 3267 int cd; 3268 struct tty_port *port = &info->port; 3269 3270 DBGINFO(("%s block_til_ready\n", tty->driver->name)); 3271 3272 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){ 3273 /* nonblock mode is set or port is not enabled */ 3274 port->flags |= ASYNC_NORMAL_ACTIVE; 3275 return 0; 3276 } 3277 3278 if (C_CLOCAL(tty)) 3279 do_clocal = true; 3280 3281 /* Wait for carrier detect and the line to become 3282 * free (i.e., not in use by the callout). While we are in 3283 * this loop, port->count is dropped by one, so that 3284 * close() knows when to free things. We restore it upon 3285 * exit, either normal or abnormal. 3286 */ 3287 3288 retval = 0; 3289 add_wait_queue(&port->open_wait, &wait); 3290 3291 spin_lock_irqsave(&info->lock, flags); 3292 port->count--; 3293 spin_unlock_irqrestore(&info->lock, flags); 3294 port->blocked_open++; 3295 3296 while (1) { 3297 if (C_BAUD(tty) && test_bit(ASYNCB_INITIALIZED, &port->flags)) 3298 tty_port_raise_dtr_rts(port); 3299 3300 set_current_state(TASK_INTERRUPTIBLE); 3301 3302 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){ 3303 retval = (port->flags & ASYNC_HUP_NOTIFY) ? 3304 -EAGAIN : -ERESTARTSYS; 3305 break; 3306 } 3307 3308 cd = tty_port_carrier_raised(port); 3309 if (do_clocal || cd) 3310 break; 3311 3312 if (signal_pending(current)) { 3313 retval = -ERESTARTSYS; 3314 break; 3315 } 3316 3317 DBGINFO(("%s block_til_ready wait\n", tty->driver->name)); 3318 tty_unlock(tty); 3319 schedule(); 3320 tty_lock(tty); 3321 } 3322 3323 set_current_state(TASK_RUNNING); 3324 remove_wait_queue(&port->open_wait, &wait); 3325 3326 if (!tty_hung_up_p(filp)) 3327 port->count++; 3328 port->blocked_open--; 3329 3330 if (!retval) 3331 port->flags |= ASYNC_NORMAL_ACTIVE; 3332 3333 DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval)); 3334 return retval; 3335 } 3336 3337 /* 3338 * allocate buffers used for calling line discipline receive_buf 3339 * directly in synchronous mode 3340 * note: add 5 bytes to max frame size to allow appending 3341 * 32-bit CRC and status byte when configured to do so 3342 */ 3343 static int alloc_tmp_rbuf(struct slgt_info *info) 3344 { 3345 info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL); 3346 if (info->tmp_rbuf == NULL) 3347 return -ENOMEM; 3348 /* unused flag buffer to satisfy receive_buf calling interface */ 3349 info->flag_buf = kzalloc(info->max_frame_size + 5, GFP_KERNEL); 3350 if (!info->flag_buf) { 3351 kfree(info->tmp_rbuf); 3352 info->tmp_rbuf = NULL; 3353 return -ENOMEM; 3354 } 3355 return 0; 3356 } 3357 3358 static void free_tmp_rbuf(struct slgt_info *info) 3359 { 3360 kfree(info->tmp_rbuf); 3361 info->tmp_rbuf = NULL; 3362 kfree(info->flag_buf); 3363 info->flag_buf = NULL; 3364 } 3365 3366 /* 3367 * allocate DMA descriptor lists. 3368 */ 3369 static int alloc_desc(struct slgt_info *info) 3370 { 3371 unsigned int i; 3372 unsigned int pbufs; 3373 3374 /* allocate memory to hold descriptor lists */ 3375 info->bufs = pci_zalloc_consistent(info->pdev, DESC_LIST_SIZE, 3376 &info->bufs_dma_addr); 3377 if (info->bufs == NULL) 3378 return -ENOMEM; 3379 3380 info->rbufs = (struct slgt_desc*)info->bufs; 3381 info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count; 3382 3383 pbufs = (unsigned int)info->bufs_dma_addr; 3384 3385 /* 3386 * Build circular lists of descriptors 3387 */ 3388 3389 for (i=0; i < info->rbuf_count; i++) { 3390 /* physical address of this descriptor */ 3391 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc)); 3392 3393 /* physical address of next descriptor */ 3394 if (i == info->rbuf_count - 1) 3395 info->rbufs[i].next = cpu_to_le32(pbufs); 3396 else 3397 info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc))); 3398 set_desc_count(info->rbufs[i], DMABUFSIZE); 3399 } 3400 3401 for (i=0; i < info->tbuf_count; i++) { 3402 /* physical address of this descriptor */ 3403 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc)); 3404 3405 /* physical address of next descriptor */ 3406 if (i == info->tbuf_count - 1) 3407 info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc)); 3408 else 3409 info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc))); 3410 } 3411 3412 return 0; 3413 } 3414 3415 static void free_desc(struct slgt_info *info) 3416 { 3417 if (info->bufs != NULL) { 3418 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr); 3419 info->bufs = NULL; 3420 info->rbufs = NULL; 3421 info->tbufs = NULL; 3422 } 3423 } 3424 3425 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count) 3426 { 3427 int i; 3428 for (i=0; i < count; i++) { 3429 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL) 3430 return -ENOMEM; 3431 bufs[i].pbuf = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr); 3432 } 3433 return 0; 3434 } 3435 3436 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count) 3437 { 3438 int i; 3439 for (i=0; i < count; i++) { 3440 if (bufs[i].buf == NULL) 3441 continue; 3442 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr); 3443 bufs[i].buf = NULL; 3444 } 3445 } 3446 3447 static int alloc_dma_bufs(struct slgt_info *info) 3448 { 3449 info->rbuf_count = 32; 3450 info->tbuf_count = 32; 3451 3452 if (alloc_desc(info) < 0 || 3453 alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 || 3454 alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 || 3455 alloc_tmp_rbuf(info) < 0) { 3456 DBGERR(("%s DMA buffer alloc fail\n", info->device_name)); 3457 return -ENOMEM; 3458 } 3459 reset_rbufs(info); 3460 return 0; 3461 } 3462 3463 static void free_dma_bufs(struct slgt_info *info) 3464 { 3465 if (info->bufs) { 3466 free_bufs(info, info->rbufs, info->rbuf_count); 3467 free_bufs(info, info->tbufs, info->tbuf_count); 3468 free_desc(info); 3469 } 3470 free_tmp_rbuf(info); 3471 } 3472 3473 static int claim_resources(struct slgt_info *info) 3474 { 3475 if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) { 3476 DBGERR(("%s reg addr conflict, addr=%08X\n", 3477 info->device_name, info->phys_reg_addr)); 3478 info->init_error = DiagStatus_AddressConflict; 3479 goto errout; 3480 } 3481 else 3482 info->reg_addr_requested = true; 3483 3484 info->reg_addr = ioremap_nocache(info->phys_reg_addr, SLGT_REG_SIZE); 3485 if (!info->reg_addr) { 3486 DBGERR(("%s can't map device registers, addr=%08X\n", 3487 info->device_name, info->phys_reg_addr)); 3488 info->init_error = DiagStatus_CantAssignPciResources; 3489 goto errout; 3490 } 3491 return 0; 3492 3493 errout: 3494 release_resources(info); 3495 return -ENODEV; 3496 } 3497 3498 static void release_resources(struct slgt_info *info) 3499 { 3500 if (info->irq_requested) { 3501 free_irq(info->irq_level, info); 3502 info->irq_requested = false; 3503 } 3504 3505 if (info->reg_addr_requested) { 3506 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE); 3507 info->reg_addr_requested = false; 3508 } 3509 3510 if (info->reg_addr) { 3511 iounmap(info->reg_addr); 3512 info->reg_addr = NULL; 3513 } 3514 } 3515 3516 /* Add the specified device instance data structure to the 3517 * global linked list of devices and increment the device count. 3518 */ 3519 static void add_device(struct slgt_info *info) 3520 { 3521 char *devstr; 3522 3523 info->next_device = NULL; 3524 info->line = slgt_device_count; 3525 sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line); 3526 3527 if (info->line < MAX_DEVICES) { 3528 if (maxframe[info->line]) 3529 info->max_frame_size = maxframe[info->line]; 3530 } 3531 3532 slgt_device_count++; 3533 3534 if (!slgt_device_list) 3535 slgt_device_list = info; 3536 else { 3537 struct slgt_info *current_dev = slgt_device_list; 3538 while(current_dev->next_device) 3539 current_dev = current_dev->next_device; 3540 current_dev->next_device = info; 3541 } 3542 3543 if (info->max_frame_size < 4096) 3544 info->max_frame_size = 4096; 3545 else if (info->max_frame_size > 65535) 3546 info->max_frame_size = 65535; 3547 3548 switch(info->pdev->device) { 3549 case SYNCLINK_GT_DEVICE_ID: 3550 devstr = "GT"; 3551 break; 3552 case SYNCLINK_GT2_DEVICE_ID: 3553 devstr = "GT2"; 3554 break; 3555 case SYNCLINK_GT4_DEVICE_ID: 3556 devstr = "GT4"; 3557 break; 3558 case SYNCLINK_AC_DEVICE_ID: 3559 devstr = "AC"; 3560 info->params.mode = MGSL_MODE_ASYNC; 3561 break; 3562 default: 3563 devstr = "(unknown model)"; 3564 } 3565 printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n", 3566 devstr, info->device_name, info->phys_reg_addr, 3567 info->irq_level, info->max_frame_size); 3568 3569 #if SYNCLINK_GENERIC_HDLC 3570 hdlcdev_init(info); 3571 #endif 3572 } 3573 3574 static const struct tty_port_operations slgt_port_ops = { 3575 .carrier_raised = carrier_raised, 3576 .dtr_rts = dtr_rts, 3577 }; 3578 3579 /* 3580 * allocate device instance structure, return NULL on failure 3581 */ 3582 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev) 3583 { 3584 struct slgt_info *info; 3585 3586 info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL); 3587 3588 if (!info) { 3589 DBGERR(("%s device alloc failed adapter=%d port=%d\n", 3590 driver_name, adapter_num, port_num)); 3591 } else { 3592 tty_port_init(&info->port); 3593 info->port.ops = &slgt_port_ops; 3594 info->magic = MGSL_MAGIC; 3595 INIT_WORK(&info->task, bh_handler); 3596 info->max_frame_size = 4096; 3597 info->base_clock = 14745600; 3598 info->rbuf_fill_level = DMABUFSIZE; 3599 info->port.close_delay = 5*HZ/10; 3600 info->port.closing_wait = 30*HZ; 3601 init_waitqueue_head(&info->status_event_wait_q); 3602 init_waitqueue_head(&info->event_wait_q); 3603 spin_lock_init(&info->netlock); 3604 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS)); 3605 info->idle_mode = HDLC_TXIDLE_FLAGS; 3606 info->adapter_num = adapter_num; 3607 info->port_num = port_num; 3608 3609 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info); 3610 setup_timer(&info->rx_timer, rx_timeout, (unsigned long)info); 3611 3612 /* Copy configuration info to device instance data */ 3613 info->pdev = pdev; 3614 info->irq_level = pdev->irq; 3615 info->phys_reg_addr = pci_resource_start(pdev,0); 3616 3617 info->bus_type = MGSL_BUS_TYPE_PCI; 3618 info->irq_flags = IRQF_SHARED; 3619 3620 info->init_error = -1; /* assume error, set to 0 on successful init */ 3621 } 3622 3623 return info; 3624 } 3625 3626 static void device_init(int adapter_num, struct pci_dev *pdev) 3627 { 3628 struct slgt_info *port_array[SLGT_MAX_PORTS]; 3629 int i; 3630 int port_count = 1; 3631 3632 if (pdev->device == SYNCLINK_GT2_DEVICE_ID) 3633 port_count = 2; 3634 else if (pdev->device == SYNCLINK_GT4_DEVICE_ID) 3635 port_count = 4; 3636 3637 /* allocate device instances for all ports */ 3638 for (i=0; i < port_count; ++i) { 3639 port_array[i] = alloc_dev(adapter_num, i, pdev); 3640 if (port_array[i] == NULL) { 3641 for (--i; i >= 0; --i) { 3642 tty_port_destroy(&port_array[i]->port); 3643 kfree(port_array[i]); 3644 } 3645 return; 3646 } 3647 } 3648 3649 /* give copy of port_array to all ports and add to device list */ 3650 for (i=0; i < port_count; ++i) { 3651 memcpy(port_array[i]->port_array, port_array, sizeof(port_array)); 3652 add_device(port_array[i]); 3653 port_array[i]->port_count = port_count; 3654 spin_lock_init(&port_array[i]->lock); 3655 } 3656 3657 /* Allocate and claim adapter resources */ 3658 if (!claim_resources(port_array[0])) { 3659 3660 alloc_dma_bufs(port_array[0]); 3661 3662 /* copy resource information from first port to others */ 3663 for (i = 1; i < port_count; ++i) { 3664 port_array[i]->irq_level = port_array[0]->irq_level; 3665 port_array[i]->reg_addr = port_array[0]->reg_addr; 3666 alloc_dma_bufs(port_array[i]); 3667 } 3668 3669 if (request_irq(port_array[0]->irq_level, 3670 slgt_interrupt, 3671 port_array[0]->irq_flags, 3672 port_array[0]->device_name, 3673 port_array[0]) < 0) { 3674 DBGERR(("%s request_irq failed IRQ=%d\n", 3675 port_array[0]->device_name, 3676 port_array[0]->irq_level)); 3677 } else { 3678 port_array[0]->irq_requested = true; 3679 adapter_test(port_array[0]); 3680 for (i=1 ; i < port_count ; i++) { 3681 port_array[i]->init_error = port_array[0]->init_error; 3682 port_array[i]->gpio_present = port_array[0]->gpio_present; 3683 } 3684 } 3685 } 3686 3687 for (i = 0; i < port_count; ++i) { 3688 struct slgt_info *info = port_array[i]; 3689 tty_port_register_device(&info->port, serial_driver, info->line, 3690 &info->pdev->dev); 3691 } 3692 } 3693 3694 static int init_one(struct pci_dev *dev, 3695 const struct pci_device_id *ent) 3696 { 3697 if (pci_enable_device(dev)) { 3698 printk("error enabling pci device %p\n", dev); 3699 return -EIO; 3700 } 3701 pci_set_master(dev); 3702 device_init(slgt_device_count, dev); 3703 return 0; 3704 } 3705 3706 static void remove_one(struct pci_dev *dev) 3707 { 3708 } 3709 3710 static const struct tty_operations ops = { 3711 .open = open, 3712 .close = close, 3713 .write = write, 3714 .put_char = put_char, 3715 .flush_chars = flush_chars, 3716 .write_room = write_room, 3717 .chars_in_buffer = chars_in_buffer, 3718 .flush_buffer = flush_buffer, 3719 .ioctl = ioctl, 3720 .compat_ioctl = slgt_compat_ioctl, 3721 .throttle = throttle, 3722 .unthrottle = unthrottle, 3723 .send_xchar = send_xchar, 3724 .break_ctl = set_break, 3725 .wait_until_sent = wait_until_sent, 3726 .set_termios = set_termios, 3727 .stop = tx_hold, 3728 .start = tx_release, 3729 .hangup = hangup, 3730 .tiocmget = tiocmget, 3731 .tiocmset = tiocmset, 3732 .get_icount = get_icount, 3733 .proc_fops = &synclink_gt_proc_fops, 3734 }; 3735 3736 static void slgt_cleanup(void) 3737 { 3738 int rc; 3739 struct slgt_info *info; 3740 struct slgt_info *tmp; 3741 3742 printk(KERN_INFO "unload %s\n", driver_name); 3743 3744 if (serial_driver) { 3745 for (info=slgt_device_list ; info != NULL ; info=info->next_device) 3746 tty_unregister_device(serial_driver, info->line); 3747 rc = tty_unregister_driver(serial_driver); 3748 if (rc) 3749 DBGERR(("tty_unregister_driver error=%d\n", rc)); 3750 put_tty_driver(serial_driver); 3751 } 3752 3753 /* reset devices */ 3754 info = slgt_device_list; 3755 while(info) { 3756 reset_port(info); 3757 info = info->next_device; 3758 } 3759 3760 /* release devices */ 3761 info = slgt_device_list; 3762 while(info) { 3763 #if SYNCLINK_GENERIC_HDLC 3764 hdlcdev_exit(info); 3765 #endif 3766 free_dma_bufs(info); 3767 free_tmp_rbuf(info); 3768 if (info->port_num == 0) 3769 release_resources(info); 3770 tmp = info; 3771 info = info->next_device; 3772 tty_port_destroy(&tmp->port); 3773 kfree(tmp); 3774 } 3775 3776 if (pci_registered) 3777 pci_unregister_driver(&pci_driver); 3778 } 3779 3780 /* 3781 * Driver initialization entry point. 3782 */ 3783 static int __init slgt_init(void) 3784 { 3785 int rc; 3786 3787 printk(KERN_INFO "%s\n", driver_name); 3788 3789 serial_driver = alloc_tty_driver(MAX_DEVICES); 3790 if (!serial_driver) { 3791 printk("%s can't allocate tty driver\n", driver_name); 3792 return -ENOMEM; 3793 } 3794 3795 /* Initialize the tty_driver structure */ 3796 3797 serial_driver->driver_name = slgt_driver_name; 3798 serial_driver->name = tty_dev_prefix; 3799 serial_driver->major = ttymajor; 3800 serial_driver->minor_start = 64; 3801 serial_driver->type = TTY_DRIVER_TYPE_SERIAL; 3802 serial_driver->subtype = SERIAL_TYPE_NORMAL; 3803 serial_driver->init_termios = tty_std_termios; 3804 serial_driver->init_termios.c_cflag = 3805 B9600 | CS8 | CREAD | HUPCL | CLOCAL; 3806 serial_driver->init_termios.c_ispeed = 9600; 3807 serial_driver->init_termios.c_ospeed = 9600; 3808 serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV; 3809 tty_set_operations(serial_driver, &ops); 3810 if ((rc = tty_register_driver(serial_driver)) < 0) { 3811 DBGERR(("%s can't register serial driver\n", driver_name)); 3812 put_tty_driver(serial_driver); 3813 serial_driver = NULL; 3814 goto error; 3815 } 3816 3817 printk(KERN_INFO "%s, tty major#%d\n", 3818 driver_name, serial_driver->major); 3819 3820 slgt_device_count = 0; 3821 if ((rc = pci_register_driver(&pci_driver)) < 0) { 3822 printk("%s pci_register_driver error=%d\n", driver_name, rc); 3823 goto error; 3824 } 3825 pci_registered = true; 3826 3827 if (!slgt_device_list) 3828 printk("%s no devices found\n",driver_name); 3829 3830 return 0; 3831 3832 error: 3833 slgt_cleanup(); 3834 return rc; 3835 } 3836 3837 static void __exit slgt_exit(void) 3838 { 3839 slgt_cleanup(); 3840 } 3841 3842 module_init(slgt_init); 3843 module_exit(slgt_exit); 3844 3845 /* 3846 * register access routines 3847 */ 3848 3849 #define CALC_REGADDR() \ 3850 unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \ 3851 if (addr >= 0x80) \ 3852 reg_addr += (info->port_num) * 32; \ 3853 else if (addr >= 0x40) \ 3854 reg_addr += (info->port_num) * 16; 3855 3856 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr) 3857 { 3858 CALC_REGADDR(); 3859 return readb((void __iomem *)reg_addr); 3860 } 3861 3862 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value) 3863 { 3864 CALC_REGADDR(); 3865 writeb(value, (void __iomem *)reg_addr); 3866 } 3867 3868 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr) 3869 { 3870 CALC_REGADDR(); 3871 return readw((void __iomem *)reg_addr); 3872 } 3873 3874 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value) 3875 { 3876 CALC_REGADDR(); 3877 writew(value, (void __iomem *)reg_addr); 3878 } 3879 3880 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr) 3881 { 3882 CALC_REGADDR(); 3883 return readl((void __iomem *)reg_addr); 3884 } 3885 3886 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value) 3887 { 3888 CALC_REGADDR(); 3889 writel(value, (void __iomem *)reg_addr); 3890 } 3891 3892 static void rdma_reset(struct slgt_info *info) 3893 { 3894 unsigned int i; 3895 3896 /* set reset bit */ 3897 wr_reg32(info, RDCSR, BIT1); 3898 3899 /* wait for enable bit cleared */ 3900 for(i=0 ; i < 1000 ; i++) 3901 if (!(rd_reg32(info, RDCSR) & BIT0)) 3902 break; 3903 } 3904 3905 static void tdma_reset(struct slgt_info *info) 3906 { 3907 unsigned int i; 3908 3909 /* set reset bit */ 3910 wr_reg32(info, TDCSR, BIT1); 3911 3912 /* wait for enable bit cleared */ 3913 for(i=0 ; i < 1000 ; i++) 3914 if (!(rd_reg32(info, TDCSR) & BIT0)) 3915 break; 3916 } 3917 3918 /* 3919 * enable internal loopback 3920 * TxCLK and RxCLK are generated from BRG 3921 * and TxD is looped back to RxD internally. 3922 */ 3923 static void enable_loopback(struct slgt_info *info) 3924 { 3925 /* SCR (serial control) BIT2=loopback enable */ 3926 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2)); 3927 3928 if (info->params.mode != MGSL_MODE_ASYNC) { 3929 /* CCR (clock control) 3930 * 07..05 tx clock source (010 = BRG) 3931 * 04..02 rx clock source (010 = BRG) 3932 * 01 auxclk enable (0 = disable) 3933 * 00 BRG enable (1 = enable) 3934 * 3935 * 0100 1001 3936 */ 3937 wr_reg8(info, CCR, 0x49); 3938 3939 /* set speed if available, otherwise use default */ 3940 if (info->params.clock_speed) 3941 set_rate(info, info->params.clock_speed); 3942 else 3943 set_rate(info, 3686400); 3944 } 3945 } 3946 3947 /* 3948 * set baud rate generator to specified rate 3949 */ 3950 static void set_rate(struct slgt_info *info, u32 rate) 3951 { 3952 unsigned int div; 3953 unsigned int osc = info->base_clock; 3954 3955 /* div = osc/rate - 1 3956 * 3957 * Round div up if osc/rate is not integer to 3958 * force to next slowest rate. 3959 */ 3960 3961 if (rate) { 3962 div = osc/rate; 3963 if (!(osc % rate) && div) 3964 div--; 3965 wr_reg16(info, BDR, (unsigned short)div); 3966 } 3967 } 3968 3969 static void rx_stop(struct slgt_info *info) 3970 { 3971 unsigned short val; 3972 3973 /* disable and reset receiver */ 3974 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */ 3975 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */ 3976 wr_reg16(info, RCR, val); /* clear reset bit */ 3977 3978 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE); 3979 3980 /* clear pending rx interrupts */ 3981 wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER); 3982 3983 rdma_reset(info); 3984 3985 info->rx_enabled = false; 3986 info->rx_restart = false; 3987 } 3988 3989 static void rx_start(struct slgt_info *info) 3990 { 3991 unsigned short val; 3992 3993 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA); 3994 3995 /* clear pending rx overrun IRQ */ 3996 wr_reg16(info, SSR, IRQ_RXOVER); 3997 3998 /* reset and disable receiver */ 3999 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */ 4000 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */ 4001 wr_reg16(info, RCR, val); /* clear reset bit */ 4002 4003 rdma_reset(info); 4004 reset_rbufs(info); 4005 4006 if (info->rx_pio) { 4007 /* rx request when rx FIFO not empty */ 4008 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14)); 4009 slgt_irq_on(info, IRQ_RXDATA); 4010 if (info->params.mode == MGSL_MODE_ASYNC) { 4011 /* enable saving of rx status */ 4012 wr_reg32(info, RDCSR, BIT6); 4013 } 4014 } else { 4015 /* rx request when rx FIFO half full */ 4016 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14)); 4017 /* set 1st descriptor address */ 4018 wr_reg32(info, RDDAR, info->rbufs[0].pdesc); 4019 4020 if (info->params.mode != MGSL_MODE_ASYNC) { 4021 /* enable rx DMA and DMA interrupt */ 4022 wr_reg32(info, RDCSR, (BIT2 + BIT0)); 4023 } else { 4024 /* enable saving of rx status, rx DMA and DMA interrupt */ 4025 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0)); 4026 } 4027 } 4028 4029 slgt_irq_on(info, IRQ_RXOVER); 4030 4031 /* enable receiver */ 4032 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1)); 4033 4034 info->rx_restart = false; 4035 info->rx_enabled = true; 4036 } 4037 4038 static void tx_start(struct slgt_info *info) 4039 { 4040 if (!info->tx_enabled) { 4041 wr_reg16(info, TCR, 4042 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2)); 4043 info->tx_enabled = true; 4044 } 4045 4046 if (desc_count(info->tbufs[info->tbuf_start])) { 4047 info->drop_rts_on_tx_done = false; 4048 4049 if (info->params.mode != MGSL_MODE_ASYNC) { 4050 if (info->params.flags & HDLC_FLAG_AUTO_RTS) { 4051 get_signals(info); 4052 if (!(info->signals & SerialSignal_RTS)) { 4053 info->signals |= SerialSignal_RTS; 4054 set_signals(info); 4055 info->drop_rts_on_tx_done = true; 4056 } 4057 } 4058 4059 slgt_irq_off(info, IRQ_TXDATA); 4060 slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE); 4061 /* clear tx idle and underrun status bits */ 4062 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER)); 4063 } else { 4064 slgt_irq_off(info, IRQ_TXDATA); 4065 slgt_irq_on(info, IRQ_TXIDLE); 4066 /* clear tx idle status bit */ 4067 wr_reg16(info, SSR, IRQ_TXIDLE); 4068 } 4069 /* set 1st descriptor address and start DMA */ 4070 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc); 4071 wr_reg32(info, TDCSR, BIT2 + BIT0); 4072 info->tx_active = true; 4073 } 4074 } 4075 4076 static void tx_stop(struct slgt_info *info) 4077 { 4078 unsigned short val; 4079 4080 del_timer(&info->tx_timer); 4081 4082 tdma_reset(info); 4083 4084 /* reset and disable transmitter */ 4085 val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */ 4086 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */ 4087 4088 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER); 4089 4090 /* clear tx idle and underrun status bit */ 4091 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER)); 4092 4093 reset_tbufs(info); 4094 4095 info->tx_enabled = false; 4096 info->tx_active = false; 4097 } 4098 4099 static void reset_port(struct slgt_info *info) 4100 { 4101 if (!info->reg_addr) 4102 return; 4103 4104 tx_stop(info); 4105 rx_stop(info); 4106 4107 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR); 4108 set_signals(info); 4109 4110 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER); 4111 } 4112 4113 static void reset_adapter(struct slgt_info *info) 4114 { 4115 int i; 4116 for (i=0; i < info->port_count; ++i) { 4117 if (info->port_array[i]) 4118 reset_port(info->port_array[i]); 4119 } 4120 } 4121 4122 static void async_mode(struct slgt_info *info) 4123 { 4124 unsigned short val; 4125 4126 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER); 4127 tx_stop(info); 4128 rx_stop(info); 4129 4130 /* TCR (tx control) 4131 * 4132 * 15..13 mode, 010=async 4133 * 12..10 encoding, 000=NRZ 4134 * 09 parity enable 4135 * 08 1=odd parity, 0=even parity 4136 * 07 1=RTS driver control 4137 * 06 1=break enable 4138 * 05..04 character length 4139 * 00=5 bits 4140 * 01=6 bits 4141 * 10=7 bits 4142 * 11=8 bits 4143 * 03 0=1 stop bit, 1=2 stop bits 4144 * 02 reset 4145 * 01 enable 4146 * 00 auto-CTS enable 4147 */ 4148 val = 0x4000; 4149 4150 if (info->if_mode & MGSL_INTERFACE_RTS_EN) 4151 val |= BIT7; 4152 4153 if (info->params.parity != ASYNC_PARITY_NONE) { 4154 val |= BIT9; 4155 if (info->params.parity == ASYNC_PARITY_ODD) 4156 val |= BIT8; 4157 } 4158 4159 switch (info->params.data_bits) 4160 { 4161 case 6: val |= BIT4; break; 4162 case 7: val |= BIT5; break; 4163 case 8: val |= BIT5 + BIT4; break; 4164 } 4165 4166 if (info->params.stop_bits != 1) 4167 val |= BIT3; 4168 4169 if (info->params.flags & HDLC_FLAG_AUTO_CTS) 4170 val |= BIT0; 4171 4172 wr_reg16(info, TCR, val); 4173 4174 /* RCR (rx control) 4175 * 4176 * 15..13 mode, 010=async 4177 * 12..10 encoding, 000=NRZ 4178 * 09 parity enable 4179 * 08 1=odd parity, 0=even parity 4180 * 07..06 reserved, must be 0 4181 * 05..04 character length 4182 * 00=5 bits 4183 * 01=6 bits 4184 * 10=7 bits 4185 * 11=8 bits 4186 * 03 reserved, must be zero 4187 * 02 reset 4188 * 01 enable 4189 * 00 auto-DCD enable 4190 */ 4191 val = 0x4000; 4192 4193 if (info->params.parity != ASYNC_PARITY_NONE) { 4194 val |= BIT9; 4195 if (info->params.parity == ASYNC_PARITY_ODD) 4196 val |= BIT8; 4197 } 4198 4199 switch (info->params.data_bits) 4200 { 4201 case 6: val |= BIT4; break; 4202 case 7: val |= BIT5; break; 4203 case 8: val |= BIT5 + BIT4; break; 4204 } 4205 4206 if (info->params.flags & HDLC_FLAG_AUTO_DCD) 4207 val |= BIT0; 4208 4209 wr_reg16(info, RCR, val); 4210 4211 /* CCR (clock control) 4212 * 4213 * 07..05 011 = tx clock source is BRG/16 4214 * 04..02 010 = rx clock source is BRG 4215 * 01 0 = auxclk disabled 4216 * 00 1 = BRG enabled 4217 * 4218 * 0110 1001 4219 */ 4220 wr_reg8(info, CCR, 0x69); 4221 4222 msc_set_vcr(info); 4223 4224 /* SCR (serial control) 4225 * 4226 * 15 1=tx req on FIFO half empty 4227 * 14 1=rx req on FIFO half full 4228 * 13 tx data IRQ enable 4229 * 12 tx idle IRQ enable 4230 * 11 rx break on IRQ enable 4231 * 10 rx data IRQ enable 4232 * 09 rx break off IRQ enable 4233 * 08 overrun IRQ enable 4234 * 07 DSR IRQ enable 4235 * 06 CTS IRQ enable 4236 * 05 DCD IRQ enable 4237 * 04 RI IRQ enable 4238 * 03 0=16x sampling, 1=8x sampling 4239 * 02 1=txd->rxd internal loopback enable 4240 * 01 reserved, must be zero 4241 * 00 1=master IRQ enable 4242 */ 4243 val = BIT15 + BIT14 + BIT0; 4244 /* JCR[8] : 1 = x8 async mode feature available */ 4245 if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate && 4246 ((info->base_clock < (info->params.data_rate * 16)) || 4247 (info->base_clock % (info->params.data_rate * 16)))) { 4248 /* use 8x sampling */ 4249 val |= BIT3; 4250 set_rate(info, info->params.data_rate * 8); 4251 } else { 4252 /* use 16x sampling */ 4253 set_rate(info, info->params.data_rate * 16); 4254 } 4255 wr_reg16(info, SCR, val); 4256 4257 slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER); 4258 4259 if (info->params.loopback) 4260 enable_loopback(info); 4261 } 4262 4263 static void sync_mode(struct slgt_info *info) 4264 { 4265 unsigned short val; 4266 4267 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER); 4268 tx_stop(info); 4269 rx_stop(info); 4270 4271 /* TCR (tx control) 4272 * 4273 * 15..13 mode 4274 * 000=HDLC/SDLC 4275 * 001=raw bit synchronous 4276 * 010=asynchronous/isochronous 4277 * 011=monosync byte synchronous 4278 * 100=bisync byte synchronous 4279 * 101=xsync byte synchronous 4280 * 12..10 encoding 4281 * 09 CRC enable 4282 * 08 CRC32 4283 * 07 1=RTS driver control 4284 * 06 preamble enable 4285 * 05..04 preamble length 4286 * 03 share open/close flag 4287 * 02 reset 4288 * 01 enable 4289 * 00 auto-CTS enable 4290 */ 4291 val = BIT2; 4292 4293 switch(info->params.mode) { 4294 case MGSL_MODE_XSYNC: 4295 val |= BIT15 + BIT13; 4296 break; 4297 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break; 4298 case MGSL_MODE_BISYNC: val |= BIT15; break; 4299 case MGSL_MODE_RAW: val |= BIT13; break; 4300 } 4301 if (info->if_mode & MGSL_INTERFACE_RTS_EN) 4302 val |= BIT7; 4303 4304 switch(info->params.encoding) 4305 { 4306 case HDLC_ENCODING_NRZB: val |= BIT10; break; 4307 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break; 4308 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break; 4309 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break; 4310 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break; 4311 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break; 4312 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; 4313 } 4314 4315 switch (info->params.crc_type & HDLC_CRC_MASK) 4316 { 4317 case HDLC_CRC_16_CCITT: val |= BIT9; break; 4318 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break; 4319 } 4320 4321 if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE) 4322 val |= BIT6; 4323 4324 switch (info->params.preamble_length) 4325 { 4326 case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break; 4327 case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break; 4328 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break; 4329 } 4330 4331 if (info->params.flags & HDLC_FLAG_AUTO_CTS) 4332 val |= BIT0; 4333 4334 wr_reg16(info, TCR, val); 4335 4336 /* TPR (transmit preamble) */ 4337 4338 switch (info->params.preamble) 4339 { 4340 case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break; 4341 case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break; 4342 case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break; 4343 case HDLC_PREAMBLE_PATTERN_10: val = 0x55; break; 4344 case HDLC_PREAMBLE_PATTERN_01: val = 0xaa; break; 4345 default: val = 0x7e; break; 4346 } 4347 wr_reg8(info, TPR, (unsigned char)val); 4348 4349 /* RCR (rx control) 4350 * 4351 * 15..13 mode 4352 * 000=HDLC/SDLC 4353 * 001=raw bit synchronous 4354 * 010=asynchronous/isochronous 4355 * 011=monosync byte synchronous 4356 * 100=bisync byte synchronous 4357 * 101=xsync byte synchronous 4358 * 12..10 encoding 4359 * 09 CRC enable 4360 * 08 CRC32 4361 * 07..03 reserved, must be 0 4362 * 02 reset 4363 * 01 enable 4364 * 00 auto-DCD enable 4365 */ 4366 val = 0; 4367 4368 switch(info->params.mode) { 4369 case MGSL_MODE_XSYNC: 4370 val |= BIT15 + BIT13; 4371 break; 4372 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break; 4373 case MGSL_MODE_BISYNC: val |= BIT15; break; 4374 case MGSL_MODE_RAW: val |= BIT13; break; 4375 } 4376 4377 switch(info->params.encoding) 4378 { 4379 case HDLC_ENCODING_NRZB: val |= BIT10; break; 4380 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break; 4381 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break; 4382 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break; 4383 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break; 4384 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break; 4385 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; 4386 } 4387 4388 switch (info->params.crc_type & HDLC_CRC_MASK) 4389 { 4390 case HDLC_CRC_16_CCITT: val |= BIT9; break; 4391 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break; 4392 } 4393 4394 if (info->params.flags & HDLC_FLAG_AUTO_DCD) 4395 val |= BIT0; 4396 4397 wr_reg16(info, RCR, val); 4398 4399 /* CCR (clock control) 4400 * 4401 * 07..05 tx clock source 4402 * 04..02 rx clock source 4403 * 01 auxclk enable 4404 * 00 BRG enable 4405 */ 4406 val = 0; 4407 4408 if (info->params.flags & HDLC_FLAG_TXC_BRG) 4409 { 4410 // when RxC source is DPLL, BRG generates 16X DPLL 4411 // reference clock, so take TxC from BRG/16 to get 4412 // transmit clock at actual data rate 4413 if (info->params.flags & HDLC_FLAG_RXC_DPLL) 4414 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */ 4415 else 4416 val |= BIT6; /* 010, txclk = BRG */ 4417 } 4418 else if (info->params.flags & HDLC_FLAG_TXC_DPLL) 4419 val |= BIT7; /* 100, txclk = DPLL Input */ 4420 else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN) 4421 val |= BIT5; /* 001, txclk = RXC Input */ 4422 4423 if (info->params.flags & HDLC_FLAG_RXC_BRG) 4424 val |= BIT3; /* 010, rxclk = BRG */ 4425 else if (info->params.flags & HDLC_FLAG_RXC_DPLL) 4426 val |= BIT4; /* 100, rxclk = DPLL */ 4427 else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN) 4428 val |= BIT2; /* 001, rxclk = TXC Input */ 4429 4430 if (info->params.clock_speed) 4431 val |= BIT1 + BIT0; 4432 4433 wr_reg8(info, CCR, (unsigned char)val); 4434 4435 if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL)) 4436 { 4437 // program DPLL mode 4438 switch(info->params.encoding) 4439 { 4440 case HDLC_ENCODING_BIPHASE_MARK: 4441 case HDLC_ENCODING_BIPHASE_SPACE: 4442 val = BIT7; break; 4443 case HDLC_ENCODING_BIPHASE_LEVEL: 4444 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: 4445 val = BIT7 + BIT6; break; 4446 default: val = BIT6; // NRZ encodings 4447 } 4448 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val)); 4449 4450 // DPLL requires a 16X reference clock from BRG 4451 set_rate(info, info->params.clock_speed * 16); 4452 } 4453 else 4454 set_rate(info, info->params.clock_speed); 4455 4456 tx_set_idle(info); 4457 4458 msc_set_vcr(info); 4459 4460 /* SCR (serial control) 4461 * 4462 * 15 1=tx req on FIFO half empty 4463 * 14 1=rx req on FIFO half full 4464 * 13 tx data IRQ enable 4465 * 12 tx idle IRQ enable 4466 * 11 underrun IRQ enable 4467 * 10 rx data IRQ enable 4468 * 09 rx idle IRQ enable 4469 * 08 overrun IRQ enable 4470 * 07 DSR IRQ enable 4471 * 06 CTS IRQ enable 4472 * 05 DCD IRQ enable 4473 * 04 RI IRQ enable 4474 * 03 reserved, must be zero 4475 * 02 1=txd->rxd internal loopback enable 4476 * 01 reserved, must be zero 4477 * 00 1=master IRQ enable 4478 */ 4479 wr_reg16(info, SCR, BIT15 + BIT14 + BIT0); 4480 4481 if (info->params.loopback) 4482 enable_loopback(info); 4483 } 4484 4485 /* 4486 * set transmit idle mode 4487 */ 4488 static void tx_set_idle(struct slgt_info *info) 4489 { 4490 unsigned char val; 4491 unsigned short tcr; 4492 4493 /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits 4494 * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits 4495 */ 4496 tcr = rd_reg16(info, TCR); 4497 if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) { 4498 /* disable preamble, set idle size to 16 bits */ 4499 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4; 4500 /* MSB of 16 bit idle specified in tx preamble register (TPR) */ 4501 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff)); 4502 } else if (!(tcr & BIT6)) { 4503 /* preamble is disabled, set idle size to 8 bits */ 4504 tcr &= ~(BIT5 + BIT4); 4505 } 4506 wr_reg16(info, TCR, tcr); 4507 4508 if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) { 4509 /* LSB of custom tx idle specified in tx idle register */ 4510 val = (unsigned char)(info->idle_mode & 0xff); 4511 } else { 4512 /* standard 8 bit idle patterns */ 4513 switch(info->idle_mode) 4514 { 4515 case HDLC_TXIDLE_FLAGS: val = 0x7e; break; 4516 case HDLC_TXIDLE_ALT_ZEROS_ONES: 4517 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break; 4518 case HDLC_TXIDLE_ZEROS: 4519 case HDLC_TXIDLE_SPACE: val = 0x00; break; 4520 default: val = 0xff; 4521 } 4522 } 4523 4524 wr_reg8(info, TIR, val); 4525 } 4526 4527 /* 4528 * get state of V24 status (input) signals 4529 */ 4530 static void get_signals(struct slgt_info *info) 4531 { 4532 unsigned short status = rd_reg16(info, SSR); 4533 4534 /* clear all serial signals except RTS and DTR */ 4535 info->signals &= SerialSignal_RTS | SerialSignal_DTR; 4536 4537 if (status & BIT3) 4538 info->signals |= SerialSignal_DSR; 4539 if (status & BIT2) 4540 info->signals |= SerialSignal_CTS; 4541 if (status & BIT1) 4542 info->signals |= SerialSignal_DCD; 4543 if (status & BIT0) 4544 info->signals |= SerialSignal_RI; 4545 } 4546 4547 /* 4548 * set V.24 Control Register based on current configuration 4549 */ 4550 static void msc_set_vcr(struct slgt_info *info) 4551 { 4552 unsigned char val = 0; 4553 4554 /* VCR (V.24 control) 4555 * 4556 * 07..04 serial IF select 4557 * 03 DTR 4558 * 02 RTS 4559 * 01 LL 4560 * 00 RL 4561 */ 4562 4563 switch(info->if_mode & MGSL_INTERFACE_MASK) 4564 { 4565 case MGSL_INTERFACE_RS232: 4566 val |= BIT5; /* 0010 */ 4567 break; 4568 case MGSL_INTERFACE_V35: 4569 val |= BIT7 + BIT6 + BIT5; /* 1110 */ 4570 break; 4571 case MGSL_INTERFACE_RS422: 4572 val |= BIT6; /* 0100 */ 4573 break; 4574 } 4575 4576 if (info->if_mode & MGSL_INTERFACE_MSB_FIRST) 4577 val |= BIT4; 4578 if (info->signals & SerialSignal_DTR) 4579 val |= BIT3; 4580 if (info->signals & SerialSignal_RTS) 4581 val |= BIT2; 4582 if (info->if_mode & MGSL_INTERFACE_LL) 4583 val |= BIT1; 4584 if (info->if_mode & MGSL_INTERFACE_RL) 4585 val |= BIT0; 4586 wr_reg8(info, VCR, val); 4587 } 4588 4589 /* 4590 * set state of V24 control (output) signals 4591 */ 4592 static void set_signals(struct slgt_info *info) 4593 { 4594 unsigned char val = rd_reg8(info, VCR); 4595 if (info->signals & SerialSignal_DTR) 4596 val |= BIT3; 4597 else 4598 val &= ~BIT3; 4599 if (info->signals & SerialSignal_RTS) 4600 val |= BIT2; 4601 else 4602 val &= ~BIT2; 4603 wr_reg8(info, VCR, val); 4604 } 4605 4606 /* 4607 * free range of receive DMA buffers (i to last) 4608 */ 4609 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last) 4610 { 4611 int done = 0; 4612 4613 while(!done) { 4614 /* reset current buffer for reuse */ 4615 info->rbufs[i].status = 0; 4616 set_desc_count(info->rbufs[i], info->rbuf_fill_level); 4617 if (i == last) 4618 done = 1; 4619 if (++i == info->rbuf_count) 4620 i = 0; 4621 } 4622 info->rbuf_current = i; 4623 } 4624 4625 /* 4626 * mark all receive DMA buffers as free 4627 */ 4628 static void reset_rbufs(struct slgt_info *info) 4629 { 4630 free_rbufs(info, 0, info->rbuf_count - 1); 4631 info->rbuf_fill_index = 0; 4632 info->rbuf_fill_count = 0; 4633 } 4634 4635 /* 4636 * pass receive HDLC frame to upper layer 4637 * 4638 * return true if frame available, otherwise false 4639 */ 4640 static bool rx_get_frame(struct slgt_info *info) 4641 { 4642 unsigned int start, end; 4643 unsigned short status; 4644 unsigned int framesize = 0; 4645 unsigned long flags; 4646 struct tty_struct *tty = info->port.tty; 4647 unsigned char addr_field = 0xff; 4648 unsigned int crc_size = 0; 4649 4650 switch (info->params.crc_type & HDLC_CRC_MASK) { 4651 case HDLC_CRC_16_CCITT: crc_size = 2; break; 4652 case HDLC_CRC_32_CCITT: crc_size = 4; break; 4653 } 4654 4655 check_again: 4656 4657 framesize = 0; 4658 addr_field = 0xff; 4659 start = end = info->rbuf_current; 4660 4661 for (;;) { 4662 if (!desc_complete(info->rbufs[end])) 4663 goto cleanup; 4664 4665 if (framesize == 0 && info->params.addr_filter != 0xff) 4666 addr_field = info->rbufs[end].buf[0]; 4667 4668 framesize += desc_count(info->rbufs[end]); 4669 4670 if (desc_eof(info->rbufs[end])) 4671 break; 4672 4673 if (++end == info->rbuf_count) 4674 end = 0; 4675 4676 if (end == info->rbuf_current) { 4677 if (info->rx_enabled){ 4678 spin_lock_irqsave(&info->lock,flags); 4679 rx_start(info); 4680 spin_unlock_irqrestore(&info->lock,flags); 4681 } 4682 goto cleanup; 4683 } 4684 } 4685 4686 /* status 4687 * 4688 * 15 buffer complete 4689 * 14..06 reserved 4690 * 05..04 residue 4691 * 02 eof (end of frame) 4692 * 01 CRC error 4693 * 00 abort 4694 */ 4695 status = desc_status(info->rbufs[end]); 4696 4697 /* ignore CRC bit if not using CRC (bit is undefined) */ 4698 if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE) 4699 status &= ~BIT1; 4700 4701 if (framesize == 0 || 4702 (addr_field != 0xff && addr_field != info->params.addr_filter)) { 4703 free_rbufs(info, start, end); 4704 goto check_again; 4705 } 4706 4707 if (framesize < (2 + crc_size) || status & BIT0) { 4708 info->icount.rxshort++; 4709 framesize = 0; 4710 } else if (status & BIT1) { 4711 info->icount.rxcrc++; 4712 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) 4713 framesize = 0; 4714 } 4715 4716 #if SYNCLINK_GENERIC_HDLC 4717 if (framesize == 0) { 4718 info->netdev->stats.rx_errors++; 4719 info->netdev->stats.rx_frame_errors++; 4720 } 4721 #endif 4722 4723 DBGBH(("%s rx frame status=%04X size=%d\n", 4724 info->device_name, status, framesize)); 4725 DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx"); 4726 4727 if (framesize) { 4728 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) { 4729 framesize -= crc_size; 4730 crc_size = 0; 4731 } 4732 4733 if (framesize > info->max_frame_size + crc_size) 4734 info->icount.rxlong++; 4735 else { 4736 /* copy dma buffer(s) to contiguous temp buffer */ 4737 int copy_count = framesize; 4738 int i = start; 4739 unsigned char *p = info->tmp_rbuf; 4740 info->tmp_rbuf_count = framesize; 4741 4742 info->icount.rxok++; 4743 4744 while(copy_count) { 4745 int partial_count = min_t(int, copy_count, info->rbuf_fill_level); 4746 memcpy(p, info->rbufs[i].buf, partial_count); 4747 p += partial_count; 4748 copy_count -= partial_count; 4749 if (++i == info->rbuf_count) 4750 i = 0; 4751 } 4752 4753 if (info->params.crc_type & HDLC_CRC_RETURN_EX) { 4754 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK; 4755 framesize++; 4756 } 4757 4758 #if SYNCLINK_GENERIC_HDLC 4759 if (info->netcount) 4760 hdlcdev_rx(info,info->tmp_rbuf, framesize); 4761 else 4762 #endif 4763 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize); 4764 } 4765 } 4766 free_rbufs(info, start, end); 4767 return true; 4768 4769 cleanup: 4770 return false; 4771 } 4772 4773 /* 4774 * pass receive buffer (RAW synchronous mode) to tty layer 4775 * return true if buffer available, otherwise false 4776 */ 4777 static bool rx_get_buf(struct slgt_info *info) 4778 { 4779 unsigned int i = info->rbuf_current; 4780 unsigned int count; 4781 4782 if (!desc_complete(info->rbufs[i])) 4783 return false; 4784 count = desc_count(info->rbufs[i]); 4785 switch(info->params.mode) { 4786 case MGSL_MODE_MONOSYNC: 4787 case MGSL_MODE_BISYNC: 4788 case MGSL_MODE_XSYNC: 4789 /* ignore residue in byte synchronous modes */ 4790 if (desc_residue(info->rbufs[i])) 4791 count--; 4792 break; 4793 } 4794 DBGDATA(info, info->rbufs[i].buf, count, "rx"); 4795 DBGINFO(("rx_get_buf size=%d\n", count)); 4796 if (count) 4797 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf, 4798 info->flag_buf, count); 4799 free_rbufs(info, i, i); 4800 return true; 4801 } 4802 4803 static void reset_tbufs(struct slgt_info *info) 4804 { 4805 unsigned int i; 4806 info->tbuf_current = 0; 4807 for (i=0 ; i < info->tbuf_count ; i++) { 4808 info->tbufs[i].status = 0; 4809 info->tbufs[i].count = 0; 4810 } 4811 } 4812 4813 /* 4814 * return number of free transmit DMA buffers 4815 */ 4816 static unsigned int free_tbuf_count(struct slgt_info *info) 4817 { 4818 unsigned int count = 0; 4819 unsigned int i = info->tbuf_current; 4820 4821 do 4822 { 4823 if (desc_count(info->tbufs[i])) 4824 break; /* buffer in use */ 4825 ++count; 4826 if (++i == info->tbuf_count) 4827 i=0; 4828 } while (i != info->tbuf_current); 4829 4830 /* if tx DMA active, last zero count buffer is in use */ 4831 if (count && (rd_reg32(info, TDCSR) & BIT0)) 4832 --count; 4833 4834 return count; 4835 } 4836 4837 /* 4838 * return number of bytes in unsent transmit DMA buffers 4839 * and the serial controller tx FIFO 4840 */ 4841 static unsigned int tbuf_bytes(struct slgt_info *info) 4842 { 4843 unsigned int total_count = 0; 4844 unsigned int i = info->tbuf_current; 4845 unsigned int reg_value; 4846 unsigned int count; 4847 unsigned int active_buf_count = 0; 4848 4849 /* 4850 * Add descriptor counts for all tx DMA buffers. 4851 * If count is zero (cleared by DMA controller after read), 4852 * the buffer is complete or is actively being read from. 4853 * 4854 * Record buf_count of last buffer with zero count starting 4855 * from current ring position. buf_count is mirror 4856 * copy of count and is not cleared by serial controller. 4857 * If DMA controller is active, that buffer is actively 4858 * being read so add to total. 4859 */ 4860 do { 4861 count = desc_count(info->tbufs[i]); 4862 if (count) 4863 total_count += count; 4864 else if (!total_count) 4865 active_buf_count = info->tbufs[i].buf_count; 4866 if (++i == info->tbuf_count) 4867 i = 0; 4868 } while (i != info->tbuf_current); 4869 4870 /* read tx DMA status register */ 4871 reg_value = rd_reg32(info, TDCSR); 4872 4873 /* if tx DMA active, last zero count buffer is in use */ 4874 if (reg_value & BIT0) 4875 total_count += active_buf_count; 4876 4877 /* add tx FIFO count = reg_value[15..8] */ 4878 total_count += (reg_value >> 8) & 0xff; 4879 4880 /* if transmitter active add one byte for shift register */ 4881 if (info->tx_active) 4882 total_count++; 4883 4884 return total_count; 4885 } 4886 4887 /* 4888 * load data into transmit DMA buffer ring and start transmitter if needed 4889 * return true if data accepted, otherwise false (buffers full) 4890 */ 4891 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int size) 4892 { 4893 unsigned short count; 4894 unsigned int i; 4895 struct slgt_desc *d; 4896 4897 /* check required buffer space */ 4898 if (DIV_ROUND_UP(size, DMABUFSIZE) > free_tbuf_count(info)) 4899 return false; 4900 4901 DBGDATA(info, buf, size, "tx"); 4902 4903 /* 4904 * copy data to one or more DMA buffers in circular ring 4905 * tbuf_start = first buffer for this data 4906 * tbuf_current = next free buffer 4907 * 4908 * Copy all data before making data visible to DMA controller by 4909 * setting descriptor count of the first buffer. 4910 * This prevents an active DMA controller from reading the first DMA 4911 * buffers of a frame and stopping before the final buffers are filled. 4912 */ 4913 4914 info->tbuf_start = i = info->tbuf_current; 4915 4916 while (size) { 4917 d = &info->tbufs[i]; 4918 4919 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size); 4920 memcpy(d->buf, buf, count); 4921 4922 size -= count; 4923 buf += count; 4924 4925 /* 4926 * set EOF bit for last buffer of HDLC frame or 4927 * for every buffer in raw mode 4928 */ 4929 if ((!size && info->params.mode == MGSL_MODE_HDLC) || 4930 info->params.mode == MGSL_MODE_RAW) 4931 set_desc_eof(*d, 1); 4932 else 4933 set_desc_eof(*d, 0); 4934 4935 /* set descriptor count for all but first buffer */ 4936 if (i != info->tbuf_start) 4937 set_desc_count(*d, count); 4938 d->buf_count = count; 4939 4940 if (++i == info->tbuf_count) 4941 i = 0; 4942 } 4943 4944 info->tbuf_current = i; 4945 4946 /* set first buffer count to make new data visible to DMA controller */ 4947 d = &info->tbufs[info->tbuf_start]; 4948 set_desc_count(*d, d->buf_count); 4949 4950 /* start transmitter if needed and update transmit timeout */ 4951 if (!info->tx_active) 4952 tx_start(info); 4953 update_tx_timer(info); 4954 4955 return true; 4956 } 4957 4958 static int register_test(struct slgt_info *info) 4959 { 4960 static unsigned short patterns[] = 4961 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696}; 4962 static unsigned int count = ARRAY_SIZE(patterns); 4963 unsigned int i; 4964 int rc = 0; 4965 4966 for (i=0 ; i < count ; i++) { 4967 wr_reg16(info, TIR, patterns[i]); 4968 wr_reg16(info, BDR, patterns[(i+1)%count]); 4969 if ((rd_reg16(info, TIR) != patterns[i]) || 4970 (rd_reg16(info, BDR) != patterns[(i+1)%count])) { 4971 rc = -ENODEV; 4972 break; 4973 } 4974 } 4975 info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0; 4976 info->init_error = rc ? 0 : DiagStatus_AddressFailure; 4977 return rc; 4978 } 4979 4980 static int irq_test(struct slgt_info *info) 4981 { 4982 unsigned long timeout; 4983 unsigned long flags; 4984 struct tty_struct *oldtty = info->port.tty; 4985 u32 speed = info->params.data_rate; 4986 4987 info->params.data_rate = 921600; 4988 info->port.tty = NULL; 4989 4990 spin_lock_irqsave(&info->lock, flags); 4991 async_mode(info); 4992 slgt_irq_on(info, IRQ_TXIDLE); 4993 4994 /* enable transmitter */ 4995 wr_reg16(info, TCR, 4996 (unsigned short)(rd_reg16(info, TCR) | BIT1)); 4997 4998 /* write one byte and wait for tx idle */ 4999 wr_reg16(info, TDR, 0); 5000 5001 /* assume failure */ 5002 info->init_error = DiagStatus_IrqFailure; 5003 info->irq_occurred = false; 5004 5005 spin_unlock_irqrestore(&info->lock, flags); 5006 5007 timeout=100; 5008 while(timeout-- && !info->irq_occurred) 5009 msleep_interruptible(10); 5010 5011 spin_lock_irqsave(&info->lock,flags); 5012 reset_port(info); 5013 spin_unlock_irqrestore(&info->lock,flags); 5014 5015 info->params.data_rate = speed; 5016 info->port.tty = oldtty; 5017 5018 info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure; 5019 return info->irq_occurred ? 0 : -ENODEV; 5020 } 5021 5022 static int loopback_test_rx(struct slgt_info *info) 5023 { 5024 unsigned char *src, *dest; 5025 int count; 5026 5027 if (desc_complete(info->rbufs[0])) { 5028 count = desc_count(info->rbufs[0]); 5029 src = info->rbufs[0].buf; 5030 dest = info->tmp_rbuf; 5031 5032 for( ; count ; count-=2, src+=2) { 5033 /* src=data byte (src+1)=status byte */ 5034 if (!(*(src+1) & (BIT9 + BIT8))) { 5035 *dest = *src; 5036 dest++; 5037 info->tmp_rbuf_count++; 5038 } 5039 } 5040 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx"); 5041 return 1; 5042 } 5043 return 0; 5044 } 5045 5046 static int loopback_test(struct slgt_info *info) 5047 { 5048 #define TESTFRAMESIZE 20 5049 5050 unsigned long timeout; 5051 u16 count = TESTFRAMESIZE; 5052 unsigned char buf[TESTFRAMESIZE]; 5053 int rc = -ENODEV; 5054 unsigned long flags; 5055 5056 struct tty_struct *oldtty = info->port.tty; 5057 MGSL_PARAMS params; 5058 5059 memcpy(¶ms, &info->params, sizeof(params)); 5060 5061 info->params.mode = MGSL_MODE_ASYNC; 5062 info->params.data_rate = 921600; 5063 info->params.loopback = 1; 5064 info->port.tty = NULL; 5065 5066 /* build and send transmit frame */ 5067 for (count = 0; count < TESTFRAMESIZE; ++count) 5068 buf[count] = (unsigned char)count; 5069 5070 info->tmp_rbuf_count = 0; 5071 memset(info->tmp_rbuf, 0, TESTFRAMESIZE); 5072 5073 /* program hardware for HDLC and enabled receiver */ 5074 spin_lock_irqsave(&info->lock,flags); 5075 async_mode(info); 5076 rx_start(info); 5077 tx_load(info, buf, count); 5078 spin_unlock_irqrestore(&info->lock, flags); 5079 5080 /* wait for receive complete */ 5081 for (timeout = 100; timeout; --timeout) { 5082 msleep_interruptible(10); 5083 if (loopback_test_rx(info)) { 5084 rc = 0; 5085 break; 5086 } 5087 } 5088 5089 /* verify received frame length and contents */ 5090 if (!rc && (info->tmp_rbuf_count != count || 5091 memcmp(buf, info->tmp_rbuf, count))) { 5092 rc = -ENODEV; 5093 } 5094 5095 spin_lock_irqsave(&info->lock,flags); 5096 reset_adapter(info); 5097 spin_unlock_irqrestore(&info->lock,flags); 5098 5099 memcpy(&info->params, ¶ms, sizeof(info->params)); 5100 info->port.tty = oldtty; 5101 5102 info->init_error = rc ? DiagStatus_DmaFailure : 0; 5103 return rc; 5104 } 5105 5106 static int adapter_test(struct slgt_info *info) 5107 { 5108 DBGINFO(("testing %s\n", info->device_name)); 5109 if (register_test(info) < 0) { 5110 printk("register test failure %s addr=%08X\n", 5111 info->device_name, info->phys_reg_addr); 5112 } else if (irq_test(info) < 0) { 5113 printk("IRQ test failure %s IRQ=%d\n", 5114 info->device_name, info->irq_level); 5115 } else if (loopback_test(info) < 0) { 5116 printk("loopback test failure %s\n", info->device_name); 5117 } 5118 return info->init_error; 5119 } 5120 5121 /* 5122 * transmit timeout handler 5123 */ 5124 static void tx_timeout(unsigned long context) 5125 { 5126 struct slgt_info *info = (struct slgt_info*)context; 5127 unsigned long flags; 5128 5129 DBGINFO(("%s tx_timeout\n", info->device_name)); 5130 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) { 5131 info->icount.txtimeout++; 5132 } 5133 spin_lock_irqsave(&info->lock,flags); 5134 tx_stop(info); 5135 spin_unlock_irqrestore(&info->lock,flags); 5136 5137 #if SYNCLINK_GENERIC_HDLC 5138 if (info->netcount) 5139 hdlcdev_tx_done(info); 5140 else 5141 #endif 5142 bh_transmit(info); 5143 } 5144 5145 /* 5146 * receive buffer polling timer 5147 */ 5148 static void rx_timeout(unsigned long context) 5149 { 5150 struct slgt_info *info = (struct slgt_info*)context; 5151 unsigned long flags; 5152 5153 DBGINFO(("%s rx_timeout\n", info->device_name)); 5154 spin_lock_irqsave(&info->lock, flags); 5155 info->pending_bh |= BH_RECEIVE; 5156 spin_unlock_irqrestore(&info->lock, flags); 5157 bh_handler(&info->task); 5158 } 5159 5160