1 // SPDX-License-Identifier: GPL-1.0+ 2 /* 3 * Device driver for Microgate SyncLink GT serial adapters. 4 * 5 * written by Paul Fulghum for Microgate Corporation 6 * paulkf@microgate.com 7 * 8 * Microgate and SyncLink are trademarks of Microgate Corporation 9 * 10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 12 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 13 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 14 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 15 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 16 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 17 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 18 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 19 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 20 * OF THE POSSIBILITY OF SUCH DAMAGE. 21 */ 22 23 /* 24 * DEBUG OUTPUT DEFINITIONS 25 * 26 * uncomment lines below to enable specific types of debug output 27 * 28 * DBGINFO information - most verbose output 29 * DBGERR serious errors 30 * DBGBH bottom half service routine debugging 31 * DBGISR interrupt service routine debugging 32 * DBGDATA output receive and transmit data 33 * DBGTBUF output transmit DMA buffers and registers 34 * DBGRBUF output receive DMA buffers and registers 35 */ 36 37 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt 38 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt 39 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt 40 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt 41 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label)) 42 /*#define DBGTBUF(info) dump_tbufs(info)*/ 43 /*#define DBGRBUF(info) dump_rbufs(info)*/ 44 45 46 #include <linux/module.h> 47 #include <linux/errno.h> 48 #include <linux/signal.h> 49 #include <linux/sched.h> 50 #include <linux/timer.h> 51 #include <linux/interrupt.h> 52 #include <linux/pci.h> 53 #include <linux/tty.h> 54 #include <linux/tty_flip.h> 55 #include <linux/serial.h> 56 #include <linux/major.h> 57 #include <linux/string.h> 58 #include <linux/fcntl.h> 59 #include <linux/ptrace.h> 60 #include <linux/ioport.h> 61 #include <linux/mm.h> 62 #include <linux/seq_file.h> 63 #include <linux/slab.h> 64 #include <linux/netdevice.h> 65 #include <linux/vmalloc.h> 66 #include <linux/init.h> 67 #include <linux/delay.h> 68 #include <linux/ioctl.h> 69 #include <linux/termios.h> 70 #include <linux/bitops.h> 71 #include <linux/workqueue.h> 72 #include <linux/hdlc.h> 73 #include <linux/synclink.h> 74 75 #include <asm/io.h> 76 #include <asm/irq.h> 77 #include <asm/dma.h> 78 #include <asm/types.h> 79 #include <linux/uaccess.h> 80 81 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE)) 82 #define SYNCLINK_GENERIC_HDLC 1 83 #else 84 #define SYNCLINK_GENERIC_HDLC 0 85 #endif 86 87 /* 88 * module identification 89 */ 90 static char *driver_name = "SyncLink GT"; 91 static char *slgt_driver_name = "synclink_gt"; 92 static char *tty_dev_prefix = "ttySLG"; 93 MODULE_LICENSE("GPL"); 94 #define MGSL_MAGIC 0x5401 95 #define MAX_DEVICES 32 96 97 static const struct pci_device_id pci_table[] = { 98 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, 99 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, 100 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, 101 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, 102 {0,}, /* terminate list */ 103 }; 104 MODULE_DEVICE_TABLE(pci, pci_table); 105 106 static int init_one(struct pci_dev *dev,const struct pci_device_id *ent); 107 static void remove_one(struct pci_dev *dev); 108 static struct pci_driver pci_driver = { 109 .name = "synclink_gt", 110 .id_table = pci_table, 111 .probe = init_one, 112 .remove = remove_one, 113 }; 114 115 static bool pci_registered; 116 117 /* 118 * module configuration and status 119 */ 120 static struct slgt_info *slgt_device_list; 121 static int slgt_device_count; 122 123 static int ttymajor; 124 static int debug_level; 125 static int maxframe[MAX_DEVICES]; 126 127 module_param(ttymajor, int, 0); 128 module_param(debug_level, int, 0); 129 module_param_array(maxframe, int, NULL, 0); 130 131 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned"); 132 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail"); 133 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)"); 134 135 /* 136 * tty support and callbacks 137 */ 138 static struct tty_driver *serial_driver; 139 140 static int open(struct tty_struct *tty, struct file * filp); 141 static void close(struct tty_struct *tty, struct file * filp); 142 static void hangup(struct tty_struct *tty); 143 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios); 144 145 static int write(struct tty_struct *tty, const unsigned char *buf, int count); 146 static int put_char(struct tty_struct *tty, unsigned char ch); 147 static void send_xchar(struct tty_struct *tty, char ch); 148 static void wait_until_sent(struct tty_struct *tty, int timeout); 149 static int write_room(struct tty_struct *tty); 150 static void flush_chars(struct tty_struct *tty); 151 static void flush_buffer(struct tty_struct *tty); 152 static void tx_hold(struct tty_struct *tty); 153 static void tx_release(struct tty_struct *tty); 154 155 static int ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg); 156 static int chars_in_buffer(struct tty_struct *tty); 157 static void throttle(struct tty_struct * tty); 158 static void unthrottle(struct tty_struct * tty); 159 static int set_break(struct tty_struct *tty, int break_state); 160 161 /* 162 * generic HDLC support and callbacks 163 */ 164 #if SYNCLINK_GENERIC_HDLC 165 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 166 static void hdlcdev_tx_done(struct slgt_info *info); 167 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size); 168 static int hdlcdev_init(struct slgt_info *info); 169 static void hdlcdev_exit(struct slgt_info *info); 170 #endif 171 172 173 /* 174 * device specific structures, macros and functions 175 */ 176 177 #define SLGT_MAX_PORTS 4 178 #define SLGT_REG_SIZE 256 179 180 /* 181 * conditional wait facility 182 */ 183 struct cond_wait { 184 struct cond_wait *next; 185 wait_queue_head_t q; 186 wait_queue_entry_t wait; 187 unsigned int data; 188 }; 189 static void init_cond_wait(struct cond_wait *w, unsigned int data); 190 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w); 191 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w); 192 static void flush_cond_wait(struct cond_wait **head); 193 194 /* 195 * DMA buffer descriptor and access macros 196 */ 197 struct slgt_desc 198 { 199 __le16 count; 200 __le16 status; 201 __le32 pbuf; /* physical address of data buffer */ 202 __le32 next; /* physical address of next descriptor */ 203 204 /* driver book keeping */ 205 char *buf; /* virtual address of data buffer */ 206 unsigned int pdesc; /* physical address of this descriptor */ 207 dma_addr_t buf_dma_addr; 208 unsigned short buf_count; 209 }; 210 211 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b)) 212 #define set_desc_next(a,b) (a).next = cpu_to_le32((unsigned int)(b)) 213 #define set_desc_count(a,b)(a).count = cpu_to_le16((unsigned short)(b)) 214 #define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0)) 215 #define set_desc_status(a, b) (a).status = cpu_to_le16((unsigned short)(b)) 216 #define desc_count(a) (le16_to_cpu((a).count)) 217 #define desc_status(a) (le16_to_cpu((a).status)) 218 #define desc_complete(a) (le16_to_cpu((a).status) & BIT15) 219 #define desc_eof(a) (le16_to_cpu((a).status) & BIT2) 220 #define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1) 221 #define desc_abort(a) (le16_to_cpu((a).status) & BIT0) 222 #define desc_residue(a) ((le16_to_cpu((a).status) & 0x38) >> 3) 223 224 struct _input_signal_events { 225 int ri_up; 226 int ri_down; 227 int dsr_up; 228 int dsr_down; 229 int dcd_up; 230 int dcd_down; 231 int cts_up; 232 int cts_down; 233 }; 234 235 /* 236 * device instance data structure 237 */ 238 struct slgt_info { 239 void *if_ptr; /* General purpose pointer (used by SPPP) */ 240 struct tty_port port; 241 242 struct slgt_info *next_device; /* device list link */ 243 244 int magic; 245 246 char device_name[25]; 247 struct pci_dev *pdev; 248 249 int port_count; /* count of ports on adapter */ 250 int adapter_num; /* adapter instance number */ 251 int port_num; /* port instance number */ 252 253 /* array of pointers to port contexts on this adapter */ 254 struct slgt_info *port_array[SLGT_MAX_PORTS]; 255 256 int line; /* tty line instance number */ 257 258 struct mgsl_icount icount; 259 260 int timeout; 261 int x_char; /* xon/xoff character */ 262 unsigned int read_status_mask; 263 unsigned int ignore_status_mask; 264 265 wait_queue_head_t status_event_wait_q; 266 wait_queue_head_t event_wait_q; 267 struct timer_list tx_timer; 268 struct timer_list rx_timer; 269 270 unsigned int gpio_present; 271 struct cond_wait *gpio_wait_q; 272 273 spinlock_t lock; /* spinlock for synchronizing with ISR */ 274 275 struct work_struct task; 276 u32 pending_bh; 277 bool bh_requested; 278 bool bh_running; 279 280 int isr_overflow; 281 bool irq_requested; /* true if IRQ requested */ 282 bool irq_occurred; /* for diagnostics use */ 283 284 /* device configuration */ 285 286 unsigned int bus_type; 287 unsigned int irq_level; 288 unsigned long irq_flags; 289 290 unsigned char __iomem * reg_addr; /* memory mapped registers address */ 291 u32 phys_reg_addr; 292 bool reg_addr_requested; 293 294 MGSL_PARAMS params; /* communications parameters */ 295 u32 idle_mode; 296 u32 max_frame_size; /* as set by device config */ 297 298 unsigned int rbuf_fill_level; 299 unsigned int rx_pio; 300 unsigned int if_mode; 301 unsigned int base_clock; 302 unsigned int xsync; 303 unsigned int xctrl; 304 305 /* device status */ 306 307 bool rx_enabled; 308 bool rx_restart; 309 310 bool tx_enabled; 311 bool tx_active; 312 313 unsigned char signals; /* serial signal states */ 314 int init_error; /* initialization error */ 315 316 unsigned char *tx_buf; 317 int tx_count; 318 319 char *flag_buf; 320 bool drop_rts_on_tx_done; 321 struct _input_signal_events input_signal_events; 322 323 int dcd_chkcount; /* check counts to prevent */ 324 int cts_chkcount; /* too many IRQs if a signal */ 325 int dsr_chkcount; /* is floating */ 326 int ri_chkcount; 327 328 char *bufs; /* virtual address of DMA buffer lists */ 329 dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */ 330 331 unsigned int rbuf_count; 332 struct slgt_desc *rbufs; 333 unsigned int rbuf_current; 334 unsigned int rbuf_index; 335 unsigned int rbuf_fill_index; 336 unsigned short rbuf_fill_count; 337 338 unsigned int tbuf_count; 339 struct slgt_desc *tbufs; 340 unsigned int tbuf_current; 341 unsigned int tbuf_start; 342 343 unsigned char *tmp_rbuf; 344 unsigned int tmp_rbuf_count; 345 346 /* SPPP/Cisco HDLC device parts */ 347 348 int netcount; 349 spinlock_t netlock; 350 #if SYNCLINK_GENERIC_HDLC 351 struct net_device *netdev; 352 #endif 353 354 }; 355 356 static MGSL_PARAMS default_params = { 357 .mode = MGSL_MODE_HDLC, 358 .loopback = 0, 359 .flags = HDLC_FLAG_UNDERRUN_ABORT15, 360 .encoding = HDLC_ENCODING_NRZI_SPACE, 361 .clock_speed = 0, 362 .addr_filter = 0xff, 363 .crc_type = HDLC_CRC_16_CCITT, 364 .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS, 365 .preamble = HDLC_PREAMBLE_PATTERN_NONE, 366 .data_rate = 9600, 367 .data_bits = 8, 368 .stop_bits = 1, 369 .parity = ASYNC_PARITY_NONE 370 }; 371 372 373 #define BH_RECEIVE 1 374 #define BH_TRANSMIT 2 375 #define BH_STATUS 4 376 #define IO_PIN_SHUTDOWN_LIMIT 100 377 378 #define DMABUFSIZE 256 379 #define DESC_LIST_SIZE 4096 380 381 #define MASK_PARITY BIT1 382 #define MASK_FRAMING BIT0 383 #define MASK_BREAK BIT14 384 #define MASK_OVERRUN BIT4 385 386 #define GSR 0x00 /* global status */ 387 #define JCR 0x04 /* JTAG control */ 388 #define IODR 0x08 /* GPIO direction */ 389 #define IOER 0x0c /* GPIO interrupt enable */ 390 #define IOVR 0x10 /* GPIO value */ 391 #define IOSR 0x14 /* GPIO interrupt status */ 392 #define TDR 0x80 /* tx data */ 393 #define RDR 0x80 /* rx data */ 394 #define TCR 0x82 /* tx control */ 395 #define TIR 0x84 /* tx idle */ 396 #define TPR 0x85 /* tx preamble */ 397 #define RCR 0x86 /* rx control */ 398 #define VCR 0x88 /* V.24 control */ 399 #define CCR 0x89 /* clock control */ 400 #define BDR 0x8a /* baud divisor */ 401 #define SCR 0x8c /* serial control */ 402 #define SSR 0x8e /* serial status */ 403 #define RDCSR 0x90 /* rx DMA control/status */ 404 #define TDCSR 0x94 /* tx DMA control/status */ 405 #define RDDAR 0x98 /* rx DMA descriptor address */ 406 #define TDDAR 0x9c /* tx DMA descriptor address */ 407 #define XSR 0x40 /* extended sync pattern */ 408 #define XCR 0x44 /* extended control */ 409 410 #define RXIDLE BIT14 411 #define RXBREAK BIT14 412 #define IRQ_TXDATA BIT13 413 #define IRQ_TXIDLE BIT12 414 #define IRQ_TXUNDER BIT11 /* HDLC */ 415 #define IRQ_RXDATA BIT10 416 #define IRQ_RXIDLE BIT9 /* HDLC */ 417 #define IRQ_RXBREAK BIT9 /* async */ 418 #define IRQ_RXOVER BIT8 419 #define IRQ_DSR BIT7 420 #define IRQ_CTS BIT6 421 #define IRQ_DCD BIT5 422 #define IRQ_RI BIT4 423 #define IRQ_ALL 0x3ff0 424 #define IRQ_MASTER BIT0 425 426 #define slgt_irq_on(info, mask) \ 427 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask))) 428 #define slgt_irq_off(info, mask) \ 429 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask))) 430 431 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr); 432 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value); 433 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr); 434 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value); 435 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr); 436 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value); 437 438 static void msc_set_vcr(struct slgt_info *info); 439 440 static int startup(struct slgt_info *info); 441 static int block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info); 442 static void shutdown(struct slgt_info *info); 443 static void program_hw(struct slgt_info *info); 444 static void change_params(struct slgt_info *info); 445 446 static int register_test(struct slgt_info *info); 447 static int irq_test(struct slgt_info *info); 448 static int loopback_test(struct slgt_info *info); 449 static int adapter_test(struct slgt_info *info); 450 451 static void reset_adapter(struct slgt_info *info); 452 static void reset_port(struct slgt_info *info); 453 static void async_mode(struct slgt_info *info); 454 static void sync_mode(struct slgt_info *info); 455 456 static void rx_stop(struct slgt_info *info); 457 static void rx_start(struct slgt_info *info); 458 static void reset_rbufs(struct slgt_info *info); 459 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last); 460 static void rdma_reset(struct slgt_info *info); 461 static bool rx_get_frame(struct slgt_info *info); 462 static bool rx_get_buf(struct slgt_info *info); 463 464 static void tx_start(struct slgt_info *info); 465 static void tx_stop(struct slgt_info *info); 466 static void tx_set_idle(struct slgt_info *info); 467 static unsigned int free_tbuf_count(struct slgt_info *info); 468 static unsigned int tbuf_bytes(struct slgt_info *info); 469 static void reset_tbufs(struct slgt_info *info); 470 static void tdma_reset(struct slgt_info *info); 471 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int count); 472 473 static void get_signals(struct slgt_info *info); 474 static void set_signals(struct slgt_info *info); 475 static void enable_loopback(struct slgt_info *info); 476 static void set_rate(struct slgt_info *info, u32 data_rate); 477 478 static int bh_action(struct slgt_info *info); 479 static void bh_handler(struct work_struct *work); 480 static void bh_transmit(struct slgt_info *info); 481 static void isr_serial(struct slgt_info *info); 482 static void isr_rdma(struct slgt_info *info); 483 static void isr_txeom(struct slgt_info *info, unsigned short status); 484 static void isr_tdma(struct slgt_info *info); 485 486 static int alloc_dma_bufs(struct slgt_info *info); 487 static void free_dma_bufs(struct slgt_info *info); 488 static int alloc_desc(struct slgt_info *info); 489 static void free_desc(struct slgt_info *info); 490 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count); 491 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count); 492 493 static int alloc_tmp_rbuf(struct slgt_info *info); 494 static void free_tmp_rbuf(struct slgt_info *info); 495 496 static void tx_timeout(struct timer_list *t); 497 static void rx_timeout(struct timer_list *t); 498 499 /* 500 * ioctl handlers 501 */ 502 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount); 503 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *params); 504 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *params); 505 static int get_txidle(struct slgt_info *info, int __user *idle_mode); 506 static int set_txidle(struct slgt_info *info, int idle_mode); 507 static int tx_enable(struct slgt_info *info, int enable); 508 static int tx_abort(struct slgt_info *info); 509 static int rx_enable(struct slgt_info *info, int enable); 510 static int modem_input_wait(struct slgt_info *info,int arg); 511 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr); 512 static int tiocmget(struct tty_struct *tty); 513 static int tiocmset(struct tty_struct *tty, 514 unsigned int set, unsigned int clear); 515 static int set_break(struct tty_struct *tty, int break_state); 516 static int get_interface(struct slgt_info *info, int __user *if_mode); 517 static int set_interface(struct slgt_info *info, int if_mode); 518 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio); 519 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio); 520 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio); 521 static int get_xsync(struct slgt_info *info, int __user *if_mode); 522 static int set_xsync(struct slgt_info *info, int if_mode); 523 static int get_xctrl(struct slgt_info *info, int __user *if_mode); 524 static int set_xctrl(struct slgt_info *info, int if_mode); 525 526 /* 527 * driver functions 528 */ 529 static void add_device(struct slgt_info *info); 530 static void device_init(int adapter_num, struct pci_dev *pdev); 531 static int claim_resources(struct slgt_info *info); 532 static void release_resources(struct slgt_info *info); 533 534 /* 535 * DEBUG OUTPUT CODE 536 */ 537 #ifndef DBGINFO 538 #define DBGINFO(fmt) 539 #endif 540 #ifndef DBGERR 541 #define DBGERR(fmt) 542 #endif 543 #ifndef DBGBH 544 #define DBGBH(fmt) 545 #endif 546 #ifndef DBGISR 547 #define DBGISR(fmt) 548 #endif 549 550 #ifdef DBGDATA 551 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label) 552 { 553 int i; 554 int linecount; 555 printk("%s %s data:\n",info->device_name, label); 556 while(count) { 557 linecount = (count > 16) ? 16 : count; 558 for(i=0; i < linecount; i++) 559 printk("%02X ",(unsigned char)data[i]); 560 for(;i<17;i++) 561 printk(" "); 562 for(i=0;i<linecount;i++) { 563 if (data[i]>=040 && data[i]<=0176) 564 printk("%c",data[i]); 565 else 566 printk("."); 567 } 568 printk("\n"); 569 data += linecount; 570 count -= linecount; 571 } 572 } 573 #else 574 #define DBGDATA(info, buf, size, label) 575 #endif 576 577 #ifdef DBGTBUF 578 static void dump_tbufs(struct slgt_info *info) 579 { 580 int i; 581 printk("tbuf_current=%d\n", info->tbuf_current); 582 for (i=0 ; i < info->tbuf_count ; i++) { 583 printk("%d: count=%04X status=%04X\n", 584 i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status)); 585 } 586 } 587 #else 588 #define DBGTBUF(info) 589 #endif 590 591 #ifdef DBGRBUF 592 static void dump_rbufs(struct slgt_info *info) 593 { 594 int i; 595 printk("rbuf_current=%d\n", info->rbuf_current); 596 for (i=0 ; i < info->rbuf_count ; i++) { 597 printk("%d: count=%04X status=%04X\n", 598 i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status)); 599 } 600 } 601 #else 602 #define DBGRBUF(info) 603 #endif 604 605 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name) 606 { 607 #ifdef SANITY_CHECK 608 if (!info) { 609 printk("null struct slgt_info for (%s) in %s\n", devname, name); 610 return 1; 611 } 612 if (info->magic != MGSL_MAGIC) { 613 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name); 614 return 1; 615 } 616 #else 617 if (!info) 618 return 1; 619 #endif 620 return 0; 621 } 622 623 /* 624 * line discipline callback wrappers 625 * 626 * The wrappers maintain line discipline references 627 * while calling into the line discipline. 628 * 629 * ldisc_receive_buf - pass receive data to line discipline 630 */ 631 static void ldisc_receive_buf(struct tty_struct *tty, 632 const __u8 *data, char *flags, int count) 633 { 634 struct tty_ldisc *ld; 635 if (!tty) 636 return; 637 ld = tty_ldisc_ref(tty); 638 if (ld) { 639 if (ld->ops->receive_buf) 640 ld->ops->receive_buf(tty, data, flags, count); 641 tty_ldisc_deref(ld); 642 } 643 } 644 645 /* tty callbacks */ 646 647 static int open(struct tty_struct *tty, struct file *filp) 648 { 649 struct slgt_info *info; 650 int retval, line; 651 unsigned long flags; 652 653 line = tty->index; 654 if (line >= slgt_device_count) { 655 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line)); 656 return -ENODEV; 657 } 658 659 info = slgt_device_list; 660 while(info && info->line != line) 661 info = info->next_device; 662 if (sanity_check(info, tty->name, "open")) 663 return -ENODEV; 664 if (info->init_error) { 665 DBGERR(("%s init error=%d\n", info->device_name, info->init_error)); 666 return -ENODEV; 667 } 668 669 tty->driver_data = info; 670 info->port.tty = tty; 671 672 DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count)); 673 674 mutex_lock(&info->port.mutex); 675 676 spin_lock_irqsave(&info->netlock, flags); 677 if (info->netcount) { 678 retval = -EBUSY; 679 spin_unlock_irqrestore(&info->netlock, flags); 680 mutex_unlock(&info->port.mutex); 681 goto cleanup; 682 } 683 info->port.count++; 684 spin_unlock_irqrestore(&info->netlock, flags); 685 686 if (info->port.count == 1) { 687 /* 1st open on this device, init hardware */ 688 retval = startup(info); 689 if (retval < 0) { 690 mutex_unlock(&info->port.mutex); 691 goto cleanup; 692 } 693 } 694 mutex_unlock(&info->port.mutex); 695 retval = block_til_ready(tty, filp, info); 696 if (retval) { 697 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval)); 698 goto cleanup; 699 } 700 701 retval = 0; 702 703 cleanup: 704 if (retval) { 705 if (tty->count == 1) 706 info->port.tty = NULL; /* tty layer will release tty struct */ 707 if(info->port.count) 708 info->port.count--; 709 } 710 711 DBGINFO(("%s open rc=%d\n", info->device_name, retval)); 712 return retval; 713 } 714 715 static void close(struct tty_struct *tty, struct file *filp) 716 { 717 struct slgt_info *info = tty->driver_data; 718 719 if (sanity_check(info, tty->name, "close")) 720 return; 721 DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count)); 722 723 if (tty_port_close_start(&info->port, tty, filp) == 0) 724 goto cleanup; 725 726 mutex_lock(&info->port.mutex); 727 if (tty_port_initialized(&info->port)) 728 wait_until_sent(tty, info->timeout); 729 flush_buffer(tty); 730 tty_ldisc_flush(tty); 731 732 shutdown(info); 733 mutex_unlock(&info->port.mutex); 734 735 tty_port_close_end(&info->port, tty); 736 info->port.tty = NULL; 737 cleanup: 738 DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count)); 739 } 740 741 static void hangup(struct tty_struct *tty) 742 { 743 struct slgt_info *info = tty->driver_data; 744 unsigned long flags; 745 746 if (sanity_check(info, tty->name, "hangup")) 747 return; 748 DBGINFO(("%s hangup\n", info->device_name)); 749 750 flush_buffer(tty); 751 752 mutex_lock(&info->port.mutex); 753 shutdown(info); 754 755 spin_lock_irqsave(&info->port.lock, flags); 756 info->port.count = 0; 757 info->port.tty = NULL; 758 spin_unlock_irqrestore(&info->port.lock, flags); 759 tty_port_set_active(&info->port, 0); 760 mutex_unlock(&info->port.mutex); 761 762 wake_up_interruptible(&info->port.open_wait); 763 } 764 765 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios) 766 { 767 struct slgt_info *info = tty->driver_data; 768 unsigned long flags; 769 770 DBGINFO(("%s set_termios\n", tty->driver->name)); 771 772 change_params(info); 773 774 /* Handle transition to B0 status */ 775 if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) { 776 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR); 777 spin_lock_irqsave(&info->lock,flags); 778 set_signals(info); 779 spin_unlock_irqrestore(&info->lock,flags); 780 } 781 782 /* Handle transition away from B0 status */ 783 if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) { 784 info->signals |= SerialSignal_DTR; 785 if (!C_CRTSCTS(tty) || !tty_throttled(tty)) 786 info->signals |= SerialSignal_RTS; 787 spin_lock_irqsave(&info->lock,flags); 788 set_signals(info); 789 spin_unlock_irqrestore(&info->lock,flags); 790 } 791 792 /* Handle turning off CRTSCTS */ 793 if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty)) { 794 tty->hw_stopped = 0; 795 tx_release(tty); 796 } 797 } 798 799 static void update_tx_timer(struct slgt_info *info) 800 { 801 /* 802 * use worst case speed of 1200bps to calculate transmit timeout 803 * based on data in buffers (tbuf_bytes) and FIFO (128 bytes) 804 */ 805 if (info->params.mode == MGSL_MODE_HDLC) { 806 int timeout = (tbuf_bytes(info) * 7) + 1000; 807 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(timeout)); 808 } 809 } 810 811 static int write(struct tty_struct *tty, 812 const unsigned char *buf, int count) 813 { 814 int ret = 0; 815 struct slgt_info *info = tty->driver_data; 816 unsigned long flags; 817 818 if (sanity_check(info, tty->name, "write")) 819 return -EIO; 820 821 DBGINFO(("%s write count=%d\n", info->device_name, count)); 822 823 if (!info->tx_buf || (count > info->max_frame_size)) 824 return -EIO; 825 826 if (!count || tty->stopped || tty->hw_stopped) 827 return 0; 828 829 spin_lock_irqsave(&info->lock, flags); 830 831 if (info->tx_count) { 832 /* send accumulated data from send_char() */ 833 if (!tx_load(info, info->tx_buf, info->tx_count)) 834 goto cleanup; 835 info->tx_count = 0; 836 } 837 838 if (tx_load(info, buf, count)) 839 ret = count; 840 841 cleanup: 842 spin_unlock_irqrestore(&info->lock, flags); 843 DBGINFO(("%s write rc=%d\n", info->device_name, ret)); 844 return ret; 845 } 846 847 static int put_char(struct tty_struct *tty, unsigned char ch) 848 { 849 struct slgt_info *info = tty->driver_data; 850 unsigned long flags; 851 int ret = 0; 852 853 if (sanity_check(info, tty->name, "put_char")) 854 return 0; 855 DBGINFO(("%s put_char(%d)\n", info->device_name, ch)); 856 if (!info->tx_buf) 857 return 0; 858 spin_lock_irqsave(&info->lock,flags); 859 if (info->tx_count < info->max_frame_size) { 860 info->tx_buf[info->tx_count++] = ch; 861 ret = 1; 862 } 863 spin_unlock_irqrestore(&info->lock,flags); 864 return ret; 865 } 866 867 static void send_xchar(struct tty_struct *tty, char ch) 868 { 869 struct slgt_info *info = tty->driver_data; 870 unsigned long flags; 871 872 if (sanity_check(info, tty->name, "send_xchar")) 873 return; 874 DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch)); 875 info->x_char = ch; 876 if (ch) { 877 spin_lock_irqsave(&info->lock,flags); 878 if (!info->tx_enabled) 879 tx_start(info); 880 spin_unlock_irqrestore(&info->lock,flags); 881 } 882 } 883 884 static void wait_until_sent(struct tty_struct *tty, int timeout) 885 { 886 struct slgt_info *info = tty->driver_data; 887 unsigned long orig_jiffies, char_time; 888 889 if (!info ) 890 return; 891 if (sanity_check(info, tty->name, "wait_until_sent")) 892 return; 893 DBGINFO(("%s wait_until_sent entry\n", info->device_name)); 894 if (!tty_port_initialized(&info->port)) 895 goto exit; 896 897 orig_jiffies = jiffies; 898 899 /* Set check interval to 1/5 of estimated time to 900 * send a character, and make it at least 1. The check 901 * interval should also be less than the timeout. 902 * Note: use tight timings here to satisfy the NIST-PCTS. 903 */ 904 905 if (info->params.data_rate) { 906 char_time = info->timeout/(32 * 5); 907 if (!char_time) 908 char_time++; 909 } else 910 char_time = 1; 911 912 if (timeout) 913 char_time = min_t(unsigned long, char_time, timeout); 914 915 while (info->tx_active) { 916 msleep_interruptible(jiffies_to_msecs(char_time)); 917 if (signal_pending(current)) 918 break; 919 if (timeout && time_after(jiffies, orig_jiffies + timeout)) 920 break; 921 } 922 exit: 923 DBGINFO(("%s wait_until_sent exit\n", info->device_name)); 924 } 925 926 static int write_room(struct tty_struct *tty) 927 { 928 struct slgt_info *info = tty->driver_data; 929 int ret; 930 931 if (sanity_check(info, tty->name, "write_room")) 932 return 0; 933 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE; 934 DBGINFO(("%s write_room=%d\n", info->device_name, ret)); 935 return ret; 936 } 937 938 static void flush_chars(struct tty_struct *tty) 939 { 940 struct slgt_info *info = tty->driver_data; 941 unsigned long flags; 942 943 if (sanity_check(info, tty->name, "flush_chars")) 944 return; 945 DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count)); 946 947 if (info->tx_count <= 0 || tty->stopped || 948 tty->hw_stopped || !info->tx_buf) 949 return; 950 951 DBGINFO(("%s flush_chars start transmit\n", info->device_name)); 952 953 spin_lock_irqsave(&info->lock,flags); 954 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count)) 955 info->tx_count = 0; 956 spin_unlock_irqrestore(&info->lock,flags); 957 } 958 959 static void flush_buffer(struct tty_struct *tty) 960 { 961 struct slgt_info *info = tty->driver_data; 962 unsigned long flags; 963 964 if (sanity_check(info, tty->name, "flush_buffer")) 965 return; 966 DBGINFO(("%s flush_buffer\n", info->device_name)); 967 968 spin_lock_irqsave(&info->lock, flags); 969 info->tx_count = 0; 970 spin_unlock_irqrestore(&info->lock, flags); 971 972 tty_wakeup(tty); 973 } 974 975 /* 976 * throttle (stop) transmitter 977 */ 978 static void tx_hold(struct tty_struct *tty) 979 { 980 struct slgt_info *info = tty->driver_data; 981 unsigned long flags; 982 983 if (sanity_check(info, tty->name, "tx_hold")) 984 return; 985 DBGINFO(("%s tx_hold\n", info->device_name)); 986 spin_lock_irqsave(&info->lock,flags); 987 if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC) 988 tx_stop(info); 989 spin_unlock_irqrestore(&info->lock,flags); 990 } 991 992 /* 993 * release (start) transmitter 994 */ 995 static void tx_release(struct tty_struct *tty) 996 { 997 struct slgt_info *info = tty->driver_data; 998 unsigned long flags; 999 1000 if (sanity_check(info, tty->name, "tx_release")) 1001 return; 1002 DBGINFO(("%s tx_release\n", info->device_name)); 1003 spin_lock_irqsave(&info->lock, flags); 1004 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count)) 1005 info->tx_count = 0; 1006 spin_unlock_irqrestore(&info->lock, flags); 1007 } 1008 1009 /* 1010 * Service an IOCTL request 1011 * 1012 * Arguments 1013 * 1014 * tty pointer to tty instance data 1015 * cmd IOCTL command code 1016 * arg command argument/context 1017 * 1018 * Return 0 if success, otherwise error code 1019 */ 1020 static int ioctl(struct tty_struct *tty, 1021 unsigned int cmd, unsigned long arg) 1022 { 1023 struct slgt_info *info = tty->driver_data; 1024 void __user *argp = (void __user *)arg; 1025 int ret; 1026 1027 if (sanity_check(info, tty->name, "ioctl")) 1028 return -ENODEV; 1029 DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd)); 1030 1031 if (cmd != TIOCMIWAIT) { 1032 if (tty_io_error(tty)) 1033 return -EIO; 1034 } 1035 1036 switch (cmd) { 1037 case MGSL_IOCWAITEVENT: 1038 return wait_mgsl_event(info, argp); 1039 case TIOCMIWAIT: 1040 return modem_input_wait(info,(int)arg); 1041 case MGSL_IOCSGPIO: 1042 return set_gpio(info, argp); 1043 case MGSL_IOCGGPIO: 1044 return get_gpio(info, argp); 1045 case MGSL_IOCWAITGPIO: 1046 return wait_gpio(info, argp); 1047 case MGSL_IOCGXSYNC: 1048 return get_xsync(info, argp); 1049 case MGSL_IOCSXSYNC: 1050 return set_xsync(info, (int)arg); 1051 case MGSL_IOCGXCTRL: 1052 return get_xctrl(info, argp); 1053 case MGSL_IOCSXCTRL: 1054 return set_xctrl(info, (int)arg); 1055 } 1056 mutex_lock(&info->port.mutex); 1057 switch (cmd) { 1058 case MGSL_IOCGPARAMS: 1059 ret = get_params(info, argp); 1060 break; 1061 case MGSL_IOCSPARAMS: 1062 ret = set_params(info, argp); 1063 break; 1064 case MGSL_IOCGTXIDLE: 1065 ret = get_txidle(info, argp); 1066 break; 1067 case MGSL_IOCSTXIDLE: 1068 ret = set_txidle(info, (int)arg); 1069 break; 1070 case MGSL_IOCTXENABLE: 1071 ret = tx_enable(info, (int)arg); 1072 break; 1073 case MGSL_IOCRXENABLE: 1074 ret = rx_enable(info, (int)arg); 1075 break; 1076 case MGSL_IOCTXABORT: 1077 ret = tx_abort(info); 1078 break; 1079 case MGSL_IOCGSTATS: 1080 ret = get_stats(info, argp); 1081 break; 1082 case MGSL_IOCGIF: 1083 ret = get_interface(info, argp); 1084 break; 1085 case MGSL_IOCSIF: 1086 ret = set_interface(info,(int)arg); 1087 break; 1088 default: 1089 ret = -ENOIOCTLCMD; 1090 } 1091 mutex_unlock(&info->port.mutex); 1092 return ret; 1093 } 1094 1095 static int get_icount(struct tty_struct *tty, 1096 struct serial_icounter_struct *icount) 1097 1098 { 1099 struct slgt_info *info = tty->driver_data; 1100 struct mgsl_icount cnow; /* kernel counter temps */ 1101 unsigned long flags; 1102 1103 spin_lock_irqsave(&info->lock,flags); 1104 cnow = info->icount; 1105 spin_unlock_irqrestore(&info->lock,flags); 1106 1107 icount->cts = cnow.cts; 1108 icount->dsr = cnow.dsr; 1109 icount->rng = cnow.rng; 1110 icount->dcd = cnow.dcd; 1111 icount->rx = cnow.rx; 1112 icount->tx = cnow.tx; 1113 icount->frame = cnow.frame; 1114 icount->overrun = cnow.overrun; 1115 icount->parity = cnow.parity; 1116 icount->brk = cnow.brk; 1117 icount->buf_overrun = cnow.buf_overrun; 1118 1119 return 0; 1120 } 1121 1122 /* 1123 * support for 32 bit ioctl calls on 64 bit systems 1124 */ 1125 #ifdef CONFIG_COMPAT 1126 static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params) 1127 { 1128 struct MGSL_PARAMS32 tmp_params; 1129 1130 DBGINFO(("%s get_params32\n", info->device_name)); 1131 memset(&tmp_params, 0, sizeof(tmp_params)); 1132 tmp_params.mode = (compat_ulong_t)info->params.mode; 1133 tmp_params.loopback = info->params.loopback; 1134 tmp_params.flags = info->params.flags; 1135 tmp_params.encoding = info->params.encoding; 1136 tmp_params.clock_speed = (compat_ulong_t)info->params.clock_speed; 1137 tmp_params.addr_filter = info->params.addr_filter; 1138 tmp_params.crc_type = info->params.crc_type; 1139 tmp_params.preamble_length = info->params.preamble_length; 1140 tmp_params.preamble = info->params.preamble; 1141 tmp_params.data_rate = (compat_ulong_t)info->params.data_rate; 1142 tmp_params.data_bits = info->params.data_bits; 1143 tmp_params.stop_bits = info->params.stop_bits; 1144 tmp_params.parity = info->params.parity; 1145 if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32))) 1146 return -EFAULT; 1147 return 0; 1148 } 1149 1150 static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params) 1151 { 1152 struct MGSL_PARAMS32 tmp_params; 1153 1154 DBGINFO(("%s set_params32\n", info->device_name)); 1155 if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32))) 1156 return -EFAULT; 1157 1158 spin_lock(&info->lock); 1159 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) { 1160 info->base_clock = tmp_params.clock_speed; 1161 } else { 1162 info->params.mode = tmp_params.mode; 1163 info->params.loopback = tmp_params.loopback; 1164 info->params.flags = tmp_params.flags; 1165 info->params.encoding = tmp_params.encoding; 1166 info->params.clock_speed = tmp_params.clock_speed; 1167 info->params.addr_filter = tmp_params.addr_filter; 1168 info->params.crc_type = tmp_params.crc_type; 1169 info->params.preamble_length = tmp_params.preamble_length; 1170 info->params.preamble = tmp_params.preamble; 1171 info->params.data_rate = tmp_params.data_rate; 1172 info->params.data_bits = tmp_params.data_bits; 1173 info->params.stop_bits = tmp_params.stop_bits; 1174 info->params.parity = tmp_params.parity; 1175 } 1176 spin_unlock(&info->lock); 1177 1178 program_hw(info); 1179 1180 return 0; 1181 } 1182 1183 static long slgt_compat_ioctl(struct tty_struct *tty, 1184 unsigned int cmd, unsigned long arg) 1185 { 1186 struct slgt_info *info = tty->driver_data; 1187 int rc; 1188 1189 if (sanity_check(info, tty->name, "compat_ioctl")) 1190 return -ENODEV; 1191 DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd)); 1192 1193 switch (cmd) { 1194 case MGSL_IOCSPARAMS32: 1195 rc = set_params32(info, compat_ptr(arg)); 1196 break; 1197 1198 case MGSL_IOCGPARAMS32: 1199 rc = get_params32(info, compat_ptr(arg)); 1200 break; 1201 1202 case MGSL_IOCGPARAMS: 1203 case MGSL_IOCSPARAMS: 1204 case MGSL_IOCGTXIDLE: 1205 case MGSL_IOCGSTATS: 1206 case MGSL_IOCWAITEVENT: 1207 case MGSL_IOCGIF: 1208 case MGSL_IOCSGPIO: 1209 case MGSL_IOCGGPIO: 1210 case MGSL_IOCWAITGPIO: 1211 case MGSL_IOCGXSYNC: 1212 case MGSL_IOCGXCTRL: 1213 rc = ioctl(tty, cmd, (unsigned long)compat_ptr(arg)); 1214 break; 1215 default: 1216 rc = ioctl(tty, cmd, arg); 1217 } 1218 DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc)); 1219 return rc; 1220 } 1221 #else 1222 #define slgt_compat_ioctl NULL 1223 #endif /* ifdef CONFIG_COMPAT */ 1224 1225 /* 1226 * proc fs support 1227 */ 1228 static inline void line_info(struct seq_file *m, struct slgt_info *info) 1229 { 1230 char stat_buf[30]; 1231 unsigned long flags; 1232 1233 seq_printf(m, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n", 1234 info->device_name, info->phys_reg_addr, 1235 info->irq_level, info->max_frame_size); 1236 1237 /* output current serial signal states */ 1238 spin_lock_irqsave(&info->lock,flags); 1239 get_signals(info); 1240 spin_unlock_irqrestore(&info->lock,flags); 1241 1242 stat_buf[0] = 0; 1243 stat_buf[1] = 0; 1244 if (info->signals & SerialSignal_RTS) 1245 strcat(stat_buf, "|RTS"); 1246 if (info->signals & SerialSignal_CTS) 1247 strcat(stat_buf, "|CTS"); 1248 if (info->signals & SerialSignal_DTR) 1249 strcat(stat_buf, "|DTR"); 1250 if (info->signals & SerialSignal_DSR) 1251 strcat(stat_buf, "|DSR"); 1252 if (info->signals & SerialSignal_DCD) 1253 strcat(stat_buf, "|CD"); 1254 if (info->signals & SerialSignal_RI) 1255 strcat(stat_buf, "|RI"); 1256 1257 if (info->params.mode != MGSL_MODE_ASYNC) { 1258 seq_printf(m, "\tHDLC txok:%d rxok:%d", 1259 info->icount.txok, info->icount.rxok); 1260 if (info->icount.txunder) 1261 seq_printf(m, " txunder:%d", info->icount.txunder); 1262 if (info->icount.txabort) 1263 seq_printf(m, " txabort:%d", info->icount.txabort); 1264 if (info->icount.rxshort) 1265 seq_printf(m, " rxshort:%d", info->icount.rxshort); 1266 if (info->icount.rxlong) 1267 seq_printf(m, " rxlong:%d", info->icount.rxlong); 1268 if (info->icount.rxover) 1269 seq_printf(m, " rxover:%d", info->icount.rxover); 1270 if (info->icount.rxcrc) 1271 seq_printf(m, " rxcrc:%d", info->icount.rxcrc); 1272 } else { 1273 seq_printf(m, "\tASYNC tx:%d rx:%d", 1274 info->icount.tx, info->icount.rx); 1275 if (info->icount.frame) 1276 seq_printf(m, " fe:%d", info->icount.frame); 1277 if (info->icount.parity) 1278 seq_printf(m, " pe:%d", info->icount.parity); 1279 if (info->icount.brk) 1280 seq_printf(m, " brk:%d", info->icount.brk); 1281 if (info->icount.overrun) 1282 seq_printf(m, " oe:%d", info->icount.overrun); 1283 } 1284 1285 /* Append serial signal status to end */ 1286 seq_printf(m, " %s\n", stat_buf+1); 1287 1288 seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n", 1289 info->tx_active,info->bh_requested,info->bh_running, 1290 info->pending_bh); 1291 } 1292 1293 /* Called to print information about devices 1294 */ 1295 static int synclink_gt_proc_show(struct seq_file *m, void *v) 1296 { 1297 struct slgt_info *info; 1298 1299 seq_puts(m, "synclink_gt driver\n"); 1300 1301 info = slgt_device_list; 1302 while( info ) { 1303 line_info(m, info); 1304 info = info->next_device; 1305 } 1306 return 0; 1307 } 1308 1309 /* 1310 * return count of bytes in transmit buffer 1311 */ 1312 static int chars_in_buffer(struct tty_struct *tty) 1313 { 1314 struct slgt_info *info = tty->driver_data; 1315 int count; 1316 if (sanity_check(info, tty->name, "chars_in_buffer")) 1317 return 0; 1318 count = tbuf_bytes(info); 1319 DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, count)); 1320 return count; 1321 } 1322 1323 /* 1324 * signal remote device to throttle send data (our receive data) 1325 */ 1326 static void throttle(struct tty_struct * tty) 1327 { 1328 struct slgt_info *info = tty->driver_data; 1329 unsigned long flags; 1330 1331 if (sanity_check(info, tty->name, "throttle")) 1332 return; 1333 DBGINFO(("%s throttle\n", info->device_name)); 1334 if (I_IXOFF(tty)) 1335 send_xchar(tty, STOP_CHAR(tty)); 1336 if (C_CRTSCTS(tty)) { 1337 spin_lock_irqsave(&info->lock,flags); 1338 info->signals &= ~SerialSignal_RTS; 1339 set_signals(info); 1340 spin_unlock_irqrestore(&info->lock,flags); 1341 } 1342 } 1343 1344 /* 1345 * signal remote device to stop throttling send data (our receive data) 1346 */ 1347 static void unthrottle(struct tty_struct * tty) 1348 { 1349 struct slgt_info *info = tty->driver_data; 1350 unsigned long flags; 1351 1352 if (sanity_check(info, tty->name, "unthrottle")) 1353 return; 1354 DBGINFO(("%s unthrottle\n", info->device_name)); 1355 if (I_IXOFF(tty)) { 1356 if (info->x_char) 1357 info->x_char = 0; 1358 else 1359 send_xchar(tty, START_CHAR(tty)); 1360 } 1361 if (C_CRTSCTS(tty)) { 1362 spin_lock_irqsave(&info->lock,flags); 1363 info->signals |= SerialSignal_RTS; 1364 set_signals(info); 1365 spin_unlock_irqrestore(&info->lock,flags); 1366 } 1367 } 1368 1369 /* 1370 * set or clear transmit break condition 1371 * break_state -1=set break condition, 0=clear 1372 */ 1373 static int set_break(struct tty_struct *tty, int break_state) 1374 { 1375 struct slgt_info *info = tty->driver_data; 1376 unsigned short value; 1377 unsigned long flags; 1378 1379 if (sanity_check(info, tty->name, "set_break")) 1380 return -EINVAL; 1381 DBGINFO(("%s set_break(%d)\n", info->device_name, break_state)); 1382 1383 spin_lock_irqsave(&info->lock,flags); 1384 value = rd_reg16(info, TCR); 1385 if (break_state == -1) 1386 value |= BIT6; 1387 else 1388 value &= ~BIT6; 1389 wr_reg16(info, TCR, value); 1390 spin_unlock_irqrestore(&info->lock,flags); 1391 return 0; 1392 } 1393 1394 #if SYNCLINK_GENERIC_HDLC 1395 1396 /** 1397 * hdlcdev_attach - called by generic HDLC layer when protocol selected (PPP, frame relay, etc.) 1398 * @dev: pointer to network device structure 1399 * @encoding: serial encoding setting 1400 * @parity: FCS setting 1401 * 1402 * Set encoding and frame check sequence (FCS) options. 1403 * 1404 * Return: 0 if success, otherwise error code 1405 */ 1406 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding, 1407 unsigned short parity) 1408 { 1409 struct slgt_info *info = dev_to_port(dev); 1410 unsigned char new_encoding; 1411 unsigned short new_crctype; 1412 1413 /* return error if TTY interface open */ 1414 if (info->port.count) 1415 return -EBUSY; 1416 1417 DBGINFO(("%s hdlcdev_attach\n", info->device_name)); 1418 1419 switch (encoding) 1420 { 1421 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break; 1422 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break; 1423 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break; 1424 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break; 1425 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break; 1426 default: return -EINVAL; 1427 } 1428 1429 switch (parity) 1430 { 1431 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break; 1432 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break; 1433 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break; 1434 default: return -EINVAL; 1435 } 1436 1437 info->params.encoding = new_encoding; 1438 info->params.crc_type = new_crctype; 1439 1440 /* if network interface up, reprogram hardware */ 1441 if (info->netcount) 1442 program_hw(info); 1443 1444 return 0; 1445 } 1446 1447 /** 1448 * hdlcdev_xmit - called by generic HDLC layer to send a frame 1449 * @skb: socket buffer containing HDLC frame 1450 * @dev: pointer to network device structure 1451 */ 1452 static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb, 1453 struct net_device *dev) 1454 { 1455 struct slgt_info *info = dev_to_port(dev); 1456 unsigned long flags; 1457 1458 DBGINFO(("%s hdlc_xmit\n", dev->name)); 1459 1460 if (!skb->len) 1461 return NETDEV_TX_OK; 1462 1463 /* stop sending until this frame completes */ 1464 netif_stop_queue(dev); 1465 1466 /* update network statistics */ 1467 dev->stats.tx_packets++; 1468 dev->stats.tx_bytes += skb->len; 1469 1470 /* save start time for transmit timeout detection */ 1471 netif_trans_update(dev); 1472 1473 spin_lock_irqsave(&info->lock, flags); 1474 tx_load(info, skb->data, skb->len); 1475 spin_unlock_irqrestore(&info->lock, flags); 1476 1477 /* done with socket buffer, so free it */ 1478 dev_kfree_skb(skb); 1479 1480 return NETDEV_TX_OK; 1481 } 1482 1483 /** 1484 * hdlcdev_open - called by network layer when interface enabled 1485 * @dev: pointer to network device structure 1486 * 1487 * Claim resources and initialize hardware. 1488 * 1489 * Return: 0 if success, otherwise error code 1490 */ 1491 static int hdlcdev_open(struct net_device *dev) 1492 { 1493 struct slgt_info *info = dev_to_port(dev); 1494 int rc; 1495 unsigned long flags; 1496 1497 if (!try_module_get(THIS_MODULE)) 1498 return -EBUSY; 1499 1500 DBGINFO(("%s hdlcdev_open\n", dev->name)); 1501 1502 /* generic HDLC layer open processing */ 1503 rc = hdlc_open(dev); 1504 if (rc) 1505 return rc; 1506 1507 /* arbitrate between network and tty opens */ 1508 spin_lock_irqsave(&info->netlock, flags); 1509 if (info->port.count != 0 || info->netcount != 0) { 1510 DBGINFO(("%s hdlc_open busy\n", dev->name)); 1511 spin_unlock_irqrestore(&info->netlock, flags); 1512 return -EBUSY; 1513 } 1514 info->netcount=1; 1515 spin_unlock_irqrestore(&info->netlock, flags); 1516 1517 /* claim resources and init adapter */ 1518 if ((rc = startup(info)) != 0) { 1519 spin_lock_irqsave(&info->netlock, flags); 1520 info->netcount=0; 1521 spin_unlock_irqrestore(&info->netlock, flags); 1522 return rc; 1523 } 1524 1525 /* assert RTS and DTR, apply hardware settings */ 1526 info->signals |= SerialSignal_RTS | SerialSignal_DTR; 1527 program_hw(info); 1528 1529 /* enable network layer transmit */ 1530 netif_trans_update(dev); 1531 netif_start_queue(dev); 1532 1533 /* inform generic HDLC layer of current DCD status */ 1534 spin_lock_irqsave(&info->lock, flags); 1535 get_signals(info); 1536 spin_unlock_irqrestore(&info->lock, flags); 1537 if (info->signals & SerialSignal_DCD) 1538 netif_carrier_on(dev); 1539 else 1540 netif_carrier_off(dev); 1541 return 0; 1542 } 1543 1544 /** 1545 * hdlcdev_close - called by network layer when interface is disabled 1546 * @dev: pointer to network device structure 1547 * 1548 * Shutdown hardware and release resources. 1549 * 1550 * Return: 0 if success, otherwise error code 1551 */ 1552 static int hdlcdev_close(struct net_device *dev) 1553 { 1554 struct slgt_info *info = dev_to_port(dev); 1555 unsigned long flags; 1556 1557 DBGINFO(("%s hdlcdev_close\n", dev->name)); 1558 1559 netif_stop_queue(dev); 1560 1561 /* shutdown adapter and release resources */ 1562 shutdown(info); 1563 1564 hdlc_close(dev); 1565 1566 spin_lock_irqsave(&info->netlock, flags); 1567 info->netcount=0; 1568 spin_unlock_irqrestore(&info->netlock, flags); 1569 1570 module_put(THIS_MODULE); 1571 return 0; 1572 } 1573 1574 /** 1575 * hdlcdev_ioctl - called by network layer to process IOCTL call to network device 1576 * @dev: pointer to network device structure 1577 * @ifr: pointer to network interface request structure 1578 * @cmd: IOCTL command code 1579 * 1580 * Return: 0 if success, otherwise error code 1581 */ 1582 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 1583 { 1584 const size_t size = sizeof(sync_serial_settings); 1585 sync_serial_settings new_line; 1586 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync; 1587 struct slgt_info *info = dev_to_port(dev); 1588 unsigned int flags; 1589 1590 DBGINFO(("%s hdlcdev_ioctl\n", dev->name)); 1591 1592 /* return error if TTY interface open */ 1593 if (info->port.count) 1594 return -EBUSY; 1595 1596 if (cmd != SIOCWANDEV) 1597 return hdlc_ioctl(dev, ifr, cmd); 1598 1599 memset(&new_line, 0, sizeof(new_line)); 1600 1601 switch(ifr->ifr_settings.type) { 1602 case IF_GET_IFACE: /* return current sync_serial_settings */ 1603 1604 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL; 1605 if (ifr->ifr_settings.size < size) { 1606 ifr->ifr_settings.size = size; /* data size wanted */ 1607 return -ENOBUFS; 1608 } 1609 1610 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL | 1611 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN | 1612 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL | 1613 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); 1614 1615 switch (flags){ 1616 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break; 1617 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break; 1618 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break; 1619 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break; 1620 default: new_line.clock_type = CLOCK_DEFAULT; 1621 } 1622 1623 new_line.clock_rate = info->params.clock_speed; 1624 new_line.loopback = info->params.loopback ? 1:0; 1625 1626 if (copy_to_user(line, &new_line, size)) 1627 return -EFAULT; 1628 return 0; 1629 1630 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */ 1631 1632 if(!capable(CAP_NET_ADMIN)) 1633 return -EPERM; 1634 if (copy_from_user(&new_line, line, size)) 1635 return -EFAULT; 1636 1637 switch (new_line.clock_type) 1638 { 1639 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break; 1640 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break; 1641 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break; 1642 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break; 1643 case CLOCK_DEFAULT: flags = info->params.flags & 1644 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL | 1645 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN | 1646 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL | 1647 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break; 1648 default: return -EINVAL; 1649 } 1650 1651 if (new_line.loopback != 0 && new_line.loopback != 1) 1652 return -EINVAL; 1653 1654 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL | 1655 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN | 1656 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL | 1657 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); 1658 info->params.flags |= flags; 1659 1660 info->params.loopback = new_line.loopback; 1661 1662 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG)) 1663 info->params.clock_speed = new_line.clock_rate; 1664 else 1665 info->params.clock_speed = 0; 1666 1667 /* if network interface up, reprogram hardware */ 1668 if (info->netcount) 1669 program_hw(info); 1670 return 0; 1671 1672 default: 1673 return hdlc_ioctl(dev, ifr, cmd); 1674 } 1675 } 1676 1677 /** 1678 * hdlcdev_tx_timeout - called by network layer when transmit timeout is detected 1679 * @dev: pointer to network device structure 1680 * @txqueue: unused 1681 */ 1682 static void hdlcdev_tx_timeout(struct net_device *dev, unsigned int txqueue) 1683 { 1684 struct slgt_info *info = dev_to_port(dev); 1685 unsigned long flags; 1686 1687 DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name)); 1688 1689 dev->stats.tx_errors++; 1690 dev->stats.tx_aborted_errors++; 1691 1692 spin_lock_irqsave(&info->lock,flags); 1693 tx_stop(info); 1694 spin_unlock_irqrestore(&info->lock,flags); 1695 1696 netif_wake_queue(dev); 1697 } 1698 1699 /** 1700 * hdlcdev_tx_done - called by device driver when transmit completes 1701 * @info: pointer to device instance information 1702 * 1703 * Reenable network layer transmit if stopped. 1704 */ 1705 static void hdlcdev_tx_done(struct slgt_info *info) 1706 { 1707 if (netif_queue_stopped(info->netdev)) 1708 netif_wake_queue(info->netdev); 1709 } 1710 1711 /** 1712 * hdlcdev_rx - called by device driver when frame received 1713 * @info: pointer to device instance information 1714 * @buf: pointer to buffer contianing frame data 1715 * @size: count of data bytes in buf 1716 * 1717 * Pass frame to network layer. 1718 */ 1719 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size) 1720 { 1721 struct sk_buff *skb = dev_alloc_skb(size); 1722 struct net_device *dev = info->netdev; 1723 1724 DBGINFO(("%s hdlcdev_rx\n", dev->name)); 1725 1726 if (skb == NULL) { 1727 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name)); 1728 dev->stats.rx_dropped++; 1729 return; 1730 } 1731 1732 skb_put_data(skb, buf, size); 1733 1734 skb->protocol = hdlc_type_trans(skb, dev); 1735 1736 dev->stats.rx_packets++; 1737 dev->stats.rx_bytes += size; 1738 1739 netif_rx(skb); 1740 } 1741 1742 static const struct net_device_ops hdlcdev_ops = { 1743 .ndo_open = hdlcdev_open, 1744 .ndo_stop = hdlcdev_close, 1745 .ndo_start_xmit = hdlc_start_xmit, 1746 .ndo_do_ioctl = hdlcdev_ioctl, 1747 .ndo_tx_timeout = hdlcdev_tx_timeout, 1748 }; 1749 1750 /** 1751 * hdlcdev_init - called by device driver when adding device instance 1752 * @info: pointer to device instance information 1753 * 1754 * Do generic HDLC initialization. 1755 * 1756 * Return: 0 if success, otherwise error code 1757 */ 1758 static int hdlcdev_init(struct slgt_info *info) 1759 { 1760 int rc; 1761 struct net_device *dev; 1762 hdlc_device *hdlc; 1763 1764 /* allocate and initialize network and HDLC layer objects */ 1765 1766 dev = alloc_hdlcdev(info); 1767 if (!dev) { 1768 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name); 1769 return -ENOMEM; 1770 } 1771 1772 /* for network layer reporting purposes only */ 1773 dev->mem_start = info->phys_reg_addr; 1774 dev->mem_end = info->phys_reg_addr + SLGT_REG_SIZE - 1; 1775 dev->irq = info->irq_level; 1776 1777 /* network layer callbacks and settings */ 1778 dev->netdev_ops = &hdlcdev_ops; 1779 dev->watchdog_timeo = 10 * HZ; 1780 dev->tx_queue_len = 50; 1781 1782 /* generic HDLC layer callbacks and settings */ 1783 hdlc = dev_to_hdlc(dev); 1784 hdlc->attach = hdlcdev_attach; 1785 hdlc->xmit = hdlcdev_xmit; 1786 1787 /* register objects with HDLC layer */ 1788 rc = register_hdlc_device(dev); 1789 if (rc) { 1790 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__); 1791 free_netdev(dev); 1792 return rc; 1793 } 1794 1795 info->netdev = dev; 1796 return 0; 1797 } 1798 1799 /** 1800 * hdlcdev_exit - called by device driver when removing device instance 1801 * @info: pointer to device instance information 1802 * 1803 * Do generic HDLC cleanup. 1804 */ 1805 static void hdlcdev_exit(struct slgt_info *info) 1806 { 1807 unregister_hdlc_device(info->netdev); 1808 free_netdev(info->netdev); 1809 info->netdev = NULL; 1810 } 1811 1812 #endif /* ifdef CONFIG_HDLC */ 1813 1814 /* 1815 * get async data from rx DMA buffers 1816 */ 1817 static void rx_async(struct slgt_info *info) 1818 { 1819 struct mgsl_icount *icount = &info->icount; 1820 unsigned int start, end; 1821 unsigned char *p; 1822 unsigned char status; 1823 struct slgt_desc *bufs = info->rbufs; 1824 int i, count; 1825 int chars = 0; 1826 int stat; 1827 unsigned char ch; 1828 1829 start = end = info->rbuf_current; 1830 1831 while(desc_complete(bufs[end])) { 1832 count = desc_count(bufs[end]) - info->rbuf_index; 1833 p = bufs[end].buf + info->rbuf_index; 1834 1835 DBGISR(("%s rx_async count=%d\n", info->device_name, count)); 1836 DBGDATA(info, p, count, "rx"); 1837 1838 for(i=0 ; i < count; i+=2, p+=2) { 1839 ch = *p; 1840 icount->rx++; 1841 1842 stat = 0; 1843 1844 status = *(p + 1) & (BIT1 + BIT0); 1845 if (status) { 1846 if (status & BIT1) 1847 icount->parity++; 1848 else if (status & BIT0) 1849 icount->frame++; 1850 /* discard char if tty control flags say so */ 1851 if (status & info->ignore_status_mask) 1852 continue; 1853 if (status & BIT1) 1854 stat = TTY_PARITY; 1855 else if (status & BIT0) 1856 stat = TTY_FRAME; 1857 } 1858 tty_insert_flip_char(&info->port, ch, stat); 1859 chars++; 1860 } 1861 1862 if (i < count) { 1863 /* receive buffer not completed */ 1864 info->rbuf_index += i; 1865 mod_timer(&info->rx_timer, jiffies + 1); 1866 break; 1867 } 1868 1869 info->rbuf_index = 0; 1870 free_rbufs(info, end, end); 1871 1872 if (++end == info->rbuf_count) 1873 end = 0; 1874 1875 /* if entire list searched then no frame available */ 1876 if (end == start) 1877 break; 1878 } 1879 1880 if (chars) 1881 tty_flip_buffer_push(&info->port); 1882 } 1883 1884 /* 1885 * return next bottom half action to perform 1886 */ 1887 static int bh_action(struct slgt_info *info) 1888 { 1889 unsigned long flags; 1890 int rc; 1891 1892 spin_lock_irqsave(&info->lock,flags); 1893 1894 if (info->pending_bh & BH_RECEIVE) { 1895 info->pending_bh &= ~BH_RECEIVE; 1896 rc = BH_RECEIVE; 1897 } else if (info->pending_bh & BH_TRANSMIT) { 1898 info->pending_bh &= ~BH_TRANSMIT; 1899 rc = BH_TRANSMIT; 1900 } else if (info->pending_bh & BH_STATUS) { 1901 info->pending_bh &= ~BH_STATUS; 1902 rc = BH_STATUS; 1903 } else { 1904 /* Mark BH routine as complete */ 1905 info->bh_running = false; 1906 info->bh_requested = false; 1907 rc = 0; 1908 } 1909 1910 spin_unlock_irqrestore(&info->lock,flags); 1911 1912 return rc; 1913 } 1914 1915 /* 1916 * perform bottom half processing 1917 */ 1918 static void bh_handler(struct work_struct *work) 1919 { 1920 struct slgt_info *info = container_of(work, struct slgt_info, task); 1921 int action; 1922 1923 info->bh_running = true; 1924 1925 while((action = bh_action(info))) { 1926 switch (action) { 1927 case BH_RECEIVE: 1928 DBGBH(("%s bh receive\n", info->device_name)); 1929 switch(info->params.mode) { 1930 case MGSL_MODE_ASYNC: 1931 rx_async(info); 1932 break; 1933 case MGSL_MODE_HDLC: 1934 while(rx_get_frame(info)); 1935 break; 1936 case MGSL_MODE_RAW: 1937 case MGSL_MODE_MONOSYNC: 1938 case MGSL_MODE_BISYNC: 1939 case MGSL_MODE_XSYNC: 1940 while(rx_get_buf(info)); 1941 break; 1942 } 1943 /* restart receiver if rx DMA buffers exhausted */ 1944 if (info->rx_restart) 1945 rx_start(info); 1946 break; 1947 case BH_TRANSMIT: 1948 bh_transmit(info); 1949 break; 1950 case BH_STATUS: 1951 DBGBH(("%s bh status\n", info->device_name)); 1952 info->ri_chkcount = 0; 1953 info->dsr_chkcount = 0; 1954 info->dcd_chkcount = 0; 1955 info->cts_chkcount = 0; 1956 break; 1957 default: 1958 DBGBH(("%s unknown action\n", info->device_name)); 1959 break; 1960 } 1961 } 1962 DBGBH(("%s bh_handler exit\n", info->device_name)); 1963 } 1964 1965 static void bh_transmit(struct slgt_info *info) 1966 { 1967 struct tty_struct *tty = info->port.tty; 1968 1969 DBGBH(("%s bh_transmit\n", info->device_name)); 1970 if (tty) 1971 tty_wakeup(tty); 1972 } 1973 1974 static void dsr_change(struct slgt_info *info, unsigned short status) 1975 { 1976 if (status & BIT3) { 1977 info->signals |= SerialSignal_DSR; 1978 info->input_signal_events.dsr_up++; 1979 } else { 1980 info->signals &= ~SerialSignal_DSR; 1981 info->input_signal_events.dsr_down++; 1982 } 1983 DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals)); 1984 if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) { 1985 slgt_irq_off(info, IRQ_DSR); 1986 return; 1987 } 1988 info->icount.dsr++; 1989 wake_up_interruptible(&info->status_event_wait_q); 1990 wake_up_interruptible(&info->event_wait_q); 1991 info->pending_bh |= BH_STATUS; 1992 } 1993 1994 static void cts_change(struct slgt_info *info, unsigned short status) 1995 { 1996 if (status & BIT2) { 1997 info->signals |= SerialSignal_CTS; 1998 info->input_signal_events.cts_up++; 1999 } else { 2000 info->signals &= ~SerialSignal_CTS; 2001 info->input_signal_events.cts_down++; 2002 } 2003 DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals)); 2004 if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) { 2005 slgt_irq_off(info, IRQ_CTS); 2006 return; 2007 } 2008 info->icount.cts++; 2009 wake_up_interruptible(&info->status_event_wait_q); 2010 wake_up_interruptible(&info->event_wait_q); 2011 info->pending_bh |= BH_STATUS; 2012 2013 if (tty_port_cts_enabled(&info->port)) { 2014 if (info->port.tty) { 2015 if (info->port.tty->hw_stopped) { 2016 if (info->signals & SerialSignal_CTS) { 2017 info->port.tty->hw_stopped = 0; 2018 info->pending_bh |= BH_TRANSMIT; 2019 return; 2020 } 2021 } else { 2022 if (!(info->signals & SerialSignal_CTS)) 2023 info->port.tty->hw_stopped = 1; 2024 } 2025 } 2026 } 2027 } 2028 2029 static void dcd_change(struct slgt_info *info, unsigned short status) 2030 { 2031 if (status & BIT1) { 2032 info->signals |= SerialSignal_DCD; 2033 info->input_signal_events.dcd_up++; 2034 } else { 2035 info->signals &= ~SerialSignal_DCD; 2036 info->input_signal_events.dcd_down++; 2037 } 2038 DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals)); 2039 if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) { 2040 slgt_irq_off(info, IRQ_DCD); 2041 return; 2042 } 2043 info->icount.dcd++; 2044 #if SYNCLINK_GENERIC_HDLC 2045 if (info->netcount) { 2046 if (info->signals & SerialSignal_DCD) 2047 netif_carrier_on(info->netdev); 2048 else 2049 netif_carrier_off(info->netdev); 2050 } 2051 #endif 2052 wake_up_interruptible(&info->status_event_wait_q); 2053 wake_up_interruptible(&info->event_wait_q); 2054 info->pending_bh |= BH_STATUS; 2055 2056 if (tty_port_check_carrier(&info->port)) { 2057 if (info->signals & SerialSignal_DCD) 2058 wake_up_interruptible(&info->port.open_wait); 2059 else { 2060 if (info->port.tty) 2061 tty_hangup(info->port.tty); 2062 } 2063 } 2064 } 2065 2066 static void ri_change(struct slgt_info *info, unsigned short status) 2067 { 2068 if (status & BIT0) { 2069 info->signals |= SerialSignal_RI; 2070 info->input_signal_events.ri_up++; 2071 } else { 2072 info->signals &= ~SerialSignal_RI; 2073 info->input_signal_events.ri_down++; 2074 } 2075 DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals)); 2076 if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) { 2077 slgt_irq_off(info, IRQ_RI); 2078 return; 2079 } 2080 info->icount.rng++; 2081 wake_up_interruptible(&info->status_event_wait_q); 2082 wake_up_interruptible(&info->event_wait_q); 2083 info->pending_bh |= BH_STATUS; 2084 } 2085 2086 static void isr_rxdata(struct slgt_info *info) 2087 { 2088 unsigned int count = info->rbuf_fill_count; 2089 unsigned int i = info->rbuf_fill_index; 2090 unsigned short reg; 2091 2092 while (rd_reg16(info, SSR) & IRQ_RXDATA) { 2093 reg = rd_reg16(info, RDR); 2094 DBGISR(("isr_rxdata %s RDR=%04X\n", info->device_name, reg)); 2095 if (desc_complete(info->rbufs[i])) { 2096 /* all buffers full */ 2097 rx_stop(info); 2098 info->rx_restart = true; 2099 continue; 2100 } 2101 info->rbufs[i].buf[count++] = (unsigned char)reg; 2102 /* async mode saves status byte to buffer for each data byte */ 2103 if (info->params.mode == MGSL_MODE_ASYNC) 2104 info->rbufs[i].buf[count++] = (unsigned char)(reg >> 8); 2105 if (count == info->rbuf_fill_level || (reg & BIT10)) { 2106 /* buffer full or end of frame */ 2107 set_desc_count(info->rbufs[i], count); 2108 set_desc_status(info->rbufs[i], BIT15 | (reg >> 8)); 2109 info->rbuf_fill_count = count = 0; 2110 if (++i == info->rbuf_count) 2111 i = 0; 2112 info->pending_bh |= BH_RECEIVE; 2113 } 2114 } 2115 2116 info->rbuf_fill_index = i; 2117 info->rbuf_fill_count = count; 2118 } 2119 2120 static void isr_serial(struct slgt_info *info) 2121 { 2122 unsigned short status = rd_reg16(info, SSR); 2123 2124 DBGISR(("%s isr_serial status=%04X\n", info->device_name, status)); 2125 2126 wr_reg16(info, SSR, status); /* clear pending */ 2127 2128 info->irq_occurred = true; 2129 2130 if (info->params.mode == MGSL_MODE_ASYNC) { 2131 if (status & IRQ_TXIDLE) { 2132 if (info->tx_active) 2133 isr_txeom(info, status); 2134 } 2135 if (info->rx_pio && (status & IRQ_RXDATA)) 2136 isr_rxdata(info); 2137 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) { 2138 info->icount.brk++; 2139 /* process break detection if tty control allows */ 2140 if (info->port.tty) { 2141 if (!(status & info->ignore_status_mask)) { 2142 if (info->read_status_mask & MASK_BREAK) { 2143 tty_insert_flip_char(&info->port, 0, TTY_BREAK); 2144 if (info->port.flags & ASYNC_SAK) 2145 do_SAK(info->port.tty); 2146 } 2147 } 2148 } 2149 } 2150 } else { 2151 if (status & (IRQ_TXIDLE + IRQ_TXUNDER)) 2152 isr_txeom(info, status); 2153 if (info->rx_pio && (status & IRQ_RXDATA)) 2154 isr_rxdata(info); 2155 if (status & IRQ_RXIDLE) { 2156 if (status & RXIDLE) 2157 info->icount.rxidle++; 2158 else 2159 info->icount.exithunt++; 2160 wake_up_interruptible(&info->event_wait_q); 2161 } 2162 2163 if (status & IRQ_RXOVER) 2164 rx_start(info); 2165 } 2166 2167 if (status & IRQ_DSR) 2168 dsr_change(info, status); 2169 if (status & IRQ_CTS) 2170 cts_change(info, status); 2171 if (status & IRQ_DCD) 2172 dcd_change(info, status); 2173 if (status & IRQ_RI) 2174 ri_change(info, status); 2175 } 2176 2177 static void isr_rdma(struct slgt_info *info) 2178 { 2179 unsigned int status = rd_reg32(info, RDCSR); 2180 2181 DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status)); 2182 2183 /* RDCSR (rx DMA control/status) 2184 * 2185 * 31..07 reserved 2186 * 06 save status byte to DMA buffer 2187 * 05 error 2188 * 04 eol (end of list) 2189 * 03 eob (end of buffer) 2190 * 02 IRQ enable 2191 * 01 reset 2192 * 00 enable 2193 */ 2194 wr_reg32(info, RDCSR, status); /* clear pending */ 2195 2196 if (status & (BIT5 + BIT4)) { 2197 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name)); 2198 info->rx_restart = true; 2199 } 2200 info->pending_bh |= BH_RECEIVE; 2201 } 2202 2203 static void isr_tdma(struct slgt_info *info) 2204 { 2205 unsigned int status = rd_reg32(info, TDCSR); 2206 2207 DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status)); 2208 2209 /* TDCSR (tx DMA control/status) 2210 * 2211 * 31..06 reserved 2212 * 05 error 2213 * 04 eol (end of list) 2214 * 03 eob (end of buffer) 2215 * 02 IRQ enable 2216 * 01 reset 2217 * 00 enable 2218 */ 2219 wr_reg32(info, TDCSR, status); /* clear pending */ 2220 2221 if (status & (BIT5 + BIT4 + BIT3)) { 2222 // another transmit buffer has completed 2223 // run bottom half to get more send data from user 2224 info->pending_bh |= BH_TRANSMIT; 2225 } 2226 } 2227 2228 /* 2229 * return true if there are unsent tx DMA buffers, otherwise false 2230 * 2231 * if there are unsent buffers then info->tbuf_start 2232 * is set to index of first unsent buffer 2233 */ 2234 static bool unsent_tbufs(struct slgt_info *info) 2235 { 2236 unsigned int i = info->tbuf_current; 2237 bool rc = false; 2238 2239 /* 2240 * search backwards from last loaded buffer (precedes tbuf_current) 2241 * for first unsent buffer (desc_count > 0) 2242 */ 2243 2244 do { 2245 if (i) 2246 i--; 2247 else 2248 i = info->tbuf_count - 1; 2249 if (!desc_count(info->tbufs[i])) 2250 break; 2251 info->tbuf_start = i; 2252 rc = true; 2253 } while (i != info->tbuf_current); 2254 2255 return rc; 2256 } 2257 2258 static void isr_txeom(struct slgt_info *info, unsigned short status) 2259 { 2260 DBGISR(("%s txeom status=%04x\n", info->device_name, status)); 2261 2262 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER); 2263 tdma_reset(info); 2264 if (status & IRQ_TXUNDER) { 2265 unsigned short val = rd_reg16(info, TCR); 2266 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */ 2267 wr_reg16(info, TCR, val); /* clear reset bit */ 2268 } 2269 2270 if (info->tx_active) { 2271 if (info->params.mode != MGSL_MODE_ASYNC) { 2272 if (status & IRQ_TXUNDER) 2273 info->icount.txunder++; 2274 else if (status & IRQ_TXIDLE) 2275 info->icount.txok++; 2276 } 2277 2278 if (unsent_tbufs(info)) { 2279 tx_start(info); 2280 update_tx_timer(info); 2281 return; 2282 } 2283 info->tx_active = false; 2284 2285 del_timer(&info->tx_timer); 2286 2287 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) { 2288 info->signals &= ~SerialSignal_RTS; 2289 info->drop_rts_on_tx_done = false; 2290 set_signals(info); 2291 } 2292 2293 #if SYNCLINK_GENERIC_HDLC 2294 if (info->netcount) 2295 hdlcdev_tx_done(info); 2296 else 2297 #endif 2298 { 2299 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) { 2300 tx_stop(info); 2301 return; 2302 } 2303 info->pending_bh |= BH_TRANSMIT; 2304 } 2305 } 2306 } 2307 2308 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state) 2309 { 2310 struct cond_wait *w, *prev; 2311 2312 /* wake processes waiting for specific transitions */ 2313 for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) { 2314 if (w->data & changed) { 2315 w->data = state; 2316 wake_up_interruptible(&w->q); 2317 if (prev != NULL) 2318 prev->next = w->next; 2319 else 2320 info->gpio_wait_q = w->next; 2321 } else 2322 prev = w; 2323 } 2324 } 2325 2326 /* interrupt service routine 2327 * 2328 * irq interrupt number 2329 * dev_id device ID supplied during interrupt registration 2330 */ 2331 static irqreturn_t slgt_interrupt(int dummy, void *dev_id) 2332 { 2333 struct slgt_info *info = dev_id; 2334 unsigned int gsr; 2335 unsigned int i; 2336 2337 DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level)); 2338 2339 while((gsr = rd_reg32(info, GSR) & 0xffffff00)) { 2340 DBGISR(("%s gsr=%08x\n", info->device_name, gsr)); 2341 info->irq_occurred = true; 2342 for(i=0; i < info->port_count ; i++) { 2343 if (info->port_array[i] == NULL) 2344 continue; 2345 spin_lock(&info->port_array[i]->lock); 2346 if (gsr & (BIT8 << i)) 2347 isr_serial(info->port_array[i]); 2348 if (gsr & (BIT16 << (i*2))) 2349 isr_rdma(info->port_array[i]); 2350 if (gsr & (BIT17 << (i*2))) 2351 isr_tdma(info->port_array[i]); 2352 spin_unlock(&info->port_array[i]->lock); 2353 } 2354 } 2355 2356 if (info->gpio_present) { 2357 unsigned int state; 2358 unsigned int changed; 2359 spin_lock(&info->lock); 2360 while ((changed = rd_reg32(info, IOSR)) != 0) { 2361 DBGISR(("%s iosr=%08x\n", info->device_name, changed)); 2362 /* read latched state of GPIO signals */ 2363 state = rd_reg32(info, IOVR); 2364 /* clear pending GPIO interrupt bits */ 2365 wr_reg32(info, IOSR, changed); 2366 for (i=0 ; i < info->port_count ; i++) { 2367 if (info->port_array[i] != NULL) 2368 isr_gpio(info->port_array[i], changed, state); 2369 } 2370 } 2371 spin_unlock(&info->lock); 2372 } 2373 2374 for(i=0; i < info->port_count ; i++) { 2375 struct slgt_info *port = info->port_array[i]; 2376 if (port == NULL) 2377 continue; 2378 spin_lock(&port->lock); 2379 if ((port->port.count || port->netcount) && 2380 port->pending_bh && !port->bh_running && 2381 !port->bh_requested) { 2382 DBGISR(("%s bh queued\n", port->device_name)); 2383 schedule_work(&port->task); 2384 port->bh_requested = true; 2385 } 2386 spin_unlock(&port->lock); 2387 } 2388 2389 DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level)); 2390 return IRQ_HANDLED; 2391 } 2392 2393 static int startup(struct slgt_info *info) 2394 { 2395 DBGINFO(("%s startup\n", info->device_name)); 2396 2397 if (tty_port_initialized(&info->port)) 2398 return 0; 2399 2400 if (!info->tx_buf) { 2401 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL); 2402 if (!info->tx_buf) { 2403 DBGERR(("%s can't allocate tx buffer\n", info->device_name)); 2404 return -ENOMEM; 2405 } 2406 } 2407 2408 info->pending_bh = 0; 2409 2410 memset(&info->icount, 0, sizeof(info->icount)); 2411 2412 /* program hardware for current parameters */ 2413 change_params(info); 2414 2415 if (info->port.tty) 2416 clear_bit(TTY_IO_ERROR, &info->port.tty->flags); 2417 2418 tty_port_set_initialized(&info->port, 1); 2419 2420 return 0; 2421 } 2422 2423 /* 2424 * called by close() and hangup() to shutdown hardware 2425 */ 2426 static void shutdown(struct slgt_info *info) 2427 { 2428 unsigned long flags; 2429 2430 if (!tty_port_initialized(&info->port)) 2431 return; 2432 2433 DBGINFO(("%s shutdown\n", info->device_name)); 2434 2435 /* clear status wait queue because status changes */ 2436 /* can't happen after shutting down the hardware */ 2437 wake_up_interruptible(&info->status_event_wait_q); 2438 wake_up_interruptible(&info->event_wait_q); 2439 2440 del_timer_sync(&info->tx_timer); 2441 del_timer_sync(&info->rx_timer); 2442 2443 kfree(info->tx_buf); 2444 info->tx_buf = NULL; 2445 2446 spin_lock_irqsave(&info->lock,flags); 2447 2448 tx_stop(info); 2449 rx_stop(info); 2450 2451 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER); 2452 2453 if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) { 2454 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR); 2455 set_signals(info); 2456 } 2457 2458 flush_cond_wait(&info->gpio_wait_q); 2459 2460 spin_unlock_irqrestore(&info->lock,flags); 2461 2462 if (info->port.tty) 2463 set_bit(TTY_IO_ERROR, &info->port.tty->flags); 2464 2465 tty_port_set_initialized(&info->port, 0); 2466 } 2467 2468 static void program_hw(struct slgt_info *info) 2469 { 2470 unsigned long flags; 2471 2472 spin_lock_irqsave(&info->lock,flags); 2473 2474 rx_stop(info); 2475 tx_stop(info); 2476 2477 if (info->params.mode != MGSL_MODE_ASYNC || 2478 info->netcount) 2479 sync_mode(info); 2480 else 2481 async_mode(info); 2482 2483 set_signals(info); 2484 2485 info->dcd_chkcount = 0; 2486 info->cts_chkcount = 0; 2487 info->ri_chkcount = 0; 2488 info->dsr_chkcount = 0; 2489 2490 slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI); 2491 get_signals(info); 2492 2493 if (info->netcount || 2494 (info->port.tty && info->port.tty->termios.c_cflag & CREAD)) 2495 rx_start(info); 2496 2497 spin_unlock_irqrestore(&info->lock,flags); 2498 } 2499 2500 /* 2501 * reconfigure adapter based on new parameters 2502 */ 2503 static void change_params(struct slgt_info *info) 2504 { 2505 unsigned cflag; 2506 int bits_per_char; 2507 2508 if (!info->port.tty) 2509 return; 2510 DBGINFO(("%s change_params\n", info->device_name)); 2511 2512 cflag = info->port.tty->termios.c_cflag; 2513 2514 /* if B0 rate (hangup) specified then negate RTS and DTR */ 2515 /* otherwise assert RTS and DTR */ 2516 if (cflag & CBAUD) 2517 info->signals |= SerialSignal_RTS | SerialSignal_DTR; 2518 else 2519 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR); 2520 2521 /* byte size and parity */ 2522 2523 switch (cflag & CSIZE) { 2524 case CS5: info->params.data_bits = 5; break; 2525 case CS6: info->params.data_bits = 6; break; 2526 case CS7: info->params.data_bits = 7; break; 2527 case CS8: info->params.data_bits = 8; break; 2528 default: info->params.data_bits = 7; break; 2529 } 2530 2531 info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1; 2532 2533 if (cflag & PARENB) 2534 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN; 2535 else 2536 info->params.parity = ASYNC_PARITY_NONE; 2537 2538 /* calculate number of jiffies to transmit a full 2539 * FIFO (32 bytes) at specified data rate 2540 */ 2541 bits_per_char = info->params.data_bits + 2542 info->params.stop_bits + 1; 2543 2544 info->params.data_rate = tty_get_baud_rate(info->port.tty); 2545 2546 if (info->params.data_rate) { 2547 info->timeout = (32*HZ*bits_per_char) / 2548 info->params.data_rate; 2549 } 2550 info->timeout += HZ/50; /* Add .02 seconds of slop */ 2551 2552 tty_port_set_cts_flow(&info->port, cflag & CRTSCTS); 2553 tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL); 2554 2555 /* process tty input control flags */ 2556 2557 info->read_status_mask = IRQ_RXOVER; 2558 if (I_INPCK(info->port.tty)) 2559 info->read_status_mask |= MASK_PARITY | MASK_FRAMING; 2560 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty)) 2561 info->read_status_mask |= MASK_BREAK; 2562 if (I_IGNPAR(info->port.tty)) 2563 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING; 2564 if (I_IGNBRK(info->port.tty)) { 2565 info->ignore_status_mask |= MASK_BREAK; 2566 /* If ignoring parity and break indicators, ignore 2567 * overruns too. (For real raw support). 2568 */ 2569 if (I_IGNPAR(info->port.tty)) 2570 info->ignore_status_mask |= MASK_OVERRUN; 2571 } 2572 2573 program_hw(info); 2574 } 2575 2576 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount) 2577 { 2578 DBGINFO(("%s get_stats\n", info->device_name)); 2579 if (!user_icount) { 2580 memset(&info->icount, 0, sizeof(info->icount)); 2581 } else { 2582 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount))) 2583 return -EFAULT; 2584 } 2585 return 0; 2586 } 2587 2588 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params) 2589 { 2590 DBGINFO(("%s get_params\n", info->device_name)); 2591 if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS))) 2592 return -EFAULT; 2593 return 0; 2594 } 2595 2596 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params) 2597 { 2598 unsigned long flags; 2599 MGSL_PARAMS tmp_params; 2600 2601 DBGINFO(("%s set_params\n", info->device_name)); 2602 if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS))) 2603 return -EFAULT; 2604 2605 spin_lock_irqsave(&info->lock, flags); 2606 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) 2607 info->base_clock = tmp_params.clock_speed; 2608 else 2609 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS)); 2610 spin_unlock_irqrestore(&info->lock, flags); 2611 2612 program_hw(info); 2613 2614 return 0; 2615 } 2616 2617 static int get_txidle(struct slgt_info *info, int __user *idle_mode) 2618 { 2619 DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode)); 2620 if (put_user(info->idle_mode, idle_mode)) 2621 return -EFAULT; 2622 return 0; 2623 } 2624 2625 static int set_txidle(struct slgt_info *info, int idle_mode) 2626 { 2627 unsigned long flags; 2628 DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode)); 2629 spin_lock_irqsave(&info->lock,flags); 2630 info->idle_mode = idle_mode; 2631 if (info->params.mode != MGSL_MODE_ASYNC) 2632 tx_set_idle(info); 2633 spin_unlock_irqrestore(&info->lock,flags); 2634 return 0; 2635 } 2636 2637 static int tx_enable(struct slgt_info *info, int enable) 2638 { 2639 unsigned long flags; 2640 DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable)); 2641 spin_lock_irqsave(&info->lock,flags); 2642 if (enable) { 2643 if (!info->tx_enabled) 2644 tx_start(info); 2645 } else { 2646 if (info->tx_enabled) 2647 tx_stop(info); 2648 } 2649 spin_unlock_irqrestore(&info->lock,flags); 2650 return 0; 2651 } 2652 2653 /* 2654 * abort transmit HDLC frame 2655 */ 2656 static int tx_abort(struct slgt_info *info) 2657 { 2658 unsigned long flags; 2659 DBGINFO(("%s tx_abort\n", info->device_name)); 2660 spin_lock_irqsave(&info->lock,flags); 2661 tdma_reset(info); 2662 spin_unlock_irqrestore(&info->lock,flags); 2663 return 0; 2664 } 2665 2666 static int rx_enable(struct slgt_info *info, int enable) 2667 { 2668 unsigned long flags; 2669 unsigned int rbuf_fill_level; 2670 DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable)); 2671 spin_lock_irqsave(&info->lock,flags); 2672 /* 2673 * enable[31..16] = receive DMA buffer fill level 2674 * 0 = noop (leave fill level unchanged) 2675 * fill level must be multiple of 4 and <= buffer size 2676 */ 2677 rbuf_fill_level = ((unsigned int)enable) >> 16; 2678 if (rbuf_fill_level) { 2679 if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) { 2680 spin_unlock_irqrestore(&info->lock, flags); 2681 return -EINVAL; 2682 } 2683 info->rbuf_fill_level = rbuf_fill_level; 2684 if (rbuf_fill_level < 128) 2685 info->rx_pio = 1; /* PIO mode */ 2686 else 2687 info->rx_pio = 0; /* DMA mode */ 2688 rx_stop(info); /* restart receiver to use new fill level */ 2689 } 2690 2691 /* 2692 * enable[1..0] = receiver enable command 2693 * 0 = disable 2694 * 1 = enable 2695 * 2 = enable or force hunt mode if already enabled 2696 */ 2697 enable &= 3; 2698 if (enable) { 2699 if (!info->rx_enabled) 2700 rx_start(info); 2701 else if (enable == 2) { 2702 /* force hunt mode (write 1 to RCR[3]) */ 2703 wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3); 2704 } 2705 } else { 2706 if (info->rx_enabled) 2707 rx_stop(info); 2708 } 2709 spin_unlock_irqrestore(&info->lock,flags); 2710 return 0; 2711 } 2712 2713 /* 2714 * wait for specified event to occur 2715 */ 2716 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr) 2717 { 2718 unsigned long flags; 2719 int s; 2720 int rc=0; 2721 struct mgsl_icount cprev, cnow; 2722 int events; 2723 int mask; 2724 struct _input_signal_events oldsigs, newsigs; 2725 DECLARE_WAITQUEUE(wait, current); 2726 2727 if (get_user(mask, mask_ptr)) 2728 return -EFAULT; 2729 2730 DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask)); 2731 2732 spin_lock_irqsave(&info->lock,flags); 2733 2734 /* return immediately if state matches requested events */ 2735 get_signals(info); 2736 s = info->signals; 2737 2738 events = mask & 2739 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) + 2740 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) + 2741 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) + 2742 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) ); 2743 if (events) { 2744 spin_unlock_irqrestore(&info->lock,flags); 2745 goto exit; 2746 } 2747 2748 /* save current irq counts */ 2749 cprev = info->icount; 2750 oldsigs = info->input_signal_events; 2751 2752 /* enable hunt and idle irqs if needed */ 2753 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) { 2754 unsigned short val = rd_reg16(info, SCR); 2755 if (!(val & IRQ_RXIDLE)) 2756 wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE)); 2757 } 2758 2759 set_current_state(TASK_INTERRUPTIBLE); 2760 add_wait_queue(&info->event_wait_q, &wait); 2761 2762 spin_unlock_irqrestore(&info->lock,flags); 2763 2764 for(;;) { 2765 schedule(); 2766 if (signal_pending(current)) { 2767 rc = -ERESTARTSYS; 2768 break; 2769 } 2770 2771 /* get current irq counts */ 2772 spin_lock_irqsave(&info->lock,flags); 2773 cnow = info->icount; 2774 newsigs = info->input_signal_events; 2775 set_current_state(TASK_INTERRUPTIBLE); 2776 spin_unlock_irqrestore(&info->lock,flags); 2777 2778 /* if no change, wait aborted for some reason */ 2779 if (newsigs.dsr_up == oldsigs.dsr_up && 2780 newsigs.dsr_down == oldsigs.dsr_down && 2781 newsigs.dcd_up == oldsigs.dcd_up && 2782 newsigs.dcd_down == oldsigs.dcd_down && 2783 newsigs.cts_up == oldsigs.cts_up && 2784 newsigs.cts_down == oldsigs.cts_down && 2785 newsigs.ri_up == oldsigs.ri_up && 2786 newsigs.ri_down == oldsigs.ri_down && 2787 cnow.exithunt == cprev.exithunt && 2788 cnow.rxidle == cprev.rxidle) { 2789 rc = -EIO; 2790 break; 2791 } 2792 2793 events = mask & 2794 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) + 2795 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) + 2796 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) + 2797 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) + 2798 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) + 2799 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) + 2800 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) + 2801 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) + 2802 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) + 2803 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) ); 2804 if (events) 2805 break; 2806 2807 cprev = cnow; 2808 oldsigs = newsigs; 2809 } 2810 2811 remove_wait_queue(&info->event_wait_q, &wait); 2812 set_current_state(TASK_RUNNING); 2813 2814 2815 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) { 2816 spin_lock_irqsave(&info->lock,flags); 2817 if (!waitqueue_active(&info->event_wait_q)) { 2818 /* disable enable exit hunt mode/idle rcvd IRQs */ 2819 wr_reg16(info, SCR, 2820 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE)); 2821 } 2822 spin_unlock_irqrestore(&info->lock,flags); 2823 } 2824 exit: 2825 if (rc == 0) 2826 rc = put_user(events, mask_ptr); 2827 return rc; 2828 } 2829 2830 static int get_interface(struct slgt_info *info, int __user *if_mode) 2831 { 2832 DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode)); 2833 if (put_user(info->if_mode, if_mode)) 2834 return -EFAULT; 2835 return 0; 2836 } 2837 2838 static int set_interface(struct slgt_info *info, int if_mode) 2839 { 2840 unsigned long flags; 2841 unsigned short val; 2842 2843 DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode)); 2844 spin_lock_irqsave(&info->lock,flags); 2845 info->if_mode = if_mode; 2846 2847 msc_set_vcr(info); 2848 2849 /* TCR (tx control) 07 1=RTS driver control */ 2850 val = rd_reg16(info, TCR); 2851 if (info->if_mode & MGSL_INTERFACE_RTS_EN) 2852 val |= BIT7; 2853 else 2854 val &= ~BIT7; 2855 wr_reg16(info, TCR, val); 2856 2857 spin_unlock_irqrestore(&info->lock,flags); 2858 return 0; 2859 } 2860 2861 static int get_xsync(struct slgt_info *info, int __user *xsync) 2862 { 2863 DBGINFO(("%s get_xsync=%x\n", info->device_name, info->xsync)); 2864 if (put_user(info->xsync, xsync)) 2865 return -EFAULT; 2866 return 0; 2867 } 2868 2869 /* 2870 * set extended sync pattern (1 to 4 bytes) for extended sync mode 2871 * 2872 * sync pattern is contained in least significant bytes of value 2873 * most significant byte of sync pattern is oldest (1st sent/detected) 2874 */ 2875 static int set_xsync(struct slgt_info *info, int xsync) 2876 { 2877 unsigned long flags; 2878 2879 DBGINFO(("%s set_xsync=%x)\n", info->device_name, xsync)); 2880 spin_lock_irqsave(&info->lock, flags); 2881 info->xsync = xsync; 2882 wr_reg32(info, XSR, xsync); 2883 spin_unlock_irqrestore(&info->lock, flags); 2884 return 0; 2885 } 2886 2887 static int get_xctrl(struct slgt_info *info, int __user *xctrl) 2888 { 2889 DBGINFO(("%s get_xctrl=%x\n", info->device_name, info->xctrl)); 2890 if (put_user(info->xctrl, xctrl)) 2891 return -EFAULT; 2892 return 0; 2893 } 2894 2895 /* 2896 * set extended control options 2897 * 2898 * xctrl[31:19] reserved, must be zero 2899 * xctrl[18:17] extended sync pattern length in bytes 2900 * 00 = 1 byte in xsr[7:0] 2901 * 01 = 2 bytes in xsr[15:0] 2902 * 10 = 3 bytes in xsr[23:0] 2903 * 11 = 4 bytes in xsr[31:0] 2904 * xctrl[16] 1 = enable terminal count, 0=disabled 2905 * xctrl[15:0] receive terminal count for fixed length packets 2906 * value is count minus one (0 = 1 byte packet) 2907 * when terminal count is reached, receiver 2908 * automatically returns to hunt mode and receive 2909 * FIFO contents are flushed to DMA buffers with 2910 * end of frame (EOF) status 2911 */ 2912 static int set_xctrl(struct slgt_info *info, int xctrl) 2913 { 2914 unsigned long flags; 2915 2916 DBGINFO(("%s set_xctrl=%x)\n", info->device_name, xctrl)); 2917 spin_lock_irqsave(&info->lock, flags); 2918 info->xctrl = xctrl; 2919 wr_reg32(info, XCR, xctrl); 2920 spin_unlock_irqrestore(&info->lock, flags); 2921 return 0; 2922 } 2923 2924 /* 2925 * set general purpose IO pin state and direction 2926 * 2927 * user_gpio fields: 2928 * state each bit indicates a pin state 2929 * smask set bit indicates pin state to set 2930 * dir each bit indicates a pin direction (0=input, 1=output) 2931 * dmask set bit indicates pin direction to set 2932 */ 2933 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio) 2934 { 2935 unsigned long flags; 2936 struct gpio_desc gpio; 2937 __u32 data; 2938 2939 if (!info->gpio_present) 2940 return -EINVAL; 2941 if (copy_from_user(&gpio, user_gpio, sizeof(gpio))) 2942 return -EFAULT; 2943 DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n", 2944 info->device_name, gpio.state, gpio.smask, 2945 gpio.dir, gpio.dmask)); 2946 2947 spin_lock_irqsave(&info->port_array[0]->lock, flags); 2948 if (gpio.dmask) { 2949 data = rd_reg32(info, IODR); 2950 data |= gpio.dmask & gpio.dir; 2951 data &= ~(gpio.dmask & ~gpio.dir); 2952 wr_reg32(info, IODR, data); 2953 } 2954 if (gpio.smask) { 2955 data = rd_reg32(info, IOVR); 2956 data |= gpio.smask & gpio.state; 2957 data &= ~(gpio.smask & ~gpio.state); 2958 wr_reg32(info, IOVR, data); 2959 } 2960 spin_unlock_irqrestore(&info->port_array[0]->lock, flags); 2961 2962 return 0; 2963 } 2964 2965 /* 2966 * get general purpose IO pin state and direction 2967 */ 2968 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio) 2969 { 2970 struct gpio_desc gpio; 2971 if (!info->gpio_present) 2972 return -EINVAL; 2973 gpio.state = rd_reg32(info, IOVR); 2974 gpio.smask = 0xffffffff; 2975 gpio.dir = rd_reg32(info, IODR); 2976 gpio.dmask = 0xffffffff; 2977 if (copy_to_user(user_gpio, &gpio, sizeof(gpio))) 2978 return -EFAULT; 2979 DBGINFO(("%s get_gpio state=%08x dir=%08x\n", 2980 info->device_name, gpio.state, gpio.dir)); 2981 return 0; 2982 } 2983 2984 /* 2985 * conditional wait facility 2986 */ 2987 static void init_cond_wait(struct cond_wait *w, unsigned int data) 2988 { 2989 init_waitqueue_head(&w->q); 2990 init_waitqueue_entry(&w->wait, current); 2991 w->data = data; 2992 } 2993 2994 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w) 2995 { 2996 set_current_state(TASK_INTERRUPTIBLE); 2997 add_wait_queue(&w->q, &w->wait); 2998 w->next = *head; 2999 *head = w; 3000 } 3001 3002 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw) 3003 { 3004 struct cond_wait *w, *prev; 3005 remove_wait_queue(&cw->q, &cw->wait); 3006 set_current_state(TASK_RUNNING); 3007 for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) { 3008 if (w == cw) { 3009 if (prev != NULL) 3010 prev->next = w->next; 3011 else 3012 *head = w->next; 3013 break; 3014 } 3015 } 3016 } 3017 3018 static void flush_cond_wait(struct cond_wait **head) 3019 { 3020 while (*head != NULL) { 3021 wake_up_interruptible(&(*head)->q); 3022 *head = (*head)->next; 3023 } 3024 } 3025 3026 /* 3027 * wait for general purpose I/O pin(s) to enter specified state 3028 * 3029 * user_gpio fields: 3030 * state - bit indicates target pin state 3031 * smask - set bit indicates watched pin 3032 * 3033 * The wait ends when at least one watched pin enters the specified 3034 * state. When 0 (no error) is returned, user_gpio->state is set to the 3035 * state of all GPIO pins when the wait ends. 3036 * 3037 * Note: Each pin may be a dedicated input, dedicated output, or 3038 * configurable input/output. The number and configuration of pins 3039 * varies with the specific adapter model. Only input pins (dedicated 3040 * or configured) can be monitored with this function. 3041 */ 3042 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio) 3043 { 3044 unsigned long flags; 3045 int rc = 0; 3046 struct gpio_desc gpio; 3047 struct cond_wait wait; 3048 u32 state; 3049 3050 if (!info->gpio_present) 3051 return -EINVAL; 3052 if (copy_from_user(&gpio, user_gpio, sizeof(gpio))) 3053 return -EFAULT; 3054 DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n", 3055 info->device_name, gpio.state, gpio.smask)); 3056 /* ignore output pins identified by set IODR bit */ 3057 if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0) 3058 return -EINVAL; 3059 init_cond_wait(&wait, gpio.smask); 3060 3061 spin_lock_irqsave(&info->port_array[0]->lock, flags); 3062 /* enable interrupts for watched pins */ 3063 wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask); 3064 /* get current pin states */ 3065 state = rd_reg32(info, IOVR); 3066 3067 if (gpio.smask & ~(state ^ gpio.state)) { 3068 /* already in target state */ 3069 gpio.state = state; 3070 } else { 3071 /* wait for target state */ 3072 add_cond_wait(&info->gpio_wait_q, &wait); 3073 spin_unlock_irqrestore(&info->port_array[0]->lock, flags); 3074 schedule(); 3075 if (signal_pending(current)) 3076 rc = -ERESTARTSYS; 3077 else 3078 gpio.state = wait.data; 3079 spin_lock_irqsave(&info->port_array[0]->lock, flags); 3080 remove_cond_wait(&info->gpio_wait_q, &wait); 3081 } 3082 3083 /* disable all GPIO interrupts if no waiting processes */ 3084 if (info->gpio_wait_q == NULL) 3085 wr_reg32(info, IOER, 0); 3086 spin_unlock_irqrestore(&info->port_array[0]->lock, flags); 3087 3088 if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio))) 3089 rc = -EFAULT; 3090 return rc; 3091 } 3092 3093 static int modem_input_wait(struct slgt_info *info,int arg) 3094 { 3095 unsigned long flags; 3096 int rc; 3097 struct mgsl_icount cprev, cnow; 3098 DECLARE_WAITQUEUE(wait, current); 3099 3100 /* save current irq counts */ 3101 spin_lock_irqsave(&info->lock,flags); 3102 cprev = info->icount; 3103 add_wait_queue(&info->status_event_wait_q, &wait); 3104 set_current_state(TASK_INTERRUPTIBLE); 3105 spin_unlock_irqrestore(&info->lock,flags); 3106 3107 for(;;) { 3108 schedule(); 3109 if (signal_pending(current)) { 3110 rc = -ERESTARTSYS; 3111 break; 3112 } 3113 3114 /* get new irq counts */ 3115 spin_lock_irqsave(&info->lock,flags); 3116 cnow = info->icount; 3117 set_current_state(TASK_INTERRUPTIBLE); 3118 spin_unlock_irqrestore(&info->lock,flags); 3119 3120 /* if no change, wait aborted for some reason */ 3121 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr && 3122 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) { 3123 rc = -EIO; 3124 break; 3125 } 3126 3127 /* check for change in caller specified modem input */ 3128 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) || 3129 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) || 3130 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) || 3131 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) { 3132 rc = 0; 3133 break; 3134 } 3135 3136 cprev = cnow; 3137 } 3138 remove_wait_queue(&info->status_event_wait_q, &wait); 3139 set_current_state(TASK_RUNNING); 3140 return rc; 3141 } 3142 3143 /* 3144 * return state of serial control and status signals 3145 */ 3146 static int tiocmget(struct tty_struct *tty) 3147 { 3148 struct slgt_info *info = tty->driver_data; 3149 unsigned int result; 3150 unsigned long flags; 3151 3152 spin_lock_irqsave(&info->lock,flags); 3153 get_signals(info); 3154 spin_unlock_irqrestore(&info->lock,flags); 3155 3156 result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) + 3157 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) + 3158 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) + 3159 ((info->signals & SerialSignal_RI) ? TIOCM_RNG:0) + 3160 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) + 3161 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0); 3162 3163 DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result)); 3164 return result; 3165 } 3166 3167 /* 3168 * set modem control signals (DTR/RTS) 3169 * 3170 * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit 3171 * TIOCMSET = set/clear signal values 3172 * value bit mask for command 3173 */ 3174 static int tiocmset(struct tty_struct *tty, 3175 unsigned int set, unsigned int clear) 3176 { 3177 struct slgt_info *info = tty->driver_data; 3178 unsigned long flags; 3179 3180 DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear)); 3181 3182 if (set & TIOCM_RTS) 3183 info->signals |= SerialSignal_RTS; 3184 if (set & TIOCM_DTR) 3185 info->signals |= SerialSignal_DTR; 3186 if (clear & TIOCM_RTS) 3187 info->signals &= ~SerialSignal_RTS; 3188 if (clear & TIOCM_DTR) 3189 info->signals &= ~SerialSignal_DTR; 3190 3191 spin_lock_irqsave(&info->lock,flags); 3192 set_signals(info); 3193 spin_unlock_irqrestore(&info->lock,flags); 3194 return 0; 3195 } 3196 3197 static int carrier_raised(struct tty_port *port) 3198 { 3199 unsigned long flags; 3200 struct slgt_info *info = container_of(port, struct slgt_info, port); 3201 3202 spin_lock_irqsave(&info->lock,flags); 3203 get_signals(info); 3204 spin_unlock_irqrestore(&info->lock,flags); 3205 return (info->signals & SerialSignal_DCD) ? 1 : 0; 3206 } 3207 3208 static void dtr_rts(struct tty_port *port, int on) 3209 { 3210 unsigned long flags; 3211 struct slgt_info *info = container_of(port, struct slgt_info, port); 3212 3213 spin_lock_irqsave(&info->lock,flags); 3214 if (on) 3215 info->signals |= SerialSignal_RTS | SerialSignal_DTR; 3216 else 3217 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR); 3218 set_signals(info); 3219 spin_unlock_irqrestore(&info->lock,flags); 3220 } 3221 3222 3223 /* 3224 * block current process until the device is ready to open 3225 */ 3226 static int block_til_ready(struct tty_struct *tty, struct file *filp, 3227 struct slgt_info *info) 3228 { 3229 DECLARE_WAITQUEUE(wait, current); 3230 int retval; 3231 bool do_clocal = false; 3232 unsigned long flags; 3233 int cd; 3234 struct tty_port *port = &info->port; 3235 3236 DBGINFO(("%s block_til_ready\n", tty->driver->name)); 3237 3238 if (filp->f_flags & O_NONBLOCK || tty_io_error(tty)) { 3239 /* nonblock mode is set or port is not enabled */ 3240 tty_port_set_active(port, 1); 3241 return 0; 3242 } 3243 3244 if (C_CLOCAL(tty)) 3245 do_clocal = true; 3246 3247 /* Wait for carrier detect and the line to become 3248 * free (i.e., not in use by the callout). While we are in 3249 * this loop, port->count is dropped by one, so that 3250 * close() knows when to free things. We restore it upon 3251 * exit, either normal or abnormal. 3252 */ 3253 3254 retval = 0; 3255 add_wait_queue(&port->open_wait, &wait); 3256 3257 spin_lock_irqsave(&info->lock, flags); 3258 port->count--; 3259 spin_unlock_irqrestore(&info->lock, flags); 3260 port->blocked_open++; 3261 3262 while (1) { 3263 if (C_BAUD(tty) && tty_port_initialized(port)) 3264 tty_port_raise_dtr_rts(port); 3265 3266 set_current_state(TASK_INTERRUPTIBLE); 3267 3268 if (tty_hung_up_p(filp) || !tty_port_initialized(port)) { 3269 retval = (port->flags & ASYNC_HUP_NOTIFY) ? 3270 -EAGAIN : -ERESTARTSYS; 3271 break; 3272 } 3273 3274 cd = tty_port_carrier_raised(port); 3275 if (do_clocal || cd) 3276 break; 3277 3278 if (signal_pending(current)) { 3279 retval = -ERESTARTSYS; 3280 break; 3281 } 3282 3283 DBGINFO(("%s block_til_ready wait\n", tty->driver->name)); 3284 tty_unlock(tty); 3285 schedule(); 3286 tty_lock(tty); 3287 } 3288 3289 set_current_state(TASK_RUNNING); 3290 remove_wait_queue(&port->open_wait, &wait); 3291 3292 if (!tty_hung_up_p(filp)) 3293 port->count++; 3294 port->blocked_open--; 3295 3296 if (!retval) 3297 tty_port_set_active(port, 1); 3298 3299 DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval)); 3300 return retval; 3301 } 3302 3303 /* 3304 * allocate buffers used for calling line discipline receive_buf 3305 * directly in synchronous mode 3306 * note: add 5 bytes to max frame size to allow appending 3307 * 32-bit CRC and status byte when configured to do so 3308 */ 3309 static int alloc_tmp_rbuf(struct slgt_info *info) 3310 { 3311 info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL); 3312 if (info->tmp_rbuf == NULL) 3313 return -ENOMEM; 3314 /* unused flag buffer to satisfy receive_buf calling interface */ 3315 info->flag_buf = kzalloc(info->max_frame_size + 5, GFP_KERNEL); 3316 if (!info->flag_buf) { 3317 kfree(info->tmp_rbuf); 3318 info->tmp_rbuf = NULL; 3319 return -ENOMEM; 3320 } 3321 return 0; 3322 } 3323 3324 static void free_tmp_rbuf(struct slgt_info *info) 3325 { 3326 kfree(info->tmp_rbuf); 3327 info->tmp_rbuf = NULL; 3328 kfree(info->flag_buf); 3329 info->flag_buf = NULL; 3330 } 3331 3332 /* 3333 * allocate DMA descriptor lists. 3334 */ 3335 static int alloc_desc(struct slgt_info *info) 3336 { 3337 unsigned int i; 3338 unsigned int pbufs; 3339 3340 /* allocate memory to hold descriptor lists */ 3341 info->bufs = dma_alloc_coherent(&info->pdev->dev, DESC_LIST_SIZE, 3342 &info->bufs_dma_addr, GFP_KERNEL); 3343 if (info->bufs == NULL) 3344 return -ENOMEM; 3345 3346 info->rbufs = (struct slgt_desc*)info->bufs; 3347 info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count; 3348 3349 pbufs = (unsigned int)info->bufs_dma_addr; 3350 3351 /* 3352 * Build circular lists of descriptors 3353 */ 3354 3355 for (i=0; i < info->rbuf_count; i++) { 3356 /* physical address of this descriptor */ 3357 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc)); 3358 3359 /* physical address of next descriptor */ 3360 if (i == info->rbuf_count - 1) 3361 info->rbufs[i].next = cpu_to_le32(pbufs); 3362 else 3363 info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc))); 3364 set_desc_count(info->rbufs[i], DMABUFSIZE); 3365 } 3366 3367 for (i=0; i < info->tbuf_count; i++) { 3368 /* physical address of this descriptor */ 3369 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc)); 3370 3371 /* physical address of next descriptor */ 3372 if (i == info->tbuf_count - 1) 3373 info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc)); 3374 else 3375 info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc))); 3376 } 3377 3378 return 0; 3379 } 3380 3381 static void free_desc(struct slgt_info *info) 3382 { 3383 if (info->bufs != NULL) { 3384 dma_free_coherent(&info->pdev->dev, DESC_LIST_SIZE, 3385 info->bufs, info->bufs_dma_addr); 3386 info->bufs = NULL; 3387 info->rbufs = NULL; 3388 info->tbufs = NULL; 3389 } 3390 } 3391 3392 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count) 3393 { 3394 int i; 3395 for (i=0; i < count; i++) { 3396 bufs[i].buf = dma_alloc_coherent(&info->pdev->dev, DMABUFSIZE, 3397 &bufs[i].buf_dma_addr, GFP_KERNEL); 3398 if (!bufs[i].buf) 3399 return -ENOMEM; 3400 bufs[i].pbuf = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr); 3401 } 3402 return 0; 3403 } 3404 3405 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count) 3406 { 3407 int i; 3408 for (i=0; i < count; i++) { 3409 if (bufs[i].buf == NULL) 3410 continue; 3411 dma_free_coherent(&info->pdev->dev, DMABUFSIZE, bufs[i].buf, 3412 bufs[i].buf_dma_addr); 3413 bufs[i].buf = NULL; 3414 } 3415 } 3416 3417 static int alloc_dma_bufs(struct slgt_info *info) 3418 { 3419 info->rbuf_count = 32; 3420 info->tbuf_count = 32; 3421 3422 if (alloc_desc(info) < 0 || 3423 alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 || 3424 alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 || 3425 alloc_tmp_rbuf(info) < 0) { 3426 DBGERR(("%s DMA buffer alloc fail\n", info->device_name)); 3427 return -ENOMEM; 3428 } 3429 reset_rbufs(info); 3430 return 0; 3431 } 3432 3433 static void free_dma_bufs(struct slgt_info *info) 3434 { 3435 if (info->bufs) { 3436 free_bufs(info, info->rbufs, info->rbuf_count); 3437 free_bufs(info, info->tbufs, info->tbuf_count); 3438 free_desc(info); 3439 } 3440 free_tmp_rbuf(info); 3441 } 3442 3443 static int claim_resources(struct slgt_info *info) 3444 { 3445 if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) { 3446 DBGERR(("%s reg addr conflict, addr=%08X\n", 3447 info->device_name, info->phys_reg_addr)); 3448 info->init_error = DiagStatus_AddressConflict; 3449 goto errout; 3450 } 3451 else 3452 info->reg_addr_requested = true; 3453 3454 info->reg_addr = ioremap(info->phys_reg_addr, SLGT_REG_SIZE); 3455 if (!info->reg_addr) { 3456 DBGERR(("%s can't map device registers, addr=%08X\n", 3457 info->device_name, info->phys_reg_addr)); 3458 info->init_error = DiagStatus_CantAssignPciResources; 3459 goto errout; 3460 } 3461 return 0; 3462 3463 errout: 3464 release_resources(info); 3465 return -ENODEV; 3466 } 3467 3468 static void release_resources(struct slgt_info *info) 3469 { 3470 if (info->irq_requested) { 3471 free_irq(info->irq_level, info); 3472 info->irq_requested = false; 3473 } 3474 3475 if (info->reg_addr_requested) { 3476 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE); 3477 info->reg_addr_requested = false; 3478 } 3479 3480 if (info->reg_addr) { 3481 iounmap(info->reg_addr); 3482 info->reg_addr = NULL; 3483 } 3484 } 3485 3486 /* Add the specified device instance data structure to the 3487 * global linked list of devices and increment the device count. 3488 */ 3489 static void add_device(struct slgt_info *info) 3490 { 3491 char *devstr; 3492 3493 info->next_device = NULL; 3494 info->line = slgt_device_count; 3495 sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line); 3496 3497 if (info->line < MAX_DEVICES) { 3498 if (maxframe[info->line]) 3499 info->max_frame_size = maxframe[info->line]; 3500 } 3501 3502 slgt_device_count++; 3503 3504 if (!slgt_device_list) 3505 slgt_device_list = info; 3506 else { 3507 struct slgt_info *current_dev = slgt_device_list; 3508 while(current_dev->next_device) 3509 current_dev = current_dev->next_device; 3510 current_dev->next_device = info; 3511 } 3512 3513 if (info->max_frame_size < 4096) 3514 info->max_frame_size = 4096; 3515 else if (info->max_frame_size > 65535) 3516 info->max_frame_size = 65535; 3517 3518 switch(info->pdev->device) { 3519 case SYNCLINK_GT_DEVICE_ID: 3520 devstr = "GT"; 3521 break; 3522 case SYNCLINK_GT2_DEVICE_ID: 3523 devstr = "GT2"; 3524 break; 3525 case SYNCLINK_GT4_DEVICE_ID: 3526 devstr = "GT4"; 3527 break; 3528 case SYNCLINK_AC_DEVICE_ID: 3529 devstr = "AC"; 3530 info->params.mode = MGSL_MODE_ASYNC; 3531 break; 3532 default: 3533 devstr = "(unknown model)"; 3534 } 3535 printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n", 3536 devstr, info->device_name, info->phys_reg_addr, 3537 info->irq_level, info->max_frame_size); 3538 3539 #if SYNCLINK_GENERIC_HDLC 3540 hdlcdev_init(info); 3541 #endif 3542 } 3543 3544 static const struct tty_port_operations slgt_port_ops = { 3545 .carrier_raised = carrier_raised, 3546 .dtr_rts = dtr_rts, 3547 }; 3548 3549 /* 3550 * allocate device instance structure, return NULL on failure 3551 */ 3552 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev) 3553 { 3554 struct slgt_info *info; 3555 3556 info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL); 3557 3558 if (!info) { 3559 DBGERR(("%s device alloc failed adapter=%d port=%d\n", 3560 driver_name, adapter_num, port_num)); 3561 } else { 3562 tty_port_init(&info->port); 3563 info->port.ops = &slgt_port_ops; 3564 info->magic = MGSL_MAGIC; 3565 INIT_WORK(&info->task, bh_handler); 3566 info->max_frame_size = 4096; 3567 info->base_clock = 14745600; 3568 info->rbuf_fill_level = DMABUFSIZE; 3569 info->port.close_delay = 5*HZ/10; 3570 info->port.closing_wait = 30*HZ; 3571 init_waitqueue_head(&info->status_event_wait_q); 3572 init_waitqueue_head(&info->event_wait_q); 3573 spin_lock_init(&info->netlock); 3574 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS)); 3575 info->idle_mode = HDLC_TXIDLE_FLAGS; 3576 info->adapter_num = adapter_num; 3577 info->port_num = port_num; 3578 3579 timer_setup(&info->tx_timer, tx_timeout, 0); 3580 timer_setup(&info->rx_timer, rx_timeout, 0); 3581 3582 /* Copy configuration info to device instance data */ 3583 info->pdev = pdev; 3584 info->irq_level = pdev->irq; 3585 info->phys_reg_addr = pci_resource_start(pdev,0); 3586 3587 info->bus_type = MGSL_BUS_TYPE_PCI; 3588 info->irq_flags = IRQF_SHARED; 3589 3590 info->init_error = -1; /* assume error, set to 0 on successful init */ 3591 } 3592 3593 return info; 3594 } 3595 3596 static void device_init(int adapter_num, struct pci_dev *pdev) 3597 { 3598 struct slgt_info *port_array[SLGT_MAX_PORTS]; 3599 int i; 3600 int port_count = 1; 3601 3602 if (pdev->device == SYNCLINK_GT2_DEVICE_ID) 3603 port_count = 2; 3604 else if (pdev->device == SYNCLINK_GT4_DEVICE_ID) 3605 port_count = 4; 3606 3607 /* allocate device instances for all ports */ 3608 for (i=0; i < port_count; ++i) { 3609 port_array[i] = alloc_dev(adapter_num, i, pdev); 3610 if (port_array[i] == NULL) { 3611 for (--i; i >= 0; --i) { 3612 tty_port_destroy(&port_array[i]->port); 3613 kfree(port_array[i]); 3614 } 3615 return; 3616 } 3617 } 3618 3619 /* give copy of port_array to all ports and add to device list */ 3620 for (i=0; i < port_count; ++i) { 3621 memcpy(port_array[i]->port_array, port_array, sizeof(port_array)); 3622 add_device(port_array[i]); 3623 port_array[i]->port_count = port_count; 3624 spin_lock_init(&port_array[i]->lock); 3625 } 3626 3627 /* Allocate and claim adapter resources */ 3628 if (!claim_resources(port_array[0])) { 3629 3630 alloc_dma_bufs(port_array[0]); 3631 3632 /* copy resource information from first port to others */ 3633 for (i = 1; i < port_count; ++i) { 3634 port_array[i]->irq_level = port_array[0]->irq_level; 3635 port_array[i]->reg_addr = port_array[0]->reg_addr; 3636 alloc_dma_bufs(port_array[i]); 3637 } 3638 3639 if (request_irq(port_array[0]->irq_level, 3640 slgt_interrupt, 3641 port_array[0]->irq_flags, 3642 port_array[0]->device_name, 3643 port_array[0]) < 0) { 3644 DBGERR(("%s request_irq failed IRQ=%d\n", 3645 port_array[0]->device_name, 3646 port_array[0]->irq_level)); 3647 } else { 3648 port_array[0]->irq_requested = true; 3649 adapter_test(port_array[0]); 3650 for (i=1 ; i < port_count ; i++) { 3651 port_array[i]->init_error = port_array[0]->init_error; 3652 port_array[i]->gpio_present = port_array[0]->gpio_present; 3653 } 3654 } 3655 } 3656 3657 for (i = 0; i < port_count; ++i) { 3658 struct slgt_info *info = port_array[i]; 3659 tty_port_register_device(&info->port, serial_driver, info->line, 3660 &info->pdev->dev); 3661 } 3662 } 3663 3664 static int init_one(struct pci_dev *dev, 3665 const struct pci_device_id *ent) 3666 { 3667 if (pci_enable_device(dev)) { 3668 printk("error enabling pci device %p\n", dev); 3669 return -EIO; 3670 } 3671 pci_set_master(dev); 3672 device_init(slgt_device_count, dev); 3673 return 0; 3674 } 3675 3676 static void remove_one(struct pci_dev *dev) 3677 { 3678 } 3679 3680 static const struct tty_operations ops = { 3681 .open = open, 3682 .close = close, 3683 .write = write, 3684 .put_char = put_char, 3685 .flush_chars = flush_chars, 3686 .write_room = write_room, 3687 .chars_in_buffer = chars_in_buffer, 3688 .flush_buffer = flush_buffer, 3689 .ioctl = ioctl, 3690 .compat_ioctl = slgt_compat_ioctl, 3691 .throttle = throttle, 3692 .unthrottle = unthrottle, 3693 .send_xchar = send_xchar, 3694 .break_ctl = set_break, 3695 .wait_until_sent = wait_until_sent, 3696 .set_termios = set_termios, 3697 .stop = tx_hold, 3698 .start = tx_release, 3699 .hangup = hangup, 3700 .tiocmget = tiocmget, 3701 .tiocmset = tiocmset, 3702 .get_icount = get_icount, 3703 .proc_show = synclink_gt_proc_show, 3704 }; 3705 3706 static void slgt_cleanup(void) 3707 { 3708 int rc; 3709 struct slgt_info *info; 3710 struct slgt_info *tmp; 3711 3712 printk(KERN_INFO "unload %s\n", driver_name); 3713 3714 if (serial_driver) { 3715 for (info=slgt_device_list ; info != NULL ; info=info->next_device) 3716 tty_unregister_device(serial_driver, info->line); 3717 rc = tty_unregister_driver(serial_driver); 3718 if (rc) 3719 DBGERR(("tty_unregister_driver error=%d\n", rc)); 3720 put_tty_driver(serial_driver); 3721 } 3722 3723 /* reset devices */ 3724 info = slgt_device_list; 3725 while(info) { 3726 reset_port(info); 3727 info = info->next_device; 3728 } 3729 3730 /* release devices */ 3731 info = slgt_device_list; 3732 while(info) { 3733 #if SYNCLINK_GENERIC_HDLC 3734 hdlcdev_exit(info); 3735 #endif 3736 free_dma_bufs(info); 3737 free_tmp_rbuf(info); 3738 if (info->port_num == 0) 3739 release_resources(info); 3740 tmp = info; 3741 info = info->next_device; 3742 tty_port_destroy(&tmp->port); 3743 kfree(tmp); 3744 } 3745 3746 if (pci_registered) 3747 pci_unregister_driver(&pci_driver); 3748 } 3749 3750 /* 3751 * Driver initialization entry point. 3752 */ 3753 static int __init slgt_init(void) 3754 { 3755 int rc; 3756 3757 printk(KERN_INFO "%s\n", driver_name); 3758 3759 serial_driver = alloc_tty_driver(MAX_DEVICES); 3760 if (!serial_driver) { 3761 printk("%s can't allocate tty driver\n", driver_name); 3762 return -ENOMEM; 3763 } 3764 3765 /* Initialize the tty_driver structure */ 3766 3767 serial_driver->driver_name = slgt_driver_name; 3768 serial_driver->name = tty_dev_prefix; 3769 serial_driver->major = ttymajor; 3770 serial_driver->minor_start = 64; 3771 serial_driver->type = TTY_DRIVER_TYPE_SERIAL; 3772 serial_driver->subtype = SERIAL_TYPE_NORMAL; 3773 serial_driver->init_termios = tty_std_termios; 3774 serial_driver->init_termios.c_cflag = 3775 B9600 | CS8 | CREAD | HUPCL | CLOCAL; 3776 serial_driver->init_termios.c_ispeed = 9600; 3777 serial_driver->init_termios.c_ospeed = 9600; 3778 serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV; 3779 tty_set_operations(serial_driver, &ops); 3780 if ((rc = tty_register_driver(serial_driver)) < 0) { 3781 DBGERR(("%s can't register serial driver\n", driver_name)); 3782 put_tty_driver(serial_driver); 3783 serial_driver = NULL; 3784 goto error; 3785 } 3786 3787 printk(KERN_INFO "%s, tty major#%d\n", 3788 driver_name, serial_driver->major); 3789 3790 slgt_device_count = 0; 3791 if ((rc = pci_register_driver(&pci_driver)) < 0) { 3792 printk("%s pci_register_driver error=%d\n", driver_name, rc); 3793 goto error; 3794 } 3795 pci_registered = true; 3796 3797 if (!slgt_device_list) 3798 printk("%s no devices found\n",driver_name); 3799 3800 return 0; 3801 3802 error: 3803 slgt_cleanup(); 3804 return rc; 3805 } 3806 3807 static void __exit slgt_exit(void) 3808 { 3809 slgt_cleanup(); 3810 } 3811 3812 module_init(slgt_init); 3813 module_exit(slgt_exit); 3814 3815 /* 3816 * register access routines 3817 */ 3818 3819 #define CALC_REGADDR() \ 3820 unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \ 3821 if (addr >= 0x80) \ 3822 reg_addr += (info->port_num) * 32; \ 3823 else if (addr >= 0x40) \ 3824 reg_addr += (info->port_num) * 16; 3825 3826 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr) 3827 { 3828 CALC_REGADDR(); 3829 return readb((void __iomem *)reg_addr); 3830 } 3831 3832 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value) 3833 { 3834 CALC_REGADDR(); 3835 writeb(value, (void __iomem *)reg_addr); 3836 } 3837 3838 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr) 3839 { 3840 CALC_REGADDR(); 3841 return readw((void __iomem *)reg_addr); 3842 } 3843 3844 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value) 3845 { 3846 CALC_REGADDR(); 3847 writew(value, (void __iomem *)reg_addr); 3848 } 3849 3850 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr) 3851 { 3852 CALC_REGADDR(); 3853 return readl((void __iomem *)reg_addr); 3854 } 3855 3856 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value) 3857 { 3858 CALC_REGADDR(); 3859 writel(value, (void __iomem *)reg_addr); 3860 } 3861 3862 static void rdma_reset(struct slgt_info *info) 3863 { 3864 unsigned int i; 3865 3866 /* set reset bit */ 3867 wr_reg32(info, RDCSR, BIT1); 3868 3869 /* wait for enable bit cleared */ 3870 for(i=0 ; i < 1000 ; i++) 3871 if (!(rd_reg32(info, RDCSR) & BIT0)) 3872 break; 3873 } 3874 3875 static void tdma_reset(struct slgt_info *info) 3876 { 3877 unsigned int i; 3878 3879 /* set reset bit */ 3880 wr_reg32(info, TDCSR, BIT1); 3881 3882 /* wait for enable bit cleared */ 3883 for(i=0 ; i < 1000 ; i++) 3884 if (!(rd_reg32(info, TDCSR) & BIT0)) 3885 break; 3886 } 3887 3888 /* 3889 * enable internal loopback 3890 * TxCLK and RxCLK are generated from BRG 3891 * and TxD is looped back to RxD internally. 3892 */ 3893 static void enable_loopback(struct slgt_info *info) 3894 { 3895 /* SCR (serial control) BIT2=loopback enable */ 3896 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2)); 3897 3898 if (info->params.mode != MGSL_MODE_ASYNC) { 3899 /* CCR (clock control) 3900 * 07..05 tx clock source (010 = BRG) 3901 * 04..02 rx clock source (010 = BRG) 3902 * 01 auxclk enable (0 = disable) 3903 * 00 BRG enable (1 = enable) 3904 * 3905 * 0100 1001 3906 */ 3907 wr_reg8(info, CCR, 0x49); 3908 3909 /* set speed if available, otherwise use default */ 3910 if (info->params.clock_speed) 3911 set_rate(info, info->params.clock_speed); 3912 else 3913 set_rate(info, 3686400); 3914 } 3915 } 3916 3917 /* 3918 * set baud rate generator to specified rate 3919 */ 3920 static void set_rate(struct slgt_info *info, u32 rate) 3921 { 3922 unsigned int div; 3923 unsigned int osc = info->base_clock; 3924 3925 /* div = osc/rate - 1 3926 * 3927 * Round div up if osc/rate is not integer to 3928 * force to next slowest rate. 3929 */ 3930 3931 if (rate) { 3932 div = osc/rate; 3933 if (!(osc % rate) && div) 3934 div--; 3935 wr_reg16(info, BDR, (unsigned short)div); 3936 } 3937 } 3938 3939 static void rx_stop(struct slgt_info *info) 3940 { 3941 unsigned short val; 3942 3943 /* disable and reset receiver */ 3944 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */ 3945 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */ 3946 wr_reg16(info, RCR, val); /* clear reset bit */ 3947 3948 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE); 3949 3950 /* clear pending rx interrupts */ 3951 wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER); 3952 3953 rdma_reset(info); 3954 3955 info->rx_enabled = false; 3956 info->rx_restart = false; 3957 } 3958 3959 static void rx_start(struct slgt_info *info) 3960 { 3961 unsigned short val; 3962 3963 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA); 3964 3965 /* clear pending rx overrun IRQ */ 3966 wr_reg16(info, SSR, IRQ_RXOVER); 3967 3968 /* reset and disable receiver */ 3969 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */ 3970 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */ 3971 wr_reg16(info, RCR, val); /* clear reset bit */ 3972 3973 rdma_reset(info); 3974 reset_rbufs(info); 3975 3976 if (info->rx_pio) { 3977 /* rx request when rx FIFO not empty */ 3978 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14)); 3979 slgt_irq_on(info, IRQ_RXDATA); 3980 if (info->params.mode == MGSL_MODE_ASYNC) { 3981 /* enable saving of rx status */ 3982 wr_reg32(info, RDCSR, BIT6); 3983 } 3984 } else { 3985 /* rx request when rx FIFO half full */ 3986 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14)); 3987 /* set 1st descriptor address */ 3988 wr_reg32(info, RDDAR, info->rbufs[0].pdesc); 3989 3990 if (info->params.mode != MGSL_MODE_ASYNC) { 3991 /* enable rx DMA and DMA interrupt */ 3992 wr_reg32(info, RDCSR, (BIT2 + BIT0)); 3993 } else { 3994 /* enable saving of rx status, rx DMA and DMA interrupt */ 3995 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0)); 3996 } 3997 } 3998 3999 slgt_irq_on(info, IRQ_RXOVER); 4000 4001 /* enable receiver */ 4002 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1)); 4003 4004 info->rx_restart = false; 4005 info->rx_enabled = true; 4006 } 4007 4008 static void tx_start(struct slgt_info *info) 4009 { 4010 if (!info->tx_enabled) { 4011 wr_reg16(info, TCR, 4012 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2)); 4013 info->tx_enabled = true; 4014 } 4015 4016 if (desc_count(info->tbufs[info->tbuf_start])) { 4017 info->drop_rts_on_tx_done = false; 4018 4019 if (info->params.mode != MGSL_MODE_ASYNC) { 4020 if (info->params.flags & HDLC_FLAG_AUTO_RTS) { 4021 get_signals(info); 4022 if (!(info->signals & SerialSignal_RTS)) { 4023 info->signals |= SerialSignal_RTS; 4024 set_signals(info); 4025 info->drop_rts_on_tx_done = true; 4026 } 4027 } 4028 4029 slgt_irq_off(info, IRQ_TXDATA); 4030 slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE); 4031 /* clear tx idle and underrun status bits */ 4032 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER)); 4033 } else { 4034 slgt_irq_off(info, IRQ_TXDATA); 4035 slgt_irq_on(info, IRQ_TXIDLE); 4036 /* clear tx idle status bit */ 4037 wr_reg16(info, SSR, IRQ_TXIDLE); 4038 } 4039 /* set 1st descriptor address and start DMA */ 4040 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc); 4041 wr_reg32(info, TDCSR, BIT2 + BIT0); 4042 info->tx_active = true; 4043 } 4044 } 4045 4046 static void tx_stop(struct slgt_info *info) 4047 { 4048 unsigned short val; 4049 4050 del_timer(&info->tx_timer); 4051 4052 tdma_reset(info); 4053 4054 /* reset and disable transmitter */ 4055 val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */ 4056 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */ 4057 4058 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER); 4059 4060 /* clear tx idle and underrun status bit */ 4061 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER)); 4062 4063 reset_tbufs(info); 4064 4065 info->tx_enabled = false; 4066 info->tx_active = false; 4067 } 4068 4069 static void reset_port(struct slgt_info *info) 4070 { 4071 if (!info->reg_addr) 4072 return; 4073 4074 tx_stop(info); 4075 rx_stop(info); 4076 4077 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR); 4078 set_signals(info); 4079 4080 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER); 4081 } 4082 4083 static void reset_adapter(struct slgt_info *info) 4084 { 4085 int i; 4086 for (i=0; i < info->port_count; ++i) { 4087 if (info->port_array[i]) 4088 reset_port(info->port_array[i]); 4089 } 4090 } 4091 4092 static void async_mode(struct slgt_info *info) 4093 { 4094 unsigned short val; 4095 4096 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER); 4097 tx_stop(info); 4098 rx_stop(info); 4099 4100 /* TCR (tx control) 4101 * 4102 * 15..13 mode, 010=async 4103 * 12..10 encoding, 000=NRZ 4104 * 09 parity enable 4105 * 08 1=odd parity, 0=even parity 4106 * 07 1=RTS driver control 4107 * 06 1=break enable 4108 * 05..04 character length 4109 * 00=5 bits 4110 * 01=6 bits 4111 * 10=7 bits 4112 * 11=8 bits 4113 * 03 0=1 stop bit, 1=2 stop bits 4114 * 02 reset 4115 * 01 enable 4116 * 00 auto-CTS enable 4117 */ 4118 val = 0x4000; 4119 4120 if (info->if_mode & MGSL_INTERFACE_RTS_EN) 4121 val |= BIT7; 4122 4123 if (info->params.parity != ASYNC_PARITY_NONE) { 4124 val |= BIT9; 4125 if (info->params.parity == ASYNC_PARITY_ODD) 4126 val |= BIT8; 4127 } 4128 4129 switch (info->params.data_bits) 4130 { 4131 case 6: val |= BIT4; break; 4132 case 7: val |= BIT5; break; 4133 case 8: val |= BIT5 + BIT4; break; 4134 } 4135 4136 if (info->params.stop_bits != 1) 4137 val |= BIT3; 4138 4139 if (info->params.flags & HDLC_FLAG_AUTO_CTS) 4140 val |= BIT0; 4141 4142 wr_reg16(info, TCR, val); 4143 4144 /* RCR (rx control) 4145 * 4146 * 15..13 mode, 010=async 4147 * 12..10 encoding, 000=NRZ 4148 * 09 parity enable 4149 * 08 1=odd parity, 0=even parity 4150 * 07..06 reserved, must be 0 4151 * 05..04 character length 4152 * 00=5 bits 4153 * 01=6 bits 4154 * 10=7 bits 4155 * 11=8 bits 4156 * 03 reserved, must be zero 4157 * 02 reset 4158 * 01 enable 4159 * 00 auto-DCD enable 4160 */ 4161 val = 0x4000; 4162 4163 if (info->params.parity != ASYNC_PARITY_NONE) { 4164 val |= BIT9; 4165 if (info->params.parity == ASYNC_PARITY_ODD) 4166 val |= BIT8; 4167 } 4168 4169 switch (info->params.data_bits) 4170 { 4171 case 6: val |= BIT4; break; 4172 case 7: val |= BIT5; break; 4173 case 8: val |= BIT5 + BIT4; break; 4174 } 4175 4176 if (info->params.flags & HDLC_FLAG_AUTO_DCD) 4177 val |= BIT0; 4178 4179 wr_reg16(info, RCR, val); 4180 4181 /* CCR (clock control) 4182 * 4183 * 07..05 011 = tx clock source is BRG/16 4184 * 04..02 010 = rx clock source is BRG 4185 * 01 0 = auxclk disabled 4186 * 00 1 = BRG enabled 4187 * 4188 * 0110 1001 4189 */ 4190 wr_reg8(info, CCR, 0x69); 4191 4192 msc_set_vcr(info); 4193 4194 /* SCR (serial control) 4195 * 4196 * 15 1=tx req on FIFO half empty 4197 * 14 1=rx req on FIFO half full 4198 * 13 tx data IRQ enable 4199 * 12 tx idle IRQ enable 4200 * 11 rx break on IRQ enable 4201 * 10 rx data IRQ enable 4202 * 09 rx break off IRQ enable 4203 * 08 overrun IRQ enable 4204 * 07 DSR IRQ enable 4205 * 06 CTS IRQ enable 4206 * 05 DCD IRQ enable 4207 * 04 RI IRQ enable 4208 * 03 0=16x sampling, 1=8x sampling 4209 * 02 1=txd->rxd internal loopback enable 4210 * 01 reserved, must be zero 4211 * 00 1=master IRQ enable 4212 */ 4213 val = BIT15 + BIT14 + BIT0; 4214 /* JCR[8] : 1 = x8 async mode feature available */ 4215 if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate && 4216 ((info->base_clock < (info->params.data_rate * 16)) || 4217 (info->base_clock % (info->params.data_rate * 16)))) { 4218 /* use 8x sampling */ 4219 val |= BIT3; 4220 set_rate(info, info->params.data_rate * 8); 4221 } else { 4222 /* use 16x sampling */ 4223 set_rate(info, info->params.data_rate * 16); 4224 } 4225 wr_reg16(info, SCR, val); 4226 4227 slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER); 4228 4229 if (info->params.loopback) 4230 enable_loopback(info); 4231 } 4232 4233 static void sync_mode(struct slgt_info *info) 4234 { 4235 unsigned short val; 4236 4237 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER); 4238 tx_stop(info); 4239 rx_stop(info); 4240 4241 /* TCR (tx control) 4242 * 4243 * 15..13 mode 4244 * 000=HDLC/SDLC 4245 * 001=raw bit synchronous 4246 * 010=asynchronous/isochronous 4247 * 011=monosync byte synchronous 4248 * 100=bisync byte synchronous 4249 * 101=xsync byte synchronous 4250 * 12..10 encoding 4251 * 09 CRC enable 4252 * 08 CRC32 4253 * 07 1=RTS driver control 4254 * 06 preamble enable 4255 * 05..04 preamble length 4256 * 03 share open/close flag 4257 * 02 reset 4258 * 01 enable 4259 * 00 auto-CTS enable 4260 */ 4261 val = BIT2; 4262 4263 switch(info->params.mode) { 4264 case MGSL_MODE_XSYNC: 4265 val |= BIT15 + BIT13; 4266 break; 4267 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break; 4268 case MGSL_MODE_BISYNC: val |= BIT15; break; 4269 case MGSL_MODE_RAW: val |= BIT13; break; 4270 } 4271 if (info->if_mode & MGSL_INTERFACE_RTS_EN) 4272 val |= BIT7; 4273 4274 switch(info->params.encoding) 4275 { 4276 case HDLC_ENCODING_NRZB: val |= BIT10; break; 4277 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break; 4278 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break; 4279 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break; 4280 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break; 4281 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break; 4282 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; 4283 } 4284 4285 switch (info->params.crc_type & HDLC_CRC_MASK) 4286 { 4287 case HDLC_CRC_16_CCITT: val |= BIT9; break; 4288 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break; 4289 } 4290 4291 if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE) 4292 val |= BIT6; 4293 4294 switch (info->params.preamble_length) 4295 { 4296 case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break; 4297 case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break; 4298 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break; 4299 } 4300 4301 if (info->params.flags & HDLC_FLAG_AUTO_CTS) 4302 val |= BIT0; 4303 4304 wr_reg16(info, TCR, val); 4305 4306 /* TPR (transmit preamble) */ 4307 4308 switch (info->params.preamble) 4309 { 4310 case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break; 4311 case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break; 4312 case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break; 4313 case HDLC_PREAMBLE_PATTERN_10: val = 0x55; break; 4314 case HDLC_PREAMBLE_PATTERN_01: val = 0xaa; break; 4315 default: val = 0x7e; break; 4316 } 4317 wr_reg8(info, TPR, (unsigned char)val); 4318 4319 /* RCR (rx control) 4320 * 4321 * 15..13 mode 4322 * 000=HDLC/SDLC 4323 * 001=raw bit synchronous 4324 * 010=asynchronous/isochronous 4325 * 011=monosync byte synchronous 4326 * 100=bisync byte synchronous 4327 * 101=xsync byte synchronous 4328 * 12..10 encoding 4329 * 09 CRC enable 4330 * 08 CRC32 4331 * 07..03 reserved, must be 0 4332 * 02 reset 4333 * 01 enable 4334 * 00 auto-DCD enable 4335 */ 4336 val = 0; 4337 4338 switch(info->params.mode) { 4339 case MGSL_MODE_XSYNC: 4340 val |= BIT15 + BIT13; 4341 break; 4342 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break; 4343 case MGSL_MODE_BISYNC: val |= BIT15; break; 4344 case MGSL_MODE_RAW: val |= BIT13; break; 4345 } 4346 4347 switch(info->params.encoding) 4348 { 4349 case HDLC_ENCODING_NRZB: val |= BIT10; break; 4350 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break; 4351 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break; 4352 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break; 4353 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break; 4354 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break; 4355 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; 4356 } 4357 4358 switch (info->params.crc_type & HDLC_CRC_MASK) 4359 { 4360 case HDLC_CRC_16_CCITT: val |= BIT9; break; 4361 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break; 4362 } 4363 4364 if (info->params.flags & HDLC_FLAG_AUTO_DCD) 4365 val |= BIT0; 4366 4367 wr_reg16(info, RCR, val); 4368 4369 /* CCR (clock control) 4370 * 4371 * 07..05 tx clock source 4372 * 04..02 rx clock source 4373 * 01 auxclk enable 4374 * 00 BRG enable 4375 */ 4376 val = 0; 4377 4378 if (info->params.flags & HDLC_FLAG_TXC_BRG) 4379 { 4380 // when RxC source is DPLL, BRG generates 16X DPLL 4381 // reference clock, so take TxC from BRG/16 to get 4382 // transmit clock at actual data rate 4383 if (info->params.flags & HDLC_FLAG_RXC_DPLL) 4384 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */ 4385 else 4386 val |= BIT6; /* 010, txclk = BRG */ 4387 } 4388 else if (info->params.flags & HDLC_FLAG_TXC_DPLL) 4389 val |= BIT7; /* 100, txclk = DPLL Input */ 4390 else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN) 4391 val |= BIT5; /* 001, txclk = RXC Input */ 4392 4393 if (info->params.flags & HDLC_FLAG_RXC_BRG) 4394 val |= BIT3; /* 010, rxclk = BRG */ 4395 else if (info->params.flags & HDLC_FLAG_RXC_DPLL) 4396 val |= BIT4; /* 100, rxclk = DPLL */ 4397 else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN) 4398 val |= BIT2; /* 001, rxclk = TXC Input */ 4399 4400 if (info->params.clock_speed) 4401 val |= BIT1 + BIT0; 4402 4403 wr_reg8(info, CCR, (unsigned char)val); 4404 4405 if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL)) 4406 { 4407 // program DPLL mode 4408 switch(info->params.encoding) 4409 { 4410 case HDLC_ENCODING_BIPHASE_MARK: 4411 case HDLC_ENCODING_BIPHASE_SPACE: 4412 val = BIT7; break; 4413 case HDLC_ENCODING_BIPHASE_LEVEL: 4414 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: 4415 val = BIT7 + BIT6; break; 4416 default: val = BIT6; // NRZ encodings 4417 } 4418 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val)); 4419 4420 // DPLL requires a 16X reference clock from BRG 4421 set_rate(info, info->params.clock_speed * 16); 4422 } 4423 else 4424 set_rate(info, info->params.clock_speed); 4425 4426 tx_set_idle(info); 4427 4428 msc_set_vcr(info); 4429 4430 /* SCR (serial control) 4431 * 4432 * 15 1=tx req on FIFO half empty 4433 * 14 1=rx req on FIFO half full 4434 * 13 tx data IRQ enable 4435 * 12 tx idle IRQ enable 4436 * 11 underrun IRQ enable 4437 * 10 rx data IRQ enable 4438 * 09 rx idle IRQ enable 4439 * 08 overrun IRQ enable 4440 * 07 DSR IRQ enable 4441 * 06 CTS IRQ enable 4442 * 05 DCD IRQ enable 4443 * 04 RI IRQ enable 4444 * 03 reserved, must be zero 4445 * 02 1=txd->rxd internal loopback enable 4446 * 01 reserved, must be zero 4447 * 00 1=master IRQ enable 4448 */ 4449 wr_reg16(info, SCR, BIT15 + BIT14 + BIT0); 4450 4451 if (info->params.loopback) 4452 enable_loopback(info); 4453 } 4454 4455 /* 4456 * set transmit idle mode 4457 */ 4458 static void tx_set_idle(struct slgt_info *info) 4459 { 4460 unsigned char val; 4461 unsigned short tcr; 4462 4463 /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits 4464 * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits 4465 */ 4466 tcr = rd_reg16(info, TCR); 4467 if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) { 4468 /* disable preamble, set idle size to 16 bits */ 4469 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4; 4470 /* MSB of 16 bit idle specified in tx preamble register (TPR) */ 4471 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff)); 4472 } else if (!(tcr & BIT6)) { 4473 /* preamble is disabled, set idle size to 8 bits */ 4474 tcr &= ~(BIT5 + BIT4); 4475 } 4476 wr_reg16(info, TCR, tcr); 4477 4478 if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) { 4479 /* LSB of custom tx idle specified in tx idle register */ 4480 val = (unsigned char)(info->idle_mode & 0xff); 4481 } else { 4482 /* standard 8 bit idle patterns */ 4483 switch(info->idle_mode) 4484 { 4485 case HDLC_TXIDLE_FLAGS: val = 0x7e; break; 4486 case HDLC_TXIDLE_ALT_ZEROS_ONES: 4487 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break; 4488 case HDLC_TXIDLE_ZEROS: 4489 case HDLC_TXIDLE_SPACE: val = 0x00; break; 4490 default: val = 0xff; 4491 } 4492 } 4493 4494 wr_reg8(info, TIR, val); 4495 } 4496 4497 /* 4498 * get state of V24 status (input) signals 4499 */ 4500 static void get_signals(struct slgt_info *info) 4501 { 4502 unsigned short status = rd_reg16(info, SSR); 4503 4504 /* clear all serial signals except RTS and DTR */ 4505 info->signals &= SerialSignal_RTS | SerialSignal_DTR; 4506 4507 if (status & BIT3) 4508 info->signals |= SerialSignal_DSR; 4509 if (status & BIT2) 4510 info->signals |= SerialSignal_CTS; 4511 if (status & BIT1) 4512 info->signals |= SerialSignal_DCD; 4513 if (status & BIT0) 4514 info->signals |= SerialSignal_RI; 4515 } 4516 4517 /* 4518 * set V.24 Control Register based on current configuration 4519 */ 4520 static void msc_set_vcr(struct slgt_info *info) 4521 { 4522 unsigned char val = 0; 4523 4524 /* VCR (V.24 control) 4525 * 4526 * 07..04 serial IF select 4527 * 03 DTR 4528 * 02 RTS 4529 * 01 LL 4530 * 00 RL 4531 */ 4532 4533 switch(info->if_mode & MGSL_INTERFACE_MASK) 4534 { 4535 case MGSL_INTERFACE_RS232: 4536 val |= BIT5; /* 0010 */ 4537 break; 4538 case MGSL_INTERFACE_V35: 4539 val |= BIT7 + BIT6 + BIT5; /* 1110 */ 4540 break; 4541 case MGSL_INTERFACE_RS422: 4542 val |= BIT6; /* 0100 */ 4543 break; 4544 } 4545 4546 if (info->if_mode & MGSL_INTERFACE_MSB_FIRST) 4547 val |= BIT4; 4548 if (info->signals & SerialSignal_DTR) 4549 val |= BIT3; 4550 if (info->signals & SerialSignal_RTS) 4551 val |= BIT2; 4552 if (info->if_mode & MGSL_INTERFACE_LL) 4553 val |= BIT1; 4554 if (info->if_mode & MGSL_INTERFACE_RL) 4555 val |= BIT0; 4556 wr_reg8(info, VCR, val); 4557 } 4558 4559 /* 4560 * set state of V24 control (output) signals 4561 */ 4562 static void set_signals(struct slgt_info *info) 4563 { 4564 unsigned char val = rd_reg8(info, VCR); 4565 if (info->signals & SerialSignal_DTR) 4566 val |= BIT3; 4567 else 4568 val &= ~BIT3; 4569 if (info->signals & SerialSignal_RTS) 4570 val |= BIT2; 4571 else 4572 val &= ~BIT2; 4573 wr_reg8(info, VCR, val); 4574 } 4575 4576 /* 4577 * free range of receive DMA buffers (i to last) 4578 */ 4579 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last) 4580 { 4581 int done = 0; 4582 4583 while(!done) { 4584 /* reset current buffer for reuse */ 4585 info->rbufs[i].status = 0; 4586 set_desc_count(info->rbufs[i], info->rbuf_fill_level); 4587 if (i == last) 4588 done = 1; 4589 if (++i == info->rbuf_count) 4590 i = 0; 4591 } 4592 info->rbuf_current = i; 4593 } 4594 4595 /* 4596 * mark all receive DMA buffers as free 4597 */ 4598 static void reset_rbufs(struct slgt_info *info) 4599 { 4600 free_rbufs(info, 0, info->rbuf_count - 1); 4601 info->rbuf_fill_index = 0; 4602 info->rbuf_fill_count = 0; 4603 } 4604 4605 /* 4606 * pass receive HDLC frame to upper layer 4607 * 4608 * return true if frame available, otherwise false 4609 */ 4610 static bool rx_get_frame(struct slgt_info *info) 4611 { 4612 unsigned int start, end; 4613 unsigned short status; 4614 unsigned int framesize = 0; 4615 unsigned long flags; 4616 struct tty_struct *tty = info->port.tty; 4617 unsigned char addr_field = 0xff; 4618 unsigned int crc_size = 0; 4619 4620 switch (info->params.crc_type & HDLC_CRC_MASK) { 4621 case HDLC_CRC_16_CCITT: crc_size = 2; break; 4622 case HDLC_CRC_32_CCITT: crc_size = 4; break; 4623 } 4624 4625 check_again: 4626 4627 framesize = 0; 4628 addr_field = 0xff; 4629 start = end = info->rbuf_current; 4630 4631 for (;;) { 4632 if (!desc_complete(info->rbufs[end])) 4633 goto cleanup; 4634 4635 if (framesize == 0 && info->params.addr_filter != 0xff) 4636 addr_field = info->rbufs[end].buf[0]; 4637 4638 framesize += desc_count(info->rbufs[end]); 4639 4640 if (desc_eof(info->rbufs[end])) 4641 break; 4642 4643 if (++end == info->rbuf_count) 4644 end = 0; 4645 4646 if (end == info->rbuf_current) { 4647 if (info->rx_enabled){ 4648 spin_lock_irqsave(&info->lock,flags); 4649 rx_start(info); 4650 spin_unlock_irqrestore(&info->lock,flags); 4651 } 4652 goto cleanup; 4653 } 4654 } 4655 4656 /* status 4657 * 4658 * 15 buffer complete 4659 * 14..06 reserved 4660 * 05..04 residue 4661 * 02 eof (end of frame) 4662 * 01 CRC error 4663 * 00 abort 4664 */ 4665 status = desc_status(info->rbufs[end]); 4666 4667 /* ignore CRC bit if not using CRC (bit is undefined) */ 4668 if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE) 4669 status &= ~BIT1; 4670 4671 if (framesize == 0 || 4672 (addr_field != 0xff && addr_field != info->params.addr_filter)) { 4673 free_rbufs(info, start, end); 4674 goto check_again; 4675 } 4676 4677 if (framesize < (2 + crc_size) || status & BIT0) { 4678 info->icount.rxshort++; 4679 framesize = 0; 4680 } else if (status & BIT1) { 4681 info->icount.rxcrc++; 4682 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) 4683 framesize = 0; 4684 } 4685 4686 #if SYNCLINK_GENERIC_HDLC 4687 if (framesize == 0) { 4688 info->netdev->stats.rx_errors++; 4689 info->netdev->stats.rx_frame_errors++; 4690 } 4691 #endif 4692 4693 DBGBH(("%s rx frame status=%04X size=%d\n", 4694 info->device_name, status, framesize)); 4695 DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx"); 4696 4697 if (framesize) { 4698 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) { 4699 framesize -= crc_size; 4700 crc_size = 0; 4701 } 4702 4703 if (framesize > info->max_frame_size + crc_size) 4704 info->icount.rxlong++; 4705 else { 4706 /* copy dma buffer(s) to contiguous temp buffer */ 4707 int copy_count = framesize; 4708 int i = start; 4709 unsigned char *p = info->tmp_rbuf; 4710 info->tmp_rbuf_count = framesize; 4711 4712 info->icount.rxok++; 4713 4714 while(copy_count) { 4715 int partial_count = min_t(int, copy_count, info->rbuf_fill_level); 4716 memcpy(p, info->rbufs[i].buf, partial_count); 4717 p += partial_count; 4718 copy_count -= partial_count; 4719 if (++i == info->rbuf_count) 4720 i = 0; 4721 } 4722 4723 if (info->params.crc_type & HDLC_CRC_RETURN_EX) { 4724 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK; 4725 framesize++; 4726 } 4727 4728 #if SYNCLINK_GENERIC_HDLC 4729 if (info->netcount) 4730 hdlcdev_rx(info,info->tmp_rbuf, framesize); 4731 else 4732 #endif 4733 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize); 4734 } 4735 } 4736 free_rbufs(info, start, end); 4737 return true; 4738 4739 cleanup: 4740 return false; 4741 } 4742 4743 /* 4744 * pass receive buffer (RAW synchronous mode) to tty layer 4745 * return true if buffer available, otherwise false 4746 */ 4747 static bool rx_get_buf(struct slgt_info *info) 4748 { 4749 unsigned int i = info->rbuf_current; 4750 unsigned int count; 4751 4752 if (!desc_complete(info->rbufs[i])) 4753 return false; 4754 count = desc_count(info->rbufs[i]); 4755 switch(info->params.mode) { 4756 case MGSL_MODE_MONOSYNC: 4757 case MGSL_MODE_BISYNC: 4758 case MGSL_MODE_XSYNC: 4759 /* ignore residue in byte synchronous modes */ 4760 if (desc_residue(info->rbufs[i])) 4761 count--; 4762 break; 4763 } 4764 DBGDATA(info, info->rbufs[i].buf, count, "rx"); 4765 DBGINFO(("rx_get_buf size=%d\n", count)); 4766 if (count) 4767 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf, 4768 info->flag_buf, count); 4769 free_rbufs(info, i, i); 4770 return true; 4771 } 4772 4773 static void reset_tbufs(struct slgt_info *info) 4774 { 4775 unsigned int i; 4776 info->tbuf_current = 0; 4777 for (i=0 ; i < info->tbuf_count ; i++) { 4778 info->tbufs[i].status = 0; 4779 info->tbufs[i].count = 0; 4780 } 4781 } 4782 4783 /* 4784 * return number of free transmit DMA buffers 4785 */ 4786 static unsigned int free_tbuf_count(struct slgt_info *info) 4787 { 4788 unsigned int count = 0; 4789 unsigned int i = info->tbuf_current; 4790 4791 do 4792 { 4793 if (desc_count(info->tbufs[i])) 4794 break; /* buffer in use */ 4795 ++count; 4796 if (++i == info->tbuf_count) 4797 i=0; 4798 } while (i != info->tbuf_current); 4799 4800 /* if tx DMA active, last zero count buffer is in use */ 4801 if (count && (rd_reg32(info, TDCSR) & BIT0)) 4802 --count; 4803 4804 return count; 4805 } 4806 4807 /* 4808 * return number of bytes in unsent transmit DMA buffers 4809 * and the serial controller tx FIFO 4810 */ 4811 static unsigned int tbuf_bytes(struct slgt_info *info) 4812 { 4813 unsigned int total_count = 0; 4814 unsigned int i = info->tbuf_current; 4815 unsigned int reg_value; 4816 unsigned int count; 4817 unsigned int active_buf_count = 0; 4818 4819 /* 4820 * Add descriptor counts for all tx DMA buffers. 4821 * If count is zero (cleared by DMA controller after read), 4822 * the buffer is complete or is actively being read from. 4823 * 4824 * Record buf_count of last buffer with zero count starting 4825 * from current ring position. buf_count is mirror 4826 * copy of count and is not cleared by serial controller. 4827 * If DMA controller is active, that buffer is actively 4828 * being read so add to total. 4829 */ 4830 do { 4831 count = desc_count(info->tbufs[i]); 4832 if (count) 4833 total_count += count; 4834 else if (!total_count) 4835 active_buf_count = info->tbufs[i].buf_count; 4836 if (++i == info->tbuf_count) 4837 i = 0; 4838 } while (i != info->tbuf_current); 4839 4840 /* read tx DMA status register */ 4841 reg_value = rd_reg32(info, TDCSR); 4842 4843 /* if tx DMA active, last zero count buffer is in use */ 4844 if (reg_value & BIT0) 4845 total_count += active_buf_count; 4846 4847 /* add tx FIFO count = reg_value[15..8] */ 4848 total_count += (reg_value >> 8) & 0xff; 4849 4850 /* if transmitter active add one byte for shift register */ 4851 if (info->tx_active) 4852 total_count++; 4853 4854 return total_count; 4855 } 4856 4857 /* 4858 * load data into transmit DMA buffer ring and start transmitter if needed 4859 * return true if data accepted, otherwise false (buffers full) 4860 */ 4861 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int size) 4862 { 4863 unsigned short count; 4864 unsigned int i; 4865 struct slgt_desc *d; 4866 4867 /* check required buffer space */ 4868 if (DIV_ROUND_UP(size, DMABUFSIZE) > free_tbuf_count(info)) 4869 return false; 4870 4871 DBGDATA(info, buf, size, "tx"); 4872 4873 /* 4874 * copy data to one or more DMA buffers in circular ring 4875 * tbuf_start = first buffer for this data 4876 * tbuf_current = next free buffer 4877 * 4878 * Copy all data before making data visible to DMA controller by 4879 * setting descriptor count of the first buffer. 4880 * This prevents an active DMA controller from reading the first DMA 4881 * buffers of a frame and stopping before the final buffers are filled. 4882 */ 4883 4884 info->tbuf_start = i = info->tbuf_current; 4885 4886 while (size) { 4887 d = &info->tbufs[i]; 4888 4889 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size); 4890 memcpy(d->buf, buf, count); 4891 4892 size -= count; 4893 buf += count; 4894 4895 /* 4896 * set EOF bit for last buffer of HDLC frame or 4897 * for every buffer in raw mode 4898 */ 4899 if ((!size && info->params.mode == MGSL_MODE_HDLC) || 4900 info->params.mode == MGSL_MODE_RAW) 4901 set_desc_eof(*d, 1); 4902 else 4903 set_desc_eof(*d, 0); 4904 4905 /* set descriptor count for all but first buffer */ 4906 if (i != info->tbuf_start) 4907 set_desc_count(*d, count); 4908 d->buf_count = count; 4909 4910 if (++i == info->tbuf_count) 4911 i = 0; 4912 } 4913 4914 info->tbuf_current = i; 4915 4916 /* set first buffer count to make new data visible to DMA controller */ 4917 d = &info->tbufs[info->tbuf_start]; 4918 set_desc_count(*d, d->buf_count); 4919 4920 /* start transmitter if needed and update transmit timeout */ 4921 if (!info->tx_active) 4922 tx_start(info); 4923 update_tx_timer(info); 4924 4925 return true; 4926 } 4927 4928 static int register_test(struct slgt_info *info) 4929 { 4930 static unsigned short patterns[] = 4931 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696}; 4932 static unsigned int count = ARRAY_SIZE(patterns); 4933 unsigned int i; 4934 int rc = 0; 4935 4936 for (i=0 ; i < count ; i++) { 4937 wr_reg16(info, TIR, patterns[i]); 4938 wr_reg16(info, BDR, patterns[(i+1)%count]); 4939 if ((rd_reg16(info, TIR) != patterns[i]) || 4940 (rd_reg16(info, BDR) != patterns[(i+1)%count])) { 4941 rc = -ENODEV; 4942 break; 4943 } 4944 } 4945 info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0; 4946 info->init_error = rc ? 0 : DiagStatus_AddressFailure; 4947 return rc; 4948 } 4949 4950 static int irq_test(struct slgt_info *info) 4951 { 4952 unsigned long timeout; 4953 unsigned long flags; 4954 struct tty_struct *oldtty = info->port.tty; 4955 u32 speed = info->params.data_rate; 4956 4957 info->params.data_rate = 921600; 4958 info->port.tty = NULL; 4959 4960 spin_lock_irqsave(&info->lock, flags); 4961 async_mode(info); 4962 slgt_irq_on(info, IRQ_TXIDLE); 4963 4964 /* enable transmitter */ 4965 wr_reg16(info, TCR, 4966 (unsigned short)(rd_reg16(info, TCR) | BIT1)); 4967 4968 /* write one byte and wait for tx idle */ 4969 wr_reg16(info, TDR, 0); 4970 4971 /* assume failure */ 4972 info->init_error = DiagStatus_IrqFailure; 4973 info->irq_occurred = false; 4974 4975 spin_unlock_irqrestore(&info->lock, flags); 4976 4977 timeout=100; 4978 while(timeout-- && !info->irq_occurred) 4979 msleep_interruptible(10); 4980 4981 spin_lock_irqsave(&info->lock,flags); 4982 reset_port(info); 4983 spin_unlock_irqrestore(&info->lock,flags); 4984 4985 info->params.data_rate = speed; 4986 info->port.tty = oldtty; 4987 4988 info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure; 4989 return info->irq_occurred ? 0 : -ENODEV; 4990 } 4991 4992 static int loopback_test_rx(struct slgt_info *info) 4993 { 4994 unsigned char *src, *dest; 4995 int count; 4996 4997 if (desc_complete(info->rbufs[0])) { 4998 count = desc_count(info->rbufs[0]); 4999 src = info->rbufs[0].buf; 5000 dest = info->tmp_rbuf; 5001 5002 for( ; count ; count-=2, src+=2) { 5003 /* src=data byte (src+1)=status byte */ 5004 if (!(*(src+1) & (BIT9 + BIT8))) { 5005 *dest = *src; 5006 dest++; 5007 info->tmp_rbuf_count++; 5008 } 5009 } 5010 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx"); 5011 return 1; 5012 } 5013 return 0; 5014 } 5015 5016 static int loopback_test(struct slgt_info *info) 5017 { 5018 #define TESTFRAMESIZE 20 5019 5020 unsigned long timeout; 5021 u16 count = TESTFRAMESIZE; 5022 unsigned char buf[TESTFRAMESIZE]; 5023 int rc = -ENODEV; 5024 unsigned long flags; 5025 5026 struct tty_struct *oldtty = info->port.tty; 5027 MGSL_PARAMS params; 5028 5029 memcpy(¶ms, &info->params, sizeof(params)); 5030 5031 info->params.mode = MGSL_MODE_ASYNC; 5032 info->params.data_rate = 921600; 5033 info->params.loopback = 1; 5034 info->port.tty = NULL; 5035 5036 /* build and send transmit frame */ 5037 for (count = 0; count < TESTFRAMESIZE; ++count) 5038 buf[count] = (unsigned char)count; 5039 5040 info->tmp_rbuf_count = 0; 5041 memset(info->tmp_rbuf, 0, TESTFRAMESIZE); 5042 5043 /* program hardware for HDLC and enabled receiver */ 5044 spin_lock_irqsave(&info->lock,flags); 5045 async_mode(info); 5046 rx_start(info); 5047 tx_load(info, buf, count); 5048 spin_unlock_irqrestore(&info->lock, flags); 5049 5050 /* wait for receive complete */ 5051 for (timeout = 100; timeout; --timeout) { 5052 msleep_interruptible(10); 5053 if (loopback_test_rx(info)) { 5054 rc = 0; 5055 break; 5056 } 5057 } 5058 5059 /* verify received frame length and contents */ 5060 if (!rc && (info->tmp_rbuf_count != count || 5061 memcmp(buf, info->tmp_rbuf, count))) { 5062 rc = -ENODEV; 5063 } 5064 5065 spin_lock_irqsave(&info->lock,flags); 5066 reset_adapter(info); 5067 spin_unlock_irqrestore(&info->lock,flags); 5068 5069 memcpy(&info->params, ¶ms, sizeof(info->params)); 5070 info->port.tty = oldtty; 5071 5072 info->init_error = rc ? DiagStatus_DmaFailure : 0; 5073 return rc; 5074 } 5075 5076 static int adapter_test(struct slgt_info *info) 5077 { 5078 DBGINFO(("testing %s\n", info->device_name)); 5079 if (register_test(info) < 0) { 5080 printk("register test failure %s addr=%08X\n", 5081 info->device_name, info->phys_reg_addr); 5082 } else if (irq_test(info) < 0) { 5083 printk("IRQ test failure %s IRQ=%d\n", 5084 info->device_name, info->irq_level); 5085 } else if (loopback_test(info) < 0) { 5086 printk("loopback test failure %s\n", info->device_name); 5087 } 5088 return info->init_error; 5089 } 5090 5091 /* 5092 * transmit timeout handler 5093 */ 5094 static void tx_timeout(struct timer_list *t) 5095 { 5096 struct slgt_info *info = from_timer(info, t, tx_timer); 5097 unsigned long flags; 5098 5099 DBGINFO(("%s tx_timeout\n", info->device_name)); 5100 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) { 5101 info->icount.txtimeout++; 5102 } 5103 spin_lock_irqsave(&info->lock,flags); 5104 tx_stop(info); 5105 spin_unlock_irqrestore(&info->lock,flags); 5106 5107 #if SYNCLINK_GENERIC_HDLC 5108 if (info->netcount) 5109 hdlcdev_tx_done(info); 5110 else 5111 #endif 5112 bh_transmit(info); 5113 } 5114 5115 /* 5116 * receive buffer polling timer 5117 */ 5118 static void rx_timeout(struct timer_list *t) 5119 { 5120 struct slgt_info *info = from_timer(info, t, rx_timer); 5121 unsigned long flags; 5122 5123 DBGINFO(("%s rx_timeout\n", info->device_name)); 5124 spin_lock_irqsave(&info->lock, flags); 5125 info->pending_bh |= BH_RECEIVE; 5126 spin_unlock_irqrestore(&info->lock, flags); 5127 bh_handler(&info->task); 5128 } 5129 5130