1 // SPDX-License-Identifier: GPL-1.0+ 2 /* 3 * Device driver for Microgate SyncLink GT serial adapters. 4 * 5 * written by Paul Fulghum for Microgate Corporation 6 * paulkf@microgate.com 7 * 8 * Microgate and SyncLink are trademarks of Microgate Corporation 9 * 10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 12 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 13 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 14 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 15 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 16 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 17 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 18 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 19 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 20 * OF THE POSSIBILITY OF SUCH DAMAGE. 21 */ 22 23 /* 24 * DEBUG OUTPUT DEFINITIONS 25 * 26 * uncomment lines below to enable specific types of debug output 27 * 28 * DBGINFO information - most verbose output 29 * DBGERR serious errors 30 * DBGBH bottom half service routine debugging 31 * DBGISR interrupt service routine debugging 32 * DBGDATA output receive and transmit data 33 * DBGTBUF output transmit DMA buffers and registers 34 * DBGRBUF output receive DMA buffers and registers 35 */ 36 37 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt 38 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt 39 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt 40 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt 41 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label)) 42 /*#define DBGTBUF(info) dump_tbufs(info)*/ 43 /*#define DBGRBUF(info) dump_rbufs(info)*/ 44 45 46 #include <linux/module.h> 47 #include <linux/errno.h> 48 #include <linux/signal.h> 49 #include <linux/sched.h> 50 #include <linux/timer.h> 51 #include <linux/interrupt.h> 52 #include <linux/pci.h> 53 #include <linux/tty.h> 54 #include <linux/tty_flip.h> 55 #include <linux/serial.h> 56 #include <linux/major.h> 57 #include <linux/string.h> 58 #include <linux/fcntl.h> 59 #include <linux/ptrace.h> 60 #include <linux/ioport.h> 61 #include <linux/mm.h> 62 #include <linux/seq_file.h> 63 #include <linux/slab.h> 64 #include <linux/netdevice.h> 65 #include <linux/vmalloc.h> 66 #include <linux/init.h> 67 #include <linux/delay.h> 68 #include <linux/ioctl.h> 69 #include <linux/termios.h> 70 #include <linux/bitops.h> 71 #include <linux/workqueue.h> 72 #include <linux/hdlc.h> 73 #include <linux/synclink.h> 74 75 #include <asm/io.h> 76 #include <asm/irq.h> 77 #include <asm/dma.h> 78 #include <asm/types.h> 79 #include <linux/uaccess.h> 80 81 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE)) 82 #define SYNCLINK_GENERIC_HDLC 1 83 #else 84 #define SYNCLINK_GENERIC_HDLC 0 85 #endif 86 87 /* 88 * module identification 89 */ 90 static char *driver_name = "SyncLink GT"; 91 static char *slgt_driver_name = "synclink_gt"; 92 static char *tty_dev_prefix = "ttySLG"; 93 MODULE_LICENSE("GPL"); 94 #define MAX_DEVICES 32 95 96 static const struct pci_device_id pci_table[] = { 97 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, 98 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, 99 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, 100 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, 101 {0,}, /* terminate list */ 102 }; 103 MODULE_DEVICE_TABLE(pci, pci_table); 104 105 static int init_one(struct pci_dev *dev,const struct pci_device_id *ent); 106 static void remove_one(struct pci_dev *dev); 107 static struct pci_driver pci_driver = { 108 .name = "synclink_gt", 109 .id_table = pci_table, 110 .probe = init_one, 111 .remove = remove_one, 112 }; 113 114 static bool pci_registered; 115 116 /* 117 * module configuration and status 118 */ 119 static struct slgt_info *slgt_device_list; 120 static int slgt_device_count; 121 122 static int ttymajor; 123 static int debug_level; 124 static int maxframe[MAX_DEVICES]; 125 126 module_param(ttymajor, int, 0); 127 module_param(debug_level, int, 0); 128 module_param_array(maxframe, int, NULL, 0); 129 130 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned"); 131 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail"); 132 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)"); 133 134 /* 135 * tty support and callbacks 136 */ 137 static struct tty_driver *serial_driver; 138 139 static void wait_until_sent(struct tty_struct *tty, int timeout); 140 static void flush_buffer(struct tty_struct *tty); 141 static void tx_release(struct tty_struct *tty); 142 143 /* 144 * generic HDLC support 145 */ 146 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 147 148 149 /* 150 * device specific structures, macros and functions 151 */ 152 153 #define SLGT_MAX_PORTS 4 154 #define SLGT_REG_SIZE 256 155 156 /* 157 * conditional wait facility 158 */ 159 struct cond_wait { 160 struct cond_wait *next; 161 wait_queue_head_t q; 162 wait_queue_entry_t wait; 163 unsigned int data; 164 }; 165 static void flush_cond_wait(struct cond_wait **head); 166 167 /* 168 * DMA buffer descriptor and access macros 169 */ 170 struct slgt_desc 171 { 172 __le16 count; 173 __le16 status; 174 __le32 pbuf; /* physical address of data buffer */ 175 __le32 next; /* physical address of next descriptor */ 176 177 /* driver book keeping */ 178 char *buf; /* virtual address of data buffer */ 179 unsigned int pdesc; /* physical address of this descriptor */ 180 dma_addr_t buf_dma_addr; 181 unsigned short buf_count; 182 }; 183 184 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b)) 185 #define set_desc_next(a,b) (a).next = cpu_to_le32((unsigned int)(b)) 186 #define set_desc_count(a,b)(a).count = cpu_to_le16((unsigned short)(b)) 187 #define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0)) 188 #define set_desc_status(a, b) (a).status = cpu_to_le16((unsigned short)(b)) 189 #define desc_count(a) (le16_to_cpu((a).count)) 190 #define desc_status(a) (le16_to_cpu((a).status)) 191 #define desc_complete(a) (le16_to_cpu((a).status) & BIT15) 192 #define desc_eof(a) (le16_to_cpu((a).status) & BIT2) 193 #define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1) 194 #define desc_abort(a) (le16_to_cpu((a).status) & BIT0) 195 #define desc_residue(a) ((le16_to_cpu((a).status) & 0x38) >> 3) 196 197 struct _input_signal_events { 198 int ri_up; 199 int ri_down; 200 int dsr_up; 201 int dsr_down; 202 int dcd_up; 203 int dcd_down; 204 int cts_up; 205 int cts_down; 206 }; 207 208 /* 209 * device instance data structure 210 */ 211 struct slgt_info { 212 void *if_ptr; /* General purpose pointer (used by SPPP) */ 213 struct tty_port port; 214 215 struct slgt_info *next_device; /* device list link */ 216 217 char device_name[25]; 218 struct pci_dev *pdev; 219 220 int port_count; /* count of ports on adapter */ 221 int adapter_num; /* adapter instance number */ 222 int port_num; /* port instance number */ 223 224 /* array of pointers to port contexts on this adapter */ 225 struct slgt_info *port_array[SLGT_MAX_PORTS]; 226 227 int line; /* tty line instance number */ 228 229 struct mgsl_icount icount; 230 231 int timeout; 232 int x_char; /* xon/xoff character */ 233 unsigned int read_status_mask; 234 unsigned int ignore_status_mask; 235 236 wait_queue_head_t status_event_wait_q; 237 wait_queue_head_t event_wait_q; 238 struct timer_list tx_timer; 239 struct timer_list rx_timer; 240 241 unsigned int gpio_present; 242 struct cond_wait *gpio_wait_q; 243 244 spinlock_t lock; /* spinlock for synchronizing with ISR */ 245 246 struct work_struct task; 247 u32 pending_bh; 248 bool bh_requested; 249 bool bh_running; 250 251 int isr_overflow; 252 bool irq_requested; /* true if IRQ requested */ 253 bool irq_occurred; /* for diagnostics use */ 254 255 /* device configuration */ 256 257 unsigned int bus_type; 258 unsigned int irq_level; 259 unsigned long irq_flags; 260 261 unsigned char __iomem * reg_addr; /* memory mapped registers address */ 262 u32 phys_reg_addr; 263 bool reg_addr_requested; 264 265 MGSL_PARAMS params; /* communications parameters */ 266 u32 idle_mode; 267 u32 max_frame_size; /* as set by device config */ 268 269 unsigned int rbuf_fill_level; 270 unsigned int rx_pio; 271 unsigned int if_mode; 272 unsigned int base_clock; 273 unsigned int xsync; 274 unsigned int xctrl; 275 276 /* device status */ 277 278 bool rx_enabled; 279 bool rx_restart; 280 281 bool tx_enabled; 282 bool tx_active; 283 284 unsigned char signals; /* serial signal states */ 285 int init_error; /* initialization error */ 286 287 unsigned char *tx_buf; 288 int tx_count; 289 290 bool drop_rts_on_tx_done; 291 struct _input_signal_events input_signal_events; 292 293 int dcd_chkcount; /* check counts to prevent */ 294 int cts_chkcount; /* too many IRQs if a signal */ 295 int dsr_chkcount; /* is floating */ 296 int ri_chkcount; 297 298 char *bufs; /* virtual address of DMA buffer lists */ 299 dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */ 300 301 unsigned int rbuf_count; 302 struct slgt_desc *rbufs; 303 unsigned int rbuf_current; 304 unsigned int rbuf_index; 305 unsigned int rbuf_fill_index; 306 unsigned short rbuf_fill_count; 307 308 unsigned int tbuf_count; 309 struct slgt_desc *tbufs; 310 unsigned int tbuf_current; 311 unsigned int tbuf_start; 312 313 unsigned char *tmp_rbuf; 314 unsigned int tmp_rbuf_count; 315 316 /* SPPP/Cisco HDLC device parts */ 317 318 int netcount; 319 spinlock_t netlock; 320 #if SYNCLINK_GENERIC_HDLC 321 struct net_device *netdev; 322 #endif 323 324 }; 325 326 static MGSL_PARAMS default_params = { 327 .mode = MGSL_MODE_HDLC, 328 .loopback = 0, 329 .flags = HDLC_FLAG_UNDERRUN_ABORT15, 330 .encoding = HDLC_ENCODING_NRZI_SPACE, 331 .clock_speed = 0, 332 .addr_filter = 0xff, 333 .crc_type = HDLC_CRC_16_CCITT, 334 .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS, 335 .preamble = HDLC_PREAMBLE_PATTERN_NONE, 336 .data_rate = 9600, 337 .data_bits = 8, 338 .stop_bits = 1, 339 .parity = ASYNC_PARITY_NONE 340 }; 341 342 343 #define BH_RECEIVE 1 344 #define BH_TRANSMIT 2 345 #define BH_STATUS 4 346 #define IO_PIN_SHUTDOWN_LIMIT 100 347 348 #define DMABUFSIZE 256 349 #define DESC_LIST_SIZE 4096 350 351 #define MASK_PARITY BIT1 352 #define MASK_FRAMING BIT0 353 #define MASK_BREAK BIT14 354 #define MASK_OVERRUN BIT4 355 356 #define GSR 0x00 /* global status */ 357 #define JCR 0x04 /* JTAG control */ 358 #define IODR 0x08 /* GPIO direction */ 359 #define IOER 0x0c /* GPIO interrupt enable */ 360 #define IOVR 0x10 /* GPIO value */ 361 #define IOSR 0x14 /* GPIO interrupt status */ 362 #define TDR 0x80 /* tx data */ 363 #define RDR 0x80 /* rx data */ 364 #define TCR 0x82 /* tx control */ 365 #define TIR 0x84 /* tx idle */ 366 #define TPR 0x85 /* tx preamble */ 367 #define RCR 0x86 /* rx control */ 368 #define VCR 0x88 /* V.24 control */ 369 #define CCR 0x89 /* clock control */ 370 #define BDR 0x8a /* baud divisor */ 371 #define SCR 0x8c /* serial control */ 372 #define SSR 0x8e /* serial status */ 373 #define RDCSR 0x90 /* rx DMA control/status */ 374 #define TDCSR 0x94 /* tx DMA control/status */ 375 #define RDDAR 0x98 /* rx DMA descriptor address */ 376 #define TDDAR 0x9c /* tx DMA descriptor address */ 377 #define XSR 0x40 /* extended sync pattern */ 378 #define XCR 0x44 /* extended control */ 379 380 #define RXIDLE BIT14 381 #define RXBREAK BIT14 382 #define IRQ_TXDATA BIT13 383 #define IRQ_TXIDLE BIT12 384 #define IRQ_TXUNDER BIT11 /* HDLC */ 385 #define IRQ_RXDATA BIT10 386 #define IRQ_RXIDLE BIT9 /* HDLC */ 387 #define IRQ_RXBREAK BIT9 /* async */ 388 #define IRQ_RXOVER BIT8 389 #define IRQ_DSR BIT7 390 #define IRQ_CTS BIT6 391 #define IRQ_DCD BIT5 392 #define IRQ_RI BIT4 393 #define IRQ_ALL 0x3ff0 394 #define IRQ_MASTER BIT0 395 396 #define slgt_irq_on(info, mask) \ 397 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask))) 398 #define slgt_irq_off(info, mask) \ 399 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask))) 400 401 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr); 402 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value); 403 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr); 404 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value); 405 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr); 406 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value); 407 408 static void msc_set_vcr(struct slgt_info *info); 409 410 static int startup(struct slgt_info *info); 411 static int block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info); 412 static void shutdown(struct slgt_info *info); 413 static void program_hw(struct slgt_info *info); 414 static void change_params(struct slgt_info *info); 415 416 static int adapter_test(struct slgt_info *info); 417 418 static void reset_port(struct slgt_info *info); 419 static void async_mode(struct slgt_info *info); 420 static void sync_mode(struct slgt_info *info); 421 422 static void rx_stop(struct slgt_info *info); 423 static void rx_start(struct slgt_info *info); 424 static void reset_rbufs(struct slgt_info *info); 425 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last); 426 static bool rx_get_frame(struct slgt_info *info); 427 static bool rx_get_buf(struct slgt_info *info); 428 429 static void tx_start(struct slgt_info *info); 430 static void tx_stop(struct slgt_info *info); 431 static void tx_set_idle(struct slgt_info *info); 432 static unsigned int tbuf_bytes(struct slgt_info *info); 433 static void reset_tbufs(struct slgt_info *info); 434 static void tdma_reset(struct slgt_info *info); 435 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int count); 436 437 static void get_gtsignals(struct slgt_info *info); 438 static void set_gtsignals(struct slgt_info *info); 439 static void set_rate(struct slgt_info *info, u32 data_rate); 440 441 static void bh_transmit(struct slgt_info *info); 442 static void isr_txeom(struct slgt_info *info, unsigned short status); 443 444 static void tx_timeout(struct timer_list *t); 445 static void rx_timeout(struct timer_list *t); 446 447 /* 448 * ioctl handlers 449 */ 450 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount); 451 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *params); 452 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *params); 453 static int get_txidle(struct slgt_info *info, int __user *idle_mode); 454 static int set_txidle(struct slgt_info *info, int idle_mode); 455 static int tx_enable(struct slgt_info *info, int enable); 456 static int tx_abort(struct slgt_info *info); 457 static int rx_enable(struct slgt_info *info, int enable); 458 static int modem_input_wait(struct slgt_info *info,int arg); 459 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr); 460 static int get_interface(struct slgt_info *info, int __user *if_mode); 461 static int set_interface(struct slgt_info *info, int if_mode); 462 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio); 463 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio); 464 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio); 465 static int get_xsync(struct slgt_info *info, int __user *if_mode); 466 static int set_xsync(struct slgt_info *info, int if_mode); 467 static int get_xctrl(struct slgt_info *info, int __user *if_mode); 468 static int set_xctrl(struct slgt_info *info, int if_mode); 469 470 /* 471 * driver functions 472 */ 473 static void release_resources(struct slgt_info *info); 474 475 /* 476 * DEBUG OUTPUT CODE 477 */ 478 #ifndef DBGINFO 479 #define DBGINFO(fmt) 480 #endif 481 #ifndef DBGERR 482 #define DBGERR(fmt) 483 #endif 484 #ifndef DBGBH 485 #define DBGBH(fmt) 486 #endif 487 #ifndef DBGISR 488 #define DBGISR(fmt) 489 #endif 490 491 #ifdef DBGDATA 492 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label) 493 { 494 int i; 495 int linecount; 496 printk("%s %s data:\n",info->device_name, label); 497 while(count) { 498 linecount = (count > 16) ? 16 : count; 499 for(i=0; i < linecount; i++) 500 printk("%02X ",(unsigned char)data[i]); 501 for(;i<17;i++) 502 printk(" "); 503 for(i=0;i<linecount;i++) { 504 if (data[i]>=040 && data[i]<=0176) 505 printk("%c",data[i]); 506 else 507 printk("."); 508 } 509 printk("\n"); 510 data += linecount; 511 count -= linecount; 512 } 513 } 514 #else 515 #define DBGDATA(info, buf, size, label) 516 #endif 517 518 #ifdef DBGTBUF 519 static void dump_tbufs(struct slgt_info *info) 520 { 521 int i; 522 printk("tbuf_current=%d\n", info->tbuf_current); 523 for (i=0 ; i < info->tbuf_count ; i++) { 524 printk("%d: count=%04X status=%04X\n", 525 i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status)); 526 } 527 } 528 #else 529 #define DBGTBUF(info) 530 #endif 531 532 #ifdef DBGRBUF 533 static void dump_rbufs(struct slgt_info *info) 534 { 535 int i; 536 printk("rbuf_current=%d\n", info->rbuf_current); 537 for (i=0 ; i < info->rbuf_count ; i++) { 538 printk("%d: count=%04X status=%04X\n", 539 i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status)); 540 } 541 } 542 #else 543 #define DBGRBUF(info) 544 #endif 545 546 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name) 547 { 548 #ifdef SANITY_CHECK 549 if (!info) { 550 printk("null struct slgt_info for (%s) in %s\n", devname, name); 551 return 1; 552 } 553 #else 554 if (!info) 555 return 1; 556 #endif 557 return 0; 558 } 559 560 /* 561 * line discipline callback wrappers 562 * 563 * The wrappers maintain line discipline references 564 * while calling into the line discipline. 565 * 566 * ldisc_receive_buf - pass receive data to line discipline 567 */ 568 static void ldisc_receive_buf(struct tty_struct *tty, 569 const __u8 *data, char *flags, int count) 570 { 571 struct tty_ldisc *ld; 572 if (!tty) 573 return; 574 ld = tty_ldisc_ref(tty); 575 if (ld) { 576 if (ld->ops->receive_buf) 577 ld->ops->receive_buf(tty, data, flags, count); 578 tty_ldisc_deref(ld); 579 } 580 } 581 582 /* tty callbacks */ 583 584 static int open(struct tty_struct *tty, struct file *filp) 585 { 586 struct slgt_info *info; 587 int retval, line; 588 unsigned long flags; 589 590 line = tty->index; 591 if (line >= slgt_device_count) { 592 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line)); 593 return -ENODEV; 594 } 595 596 info = slgt_device_list; 597 while(info && info->line != line) 598 info = info->next_device; 599 if (sanity_check(info, tty->name, "open")) 600 return -ENODEV; 601 if (info->init_error) { 602 DBGERR(("%s init error=%d\n", info->device_name, info->init_error)); 603 return -ENODEV; 604 } 605 606 tty->driver_data = info; 607 info->port.tty = tty; 608 609 DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count)); 610 611 mutex_lock(&info->port.mutex); 612 613 spin_lock_irqsave(&info->netlock, flags); 614 if (info->netcount) { 615 retval = -EBUSY; 616 spin_unlock_irqrestore(&info->netlock, flags); 617 mutex_unlock(&info->port.mutex); 618 goto cleanup; 619 } 620 info->port.count++; 621 spin_unlock_irqrestore(&info->netlock, flags); 622 623 if (info->port.count == 1) { 624 /* 1st open on this device, init hardware */ 625 retval = startup(info); 626 if (retval < 0) { 627 mutex_unlock(&info->port.mutex); 628 goto cleanup; 629 } 630 } 631 mutex_unlock(&info->port.mutex); 632 retval = block_til_ready(tty, filp, info); 633 if (retval) { 634 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval)); 635 goto cleanup; 636 } 637 638 retval = 0; 639 640 cleanup: 641 if (retval) { 642 if (tty->count == 1) 643 info->port.tty = NULL; /* tty layer will release tty struct */ 644 if(info->port.count) 645 info->port.count--; 646 } 647 648 DBGINFO(("%s open rc=%d\n", info->device_name, retval)); 649 return retval; 650 } 651 652 static void close(struct tty_struct *tty, struct file *filp) 653 { 654 struct slgt_info *info = tty->driver_data; 655 656 if (sanity_check(info, tty->name, "close")) 657 return; 658 DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count)); 659 660 if (tty_port_close_start(&info->port, tty, filp) == 0) 661 goto cleanup; 662 663 mutex_lock(&info->port.mutex); 664 if (tty_port_initialized(&info->port)) 665 wait_until_sent(tty, info->timeout); 666 flush_buffer(tty); 667 tty_ldisc_flush(tty); 668 669 shutdown(info); 670 mutex_unlock(&info->port.mutex); 671 672 tty_port_close_end(&info->port, tty); 673 info->port.tty = NULL; 674 cleanup: 675 DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count)); 676 } 677 678 static void hangup(struct tty_struct *tty) 679 { 680 struct slgt_info *info = tty->driver_data; 681 unsigned long flags; 682 683 if (sanity_check(info, tty->name, "hangup")) 684 return; 685 DBGINFO(("%s hangup\n", info->device_name)); 686 687 flush_buffer(tty); 688 689 mutex_lock(&info->port.mutex); 690 shutdown(info); 691 692 spin_lock_irqsave(&info->port.lock, flags); 693 info->port.count = 0; 694 info->port.tty = NULL; 695 spin_unlock_irqrestore(&info->port.lock, flags); 696 tty_port_set_active(&info->port, false); 697 mutex_unlock(&info->port.mutex); 698 699 wake_up_interruptible(&info->port.open_wait); 700 } 701 702 static void set_termios(struct tty_struct *tty, 703 const struct ktermios *old_termios) 704 { 705 struct slgt_info *info = tty->driver_data; 706 unsigned long flags; 707 708 DBGINFO(("%s set_termios\n", tty->driver->name)); 709 710 change_params(info); 711 712 /* Handle transition to B0 status */ 713 if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) { 714 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR); 715 spin_lock_irqsave(&info->lock,flags); 716 set_gtsignals(info); 717 spin_unlock_irqrestore(&info->lock,flags); 718 } 719 720 /* Handle transition away from B0 status */ 721 if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) { 722 info->signals |= SerialSignal_DTR; 723 if (!C_CRTSCTS(tty) || !tty_throttled(tty)) 724 info->signals |= SerialSignal_RTS; 725 spin_lock_irqsave(&info->lock,flags); 726 set_gtsignals(info); 727 spin_unlock_irqrestore(&info->lock,flags); 728 } 729 730 /* Handle turning off CRTSCTS */ 731 if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty)) { 732 tty->hw_stopped = false; 733 tx_release(tty); 734 } 735 } 736 737 static void update_tx_timer(struct slgt_info *info) 738 { 739 /* 740 * use worst case speed of 1200bps to calculate transmit timeout 741 * based on data in buffers (tbuf_bytes) and FIFO (128 bytes) 742 */ 743 if (info->params.mode == MGSL_MODE_HDLC) { 744 int timeout = (tbuf_bytes(info) * 7) + 1000; 745 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(timeout)); 746 } 747 } 748 749 static int write(struct tty_struct *tty, 750 const unsigned char *buf, int count) 751 { 752 int ret = 0; 753 struct slgt_info *info = tty->driver_data; 754 unsigned long flags; 755 756 if (sanity_check(info, tty->name, "write")) 757 return -EIO; 758 759 DBGINFO(("%s write count=%d\n", info->device_name, count)); 760 761 if (!info->tx_buf || (count > info->max_frame_size)) 762 return -EIO; 763 764 if (!count || tty->flow.stopped || tty->hw_stopped) 765 return 0; 766 767 spin_lock_irqsave(&info->lock, flags); 768 769 if (info->tx_count) { 770 /* send accumulated data from send_char() */ 771 if (!tx_load(info, info->tx_buf, info->tx_count)) 772 goto cleanup; 773 info->tx_count = 0; 774 } 775 776 if (tx_load(info, buf, count)) 777 ret = count; 778 779 cleanup: 780 spin_unlock_irqrestore(&info->lock, flags); 781 DBGINFO(("%s write rc=%d\n", info->device_name, ret)); 782 return ret; 783 } 784 785 static int put_char(struct tty_struct *tty, unsigned char ch) 786 { 787 struct slgt_info *info = tty->driver_data; 788 unsigned long flags; 789 int ret = 0; 790 791 if (sanity_check(info, tty->name, "put_char")) 792 return 0; 793 DBGINFO(("%s put_char(%d)\n", info->device_name, ch)); 794 if (!info->tx_buf) 795 return 0; 796 spin_lock_irqsave(&info->lock,flags); 797 if (info->tx_count < info->max_frame_size) { 798 info->tx_buf[info->tx_count++] = ch; 799 ret = 1; 800 } 801 spin_unlock_irqrestore(&info->lock,flags); 802 return ret; 803 } 804 805 static void send_xchar(struct tty_struct *tty, char ch) 806 { 807 struct slgt_info *info = tty->driver_data; 808 unsigned long flags; 809 810 if (sanity_check(info, tty->name, "send_xchar")) 811 return; 812 DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch)); 813 info->x_char = ch; 814 if (ch) { 815 spin_lock_irqsave(&info->lock,flags); 816 if (!info->tx_enabled) 817 tx_start(info); 818 spin_unlock_irqrestore(&info->lock,flags); 819 } 820 } 821 822 static void wait_until_sent(struct tty_struct *tty, int timeout) 823 { 824 struct slgt_info *info = tty->driver_data; 825 unsigned long orig_jiffies, char_time; 826 827 if (!info ) 828 return; 829 if (sanity_check(info, tty->name, "wait_until_sent")) 830 return; 831 DBGINFO(("%s wait_until_sent entry\n", info->device_name)); 832 if (!tty_port_initialized(&info->port)) 833 goto exit; 834 835 orig_jiffies = jiffies; 836 837 /* Set check interval to 1/5 of estimated time to 838 * send a character, and make it at least 1. The check 839 * interval should also be less than the timeout. 840 * Note: use tight timings here to satisfy the NIST-PCTS. 841 */ 842 843 if (info->params.data_rate) { 844 char_time = info->timeout/(32 * 5); 845 if (!char_time) 846 char_time++; 847 } else 848 char_time = 1; 849 850 if (timeout) 851 char_time = min_t(unsigned long, char_time, timeout); 852 853 while (info->tx_active) { 854 msleep_interruptible(jiffies_to_msecs(char_time)); 855 if (signal_pending(current)) 856 break; 857 if (timeout && time_after(jiffies, orig_jiffies + timeout)) 858 break; 859 } 860 exit: 861 DBGINFO(("%s wait_until_sent exit\n", info->device_name)); 862 } 863 864 static unsigned int write_room(struct tty_struct *tty) 865 { 866 struct slgt_info *info = tty->driver_data; 867 unsigned int ret; 868 869 if (sanity_check(info, tty->name, "write_room")) 870 return 0; 871 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE; 872 DBGINFO(("%s write_room=%u\n", info->device_name, ret)); 873 return ret; 874 } 875 876 static void flush_chars(struct tty_struct *tty) 877 { 878 struct slgt_info *info = tty->driver_data; 879 unsigned long flags; 880 881 if (sanity_check(info, tty->name, "flush_chars")) 882 return; 883 DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count)); 884 885 if (info->tx_count <= 0 || tty->flow.stopped || 886 tty->hw_stopped || !info->tx_buf) 887 return; 888 889 DBGINFO(("%s flush_chars start transmit\n", info->device_name)); 890 891 spin_lock_irqsave(&info->lock,flags); 892 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count)) 893 info->tx_count = 0; 894 spin_unlock_irqrestore(&info->lock,flags); 895 } 896 897 static void flush_buffer(struct tty_struct *tty) 898 { 899 struct slgt_info *info = tty->driver_data; 900 unsigned long flags; 901 902 if (sanity_check(info, tty->name, "flush_buffer")) 903 return; 904 DBGINFO(("%s flush_buffer\n", info->device_name)); 905 906 spin_lock_irqsave(&info->lock, flags); 907 info->tx_count = 0; 908 spin_unlock_irqrestore(&info->lock, flags); 909 910 tty_wakeup(tty); 911 } 912 913 /* 914 * throttle (stop) transmitter 915 */ 916 static void tx_hold(struct tty_struct *tty) 917 { 918 struct slgt_info *info = tty->driver_data; 919 unsigned long flags; 920 921 if (sanity_check(info, tty->name, "tx_hold")) 922 return; 923 DBGINFO(("%s tx_hold\n", info->device_name)); 924 spin_lock_irqsave(&info->lock,flags); 925 if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC) 926 tx_stop(info); 927 spin_unlock_irqrestore(&info->lock,flags); 928 } 929 930 /* 931 * release (start) transmitter 932 */ 933 static void tx_release(struct tty_struct *tty) 934 { 935 struct slgt_info *info = tty->driver_data; 936 unsigned long flags; 937 938 if (sanity_check(info, tty->name, "tx_release")) 939 return; 940 DBGINFO(("%s tx_release\n", info->device_name)); 941 spin_lock_irqsave(&info->lock, flags); 942 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count)) 943 info->tx_count = 0; 944 spin_unlock_irqrestore(&info->lock, flags); 945 } 946 947 /* 948 * Service an IOCTL request 949 * 950 * Arguments 951 * 952 * tty pointer to tty instance data 953 * cmd IOCTL command code 954 * arg command argument/context 955 * 956 * Return 0 if success, otherwise error code 957 */ 958 static int ioctl(struct tty_struct *tty, 959 unsigned int cmd, unsigned long arg) 960 { 961 struct slgt_info *info = tty->driver_data; 962 void __user *argp = (void __user *)arg; 963 int ret; 964 965 if (sanity_check(info, tty->name, "ioctl")) 966 return -ENODEV; 967 DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd)); 968 969 if (cmd != TIOCMIWAIT) { 970 if (tty_io_error(tty)) 971 return -EIO; 972 } 973 974 switch (cmd) { 975 case MGSL_IOCWAITEVENT: 976 return wait_mgsl_event(info, argp); 977 case TIOCMIWAIT: 978 return modem_input_wait(info,(int)arg); 979 case MGSL_IOCSGPIO: 980 return set_gpio(info, argp); 981 case MGSL_IOCGGPIO: 982 return get_gpio(info, argp); 983 case MGSL_IOCWAITGPIO: 984 return wait_gpio(info, argp); 985 case MGSL_IOCGXSYNC: 986 return get_xsync(info, argp); 987 case MGSL_IOCSXSYNC: 988 return set_xsync(info, (int)arg); 989 case MGSL_IOCGXCTRL: 990 return get_xctrl(info, argp); 991 case MGSL_IOCSXCTRL: 992 return set_xctrl(info, (int)arg); 993 } 994 mutex_lock(&info->port.mutex); 995 switch (cmd) { 996 case MGSL_IOCGPARAMS: 997 ret = get_params(info, argp); 998 break; 999 case MGSL_IOCSPARAMS: 1000 ret = set_params(info, argp); 1001 break; 1002 case MGSL_IOCGTXIDLE: 1003 ret = get_txidle(info, argp); 1004 break; 1005 case MGSL_IOCSTXIDLE: 1006 ret = set_txidle(info, (int)arg); 1007 break; 1008 case MGSL_IOCTXENABLE: 1009 ret = tx_enable(info, (int)arg); 1010 break; 1011 case MGSL_IOCRXENABLE: 1012 ret = rx_enable(info, (int)arg); 1013 break; 1014 case MGSL_IOCTXABORT: 1015 ret = tx_abort(info); 1016 break; 1017 case MGSL_IOCGSTATS: 1018 ret = get_stats(info, argp); 1019 break; 1020 case MGSL_IOCGIF: 1021 ret = get_interface(info, argp); 1022 break; 1023 case MGSL_IOCSIF: 1024 ret = set_interface(info,(int)arg); 1025 break; 1026 default: 1027 ret = -ENOIOCTLCMD; 1028 } 1029 mutex_unlock(&info->port.mutex); 1030 return ret; 1031 } 1032 1033 static int get_icount(struct tty_struct *tty, 1034 struct serial_icounter_struct *icount) 1035 1036 { 1037 struct slgt_info *info = tty->driver_data; 1038 struct mgsl_icount cnow; /* kernel counter temps */ 1039 unsigned long flags; 1040 1041 spin_lock_irqsave(&info->lock,flags); 1042 cnow = info->icount; 1043 spin_unlock_irqrestore(&info->lock,flags); 1044 1045 icount->cts = cnow.cts; 1046 icount->dsr = cnow.dsr; 1047 icount->rng = cnow.rng; 1048 icount->dcd = cnow.dcd; 1049 icount->rx = cnow.rx; 1050 icount->tx = cnow.tx; 1051 icount->frame = cnow.frame; 1052 icount->overrun = cnow.overrun; 1053 icount->parity = cnow.parity; 1054 icount->brk = cnow.brk; 1055 icount->buf_overrun = cnow.buf_overrun; 1056 1057 return 0; 1058 } 1059 1060 /* 1061 * support for 32 bit ioctl calls on 64 bit systems 1062 */ 1063 #ifdef CONFIG_COMPAT 1064 static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params) 1065 { 1066 struct MGSL_PARAMS32 tmp_params; 1067 1068 DBGINFO(("%s get_params32\n", info->device_name)); 1069 memset(&tmp_params, 0, sizeof(tmp_params)); 1070 tmp_params.mode = (compat_ulong_t)info->params.mode; 1071 tmp_params.loopback = info->params.loopback; 1072 tmp_params.flags = info->params.flags; 1073 tmp_params.encoding = info->params.encoding; 1074 tmp_params.clock_speed = (compat_ulong_t)info->params.clock_speed; 1075 tmp_params.addr_filter = info->params.addr_filter; 1076 tmp_params.crc_type = info->params.crc_type; 1077 tmp_params.preamble_length = info->params.preamble_length; 1078 tmp_params.preamble = info->params.preamble; 1079 tmp_params.data_rate = (compat_ulong_t)info->params.data_rate; 1080 tmp_params.data_bits = info->params.data_bits; 1081 tmp_params.stop_bits = info->params.stop_bits; 1082 tmp_params.parity = info->params.parity; 1083 if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32))) 1084 return -EFAULT; 1085 return 0; 1086 } 1087 1088 static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params) 1089 { 1090 struct MGSL_PARAMS32 tmp_params; 1091 1092 DBGINFO(("%s set_params32\n", info->device_name)); 1093 if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32))) 1094 return -EFAULT; 1095 1096 spin_lock(&info->lock); 1097 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) { 1098 info->base_clock = tmp_params.clock_speed; 1099 } else { 1100 info->params.mode = tmp_params.mode; 1101 info->params.loopback = tmp_params.loopback; 1102 info->params.flags = tmp_params.flags; 1103 info->params.encoding = tmp_params.encoding; 1104 info->params.clock_speed = tmp_params.clock_speed; 1105 info->params.addr_filter = tmp_params.addr_filter; 1106 info->params.crc_type = tmp_params.crc_type; 1107 info->params.preamble_length = tmp_params.preamble_length; 1108 info->params.preamble = tmp_params.preamble; 1109 info->params.data_rate = tmp_params.data_rate; 1110 info->params.data_bits = tmp_params.data_bits; 1111 info->params.stop_bits = tmp_params.stop_bits; 1112 info->params.parity = tmp_params.parity; 1113 } 1114 spin_unlock(&info->lock); 1115 1116 program_hw(info); 1117 1118 return 0; 1119 } 1120 1121 static long slgt_compat_ioctl(struct tty_struct *tty, 1122 unsigned int cmd, unsigned long arg) 1123 { 1124 struct slgt_info *info = tty->driver_data; 1125 int rc; 1126 1127 if (sanity_check(info, tty->name, "compat_ioctl")) 1128 return -ENODEV; 1129 DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd)); 1130 1131 switch (cmd) { 1132 case MGSL_IOCSPARAMS32: 1133 rc = set_params32(info, compat_ptr(arg)); 1134 break; 1135 1136 case MGSL_IOCGPARAMS32: 1137 rc = get_params32(info, compat_ptr(arg)); 1138 break; 1139 1140 case MGSL_IOCGPARAMS: 1141 case MGSL_IOCSPARAMS: 1142 case MGSL_IOCGTXIDLE: 1143 case MGSL_IOCGSTATS: 1144 case MGSL_IOCWAITEVENT: 1145 case MGSL_IOCGIF: 1146 case MGSL_IOCSGPIO: 1147 case MGSL_IOCGGPIO: 1148 case MGSL_IOCWAITGPIO: 1149 case MGSL_IOCGXSYNC: 1150 case MGSL_IOCGXCTRL: 1151 rc = ioctl(tty, cmd, (unsigned long)compat_ptr(arg)); 1152 break; 1153 default: 1154 rc = ioctl(tty, cmd, arg); 1155 } 1156 DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc)); 1157 return rc; 1158 } 1159 #else 1160 #define slgt_compat_ioctl NULL 1161 #endif /* ifdef CONFIG_COMPAT */ 1162 1163 /* 1164 * proc fs support 1165 */ 1166 static inline void line_info(struct seq_file *m, struct slgt_info *info) 1167 { 1168 char stat_buf[30]; 1169 unsigned long flags; 1170 1171 seq_printf(m, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n", 1172 info->device_name, info->phys_reg_addr, 1173 info->irq_level, info->max_frame_size); 1174 1175 /* output current serial signal states */ 1176 spin_lock_irqsave(&info->lock,flags); 1177 get_gtsignals(info); 1178 spin_unlock_irqrestore(&info->lock,flags); 1179 1180 stat_buf[0] = 0; 1181 stat_buf[1] = 0; 1182 if (info->signals & SerialSignal_RTS) 1183 strcat(stat_buf, "|RTS"); 1184 if (info->signals & SerialSignal_CTS) 1185 strcat(stat_buf, "|CTS"); 1186 if (info->signals & SerialSignal_DTR) 1187 strcat(stat_buf, "|DTR"); 1188 if (info->signals & SerialSignal_DSR) 1189 strcat(stat_buf, "|DSR"); 1190 if (info->signals & SerialSignal_DCD) 1191 strcat(stat_buf, "|CD"); 1192 if (info->signals & SerialSignal_RI) 1193 strcat(stat_buf, "|RI"); 1194 1195 if (info->params.mode != MGSL_MODE_ASYNC) { 1196 seq_printf(m, "\tHDLC txok:%d rxok:%d", 1197 info->icount.txok, info->icount.rxok); 1198 if (info->icount.txunder) 1199 seq_printf(m, " txunder:%d", info->icount.txunder); 1200 if (info->icount.txabort) 1201 seq_printf(m, " txabort:%d", info->icount.txabort); 1202 if (info->icount.rxshort) 1203 seq_printf(m, " rxshort:%d", info->icount.rxshort); 1204 if (info->icount.rxlong) 1205 seq_printf(m, " rxlong:%d", info->icount.rxlong); 1206 if (info->icount.rxover) 1207 seq_printf(m, " rxover:%d", info->icount.rxover); 1208 if (info->icount.rxcrc) 1209 seq_printf(m, " rxcrc:%d", info->icount.rxcrc); 1210 } else { 1211 seq_printf(m, "\tASYNC tx:%d rx:%d", 1212 info->icount.tx, info->icount.rx); 1213 if (info->icount.frame) 1214 seq_printf(m, " fe:%d", info->icount.frame); 1215 if (info->icount.parity) 1216 seq_printf(m, " pe:%d", info->icount.parity); 1217 if (info->icount.brk) 1218 seq_printf(m, " brk:%d", info->icount.brk); 1219 if (info->icount.overrun) 1220 seq_printf(m, " oe:%d", info->icount.overrun); 1221 } 1222 1223 /* Append serial signal status to end */ 1224 seq_printf(m, " %s\n", stat_buf+1); 1225 1226 seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n", 1227 info->tx_active,info->bh_requested,info->bh_running, 1228 info->pending_bh); 1229 } 1230 1231 /* Called to print information about devices 1232 */ 1233 static int synclink_gt_proc_show(struct seq_file *m, void *v) 1234 { 1235 struct slgt_info *info; 1236 1237 seq_puts(m, "synclink_gt driver\n"); 1238 1239 info = slgt_device_list; 1240 while( info ) { 1241 line_info(m, info); 1242 info = info->next_device; 1243 } 1244 return 0; 1245 } 1246 1247 /* 1248 * return count of bytes in transmit buffer 1249 */ 1250 static unsigned int chars_in_buffer(struct tty_struct *tty) 1251 { 1252 struct slgt_info *info = tty->driver_data; 1253 unsigned int count; 1254 if (sanity_check(info, tty->name, "chars_in_buffer")) 1255 return 0; 1256 count = tbuf_bytes(info); 1257 DBGINFO(("%s chars_in_buffer()=%u\n", info->device_name, count)); 1258 return count; 1259 } 1260 1261 /* 1262 * signal remote device to throttle send data (our receive data) 1263 */ 1264 static void throttle(struct tty_struct * tty) 1265 { 1266 struct slgt_info *info = tty->driver_data; 1267 unsigned long flags; 1268 1269 if (sanity_check(info, tty->name, "throttle")) 1270 return; 1271 DBGINFO(("%s throttle\n", info->device_name)); 1272 if (I_IXOFF(tty)) 1273 send_xchar(tty, STOP_CHAR(tty)); 1274 if (C_CRTSCTS(tty)) { 1275 spin_lock_irqsave(&info->lock,flags); 1276 info->signals &= ~SerialSignal_RTS; 1277 set_gtsignals(info); 1278 spin_unlock_irqrestore(&info->lock,flags); 1279 } 1280 } 1281 1282 /* 1283 * signal remote device to stop throttling send data (our receive data) 1284 */ 1285 static void unthrottle(struct tty_struct * tty) 1286 { 1287 struct slgt_info *info = tty->driver_data; 1288 unsigned long flags; 1289 1290 if (sanity_check(info, tty->name, "unthrottle")) 1291 return; 1292 DBGINFO(("%s unthrottle\n", info->device_name)); 1293 if (I_IXOFF(tty)) { 1294 if (info->x_char) 1295 info->x_char = 0; 1296 else 1297 send_xchar(tty, START_CHAR(tty)); 1298 } 1299 if (C_CRTSCTS(tty)) { 1300 spin_lock_irqsave(&info->lock,flags); 1301 info->signals |= SerialSignal_RTS; 1302 set_gtsignals(info); 1303 spin_unlock_irqrestore(&info->lock,flags); 1304 } 1305 } 1306 1307 /* 1308 * set or clear transmit break condition 1309 * break_state -1=set break condition, 0=clear 1310 */ 1311 static int set_break(struct tty_struct *tty, int break_state) 1312 { 1313 struct slgt_info *info = tty->driver_data; 1314 unsigned short value; 1315 unsigned long flags; 1316 1317 if (sanity_check(info, tty->name, "set_break")) 1318 return -EINVAL; 1319 DBGINFO(("%s set_break(%d)\n", info->device_name, break_state)); 1320 1321 spin_lock_irqsave(&info->lock,flags); 1322 value = rd_reg16(info, TCR); 1323 if (break_state == -1) 1324 value |= BIT6; 1325 else 1326 value &= ~BIT6; 1327 wr_reg16(info, TCR, value); 1328 spin_unlock_irqrestore(&info->lock,flags); 1329 return 0; 1330 } 1331 1332 #if SYNCLINK_GENERIC_HDLC 1333 1334 /** 1335 * hdlcdev_attach - called by generic HDLC layer when protocol selected (PPP, frame relay, etc.) 1336 * @dev: pointer to network device structure 1337 * @encoding: serial encoding setting 1338 * @parity: FCS setting 1339 * 1340 * Set encoding and frame check sequence (FCS) options. 1341 * 1342 * Return: 0 if success, otherwise error code 1343 */ 1344 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding, 1345 unsigned short parity) 1346 { 1347 struct slgt_info *info = dev_to_port(dev); 1348 unsigned char new_encoding; 1349 unsigned short new_crctype; 1350 1351 /* return error if TTY interface open */ 1352 if (info->port.count) 1353 return -EBUSY; 1354 1355 DBGINFO(("%s hdlcdev_attach\n", info->device_name)); 1356 1357 switch (encoding) 1358 { 1359 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break; 1360 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break; 1361 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break; 1362 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break; 1363 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break; 1364 default: return -EINVAL; 1365 } 1366 1367 switch (parity) 1368 { 1369 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break; 1370 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break; 1371 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break; 1372 default: return -EINVAL; 1373 } 1374 1375 info->params.encoding = new_encoding; 1376 info->params.crc_type = new_crctype; 1377 1378 /* if network interface up, reprogram hardware */ 1379 if (info->netcount) 1380 program_hw(info); 1381 1382 return 0; 1383 } 1384 1385 /** 1386 * hdlcdev_xmit - called by generic HDLC layer to send a frame 1387 * @skb: socket buffer containing HDLC frame 1388 * @dev: pointer to network device structure 1389 */ 1390 static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb, 1391 struct net_device *dev) 1392 { 1393 struct slgt_info *info = dev_to_port(dev); 1394 unsigned long flags; 1395 1396 DBGINFO(("%s hdlc_xmit\n", dev->name)); 1397 1398 if (!skb->len) 1399 return NETDEV_TX_OK; 1400 1401 /* stop sending until this frame completes */ 1402 netif_stop_queue(dev); 1403 1404 /* update network statistics */ 1405 dev->stats.tx_packets++; 1406 dev->stats.tx_bytes += skb->len; 1407 1408 /* save start time for transmit timeout detection */ 1409 netif_trans_update(dev); 1410 1411 spin_lock_irqsave(&info->lock, flags); 1412 tx_load(info, skb->data, skb->len); 1413 spin_unlock_irqrestore(&info->lock, flags); 1414 1415 /* done with socket buffer, so free it */ 1416 dev_kfree_skb(skb); 1417 1418 return NETDEV_TX_OK; 1419 } 1420 1421 /** 1422 * hdlcdev_open - called by network layer when interface enabled 1423 * @dev: pointer to network device structure 1424 * 1425 * Claim resources and initialize hardware. 1426 * 1427 * Return: 0 if success, otherwise error code 1428 */ 1429 static int hdlcdev_open(struct net_device *dev) 1430 { 1431 struct slgt_info *info = dev_to_port(dev); 1432 int rc; 1433 unsigned long flags; 1434 1435 DBGINFO(("%s hdlcdev_open\n", dev->name)); 1436 1437 /* arbitrate between network and tty opens */ 1438 spin_lock_irqsave(&info->netlock, flags); 1439 if (info->port.count != 0 || info->netcount != 0) { 1440 DBGINFO(("%s hdlc_open busy\n", dev->name)); 1441 spin_unlock_irqrestore(&info->netlock, flags); 1442 return -EBUSY; 1443 } 1444 info->netcount=1; 1445 spin_unlock_irqrestore(&info->netlock, flags); 1446 1447 /* claim resources and init adapter */ 1448 if ((rc = startup(info)) != 0) { 1449 spin_lock_irqsave(&info->netlock, flags); 1450 info->netcount=0; 1451 spin_unlock_irqrestore(&info->netlock, flags); 1452 return rc; 1453 } 1454 1455 /* generic HDLC layer open processing */ 1456 rc = hdlc_open(dev); 1457 if (rc) { 1458 shutdown(info); 1459 spin_lock_irqsave(&info->netlock, flags); 1460 info->netcount = 0; 1461 spin_unlock_irqrestore(&info->netlock, flags); 1462 return rc; 1463 } 1464 1465 /* assert RTS and DTR, apply hardware settings */ 1466 info->signals |= SerialSignal_RTS | SerialSignal_DTR; 1467 program_hw(info); 1468 1469 /* enable network layer transmit */ 1470 netif_trans_update(dev); 1471 netif_start_queue(dev); 1472 1473 /* inform generic HDLC layer of current DCD status */ 1474 spin_lock_irqsave(&info->lock, flags); 1475 get_gtsignals(info); 1476 spin_unlock_irqrestore(&info->lock, flags); 1477 if (info->signals & SerialSignal_DCD) 1478 netif_carrier_on(dev); 1479 else 1480 netif_carrier_off(dev); 1481 return 0; 1482 } 1483 1484 /** 1485 * hdlcdev_close - called by network layer when interface is disabled 1486 * @dev: pointer to network device structure 1487 * 1488 * Shutdown hardware and release resources. 1489 * 1490 * Return: 0 if success, otherwise error code 1491 */ 1492 static int hdlcdev_close(struct net_device *dev) 1493 { 1494 struct slgt_info *info = dev_to_port(dev); 1495 unsigned long flags; 1496 1497 DBGINFO(("%s hdlcdev_close\n", dev->name)); 1498 1499 netif_stop_queue(dev); 1500 1501 /* shutdown adapter and release resources */ 1502 shutdown(info); 1503 1504 hdlc_close(dev); 1505 1506 spin_lock_irqsave(&info->netlock, flags); 1507 info->netcount=0; 1508 spin_unlock_irqrestore(&info->netlock, flags); 1509 1510 return 0; 1511 } 1512 1513 /** 1514 * hdlcdev_ioctl - called by network layer to process IOCTL call to network device 1515 * @dev: pointer to network device structure 1516 * @ifr: pointer to network interface request structure 1517 * @cmd: IOCTL command code 1518 * 1519 * Return: 0 if success, otherwise error code 1520 */ 1521 static int hdlcdev_ioctl(struct net_device *dev, struct if_settings *ifs) 1522 { 1523 const size_t size = sizeof(sync_serial_settings); 1524 sync_serial_settings new_line; 1525 sync_serial_settings __user *line = ifs->ifs_ifsu.sync; 1526 struct slgt_info *info = dev_to_port(dev); 1527 unsigned int flags; 1528 1529 DBGINFO(("%s hdlcdev_ioctl\n", dev->name)); 1530 1531 /* return error if TTY interface open */ 1532 if (info->port.count) 1533 return -EBUSY; 1534 1535 memset(&new_line, 0, sizeof(new_line)); 1536 1537 switch (ifs->type) { 1538 case IF_GET_IFACE: /* return current sync_serial_settings */ 1539 1540 ifs->type = IF_IFACE_SYNC_SERIAL; 1541 if (ifs->size < size) { 1542 ifs->size = size; /* data size wanted */ 1543 return -ENOBUFS; 1544 } 1545 1546 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL | 1547 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN | 1548 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL | 1549 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); 1550 1551 switch (flags){ 1552 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break; 1553 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break; 1554 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break; 1555 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break; 1556 default: new_line.clock_type = CLOCK_DEFAULT; 1557 } 1558 1559 new_line.clock_rate = info->params.clock_speed; 1560 new_line.loopback = info->params.loopback ? 1:0; 1561 1562 if (copy_to_user(line, &new_line, size)) 1563 return -EFAULT; 1564 return 0; 1565 1566 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */ 1567 1568 if(!capable(CAP_NET_ADMIN)) 1569 return -EPERM; 1570 if (copy_from_user(&new_line, line, size)) 1571 return -EFAULT; 1572 1573 switch (new_line.clock_type) 1574 { 1575 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break; 1576 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break; 1577 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break; 1578 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break; 1579 case CLOCK_DEFAULT: flags = info->params.flags & 1580 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL | 1581 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN | 1582 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL | 1583 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break; 1584 default: return -EINVAL; 1585 } 1586 1587 if (new_line.loopback != 0 && new_line.loopback != 1) 1588 return -EINVAL; 1589 1590 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL | 1591 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN | 1592 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL | 1593 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); 1594 info->params.flags |= flags; 1595 1596 info->params.loopback = new_line.loopback; 1597 1598 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG)) 1599 info->params.clock_speed = new_line.clock_rate; 1600 else 1601 info->params.clock_speed = 0; 1602 1603 /* if network interface up, reprogram hardware */ 1604 if (info->netcount) 1605 program_hw(info); 1606 return 0; 1607 1608 default: 1609 return hdlc_ioctl(dev, ifs); 1610 } 1611 } 1612 1613 /** 1614 * hdlcdev_tx_timeout - called by network layer when transmit timeout is detected 1615 * @dev: pointer to network device structure 1616 * @txqueue: unused 1617 */ 1618 static void hdlcdev_tx_timeout(struct net_device *dev, unsigned int txqueue) 1619 { 1620 struct slgt_info *info = dev_to_port(dev); 1621 unsigned long flags; 1622 1623 DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name)); 1624 1625 dev->stats.tx_errors++; 1626 dev->stats.tx_aborted_errors++; 1627 1628 spin_lock_irqsave(&info->lock,flags); 1629 tx_stop(info); 1630 spin_unlock_irqrestore(&info->lock,flags); 1631 1632 netif_wake_queue(dev); 1633 } 1634 1635 /** 1636 * hdlcdev_tx_done - called by device driver when transmit completes 1637 * @info: pointer to device instance information 1638 * 1639 * Reenable network layer transmit if stopped. 1640 */ 1641 static void hdlcdev_tx_done(struct slgt_info *info) 1642 { 1643 if (netif_queue_stopped(info->netdev)) 1644 netif_wake_queue(info->netdev); 1645 } 1646 1647 /** 1648 * hdlcdev_rx - called by device driver when frame received 1649 * @info: pointer to device instance information 1650 * @buf: pointer to buffer contianing frame data 1651 * @size: count of data bytes in buf 1652 * 1653 * Pass frame to network layer. 1654 */ 1655 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size) 1656 { 1657 struct sk_buff *skb = dev_alloc_skb(size); 1658 struct net_device *dev = info->netdev; 1659 1660 DBGINFO(("%s hdlcdev_rx\n", dev->name)); 1661 1662 if (skb == NULL) { 1663 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name)); 1664 dev->stats.rx_dropped++; 1665 return; 1666 } 1667 1668 skb_put_data(skb, buf, size); 1669 1670 skb->protocol = hdlc_type_trans(skb, dev); 1671 1672 dev->stats.rx_packets++; 1673 dev->stats.rx_bytes += size; 1674 1675 netif_rx(skb); 1676 } 1677 1678 static const struct net_device_ops hdlcdev_ops = { 1679 .ndo_open = hdlcdev_open, 1680 .ndo_stop = hdlcdev_close, 1681 .ndo_start_xmit = hdlc_start_xmit, 1682 .ndo_siocwandev = hdlcdev_ioctl, 1683 .ndo_tx_timeout = hdlcdev_tx_timeout, 1684 }; 1685 1686 /** 1687 * hdlcdev_init - called by device driver when adding device instance 1688 * @info: pointer to device instance information 1689 * 1690 * Do generic HDLC initialization. 1691 * 1692 * Return: 0 if success, otherwise error code 1693 */ 1694 static int hdlcdev_init(struct slgt_info *info) 1695 { 1696 int rc; 1697 struct net_device *dev; 1698 hdlc_device *hdlc; 1699 1700 /* allocate and initialize network and HDLC layer objects */ 1701 1702 dev = alloc_hdlcdev(info); 1703 if (!dev) { 1704 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name); 1705 return -ENOMEM; 1706 } 1707 1708 /* for network layer reporting purposes only */ 1709 dev->mem_start = info->phys_reg_addr; 1710 dev->mem_end = info->phys_reg_addr + SLGT_REG_SIZE - 1; 1711 dev->irq = info->irq_level; 1712 1713 /* network layer callbacks and settings */ 1714 dev->netdev_ops = &hdlcdev_ops; 1715 dev->watchdog_timeo = 10 * HZ; 1716 dev->tx_queue_len = 50; 1717 1718 /* generic HDLC layer callbacks and settings */ 1719 hdlc = dev_to_hdlc(dev); 1720 hdlc->attach = hdlcdev_attach; 1721 hdlc->xmit = hdlcdev_xmit; 1722 1723 /* register objects with HDLC layer */ 1724 rc = register_hdlc_device(dev); 1725 if (rc) { 1726 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__); 1727 free_netdev(dev); 1728 return rc; 1729 } 1730 1731 info->netdev = dev; 1732 return 0; 1733 } 1734 1735 /** 1736 * hdlcdev_exit - called by device driver when removing device instance 1737 * @info: pointer to device instance information 1738 * 1739 * Do generic HDLC cleanup. 1740 */ 1741 static void hdlcdev_exit(struct slgt_info *info) 1742 { 1743 if (!info->netdev) 1744 return; 1745 unregister_hdlc_device(info->netdev); 1746 free_netdev(info->netdev); 1747 info->netdev = NULL; 1748 } 1749 1750 #endif /* ifdef CONFIG_HDLC */ 1751 1752 /* 1753 * get async data from rx DMA buffers 1754 */ 1755 static void rx_async(struct slgt_info *info) 1756 { 1757 struct mgsl_icount *icount = &info->icount; 1758 unsigned int start, end; 1759 unsigned char *p; 1760 unsigned char status; 1761 struct slgt_desc *bufs = info->rbufs; 1762 int i, count; 1763 int chars = 0; 1764 int stat; 1765 unsigned char ch; 1766 1767 start = end = info->rbuf_current; 1768 1769 while(desc_complete(bufs[end])) { 1770 count = desc_count(bufs[end]) - info->rbuf_index; 1771 p = bufs[end].buf + info->rbuf_index; 1772 1773 DBGISR(("%s rx_async count=%d\n", info->device_name, count)); 1774 DBGDATA(info, p, count, "rx"); 1775 1776 for(i=0 ; i < count; i+=2, p+=2) { 1777 ch = *p; 1778 icount->rx++; 1779 1780 stat = 0; 1781 1782 status = *(p + 1) & (BIT1 + BIT0); 1783 if (status) { 1784 if (status & BIT1) 1785 icount->parity++; 1786 else if (status & BIT0) 1787 icount->frame++; 1788 /* discard char if tty control flags say so */ 1789 if (status & info->ignore_status_mask) 1790 continue; 1791 if (status & BIT1) 1792 stat = TTY_PARITY; 1793 else if (status & BIT0) 1794 stat = TTY_FRAME; 1795 } 1796 tty_insert_flip_char(&info->port, ch, stat); 1797 chars++; 1798 } 1799 1800 if (i < count) { 1801 /* receive buffer not completed */ 1802 info->rbuf_index += i; 1803 mod_timer(&info->rx_timer, jiffies + 1); 1804 break; 1805 } 1806 1807 info->rbuf_index = 0; 1808 free_rbufs(info, end, end); 1809 1810 if (++end == info->rbuf_count) 1811 end = 0; 1812 1813 /* if entire list searched then no frame available */ 1814 if (end == start) 1815 break; 1816 } 1817 1818 if (chars) 1819 tty_flip_buffer_push(&info->port); 1820 } 1821 1822 /* 1823 * return next bottom half action to perform 1824 */ 1825 static int bh_action(struct slgt_info *info) 1826 { 1827 unsigned long flags; 1828 int rc; 1829 1830 spin_lock_irqsave(&info->lock,flags); 1831 1832 if (info->pending_bh & BH_RECEIVE) { 1833 info->pending_bh &= ~BH_RECEIVE; 1834 rc = BH_RECEIVE; 1835 } else if (info->pending_bh & BH_TRANSMIT) { 1836 info->pending_bh &= ~BH_TRANSMIT; 1837 rc = BH_TRANSMIT; 1838 } else if (info->pending_bh & BH_STATUS) { 1839 info->pending_bh &= ~BH_STATUS; 1840 rc = BH_STATUS; 1841 } else { 1842 /* Mark BH routine as complete */ 1843 info->bh_running = false; 1844 info->bh_requested = false; 1845 rc = 0; 1846 } 1847 1848 spin_unlock_irqrestore(&info->lock,flags); 1849 1850 return rc; 1851 } 1852 1853 /* 1854 * perform bottom half processing 1855 */ 1856 static void bh_handler(struct work_struct *work) 1857 { 1858 struct slgt_info *info = container_of(work, struct slgt_info, task); 1859 int action; 1860 1861 info->bh_running = true; 1862 1863 while((action = bh_action(info))) { 1864 switch (action) { 1865 case BH_RECEIVE: 1866 DBGBH(("%s bh receive\n", info->device_name)); 1867 switch(info->params.mode) { 1868 case MGSL_MODE_ASYNC: 1869 rx_async(info); 1870 break; 1871 case MGSL_MODE_HDLC: 1872 while(rx_get_frame(info)); 1873 break; 1874 case MGSL_MODE_RAW: 1875 case MGSL_MODE_MONOSYNC: 1876 case MGSL_MODE_BISYNC: 1877 case MGSL_MODE_XSYNC: 1878 while(rx_get_buf(info)); 1879 break; 1880 } 1881 /* restart receiver if rx DMA buffers exhausted */ 1882 if (info->rx_restart) 1883 rx_start(info); 1884 break; 1885 case BH_TRANSMIT: 1886 bh_transmit(info); 1887 break; 1888 case BH_STATUS: 1889 DBGBH(("%s bh status\n", info->device_name)); 1890 info->ri_chkcount = 0; 1891 info->dsr_chkcount = 0; 1892 info->dcd_chkcount = 0; 1893 info->cts_chkcount = 0; 1894 break; 1895 default: 1896 DBGBH(("%s unknown action\n", info->device_name)); 1897 break; 1898 } 1899 } 1900 DBGBH(("%s bh_handler exit\n", info->device_name)); 1901 } 1902 1903 static void bh_transmit(struct slgt_info *info) 1904 { 1905 struct tty_struct *tty = info->port.tty; 1906 1907 DBGBH(("%s bh_transmit\n", info->device_name)); 1908 if (tty) 1909 tty_wakeup(tty); 1910 } 1911 1912 static void dsr_change(struct slgt_info *info, unsigned short status) 1913 { 1914 if (status & BIT3) { 1915 info->signals |= SerialSignal_DSR; 1916 info->input_signal_events.dsr_up++; 1917 } else { 1918 info->signals &= ~SerialSignal_DSR; 1919 info->input_signal_events.dsr_down++; 1920 } 1921 DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals)); 1922 if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) { 1923 slgt_irq_off(info, IRQ_DSR); 1924 return; 1925 } 1926 info->icount.dsr++; 1927 wake_up_interruptible(&info->status_event_wait_q); 1928 wake_up_interruptible(&info->event_wait_q); 1929 info->pending_bh |= BH_STATUS; 1930 } 1931 1932 static void cts_change(struct slgt_info *info, unsigned short status) 1933 { 1934 if (status & BIT2) { 1935 info->signals |= SerialSignal_CTS; 1936 info->input_signal_events.cts_up++; 1937 } else { 1938 info->signals &= ~SerialSignal_CTS; 1939 info->input_signal_events.cts_down++; 1940 } 1941 DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals)); 1942 if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) { 1943 slgt_irq_off(info, IRQ_CTS); 1944 return; 1945 } 1946 info->icount.cts++; 1947 wake_up_interruptible(&info->status_event_wait_q); 1948 wake_up_interruptible(&info->event_wait_q); 1949 info->pending_bh |= BH_STATUS; 1950 1951 if (tty_port_cts_enabled(&info->port)) { 1952 if (info->port.tty) { 1953 if (info->port.tty->hw_stopped) { 1954 if (info->signals & SerialSignal_CTS) { 1955 info->port.tty->hw_stopped = false; 1956 info->pending_bh |= BH_TRANSMIT; 1957 return; 1958 } 1959 } else { 1960 if (!(info->signals & SerialSignal_CTS)) 1961 info->port.tty->hw_stopped = true; 1962 } 1963 } 1964 } 1965 } 1966 1967 static void dcd_change(struct slgt_info *info, unsigned short status) 1968 { 1969 if (status & BIT1) { 1970 info->signals |= SerialSignal_DCD; 1971 info->input_signal_events.dcd_up++; 1972 } else { 1973 info->signals &= ~SerialSignal_DCD; 1974 info->input_signal_events.dcd_down++; 1975 } 1976 DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals)); 1977 if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) { 1978 slgt_irq_off(info, IRQ_DCD); 1979 return; 1980 } 1981 info->icount.dcd++; 1982 #if SYNCLINK_GENERIC_HDLC 1983 if (info->netcount) { 1984 if (info->signals & SerialSignal_DCD) 1985 netif_carrier_on(info->netdev); 1986 else 1987 netif_carrier_off(info->netdev); 1988 } 1989 #endif 1990 wake_up_interruptible(&info->status_event_wait_q); 1991 wake_up_interruptible(&info->event_wait_q); 1992 info->pending_bh |= BH_STATUS; 1993 1994 if (tty_port_check_carrier(&info->port)) { 1995 if (info->signals & SerialSignal_DCD) 1996 wake_up_interruptible(&info->port.open_wait); 1997 else { 1998 if (info->port.tty) 1999 tty_hangup(info->port.tty); 2000 } 2001 } 2002 } 2003 2004 static void ri_change(struct slgt_info *info, unsigned short status) 2005 { 2006 if (status & BIT0) { 2007 info->signals |= SerialSignal_RI; 2008 info->input_signal_events.ri_up++; 2009 } else { 2010 info->signals &= ~SerialSignal_RI; 2011 info->input_signal_events.ri_down++; 2012 } 2013 DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals)); 2014 if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) { 2015 slgt_irq_off(info, IRQ_RI); 2016 return; 2017 } 2018 info->icount.rng++; 2019 wake_up_interruptible(&info->status_event_wait_q); 2020 wake_up_interruptible(&info->event_wait_q); 2021 info->pending_bh |= BH_STATUS; 2022 } 2023 2024 static void isr_rxdata(struct slgt_info *info) 2025 { 2026 unsigned int count = info->rbuf_fill_count; 2027 unsigned int i = info->rbuf_fill_index; 2028 unsigned short reg; 2029 2030 while (rd_reg16(info, SSR) & IRQ_RXDATA) { 2031 reg = rd_reg16(info, RDR); 2032 DBGISR(("isr_rxdata %s RDR=%04X\n", info->device_name, reg)); 2033 if (desc_complete(info->rbufs[i])) { 2034 /* all buffers full */ 2035 rx_stop(info); 2036 info->rx_restart = true; 2037 continue; 2038 } 2039 info->rbufs[i].buf[count++] = (unsigned char)reg; 2040 /* async mode saves status byte to buffer for each data byte */ 2041 if (info->params.mode == MGSL_MODE_ASYNC) 2042 info->rbufs[i].buf[count++] = (unsigned char)(reg >> 8); 2043 if (count == info->rbuf_fill_level || (reg & BIT10)) { 2044 /* buffer full or end of frame */ 2045 set_desc_count(info->rbufs[i], count); 2046 set_desc_status(info->rbufs[i], BIT15 | (reg >> 8)); 2047 info->rbuf_fill_count = count = 0; 2048 if (++i == info->rbuf_count) 2049 i = 0; 2050 info->pending_bh |= BH_RECEIVE; 2051 } 2052 } 2053 2054 info->rbuf_fill_index = i; 2055 info->rbuf_fill_count = count; 2056 } 2057 2058 static void isr_serial(struct slgt_info *info) 2059 { 2060 unsigned short status = rd_reg16(info, SSR); 2061 2062 DBGISR(("%s isr_serial status=%04X\n", info->device_name, status)); 2063 2064 wr_reg16(info, SSR, status); /* clear pending */ 2065 2066 info->irq_occurred = true; 2067 2068 if (info->params.mode == MGSL_MODE_ASYNC) { 2069 if (status & IRQ_TXIDLE) { 2070 if (info->tx_active) 2071 isr_txeom(info, status); 2072 } 2073 if (info->rx_pio && (status & IRQ_RXDATA)) 2074 isr_rxdata(info); 2075 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) { 2076 info->icount.brk++; 2077 /* process break detection if tty control allows */ 2078 if (info->port.tty) { 2079 if (!(status & info->ignore_status_mask)) { 2080 if (info->read_status_mask & MASK_BREAK) { 2081 tty_insert_flip_char(&info->port, 0, TTY_BREAK); 2082 if (info->port.flags & ASYNC_SAK) 2083 do_SAK(info->port.tty); 2084 } 2085 } 2086 } 2087 } 2088 } else { 2089 if (status & (IRQ_TXIDLE + IRQ_TXUNDER)) 2090 isr_txeom(info, status); 2091 if (info->rx_pio && (status & IRQ_RXDATA)) 2092 isr_rxdata(info); 2093 if (status & IRQ_RXIDLE) { 2094 if (status & RXIDLE) 2095 info->icount.rxidle++; 2096 else 2097 info->icount.exithunt++; 2098 wake_up_interruptible(&info->event_wait_q); 2099 } 2100 2101 if (status & IRQ_RXOVER) 2102 rx_start(info); 2103 } 2104 2105 if (status & IRQ_DSR) 2106 dsr_change(info, status); 2107 if (status & IRQ_CTS) 2108 cts_change(info, status); 2109 if (status & IRQ_DCD) 2110 dcd_change(info, status); 2111 if (status & IRQ_RI) 2112 ri_change(info, status); 2113 } 2114 2115 static void isr_rdma(struct slgt_info *info) 2116 { 2117 unsigned int status = rd_reg32(info, RDCSR); 2118 2119 DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status)); 2120 2121 /* RDCSR (rx DMA control/status) 2122 * 2123 * 31..07 reserved 2124 * 06 save status byte to DMA buffer 2125 * 05 error 2126 * 04 eol (end of list) 2127 * 03 eob (end of buffer) 2128 * 02 IRQ enable 2129 * 01 reset 2130 * 00 enable 2131 */ 2132 wr_reg32(info, RDCSR, status); /* clear pending */ 2133 2134 if (status & (BIT5 + BIT4)) { 2135 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name)); 2136 info->rx_restart = true; 2137 } 2138 info->pending_bh |= BH_RECEIVE; 2139 } 2140 2141 static void isr_tdma(struct slgt_info *info) 2142 { 2143 unsigned int status = rd_reg32(info, TDCSR); 2144 2145 DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status)); 2146 2147 /* TDCSR (tx DMA control/status) 2148 * 2149 * 31..06 reserved 2150 * 05 error 2151 * 04 eol (end of list) 2152 * 03 eob (end of buffer) 2153 * 02 IRQ enable 2154 * 01 reset 2155 * 00 enable 2156 */ 2157 wr_reg32(info, TDCSR, status); /* clear pending */ 2158 2159 if (status & (BIT5 + BIT4 + BIT3)) { 2160 // another transmit buffer has completed 2161 // run bottom half to get more send data from user 2162 info->pending_bh |= BH_TRANSMIT; 2163 } 2164 } 2165 2166 /* 2167 * return true if there are unsent tx DMA buffers, otherwise false 2168 * 2169 * if there are unsent buffers then info->tbuf_start 2170 * is set to index of first unsent buffer 2171 */ 2172 static bool unsent_tbufs(struct slgt_info *info) 2173 { 2174 unsigned int i = info->tbuf_current; 2175 bool rc = false; 2176 2177 /* 2178 * search backwards from last loaded buffer (precedes tbuf_current) 2179 * for first unsent buffer (desc_count > 0) 2180 */ 2181 2182 do { 2183 if (i) 2184 i--; 2185 else 2186 i = info->tbuf_count - 1; 2187 if (!desc_count(info->tbufs[i])) 2188 break; 2189 info->tbuf_start = i; 2190 rc = true; 2191 } while (i != info->tbuf_current); 2192 2193 return rc; 2194 } 2195 2196 static void isr_txeom(struct slgt_info *info, unsigned short status) 2197 { 2198 DBGISR(("%s txeom status=%04x\n", info->device_name, status)); 2199 2200 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER); 2201 tdma_reset(info); 2202 if (status & IRQ_TXUNDER) { 2203 unsigned short val = rd_reg16(info, TCR); 2204 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */ 2205 wr_reg16(info, TCR, val); /* clear reset bit */ 2206 } 2207 2208 if (info->tx_active) { 2209 if (info->params.mode != MGSL_MODE_ASYNC) { 2210 if (status & IRQ_TXUNDER) 2211 info->icount.txunder++; 2212 else if (status & IRQ_TXIDLE) 2213 info->icount.txok++; 2214 } 2215 2216 if (unsent_tbufs(info)) { 2217 tx_start(info); 2218 update_tx_timer(info); 2219 return; 2220 } 2221 info->tx_active = false; 2222 2223 del_timer(&info->tx_timer); 2224 2225 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) { 2226 info->signals &= ~SerialSignal_RTS; 2227 info->drop_rts_on_tx_done = false; 2228 set_gtsignals(info); 2229 } 2230 2231 #if SYNCLINK_GENERIC_HDLC 2232 if (info->netcount) 2233 hdlcdev_tx_done(info); 2234 else 2235 #endif 2236 { 2237 if (info->port.tty && (info->port.tty->flow.stopped || info->port.tty->hw_stopped)) { 2238 tx_stop(info); 2239 return; 2240 } 2241 info->pending_bh |= BH_TRANSMIT; 2242 } 2243 } 2244 } 2245 2246 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state) 2247 { 2248 struct cond_wait *w, *prev; 2249 2250 /* wake processes waiting for specific transitions */ 2251 for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) { 2252 if (w->data & changed) { 2253 w->data = state; 2254 wake_up_interruptible(&w->q); 2255 if (prev != NULL) 2256 prev->next = w->next; 2257 else 2258 info->gpio_wait_q = w->next; 2259 } else 2260 prev = w; 2261 } 2262 } 2263 2264 /* interrupt service routine 2265 * 2266 * irq interrupt number 2267 * dev_id device ID supplied during interrupt registration 2268 */ 2269 static irqreturn_t slgt_interrupt(int dummy, void *dev_id) 2270 { 2271 struct slgt_info *info = dev_id; 2272 unsigned int gsr; 2273 unsigned int i; 2274 2275 DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level)); 2276 2277 while((gsr = rd_reg32(info, GSR) & 0xffffff00)) { 2278 DBGISR(("%s gsr=%08x\n", info->device_name, gsr)); 2279 info->irq_occurred = true; 2280 for(i=0; i < info->port_count ; i++) { 2281 if (info->port_array[i] == NULL) 2282 continue; 2283 spin_lock(&info->port_array[i]->lock); 2284 if (gsr & (BIT8 << i)) 2285 isr_serial(info->port_array[i]); 2286 if (gsr & (BIT16 << (i*2))) 2287 isr_rdma(info->port_array[i]); 2288 if (gsr & (BIT17 << (i*2))) 2289 isr_tdma(info->port_array[i]); 2290 spin_unlock(&info->port_array[i]->lock); 2291 } 2292 } 2293 2294 if (info->gpio_present) { 2295 unsigned int state; 2296 unsigned int changed; 2297 spin_lock(&info->lock); 2298 while ((changed = rd_reg32(info, IOSR)) != 0) { 2299 DBGISR(("%s iosr=%08x\n", info->device_name, changed)); 2300 /* read latched state of GPIO signals */ 2301 state = rd_reg32(info, IOVR); 2302 /* clear pending GPIO interrupt bits */ 2303 wr_reg32(info, IOSR, changed); 2304 for (i=0 ; i < info->port_count ; i++) { 2305 if (info->port_array[i] != NULL) 2306 isr_gpio(info->port_array[i], changed, state); 2307 } 2308 } 2309 spin_unlock(&info->lock); 2310 } 2311 2312 for(i=0; i < info->port_count ; i++) { 2313 struct slgt_info *port = info->port_array[i]; 2314 if (port == NULL) 2315 continue; 2316 spin_lock(&port->lock); 2317 if ((port->port.count || port->netcount) && 2318 port->pending_bh && !port->bh_running && 2319 !port->bh_requested) { 2320 DBGISR(("%s bh queued\n", port->device_name)); 2321 schedule_work(&port->task); 2322 port->bh_requested = true; 2323 } 2324 spin_unlock(&port->lock); 2325 } 2326 2327 DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level)); 2328 return IRQ_HANDLED; 2329 } 2330 2331 static int startup(struct slgt_info *info) 2332 { 2333 DBGINFO(("%s startup\n", info->device_name)); 2334 2335 if (tty_port_initialized(&info->port)) 2336 return 0; 2337 2338 if (!info->tx_buf) { 2339 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL); 2340 if (!info->tx_buf) { 2341 DBGERR(("%s can't allocate tx buffer\n", info->device_name)); 2342 return -ENOMEM; 2343 } 2344 } 2345 2346 info->pending_bh = 0; 2347 2348 memset(&info->icount, 0, sizeof(info->icount)); 2349 2350 /* program hardware for current parameters */ 2351 change_params(info); 2352 2353 if (info->port.tty) 2354 clear_bit(TTY_IO_ERROR, &info->port.tty->flags); 2355 2356 tty_port_set_initialized(&info->port, true); 2357 2358 return 0; 2359 } 2360 2361 /* 2362 * called by close() and hangup() to shutdown hardware 2363 */ 2364 static void shutdown(struct slgt_info *info) 2365 { 2366 unsigned long flags; 2367 2368 if (!tty_port_initialized(&info->port)) 2369 return; 2370 2371 DBGINFO(("%s shutdown\n", info->device_name)); 2372 2373 /* clear status wait queue because status changes */ 2374 /* can't happen after shutting down the hardware */ 2375 wake_up_interruptible(&info->status_event_wait_q); 2376 wake_up_interruptible(&info->event_wait_q); 2377 2378 del_timer_sync(&info->tx_timer); 2379 del_timer_sync(&info->rx_timer); 2380 2381 kfree(info->tx_buf); 2382 info->tx_buf = NULL; 2383 2384 spin_lock_irqsave(&info->lock,flags); 2385 2386 tx_stop(info); 2387 rx_stop(info); 2388 2389 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER); 2390 2391 if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) { 2392 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR); 2393 set_gtsignals(info); 2394 } 2395 2396 flush_cond_wait(&info->gpio_wait_q); 2397 2398 spin_unlock_irqrestore(&info->lock,flags); 2399 2400 if (info->port.tty) 2401 set_bit(TTY_IO_ERROR, &info->port.tty->flags); 2402 2403 tty_port_set_initialized(&info->port, false); 2404 } 2405 2406 static void program_hw(struct slgt_info *info) 2407 { 2408 unsigned long flags; 2409 2410 spin_lock_irqsave(&info->lock,flags); 2411 2412 rx_stop(info); 2413 tx_stop(info); 2414 2415 if (info->params.mode != MGSL_MODE_ASYNC || 2416 info->netcount) 2417 sync_mode(info); 2418 else 2419 async_mode(info); 2420 2421 set_gtsignals(info); 2422 2423 info->dcd_chkcount = 0; 2424 info->cts_chkcount = 0; 2425 info->ri_chkcount = 0; 2426 info->dsr_chkcount = 0; 2427 2428 slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI); 2429 get_gtsignals(info); 2430 2431 if (info->netcount || 2432 (info->port.tty && info->port.tty->termios.c_cflag & CREAD)) 2433 rx_start(info); 2434 2435 spin_unlock_irqrestore(&info->lock,flags); 2436 } 2437 2438 /* 2439 * reconfigure adapter based on new parameters 2440 */ 2441 static void change_params(struct slgt_info *info) 2442 { 2443 unsigned cflag; 2444 int bits_per_char; 2445 2446 if (!info->port.tty) 2447 return; 2448 DBGINFO(("%s change_params\n", info->device_name)); 2449 2450 cflag = info->port.tty->termios.c_cflag; 2451 2452 /* if B0 rate (hangup) specified then negate RTS and DTR */ 2453 /* otherwise assert RTS and DTR */ 2454 if (cflag & CBAUD) 2455 info->signals |= SerialSignal_RTS | SerialSignal_DTR; 2456 else 2457 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR); 2458 2459 /* byte size and parity */ 2460 2461 info->params.data_bits = tty_get_char_size(cflag); 2462 info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1; 2463 2464 if (cflag & PARENB) 2465 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN; 2466 else 2467 info->params.parity = ASYNC_PARITY_NONE; 2468 2469 /* calculate number of jiffies to transmit a full 2470 * FIFO (32 bytes) at specified data rate 2471 */ 2472 bits_per_char = info->params.data_bits + 2473 info->params.stop_bits + 1; 2474 2475 info->params.data_rate = tty_get_baud_rate(info->port.tty); 2476 2477 if (info->params.data_rate) { 2478 info->timeout = (32*HZ*bits_per_char) / 2479 info->params.data_rate; 2480 } 2481 info->timeout += HZ/50; /* Add .02 seconds of slop */ 2482 2483 tty_port_set_cts_flow(&info->port, cflag & CRTSCTS); 2484 tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL); 2485 2486 /* process tty input control flags */ 2487 2488 info->read_status_mask = IRQ_RXOVER; 2489 if (I_INPCK(info->port.tty)) 2490 info->read_status_mask |= MASK_PARITY | MASK_FRAMING; 2491 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty)) 2492 info->read_status_mask |= MASK_BREAK; 2493 if (I_IGNPAR(info->port.tty)) 2494 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING; 2495 if (I_IGNBRK(info->port.tty)) { 2496 info->ignore_status_mask |= MASK_BREAK; 2497 /* If ignoring parity and break indicators, ignore 2498 * overruns too. (For real raw support). 2499 */ 2500 if (I_IGNPAR(info->port.tty)) 2501 info->ignore_status_mask |= MASK_OVERRUN; 2502 } 2503 2504 program_hw(info); 2505 } 2506 2507 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount) 2508 { 2509 DBGINFO(("%s get_stats\n", info->device_name)); 2510 if (!user_icount) { 2511 memset(&info->icount, 0, sizeof(info->icount)); 2512 } else { 2513 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount))) 2514 return -EFAULT; 2515 } 2516 return 0; 2517 } 2518 2519 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params) 2520 { 2521 DBGINFO(("%s get_params\n", info->device_name)); 2522 if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS))) 2523 return -EFAULT; 2524 return 0; 2525 } 2526 2527 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params) 2528 { 2529 unsigned long flags; 2530 MGSL_PARAMS tmp_params; 2531 2532 DBGINFO(("%s set_params\n", info->device_name)); 2533 if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS))) 2534 return -EFAULT; 2535 2536 spin_lock_irqsave(&info->lock, flags); 2537 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) 2538 info->base_clock = tmp_params.clock_speed; 2539 else 2540 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS)); 2541 spin_unlock_irqrestore(&info->lock, flags); 2542 2543 program_hw(info); 2544 2545 return 0; 2546 } 2547 2548 static int get_txidle(struct slgt_info *info, int __user *idle_mode) 2549 { 2550 DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode)); 2551 if (put_user(info->idle_mode, idle_mode)) 2552 return -EFAULT; 2553 return 0; 2554 } 2555 2556 static int set_txidle(struct slgt_info *info, int idle_mode) 2557 { 2558 unsigned long flags; 2559 DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode)); 2560 spin_lock_irqsave(&info->lock,flags); 2561 info->idle_mode = idle_mode; 2562 if (info->params.mode != MGSL_MODE_ASYNC) 2563 tx_set_idle(info); 2564 spin_unlock_irqrestore(&info->lock,flags); 2565 return 0; 2566 } 2567 2568 static int tx_enable(struct slgt_info *info, int enable) 2569 { 2570 unsigned long flags; 2571 DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable)); 2572 spin_lock_irqsave(&info->lock,flags); 2573 if (enable) { 2574 if (!info->tx_enabled) 2575 tx_start(info); 2576 } else { 2577 if (info->tx_enabled) 2578 tx_stop(info); 2579 } 2580 spin_unlock_irqrestore(&info->lock,flags); 2581 return 0; 2582 } 2583 2584 /* 2585 * abort transmit HDLC frame 2586 */ 2587 static int tx_abort(struct slgt_info *info) 2588 { 2589 unsigned long flags; 2590 DBGINFO(("%s tx_abort\n", info->device_name)); 2591 spin_lock_irqsave(&info->lock,flags); 2592 tdma_reset(info); 2593 spin_unlock_irqrestore(&info->lock,flags); 2594 return 0; 2595 } 2596 2597 static int rx_enable(struct slgt_info *info, int enable) 2598 { 2599 unsigned long flags; 2600 unsigned int rbuf_fill_level; 2601 DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable)); 2602 spin_lock_irqsave(&info->lock,flags); 2603 /* 2604 * enable[31..16] = receive DMA buffer fill level 2605 * 0 = noop (leave fill level unchanged) 2606 * fill level must be multiple of 4 and <= buffer size 2607 */ 2608 rbuf_fill_level = ((unsigned int)enable) >> 16; 2609 if (rbuf_fill_level) { 2610 if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) { 2611 spin_unlock_irqrestore(&info->lock, flags); 2612 return -EINVAL; 2613 } 2614 info->rbuf_fill_level = rbuf_fill_level; 2615 if (rbuf_fill_level < 128) 2616 info->rx_pio = 1; /* PIO mode */ 2617 else 2618 info->rx_pio = 0; /* DMA mode */ 2619 rx_stop(info); /* restart receiver to use new fill level */ 2620 } 2621 2622 /* 2623 * enable[1..0] = receiver enable command 2624 * 0 = disable 2625 * 1 = enable 2626 * 2 = enable or force hunt mode if already enabled 2627 */ 2628 enable &= 3; 2629 if (enable) { 2630 if (!info->rx_enabled) 2631 rx_start(info); 2632 else if (enable == 2) { 2633 /* force hunt mode (write 1 to RCR[3]) */ 2634 wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3); 2635 } 2636 } else { 2637 if (info->rx_enabled) 2638 rx_stop(info); 2639 } 2640 spin_unlock_irqrestore(&info->lock,flags); 2641 return 0; 2642 } 2643 2644 /* 2645 * wait for specified event to occur 2646 */ 2647 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr) 2648 { 2649 unsigned long flags; 2650 int s; 2651 int rc=0; 2652 struct mgsl_icount cprev, cnow; 2653 int events; 2654 int mask; 2655 struct _input_signal_events oldsigs, newsigs; 2656 DECLARE_WAITQUEUE(wait, current); 2657 2658 if (get_user(mask, mask_ptr)) 2659 return -EFAULT; 2660 2661 DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask)); 2662 2663 spin_lock_irqsave(&info->lock,flags); 2664 2665 /* return immediately if state matches requested events */ 2666 get_gtsignals(info); 2667 s = info->signals; 2668 2669 events = mask & 2670 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) + 2671 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) + 2672 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) + 2673 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) ); 2674 if (events) { 2675 spin_unlock_irqrestore(&info->lock,flags); 2676 goto exit; 2677 } 2678 2679 /* save current irq counts */ 2680 cprev = info->icount; 2681 oldsigs = info->input_signal_events; 2682 2683 /* enable hunt and idle irqs if needed */ 2684 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) { 2685 unsigned short val = rd_reg16(info, SCR); 2686 if (!(val & IRQ_RXIDLE)) 2687 wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE)); 2688 } 2689 2690 set_current_state(TASK_INTERRUPTIBLE); 2691 add_wait_queue(&info->event_wait_q, &wait); 2692 2693 spin_unlock_irqrestore(&info->lock,flags); 2694 2695 for(;;) { 2696 schedule(); 2697 if (signal_pending(current)) { 2698 rc = -ERESTARTSYS; 2699 break; 2700 } 2701 2702 /* get current irq counts */ 2703 spin_lock_irqsave(&info->lock,flags); 2704 cnow = info->icount; 2705 newsigs = info->input_signal_events; 2706 set_current_state(TASK_INTERRUPTIBLE); 2707 spin_unlock_irqrestore(&info->lock,flags); 2708 2709 /* if no change, wait aborted for some reason */ 2710 if (newsigs.dsr_up == oldsigs.dsr_up && 2711 newsigs.dsr_down == oldsigs.dsr_down && 2712 newsigs.dcd_up == oldsigs.dcd_up && 2713 newsigs.dcd_down == oldsigs.dcd_down && 2714 newsigs.cts_up == oldsigs.cts_up && 2715 newsigs.cts_down == oldsigs.cts_down && 2716 newsigs.ri_up == oldsigs.ri_up && 2717 newsigs.ri_down == oldsigs.ri_down && 2718 cnow.exithunt == cprev.exithunt && 2719 cnow.rxidle == cprev.rxidle) { 2720 rc = -EIO; 2721 break; 2722 } 2723 2724 events = mask & 2725 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) + 2726 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) + 2727 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) + 2728 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) + 2729 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) + 2730 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) + 2731 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) + 2732 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) + 2733 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) + 2734 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) ); 2735 if (events) 2736 break; 2737 2738 cprev = cnow; 2739 oldsigs = newsigs; 2740 } 2741 2742 remove_wait_queue(&info->event_wait_q, &wait); 2743 set_current_state(TASK_RUNNING); 2744 2745 2746 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) { 2747 spin_lock_irqsave(&info->lock,flags); 2748 if (!waitqueue_active(&info->event_wait_q)) { 2749 /* disable enable exit hunt mode/idle rcvd IRQs */ 2750 wr_reg16(info, SCR, 2751 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE)); 2752 } 2753 spin_unlock_irqrestore(&info->lock,flags); 2754 } 2755 exit: 2756 if (rc == 0) 2757 rc = put_user(events, mask_ptr); 2758 return rc; 2759 } 2760 2761 static int get_interface(struct slgt_info *info, int __user *if_mode) 2762 { 2763 DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode)); 2764 if (put_user(info->if_mode, if_mode)) 2765 return -EFAULT; 2766 return 0; 2767 } 2768 2769 static int set_interface(struct slgt_info *info, int if_mode) 2770 { 2771 unsigned long flags; 2772 unsigned short val; 2773 2774 DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode)); 2775 spin_lock_irqsave(&info->lock,flags); 2776 info->if_mode = if_mode; 2777 2778 msc_set_vcr(info); 2779 2780 /* TCR (tx control) 07 1=RTS driver control */ 2781 val = rd_reg16(info, TCR); 2782 if (info->if_mode & MGSL_INTERFACE_RTS_EN) 2783 val |= BIT7; 2784 else 2785 val &= ~BIT7; 2786 wr_reg16(info, TCR, val); 2787 2788 spin_unlock_irqrestore(&info->lock,flags); 2789 return 0; 2790 } 2791 2792 static int get_xsync(struct slgt_info *info, int __user *xsync) 2793 { 2794 DBGINFO(("%s get_xsync=%x\n", info->device_name, info->xsync)); 2795 if (put_user(info->xsync, xsync)) 2796 return -EFAULT; 2797 return 0; 2798 } 2799 2800 /* 2801 * set extended sync pattern (1 to 4 bytes) for extended sync mode 2802 * 2803 * sync pattern is contained in least significant bytes of value 2804 * most significant byte of sync pattern is oldest (1st sent/detected) 2805 */ 2806 static int set_xsync(struct slgt_info *info, int xsync) 2807 { 2808 unsigned long flags; 2809 2810 DBGINFO(("%s set_xsync=%x)\n", info->device_name, xsync)); 2811 spin_lock_irqsave(&info->lock, flags); 2812 info->xsync = xsync; 2813 wr_reg32(info, XSR, xsync); 2814 spin_unlock_irqrestore(&info->lock, flags); 2815 return 0; 2816 } 2817 2818 static int get_xctrl(struct slgt_info *info, int __user *xctrl) 2819 { 2820 DBGINFO(("%s get_xctrl=%x\n", info->device_name, info->xctrl)); 2821 if (put_user(info->xctrl, xctrl)) 2822 return -EFAULT; 2823 return 0; 2824 } 2825 2826 /* 2827 * set extended control options 2828 * 2829 * xctrl[31:19] reserved, must be zero 2830 * xctrl[18:17] extended sync pattern length in bytes 2831 * 00 = 1 byte in xsr[7:0] 2832 * 01 = 2 bytes in xsr[15:0] 2833 * 10 = 3 bytes in xsr[23:0] 2834 * 11 = 4 bytes in xsr[31:0] 2835 * xctrl[16] 1 = enable terminal count, 0=disabled 2836 * xctrl[15:0] receive terminal count for fixed length packets 2837 * value is count minus one (0 = 1 byte packet) 2838 * when terminal count is reached, receiver 2839 * automatically returns to hunt mode and receive 2840 * FIFO contents are flushed to DMA buffers with 2841 * end of frame (EOF) status 2842 */ 2843 static int set_xctrl(struct slgt_info *info, int xctrl) 2844 { 2845 unsigned long flags; 2846 2847 DBGINFO(("%s set_xctrl=%x)\n", info->device_name, xctrl)); 2848 spin_lock_irqsave(&info->lock, flags); 2849 info->xctrl = xctrl; 2850 wr_reg32(info, XCR, xctrl); 2851 spin_unlock_irqrestore(&info->lock, flags); 2852 return 0; 2853 } 2854 2855 /* 2856 * set general purpose IO pin state and direction 2857 * 2858 * user_gpio fields: 2859 * state each bit indicates a pin state 2860 * smask set bit indicates pin state to set 2861 * dir each bit indicates a pin direction (0=input, 1=output) 2862 * dmask set bit indicates pin direction to set 2863 */ 2864 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio) 2865 { 2866 unsigned long flags; 2867 struct gpio_desc gpio; 2868 __u32 data; 2869 2870 if (!info->gpio_present) 2871 return -EINVAL; 2872 if (copy_from_user(&gpio, user_gpio, sizeof(gpio))) 2873 return -EFAULT; 2874 DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n", 2875 info->device_name, gpio.state, gpio.smask, 2876 gpio.dir, gpio.dmask)); 2877 2878 spin_lock_irqsave(&info->port_array[0]->lock, flags); 2879 if (gpio.dmask) { 2880 data = rd_reg32(info, IODR); 2881 data |= gpio.dmask & gpio.dir; 2882 data &= ~(gpio.dmask & ~gpio.dir); 2883 wr_reg32(info, IODR, data); 2884 } 2885 if (gpio.smask) { 2886 data = rd_reg32(info, IOVR); 2887 data |= gpio.smask & gpio.state; 2888 data &= ~(gpio.smask & ~gpio.state); 2889 wr_reg32(info, IOVR, data); 2890 } 2891 spin_unlock_irqrestore(&info->port_array[0]->lock, flags); 2892 2893 return 0; 2894 } 2895 2896 /* 2897 * get general purpose IO pin state and direction 2898 */ 2899 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio) 2900 { 2901 struct gpio_desc gpio; 2902 if (!info->gpio_present) 2903 return -EINVAL; 2904 gpio.state = rd_reg32(info, IOVR); 2905 gpio.smask = 0xffffffff; 2906 gpio.dir = rd_reg32(info, IODR); 2907 gpio.dmask = 0xffffffff; 2908 if (copy_to_user(user_gpio, &gpio, sizeof(gpio))) 2909 return -EFAULT; 2910 DBGINFO(("%s get_gpio state=%08x dir=%08x\n", 2911 info->device_name, gpio.state, gpio.dir)); 2912 return 0; 2913 } 2914 2915 /* 2916 * conditional wait facility 2917 */ 2918 static void init_cond_wait(struct cond_wait *w, unsigned int data) 2919 { 2920 init_waitqueue_head(&w->q); 2921 init_waitqueue_entry(&w->wait, current); 2922 w->data = data; 2923 } 2924 2925 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w) 2926 { 2927 set_current_state(TASK_INTERRUPTIBLE); 2928 add_wait_queue(&w->q, &w->wait); 2929 w->next = *head; 2930 *head = w; 2931 } 2932 2933 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw) 2934 { 2935 struct cond_wait *w, *prev; 2936 remove_wait_queue(&cw->q, &cw->wait); 2937 set_current_state(TASK_RUNNING); 2938 for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) { 2939 if (w == cw) { 2940 if (prev != NULL) 2941 prev->next = w->next; 2942 else 2943 *head = w->next; 2944 break; 2945 } 2946 } 2947 } 2948 2949 static void flush_cond_wait(struct cond_wait **head) 2950 { 2951 while (*head != NULL) { 2952 wake_up_interruptible(&(*head)->q); 2953 *head = (*head)->next; 2954 } 2955 } 2956 2957 /* 2958 * wait for general purpose I/O pin(s) to enter specified state 2959 * 2960 * user_gpio fields: 2961 * state - bit indicates target pin state 2962 * smask - set bit indicates watched pin 2963 * 2964 * The wait ends when at least one watched pin enters the specified 2965 * state. When 0 (no error) is returned, user_gpio->state is set to the 2966 * state of all GPIO pins when the wait ends. 2967 * 2968 * Note: Each pin may be a dedicated input, dedicated output, or 2969 * configurable input/output. The number and configuration of pins 2970 * varies with the specific adapter model. Only input pins (dedicated 2971 * or configured) can be monitored with this function. 2972 */ 2973 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio) 2974 { 2975 unsigned long flags; 2976 int rc = 0; 2977 struct gpio_desc gpio; 2978 struct cond_wait wait; 2979 u32 state; 2980 2981 if (!info->gpio_present) 2982 return -EINVAL; 2983 if (copy_from_user(&gpio, user_gpio, sizeof(gpio))) 2984 return -EFAULT; 2985 DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n", 2986 info->device_name, gpio.state, gpio.smask)); 2987 /* ignore output pins identified by set IODR bit */ 2988 if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0) 2989 return -EINVAL; 2990 init_cond_wait(&wait, gpio.smask); 2991 2992 spin_lock_irqsave(&info->port_array[0]->lock, flags); 2993 /* enable interrupts for watched pins */ 2994 wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask); 2995 /* get current pin states */ 2996 state = rd_reg32(info, IOVR); 2997 2998 if (gpio.smask & ~(state ^ gpio.state)) { 2999 /* already in target state */ 3000 gpio.state = state; 3001 } else { 3002 /* wait for target state */ 3003 add_cond_wait(&info->gpio_wait_q, &wait); 3004 spin_unlock_irqrestore(&info->port_array[0]->lock, flags); 3005 schedule(); 3006 if (signal_pending(current)) 3007 rc = -ERESTARTSYS; 3008 else 3009 gpio.state = wait.data; 3010 spin_lock_irqsave(&info->port_array[0]->lock, flags); 3011 remove_cond_wait(&info->gpio_wait_q, &wait); 3012 } 3013 3014 /* disable all GPIO interrupts if no waiting processes */ 3015 if (info->gpio_wait_q == NULL) 3016 wr_reg32(info, IOER, 0); 3017 spin_unlock_irqrestore(&info->port_array[0]->lock, flags); 3018 3019 if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio))) 3020 rc = -EFAULT; 3021 return rc; 3022 } 3023 3024 static int modem_input_wait(struct slgt_info *info,int arg) 3025 { 3026 unsigned long flags; 3027 int rc; 3028 struct mgsl_icount cprev, cnow; 3029 DECLARE_WAITQUEUE(wait, current); 3030 3031 /* save current irq counts */ 3032 spin_lock_irqsave(&info->lock,flags); 3033 cprev = info->icount; 3034 add_wait_queue(&info->status_event_wait_q, &wait); 3035 set_current_state(TASK_INTERRUPTIBLE); 3036 spin_unlock_irqrestore(&info->lock,flags); 3037 3038 for(;;) { 3039 schedule(); 3040 if (signal_pending(current)) { 3041 rc = -ERESTARTSYS; 3042 break; 3043 } 3044 3045 /* get new irq counts */ 3046 spin_lock_irqsave(&info->lock,flags); 3047 cnow = info->icount; 3048 set_current_state(TASK_INTERRUPTIBLE); 3049 spin_unlock_irqrestore(&info->lock,flags); 3050 3051 /* if no change, wait aborted for some reason */ 3052 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr && 3053 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) { 3054 rc = -EIO; 3055 break; 3056 } 3057 3058 /* check for change in caller specified modem input */ 3059 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) || 3060 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) || 3061 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) || 3062 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) { 3063 rc = 0; 3064 break; 3065 } 3066 3067 cprev = cnow; 3068 } 3069 remove_wait_queue(&info->status_event_wait_q, &wait); 3070 set_current_state(TASK_RUNNING); 3071 return rc; 3072 } 3073 3074 /* 3075 * return state of serial control and status signals 3076 */ 3077 static int tiocmget(struct tty_struct *tty) 3078 { 3079 struct slgt_info *info = tty->driver_data; 3080 unsigned int result; 3081 unsigned long flags; 3082 3083 spin_lock_irqsave(&info->lock,flags); 3084 get_gtsignals(info); 3085 spin_unlock_irqrestore(&info->lock,flags); 3086 3087 result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) + 3088 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) + 3089 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) + 3090 ((info->signals & SerialSignal_RI) ? TIOCM_RNG:0) + 3091 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) + 3092 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0); 3093 3094 DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result)); 3095 return result; 3096 } 3097 3098 /* 3099 * set modem control signals (DTR/RTS) 3100 * 3101 * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit 3102 * TIOCMSET = set/clear signal values 3103 * value bit mask for command 3104 */ 3105 static int tiocmset(struct tty_struct *tty, 3106 unsigned int set, unsigned int clear) 3107 { 3108 struct slgt_info *info = tty->driver_data; 3109 unsigned long flags; 3110 3111 DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear)); 3112 3113 if (set & TIOCM_RTS) 3114 info->signals |= SerialSignal_RTS; 3115 if (set & TIOCM_DTR) 3116 info->signals |= SerialSignal_DTR; 3117 if (clear & TIOCM_RTS) 3118 info->signals &= ~SerialSignal_RTS; 3119 if (clear & TIOCM_DTR) 3120 info->signals &= ~SerialSignal_DTR; 3121 3122 spin_lock_irqsave(&info->lock,flags); 3123 set_gtsignals(info); 3124 spin_unlock_irqrestore(&info->lock,flags); 3125 return 0; 3126 } 3127 3128 static bool carrier_raised(struct tty_port *port) 3129 { 3130 unsigned long flags; 3131 struct slgt_info *info = container_of(port, struct slgt_info, port); 3132 3133 spin_lock_irqsave(&info->lock,flags); 3134 get_gtsignals(info); 3135 spin_unlock_irqrestore(&info->lock,flags); 3136 3137 return info->signals & SerialSignal_DCD; 3138 } 3139 3140 static void dtr_rts(struct tty_port *port, bool active) 3141 { 3142 unsigned long flags; 3143 struct slgt_info *info = container_of(port, struct slgt_info, port); 3144 3145 spin_lock_irqsave(&info->lock,flags); 3146 if (active) 3147 info->signals |= SerialSignal_RTS | SerialSignal_DTR; 3148 else 3149 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR); 3150 set_gtsignals(info); 3151 spin_unlock_irqrestore(&info->lock,flags); 3152 } 3153 3154 3155 /* 3156 * block current process until the device is ready to open 3157 */ 3158 static int block_til_ready(struct tty_struct *tty, struct file *filp, 3159 struct slgt_info *info) 3160 { 3161 DECLARE_WAITQUEUE(wait, current); 3162 int retval; 3163 bool do_clocal = false; 3164 unsigned long flags; 3165 bool cd; 3166 struct tty_port *port = &info->port; 3167 3168 DBGINFO(("%s block_til_ready\n", tty->driver->name)); 3169 3170 if (filp->f_flags & O_NONBLOCK || tty_io_error(tty)) { 3171 /* nonblock mode is set or port is not enabled */ 3172 tty_port_set_active(port, true); 3173 return 0; 3174 } 3175 3176 if (C_CLOCAL(tty)) 3177 do_clocal = true; 3178 3179 /* Wait for carrier detect and the line to become 3180 * free (i.e., not in use by the callout). While we are in 3181 * this loop, port->count is dropped by one, so that 3182 * close() knows when to free things. We restore it upon 3183 * exit, either normal or abnormal. 3184 */ 3185 3186 retval = 0; 3187 add_wait_queue(&port->open_wait, &wait); 3188 3189 spin_lock_irqsave(&info->lock, flags); 3190 port->count--; 3191 spin_unlock_irqrestore(&info->lock, flags); 3192 port->blocked_open++; 3193 3194 while (1) { 3195 if (C_BAUD(tty) && tty_port_initialized(port)) 3196 tty_port_raise_dtr_rts(port); 3197 3198 set_current_state(TASK_INTERRUPTIBLE); 3199 3200 if (tty_hung_up_p(filp) || !tty_port_initialized(port)) { 3201 retval = (port->flags & ASYNC_HUP_NOTIFY) ? 3202 -EAGAIN : -ERESTARTSYS; 3203 break; 3204 } 3205 3206 cd = tty_port_carrier_raised(port); 3207 if (do_clocal || cd) 3208 break; 3209 3210 if (signal_pending(current)) { 3211 retval = -ERESTARTSYS; 3212 break; 3213 } 3214 3215 DBGINFO(("%s block_til_ready wait\n", tty->driver->name)); 3216 tty_unlock(tty); 3217 schedule(); 3218 tty_lock(tty); 3219 } 3220 3221 set_current_state(TASK_RUNNING); 3222 remove_wait_queue(&port->open_wait, &wait); 3223 3224 if (!tty_hung_up_p(filp)) 3225 port->count++; 3226 port->blocked_open--; 3227 3228 if (!retval) 3229 tty_port_set_active(port, true); 3230 3231 DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval)); 3232 return retval; 3233 } 3234 3235 /* 3236 * allocate buffers used for calling line discipline receive_buf 3237 * directly in synchronous mode 3238 * note: add 5 bytes to max frame size to allow appending 3239 * 32-bit CRC and status byte when configured to do so 3240 */ 3241 static int alloc_tmp_rbuf(struct slgt_info *info) 3242 { 3243 info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL); 3244 if (info->tmp_rbuf == NULL) 3245 return -ENOMEM; 3246 3247 return 0; 3248 } 3249 3250 static void free_tmp_rbuf(struct slgt_info *info) 3251 { 3252 kfree(info->tmp_rbuf); 3253 info->tmp_rbuf = NULL; 3254 } 3255 3256 /* 3257 * allocate DMA descriptor lists. 3258 */ 3259 static int alloc_desc(struct slgt_info *info) 3260 { 3261 unsigned int i; 3262 unsigned int pbufs; 3263 3264 /* allocate memory to hold descriptor lists */ 3265 info->bufs = dma_alloc_coherent(&info->pdev->dev, DESC_LIST_SIZE, 3266 &info->bufs_dma_addr, GFP_KERNEL); 3267 if (info->bufs == NULL) 3268 return -ENOMEM; 3269 3270 info->rbufs = (struct slgt_desc*)info->bufs; 3271 info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count; 3272 3273 pbufs = (unsigned int)info->bufs_dma_addr; 3274 3275 /* 3276 * Build circular lists of descriptors 3277 */ 3278 3279 for (i=0; i < info->rbuf_count; i++) { 3280 /* physical address of this descriptor */ 3281 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc)); 3282 3283 /* physical address of next descriptor */ 3284 if (i == info->rbuf_count - 1) 3285 info->rbufs[i].next = cpu_to_le32(pbufs); 3286 else 3287 info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc))); 3288 set_desc_count(info->rbufs[i], DMABUFSIZE); 3289 } 3290 3291 for (i=0; i < info->tbuf_count; i++) { 3292 /* physical address of this descriptor */ 3293 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc)); 3294 3295 /* physical address of next descriptor */ 3296 if (i == info->tbuf_count - 1) 3297 info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc)); 3298 else 3299 info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc))); 3300 } 3301 3302 return 0; 3303 } 3304 3305 static void free_desc(struct slgt_info *info) 3306 { 3307 if (info->bufs != NULL) { 3308 dma_free_coherent(&info->pdev->dev, DESC_LIST_SIZE, 3309 info->bufs, info->bufs_dma_addr); 3310 info->bufs = NULL; 3311 info->rbufs = NULL; 3312 info->tbufs = NULL; 3313 } 3314 } 3315 3316 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count) 3317 { 3318 int i; 3319 for (i=0; i < count; i++) { 3320 bufs[i].buf = dma_alloc_coherent(&info->pdev->dev, DMABUFSIZE, 3321 &bufs[i].buf_dma_addr, GFP_KERNEL); 3322 if (!bufs[i].buf) 3323 return -ENOMEM; 3324 bufs[i].pbuf = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr); 3325 } 3326 return 0; 3327 } 3328 3329 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count) 3330 { 3331 int i; 3332 for (i=0; i < count; i++) { 3333 if (bufs[i].buf == NULL) 3334 continue; 3335 dma_free_coherent(&info->pdev->dev, DMABUFSIZE, bufs[i].buf, 3336 bufs[i].buf_dma_addr); 3337 bufs[i].buf = NULL; 3338 } 3339 } 3340 3341 static int alloc_dma_bufs(struct slgt_info *info) 3342 { 3343 info->rbuf_count = 32; 3344 info->tbuf_count = 32; 3345 3346 if (alloc_desc(info) < 0 || 3347 alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 || 3348 alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 || 3349 alloc_tmp_rbuf(info) < 0) { 3350 DBGERR(("%s DMA buffer alloc fail\n", info->device_name)); 3351 return -ENOMEM; 3352 } 3353 reset_rbufs(info); 3354 return 0; 3355 } 3356 3357 static void free_dma_bufs(struct slgt_info *info) 3358 { 3359 if (info->bufs) { 3360 free_bufs(info, info->rbufs, info->rbuf_count); 3361 free_bufs(info, info->tbufs, info->tbuf_count); 3362 free_desc(info); 3363 } 3364 free_tmp_rbuf(info); 3365 } 3366 3367 static int claim_resources(struct slgt_info *info) 3368 { 3369 if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) { 3370 DBGERR(("%s reg addr conflict, addr=%08X\n", 3371 info->device_name, info->phys_reg_addr)); 3372 info->init_error = DiagStatus_AddressConflict; 3373 goto errout; 3374 } 3375 else 3376 info->reg_addr_requested = true; 3377 3378 info->reg_addr = ioremap(info->phys_reg_addr, SLGT_REG_SIZE); 3379 if (!info->reg_addr) { 3380 DBGERR(("%s can't map device registers, addr=%08X\n", 3381 info->device_name, info->phys_reg_addr)); 3382 info->init_error = DiagStatus_CantAssignPciResources; 3383 goto errout; 3384 } 3385 return 0; 3386 3387 errout: 3388 release_resources(info); 3389 return -ENODEV; 3390 } 3391 3392 static void release_resources(struct slgt_info *info) 3393 { 3394 if (info->irq_requested) { 3395 free_irq(info->irq_level, info); 3396 info->irq_requested = false; 3397 } 3398 3399 if (info->reg_addr_requested) { 3400 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE); 3401 info->reg_addr_requested = false; 3402 } 3403 3404 if (info->reg_addr) { 3405 iounmap(info->reg_addr); 3406 info->reg_addr = NULL; 3407 } 3408 } 3409 3410 /* Add the specified device instance data structure to the 3411 * global linked list of devices and increment the device count. 3412 */ 3413 static void add_device(struct slgt_info *info) 3414 { 3415 char *devstr; 3416 3417 info->next_device = NULL; 3418 info->line = slgt_device_count; 3419 sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line); 3420 3421 if (info->line < MAX_DEVICES) { 3422 if (maxframe[info->line]) 3423 info->max_frame_size = maxframe[info->line]; 3424 } 3425 3426 slgt_device_count++; 3427 3428 if (!slgt_device_list) 3429 slgt_device_list = info; 3430 else { 3431 struct slgt_info *current_dev = slgt_device_list; 3432 while(current_dev->next_device) 3433 current_dev = current_dev->next_device; 3434 current_dev->next_device = info; 3435 } 3436 3437 if (info->max_frame_size < 4096) 3438 info->max_frame_size = 4096; 3439 else if (info->max_frame_size > 65535) 3440 info->max_frame_size = 65535; 3441 3442 switch(info->pdev->device) { 3443 case SYNCLINK_GT_DEVICE_ID: 3444 devstr = "GT"; 3445 break; 3446 case SYNCLINK_GT2_DEVICE_ID: 3447 devstr = "GT2"; 3448 break; 3449 case SYNCLINK_GT4_DEVICE_ID: 3450 devstr = "GT4"; 3451 break; 3452 case SYNCLINK_AC_DEVICE_ID: 3453 devstr = "AC"; 3454 info->params.mode = MGSL_MODE_ASYNC; 3455 break; 3456 default: 3457 devstr = "(unknown model)"; 3458 } 3459 printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n", 3460 devstr, info->device_name, info->phys_reg_addr, 3461 info->irq_level, info->max_frame_size); 3462 3463 #if SYNCLINK_GENERIC_HDLC 3464 hdlcdev_init(info); 3465 #endif 3466 } 3467 3468 static const struct tty_port_operations slgt_port_ops = { 3469 .carrier_raised = carrier_raised, 3470 .dtr_rts = dtr_rts, 3471 }; 3472 3473 /* 3474 * allocate device instance structure, return NULL on failure 3475 */ 3476 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev) 3477 { 3478 struct slgt_info *info; 3479 3480 info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL); 3481 3482 if (!info) { 3483 DBGERR(("%s device alloc failed adapter=%d port=%d\n", 3484 driver_name, adapter_num, port_num)); 3485 } else { 3486 tty_port_init(&info->port); 3487 info->port.ops = &slgt_port_ops; 3488 INIT_WORK(&info->task, bh_handler); 3489 info->max_frame_size = 4096; 3490 info->base_clock = 14745600; 3491 info->rbuf_fill_level = DMABUFSIZE; 3492 init_waitqueue_head(&info->status_event_wait_q); 3493 init_waitqueue_head(&info->event_wait_q); 3494 spin_lock_init(&info->netlock); 3495 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS)); 3496 info->idle_mode = HDLC_TXIDLE_FLAGS; 3497 info->adapter_num = adapter_num; 3498 info->port_num = port_num; 3499 3500 timer_setup(&info->tx_timer, tx_timeout, 0); 3501 timer_setup(&info->rx_timer, rx_timeout, 0); 3502 3503 /* Copy configuration info to device instance data */ 3504 info->pdev = pdev; 3505 info->irq_level = pdev->irq; 3506 info->phys_reg_addr = pci_resource_start(pdev,0); 3507 3508 info->bus_type = MGSL_BUS_TYPE_PCI; 3509 info->irq_flags = IRQF_SHARED; 3510 3511 info->init_error = -1; /* assume error, set to 0 on successful init */ 3512 } 3513 3514 return info; 3515 } 3516 3517 static void device_init(int adapter_num, struct pci_dev *pdev) 3518 { 3519 struct slgt_info *port_array[SLGT_MAX_PORTS]; 3520 int i; 3521 int port_count = 1; 3522 3523 if (pdev->device == SYNCLINK_GT2_DEVICE_ID) 3524 port_count = 2; 3525 else if (pdev->device == SYNCLINK_GT4_DEVICE_ID) 3526 port_count = 4; 3527 3528 /* allocate device instances for all ports */ 3529 for (i=0; i < port_count; ++i) { 3530 port_array[i] = alloc_dev(adapter_num, i, pdev); 3531 if (port_array[i] == NULL) { 3532 for (--i; i >= 0; --i) { 3533 tty_port_destroy(&port_array[i]->port); 3534 kfree(port_array[i]); 3535 } 3536 return; 3537 } 3538 } 3539 3540 /* give copy of port_array to all ports and add to device list */ 3541 for (i=0; i < port_count; ++i) { 3542 memcpy(port_array[i]->port_array, port_array, sizeof(port_array)); 3543 add_device(port_array[i]); 3544 port_array[i]->port_count = port_count; 3545 spin_lock_init(&port_array[i]->lock); 3546 } 3547 3548 /* Allocate and claim adapter resources */ 3549 if (!claim_resources(port_array[0])) { 3550 3551 alloc_dma_bufs(port_array[0]); 3552 3553 /* copy resource information from first port to others */ 3554 for (i = 1; i < port_count; ++i) { 3555 port_array[i]->irq_level = port_array[0]->irq_level; 3556 port_array[i]->reg_addr = port_array[0]->reg_addr; 3557 alloc_dma_bufs(port_array[i]); 3558 } 3559 3560 if (request_irq(port_array[0]->irq_level, 3561 slgt_interrupt, 3562 port_array[0]->irq_flags, 3563 port_array[0]->device_name, 3564 port_array[0]) < 0) { 3565 DBGERR(("%s request_irq failed IRQ=%d\n", 3566 port_array[0]->device_name, 3567 port_array[0]->irq_level)); 3568 } else { 3569 port_array[0]->irq_requested = true; 3570 adapter_test(port_array[0]); 3571 for (i=1 ; i < port_count ; i++) { 3572 port_array[i]->init_error = port_array[0]->init_error; 3573 port_array[i]->gpio_present = port_array[0]->gpio_present; 3574 } 3575 } 3576 } 3577 3578 for (i = 0; i < port_count; ++i) { 3579 struct slgt_info *info = port_array[i]; 3580 tty_port_register_device(&info->port, serial_driver, info->line, 3581 &info->pdev->dev); 3582 } 3583 } 3584 3585 static int init_one(struct pci_dev *dev, 3586 const struct pci_device_id *ent) 3587 { 3588 if (pci_enable_device(dev)) { 3589 printk("error enabling pci device %p\n", dev); 3590 return -EIO; 3591 } 3592 pci_set_master(dev); 3593 device_init(slgt_device_count, dev); 3594 return 0; 3595 } 3596 3597 static void remove_one(struct pci_dev *dev) 3598 { 3599 } 3600 3601 static const struct tty_operations ops = { 3602 .open = open, 3603 .close = close, 3604 .write = write, 3605 .put_char = put_char, 3606 .flush_chars = flush_chars, 3607 .write_room = write_room, 3608 .chars_in_buffer = chars_in_buffer, 3609 .flush_buffer = flush_buffer, 3610 .ioctl = ioctl, 3611 .compat_ioctl = slgt_compat_ioctl, 3612 .throttle = throttle, 3613 .unthrottle = unthrottle, 3614 .send_xchar = send_xchar, 3615 .break_ctl = set_break, 3616 .wait_until_sent = wait_until_sent, 3617 .set_termios = set_termios, 3618 .stop = tx_hold, 3619 .start = tx_release, 3620 .hangup = hangup, 3621 .tiocmget = tiocmget, 3622 .tiocmset = tiocmset, 3623 .get_icount = get_icount, 3624 .proc_show = synclink_gt_proc_show, 3625 }; 3626 3627 static void slgt_cleanup(void) 3628 { 3629 struct slgt_info *info; 3630 struct slgt_info *tmp; 3631 3632 printk(KERN_INFO "unload %s\n", driver_name); 3633 3634 if (serial_driver) { 3635 for (info=slgt_device_list ; info != NULL ; info=info->next_device) 3636 tty_unregister_device(serial_driver, info->line); 3637 tty_unregister_driver(serial_driver); 3638 tty_driver_kref_put(serial_driver); 3639 } 3640 3641 /* reset devices */ 3642 info = slgt_device_list; 3643 while(info) { 3644 reset_port(info); 3645 info = info->next_device; 3646 } 3647 3648 /* release devices */ 3649 info = slgt_device_list; 3650 while(info) { 3651 #if SYNCLINK_GENERIC_HDLC 3652 hdlcdev_exit(info); 3653 #endif 3654 free_dma_bufs(info); 3655 free_tmp_rbuf(info); 3656 if (info->port_num == 0) 3657 release_resources(info); 3658 tmp = info; 3659 info = info->next_device; 3660 tty_port_destroy(&tmp->port); 3661 kfree(tmp); 3662 } 3663 3664 if (pci_registered) 3665 pci_unregister_driver(&pci_driver); 3666 } 3667 3668 /* 3669 * Driver initialization entry point. 3670 */ 3671 static int __init slgt_init(void) 3672 { 3673 int rc; 3674 3675 printk(KERN_INFO "%s\n", driver_name); 3676 3677 serial_driver = tty_alloc_driver(MAX_DEVICES, TTY_DRIVER_REAL_RAW | 3678 TTY_DRIVER_DYNAMIC_DEV); 3679 if (IS_ERR(serial_driver)) { 3680 printk("%s can't allocate tty driver\n", driver_name); 3681 return PTR_ERR(serial_driver); 3682 } 3683 3684 /* Initialize the tty_driver structure */ 3685 3686 serial_driver->driver_name = slgt_driver_name; 3687 serial_driver->name = tty_dev_prefix; 3688 serial_driver->major = ttymajor; 3689 serial_driver->minor_start = 64; 3690 serial_driver->type = TTY_DRIVER_TYPE_SERIAL; 3691 serial_driver->subtype = SERIAL_TYPE_NORMAL; 3692 serial_driver->init_termios = tty_std_termios; 3693 serial_driver->init_termios.c_cflag = 3694 B9600 | CS8 | CREAD | HUPCL | CLOCAL; 3695 serial_driver->init_termios.c_ispeed = 9600; 3696 serial_driver->init_termios.c_ospeed = 9600; 3697 tty_set_operations(serial_driver, &ops); 3698 if ((rc = tty_register_driver(serial_driver)) < 0) { 3699 DBGERR(("%s can't register serial driver\n", driver_name)); 3700 tty_driver_kref_put(serial_driver); 3701 serial_driver = NULL; 3702 goto error; 3703 } 3704 3705 printk(KERN_INFO "%s, tty major#%d\n", 3706 driver_name, serial_driver->major); 3707 3708 slgt_device_count = 0; 3709 if ((rc = pci_register_driver(&pci_driver)) < 0) { 3710 printk("%s pci_register_driver error=%d\n", driver_name, rc); 3711 goto error; 3712 } 3713 pci_registered = true; 3714 3715 if (!slgt_device_list) 3716 printk("%s no devices found\n",driver_name); 3717 3718 return 0; 3719 3720 error: 3721 slgt_cleanup(); 3722 return rc; 3723 } 3724 3725 static void __exit slgt_exit(void) 3726 { 3727 slgt_cleanup(); 3728 } 3729 3730 module_init(slgt_init); 3731 module_exit(slgt_exit); 3732 3733 /* 3734 * register access routines 3735 */ 3736 3737 #define CALC_REGADDR() \ 3738 unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \ 3739 if (addr >= 0x80) \ 3740 reg_addr += (info->port_num) * 32; \ 3741 else if (addr >= 0x40) \ 3742 reg_addr += (info->port_num) * 16; 3743 3744 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr) 3745 { 3746 CALC_REGADDR(); 3747 return readb((void __iomem *)reg_addr); 3748 } 3749 3750 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value) 3751 { 3752 CALC_REGADDR(); 3753 writeb(value, (void __iomem *)reg_addr); 3754 } 3755 3756 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr) 3757 { 3758 CALC_REGADDR(); 3759 return readw((void __iomem *)reg_addr); 3760 } 3761 3762 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value) 3763 { 3764 CALC_REGADDR(); 3765 writew(value, (void __iomem *)reg_addr); 3766 } 3767 3768 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr) 3769 { 3770 CALC_REGADDR(); 3771 return readl((void __iomem *)reg_addr); 3772 } 3773 3774 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value) 3775 { 3776 CALC_REGADDR(); 3777 writel(value, (void __iomem *)reg_addr); 3778 } 3779 3780 static void rdma_reset(struct slgt_info *info) 3781 { 3782 unsigned int i; 3783 3784 /* set reset bit */ 3785 wr_reg32(info, RDCSR, BIT1); 3786 3787 /* wait for enable bit cleared */ 3788 for(i=0 ; i < 1000 ; i++) 3789 if (!(rd_reg32(info, RDCSR) & BIT0)) 3790 break; 3791 } 3792 3793 static void tdma_reset(struct slgt_info *info) 3794 { 3795 unsigned int i; 3796 3797 /* set reset bit */ 3798 wr_reg32(info, TDCSR, BIT1); 3799 3800 /* wait for enable bit cleared */ 3801 for(i=0 ; i < 1000 ; i++) 3802 if (!(rd_reg32(info, TDCSR) & BIT0)) 3803 break; 3804 } 3805 3806 /* 3807 * enable internal loopback 3808 * TxCLK and RxCLK are generated from BRG 3809 * and TxD is looped back to RxD internally. 3810 */ 3811 static void enable_loopback(struct slgt_info *info) 3812 { 3813 /* SCR (serial control) BIT2=loopback enable */ 3814 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2)); 3815 3816 if (info->params.mode != MGSL_MODE_ASYNC) { 3817 /* CCR (clock control) 3818 * 07..05 tx clock source (010 = BRG) 3819 * 04..02 rx clock source (010 = BRG) 3820 * 01 auxclk enable (0 = disable) 3821 * 00 BRG enable (1 = enable) 3822 * 3823 * 0100 1001 3824 */ 3825 wr_reg8(info, CCR, 0x49); 3826 3827 /* set speed if available, otherwise use default */ 3828 if (info->params.clock_speed) 3829 set_rate(info, info->params.clock_speed); 3830 else 3831 set_rate(info, 3686400); 3832 } 3833 } 3834 3835 /* 3836 * set baud rate generator to specified rate 3837 */ 3838 static void set_rate(struct slgt_info *info, u32 rate) 3839 { 3840 unsigned int div; 3841 unsigned int osc = info->base_clock; 3842 3843 /* div = osc/rate - 1 3844 * 3845 * Round div up if osc/rate is not integer to 3846 * force to next slowest rate. 3847 */ 3848 3849 if (rate) { 3850 div = osc/rate; 3851 if (!(osc % rate) && div) 3852 div--; 3853 wr_reg16(info, BDR, (unsigned short)div); 3854 } 3855 } 3856 3857 static void rx_stop(struct slgt_info *info) 3858 { 3859 unsigned short val; 3860 3861 /* disable and reset receiver */ 3862 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */ 3863 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */ 3864 wr_reg16(info, RCR, val); /* clear reset bit */ 3865 3866 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE); 3867 3868 /* clear pending rx interrupts */ 3869 wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER); 3870 3871 rdma_reset(info); 3872 3873 info->rx_enabled = false; 3874 info->rx_restart = false; 3875 } 3876 3877 static void rx_start(struct slgt_info *info) 3878 { 3879 unsigned short val; 3880 3881 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA); 3882 3883 /* clear pending rx overrun IRQ */ 3884 wr_reg16(info, SSR, IRQ_RXOVER); 3885 3886 /* reset and disable receiver */ 3887 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */ 3888 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */ 3889 wr_reg16(info, RCR, val); /* clear reset bit */ 3890 3891 rdma_reset(info); 3892 reset_rbufs(info); 3893 3894 if (info->rx_pio) { 3895 /* rx request when rx FIFO not empty */ 3896 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14)); 3897 slgt_irq_on(info, IRQ_RXDATA); 3898 if (info->params.mode == MGSL_MODE_ASYNC) { 3899 /* enable saving of rx status */ 3900 wr_reg32(info, RDCSR, BIT6); 3901 } 3902 } else { 3903 /* rx request when rx FIFO half full */ 3904 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14)); 3905 /* set 1st descriptor address */ 3906 wr_reg32(info, RDDAR, info->rbufs[0].pdesc); 3907 3908 if (info->params.mode != MGSL_MODE_ASYNC) { 3909 /* enable rx DMA and DMA interrupt */ 3910 wr_reg32(info, RDCSR, (BIT2 + BIT0)); 3911 } else { 3912 /* enable saving of rx status, rx DMA and DMA interrupt */ 3913 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0)); 3914 } 3915 } 3916 3917 slgt_irq_on(info, IRQ_RXOVER); 3918 3919 /* enable receiver */ 3920 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1)); 3921 3922 info->rx_restart = false; 3923 info->rx_enabled = true; 3924 } 3925 3926 static void tx_start(struct slgt_info *info) 3927 { 3928 if (!info->tx_enabled) { 3929 wr_reg16(info, TCR, 3930 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2)); 3931 info->tx_enabled = true; 3932 } 3933 3934 if (desc_count(info->tbufs[info->tbuf_start])) { 3935 info->drop_rts_on_tx_done = false; 3936 3937 if (info->params.mode != MGSL_MODE_ASYNC) { 3938 if (info->params.flags & HDLC_FLAG_AUTO_RTS) { 3939 get_gtsignals(info); 3940 if (!(info->signals & SerialSignal_RTS)) { 3941 info->signals |= SerialSignal_RTS; 3942 set_gtsignals(info); 3943 info->drop_rts_on_tx_done = true; 3944 } 3945 } 3946 3947 slgt_irq_off(info, IRQ_TXDATA); 3948 slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE); 3949 /* clear tx idle and underrun status bits */ 3950 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER)); 3951 } else { 3952 slgt_irq_off(info, IRQ_TXDATA); 3953 slgt_irq_on(info, IRQ_TXIDLE); 3954 /* clear tx idle status bit */ 3955 wr_reg16(info, SSR, IRQ_TXIDLE); 3956 } 3957 /* set 1st descriptor address and start DMA */ 3958 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc); 3959 wr_reg32(info, TDCSR, BIT2 + BIT0); 3960 info->tx_active = true; 3961 } 3962 } 3963 3964 static void tx_stop(struct slgt_info *info) 3965 { 3966 unsigned short val; 3967 3968 del_timer(&info->tx_timer); 3969 3970 tdma_reset(info); 3971 3972 /* reset and disable transmitter */ 3973 val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */ 3974 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */ 3975 3976 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER); 3977 3978 /* clear tx idle and underrun status bit */ 3979 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER)); 3980 3981 reset_tbufs(info); 3982 3983 info->tx_enabled = false; 3984 info->tx_active = false; 3985 } 3986 3987 static void reset_port(struct slgt_info *info) 3988 { 3989 if (!info->reg_addr) 3990 return; 3991 3992 tx_stop(info); 3993 rx_stop(info); 3994 3995 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR); 3996 set_gtsignals(info); 3997 3998 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER); 3999 } 4000 4001 static void reset_adapter(struct slgt_info *info) 4002 { 4003 int i; 4004 for (i=0; i < info->port_count; ++i) { 4005 if (info->port_array[i]) 4006 reset_port(info->port_array[i]); 4007 } 4008 } 4009 4010 static void async_mode(struct slgt_info *info) 4011 { 4012 unsigned short val; 4013 4014 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER); 4015 tx_stop(info); 4016 rx_stop(info); 4017 4018 /* TCR (tx control) 4019 * 4020 * 15..13 mode, 010=async 4021 * 12..10 encoding, 000=NRZ 4022 * 09 parity enable 4023 * 08 1=odd parity, 0=even parity 4024 * 07 1=RTS driver control 4025 * 06 1=break enable 4026 * 05..04 character length 4027 * 00=5 bits 4028 * 01=6 bits 4029 * 10=7 bits 4030 * 11=8 bits 4031 * 03 0=1 stop bit, 1=2 stop bits 4032 * 02 reset 4033 * 01 enable 4034 * 00 auto-CTS enable 4035 */ 4036 val = 0x4000; 4037 4038 if (info->if_mode & MGSL_INTERFACE_RTS_EN) 4039 val |= BIT7; 4040 4041 if (info->params.parity != ASYNC_PARITY_NONE) { 4042 val |= BIT9; 4043 if (info->params.parity == ASYNC_PARITY_ODD) 4044 val |= BIT8; 4045 } 4046 4047 switch (info->params.data_bits) 4048 { 4049 case 6: val |= BIT4; break; 4050 case 7: val |= BIT5; break; 4051 case 8: val |= BIT5 + BIT4; break; 4052 } 4053 4054 if (info->params.stop_bits != 1) 4055 val |= BIT3; 4056 4057 if (info->params.flags & HDLC_FLAG_AUTO_CTS) 4058 val |= BIT0; 4059 4060 wr_reg16(info, TCR, val); 4061 4062 /* RCR (rx control) 4063 * 4064 * 15..13 mode, 010=async 4065 * 12..10 encoding, 000=NRZ 4066 * 09 parity enable 4067 * 08 1=odd parity, 0=even parity 4068 * 07..06 reserved, must be 0 4069 * 05..04 character length 4070 * 00=5 bits 4071 * 01=6 bits 4072 * 10=7 bits 4073 * 11=8 bits 4074 * 03 reserved, must be zero 4075 * 02 reset 4076 * 01 enable 4077 * 00 auto-DCD enable 4078 */ 4079 val = 0x4000; 4080 4081 if (info->params.parity != ASYNC_PARITY_NONE) { 4082 val |= BIT9; 4083 if (info->params.parity == ASYNC_PARITY_ODD) 4084 val |= BIT8; 4085 } 4086 4087 switch (info->params.data_bits) 4088 { 4089 case 6: val |= BIT4; break; 4090 case 7: val |= BIT5; break; 4091 case 8: val |= BIT5 + BIT4; break; 4092 } 4093 4094 if (info->params.flags & HDLC_FLAG_AUTO_DCD) 4095 val |= BIT0; 4096 4097 wr_reg16(info, RCR, val); 4098 4099 /* CCR (clock control) 4100 * 4101 * 07..05 011 = tx clock source is BRG/16 4102 * 04..02 010 = rx clock source is BRG 4103 * 01 0 = auxclk disabled 4104 * 00 1 = BRG enabled 4105 * 4106 * 0110 1001 4107 */ 4108 wr_reg8(info, CCR, 0x69); 4109 4110 msc_set_vcr(info); 4111 4112 /* SCR (serial control) 4113 * 4114 * 15 1=tx req on FIFO half empty 4115 * 14 1=rx req on FIFO half full 4116 * 13 tx data IRQ enable 4117 * 12 tx idle IRQ enable 4118 * 11 rx break on IRQ enable 4119 * 10 rx data IRQ enable 4120 * 09 rx break off IRQ enable 4121 * 08 overrun IRQ enable 4122 * 07 DSR IRQ enable 4123 * 06 CTS IRQ enable 4124 * 05 DCD IRQ enable 4125 * 04 RI IRQ enable 4126 * 03 0=16x sampling, 1=8x sampling 4127 * 02 1=txd->rxd internal loopback enable 4128 * 01 reserved, must be zero 4129 * 00 1=master IRQ enable 4130 */ 4131 val = BIT15 + BIT14 + BIT0; 4132 /* JCR[8] : 1 = x8 async mode feature available */ 4133 if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate && 4134 ((info->base_clock < (info->params.data_rate * 16)) || 4135 (info->base_clock % (info->params.data_rate * 16)))) { 4136 /* use 8x sampling */ 4137 val |= BIT3; 4138 set_rate(info, info->params.data_rate * 8); 4139 } else { 4140 /* use 16x sampling */ 4141 set_rate(info, info->params.data_rate * 16); 4142 } 4143 wr_reg16(info, SCR, val); 4144 4145 slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER); 4146 4147 if (info->params.loopback) 4148 enable_loopback(info); 4149 } 4150 4151 static void sync_mode(struct slgt_info *info) 4152 { 4153 unsigned short val; 4154 4155 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER); 4156 tx_stop(info); 4157 rx_stop(info); 4158 4159 /* TCR (tx control) 4160 * 4161 * 15..13 mode 4162 * 000=HDLC/SDLC 4163 * 001=raw bit synchronous 4164 * 010=asynchronous/isochronous 4165 * 011=monosync byte synchronous 4166 * 100=bisync byte synchronous 4167 * 101=xsync byte synchronous 4168 * 12..10 encoding 4169 * 09 CRC enable 4170 * 08 CRC32 4171 * 07 1=RTS driver control 4172 * 06 preamble enable 4173 * 05..04 preamble length 4174 * 03 share open/close flag 4175 * 02 reset 4176 * 01 enable 4177 * 00 auto-CTS enable 4178 */ 4179 val = BIT2; 4180 4181 switch(info->params.mode) { 4182 case MGSL_MODE_XSYNC: 4183 val |= BIT15 + BIT13; 4184 break; 4185 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break; 4186 case MGSL_MODE_BISYNC: val |= BIT15; break; 4187 case MGSL_MODE_RAW: val |= BIT13; break; 4188 } 4189 if (info->if_mode & MGSL_INTERFACE_RTS_EN) 4190 val |= BIT7; 4191 4192 switch(info->params.encoding) 4193 { 4194 case HDLC_ENCODING_NRZB: val |= BIT10; break; 4195 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break; 4196 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break; 4197 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break; 4198 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break; 4199 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break; 4200 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; 4201 } 4202 4203 switch (info->params.crc_type & HDLC_CRC_MASK) 4204 { 4205 case HDLC_CRC_16_CCITT: val |= BIT9; break; 4206 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break; 4207 } 4208 4209 if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE) 4210 val |= BIT6; 4211 4212 switch (info->params.preamble_length) 4213 { 4214 case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break; 4215 case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break; 4216 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break; 4217 } 4218 4219 if (info->params.flags & HDLC_FLAG_AUTO_CTS) 4220 val |= BIT0; 4221 4222 wr_reg16(info, TCR, val); 4223 4224 /* TPR (transmit preamble) */ 4225 4226 switch (info->params.preamble) 4227 { 4228 case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break; 4229 case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break; 4230 case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break; 4231 case HDLC_PREAMBLE_PATTERN_10: val = 0x55; break; 4232 case HDLC_PREAMBLE_PATTERN_01: val = 0xaa; break; 4233 default: val = 0x7e; break; 4234 } 4235 wr_reg8(info, TPR, (unsigned char)val); 4236 4237 /* RCR (rx control) 4238 * 4239 * 15..13 mode 4240 * 000=HDLC/SDLC 4241 * 001=raw bit synchronous 4242 * 010=asynchronous/isochronous 4243 * 011=monosync byte synchronous 4244 * 100=bisync byte synchronous 4245 * 101=xsync byte synchronous 4246 * 12..10 encoding 4247 * 09 CRC enable 4248 * 08 CRC32 4249 * 07..03 reserved, must be 0 4250 * 02 reset 4251 * 01 enable 4252 * 00 auto-DCD enable 4253 */ 4254 val = 0; 4255 4256 switch(info->params.mode) { 4257 case MGSL_MODE_XSYNC: 4258 val |= BIT15 + BIT13; 4259 break; 4260 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break; 4261 case MGSL_MODE_BISYNC: val |= BIT15; break; 4262 case MGSL_MODE_RAW: val |= BIT13; break; 4263 } 4264 4265 switch(info->params.encoding) 4266 { 4267 case HDLC_ENCODING_NRZB: val |= BIT10; break; 4268 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break; 4269 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break; 4270 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break; 4271 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break; 4272 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break; 4273 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; 4274 } 4275 4276 switch (info->params.crc_type & HDLC_CRC_MASK) 4277 { 4278 case HDLC_CRC_16_CCITT: val |= BIT9; break; 4279 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break; 4280 } 4281 4282 if (info->params.flags & HDLC_FLAG_AUTO_DCD) 4283 val |= BIT0; 4284 4285 wr_reg16(info, RCR, val); 4286 4287 /* CCR (clock control) 4288 * 4289 * 07..05 tx clock source 4290 * 04..02 rx clock source 4291 * 01 auxclk enable 4292 * 00 BRG enable 4293 */ 4294 val = 0; 4295 4296 if (info->params.flags & HDLC_FLAG_TXC_BRG) 4297 { 4298 // when RxC source is DPLL, BRG generates 16X DPLL 4299 // reference clock, so take TxC from BRG/16 to get 4300 // transmit clock at actual data rate 4301 if (info->params.flags & HDLC_FLAG_RXC_DPLL) 4302 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */ 4303 else 4304 val |= BIT6; /* 010, txclk = BRG */ 4305 } 4306 else if (info->params.flags & HDLC_FLAG_TXC_DPLL) 4307 val |= BIT7; /* 100, txclk = DPLL Input */ 4308 else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN) 4309 val |= BIT5; /* 001, txclk = RXC Input */ 4310 4311 if (info->params.flags & HDLC_FLAG_RXC_BRG) 4312 val |= BIT3; /* 010, rxclk = BRG */ 4313 else if (info->params.flags & HDLC_FLAG_RXC_DPLL) 4314 val |= BIT4; /* 100, rxclk = DPLL */ 4315 else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN) 4316 val |= BIT2; /* 001, rxclk = TXC Input */ 4317 4318 if (info->params.clock_speed) 4319 val |= BIT1 + BIT0; 4320 4321 wr_reg8(info, CCR, (unsigned char)val); 4322 4323 if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL)) 4324 { 4325 // program DPLL mode 4326 switch(info->params.encoding) 4327 { 4328 case HDLC_ENCODING_BIPHASE_MARK: 4329 case HDLC_ENCODING_BIPHASE_SPACE: 4330 val = BIT7; break; 4331 case HDLC_ENCODING_BIPHASE_LEVEL: 4332 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: 4333 val = BIT7 + BIT6; break; 4334 default: val = BIT6; // NRZ encodings 4335 } 4336 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val)); 4337 4338 // DPLL requires a 16X reference clock from BRG 4339 set_rate(info, info->params.clock_speed * 16); 4340 } 4341 else 4342 set_rate(info, info->params.clock_speed); 4343 4344 tx_set_idle(info); 4345 4346 msc_set_vcr(info); 4347 4348 /* SCR (serial control) 4349 * 4350 * 15 1=tx req on FIFO half empty 4351 * 14 1=rx req on FIFO half full 4352 * 13 tx data IRQ enable 4353 * 12 tx idle IRQ enable 4354 * 11 underrun IRQ enable 4355 * 10 rx data IRQ enable 4356 * 09 rx idle IRQ enable 4357 * 08 overrun IRQ enable 4358 * 07 DSR IRQ enable 4359 * 06 CTS IRQ enable 4360 * 05 DCD IRQ enable 4361 * 04 RI IRQ enable 4362 * 03 reserved, must be zero 4363 * 02 1=txd->rxd internal loopback enable 4364 * 01 reserved, must be zero 4365 * 00 1=master IRQ enable 4366 */ 4367 wr_reg16(info, SCR, BIT15 + BIT14 + BIT0); 4368 4369 if (info->params.loopback) 4370 enable_loopback(info); 4371 } 4372 4373 /* 4374 * set transmit idle mode 4375 */ 4376 static void tx_set_idle(struct slgt_info *info) 4377 { 4378 unsigned char val; 4379 unsigned short tcr; 4380 4381 /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits 4382 * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits 4383 */ 4384 tcr = rd_reg16(info, TCR); 4385 if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) { 4386 /* disable preamble, set idle size to 16 bits */ 4387 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4; 4388 /* MSB of 16 bit idle specified in tx preamble register (TPR) */ 4389 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff)); 4390 } else if (!(tcr & BIT6)) { 4391 /* preamble is disabled, set idle size to 8 bits */ 4392 tcr &= ~(BIT5 + BIT4); 4393 } 4394 wr_reg16(info, TCR, tcr); 4395 4396 if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) { 4397 /* LSB of custom tx idle specified in tx idle register */ 4398 val = (unsigned char)(info->idle_mode & 0xff); 4399 } else { 4400 /* standard 8 bit idle patterns */ 4401 switch(info->idle_mode) 4402 { 4403 case HDLC_TXIDLE_FLAGS: val = 0x7e; break; 4404 case HDLC_TXIDLE_ALT_ZEROS_ONES: 4405 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break; 4406 case HDLC_TXIDLE_ZEROS: 4407 case HDLC_TXIDLE_SPACE: val = 0x00; break; 4408 default: val = 0xff; 4409 } 4410 } 4411 4412 wr_reg8(info, TIR, val); 4413 } 4414 4415 /* 4416 * get state of V24 status (input) signals 4417 */ 4418 static void get_gtsignals(struct slgt_info *info) 4419 { 4420 unsigned short status = rd_reg16(info, SSR); 4421 4422 /* clear all serial signals except RTS and DTR */ 4423 info->signals &= SerialSignal_RTS | SerialSignal_DTR; 4424 4425 if (status & BIT3) 4426 info->signals |= SerialSignal_DSR; 4427 if (status & BIT2) 4428 info->signals |= SerialSignal_CTS; 4429 if (status & BIT1) 4430 info->signals |= SerialSignal_DCD; 4431 if (status & BIT0) 4432 info->signals |= SerialSignal_RI; 4433 } 4434 4435 /* 4436 * set V.24 Control Register based on current configuration 4437 */ 4438 static void msc_set_vcr(struct slgt_info *info) 4439 { 4440 unsigned char val = 0; 4441 4442 /* VCR (V.24 control) 4443 * 4444 * 07..04 serial IF select 4445 * 03 DTR 4446 * 02 RTS 4447 * 01 LL 4448 * 00 RL 4449 */ 4450 4451 switch(info->if_mode & MGSL_INTERFACE_MASK) 4452 { 4453 case MGSL_INTERFACE_RS232: 4454 val |= BIT5; /* 0010 */ 4455 break; 4456 case MGSL_INTERFACE_V35: 4457 val |= BIT7 + BIT6 + BIT5; /* 1110 */ 4458 break; 4459 case MGSL_INTERFACE_RS422: 4460 val |= BIT6; /* 0100 */ 4461 break; 4462 } 4463 4464 if (info->if_mode & MGSL_INTERFACE_MSB_FIRST) 4465 val |= BIT4; 4466 if (info->signals & SerialSignal_DTR) 4467 val |= BIT3; 4468 if (info->signals & SerialSignal_RTS) 4469 val |= BIT2; 4470 if (info->if_mode & MGSL_INTERFACE_LL) 4471 val |= BIT1; 4472 if (info->if_mode & MGSL_INTERFACE_RL) 4473 val |= BIT0; 4474 wr_reg8(info, VCR, val); 4475 } 4476 4477 /* 4478 * set state of V24 control (output) signals 4479 */ 4480 static void set_gtsignals(struct slgt_info *info) 4481 { 4482 unsigned char val = rd_reg8(info, VCR); 4483 if (info->signals & SerialSignal_DTR) 4484 val |= BIT3; 4485 else 4486 val &= ~BIT3; 4487 if (info->signals & SerialSignal_RTS) 4488 val |= BIT2; 4489 else 4490 val &= ~BIT2; 4491 wr_reg8(info, VCR, val); 4492 } 4493 4494 /* 4495 * free range of receive DMA buffers (i to last) 4496 */ 4497 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last) 4498 { 4499 int done = 0; 4500 4501 while(!done) { 4502 /* reset current buffer for reuse */ 4503 info->rbufs[i].status = 0; 4504 set_desc_count(info->rbufs[i], info->rbuf_fill_level); 4505 if (i == last) 4506 done = 1; 4507 if (++i == info->rbuf_count) 4508 i = 0; 4509 } 4510 info->rbuf_current = i; 4511 } 4512 4513 /* 4514 * mark all receive DMA buffers as free 4515 */ 4516 static void reset_rbufs(struct slgt_info *info) 4517 { 4518 free_rbufs(info, 0, info->rbuf_count - 1); 4519 info->rbuf_fill_index = 0; 4520 info->rbuf_fill_count = 0; 4521 } 4522 4523 /* 4524 * pass receive HDLC frame to upper layer 4525 * 4526 * return true if frame available, otherwise false 4527 */ 4528 static bool rx_get_frame(struct slgt_info *info) 4529 { 4530 unsigned int start, end; 4531 unsigned short status; 4532 unsigned int framesize = 0; 4533 unsigned long flags; 4534 struct tty_struct *tty = info->port.tty; 4535 unsigned char addr_field = 0xff; 4536 unsigned int crc_size = 0; 4537 4538 switch (info->params.crc_type & HDLC_CRC_MASK) { 4539 case HDLC_CRC_16_CCITT: crc_size = 2; break; 4540 case HDLC_CRC_32_CCITT: crc_size = 4; break; 4541 } 4542 4543 check_again: 4544 4545 framesize = 0; 4546 addr_field = 0xff; 4547 start = end = info->rbuf_current; 4548 4549 for (;;) { 4550 if (!desc_complete(info->rbufs[end])) 4551 goto cleanup; 4552 4553 if (framesize == 0 && info->params.addr_filter != 0xff) 4554 addr_field = info->rbufs[end].buf[0]; 4555 4556 framesize += desc_count(info->rbufs[end]); 4557 4558 if (desc_eof(info->rbufs[end])) 4559 break; 4560 4561 if (++end == info->rbuf_count) 4562 end = 0; 4563 4564 if (end == info->rbuf_current) { 4565 if (info->rx_enabled){ 4566 spin_lock_irqsave(&info->lock,flags); 4567 rx_start(info); 4568 spin_unlock_irqrestore(&info->lock,flags); 4569 } 4570 goto cleanup; 4571 } 4572 } 4573 4574 /* status 4575 * 4576 * 15 buffer complete 4577 * 14..06 reserved 4578 * 05..04 residue 4579 * 02 eof (end of frame) 4580 * 01 CRC error 4581 * 00 abort 4582 */ 4583 status = desc_status(info->rbufs[end]); 4584 4585 /* ignore CRC bit if not using CRC (bit is undefined) */ 4586 if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE) 4587 status &= ~BIT1; 4588 4589 if (framesize == 0 || 4590 (addr_field != 0xff && addr_field != info->params.addr_filter)) { 4591 free_rbufs(info, start, end); 4592 goto check_again; 4593 } 4594 4595 if (framesize < (2 + crc_size) || status & BIT0) { 4596 info->icount.rxshort++; 4597 framesize = 0; 4598 } else if (status & BIT1) { 4599 info->icount.rxcrc++; 4600 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) 4601 framesize = 0; 4602 } 4603 4604 #if SYNCLINK_GENERIC_HDLC 4605 if (framesize == 0) { 4606 info->netdev->stats.rx_errors++; 4607 info->netdev->stats.rx_frame_errors++; 4608 } 4609 #endif 4610 4611 DBGBH(("%s rx frame status=%04X size=%d\n", 4612 info->device_name, status, framesize)); 4613 DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx"); 4614 4615 if (framesize) { 4616 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) { 4617 framesize -= crc_size; 4618 crc_size = 0; 4619 } 4620 4621 if (framesize > info->max_frame_size + crc_size) 4622 info->icount.rxlong++; 4623 else { 4624 /* copy dma buffer(s) to contiguous temp buffer */ 4625 int copy_count = framesize; 4626 int i = start; 4627 unsigned char *p = info->tmp_rbuf; 4628 info->tmp_rbuf_count = framesize; 4629 4630 info->icount.rxok++; 4631 4632 while(copy_count) { 4633 int partial_count = min_t(int, copy_count, info->rbuf_fill_level); 4634 memcpy(p, info->rbufs[i].buf, partial_count); 4635 p += partial_count; 4636 copy_count -= partial_count; 4637 if (++i == info->rbuf_count) 4638 i = 0; 4639 } 4640 4641 if (info->params.crc_type & HDLC_CRC_RETURN_EX) { 4642 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK; 4643 framesize++; 4644 } 4645 4646 #if SYNCLINK_GENERIC_HDLC 4647 if (info->netcount) 4648 hdlcdev_rx(info,info->tmp_rbuf, framesize); 4649 else 4650 #endif 4651 ldisc_receive_buf(tty, info->tmp_rbuf, NULL, 4652 framesize); 4653 } 4654 } 4655 free_rbufs(info, start, end); 4656 return true; 4657 4658 cleanup: 4659 return false; 4660 } 4661 4662 /* 4663 * pass receive buffer (RAW synchronous mode) to tty layer 4664 * return true if buffer available, otherwise false 4665 */ 4666 static bool rx_get_buf(struct slgt_info *info) 4667 { 4668 unsigned int i = info->rbuf_current; 4669 unsigned int count; 4670 4671 if (!desc_complete(info->rbufs[i])) 4672 return false; 4673 count = desc_count(info->rbufs[i]); 4674 switch(info->params.mode) { 4675 case MGSL_MODE_MONOSYNC: 4676 case MGSL_MODE_BISYNC: 4677 case MGSL_MODE_XSYNC: 4678 /* ignore residue in byte synchronous modes */ 4679 if (desc_residue(info->rbufs[i])) 4680 count--; 4681 break; 4682 } 4683 DBGDATA(info, info->rbufs[i].buf, count, "rx"); 4684 DBGINFO(("rx_get_buf size=%d\n", count)); 4685 if (count) 4686 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf, NULL, 4687 count); 4688 free_rbufs(info, i, i); 4689 return true; 4690 } 4691 4692 static void reset_tbufs(struct slgt_info *info) 4693 { 4694 unsigned int i; 4695 info->tbuf_current = 0; 4696 for (i=0 ; i < info->tbuf_count ; i++) { 4697 info->tbufs[i].status = 0; 4698 info->tbufs[i].count = 0; 4699 } 4700 } 4701 4702 /* 4703 * return number of free transmit DMA buffers 4704 */ 4705 static unsigned int free_tbuf_count(struct slgt_info *info) 4706 { 4707 unsigned int count = 0; 4708 unsigned int i = info->tbuf_current; 4709 4710 do 4711 { 4712 if (desc_count(info->tbufs[i])) 4713 break; /* buffer in use */ 4714 ++count; 4715 if (++i == info->tbuf_count) 4716 i=0; 4717 } while (i != info->tbuf_current); 4718 4719 /* if tx DMA active, last zero count buffer is in use */ 4720 if (count && (rd_reg32(info, TDCSR) & BIT0)) 4721 --count; 4722 4723 return count; 4724 } 4725 4726 /* 4727 * return number of bytes in unsent transmit DMA buffers 4728 * and the serial controller tx FIFO 4729 */ 4730 static unsigned int tbuf_bytes(struct slgt_info *info) 4731 { 4732 unsigned int total_count = 0; 4733 unsigned int i = info->tbuf_current; 4734 unsigned int reg_value; 4735 unsigned int count; 4736 unsigned int active_buf_count = 0; 4737 4738 /* 4739 * Add descriptor counts for all tx DMA buffers. 4740 * If count is zero (cleared by DMA controller after read), 4741 * the buffer is complete or is actively being read from. 4742 * 4743 * Record buf_count of last buffer with zero count starting 4744 * from current ring position. buf_count is mirror 4745 * copy of count and is not cleared by serial controller. 4746 * If DMA controller is active, that buffer is actively 4747 * being read so add to total. 4748 */ 4749 do { 4750 count = desc_count(info->tbufs[i]); 4751 if (count) 4752 total_count += count; 4753 else if (!total_count) 4754 active_buf_count = info->tbufs[i].buf_count; 4755 if (++i == info->tbuf_count) 4756 i = 0; 4757 } while (i != info->tbuf_current); 4758 4759 /* read tx DMA status register */ 4760 reg_value = rd_reg32(info, TDCSR); 4761 4762 /* if tx DMA active, last zero count buffer is in use */ 4763 if (reg_value & BIT0) 4764 total_count += active_buf_count; 4765 4766 /* add tx FIFO count = reg_value[15..8] */ 4767 total_count += (reg_value >> 8) & 0xff; 4768 4769 /* if transmitter active add one byte for shift register */ 4770 if (info->tx_active) 4771 total_count++; 4772 4773 return total_count; 4774 } 4775 4776 /* 4777 * load data into transmit DMA buffer ring and start transmitter if needed 4778 * return true if data accepted, otherwise false (buffers full) 4779 */ 4780 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int size) 4781 { 4782 unsigned short count; 4783 unsigned int i; 4784 struct slgt_desc *d; 4785 4786 /* check required buffer space */ 4787 if (DIV_ROUND_UP(size, DMABUFSIZE) > free_tbuf_count(info)) 4788 return false; 4789 4790 DBGDATA(info, buf, size, "tx"); 4791 4792 /* 4793 * copy data to one or more DMA buffers in circular ring 4794 * tbuf_start = first buffer for this data 4795 * tbuf_current = next free buffer 4796 * 4797 * Copy all data before making data visible to DMA controller by 4798 * setting descriptor count of the first buffer. 4799 * This prevents an active DMA controller from reading the first DMA 4800 * buffers of a frame and stopping before the final buffers are filled. 4801 */ 4802 4803 info->tbuf_start = i = info->tbuf_current; 4804 4805 while (size) { 4806 d = &info->tbufs[i]; 4807 4808 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size); 4809 memcpy(d->buf, buf, count); 4810 4811 size -= count; 4812 buf += count; 4813 4814 /* 4815 * set EOF bit for last buffer of HDLC frame or 4816 * for every buffer in raw mode 4817 */ 4818 if ((!size && info->params.mode == MGSL_MODE_HDLC) || 4819 info->params.mode == MGSL_MODE_RAW) 4820 set_desc_eof(*d, 1); 4821 else 4822 set_desc_eof(*d, 0); 4823 4824 /* set descriptor count for all but first buffer */ 4825 if (i != info->tbuf_start) 4826 set_desc_count(*d, count); 4827 d->buf_count = count; 4828 4829 if (++i == info->tbuf_count) 4830 i = 0; 4831 } 4832 4833 info->tbuf_current = i; 4834 4835 /* set first buffer count to make new data visible to DMA controller */ 4836 d = &info->tbufs[info->tbuf_start]; 4837 set_desc_count(*d, d->buf_count); 4838 4839 /* start transmitter if needed and update transmit timeout */ 4840 if (!info->tx_active) 4841 tx_start(info); 4842 update_tx_timer(info); 4843 4844 return true; 4845 } 4846 4847 static int register_test(struct slgt_info *info) 4848 { 4849 static unsigned short patterns[] = 4850 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696}; 4851 static unsigned int count = ARRAY_SIZE(patterns); 4852 unsigned int i; 4853 int rc = 0; 4854 4855 for (i=0 ; i < count ; i++) { 4856 wr_reg16(info, TIR, patterns[i]); 4857 wr_reg16(info, BDR, patterns[(i+1)%count]); 4858 if ((rd_reg16(info, TIR) != patterns[i]) || 4859 (rd_reg16(info, BDR) != patterns[(i+1)%count])) { 4860 rc = -ENODEV; 4861 break; 4862 } 4863 } 4864 info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0; 4865 info->init_error = rc ? 0 : DiagStatus_AddressFailure; 4866 return rc; 4867 } 4868 4869 static int irq_test(struct slgt_info *info) 4870 { 4871 unsigned long timeout; 4872 unsigned long flags; 4873 struct tty_struct *oldtty = info->port.tty; 4874 u32 speed = info->params.data_rate; 4875 4876 info->params.data_rate = 921600; 4877 info->port.tty = NULL; 4878 4879 spin_lock_irqsave(&info->lock, flags); 4880 async_mode(info); 4881 slgt_irq_on(info, IRQ_TXIDLE); 4882 4883 /* enable transmitter */ 4884 wr_reg16(info, TCR, 4885 (unsigned short)(rd_reg16(info, TCR) | BIT1)); 4886 4887 /* write one byte and wait for tx idle */ 4888 wr_reg16(info, TDR, 0); 4889 4890 /* assume failure */ 4891 info->init_error = DiagStatus_IrqFailure; 4892 info->irq_occurred = false; 4893 4894 spin_unlock_irqrestore(&info->lock, flags); 4895 4896 timeout=100; 4897 while(timeout-- && !info->irq_occurred) 4898 msleep_interruptible(10); 4899 4900 spin_lock_irqsave(&info->lock,flags); 4901 reset_port(info); 4902 spin_unlock_irqrestore(&info->lock,flags); 4903 4904 info->params.data_rate = speed; 4905 info->port.tty = oldtty; 4906 4907 info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure; 4908 return info->irq_occurred ? 0 : -ENODEV; 4909 } 4910 4911 static int loopback_test_rx(struct slgt_info *info) 4912 { 4913 unsigned char *src, *dest; 4914 int count; 4915 4916 if (desc_complete(info->rbufs[0])) { 4917 count = desc_count(info->rbufs[0]); 4918 src = info->rbufs[0].buf; 4919 dest = info->tmp_rbuf; 4920 4921 for( ; count ; count-=2, src+=2) { 4922 /* src=data byte (src+1)=status byte */ 4923 if (!(*(src+1) & (BIT9 + BIT8))) { 4924 *dest = *src; 4925 dest++; 4926 info->tmp_rbuf_count++; 4927 } 4928 } 4929 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx"); 4930 return 1; 4931 } 4932 return 0; 4933 } 4934 4935 static int loopback_test(struct slgt_info *info) 4936 { 4937 #define TESTFRAMESIZE 20 4938 4939 unsigned long timeout; 4940 u16 count; 4941 unsigned char buf[TESTFRAMESIZE]; 4942 int rc = -ENODEV; 4943 unsigned long flags; 4944 4945 struct tty_struct *oldtty = info->port.tty; 4946 MGSL_PARAMS params; 4947 4948 memcpy(¶ms, &info->params, sizeof(params)); 4949 4950 info->params.mode = MGSL_MODE_ASYNC; 4951 info->params.data_rate = 921600; 4952 info->params.loopback = 1; 4953 info->port.tty = NULL; 4954 4955 /* build and send transmit frame */ 4956 for (count = 0; count < TESTFRAMESIZE; ++count) 4957 buf[count] = (unsigned char)count; 4958 4959 info->tmp_rbuf_count = 0; 4960 memset(info->tmp_rbuf, 0, TESTFRAMESIZE); 4961 4962 /* program hardware for HDLC and enabled receiver */ 4963 spin_lock_irqsave(&info->lock,flags); 4964 async_mode(info); 4965 rx_start(info); 4966 tx_load(info, buf, count); 4967 spin_unlock_irqrestore(&info->lock, flags); 4968 4969 /* wait for receive complete */ 4970 for (timeout = 100; timeout; --timeout) { 4971 msleep_interruptible(10); 4972 if (loopback_test_rx(info)) { 4973 rc = 0; 4974 break; 4975 } 4976 } 4977 4978 /* verify received frame length and contents */ 4979 if (!rc && (info->tmp_rbuf_count != count || 4980 memcmp(buf, info->tmp_rbuf, count))) { 4981 rc = -ENODEV; 4982 } 4983 4984 spin_lock_irqsave(&info->lock,flags); 4985 reset_adapter(info); 4986 spin_unlock_irqrestore(&info->lock,flags); 4987 4988 memcpy(&info->params, ¶ms, sizeof(info->params)); 4989 info->port.tty = oldtty; 4990 4991 info->init_error = rc ? DiagStatus_DmaFailure : 0; 4992 return rc; 4993 } 4994 4995 static int adapter_test(struct slgt_info *info) 4996 { 4997 DBGINFO(("testing %s\n", info->device_name)); 4998 if (register_test(info) < 0) { 4999 printk("register test failure %s addr=%08X\n", 5000 info->device_name, info->phys_reg_addr); 5001 } else if (irq_test(info) < 0) { 5002 printk("IRQ test failure %s IRQ=%d\n", 5003 info->device_name, info->irq_level); 5004 } else if (loopback_test(info) < 0) { 5005 printk("loopback test failure %s\n", info->device_name); 5006 } 5007 return info->init_error; 5008 } 5009 5010 /* 5011 * transmit timeout handler 5012 */ 5013 static void tx_timeout(struct timer_list *t) 5014 { 5015 struct slgt_info *info = from_timer(info, t, tx_timer); 5016 unsigned long flags; 5017 5018 DBGINFO(("%s tx_timeout\n", info->device_name)); 5019 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) { 5020 info->icount.txtimeout++; 5021 } 5022 spin_lock_irqsave(&info->lock,flags); 5023 tx_stop(info); 5024 spin_unlock_irqrestore(&info->lock,flags); 5025 5026 #if SYNCLINK_GENERIC_HDLC 5027 if (info->netcount) 5028 hdlcdev_tx_done(info); 5029 else 5030 #endif 5031 bh_transmit(info); 5032 } 5033 5034 /* 5035 * receive buffer polling timer 5036 */ 5037 static void rx_timeout(struct timer_list *t) 5038 { 5039 struct slgt_info *info = from_timer(info, t, rx_timer); 5040 unsigned long flags; 5041 5042 DBGINFO(("%s rx_timeout\n", info->device_name)); 5043 spin_lock_irqsave(&info->lock, flags); 5044 info->pending_bh |= BH_RECEIVE; 5045 spin_unlock_irqrestore(&info->lock, flags); 5046 bh_handler(&info->task); 5047 } 5048 5049