1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * zs.c: Serial port driver for IOASIC DECstations. 4 * 5 * Derived from drivers/sbus/char/sunserial.c by Paul Mackerras. 6 * Derived from drivers/macintosh/macserial.c by Harald Koerfgen. 7 * 8 * DECstation changes 9 * Copyright (C) 1998-2000 Harald Koerfgen 10 * Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki 11 * 12 * For the rest of the code the original Copyright applies: 13 * Copyright (C) 1996 Paul Mackerras (Paul.Mackerras@cs.anu.edu.au) 14 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) 15 * 16 * 17 * Note: for IOASIC systems the wiring is as follows: 18 * 19 * mouse/keyboard: 20 * DIN-7 MJ-4 signal SCC 21 * 2 1 TxD <- A.TxD 22 * 3 4 RxD -> A.RxD 23 * 24 * EIA-232/EIA-423: 25 * DB-25 MMJ-6 signal SCC 26 * 2 2 TxD <- B.TxD 27 * 3 5 RxD -> B.RxD 28 * 4 RTS <- ~A.RTS 29 * 5 CTS -> ~B.CTS 30 * 6 6 DSR -> ~A.SYNC 31 * 8 CD -> ~B.DCD 32 * 12 DSRS(DCE) -> ~A.CTS (*) 33 * 15 TxC -> B.TxC 34 * 17 RxC -> B.RxC 35 * 20 1 DTR <- ~A.DTR 36 * 22 RI -> ~A.DCD 37 * 23 DSRS(DTE) <- ~B.RTS 38 * 39 * (*) EIA-232 defines the signal at this pin to be SCD, while DSRS(DCE) 40 * is shared with DSRS(DTE) at pin 23. 41 * 42 * As you can immediately notice the wiring of the RTS, DTR and DSR signals 43 * is a bit odd. This makes the handling of port B unnecessarily 44 * complicated and prevents the use of some automatic modes of operation. 45 */ 46 47 #if defined(CONFIG_SERIAL_ZS_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 48 #define SUPPORT_SYSRQ 49 #endif 50 51 #include <linux/bug.h> 52 #include <linux/console.h> 53 #include <linux/delay.h> 54 #include <linux/errno.h> 55 #include <linux/init.h> 56 #include <linux/interrupt.h> 57 #include <linux/io.h> 58 #include <linux/ioport.h> 59 #include <linux/irqflags.h> 60 #include <linux/kernel.h> 61 #include <linux/module.h> 62 #include <linux/major.h> 63 #include <linux/serial.h> 64 #include <linux/serial_core.h> 65 #include <linux/spinlock.h> 66 #include <linux/sysrq.h> 67 #include <linux/tty.h> 68 #include <linux/tty_flip.h> 69 #include <linux/types.h> 70 71 #include <linux/atomic.h> 72 73 #include <asm/dec/interrupts.h> 74 #include <asm/dec/ioasic_addrs.h> 75 #include <asm/dec/system.h> 76 77 #include "zs.h" 78 79 80 MODULE_AUTHOR("Maciej W. Rozycki <macro@linux-mips.org>"); 81 MODULE_DESCRIPTION("DECstation Z85C30 serial driver"); 82 MODULE_LICENSE("GPL"); 83 84 85 static char zs_name[] __initdata = "DECstation Z85C30 serial driver version "; 86 static char zs_version[] __initdata = "0.10"; 87 88 /* 89 * It would be nice to dynamically allocate everything that 90 * depends on ZS_NUM_SCCS, so we could support any number of 91 * Z85C30s, but for now... 92 */ 93 #define ZS_NUM_SCCS 2 /* Max # of ZS chips supported. */ 94 #define ZS_NUM_CHAN 2 /* 2 channels per chip. */ 95 #define ZS_CHAN_A 0 /* Index of the channel A. */ 96 #define ZS_CHAN_B 1 /* Index of the channel B. */ 97 #define ZS_CHAN_IO_SIZE 8 /* IOMEM space size. */ 98 #define ZS_CHAN_IO_STRIDE 4 /* Register alignment. */ 99 #define ZS_CHAN_IO_OFFSET 1 /* The SCC resides on the high byte 100 of the 16-bit IOBUS. */ 101 #define ZS_CLOCK 7372800 /* Z85C30 PCLK input clock rate. */ 102 103 #define to_zport(uport) container_of(uport, struct zs_port, port) 104 105 struct zs_parms { 106 resource_size_t scc[ZS_NUM_SCCS]; 107 int irq[ZS_NUM_SCCS]; 108 }; 109 110 static struct zs_scc zs_sccs[ZS_NUM_SCCS]; 111 112 static u8 zs_init_regs[ZS_NUM_REGS] __initdata = { 113 0, /* write 0 */ 114 PAR_SPEC, /* write 1 */ 115 0, /* write 2 */ 116 0, /* write 3 */ 117 X16CLK | SB1, /* write 4 */ 118 0, /* write 5 */ 119 0, 0, 0, /* write 6, 7, 8 */ 120 MIE | DLC | NV, /* write 9 */ 121 NRZ, /* write 10 */ 122 TCBR | RCBR, /* write 11 */ 123 0, 0, /* BRG time constant, write 12 + 13 */ 124 BRSRC | BRENABL, /* write 14 */ 125 0, /* write 15 */ 126 }; 127 128 /* 129 * Debugging. 130 */ 131 #undef ZS_DEBUG_REGS 132 133 134 /* 135 * Reading and writing Z85C30 registers. 136 */ 137 static void recovery_delay(void) 138 { 139 udelay(2); 140 } 141 142 static u8 read_zsreg(struct zs_port *zport, int reg) 143 { 144 void __iomem *control = zport->port.membase + ZS_CHAN_IO_OFFSET; 145 u8 retval; 146 147 if (reg != 0) { 148 writeb(reg & 0xf, control); 149 fast_iob(); 150 recovery_delay(); 151 } 152 retval = readb(control); 153 recovery_delay(); 154 return retval; 155 } 156 157 static void write_zsreg(struct zs_port *zport, int reg, u8 value) 158 { 159 void __iomem *control = zport->port.membase + ZS_CHAN_IO_OFFSET; 160 161 if (reg != 0) { 162 writeb(reg & 0xf, control); 163 fast_iob(); recovery_delay(); 164 } 165 writeb(value, control); 166 fast_iob(); 167 recovery_delay(); 168 return; 169 } 170 171 static u8 read_zsdata(struct zs_port *zport) 172 { 173 void __iomem *data = zport->port.membase + 174 ZS_CHAN_IO_STRIDE + ZS_CHAN_IO_OFFSET; 175 u8 retval; 176 177 retval = readb(data); 178 recovery_delay(); 179 return retval; 180 } 181 182 static void write_zsdata(struct zs_port *zport, u8 value) 183 { 184 void __iomem *data = zport->port.membase + 185 ZS_CHAN_IO_STRIDE + ZS_CHAN_IO_OFFSET; 186 187 writeb(value, data); 188 fast_iob(); 189 recovery_delay(); 190 return; 191 } 192 193 #ifdef ZS_DEBUG_REGS 194 void zs_dump(void) 195 { 196 struct zs_port *zport; 197 int i, j; 198 199 for (i = 0; i < ZS_NUM_SCCS * ZS_NUM_CHAN; i++) { 200 zport = &zs_sccs[i / ZS_NUM_CHAN].zport[i % ZS_NUM_CHAN]; 201 202 if (!zport->scc) 203 continue; 204 205 for (j = 0; j < 16; j++) 206 printk("W%-2d = 0x%02x\t", j, zport->regs[j]); 207 printk("\n"); 208 for (j = 0; j < 16; j++) 209 printk("R%-2d = 0x%02x\t", j, read_zsreg(zport, j)); 210 printk("\n\n"); 211 } 212 } 213 #endif 214 215 216 static void zs_spin_lock_cond_irq(spinlock_t *lock, int irq) 217 { 218 if (irq) 219 spin_lock_irq(lock); 220 else 221 spin_lock(lock); 222 } 223 224 static void zs_spin_unlock_cond_irq(spinlock_t *lock, int irq) 225 { 226 if (irq) 227 spin_unlock_irq(lock); 228 else 229 spin_unlock(lock); 230 } 231 232 static int zs_receive_drain(struct zs_port *zport) 233 { 234 int loops = 10000; 235 236 while ((read_zsreg(zport, R0) & Rx_CH_AV) && --loops) 237 read_zsdata(zport); 238 return loops; 239 } 240 241 static int zs_transmit_drain(struct zs_port *zport, int irq) 242 { 243 struct zs_scc *scc = zport->scc; 244 int loops = 10000; 245 246 while (!(read_zsreg(zport, R0) & Tx_BUF_EMP) && --loops) { 247 zs_spin_unlock_cond_irq(&scc->zlock, irq); 248 udelay(2); 249 zs_spin_lock_cond_irq(&scc->zlock, irq); 250 } 251 return loops; 252 } 253 254 static int zs_line_drain(struct zs_port *zport, int irq) 255 { 256 struct zs_scc *scc = zport->scc; 257 int loops = 10000; 258 259 while (!(read_zsreg(zport, R1) & ALL_SNT) && --loops) { 260 zs_spin_unlock_cond_irq(&scc->zlock, irq); 261 udelay(2); 262 zs_spin_lock_cond_irq(&scc->zlock, irq); 263 } 264 return loops; 265 } 266 267 268 static void load_zsregs(struct zs_port *zport, u8 *regs, int irq) 269 { 270 /* Let the current transmission finish. */ 271 zs_line_drain(zport, irq); 272 /* Load 'em up. */ 273 write_zsreg(zport, R3, regs[3] & ~RxENABLE); 274 write_zsreg(zport, R5, regs[5] & ~TxENAB); 275 write_zsreg(zport, R4, regs[4]); 276 write_zsreg(zport, R9, regs[9]); 277 write_zsreg(zport, R1, regs[1]); 278 write_zsreg(zport, R2, regs[2]); 279 write_zsreg(zport, R10, regs[10]); 280 write_zsreg(zport, R14, regs[14] & ~BRENABL); 281 write_zsreg(zport, R11, regs[11]); 282 write_zsreg(zport, R12, regs[12]); 283 write_zsreg(zport, R13, regs[13]); 284 write_zsreg(zport, R14, regs[14]); 285 write_zsreg(zport, R15, regs[15]); 286 if (regs[3] & RxENABLE) 287 write_zsreg(zport, R3, regs[3]); 288 if (regs[5] & TxENAB) 289 write_zsreg(zport, R5, regs[5]); 290 return; 291 } 292 293 294 /* 295 * Status handling routines. 296 */ 297 298 /* 299 * zs_tx_empty() -- get the transmitter empty status 300 * 301 * Purpose: Let user call ioctl() to get info when the UART physically 302 * is emptied. On bus types like RS485, the transmitter must 303 * release the bus after transmitting. This must be done when 304 * the transmit shift register is empty, not be done when the 305 * transmit holding register is empty. This functionality 306 * allows an RS485 driver to be written in user space. 307 */ 308 static unsigned int zs_tx_empty(struct uart_port *uport) 309 { 310 struct zs_port *zport = to_zport(uport); 311 struct zs_scc *scc = zport->scc; 312 unsigned long flags; 313 u8 status; 314 315 spin_lock_irqsave(&scc->zlock, flags); 316 status = read_zsreg(zport, R1); 317 spin_unlock_irqrestore(&scc->zlock, flags); 318 319 return status & ALL_SNT ? TIOCSER_TEMT : 0; 320 } 321 322 static unsigned int zs_raw_get_ab_mctrl(struct zs_port *zport_a, 323 struct zs_port *zport_b) 324 { 325 u8 status_a, status_b; 326 unsigned int mctrl; 327 328 status_a = read_zsreg(zport_a, R0); 329 status_b = read_zsreg(zport_b, R0); 330 331 mctrl = ((status_b & CTS) ? TIOCM_CTS : 0) | 332 ((status_b & DCD) ? TIOCM_CAR : 0) | 333 ((status_a & DCD) ? TIOCM_RNG : 0) | 334 ((status_a & SYNC_HUNT) ? TIOCM_DSR : 0); 335 336 return mctrl; 337 } 338 339 static unsigned int zs_raw_get_mctrl(struct zs_port *zport) 340 { 341 struct zs_port *zport_a = &zport->scc->zport[ZS_CHAN_A]; 342 343 return zport != zport_a ? zs_raw_get_ab_mctrl(zport_a, zport) : 0; 344 } 345 346 static unsigned int zs_raw_xor_mctrl(struct zs_port *zport) 347 { 348 struct zs_port *zport_a = &zport->scc->zport[ZS_CHAN_A]; 349 unsigned int mmask, mctrl, delta; 350 u8 mask_a, mask_b; 351 352 if (zport == zport_a) 353 return 0; 354 355 mask_a = zport_a->regs[15]; 356 mask_b = zport->regs[15]; 357 358 mmask = ((mask_b & CTSIE) ? TIOCM_CTS : 0) | 359 ((mask_b & DCDIE) ? TIOCM_CAR : 0) | 360 ((mask_a & DCDIE) ? TIOCM_RNG : 0) | 361 ((mask_a & SYNCIE) ? TIOCM_DSR : 0); 362 363 mctrl = zport->mctrl; 364 if (mmask) { 365 mctrl &= ~mmask; 366 mctrl |= zs_raw_get_ab_mctrl(zport_a, zport) & mmask; 367 } 368 369 delta = mctrl ^ zport->mctrl; 370 if (delta) 371 zport->mctrl = mctrl; 372 373 return delta; 374 } 375 376 static unsigned int zs_get_mctrl(struct uart_port *uport) 377 { 378 struct zs_port *zport = to_zport(uport); 379 struct zs_scc *scc = zport->scc; 380 unsigned int mctrl; 381 382 spin_lock(&scc->zlock); 383 mctrl = zs_raw_get_mctrl(zport); 384 spin_unlock(&scc->zlock); 385 386 return mctrl; 387 } 388 389 static void zs_set_mctrl(struct uart_port *uport, unsigned int mctrl) 390 { 391 struct zs_port *zport = to_zport(uport); 392 struct zs_scc *scc = zport->scc; 393 struct zs_port *zport_a = &scc->zport[ZS_CHAN_A]; 394 u8 oldloop, newloop; 395 396 spin_lock(&scc->zlock); 397 if (zport != zport_a) { 398 if (mctrl & TIOCM_DTR) 399 zport_a->regs[5] |= DTR; 400 else 401 zport_a->regs[5] &= ~DTR; 402 if (mctrl & TIOCM_RTS) 403 zport_a->regs[5] |= RTS; 404 else 405 zport_a->regs[5] &= ~RTS; 406 write_zsreg(zport_a, R5, zport_a->regs[5]); 407 } 408 409 /* Rarely modified, so don't poke at hardware unless necessary. */ 410 oldloop = zport->regs[14]; 411 newloop = oldloop; 412 if (mctrl & TIOCM_LOOP) 413 newloop |= LOOPBAK; 414 else 415 newloop &= ~LOOPBAK; 416 if (newloop != oldloop) { 417 zport->regs[14] = newloop; 418 write_zsreg(zport, R14, zport->regs[14]); 419 } 420 spin_unlock(&scc->zlock); 421 } 422 423 static void zs_raw_stop_tx(struct zs_port *zport) 424 { 425 write_zsreg(zport, R0, RES_Tx_P); 426 zport->tx_stopped = 1; 427 } 428 429 static void zs_stop_tx(struct uart_port *uport) 430 { 431 struct zs_port *zport = to_zport(uport); 432 struct zs_scc *scc = zport->scc; 433 434 spin_lock(&scc->zlock); 435 zs_raw_stop_tx(zport); 436 spin_unlock(&scc->zlock); 437 } 438 439 static void zs_raw_transmit_chars(struct zs_port *); 440 441 static void zs_start_tx(struct uart_port *uport) 442 { 443 struct zs_port *zport = to_zport(uport); 444 struct zs_scc *scc = zport->scc; 445 446 spin_lock(&scc->zlock); 447 if (zport->tx_stopped) { 448 zs_transmit_drain(zport, 0); 449 zport->tx_stopped = 0; 450 zs_raw_transmit_chars(zport); 451 } 452 spin_unlock(&scc->zlock); 453 } 454 455 static void zs_stop_rx(struct uart_port *uport) 456 { 457 struct zs_port *zport = to_zport(uport); 458 struct zs_scc *scc = zport->scc; 459 struct zs_port *zport_a = &scc->zport[ZS_CHAN_A]; 460 461 spin_lock(&scc->zlock); 462 zport->regs[15] &= ~BRKIE; 463 zport->regs[1] &= ~(RxINT_MASK | TxINT_ENAB); 464 zport->regs[1] |= RxINT_DISAB; 465 466 if (zport != zport_a) { 467 /* A-side DCD tracks RI and SYNC tracks DSR. */ 468 zport_a->regs[15] &= ~(DCDIE | SYNCIE); 469 write_zsreg(zport_a, R15, zport_a->regs[15]); 470 if (!(zport_a->regs[15] & BRKIE)) { 471 zport_a->regs[1] &= ~EXT_INT_ENAB; 472 write_zsreg(zport_a, R1, zport_a->regs[1]); 473 } 474 475 /* This-side DCD tracks DCD and CTS tracks CTS. */ 476 zport->regs[15] &= ~(DCDIE | CTSIE); 477 zport->regs[1] &= ~EXT_INT_ENAB; 478 } else { 479 /* DCD tracks RI and SYNC tracks DSR for the B side. */ 480 if (!(zport->regs[15] & (DCDIE | SYNCIE))) 481 zport->regs[1] &= ~EXT_INT_ENAB; 482 } 483 484 write_zsreg(zport, R15, zport->regs[15]); 485 write_zsreg(zport, R1, zport->regs[1]); 486 spin_unlock(&scc->zlock); 487 } 488 489 static void zs_enable_ms(struct uart_port *uport) 490 { 491 struct zs_port *zport = to_zport(uport); 492 struct zs_scc *scc = zport->scc; 493 struct zs_port *zport_a = &scc->zport[ZS_CHAN_A]; 494 495 if (zport == zport_a) 496 return; 497 498 spin_lock(&scc->zlock); 499 500 /* Clear Ext interrupts if not being handled already. */ 501 if (!(zport_a->regs[1] & EXT_INT_ENAB)) 502 write_zsreg(zport_a, R0, RES_EXT_INT); 503 504 /* A-side DCD tracks RI and SYNC tracks DSR. */ 505 zport_a->regs[1] |= EXT_INT_ENAB; 506 zport_a->regs[15] |= DCDIE | SYNCIE; 507 508 /* This-side DCD tracks DCD and CTS tracks CTS. */ 509 zport->regs[15] |= DCDIE | CTSIE; 510 511 zs_raw_xor_mctrl(zport); 512 513 write_zsreg(zport_a, R1, zport_a->regs[1]); 514 write_zsreg(zport_a, R15, zport_a->regs[15]); 515 write_zsreg(zport, R15, zport->regs[15]); 516 spin_unlock(&scc->zlock); 517 } 518 519 static void zs_break_ctl(struct uart_port *uport, int break_state) 520 { 521 struct zs_port *zport = to_zport(uport); 522 struct zs_scc *scc = zport->scc; 523 unsigned long flags; 524 525 spin_lock_irqsave(&scc->zlock, flags); 526 if (break_state == -1) 527 zport->regs[5] |= SND_BRK; 528 else 529 zport->regs[5] &= ~SND_BRK; 530 write_zsreg(zport, R5, zport->regs[5]); 531 spin_unlock_irqrestore(&scc->zlock, flags); 532 } 533 534 535 /* 536 * Interrupt handling routines. 537 */ 538 #define Rx_BRK 0x0100 /* BREAK event software flag. */ 539 #define Rx_SYS 0x0200 /* SysRq event software flag. */ 540 541 static void zs_receive_chars(struct zs_port *zport) 542 { 543 struct uart_port *uport = &zport->port; 544 struct zs_scc *scc = zport->scc; 545 struct uart_icount *icount; 546 unsigned int avail, status, ch, flag; 547 int count; 548 549 for (count = 16; count; count--) { 550 spin_lock(&scc->zlock); 551 avail = read_zsreg(zport, R0) & Rx_CH_AV; 552 spin_unlock(&scc->zlock); 553 if (!avail) 554 break; 555 556 spin_lock(&scc->zlock); 557 status = read_zsreg(zport, R1) & (Rx_OVR | FRM_ERR | PAR_ERR); 558 ch = read_zsdata(zport); 559 spin_unlock(&scc->zlock); 560 561 flag = TTY_NORMAL; 562 563 icount = &uport->icount; 564 icount->rx++; 565 566 /* Handle the null char got when BREAK is removed. */ 567 if (!ch) 568 status |= zport->tty_break; 569 if (unlikely(status & 570 (Rx_OVR | FRM_ERR | PAR_ERR | Rx_SYS | Rx_BRK))) { 571 zport->tty_break = 0; 572 573 /* Reset the error indication. */ 574 if (status & (Rx_OVR | FRM_ERR | PAR_ERR)) { 575 spin_lock(&scc->zlock); 576 write_zsreg(zport, R0, ERR_RES); 577 spin_unlock(&scc->zlock); 578 } 579 580 if (status & (Rx_SYS | Rx_BRK)) { 581 icount->brk++; 582 /* SysRq discards the null char. */ 583 if (status & Rx_SYS) 584 continue; 585 } else if (status & FRM_ERR) 586 icount->frame++; 587 else if (status & PAR_ERR) 588 icount->parity++; 589 if (status & Rx_OVR) 590 icount->overrun++; 591 592 status &= uport->read_status_mask; 593 if (status & Rx_BRK) 594 flag = TTY_BREAK; 595 else if (status & FRM_ERR) 596 flag = TTY_FRAME; 597 else if (status & PAR_ERR) 598 flag = TTY_PARITY; 599 } 600 601 if (uart_handle_sysrq_char(uport, ch)) 602 continue; 603 604 uart_insert_char(uport, status, Rx_OVR, ch, flag); 605 } 606 607 tty_flip_buffer_push(&uport->state->port); 608 } 609 610 static void zs_raw_transmit_chars(struct zs_port *zport) 611 { 612 struct circ_buf *xmit = &zport->port.state->xmit; 613 614 /* XON/XOFF chars. */ 615 if (zport->port.x_char) { 616 write_zsdata(zport, zport->port.x_char); 617 zport->port.icount.tx++; 618 zport->port.x_char = 0; 619 return; 620 } 621 622 /* If nothing to do or stopped or hardware stopped. */ 623 if (uart_circ_empty(xmit) || uart_tx_stopped(&zport->port)) { 624 zs_raw_stop_tx(zport); 625 return; 626 } 627 628 /* Send char. */ 629 write_zsdata(zport, xmit->buf[xmit->tail]); 630 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 631 zport->port.icount.tx++; 632 633 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 634 uart_write_wakeup(&zport->port); 635 636 /* Are we are done? */ 637 if (uart_circ_empty(xmit)) 638 zs_raw_stop_tx(zport); 639 } 640 641 static void zs_transmit_chars(struct zs_port *zport) 642 { 643 struct zs_scc *scc = zport->scc; 644 645 spin_lock(&scc->zlock); 646 zs_raw_transmit_chars(zport); 647 spin_unlock(&scc->zlock); 648 } 649 650 static void zs_status_handle(struct zs_port *zport, struct zs_port *zport_a) 651 { 652 struct uart_port *uport = &zport->port; 653 struct zs_scc *scc = zport->scc; 654 unsigned int delta; 655 u8 status, brk; 656 657 spin_lock(&scc->zlock); 658 659 /* Get status from Read Register 0. */ 660 status = read_zsreg(zport, R0); 661 662 if (zport->regs[15] & BRKIE) { 663 brk = status & BRK_ABRT; 664 if (brk && !zport->brk) { 665 spin_unlock(&scc->zlock); 666 if (uart_handle_break(uport)) 667 zport->tty_break = Rx_SYS; 668 else 669 zport->tty_break = Rx_BRK; 670 spin_lock(&scc->zlock); 671 } 672 zport->brk = brk; 673 } 674 675 if (zport != zport_a) { 676 delta = zs_raw_xor_mctrl(zport); 677 spin_unlock(&scc->zlock); 678 679 if (delta & TIOCM_CTS) 680 uart_handle_cts_change(uport, 681 zport->mctrl & TIOCM_CTS); 682 if (delta & TIOCM_CAR) 683 uart_handle_dcd_change(uport, 684 zport->mctrl & TIOCM_CAR); 685 if (delta & TIOCM_RNG) 686 uport->icount.dsr++; 687 if (delta & TIOCM_DSR) 688 uport->icount.rng++; 689 690 if (delta) 691 wake_up_interruptible(&uport->state->port.delta_msr_wait); 692 693 spin_lock(&scc->zlock); 694 } 695 696 /* Clear the status condition... */ 697 write_zsreg(zport, R0, RES_EXT_INT); 698 699 spin_unlock(&scc->zlock); 700 } 701 702 /* 703 * This is the Z85C30 driver's generic interrupt routine. 704 */ 705 static irqreturn_t zs_interrupt(int irq, void *dev_id) 706 { 707 struct zs_scc *scc = dev_id; 708 struct zs_port *zport_a = &scc->zport[ZS_CHAN_A]; 709 struct zs_port *zport_b = &scc->zport[ZS_CHAN_B]; 710 irqreturn_t status = IRQ_NONE; 711 u8 zs_intreg; 712 int count; 713 714 /* 715 * NOTE: The read register 3, which holds the irq status, 716 * does so for both channels on each chip. Although 717 * the status value itself must be read from the A 718 * channel and is only valid when read from channel A. 719 * Yes... broken hardware... 720 */ 721 for (count = 16; count; count--) { 722 spin_lock(&scc->zlock); 723 zs_intreg = read_zsreg(zport_a, R3); 724 spin_unlock(&scc->zlock); 725 if (!zs_intreg) 726 break; 727 728 /* 729 * We do not like losing characters, so we prioritise 730 * interrupt sources a little bit differently than 731 * the SCC would, was it allowed to. 732 */ 733 if (zs_intreg & CHBRxIP) 734 zs_receive_chars(zport_b); 735 if (zs_intreg & CHARxIP) 736 zs_receive_chars(zport_a); 737 if (zs_intreg & CHBEXT) 738 zs_status_handle(zport_b, zport_a); 739 if (zs_intreg & CHAEXT) 740 zs_status_handle(zport_a, zport_a); 741 if (zs_intreg & CHBTxIP) 742 zs_transmit_chars(zport_b); 743 if (zs_intreg & CHATxIP) 744 zs_transmit_chars(zport_a); 745 746 status = IRQ_HANDLED; 747 } 748 749 return status; 750 } 751 752 753 /* 754 * Finally, routines used to initialize the serial port. 755 */ 756 static int zs_startup(struct uart_port *uport) 757 { 758 struct zs_port *zport = to_zport(uport); 759 struct zs_scc *scc = zport->scc; 760 unsigned long flags; 761 int irq_guard; 762 int ret; 763 764 irq_guard = atomic_add_return(1, &scc->irq_guard); 765 if (irq_guard == 1) { 766 ret = request_irq(zport->port.irq, zs_interrupt, 767 IRQF_SHARED, "scc", scc); 768 if (ret) { 769 atomic_add(-1, &scc->irq_guard); 770 printk(KERN_ERR "zs: can't get irq %d\n", 771 zport->port.irq); 772 return ret; 773 } 774 } 775 776 spin_lock_irqsave(&scc->zlock, flags); 777 778 /* Clear the receive FIFO. */ 779 zs_receive_drain(zport); 780 781 /* Clear the interrupt registers. */ 782 write_zsreg(zport, R0, ERR_RES); 783 write_zsreg(zport, R0, RES_Tx_P); 784 /* But Ext only if not being handled already. */ 785 if (!(zport->regs[1] & EXT_INT_ENAB)) 786 write_zsreg(zport, R0, RES_EXT_INT); 787 788 /* Finally, enable sequencing and interrupts. */ 789 zport->regs[1] &= ~RxINT_MASK; 790 zport->regs[1] |= RxINT_ALL | TxINT_ENAB | EXT_INT_ENAB; 791 zport->regs[3] |= RxENABLE; 792 zport->regs[15] |= BRKIE; 793 write_zsreg(zport, R1, zport->regs[1]); 794 write_zsreg(zport, R3, zport->regs[3]); 795 write_zsreg(zport, R5, zport->regs[5]); 796 write_zsreg(zport, R15, zport->regs[15]); 797 798 /* Record the current state of RR0. */ 799 zport->mctrl = zs_raw_get_mctrl(zport); 800 zport->brk = read_zsreg(zport, R0) & BRK_ABRT; 801 802 zport->tx_stopped = 1; 803 804 spin_unlock_irqrestore(&scc->zlock, flags); 805 806 return 0; 807 } 808 809 static void zs_shutdown(struct uart_port *uport) 810 { 811 struct zs_port *zport = to_zport(uport); 812 struct zs_scc *scc = zport->scc; 813 unsigned long flags; 814 int irq_guard; 815 816 spin_lock_irqsave(&scc->zlock, flags); 817 818 zport->regs[3] &= ~RxENABLE; 819 write_zsreg(zport, R5, zport->regs[5]); 820 write_zsreg(zport, R3, zport->regs[3]); 821 822 spin_unlock_irqrestore(&scc->zlock, flags); 823 824 irq_guard = atomic_add_return(-1, &scc->irq_guard); 825 if (!irq_guard) 826 free_irq(zport->port.irq, scc); 827 } 828 829 830 static void zs_reset(struct zs_port *zport) 831 { 832 struct zs_scc *scc = zport->scc; 833 int irq; 834 unsigned long flags; 835 836 spin_lock_irqsave(&scc->zlock, flags); 837 irq = !irqs_disabled_flags(flags); 838 if (!scc->initialised) { 839 /* Reset the pointer first, just in case... */ 840 read_zsreg(zport, R0); 841 /* And let the current transmission finish. */ 842 zs_line_drain(zport, irq); 843 write_zsreg(zport, R9, FHWRES); 844 udelay(10); 845 write_zsreg(zport, R9, 0); 846 scc->initialised = 1; 847 } 848 load_zsregs(zport, zport->regs, irq); 849 spin_unlock_irqrestore(&scc->zlock, flags); 850 } 851 852 static void zs_set_termios(struct uart_port *uport, struct ktermios *termios, 853 struct ktermios *old_termios) 854 { 855 struct zs_port *zport = to_zport(uport); 856 struct zs_scc *scc = zport->scc; 857 struct zs_port *zport_a = &scc->zport[ZS_CHAN_A]; 858 int irq; 859 unsigned int baud, brg; 860 unsigned long flags; 861 862 spin_lock_irqsave(&scc->zlock, flags); 863 irq = !irqs_disabled_flags(flags); 864 865 /* Byte size. */ 866 zport->regs[3] &= ~RxNBITS_MASK; 867 zport->regs[5] &= ~TxNBITS_MASK; 868 switch (termios->c_cflag & CSIZE) { 869 case CS5: 870 zport->regs[3] |= Rx5; 871 zport->regs[5] |= Tx5; 872 break; 873 case CS6: 874 zport->regs[3] |= Rx6; 875 zport->regs[5] |= Tx6; 876 break; 877 case CS7: 878 zport->regs[3] |= Rx7; 879 zport->regs[5] |= Tx7; 880 break; 881 case CS8: 882 default: 883 zport->regs[3] |= Rx8; 884 zport->regs[5] |= Tx8; 885 break; 886 } 887 888 /* Parity and stop bits. */ 889 zport->regs[4] &= ~(XCLK_MASK | SB_MASK | PAR_ENA | PAR_EVEN); 890 if (termios->c_cflag & CSTOPB) 891 zport->regs[4] |= SB2; 892 else 893 zport->regs[4] |= SB1; 894 if (termios->c_cflag & PARENB) 895 zport->regs[4] |= PAR_ENA; 896 if (!(termios->c_cflag & PARODD)) 897 zport->regs[4] |= PAR_EVEN; 898 switch (zport->clk_mode) { 899 case 64: 900 zport->regs[4] |= X64CLK; 901 break; 902 case 32: 903 zport->regs[4] |= X32CLK; 904 break; 905 case 16: 906 zport->regs[4] |= X16CLK; 907 break; 908 case 1: 909 zport->regs[4] |= X1CLK; 910 break; 911 default: 912 BUG(); 913 } 914 915 baud = uart_get_baud_rate(uport, termios, old_termios, 0, 916 uport->uartclk / zport->clk_mode / 4); 917 918 brg = ZS_BPS_TO_BRG(baud, uport->uartclk / zport->clk_mode); 919 zport->regs[12] = brg & 0xff; 920 zport->regs[13] = (brg >> 8) & 0xff; 921 922 uart_update_timeout(uport, termios->c_cflag, baud); 923 924 uport->read_status_mask = Rx_OVR; 925 if (termios->c_iflag & INPCK) 926 uport->read_status_mask |= FRM_ERR | PAR_ERR; 927 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 928 uport->read_status_mask |= Rx_BRK; 929 930 uport->ignore_status_mask = 0; 931 if (termios->c_iflag & IGNPAR) 932 uport->ignore_status_mask |= FRM_ERR | PAR_ERR; 933 if (termios->c_iflag & IGNBRK) { 934 uport->ignore_status_mask |= Rx_BRK; 935 if (termios->c_iflag & IGNPAR) 936 uport->ignore_status_mask |= Rx_OVR; 937 } 938 939 if (termios->c_cflag & CREAD) 940 zport->regs[3] |= RxENABLE; 941 else 942 zport->regs[3] &= ~RxENABLE; 943 944 if (zport != zport_a) { 945 if (!(termios->c_cflag & CLOCAL)) { 946 zport->regs[15] |= DCDIE; 947 } else 948 zport->regs[15] &= ~DCDIE; 949 if (termios->c_cflag & CRTSCTS) { 950 zport->regs[15] |= CTSIE; 951 } else 952 zport->regs[15] &= ~CTSIE; 953 zs_raw_xor_mctrl(zport); 954 } 955 956 /* Load up the new values. */ 957 load_zsregs(zport, zport->regs, irq); 958 959 spin_unlock_irqrestore(&scc->zlock, flags); 960 } 961 962 /* 963 * Hack alert! 964 * Required solely so that the initial PROM-based console 965 * works undisturbed in parallel with this one. 966 */ 967 static void zs_pm(struct uart_port *uport, unsigned int state, 968 unsigned int oldstate) 969 { 970 struct zs_port *zport = to_zport(uport); 971 972 if (state < 3) 973 zport->regs[5] |= TxENAB; 974 else 975 zport->regs[5] &= ~TxENAB; 976 write_zsreg(zport, R5, zport->regs[5]); 977 } 978 979 980 static const char *zs_type(struct uart_port *uport) 981 { 982 return "Z85C30 SCC"; 983 } 984 985 static void zs_release_port(struct uart_port *uport) 986 { 987 iounmap(uport->membase); 988 uport->membase = 0; 989 release_mem_region(uport->mapbase, ZS_CHAN_IO_SIZE); 990 } 991 992 static int zs_map_port(struct uart_port *uport) 993 { 994 if (!uport->membase) 995 uport->membase = ioremap_nocache(uport->mapbase, 996 ZS_CHAN_IO_SIZE); 997 if (!uport->membase) { 998 printk(KERN_ERR "zs: Cannot map MMIO\n"); 999 return -ENOMEM; 1000 } 1001 return 0; 1002 } 1003 1004 static int zs_request_port(struct uart_port *uport) 1005 { 1006 int ret; 1007 1008 if (!request_mem_region(uport->mapbase, ZS_CHAN_IO_SIZE, "scc")) { 1009 printk(KERN_ERR "zs: Unable to reserve MMIO resource\n"); 1010 return -EBUSY; 1011 } 1012 ret = zs_map_port(uport); 1013 if (ret) { 1014 release_mem_region(uport->mapbase, ZS_CHAN_IO_SIZE); 1015 return ret; 1016 } 1017 return 0; 1018 } 1019 1020 static void zs_config_port(struct uart_port *uport, int flags) 1021 { 1022 struct zs_port *zport = to_zport(uport); 1023 1024 if (flags & UART_CONFIG_TYPE) { 1025 if (zs_request_port(uport)) 1026 return; 1027 1028 uport->type = PORT_ZS; 1029 1030 zs_reset(zport); 1031 } 1032 } 1033 1034 static int zs_verify_port(struct uart_port *uport, struct serial_struct *ser) 1035 { 1036 struct zs_port *zport = to_zport(uport); 1037 int ret = 0; 1038 1039 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ZS) 1040 ret = -EINVAL; 1041 if (ser->irq != uport->irq) 1042 ret = -EINVAL; 1043 if (ser->baud_base != uport->uartclk / zport->clk_mode / 4) 1044 ret = -EINVAL; 1045 return ret; 1046 } 1047 1048 1049 static const struct uart_ops zs_ops = { 1050 .tx_empty = zs_tx_empty, 1051 .set_mctrl = zs_set_mctrl, 1052 .get_mctrl = zs_get_mctrl, 1053 .stop_tx = zs_stop_tx, 1054 .start_tx = zs_start_tx, 1055 .stop_rx = zs_stop_rx, 1056 .enable_ms = zs_enable_ms, 1057 .break_ctl = zs_break_ctl, 1058 .startup = zs_startup, 1059 .shutdown = zs_shutdown, 1060 .set_termios = zs_set_termios, 1061 .pm = zs_pm, 1062 .type = zs_type, 1063 .release_port = zs_release_port, 1064 .request_port = zs_request_port, 1065 .config_port = zs_config_port, 1066 .verify_port = zs_verify_port, 1067 }; 1068 1069 /* 1070 * Initialize Z85C30 port structures. 1071 */ 1072 static int __init zs_probe_sccs(void) 1073 { 1074 static int probed; 1075 struct zs_parms zs_parms; 1076 int chip, side, irq; 1077 int n_chips = 0; 1078 int i; 1079 1080 if (probed) 1081 return 0; 1082 1083 irq = dec_interrupt[DEC_IRQ_SCC0]; 1084 if (irq >= 0) { 1085 zs_parms.scc[n_chips] = IOASIC_SCC0; 1086 zs_parms.irq[n_chips] = dec_interrupt[DEC_IRQ_SCC0]; 1087 n_chips++; 1088 } 1089 irq = dec_interrupt[DEC_IRQ_SCC1]; 1090 if (irq >= 0) { 1091 zs_parms.scc[n_chips] = IOASIC_SCC1; 1092 zs_parms.irq[n_chips] = dec_interrupt[DEC_IRQ_SCC1]; 1093 n_chips++; 1094 } 1095 if (!n_chips) 1096 return -ENXIO; 1097 1098 probed = 1; 1099 1100 for (chip = 0; chip < n_chips; chip++) { 1101 spin_lock_init(&zs_sccs[chip].zlock); 1102 for (side = 0; side < ZS_NUM_CHAN; side++) { 1103 struct zs_port *zport = &zs_sccs[chip].zport[side]; 1104 struct uart_port *uport = &zport->port; 1105 1106 zport->scc = &zs_sccs[chip]; 1107 zport->clk_mode = 16; 1108 1109 uport->irq = zs_parms.irq[chip]; 1110 uport->uartclk = ZS_CLOCK; 1111 uport->fifosize = 1; 1112 uport->iotype = UPIO_MEM; 1113 uport->flags = UPF_BOOT_AUTOCONF; 1114 uport->ops = &zs_ops; 1115 uport->line = chip * ZS_NUM_CHAN + side; 1116 uport->mapbase = dec_kn_slot_base + 1117 zs_parms.scc[chip] + 1118 (side ^ ZS_CHAN_B) * ZS_CHAN_IO_SIZE; 1119 1120 for (i = 0; i < ZS_NUM_REGS; i++) 1121 zport->regs[i] = zs_init_regs[i]; 1122 } 1123 } 1124 1125 return 0; 1126 } 1127 1128 1129 #ifdef CONFIG_SERIAL_ZS_CONSOLE 1130 static void zs_console_putchar(struct uart_port *uport, int ch) 1131 { 1132 struct zs_port *zport = to_zport(uport); 1133 struct zs_scc *scc = zport->scc; 1134 int irq; 1135 unsigned long flags; 1136 1137 spin_lock_irqsave(&scc->zlock, flags); 1138 irq = !irqs_disabled_flags(flags); 1139 if (zs_transmit_drain(zport, irq)) 1140 write_zsdata(zport, ch); 1141 spin_unlock_irqrestore(&scc->zlock, flags); 1142 } 1143 1144 /* 1145 * Print a string to the serial port trying not to disturb 1146 * any possible real use of the port... 1147 */ 1148 static void zs_console_write(struct console *co, const char *s, 1149 unsigned int count) 1150 { 1151 int chip = co->index / ZS_NUM_CHAN, side = co->index % ZS_NUM_CHAN; 1152 struct zs_port *zport = &zs_sccs[chip].zport[side]; 1153 struct zs_scc *scc = zport->scc; 1154 unsigned long flags; 1155 u8 txint, txenb; 1156 int irq; 1157 1158 /* Disable transmit interrupts and enable the transmitter. */ 1159 spin_lock_irqsave(&scc->zlock, flags); 1160 txint = zport->regs[1]; 1161 txenb = zport->regs[5]; 1162 if (txint & TxINT_ENAB) { 1163 zport->regs[1] = txint & ~TxINT_ENAB; 1164 write_zsreg(zport, R1, zport->regs[1]); 1165 } 1166 if (!(txenb & TxENAB)) { 1167 zport->regs[5] = txenb | TxENAB; 1168 write_zsreg(zport, R5, zport->regs[5]); 1169 } 1170 spin_unlock_irqrestore(&scc->zlock, flags); 1171 1172 uart_console_write(&zport->port, s, count, zs_console_putchar); 1173 1174 /* Restore transmit interrupts and the transmitter enable. */ 1175 spin_lock_irqsave(&scc->zlock, flags); 1176 irq = !irqs_disabled_flags(flags); 1177 zs_line_drain(zport, irq); 1178 if (!(txenb & TxENAB)) { 1179 zport->regs[5] &= ~TxENAB; 1180 write_zsreg(zport, R5, zport->regs[5]); 1181 } 1182 if (txint & TxINT_ENAB) { 1183 zport->regs[1] |= TxINT_ENAB; 1184 write_zsreg(zport, R1, zport->regs[1]); 1185 1186 /* Resume any transmission as the TxIP bit won't be set. */ 1187 if (!zport->tx_stopped) 1188 zs_raw_transmit_chars(zport); 1189 } 1190 spin_unlock_irqrestore(&scc->zlock, flags); 1191 } 1192 1193 /* 1194 * Setup serial console baud/bits/parity. We do two things here: 1195 * - construct a cflag setting for the first uart_open() 1196 * - initialise the serial port 1197 * Return non-zero if we didn't find a serial port. 1198 */ 1199 static int __init zs_console_setup(struct console *co, char *options) 1200 { 1201 int chip = co->index / ZS_NUM_CHAN, side = co->index % ZS_NUM_CHAN; 1202 struct zs_port *zport = &zs_sccs[chip].zport[side]; 1203 struct uart_port *uport = &zport->port; 1204 int baud = 9600; 1205 int bits = 8; 1206 int parity = 'n'; 1207 int flow = 'n'; 1208 int ret; 1209 1210 ret = zs_map_port(uport); 1211 if (ret) 1212 return ret; 1213 1214 zs_reset(zport); 1215 zs_pm(uport, 0, -1); 1216 1217 if (options) 1218 uart_parse_options(options, &baud, &parity, &bits, &flow); 1219 return uart_set_options(uport, co, baud, parity, bits, flow); 1220 } 1221 1222 static struct uart_driver zs_reg; 1223 static struct console zs_console = { 1224 .name = "ttyS", 1225 .write = zs_console_write, 1226 .device = uart_console_device, 1227 .setup = zs_console_setup, 1228 .flags = CON_PRINTBUFFER, 1229 .index = -1, 1230 .data = &zs_reg, 1231 }; 1232 1233 /* 1234 * Register console. 1235 */ 1236 static int __init zs_serial_console_init(void) 1237 { 1238 int ret; 1239 1240 ret = zs_probe_sccs(); 1241 if (ret) 1242 return ret; 1243 register_console(&zs_console); 1244 1245 return 0; 1246 } 1247 1248 console_initcall(zs_serial_console_init); 1249 1250 #define SERIAL_ZS_CONSOLE &zs_console 1251 #else 1252 #define SERIAL_ZS_CONSOLE NULL 1253 #endif /* CONFIG_SERIAL_ZS_CONSOLE */ 1254 1255 static struct uart_driver zs_reg = { 1256 .owner = THIS_MODULE, 1257 .driver_name = "serial", 1258 .dev_name = "ttyS", 1259 .major = TTY_MAJOR, 1260 .minor = 64, 1261 .nr = ZS_NUM_SCCS * ZS_NUM_CHAN, 1262 .cons = SERIAL_ZS_CONSOLE, 1263 }; 1264 1265 /* zs_init inits the driver. */ 1266 static int __init zs_init(void) 1267 { 1268 int i, ret; 1269 1270 pr_info("%s%s\n", zs_name, zs_version); 1271 1272 /* Find out how many Z85C30 SCCs we have. */ 1273 ret = zs_probe_sccs(); 1274 if (ret) 1275 return ret; 1276 1277 ret = uart_register_driver(&zs_reg); 1278 if (ret) 1279 return ret; 1280 1281 for (i = 0; i < ZS_NUM_SCCS * ZS_NUM_CHAN; i++) { 1282 struct zs_scc *scc = &zs_sccs[i / ZS_NUM_CHAN]; 1283 struct zs_port *zport = &scc->zport[i % ZS_NUM_CHAN]; 1284 struct uart_port *uport = &zport->port; 1285 1286 if (zport->scc) 1287 uart_add_one_port(&zs_reg, uport); 1288 } 1289 1290 return 0; 1291 } 1292 1293 static void __exit zs_exit(void) 1294 { 1295 int i; 1296 1297 for (i = ZS_NUM_SCCS * ZS_NUM_CHAN - 1; i >= 0; i--) { 1298 struct zs_scc *scc = &zs_sccs[i / ZS_NUM_CHAN]; 1299 struct zs_port *zport = &scc->zport[i % ZS_NUM_CHAN]; 1300 struct uart_port *uport = &zport->port; 1301 1302 if (zport->scc) 1303 uart_remove_one_port(&zs_reg, uport); 1304 } 1305 1306 uart_unregister_driver(&zs_reg); 1307 } 1308 1309 module_init(zs_init); 1310 module_exit(zs_exit); 1311