1 /* 2 * Cadence UART driver (found in Xilinx Zynq) 3 * 4 * 2011 - 2014 (C) Xilinx Inc. 5 * 6 * This program is free software; you can redistribute it 7 * and/or modify it under the terms of the GNU General Public 8 * License as published by the Free Software Foundation; 9 * either version 2 of the License, or (at your option) any 10 * later version. 11 * 12 * This driver has originally been pushed by Xilinx using a Zynq-branding. This 13 * still shows in the naming of this file, the kconfig symbols and some symbols 14 * in the code. 15 */ 16 17 #if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 18 #define SUPPORT_SYSRQ 19 #endif 20 21 #include <linux/platform_device.h> 22 #include <linux/serial.h> 23 #include <linux/console.h> 24 #include <linux/serial_core.h> 25 #include <linux/slab.h> 26 #include <linux/tty.h> 27 #include <linux/tty_flip.h> 28 #include <linux/clk.h> 29 #include <linux/irq.h> 30 #include <linux/io.h> 31 #include <linux/of.h> 32 #include <linux/module.h> 33 34 #define CDNS_UART_TTY_NAME "ttyPS" 35 #define CDNS_UART_NAME "xuartps" 36 #define CDNS_UART_MAJOR 0 /* use dynamic node allocation */ 37 #define CDNS_UART_MINOR 0 /* works best with devtmpfs */ 38 #define CDNS_UART_NR_PORTS 2 39 #define CDNS_UART_FIFO_SIZE 64 /* FIFO size */ 40 #define CDNS_UART_REGISTER_SPACE 0xFFF 41 42 #define cdns_uart_readl(offset) ioread32(port->membase + offset) 43 #define cdns_uart_writel(val, offset) iowrite32(val, port->membase + offset) 44 45 /* Rx Trigger level */ 46 static int rx_trigger_level = 56; 47 module_param(rx_trigger_level, uint, S_IRUGO); 48 MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes"); 49 50 /* Rx Timeout */ 51 static int rx_timeout = 10; 52 module_param(rx_timeout, uint, S_IRUGO); 53 MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255"); 54 55 /* Register offsets for the UART. */ 56 #define CDNS_UART_CR_OFFSET 0x00 /* Control Register */ 57 #define CDNS_UART_MR_OFFSET 0x04 /* Mode Register */ 58 #define CDNS_UART_IER_OFFSET 0x08 /* Interrupt Enable */ 59 #define CDNS_UART_IDR_OFFSET 0x0C /* Interrupt Disable */ 60 #define CDNS_UART_IMR_OFFSET 0x10 /* Interrupt Mask */ 61 #define CDNS_UART_ISR_OFFSET 0x14 /* Interrupt Status */ 62 #define CDNS_UART_BAUDGEN_OFFSET 0x18 /* Baud Rate Generator */ 63 #define CDNS_UART_RXTOUT_OFFSET 0x1C /* RX Timeout */ 64 #define CDNS_UART_RXWM_OFFSET 0x20 /* RX FIFO Trigger Level */ 65 #define CDNS_UART_MODEMCR_OFFSET 0x24 /* Modem Control */ 66 #define CDNS_UART_MODEMSR_OFFSET 0x28 /* Modem Status */ 67 #define CDNS_UART_SR_OFFSET 0x2C /* Channel Status */ 68 #define CDNS_UART_FIFO_OFFSET 0x30 /* FIFO */ 69 #define CDNS_UART_BAUDDIV_OFFSET 0x34 /* Baud Rate Divider */ 70 #define CDNS_UART_FLOWDEL_OFFSET 0x38 /* Flow Delay */ 71 #define CDNS_UART_IRRX_PWIDTH_OFFSET 0x3C /* IR Min Received Pulse Width */ 72 #define CDNS_UART_IRTX_PWIDTH_OFFSET 0x40 /* IR Transmitted pulse Width */ 73 #define CDNS_UART_TXWM_OFFSET 0x44 /* TX FIFO Trigger Level */ 74 75 /* Control Register Bit Definitions */ 76 #define CDNS_UART_CR_STOPBRK 0x00000100 /* Stop TX break */ 77 #define CDNS_UART_CR_STARTBRK 0x00000080 /* Set TX break */ 78 #define CDNS_UART_CR_TX_DIS 0x00000020 /* TX disabled. */ 79 #define CDNS_UART_CR_TX_EN 0x00000010 /* TX enabled */ 80 #define CDNS_UART_CR_RX_DIS 0x00000008 /* RX disabled. */ 81 #define CDNS_UART_CR_RX_EN 0x00000004 /* RX enabled */ 82 #define CDNS_UART_CR_TXRST 0x00000002 /* TX logic reset */ 83 #define CDNS_UART_CR_RXRST 0x00000001 /* RX logic reset */ 84 #define CDNS_UART_CR_RST_TO 0x00000040 /* Restart Timeout Counter */ 85 86 /* 87 * Mode Register: 88 * The mode register (MR) defines the mode of transfer as well as the data 89 * format. If this register is modified during transmission or reception, 90 * data validity cannot be guaranteed. 91 */ 92 #define CDNS_UART_MR_CLKSEL 0x00000001 /* Pre-scalar selection */ 93 #define CDNS_UART_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */ 94 #define CDNS_UART_MR_CHMODE_NORM 0x00000000 /* Normal mode */ 95 96 #define CDNS_UART_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */ 97 #define CDNS_UART_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */ 98 99 #define CDNS_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */ 100 #define CDNS_UART_MR_PARITY_MARK 0x00000018 /* Mark parity mode */ 101 #define CDNS_UART_MR_PARITY_SPACE 0x00000010 /* Space parity mode */ 102 #define CDNS_UART_MR_PARITY_ODD 0x00000008 /* Odd parity mode */ 103 #define CDNS_UART_MR_PARITY_EVEN 0x00000000 /* Even parity mode */ 104 105 #define CDNS_UART_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */ 106 #define CDNS_UART_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */ 107 #define CDNS_UART_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */ 108 109 /* 110 * Interrupt Registers: 111 * Interrupt control logic uses the interrupt enable register (IER) and the 112 * interrupt disable register (IDR) to set the value of the bits in the 113 * interrupt mask register (IMR). The IMR determines whether to pass an 114 * interrupt to the interrupt status register (ISR). 115 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an 116 * interrupt. IMR and ISR are read only, and IER and IDR are write only. 117 * Reading either IER or IDR returns 0x00. 118 * All four registers have the same bit definitions. 119 */ 120 #define CDNS_UART_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */ 121 #define CDNS_UART_IXR_PARITY 0x00000080 /* Parity error interrupt */ 122 #define CDNS_UART_IXR_FRAMING 0x00000040 /* Framing error interrupt */ 123 #define CDNS_UART_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */ 124 #define CDNS_UART_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */ 125 #define CDNS_UART_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */ 126 #define CDNS_UART_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */ 127 #define CDNS_UART_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */ 128 #define CDNS_UART_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */ 129 #define CDNS_UART_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */ 130 #define CDNS_UART_IXR_MASK 0x00001FFF /* Valid bit mask */ 131 132 /* Goes in read_status_mask for break detection as the HW doesn't do it*/ 133 #define CDNS_UART_IXR_BRK 0x80000000 134 135 /* 136 * Modem Control register: 137 * The read/write Modem Control register controls the interface with the modem 138 * or data set, or a peripheral device emulating a modem. 139 */ 140 #define CDNS_UART_MODEMCR_FCM 0x00000020 /* Automatic flow control mode */ 141 #define CDNS_UART_MODEMCR_RTS 0x00000002 /* Request to send output control */ 142 #define CDNS_UART_MODEMCR_DTR 0x00000001 /* Data Terminal Ready */ 143 144 /* 145 * Channel Status Register: 146 * The channel status register (CSR) is provided to enable the control logic 147 * to monitor the status of bits in the channel interrupt status register, 148 * even if these are masked out by the interrupt mask register. 149 */ 150 #define CDNS_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */ 151 #define CDNS_UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */ 152 #define CDNS_UART_SR_TXFULL 0x00000010 /* TX FIFO full */ 153 #define CDNS_UART_SR_RXTRIG 0x00000001 /* Rx Trigger */ 154 155 /* baud dividers min/max values */ 156 #define CDNS_UART_BDIV_MIN 4 157 #define CDNS_UART_BDIV_MAX 255 158 #define CDNS_UART_CD_MAX 65535 159 160 /** 161 * struct cdns_uart - device data 162 * @port: Pointer to the UART port 163 * @uartclk: Reference clock 164 * @pclk: APB clock 165 * @baud: Current baud rate 166 * @clk_rate_change_nb: Notifier block for clock changes 167 */ 168 struct cdns_uart { 169 struct uart_port *port; 170 struct clk *uartclk; 171 struct clk *pclk; 172 unsigned int baud; 173 struct notifier_block clk_rate_change_nb; 174 }; 175 #define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \ 176 clk_rate_change_nb); 177 178 /** 179 * cdns_uart_isr - Interrupt handler 180 * @irq: Irq number 181 * @dev_id: Id of the port 182 * 183 * Return: IRQHANDLED 184 */ 185 static irqreturn_t cdns_uart_isr(int irq, void *dev_id) 186 { 187 struct uart_port *port = (struct uart_port *)dev_id; 188 unsigned long flags; 189 unsigned int isrstatus, numbytes; 190 unsigned int data; 191 char status = TTY_NORMAL; 192 193 spin_lock_irqsave(&port->lock, flags); 194 195 /* Read the interrupt status register to determine which 196 * interrupt(s) is/are active. 197 */ 198 isrstatus = cdns_uart_readl(CDNS_UART_ISR_OFFSET); 199 200 /* 201 * There is no hardware break detection, so we interpret framing 202 * error with all-zeros data as a break sequence. Most of the time, 203 * there's another non-zero byte at the end of the sequence. 204 */ 205 if (isrstatus & CDNS_UART_IXR_FRAMING) { 206 while (!(cdns_uart_readl(CDNS_UART_SR_OFFSET) & 207 CDNS_UART_SR_RXEMPTY)) { 208 if (!cdns_uart_readl(CDNS_UART_FIFO_OFFSET)) { 209 port->read_status_mask |= CDNS_UART_IXR_BRK; 210 isrstatus &= ~CDNS_UART_IXR_FRAMING; 211 } 212 } 213 cdns_uart_writel(CDNS_UART_IXR_FRAMING, CDNS_UART_ISR_OFFSET); 214 } 215 216 /* drop byte with parity error if IGNPAR specified */ 217 if (isrstatus & port->ignore_status_mask & CDNS_UART_IXR_PARITY) 218 isrstatus &= ~(CDNS_UART_IXR_RXTRIG | CDNS_UART_IXR_TOUT); 219 220 isrstatus &= port->read_status_mask; 221 isrstatus &= ~port->ignore_status_mask; 222 223 if ((isrstatus & CDNS_UART_IXR_TOUT) || 224 (isrstatus & CDNS_UART_IXR_RXTRIG)) { 225 /* Receive Timeout Interrupt */ 226 while ((cdns_uart_readl(CDNS_UART_SR_OFFSET) & 227 CDNS_UART_SR_RXEMPTY) != CDNS_UART_SR_RXEMPTY) { 228 data = cdns_uart_readl(CDNS_UART_FIFO_OFFSET); 229 230 /* Non-NULL byte after BREAK is garbage (99%) */ 231 if (data && (port->read_status_mask & 232 CDNS_UART_IXR_BRK)) { 233 port->read_status_mask &= ~CDNS_UART_IXR_BRK; 234 port->icount.brk++; 235 if (uart_handle_break(port)) 236 continue; 237 } 238 239 #ifdef SUPPORT_SYSRQ 240 /* 241 * uart_handle_sysrq_char() doesn't work if 242 * spinlocked, for some reason 243 */ 244 if (port->sysrq) { 245 spin_unlock(&port->lock); 246 if (uart_handle_sysrq_char(port, 247 (unsigned char)data)) { 248 spin_lock(&port->lock); 249 continue; 250 } 251 spin_lock(&port->lock); 252 } 253 #endif 254 255 port->icount.rx++; 256 257 if (isrstatus & CDNS_UART_IXR_PARITY) { 258 port->icount.parity++; 259 status = TTY_PARITY; 260 } else if (isrstatus & CDNS_UART_IXR_FRAMING) { 261 port->icount.frame++; 262 status = TTY_FRAME; 263 } else if (isrstatus & CDNS_UART_IXR_OVERRUN) { 264 port->icount.overrun++; 265 } 266 267 uart_insert_char(port, isrstatus, CDNS_UART_IXR_OVERRUN, 268 data, status); 269 } 270 spin_unlock(&port->lock); 271 tty_flip_buffer_push(&port->state->port); 272 spin_lock(&port->lock); 273 } 274 275 /* Dispatch an appropriate handler */ 276 if ((isrstatus & CDNS_UART_IXR_TXEMPTY) == CDNS_UART_IXR_TXEMPTY) { 277 if (uart_circ_empty(&port->state->xmit)) { 278 cdns_uart_writel(CDNS_UART_IXR_TXEMPTY, 279 CDNS_UART_IDR_OFFSET); 280 } else { 281 numbytes = port->fifosize; 282 /* Break if no more data available in the UART buffer */ 283 while (numbytes--) { 284 if (uart_circ_empty(&port->state->xmit)) 285 break; 286 /* Get the data from the UART circular buffer 287 * and write it to the cdns_uart's TX_FIFO 288 * register. 289 */ 290 cdns_uart_writel( 291 port->state->xmit.buf[port->state->xmit. 292 tail], CDNS_UART_FIFO_OFFSET); 293 294 port->icount.tx++; 295 296 /* Adjust the tail of the UART buffer and wrap 297 * the buffer if it reaches limit. 298 */ 299 port->state->xmit.tail = 300 (port->state->xmit.tail + 1) & 301 (UART_XMIT_SIZE - 1); 302 } 303 304 if (uart_circ_chars_pending( 305 &port->state->xmit) < WAKEUP_CHARS) 306 uart_write_wakeup(port); 307 } 308 } 309 310 cdns_uart_writel(isrstatus, CDNS_UART_ISR_OFFSET); 311 312 /* be sure to release the lock and tty before leaving */ 313 spin_unlock_irqrestore(&port->lock, flags); 314 315 return IRQ_HANDLED; 316 } 317 318 /** 319 * cdns_uart_calc_baud_divs - Calculate baud rate divisors 320 * @clk: UART module input clock 321 * @baud: Desired baud rate 322 * @rbdiv: BDIV value (return value) 323 * @rcd: CD value (return value) 324 * @div8: Value for clk_sel bit in mod (return value) 325 * Return: baud rate, requested baud when possible, or actual baud when there 326 * was too much error, zero if no valid divisors are found. 327 * 328 * Formula to obtain baud rate is 329 * baud_tx/rx rate = clk/CD * (BDIV + 1) 330 * input_clk = (Uart User Defined Clock or Apb Clock) 331 * depends on UCLKEN in MR Reg 332 * clk = input_clk or input_clk/8; 333 * depends on CLKS in MR reg 334 * CD and BDIV depends on values in 335 * baud rate generate register 336 * baud rate clock divisor register 337 */ 338 static unsigned int cdns_uart_calc_baud_divs(unsigned int clk, 339 unsigned int baud, u32 *rbdiv, u32 *rcd, int *div8) 340 { 341 u32 cd, bdiv; 342 unsigned int calc_baud; 343 unsigned int bestbaud = 0; 344 unsigned int bauderror; 345 unsigned int besterror = ~0; 346 347 if (baud < clk / ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX)) { 348 *div8 = 1; 349 clk /= 8; 350 } else { 351 *div8 = 0; 352 } 353 354 for (bdiv = CDNS_UART_BDIV_MIN; bdiv <= CDNS_UART_BDIV_MAX; bdiv++) { 355 cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1)); 356 if (cd < 1 || cd > CDNS_UART_CD_MAX) 357 continue; 358 359 calc_baud = clk / (cd * (bdiv + 1)); 360 361 if (baud > calc_baud) 362 bauderror = baud - calc_baud; 363 else 364 bauderror = calc_baud - baud; 365 366 if (besterror > bauderror) { 367 *rbdiv = bdiv; 368 *rcd = cd; 369 bestbaud = calc_baud; 370 besterror = bauderror; 371 } 372 } 373 /* use the values when percent error is acceptable */ 374 if (((besterror * 100) / baud) < 3) 375 bestbaud = baud; 376 377 return bestbaud; 378 } 379 380 /** 381 * cdns_uart_set_baud_rate - Calculate and set the baud rate 382 * @port: Handle to the uart port structure 383 * @baud: Baud rate to set 384 * Return: baud rate, requested baud when possible, or actual baud when there 385 * was too much error, zero if no valid divisors are found. 386 */ 387 static unsigned int cdns_uart_set_baud_rate(struct uart_port *port, 388 unsigned int baud) 389 { 390 unsigned int calc_baud; 391 u32 cd = 0, bdiv = 0; 392 u32 mreg; 393 int div8; 394 struct cdns_uart *cdns_uart = port->private_data; 395 396 calc_baud = cdns_uart_calc_baud_divs(port->uartclk, baud, &bdiv, &cd, 397 &div8); 398 399 /* Write new divisors to hardware */ 400 mreg = cdns_uart_readl(CDNS_UART_MR_OFFSET); 401 if (div8) 402 mreg |= CDNS_UART_MR_CLKSEL; 403 else 404 mreg &= ~CDNS_UART_MR_CLKSEL; 405 cdns_uart_writel(mreg, CDNS_UART_MR_OFFSET); 406 cdns_uart_writel(cd, CDNS_UART_BAUDGEN_OFFSET); 407 cdns_uart_writel(bdiv, CDNS_UART_BAUDDIV_OFFSET); 408 cdns_uart->baud = baud; 409 410 return calc_baud; 411 } 412 413 #ifdef CONFIG_COMMON_CLK 414 /** 415 * cdns_uart_clk_notitifer_cb - Clock notifier callback 416 * @nb: Notifier block 417 * @event: Notify event 418 * @data: Notifier data 419 * Return: NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error. 420 */ 421 static int cdns_uart_clk_notifier_cb(struct notifier_block *nb, 422 unsigned long event, void *data) 423 { 424 u32 ctrl_reg; 425 struct uart_port *port; 426 int locked = 0; 427 struct clk_notifier_data *ndata = data; 428 unsigned long flags = 0; 429 struct cdns_uart *cdns_uart = to_cdns_uart(nb); 430 431 port = cdns_uart->port; 432 if (port->suspended) 433 return NOTIFY_OK; 434 435 switch (event) { 436 case PRE_RATE_CHANGE: 437 { 438 u32 bdiv, cd; 439 int div8; 440 441 /* 442 * Find out if current baud-rate can be achieved with new clock 443 * frequency. 444 */ 445 if (!cdns_uart_calc_baud_divs(ndata->new_rate, cdns_uart->baud, 446 &bdiv, &cd, &div8)) { 447 dev_warn(port->dev, "clock rate change rejected\n"); 448 return NOTIFY_BAD; 449 } 450 451 spin_lock_irqsave(&cdns_uart->port->lock, flags); 452 453 /* Disable the TX and RX to set baud rate */ 454 ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET); 455 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS; 456 cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET); 457 458 spin_unlock_irqrestore(&cdns_uart->port->lock, flags); 459 460 return NOTIFY_OK; 461 } 462 case POST_RATE_CHANGE: 463 /* 464 * Set clk dividers to generate correct baud with new clock 465 * frequency. 466 */ 467 468 spin_lock_irqsave(&cdns_uart->port->lock, flags); 469 470 locked = 1; 471 port->uartclk = ndata->new_rate; 472 473 cdns_uart->baud = cdns_uart_set_baud_rate(cdns_uart->port, 474 cdns_uart->baud); 475 /* fall through */ 476 case ABORT_RATE_CHANGE: 477 if (!locked) 478 spin_lock_irqsave(&cdns_uart->port->lock, flags); 479 480 /* Set TX/RX Reset */ 481 ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET); 482 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST; 483 cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET); 484 485 while (cdns_uart_readl(CDNS_UART_CR_OFFSET) & 486 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST)) 487 cpu_relax(); 488 489 /* 490 * Clear the RX disable and TX disable bits and then set the TX 491 * enable bit and RX enable bit to enable the transmitter and 492 * receiver. 493 */ 494 cdns_uart_writel(rx_timeout, CDNS_UART_RXTOUT_OFFSET); 495 ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET); 496 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS); 497 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN; 498 cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET); 499 500 spin_unlock_irqrestore(&cdns_uart->port->lock, flags); 501 502 return NOTIFY_OK; 503 default: 504 return NOTIFY_DONE; 505 } 506 } 507 #endif 508 509 /** 510 * cdns_uart_start_tx - Start transmitting bytes 511 * @port: Handle to the uart port structure 512 */ 513 static void cdns_uart_start_tx(struct uart_port *port) 514 { 515 unsigned int status, numbytes = port->fifosize; 516 517 if (uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port)) 518 return; 519 520 status = cdns_uart_readl(CDNS_UART_CR_OFFSET); 521 /* Set the TX enable bit and clear the TX disable bit to enable the 522 * transmitter. 523 */ 524 cdns_uart_writel((status & ~CDNS_UART_CR_TX_DIS) | CDNS_UART_CR_TX_EN, 525 CDNS_UART_CR_OFFSET); 526 527 while (numbytes-- && ((cdns_uart_readl(CDNS_UART_SR_OFFSET) & 528 CDNS_UART_SR_TXFULL)) != CDNS_UART_SR_TXFULL) { 529 /* Break if no more data available in the UART buffer */ 530 if (uart_circ_empty(&port->state->xmit)) 531 break; 532 533 /* Get the data from the UART circular buffer and 534 * write it to the cdns_uart's TX_FIFO register. 535 */ 536 cdns_uart_writel( 537 port->state->xmit.buf[port->state->xmit.tail], 538 CDNS_UART_FIFO_OFFSET); 539 port->icount.tx++; 540 541 /* Adjust the tail of the UART buffer and wrap 542 * the buffer if it reaches limit. 543 */ 544 port->state->xmit.tail = (port->state->xmit.tail + 1) & 545 (UART_XMIT_SIZE - 1); 546 } 547 cdns_uart_writel(CDNS_UART_IXR_TXEMPTY, CDNS_UART_ISR_OFFSET); 548 /* Enable the TX Empty interrupt */ 549 cdns_uart_writel(CDNS_UART_IXR_TXEMPTY, CDNS_UART_IER_OFFSET); 550 551 if (uart_circ_chars_pending(&port->state->xmit) < WAKEUP_CHARS) 552 uart_write_wakeup(port); 553 } 554 555 /** 556 * cdns_uart_stop_tx - Stop TX 557 * @port: Handle to the uart port structure 558 */ 559 static void cdns_uart_stop_tx(struct uart_port *port) 560 { 561 unsigned int regval; 562 563 regval = cdns_uart_readl(CDNS_UART_CR_OFFSET); 564 regval |= CDNS_UART_CR_TX_DIS; 565 /* Disable the transmitter */ 566 cdns_uart_writel(regval, CDNS_UART_CR_OFFSET); 567 } 568 569 /** 570 * cdns_uart_stop_rx - Stop RX 571 * @port: Handle to the uart port structure 572 */ 573 static void cdns_uart_stop_rx(struct uart_port *port) 574 { 575 unsigned int regval; 576 577 regval = cdns_uart_readl(CDNS_UART_CR_OFFSET); 578 regval |= CDNS_UART_CR_RX_DIS; 579 /* Disable the receiver */ 580 cdns_uart_writel(regval, CDNS_UART_CR_OFFSET); 581 } 582 583 /** 584 * cdns_uart_tx_empty - Check whether TX is empty 585 * @port: Handle to the uart port structure 586 * 587 * Return: TIOCSER_TEMT on success, 0 otherwise 588 */ 589 static unsigned int cdns_uart_tx_empty(struct uart_port *port) 590 { 591 unsigned int status; 592 593 status = cdns_uart_readl(CDNS_UART_SR_OFFSET) & CDNS_UART_SR_TXEMPTY; 594 return status ? TIOCSER_TEMT : 0; 595 } 596 597 /** 598 * cdns_uart_break_ctl - Based on the input ctl we have to start or stop 599 * transmitting char breaks 600 * @port: Handle to the uart port structure 601 * @ctl: Value based on which start or stop decision is taken 602 */ 603 static void cdns_uart_break_ctl(struct uart_port *port, int ctl) 604 { 605 unsigned int status; 606 unsigned long flags; 607 608 spin_lock_irqsave(&port->lock, flags); 609 610 status = cdns_uart_readl(CDNS_UART_CR_OFFSET); 611 612 if (ctl == -1) 613 cdns_uart_writel(CDNS_UART_CR_STARTBRK | status, 614 CDNS_UART_CR_OFFSET); 615 else { 616 if ((status & CDNS_UART_CR_STOPBRK) == 0) 617 cdns_uart_writel(CDNS_UART_CR_STOPBRK | status, 618 CDNS_UART_CR_OFFSET); 619 } 620 spin_unlock_irqrestore(&port->lock, flags); 621 } 622 623 /** 624 * cdns_uart_set_termios - termios operations, handling data length, parity, 625 * stop bits, flow control, baud rate 626 * @port: Handle to the uart port structure 627 * @termios: Handle to the input termios structure 628 * @old: Values of the previously saved termios structure 629 */ 630 static void cdns_uart_set_termios(struct uart_port *port, 631 struct ktermios *termios, struct ktermios *old) 632 { 633 unsigned int cval = 0; 634 unsigned int baud, minbaud, maxbaud; 635 unsigned long flags; 636 unsigned int ctrl_reg, mode_reg; 637 638 spin_lock_irqsave(&port->lock, flags); 639 640 /* Wait for the transmit FIFO to empty before making changes */ 641 if (!(cdns_uart_readl(CDNS_UART_CR_OFFSET) & CDNS_UART_CR_TX_DIS)) { 642 while (!(cdns_uart_readl(CDNS_UART_SR_OFFSET) & 643 CDNS_UART_SR_TXEMPTY)) { 644 cpu_relax(); 645 } 646 } 647 648 /* Disable the TX and RX to set baud rate */ 649 ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET); 650 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS; 651 cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET); 652 653 /* 654 * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk 655 * min and max baud should be calculated here based on port->uartclk. 656 * this way we get a valid baud and can safely call set_baud() 657 */ 658 minbaud = port->uartclk / 659 ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX * 8); 660 maxbaud = port->uartclk / (CDNS_UART_BDIV_MIN + 1); 661 baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud); 662 baud = cdns_uart_set_baud_rate(port, baud); 663 if (tty_termios_baud_rate(termios)) 664 tty_termios_encode_baud_rate(termios, baud, baud); 665 666 /* Update the per-port timeout. */ 667 uart_update_timeout(port, termios->c_cflag, baud); 668 669 /* Set TX/RX Reset */ 670 ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET); 671 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST; 672 cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET); 673 674 /* 675 * Clear the RX disable and TX disable bits and then set the TX enable 676 * bit and RX enable bit to enable the transmitter and receiver. 677 */ 678 ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET); 679 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS); 680 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN; 681 cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET); 682 683 cdns_uart_writel(rx_timeout, CDNS_UART_RXTOUT_OFFSET); 684 685 port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG | 686 CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT; 687 port->ignore_status_mask = 0; 688 689 if (termios->c_iflag & INPCK) 690 port->read_status_mask |= CDNS_UART_IXR_PARITY | 691 CDNS_UART_IXR_FRAMING; 692 693 if (termios->c_iflag & IGNPAR) 694 port->ignore_status_mask |= CDNS_UART_IXR_PARITY | 695 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN; 696 697 /* ignore all characters if CREAD is not set */ 698 if ((termios->c_cflag & CREAD) == 0) 699 port->ignore_status_mask |= CDNS_UART_IXR_RXTRIG | 700 CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY | 701 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN; 702 703 mode_reg = cdns_uart_readl(CDNS_UART_MR_OFFSET); 704 705 /* Handling Data Size */ 706 switch (termios->c_cflag & CSIZE) { 707 case CS6: 708 cval |= CDNS_UART_MR_CHARLEN_6_BIT; 709 break; 710 case CS7: 711 cval |= CDNS_UART_MR_CHARLEN_7_BIT; 712 break; 713 default: 714 case CS8: 715 cval |= CDNS_UART_MR_CHARLEN_8_BIT; 716 termios->c_cflag &= ~CSIZE; 717 termios->c_cflag |= CS8; 718 break; 719 } 720 721 /* Handling Parity and Stop Bits length */ 722 if (termios->c_cflag & CSTOPB) 723 cval |= CDNS_UART_MR_STOPMODE_2_BIT; /* 2 STOP bits */ 724 else 725 cval |= CDNS_UART_MR_STOPMODE_1_BIT; /* 1 STOP bit */ 726 727 if (termios->c_cflag & PARENB) { 728 /* Mark or Space parity */ 729 if (termios->c_cflag & CMSPAR) { 730 if (termios->c_cflag & PARODD) 731 cval |= CDNS_UART_MR_PARITY_MARK; 732 else 733 cval |= CDNS_UART_MR_PARITY_SPACE; 734 } else { 735 if (termios->c_cflag & PARODD) 736 cval |= CDNS_UART_MR_PARITY_ODD; 737 else 738 cval |= CDNS_UART_MR_PARITY_EVEN; 739 } 740 } else { 741 cval |= CDNS_UART_MR_PARITY_NONE; 742 } 743 cval |= mode_reg & 1; 744 cdns_uart_writel(cval, CDNS_UART_MR_OFFSET); 745 746 spin_unlock_irqrestore(&port->lock, flags); 747 } 748 749 /** 750 * cdns_uart_startup - Called when an application opens a cdns_uart port 751 * @port: Handle to the uart port structure 752 * 753 * Return: 0 on success, negative errno otherwise 754 */ 755 static int cdns_uart_startup(struct uart_port *port) 756 { 757 unsigned int retval = 0, status = 0; 758 759 retval = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME, 760 (void *)port); 761 if (retval) 762 return retval; 763 764 /* Disable the TX and RX */ 765 cdns_uart_writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS, 766 CDNS_UART_CR_OFFSET); 767 768 /* Set the Control Register with TX/RX Enable, TX/RX Reset, 769 * no break chars. 770 */ 771 cdns_uart_writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST, 772 CDNS_UART_CR_OFFSET); 773 774 status = cdns_uart_readl(CDNS_UART_CR_OFFSET); 775 776 /* Clear the RX disable and TX disable bits and then set the TX enable 777 * bit and RX enable bit to enable the transmitter and receiver. 778 */ 779 cdns_uart_writel((status & ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS)) 780 | (CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN | 781 CDNS_UART_CR_STOPBRK), CDNS_UART_CR_OFFSET); 782 783 /* Set the Mode Register with normal mode,8 data bits,1 stop bit, 784 * no parity. 785 */ 786 cdns_uart_writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT 787 | CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT, 788 CDNS_UART_MR_OFFSET); 789 790 /* 791 * Set the RX FIFO Trigger level to use most of the FIFO, but it 792 * can be tuned with a module parameter 793 */ 794 cdns_uart_writel(rx_trigger_level, CDNS_UART_RXWM_OFFSET); 795 796 /* 797 * Receive Timeout register is enabled but it 798 * can be tuned with a module parameter 799 */ 800 cdns_uart_writel(rx_timeout, CDNS_UART_RXTOUT_OFFSET); 801 802 /* Clear out any pending interrupts before enabling them */ 803 cdns_uart_writel(cdns_uart_readl(CDNS_UART_ISR_OFFSET), 804 CDNS_UART_ISR_OFFSET); 805 806 /* Set the Interrupt Registers with desired interrupts */ 807 cdns_uart_writel(CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_PARITY | 808 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN | 809 CDNS_UART_IXR_RXTRIG | CDNS_UART_IXR_TOUT, 810 CDNS_UART_IER_OFFSET); 811 812 return retval; 813 } 814 815 /** 816 * cdns_uart_shutdown - Called when an application closes a cdns_uart port 817 * @port: Handle to the uart port structure 818 */ 819 static void cdns_uart_shutdown(struct uart_port *port) 820 { 821 int status; 822 823 /* Disable interrupts */ 824 status = cdns_uart_readl(CDNS_UART_IMR_OFFSET); 825 cdns_uart_writel(status, CDNS_UART_IDR_OFFSET); 826 827 /* Disable the TX and RX */ 828 cdns_uart_writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS, 829 CDNS_UART_CR_OFFSET); 830 free_irq(port->irq, port); 831 } 832 833 /** 834 * cdns_uart_type - Set UART type to cdns_uart port 835 * @port: Handle to the uart port structure 836 * 837 * Return: string on success, NULL otherwise 838 */ 839 static const char *cdns_uart_type(struct uart_port *port) 840 { 841 return port->type == PORT_XUARTPS ? CDNS_UART_NAME : NULL; 842 } 843 844 /** 845 * cdns_uart_verify_port - Verify the port params 846 * @port: Handle to the uart port structure 847 * @ser: Handle to the structure whose members are compared 848 * 849 * Return: 0 on success, negative errno otherwise. 850 */ 851 static int cdns_uart_verify_port(struct uart_port *port, 852 struct serial_struct *ser) 853 { 854 if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS) 855 return -EINVAL; 856 if (port->irq != ser->irq) 857 return -EINVAL; 858 if (ser->io_type != UPIO_MEM) 859 return -EINVAL; 860 if (port->iobase != ser->port) 861 return -EINVAL; 862 if (ser->hub6 != 0) 863 return -EINVAL; 864 return 0; 865 } 866 867 /** 868 * cdns_uart_request_port - Claim the memory region attached to cdns_uart port, 869 * called when the driver adds a cdns_uart port via 870 * uart_add_one_port() 871 * @port: Handle to the uart port structure 872 * 873 * Return: 0 on success, negative errno otherwise. 874 */ 875 static int cdns_uart_request_port(struct uart_port *port) 876 { 877 if (!request_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE, 878 CDNS_UART_NAME)) { 879 return -ENOMEM; 880 } 881 882 port->membase = ioremap(port->mapbase, CDNS_UART_REGISTER_SPACE); 883 if (!port->membase) { 884 dev_err(port->dev, "Unable to map registers\n"); 885 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE); 886 return -ENOMEM; 887 } 888 return 0; 889 } 890 891 /** 892 * cdns_uart_release_port - Release UART port 893 * @port: Handle to the uart port structure 894 * 895 * Release the memory region attached to a cdns_uart port. Called when the 896 * driver removes a cdns_uart port via uart_remove_one_port(). 897 */ 898 static void cdns_uart_release_port(struct uart_port *port) 899 { 900 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE); 901 iounmap(port->membase); 902 port->membase = NULL; 903 } 904 905 /** 906 * cdns_uart_config_port - Configure UART port 907 * @port: Handle to the uart port structure 908 * @flags: If any 909 */ 910 static void cdns_uart_config_port(struct uart_port *port, int flags) 911 { 912 if (flags & UART_CONFIG_TYPE && cdns_uart_request_port(port) == 0) 913 port->type = PORT_XUARTPS; 914 } 915 916 /** 917 * cdns_uart_get_mctrl - Get the modem control state 918 * @port: Handle to the uart port structure 919 * 920 * Return: the modem control state 921 */ 922 static unsigned int cdns_uart_get_mctrl(struct uart_port *port) 923 { 924 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; 925 } 926 927 static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 928 { 929 u32 val; 930 931 val = cdns_uart_readl(CDNS_UART_MODEMCR_OFFSET); 932 933 val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR); 934 935 if (mctrl & TIOCM_RTS) 936 val |= CDNS_UART_MODEMCR_RTS; 937 if (mctrl & TIOCM_DTR) 938 val |= CDNS_UART_MODEMCR_DTR; 939 940 cdns_uart_writel(val, CDNS_UART_MODEMCR_OFFSET); 941 } 942 943 #ifdef CONFIG_CONSOLE_POLL 944 static int cdns_uart_poll_get_char(struct uart_port *port) 945 { 946 u32 imr; 947 int c; 948 949 /* Disable all interrupts */ 950 imr = cdns_uart_readl(CDNS_UART_IMR_OFFSET); 951 cdns_uart_writel(imr, CDNS_UART_IDR_OFFSET); 952 953 /* Check if FIFO is empty */ 954 if (cdns_uart_readl(CDNS_UART_SR_OFFSET) & CDNS_UART_SR_RXEMPTY) 955 c = NO_POLL_CHAR; 956 else /* Read a character */ 957 c = (unsigned char) cdns_uart_readl(CDNS_UART_FIFO_OFFSET); 958 959 /* Enable interrupts */ 960 cdns_uart_writel(imr, CDNS_UART_IER_OFFSET); 961 962 return c; 963 } 964 965 static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c) 966 { 967 u32 imr; 968 969 /* Disable all interrupts */ 970 imr = cdns_uart_readl(CDNS_UART_IMR_OFFSET); 971 cdns_uart_writel(imr, CDNS_UART_IDR_OFFSET); 972 973 /* Wait until FIFO is empty */ 974 while (!(cdns_uart_readl(CDNS_UART_SR_OFFSET) & CDNS_UART_SR_TXEMPTY)) 975 cpu_relax(); 976 977 /* Write a character */ 978 cdns_uart_writel(c, CDNS_UART_FIFO_OFFSET); 979 980 /* Wait until FIFO is empty */ 981 while (!(cdns_uart_readl(CDNS_UART_SR_OFFSET) & CDNS_UART_SR_TXEMPTY)) 982 cpu_relax(); 983 984 /* Enable interrupts */ 985 cdns_uart_writel(imr, CDNS_UART_IER_OFFSET); 986 987 return; 988 } 989 #endif 990 991 static struct uart_ops cdns_uart_ops = { 992 .set_mctrl = cdns_uart_set_mctrl, 993 .get_mctrl = cdns_uart_get_mctrl, 994 .start_tx = cdns_uart_start_tx, 995 .stop_tx = cdns_uart_stop_tx, 996 .stop_rx = cdns_uart_stop_rx, 997 .tx_empty = cdns_uart_tx_empty, 998 .break_ctl = cdns_uart_break_ctl, 999 .set_termios = cdns_uart_set_termios, 1000 .startup = cdns_uart_startup, 1001 .shutdown = cdns_uart_shutdown, 1002 .type = cdns_uart_type, 1003 .verify_port = cdns_uart_verify_port, 1004 .request_port = cdns_uart_request_port, 1005 .release_port = cdns_uart_release_port, 1006 .config_port = cdns_uart_config_port, 1007 #ifdef CONFIG_CONSOLE_POLL 1008 .poll_get_char = cdns_uart_poll_get_char, 1009 .poll_put_char = cdns_uart_poll_put_char, 1010 #endif 1011 }; 1012 1013 static struct uart_port cdns_uart_port[2]; 1014 1015 /** 1016 * cdns_uart_get_port - Configure the port from platform device resource info 1017 * @id: Port id 1018 * 1019 * Return: a pointer to a uart_port or NULL for failure 1020 */ 1021 static struct uart_port *cdns_uart_get_port(int id) 1022 { 1023 struct uart_port *port; 1024 1025 /* Try the given port id if failed use default method */ 1026 if (cdns_uart_port[id].mapbase != 0) { 1027 /* Find the next unused port */ 1028 for (id = 0; id < CDNS_UART_NR_PORTS; id++) 1029 if (cdns_uart_port[id].mapbase == 0) 1030 break; 1031 } 1032 1033 if (id >= CDNS_UART_NR_PORTS) 1034 return NULL; 1035 1036 port = &cdns_uart_port[id]; 1037 1038 /* At this point, we've got an empty uart_port struct, initialize it */ 1039 spin_lock_init(&port->lock); 1040 port->membase = NULL; 1041 port->iobase = 1; /* mark port in use */ 1042 port->irq = 0; 1043 port->type = PORT_UNKNOWN; 1044 port->iotype = UPIO_MEM32; 1045 port->flags = UPF_BOOT_AUTOCONF; 1046 port->ops = &cdns_uart_ops; 1047 port->fifosize = CDNS_UART_FIFO_SIZE; 1048 port->line = id; 1049 port->dev = NULL; 1050 return port; 1051 } 1052 1053 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE 1054 /** 1055 * cdns_uart_console_wait_tx - Wait for the TX to be full 1056 * @port: Handle to the uart port structure 1057 */ 1058 static void cdns_uart_console_wait_tx(struct uart_port *port) 1059 { 1060 while ((cdns_uart_readl(CDNS_UART_SR_OFFSET) & CDNS_UART_SR_TXEMPTY) 1061 != CDNS_UART_SR_TXEMPTY) 1062 barrier(); 1063 } 1064 1065 /** 1066 * cdns_uart_console_putchar - write the character to the FIFO buffer 1067 * @port: Handle to the uart port structure 1068 * @ch: Character to be written 1069 */ 1070 static void cdns_uart_console_putchar(struct uart_port *port, int ch) 1071 { 1072 cdns_uart_console_wait_tx(port); 1073 cdns_uart_writel(ch, CDNS_UART_FIFO_OFFSET); 1074 } 1075 1076 static void cdns_early_write(struct console *con, const char *s, unsigned n) 1077 { 1078 struct earlycon_device *dev = con->data; 1079 1080 uart_console_write(&dev->port, s, n, cdns_uart_console_putchar); 1081 } 1082 1083 static int __init cdns_early_console_setup(struct earlycon_device *device, 1084 const char *opt) 1085 { 1086 if (!device->port.membase) 1087 return -ENODEV; 1088 1089 device->con->write = cdns_early_write; 1090 1091 return 0; 1092 } 1093 EARLYCON_DECLARE(cdns, cdns_early_console_setup); 1094 1095 /** 1096 * cdns_uart_console_write - perform write operation 1097 * @co: Console handle 1098 * @s: Pointer to character array 1099 * @count: No of characters 1100 */ 1101 static void cdns_uart_console_write(struct console *co, const char *s, 1102 unsigned int count) 1103 { 1104 struct uart_port *port = &cdns_uart_port[co->index]; 1105 unsigned long flags; 1106 unsigned int imr, ctrl; 1107 int locked = 1; 1108 1109 if (oops_in_progress) 1110 locked = spin_trylock_irqsave(&port->lock, flags); 1111 else 1112 spin_lock_irqsave(&port->lock, flags); 1113 1114 /* save and disable interrupt */ 1115 imr = cdns_uart_readl(CDNS_UART_IMR_OFFSET); 1116 cdns_uart_writel(imr, CDNS_UART_IDR_OFFSET); 1117 1118 /* 1119 * Make sure that the tx part is enabled. Set the TX enable bit and 1120 * clear the TX disable bit to enable the transmitter. 1121 */ 1122 ctrl = cdns_uart_readl(CDNS_UART_CR_OFFSET); 1123 cdns_uart_writel((ctrl & ~CDNS_UART_CR_TX_DIS) | CDNS_UART_CR_TX_EN, 1124 CDNS_UART_CR_OFFSET); 1125 1126 uart_console_write(port, s, count, cdns_uart_console_putchar); 1127 cdns_uart_console_wait_tx(port); 1128 1129 cdns_uart_writel(ctrl, CDNS_UART_CR_OFFSET); 1130 1131 /* restore interrupt state */ 1132 cdns_uart_writel(imr, CDNS_UART_IER_OFFSET); 1133 1134 if (locked) 1135 spin_unlock_irqrestore(&port->lock, flags); 1136 } 1137 1138 /** 1139 * cdns_uart_console_setup - Initialize the uart to default config 1140 * @co: Console handle 1141 * @options: Initial settings of uart 1142 * 1143 * Return: 0 on success, negative errno otherwise. 1144 */ 1145 static int __init cdns_uart_console_setup(struct console *co, char *options) 1146 { 1147 struct uart_port *port = &cdns_uart_port[co->index]; 1148 int baud = 9600; 1149 int bits = 8; 1150 int parity = 'n'; 1151 int flow = 'n'; 1152 1153 if (co->index < 0 || co->index >= CDNS_UART_NR_PORTS) 1154 return -EINVAL; 1155 1156 if (!port->mapbase) { 1157 pr_debug("console on ttyPS%i not present\n", co->index); 1158 return -ENODEV; 1159 } 1160 1161 if (options) 1162 uart_parse_options(options, &baud, &parity, &bits, &flow); 1163 1164 return uart_set_options(port, co, baud, parity, bits, flow); 1165 } 1166 1167 static struct uart_driver cdns_uart_uart_driver; 1168 1169 static struct console cdns_uart_console = { 1170 .name = CDNS_UART_TTY_NAME, 1171 .write = cdns_uart_console_write, 1172 .device = uart_console_device, 1173 .setup = cdns_uart_console_setup, 1174 .flags = CON_PRINTBUFFER, 1175 .index = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */ 1176 .data = &cdns_uart_uart_driver, 1177 }; 1178 1179 /** 1180 * cdns_uart_console_init - Initialization call 1181 * 1182 * Return: 0 on success, negative errno otherwise 1183 */ 1184 static int __init cdns_uart_console_init(void) 1185 { 1186 register_console(&cdns_uart_console); 1187 return 0; 1188 } 1189 1190 console_initcall(cdns_uart_console_init); 1191 1192 #endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */ 1193 1194 static struct uart_driver cdns_uart_uart_driver = { 1195 .owner = THIS_MODULE, 1196 .driver_name = CDNS_UART_NAME, 1197 .dev_name = CDNS_UART_TTY_NAME, 1198 .major = CDNS_UART_MAJOR, 1199 .minor = CDNS_UART_MINOR, 1200 .nr = CDNS_UART_NR_PORTS, 1201 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE 1202 .cons = &cdns_uart_console, 1203 #endif 1204 }; 1205 1206 #ifdef CONFIG_PM_SLEEP 1207 /** 1208 * cdns_uart_suspend - suspend event 1209 * @device: Pointer to the device structure 1210 * 1211 * Return: 0 1212 */ 1213 static int cdns_uart_suspend(struct device *device) 1214 { 1215 struct uart_port *port = dev_get_drvdata(device); 1216 struct tty_struct *tty; 1217 struct device *tty_dev; 1218 int may_wake = 0; 1219 1220 /* Get the tty which could be NULL so don't assume it's valid */ 1221 tty = tty_port_tty_get(&port->state->port); 1222 if (tty) { 1223 tty_dev = tty->dev; 1224 may_wake = device_may_wakeup(tty_dev); 1225 tty_kref_put(tty); 1226 } 1227 1228 /* 1229 * Call the API provided in serial_core.c file which handles 1230 * the suspend. 1231 */ 1232 uart_suspend_port(&cdns_uart_uart_driver, port); 1233 if (console_suspend_enabled && !may_wake) { 1234 struct cdns_uart *cdns_uart = port->private_data; 1235 1236 clk_disable(cdns_uart->uartclk); 1237 clk_disable(cdns_uart->pclk); 1238 } else { 1239 unsigned long flags = 0; 1240 1241 spin_lock_irqsave(&port->lock, flags); 1242 /* Empty the receive FIFO 1st before making changes */ 1243 while (!(cdns_uart_readl(CDNS_UART_SR_OFFSET) & 1244 CDNS_UART_SR_RXEMPTY)) 1245 cdns_uart_readl(CDNS_UART_FIFO_OFFSET); 1246 /* set RX trigger level to 1 */ 1247 cdns_uart_writel(1, CDNS_UART_RXWM_OFFSET); 1248 /* disable RX timeout interrups */ 1249 cdns_uart_writel(CDNS_UART_IXR_TOUT, CDNS_UART_IDR_OFFSET); 1250 spin_unlock_irqrestore(&port->lock, flags); 1251 } 1252 1253 return 0; 1254 } 1255 1256 /** 1257 * cdns_uart_resume - Resume after a previous suspend 1258 * @device: Pointer to the device structure 1259 * 1260 * Return: 0 1261 */ 1262 static int cdns_uart_resume(struct device *device) 1263 { 1264 struct uart_port *port = dev_get_drvdata(device); 1265 unsigned long flags = 0; 1266 u32 ctrl_reg; 1267 struct tty_struct *tty; 1268 struct device *tty_dev; 1269 int may_wake = 0; 1270 1271 /* Get the tty which could be NULL so don't assume it's valid */ 1272 tty = tty_port_tty_get(&port->state->port); 1273 if (tty) { 1274 tty_dev = tty->dev; 1275 may_wake = device_may_wakeup(tty_dev); 1276 tty_kref_put(tty); 1277 } 1278 1279 if (console_suspend_enabled && !may_wake) { 1280 struct cdns_uart *cdns_uart = port->private_data; 1281 1282 clk_enable(cdns_uart->pclk); 1283 clk_enable(cdns_uart->uartclk); 1284 1285 spin_lock_irqsave(&port->lock, flags); 1286 1287 /* Set TX/RX Reset */ 1288 ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET); 1289 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST; 1290 cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET); 1291 while (cdns_uart_readl(CDNS_UART_CR_OFFSET) & 1292 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST)) 1293 cpu_relax(); 1294 1295 /* restore rx timeout value */ 1296 cdns_uart_writel(rx_timeout, CDNS_UART_RXTOUT_OFFSET); 1297 /* Enable Tx/Rx */ 1298 ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET); 1299 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS); 1300 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN; 1301 cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET); 1302 1303 spin_unlock_irqrestore(&port->lock, flags); 1304 } else { 1305 spin_lock_irqsave(&port->lock, flags); 1306 /* restore original rx trigger level */ 1307 cdns_uart_writel(rx_trigger_level, CDNS_UART_RXWM_OFFSET); 1308 /* enable RX timeout interrupt */ 1309 cdns_uart_writel(CDNS_UART_IXR_TOUT, CDNS_UART_IER_OFFSET); 1310 spin_unlock_irqrestore(&port->lock, flags); 1311 } 1312 1313 return uart_resume_port(&cdns_uart_uart_driver, port); 1314 } 1315 #endif /* ! CONFIG_PM_SLEEP */ 1316 1317 static SIMPLE_DEV_PM_OPS(cdns_uart_dev_pm_ops, cdns_uart_suspend, 1318 cdns_uart_resume); 1319 1320 /** 1321 * cdns_uart_probe - Platform driver probe 1322 * @pdev: Pointer to the platform device structure 1323 * 1324 * Return: 0 on success, negative errno otherwise 1325 */ 1326 static int cdns_uart_probe(struct platform_device *pdev) 1327 { 1328 int rc, id; 1329 struct uart_port *port; 1330 struct resource *res, *res2; 1331 struct cdns_uart *cdns_uart_data; 1332 1333 cdns_uart_data = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_data), 1334 GFP_KERNEL); 1335 if (!cdns_uart_data) 1336 return -ENOMEM; 1337 1338 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "pclk"); 1339 if (IS_ERR(cdns_uart_data->pclk)) { 1340 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "aper_clk"); 1341 if (!IS_ERR(cdns_uart_data->pclk)) 1342 dev_err(&pdev->dev, "clock name 'aper_clk' is deprecated.\n"); 1343 } 1344 if (IS_ERR(cdns_uart_data->pclk)) { 1345 dev_err(&pdev->dev, "pclk clock not found.\n"); 1346 return PTR_ERR(cdns_uart_data->pclk); 1347 } 1348 1349 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "uart_clk"); 1350 if (IS_ERR(cdns_uart_data->uartclk)) { 1351 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "ref_clk"); 1352 if (!IS_ERR(cdns_uart_data->uartclk)) 1353 dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n"); 1354 } 1355 if (IS_ERR(cdns_uart_data->uartclk)) { 1356 dev_err(&pdev->dev, "uart_clk clock not found.\n"); 1357 return PTR_ERR(cdns_uart_data->uartclk); 1358 } 1359 1360 rc = clk_prepare_enable(cdns_uart_data->pclk); 1361 if (rc) { 1362 dev_err(&pdev->dev, "Unable to enable pclk clock.\n"); 1363 return rc; 1364 } 1365 rc = clk_prepare_enable(cdns_uart_data->uartclk); 1366 if (rc) { 1367 dev_err(&pdev->dev, "Unable to enable device clock.\n"); 1368 goto err_out_clk_dis_pclk; 1369 } 1370 1371 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1372 if (!res) { 1373 rc = -ENODEV; 1374 goto err_out_clk_disable; 1375 } 1376 1377 res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1378 if (!res2) { 1379 rc = -ENODEV; 1380 goto err_out_clk_disable; 1381 } 1382 1383 #ifdef CONFIG_COMMON_CLK 1384 cdns_uart_data->clk_rate_change_nb.notifier_call = 1385 cdns_uart_clk_notifier_cb; 1386 if (clk_notifier_register(cdns_uart_data->uartclk, 1387 &cdns_uart_data->clk_rate_change_nb)) 1388 dev_warn(&pdev->dev, "Unable to register clock notifier.\n"); 1389 #endif 1390 /* Look for a serialN alias */ 1391 id = of_alias_get_id(pdev->dev.of_node, "serial"); 1392 if (id < 0) 1393 id = 0; 1394 1395 /* Initialize the port structure */ 1396 port = cdns_uart_get_port(id); 1397 1398 if (!port) { 1399 dev_err(&pdev->dev, "Cannot get uart_port structure\n"); 1400 rc = -ENODEV; 1401 goto err_out_notif_unreg; 1402 } else { 1403 /* Register the port. 1404 * This function also registers this device with the tty layer 1405 * and triggers invocation of the config_port() entry point. 1406 */ 1407 port->mapbase = res->start; 1408 port->irq = res2->start; 1409 port->dev = &pdev->dev; 1410 port->uartclk = clk_get_rate(cdns_uart_data->uartclk); 1411 port->private_data = cdns_uart_data; 1412 cdns_uart_data->port = port; 1413 platform_set_drvdata(pdev, port); 1414 rc = uart_add_one_port(&cdns_uart_uart_driver, port); 1415 if (rc) { 1416 dev_err(&pdev->dev, 1417 "uart_add_one_port() failed; err=%i\n", rc); 1418 goto err_out_notif_unreg; 1419 } 1420 return 0; 1421 } 1422 1423 err_out_notif_unreg: 1424 #ifdef CONFIG_COMMON_CLK 1425 clk_notifier_unregister(cdns_uart_data->uartclk, 1426 &cdns_uart_data->clk_rate_change_nb); 1427 #endif 1428 err_out_clk_disable: 1429 clk_disable_unprepare(cdns_uart_data->uartclk); 1430 err_out_clk_dis_pclk: 1431 clk_disable_unprepare(cdns_uart_data->pclk); 1432 1433 return rc; 1434 } 1435 1436 /** 1437 * cdns_uart_remove - called when the platform driver is unregistered 1438 * @pdev: Pointer to the platform device structure 1439 * 1440 * Return: 0 on success, negative errno otherwise 1441 */ 1442 static int cdns_uart_remove(struct platform_device *pdev) 1443 { 1444 struct uart_port *port = platform_get_drvdata(pdev); 1445 struct cdns_uart *cdns_uart_data = port->private_data; 1446 int rc; 1447 1448 /* Remove the cdns_uart port from the serial core */ 1449 #ifdef CONFIG_COMMON_CLK 1450 clk_notifier_unregister(cdns_uart_data->uartclk, 1451 &cdns_uart_data->clk_rate_change_nb); 1452 #endif 1453 rc = uart_remove_one_port(&cdns_uart_uart_driver, port); 1454 port->mapbase = 0; 1455 clk_disable_unprepare(cdns_uart_data->uartclk); 1456 clk_disable_unprepare(cdns_uart_data->pclk); 1457 return rc; 1458 } 1459 1460 /* Match table for of_platform binding */ 1461 static struct of_device_id cdns_uart_of_match[] = { 1462 { .compatible = "xlnx,xuartps", }, 1463 { .compatible = "cdns,uart-r1p8", }, 1464 {} 1465 }; 1466 MODULE_DEVICE_TABLE(of, cdns_uart_of_match); 1467 1468 static struct platform_driver cdns_uart_platform_driver = { 1469 .probe = cdns_uart_probe, 1470 .remove = cdns_uart_remove, 1471 .driver = { 1472 .name = CDNS_UART_NAME, 1473 .of_match_table = cdns_uart_of_match, 1474 .pm = &cdns_uart_dev_pm_ops, 1475 }, 1476 }; 1477 1478 static int __init cdns_uart_init(void) 1479 { 1480 int retval = 0; 1481 1482 /* Register the cdns_uart driver with the serial core */ 1483 retval = uart_register_driver(&cdns_uart_uart_driver); 1484 if (retval) 1485 return retval; 1486 1487 /* Register the platform driver */ 1488 retval = platform_driver_register(&cdns_uart_platform_driver); 1489 if (retval) 1490 uart_unregister_driver(&cdns_uart_uart_driver); 1491 1492 return retval; 1493 } 1494 1495 static void __exit cdns_uart_exit(void) 1496 { 1497 /* Unregister the platform driver */ 1498 platform_driver_unregister(&cdns_uart_platform_driver); 1499 1500 /* Unregister the cdns_uart driver */ 1501 uart_unregister_driver(&cdns_uart_uart_driver); 1502 } 1503 1504 module_init(cdns_uart_init); 1505 module_exit(cdns_uart_exit); 1506 1507 MODULE_DESCRIPTION("Driver for Cadence UART"); 1508 MODULE_AUTHOR("Xilinx Inc."); 1509 MODULE_LICENSE("GPL"); 1510