1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Cadence UART driver (found in Xilinx Zynq) 4 * 5 * 2011 - 2014 (C) Xilinx Inc. 6 * 7 * This driver has originally been pushed by Xilinx using a Zynq-branding. This 8 * still shows in the naming of this file, the kconfig symbols and some symbols 9 * in the code. 10 */ 11 12 #if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 13 #define SUPPORT_SYSRQ 14 #endif 15 16 #include <linux/platform_device.h> 17 #include <linux/serial.h> 18 #include <linux/console.h> 19 #include <linux/serial_core.h> 20 #include <linux/slab.h> 21 #include <linux/tty.h> 22 #include <linux/tty_flip.h> 23 #include <linux/clk.h> 24 #include <linux/irq.h> 25 #include <linux/io.h> 26 #include <linux/of.h> 27 #include <linux/module.h> 28 #include <linux/pm_runtime.h> 29 30 #define CDNS_UART_TTY_NAME "ttyPS" 31 #define CDNS_UART_NAME "xuartps" 32 #define CDNS_UART_MAJOR 0 /* use dynamic node allocation */ 33 #define CDNS_UART_MINOR 0 /* works best with devtmpfs */ 34 #define CDNS_UART_NR_PORTS 2 35 #define CDNS_UART_FIFO_SIZE 64 /* FIFO size */ 36 #define CDNS_UART_REGISTER_SPACE 0x1000 37 38 /* Rx Trigger level */ 39 static int rx_trigger_level = 56; 40 module_param(rx_trigger_level, uint, S_IRUGO); 41 MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes"); 42 43 /* Rx Timeout */ 44 static int rx_timeout = 10; 45 module_param(rx_timeout, uint, S_IRUGO); 46 MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255"); 47 48 /* Register offsets for the UART. */ 49 #define CDNS_UART_CR 0x00 /* Control Register */ 50 #define CDNS_UART_MR 0x04 /* Mode Register */ 51 #define CDNS_UART_IER 0x08 /* Interrupt Enable */ 52 #define CDNS_UART_IDR 0x0C /* Interrupt Disable */ 53 #define CDNS_UART_IMR 0x10 /* Interrupt Mask */ 54 #define CDNS_UART_ISR 0x14 /* Interrupt Status */ 55 #define CDNS_UART_BAUDGEN 0x18 /* Baud Rate Generator */ 56 #define CDNS_UART_RXTOUT 0x1C /* RX Timeout */ 57 #define CDNS_UART_RXWM 0x20 /* RX FIFO Trigger Level */ 58 #define CDNS_UART_MODEMCR 0x24 /* Modem Control */ 59 #define CDNS_UART_MODEMSR 0x28 /* Modem Status */ 60 #define CDNS_UART_SR 0x2C /* Channel Status */ 61 #define CDNS_UART_FIFO 0x30 /* FIFO */ 62 #define CDNS_UART_BAUDDIV 0x34 /* Baud Rate Divider */ 63 #define CDNS_UART_FLOWDEL 0x38 /* Flow Delay */ 64 #define CDNS_UART_IRRX_PWIDTH 0x3C /* IR Min Received Pulse Width */ 65 #define CDNS_UART_IRTX_PWIDTH 0x40 /* IR Transmitted pulse Width */ 66 #define CDNS_UART_TXWM 0x44 /* TX FIFO Trigger Level */ 67 #define CDNS_UART_RXBS 0x48 /* RX FIFO byte status register */ 68 69 /* Control Register Bit Definitions */ 70 #define CDNS_UART_CR_STOPBRK 0x00000100 /* Stop TX break */ 71 #define CDNS_UART_CR_STARTBRK 0x00000080 /* Set TX break */ 72 #define CDNS_UART_CR_TX_DIS 0x00000020 /* TX disabled. */ 73 #define CDNS_UART_CR_TX_EN 0x00000010 /* TX enabled */ 74 #define CDNS_UART_CR_RX_DIS 0x00000008 /* RX disabled. */ 75 #define CDNS_UART_CR_RX_EN 0x00000004 /* RX enabled */ 76 #define CDNS_UART_CR_TXRST 0x00000002 /* TX logic reset */ 77 #define CDNS_UART_CR_RXRST 0x00000001 /* RX logic reset */ 78 #define CDNS_UART_CR_RST_TO 0x00000040 /* Restart Timeout Counter */ 79 #define CDNS_UART_RXBS_PARITY 0x00000001 /* Parity error status */ 80 #define CDNS_UART_RXBS_FRAMING 0x00000002 /* Framing error status */ 81 #define CDNS_UART_RXBS_BRK 0x00000004 /* Overrun error status */ 82 83 /* 84 * Mode Register: 85 * The mode register (MR) defines the mode of transfer as well as the data 86 * format. If this register is modified during transmission or reception, 87 * data validity cannot be guaranteed. 88 */ 89 #define CDNS_UART_MR_CLKSEL 0x00000001 /* Pre-scalar selection */ 90 #define CDNS_UART_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */ 91 #define CDNS_UART_MR_CHMODE_NORM 0x00000000 /* Normal mode */ 92 #define CDNS_UART_MR_CHMODE_MASK 0x00000300 /* Mask for mode bits */ 93 94 #define CDNS_UART_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */ 95 #define CDNS_UART_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */ 96 97 #define CDNS_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */ 98 #define CDNS_UART_MR_PARITY_MARK 0x00000018 /* Mark parity mode */ 99 #define CDNS_UART_MR_PARITY_SPACE 0x00000010 /* Space parity mode */ 100 #define CDNS_UART_MR_PARITY_ODD 0x00000008 /* Odd parity mode */ 101 #define CDNS_UART_MR_PARITY_EVEN 0x00000000 /* Even parity mode */ 102 103 #define CDNS_UART_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */ 104 #define CDNS_UART_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */ 105 #define CDNS_UART_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */ 106 107 /* 108 * Interrupt Registers: 109 * Interrupt control logic uses the interrupt enable register (IER) and the 110 * interrupt disable register (IDR) to set the value of the bits in the 111 * interrupt mask register (IMR). The IMR determines whether to pass an 112 * interrupt to the interrupt status register (ISR). 113 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an 114 * interrupt. IMR and ISR are read only, and IER and IDR are write only. 115 * Reading either IER or IDR returns 0x00. 116 * All four registers have the same bit definitions. 117 */ 118 #define CDNS_UART_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */ 119 #define CDNS_UART_IXR_PARITY 0x00000080 /* Parity error interrupt */ 120 #define CDNS_UART_IXR_FRAMING 0x00000040 /* Framing error interrupt */ 121 #define CDNS_UART_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */ 122 #define CDNS_UART_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */ 123 #define CDNS_UART_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */ 124 #define CDNS_UART_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */ 125 #define CDNS_UART_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */ 126 #define CDNS_UART_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */ 127 #define CDNS_UART_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */ 128 #define CDNS_UART_IXR_MASK 0x00001FFF /* Valid bit mask */ 129 130 /* 131 * Do not enable parity error interrupt for the following 132 * reason: When parity error interrupt is enabled, each Rx 133 * parity error always results in 2 events. The first one 134 * being parity error interrupt and the second one with a 135 * proper Rx interrupt with the incoming data. Disabling 136 * parity error interrupt ensures better handling of parity 137 * error events. With this change, for a parity error case, we 138 * get a Rx interrupt with parity error set in ISR register 139 * and we still handle parity errors in the desired way. 140 */ 141 142 #define CDNS_UART_RX_IRQS (CDNS_UART_IXR_FRAMING | \ 143 CDNS_UART_IXR_OVERRUN | \ 144 CDNS_UART_IXR_RXTRIG | \ 145 CDNS_UART_IXR_TOUT) 146 147 /* Goes in read_status_mask for break detection as the HW doesn't do it*/ 148 #define CDNS_UART_IXR_BRK 0x00002000 149 150 #define CDNS_UART_RXBS_SUPPORT BIT(1) 151 /* 152 * Modem Control register: 153 * The read/write Modem Control register controls the interface with the modem 154 * or data set, or a peripheral device emulating a modem. 155 */ 156 #define CDNS_UART_MODEMCR_FCM 0x00000020 /* Automatic flow control mode */ 157 #define CDNS_UART_MODEMCR_RTS 0x00000002 /* Request to send output control */ 158 #define CDNS_UART_MODEMCR_DTR 0x00000001 /* Data Terminal Ready */ 159 160 /* 161 * Channel Status Register: 162 * The channel status register (CSR) is provided to enable the control logic 163 * to monitor the status of bits in the channel interrupt status register, 164 * even if these are masked out by the interrupt mask register. 165 */ 166 #define CDNS_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */ 167 #define CDNS_UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */ 168 #define CDNS_UART_SR_TXFULL 0x00000010 /* TX FIFO full */ 169 #define CDNS_UART_SR_RXTRIG 0x00000001 /* Rx Trigger */ 170 171 /* baud dividers min/max values */ 172 #define CDNS_UART_BDIV_MIN 4 173 #define CDNS_UART_BDIV_MAX 255 174 #define CDNS_UART_CD_MAX 65535 175 #define UART_AUTOSUSPEND_TIMEOUT 3000 176 177 /** 178 * struct cdns_uart - device data 179 * @port: Pointer to the UART port 180 * @uartclk: Reference clock 181 * @pclk: APB clock 182 * @baud: Current baud rate 183 * @clk_rate_change_nb: Notifier block for clock changes 184 * @quirks: Flags for RXBS support. 185 */ 186 struct cdns_uart { 187 struct uart_port *port; 188 struct clk *uartclk; 189 struct clk *pclk; 190 unsigned int baud; 191 struct notifier_block clk_rate_change_nb; 192 u32 quirks; 193 }; 194 struct cdns_platform_data { 195 u32 quirks; 196 }; 197 #define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \ 198 clk_rate_change_nb); 199 200 /** 201 * cdns_uart_handle_rx - Handle the received bytes along with Rx errors. 202 * @dev_id: Id of the UART port 203 * @isrstatus: The interrupt status register value as read 204 * Return: None 205 */ 206 static void cdns_uart_handle_rx(void *dev_id, unsigned int isrstatus) 207 { 208 struct uart_port *port = (struct uart_port *)dev_id; 209 struct cdns_uart *cdns_uart = port->private_data; 210 unsigned int data; 211 unsigned int rxbs_status = 0; 212 unsigned int status_mask; 213 unsigned int framerrprocessed = 0; 214 char status = TTY_NORMAL; 215 bool is_rxbs_support; 216 217 is_rxbs_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT; 218 219 while ((readl(port->membase + CDNS_UART_SR) & 220 CDNS_UART_SR_RXEMPTY) != CDNS_UART_SR_RXEMPTY) { 221 if (is_rxbs_support) 222 rxbs_status = readl(port->membase + CDNS_UART_RXBS); 223 data = readl(port->membase + CDNS_UART_FIFO); 224 port->icount.rx++; 225 /* 226 * There is no hardware break detection in Zynq, so we interpret 227 * framing error with all-zeros data as a break sequence. 228 * Most of the time, there's another non-zero byte at the 229 * end of the sequence. 230 */ 231 if (!is_rxbs_support && (isrstatus & CDNS_UART_IXR_FRAMING)) { 232 if (!data) { 233 port->read_status_mask |= CDNS_UART_IXR_BRK; 234 framerrprocessed = 1; 235 continue; 236 } 237 } 238 if (is_rxbs_support && (rxbs_status & CDNS_UART_RXBS_BRK)) { 239 port->icount.brk++; 240 status = TTY_BREAK; 241 if (uart_handle_break(port)) 242 continue; 243 } 244 245 isrstatus &= port->read_status_mask; 246 isrstatus &= ~port->ignore_status_mask; 247 status_mask = port->read_status_mask; 248 status_mask &= ~port->ignore_status_mask; 249 250 if (data && 251 (port->read_status_mask & CDNS_UART_IXR_BRK)) { 252 port->read_status_mask &= ~CDNS_UART_IXR_BRK; 253 port->icount.brk++; 254 if (uart_handle_break(port)) 255 continue; 256 } 257 258 if (uart_handle_sysrq_char(port, data)) 259 continue; 260 261 if (is_rxbs_support) { 262 if ((rxbs_status & CDNS_UART_RXBS_PARITY) 263 && (status_mask & CDNS_UART_IXR_PARITY)) { 264 port->icount.parity++; 265 status = TTY_PARITY; 266 } 267 if ((rxbs_status & CDNS_UART_RXBS_FRAMING) 268 && (status_mask & CDNS_UART_IXR_PARITY)) { 269 port->icount.frame++; 270 status = TTY_FRAME; 271 } 272 } else { 273 if (isrstatus & CDNS_UART_IXR_PARITY) { 274 port->icount.parity++; 275 status = TTY_PARITY; 276 } 277 if ((isrstatus & CDNS_UART_IXR_FRAMING) && 278 !framerrprocessed) { 279 port->icount.frame++; 280 status = TTY_FRAME; 281 } 282 } 283 if (isrstatus & CDNS_UART_IXR_OVERRUN) { 284 port->icount.overrun++; 285 tty_insert_flip_char(&port->state->port, 0, 286 TTY_OVERRUN); 287 } 288 tty_insert_flip_char(&port->state->port, data, status); 289 isrstatus = 0; 290 } 291 spin_unlock(&port->lock); 292 tty_flip_buffer_push(&port->state->port); 293 spin_lock(&port->lock); 294 } 295 296 /** 297 * cdns_uart_handle_tx - Handle the bytes to be Txed. 298 * @dev_id: Id of the UART port 299 * Return: None 300 */ 301 static void cdns_uart_handle_tx(void *dev_id) 302 { 303 struct uart_port *port = (struct uart_port *)dev_id; 304 unsigned int numbytes; 305 306 if (uart_circ_empty(&port->state->xmit)) { 307 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR); 308 } else { 309 numbytes = port->fifosize; 310 while (numbytes && !uart_circ_empty(&port->state->xmit) && 311 !(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL)) { 312 /* 313 * Get the data from the UART circular buffer 314 * and write it to the cdns_uart's TX_FIFO 315 * register. 316 */ 317 writel( 318 port->state->xmit.buf[port->state->xmit. 319 tail], port->membase + CDNS_UART_FIFO); 320 321 port->icount.tx++; 322 323 /* 324 * Adjust the tail of the UART buffer and wrap 325 * the buffer if it reaches limit. 326 */ 327 port->state->xmit.tail = 328 (port->state->xmit.tail + 1) & 329 (UART_XMIT_SIZE - 1); 330 331 numbytes--; 332 } 333 334 if (uart_circ_chars_pending( 335 &port->state->xmit) < WAKEUP_CHARS) 336 uart_write_wakeup(port); 337 } 338 } 339 340 /** 341 * cdns_uart_isr - Interrupt handler 342 * @irq: Irq number 343 * @dev_id: Id of the port 344 * 345 * Return: IRQHANDLED 346 */ 347 static irqreturn_t cdns_uart_isr(int irq, void *dev_id) 348 { 349 struct uart_port *port = (struct uart_port *)dev_id; 350 unsigned int isrstatus; 351 352 spin_lock(&port->lock); 353 354 /* Read the interrupt status register to determine which 355 * interrupt(s) is/are active and clear them. 356 */ 357 isrstatus = readl(port->membase + CDNS_UART_ISR); 358 writel(isrstatus, port->membase + CDNS_UART_ISR); 359 360 if (isrstatus & CDNS_UART_IXR_TXEMPTY) { 361 cdns_uart_handle_tx(dev_id); 362 isrstatus &= ~CDNS_UART_IXR_TXEMPTY; 363 } 364 if (isrstatus & CDNS_UART_IXR_MASK) 365 cdns_uart_handle_rx(dev_id, isrstatus); 366 367 spin_unlock(&port->lock); 368 return IRQ_HANDLED; 369 } 370 371 /** 372 * cdns_uart_calc_baud_divs - Calculate baud rate divisors 373 * @clk: UART module input clock 374 * @baud: Desired baud rate 375 * @rbdiv: BDIV value (return value) 376 * @rcd: CD value (return value) 377 * @div8: Value for clk_sel bit in mod (return value) 378 * Return: baud rate, requested baud when possible, or actual baud when there 379 * was too much error, zero if no valid divisors are found. 380 * 381 * Formula to obtain baud rate is 382 * baud_tx/rx rate = clk/CD * (BDIV + 1) 383 * input_clk = (Uart User Defined Clock or Apb Clock) 384 * depends on UCLKEN in MR Reg 385 * clk = input_clk or input_clk/8; 386 * depends on CLKS in MR reg 387 * CD and BDIV depends on values in 388 * baud rate generate register 389 * baud rate clock divisor register 390 */ 391 static unsigned int cdns_uart_calc_baud_divs(unsigned int clk, 392 unsigned int baud, u32 *rbdiv, u32 *rcd, int *div8) 393 { 394 u32 cd, bdiv; 395 unsigned int calc_baud; 396 unsigned int bestbaud = 0; 397 unsigned int bauderror; 398 unsigned int besterror = ~0; 399 400 if (baud < clk / ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX)) { 401 *div8 = 1; 402 clk /= 8; 403 } else { 404 *div8 = 0; 405 } 406 407 for (bdiv = CDNS_UART_BDIV_MIN; bdiv <= CDNS_UART_BDIV_MAX; bdiv++) { 408 cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1)); 409 if (cd < 1 || cd > CDNS_UART_CD_MAX) 410 continue; 411 412 calc_baud = clk / (cd * (bdiv + 1)); 413 414 if (baud > calc_baud) 415 bauderror = baud - calc_baud; 416 else 417 bauderror = calc_baud - baud; 418 419 if (besterror > bauderror) { 420 *rbdiv = bdiv; 421 *rcd = cd; 422 bestbaud = calc_baud; 423 besterror = bauderror; 424 } 425 } 426 /* use the values when percent error is acceptable */ 427 if (((besterror * 100) / baud) < 3) 428 bestbaud = baud; 429 430 return bestbaud; 431 } 432 433 /** 434 * cdns_uart_set_baud_rate - Calculate and set the baud rate 435 * @port: Handle to the uart port structure 436 * @baud: Baud rate to set 437 * Return: baud rate, requested baud when possible, or actual baud when there 438 * was too much error, zero if no valid divisors are found. 439 */ 440 static unsigned int cdns_uart_set_baud_rate(struct uart_port *port, 441 unsigned int baud) 442 { 443 unsigned int calc_baud; 444 u32 cd = 0, bdiv = 0; 445 u32 mreg; 446 int div8; 447 struct cdns_uart *cdns_uart = port->private_data; 448 449 calc_baud = cdns_uart_calc_baud_divs(port->uartclk, baud, &bdiv, &cd, 450 &div8); 451 452 /* Write new divisors to hardware */ 453 mreg = readl(port->membase + CDNS_UART_MR); 454 if (div8) 455 mreg |= CDNS_UART_MR_CLKSEL; 456 else 457 mreg &= ~CDNS_UART_MR_CLKSEL; 458 writel(mreg, port->membase + CDNS_UART_MR); 459 writel(cd, port->membase + CDNS_UART_BAUDGEN); 460 writel(bdiv, port->membase + CDNS_UART_BAUDDIV); 461 cdns_uart->baud = baud; 462 463 return calc_baud; 464 } 465 466 #ifdef CONFIG_COMMON_CLK 467 /** 468 * cdns_uart_clk_notitifer_cb - Clock notifier callback 469 * @nb: Notifier block 470 * @event: Notify event 471 * @data: Notifier data 472 * Return: NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error. 473 */ 474 static int cdns_uart_clk_notifier_cb(struct notifier_block *nb, 475 unsigned long event, void *data) 476 { 477 u32 ctrl_reg; 478 struct uart_port *port; 479 int locked = 0; 480 struct clk_notifier_data *ndata = data; 481 unsigned long flags = 0; 482 struct cdns_uart *cdns_uart = to_cdns_uart(nb); 483 484 port = cdns_uart->port; 485 if (port->suspended) 486 return NOTIFY_OK; 487 488 switch (event) { 489 case PRE_RATE_CHANGE: 490 { 491 u32 bdiv, cd; 492 int div8; 493 494 /* 495 * Find out if current baud-rate can be achieved with new clock 496 * frequency. 497 */ 498 if (!cdns_uart_calc_baud_divs(ndata->new_rate, cdns_uart->baud, 499 &bdiv, &cd, &div8)) { 500 dev_warn(port->dev, "clock rate change rejected\n"); 501 return NOTIFY_BAD; 502 } 503 504 spin_lock_irqsave(&cdns_uart->port->lock, flags); 505 506 /* Disable the TX and RX to set baud rate */ 507 ctrl_reg = readl(port->membase + CDNS_UART_CR); 508 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS; 509 writel(ctrl_reg, port->membase + CDNS_UART_CR); 510 511 spin_unlock_irqrestore(&cdns_uart->port->lock, flags); 512 513 return NOTIFY_OK; 514 } 515 case POST_RATE_CHANGE: 516 /* 517 * Set clk dividers to generate correct baud with new clock 518 * frequency. 519 */ 520 521 spin_lock_irqsave(&cdns_uart->port->lock, flags); 522 523 locked = 1; 524 port->uartclk = ndata->new_rate; 525 526 cdns_uart->baud = cdns_uart_set_baud_rate(cdns_uart->port, 527 cdns_uart->baud); 528 /* fall through */ 529 case ABORT_RATE_CHANGE: 530 if (!locked) 531 spin_lock_irqsave(&cdns_uart->port->lock, flags); 532 533 /* Set TX/RX Reset */ 534 ctrl_reg = readl(port->membase + CDNS_UART_CR); 535 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST; 536 writel(ctrl_reg, port->membase + CDNS_UART_CR); 537 538 while (readl(port->membase + CDNS_UART_CR) & 539 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST)) 540 cpu_relax(); 541 542 /* 543 * Clear the RX disable and TX disable bits and then set the TX 544 * enable bit and RX enable bit to enable the transmitter and 545 * receiver. 546 */ 547 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT); 548 ctrl_reg = readl(port->membase + CDNS_UART_CR); 549 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS); 550 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN; 551 writel(ctrl_reg, port->membase + CDNS_UART_CR); 552 553 spin_unlock_irqrestore(&cdns_uart->port->lock, flags); 554 555 return NOTIFY_OK; 556 default: 557 return NOTIFY_DONE; 558 } 559 } 560 #endif 561 562 /** 563 * cdns_uart_start_tx - Start transmitting bytes 564 * @port: Handle to the uart port structure 565 */ 566 static void cdns_uart_start_tx(struct uart_port *port) 567 { 568 unsigned int status; 569 570 if (uart_tx_stopped(port)) 571 return; 572 573 /* 574 * Set the TX enable bit and clear the TX disable bit to enable the 575 * transmitter. 576 */ 577 status = readl(port->membase + CDNS_UART_CR); 578 status &= ~CDNS_UART_CR_TX_DIS; 579 status |= CDNS_UART_CR_TX_EN; 580 writel(status, port->membase + CDNS_UART_CR); 581 582 if (uart_circ_empty(&port->state->xmit)) 583 return; 584 585 cdns_uart_handle_tx(port); 586 587 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR); 588 /* Enable the TX Empty interrupt */ 589 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IER); 590 } 591 592 /** 593 * cdns_uart_stop_tx - Stop TX 594 * @port: Handle to the uart port structure 595 */ 596 static void cdns_uart_stop_tx(struct uart_port *port) 597 { 598 unsigned int regval; 599 600 regval = readl(port->membase + CDNS_UART_CR); 601 regval |= CDNS_UART_CR_TX_DIS; 602 /* Disable the transmitter */ 603 writel(regval, port->membase + CDNS_UART_CR); 604 } 605 606 /** 607 * cdns_uart_stop_rx - Stop RX 608 * @port: Handle to the uart port structure 609 */ 610 static void cdns_uart_stop_rx(struct uart_port *port) 611 { 612 unsigned int regval; 613 614 /* Disable RX IRQs */ 615 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IDR); 616 617 /* Disable the receiver */ 618 regval = readl(port->membase + CDNS_UART_CR); 619 regval |= CDNS_UART_CR_RX_DIS; 620 writel(regval, port->membase + CDNS_UART_CR); 621 } 622 623 /** 624 * cdns_uart_tx_empty - Check whether TX is empty 625 * @port: Handle to the uart port structure 626 * 627 * Return: TIOCSER_TEMT on success, 0 otherwise 628 */ 629 static unsigned int cdns_uart_tx_empty(struct uart_port *port) 630 { 631 unsigned int status; 632 633 status = readl(port->membase + CDNS_UART_SR) & 634 CDNS_UART_SR_TXEMPTY; 635 return status ? TIOCSER_TEMT : 0; 636 } 637 638 /** 639 * cdns_uart_break_ctl - Based on the input ctl we have to start or stop 640 * transmitting char breaks 641 * @port: Handle to the uart port structure 642 * @ctl: Value based on which start or stop decision is taken 643 */ 644 static void cdns_uart_break_ctl(struct uart_port *port, int ctl) 645 { 646 unsigned int status; 647 unsigned long flags; 648 649 spin_lock_irqsave(&port->lock, flags); 650 651 status = readl(port->membase + CDNS_UART_CR); 652 653 if (ctl == -1) 654 writel(CDNS_UART_CR_STARTBRK | status, 655 port->membase + CDNS_UART_CR); 656 else { 657 if ((status & CDNS_UART_CR_STOPBRK) == 0) 658 writel(CDNS_UART_CR_STOPBRK | status, 659 port->membase + CDNS_UART_CR); 660 } 661 spin_unlock_irqrestore(&port->lock, flags); 662 } 663 664 /** 665 * cdns_uart_set_termios - termios operations, handling data length, parity, 666 * stop bits, flow control, baud rate 667 * @port: Handle to the uart port structure 668 * @termios: Handle to the input termios structure 669 * @old: Values of the previously saved termios structure 670 */ 671 static void cdns_uart_set_termios(struct uart_port *port, 672 struct ktermios *termios, struct ktermios *old) 673 { 674 unsigned int cval = 0; 675 unsigned int baud, minbaud, maxbaud; 676 unsigned long flags; 677 unsigned int ctrl_reg, mode_reg; 678 679 spin_lock_irqsave(&port->lock, flags); 680 681 /* Wait for the transmit FIFO to empty before making changes */ 682 if (!(readl(port->membase + CDNS_UART_CR) & 683 CDNS_UART_CR_TX_DIS)) { 684 while (!(readl(port->membase + CDNS_UART_SR) & 685 CDNS_UART_SR_TXEMPTY)) { 686 cpu_relax(); 687 } 688 } 689 690 /* Disable the TX and RX to set baud rate */ 691 ctrl_reg = readl(port->membase + CDNS_UART_CR); 692 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS; 693 writel(ctrl_reg, port->membase + CDNS_UART_CR); 694 695 /* 696 * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk 697 * min and max baud should be calculated here based on port->uartclk. 698 * this way we get a valid baud and can safely call set_baud() 699 */ 700 minbaud = port->uartclk / 701 ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX * 8); 702 maxbaud = port->uartclk / (CDNS_UART_BDIV_MIN + 1); 703 baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud); 704 baud = cdns_uart_set_baud_rate(port, baud); 705 if (tty_termios_baud_rate(termios)) 706 tty_termios_encode_baud_rate(termios, baud, baud); 707 708 /* Update the per-port timeout. */ 709 uart_update_timeout(port, termios->c_cflag, baud); 710 711 /* Set TX/RX Reset */ 712 ctrl_reg = readl(port->membase + CDNS_UART_CR); 713 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST; 714 writel(ctrl_reg, port->membase + CDNS_UART_CR); 715 716 while (readl(port->membase + CDNS_UART_CR) & 717 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST)) 718 cpu_relax(); 719 720 /* 721 * Clear the RX disable and TX disable bits and then set the TX enable 722 * bit and RX enable bit to enable the transmitter and receiver. 723 */ 724 ctrl_reg = readl(port->membase + CDNS_UART_CR); 725 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS); 726 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN; 727 writel(ctrl_reg, port->membase + CDNS_UART_CR); 728 729 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT); 730 731 port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG | 732 CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT; 733 port->ignore_status_mask = 0; 734 735 if (termios->c_iflag & INPCK) 736 port->read_status_mask |= CDNS_UART_IXR_PARITY | 737 CDNS_UART_IXR_FRAMING; 738 739 if (termios->c_iflag & IGNPAR) 740 port->ignore_status_mask |= CDNS_UART_IXR_PARITY | 741 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN; 742 743 /* ignore all characters if CREAD is not set */ 744 if ((termios->c_cflag & CREAD) == 0) 745 port->ignore_status_mask |= CDNS_UART_IXR_RXTRIG | 746 CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY | 747 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN; 748 749 mode_reg = readl(port->membase + CDNS_UART_MR); 750 751 /* Handling Data Size */ 752 switch (termios->c_cflag & CSIZE) { 753 case CS6: 754 cval |= CDNS_UART_MR_CHARLEN_6_BIT; 755 break; 756 case CS7: 757 cval |= CDNS_UART_MR_CHARLEN_7_BIT; 758 break; 759 default: 760 case CS8: 761 cval |= CDNS_UART_MR_CHARLEN_8_BIT; 762 termios->c_cflag &= ~CSIZE; 763 termios->c_cflag |= CS8; 764 break; 765 } 766 767 /* Handling Parity and Stop Bits length */ 768 if (termios->c_cflag & CSTOPB) 769 cval |= CDNS_UART_MR_STOPMODE_2_BIT; /* 2 STOP bits */ 770 else 771 cval |= CDNS_UART_MR_STOPMODE_1_BIT; /* 1 STOP bit */ 772 773 if (termios->c_cflag & PARENB) { 774 /* Mark or Space parity */ 775 if (termios->c_cflag & CMSPAR) { 776 if (termios->c_cflag & PARODD) 777 cval |= CDNS_UART_MR_PARITY_MARK; 778 else 779 cval |= CDNS_UART_MR_PARITY_SPACE; 780 } else { 781 if (termios->c_cflag & PARODD) 782 cval |= CDNS_UART_MR_PARITY_ODD; 783 else 784 cval |= CDNS_UART_MR_PARITY_EVEN; 785 } 786 } else { 787 cval |= CDNS_UART_MR_PARITY_NONE; 788 } 789 cval |= mode_reg & 1; 790 writel(cval, port->membase + CDNS_UART_MR); 791 792 spin_unlock_irqrestore(&port->lock, flags); 793 } 794 795 /** 796 * cdns_uart_startup - Called when an application opens a cdns_uart port 797 * @port: Handle to the uart port structure 798 * 799 * Return: 0 on success, negative errno otherwise 800 */ 801 static int cdns_uart_startup(struct uart_port *port) 802 { 803 struct cdns_uart *cdns_uart = port->private_data; 804 bool is_brk_support; 805 int ret; 806 unsigned long flags; 807 unsigned int status = 0; 808 809 is_brk_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT; 810 811 spin_lock_irqsave(&port->lock, flags); 812 813 /* Disable the TX and RX */ 814 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS, 815 port->membase + CDNS_UART_CR); 816 817 /* Set the Control Register with TX/RX Enable, TX/RX Reset, 818 * no break chars. 819 */ 820 writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST, 821 port->membase + CDNS_UART_CR); 822 823 while (readl(port->membase + CDNS_UART_CR) & 824 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST)) 825 cpu_relax(); 826 827 /* 828 * Clear the RX disable bit and then set the RX enable bit to enable 829 * the receiver. 830 */ 831 status = readl(port->membase + CDNS_UART_CR); 832 status &= CDNS_UART_CR_RX_DIS; 833 status |= CDNS_UART_CR_RX_EN; 834 writel(status, port->membase + CDNS_UART_CR); 835 836 /* Set the Mode Register with normal mode,8 data bits,1 stop bit, 837 * no parity. 838 */ 839 writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT 840 | CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT, 841 port->membase + CDNS_UART_MR); 842 843 /* 844 * Set the RX FIFO Trigger level to use most of the FIFO, but it 845 * can be tuned with a module parameter 846 */ 847 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM); 848 849 /* 850 * Receive Timeout register is enabled but it 851 * can be tuned with a module parameter 852 */ 853 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT); 854 855 /* Clear out any pending interrupts before enabling them */ 856 writel(readl(port->membase + CDNS_UART_ISR), 857 port->membase + CDNS_UART_ISR); 858 859 spin_unlock_irqrestore(&port->lock, flags); 860 861 ret = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME, port); 862 if (ret) { 863 dev_err(port->dev, "request_irq '%d' failed with %d\n", 864 port->irq, ret); 865 return ret; 866 } 867 868 /* Set the Interrupt Registers with desired interrupts */ 869 if (is_brk_support) 870 writel(CDNS_UART_RX_IRQS | CDNS_UART_IXR_BRK, 871 port->membase + CDNS_UART_IER); 872 else 873 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IER); 874 875 return 0; 876 } 877 878 /** 879 * cdns_uart_shutdown - Called when an application closes a cdns_uart port 880 * @port: Handle to the uart port structure 881 */ 882 static void cdns_uart_shutdown(struct uart_port *port) 883 { 884 int status; 885 unsigned long flags; 886 887 spin_lock_irqsave(&port->lock, flags); 888 889 /* Disable interrupts */ 890 status = readl(port->membase + CDNS_UART_IMR); 891 writel(status, port->membase + CDNS_UART_IDR); 892 writel(0xffffffff, port->membase + CDNS_UART_ISR); 893 894 /* Disable the TX and RX */ 895 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS, 896 port->membase + CDNS_UART_CR); 897 898 spin_unlock_irqrestore(&port->lock, flags); 899 900 free_irq(port->irq, port); 901 } 902 903 /** 904 * cdns_uart_type - Set UART type to cdns_uart port 905 * @port: Handle to the uart port structure 906 * 907 * Return: string on success, NULL otherwise 908 */ 909 static const char *cdns_uart_type(struct uart_port *port) 910 { 911 return port->type == PORT_XUARTPS ? CDNS_UART_NAME : NULL; 912 } 913 914 /** 915 * cdns_uart_verify_port - Verify the port params 916 * @port: Handle to the uart port structure 917 * @ser: Handle to the structure whose members are compared 918 * 919 * Return: 0 on success, negative errno otherwise. 920 */ 921 static int cdns_uart_verify_port(struct uart_port *port, 922 struct serial_struct *ser) 923 { 924 if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS) 925 return -EINVAL; 926 if (port->irq != ser->irq) 927 return -EINVAL; 928 if (ser->io_type != UPIO_MEM) 929 return -EINVAL; 930 if (port->iobase != ser->port) 931 return -EINVAL; 932 if (ser->hub6 != 0) 933 return -EINVAL; 934 return 0; 935 } 936 937 /** 938 * cdns_uart_request_port - Claim the memory region attached to cdns_uart port, 939 * called when the driver adds a cdns_uart port via 940 * uart_add_one_port() 941 * @port: Handle to the uart port structure 942 * 943 * Return: 0 on success, negative errno otherwise. 944 */ 945 static int cdns_uart_request_port(struct uart_port *port) 946 { 947 if (!request_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE, 948 CDNS_UART_NAME)) { 949 return -ENOMEM; 950 } 951 952 port->membase = ioremap(port->mapbase, CDNS_UART_REGISTER_SPACE); 953 if (!port->membase) { 954 dev_err(port->dev, "Unable to map registers\n"); 955 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE); 956 return -ENOMEM; 957 } 958 return 0; 959 } 960 961 /** 962 * cdns_uart_release_port - Release UART port 963 * @port: Handle to the uart port structure 964 * 965 * Release the memory region attached to a cdns_uart port. Called when the 966 * driver removes a cdns_uart port via uart_remove_one_port(). 967 */ 968 static void cdns_uart_release_port(struct uart_port *port) 969 { 970 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE); 971 iounmap(port->membase); 972 port->membase = NULL; 973 } 974 975 /** 976 * cdns_uart_config_port - Configure UART port 977 * @port: Handle to the uart port structure 978 * @flags: If any 979 */ 980 static void cdns_uart_config_port(struct uart_port *port, int flags) 981 { 982 if (flags & UART_CONFIG_TYPE && cdns_uart_request_port(port) == 0) 983 port->type = PORT_XUARTPS; 984 } 985 986 /** 987 * cdns_uart_get_mctrl - Get the modem control state 988 * @port: Handle to the uart port structure 989 * 990 * Return: the modem control state 991 */ 992 static unsigned int cdns_uart_get_mctrl(struct uart_port *port) 993 { 994 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; 995 } 996 997 static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 998 { 999 u32 val; 1000 u32 mode_reg; 1001 1002 val = readl(port->membase + CDNS_UART_MODEMCR); 1003 mode_reg = readl(port->membase + CDNS_UART_MR); 1004 1005 val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR); 1006 mode_reg &= ~CDNS_UART_MR_CHMODE_MASK; 1007 1008 if (mctrl & TIOCM_RTS) 1009 val |= CDNS_UART_MODEMCR_RTS; 1010 if (mctrl & TIOCM_DTR) 1011 val |= CDNS_UART_MODEMCR_DTR; 1012 if (mctrl & TIOCM_LOOP) 1013 mode_reg |= CDNS_UART_MR_CHMODE_L_LOOP; 1014 else 1015 mode_reg |= CDNS_UART_MR_CHMODE_NORM; 1016 1017 writel(val, port->membase + CDNS_UART_MODEMCR); 1018 writel(mode_reg, port->membase + CDNS_UART_MR); 1019 } 1020 1021 #ifdef CONFIG_CONSOLE_POLL 1022 static int cdns_uart_poll_get_char(struct uart_port *port) 1023 { 1024 int c; 1025 unsigned long flags; 1026 1027 spin_lock_irqsave(&port->lock, flags); 1028 1029 /* Check if FIFO is empty */ 1030 if (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_RXEMPTY) 1031 c = NO_POLL_CHAR; 1032 else /* Read a character */ 1033 c = (unsigned char) readl(port->membase + CDNS_UART_FIFO); 1034 1035 spin_unlock_irqrestore(&port->lock, flags); 1036 1037 return c; 1038 } 1039 1040 static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c) 1041 { 1042 unsigned long flags; 1043 1044 spin_lock_irqsave(&port->lock, flags); 1045 1046 /* Wait until FIFO is empty */ 1047 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY)) 1048 cpu_relax(); 1049 1050 /* Write a character */ 1051 writel(c, port->membase + CDNS_UART_FIFO); 1052 1053 /* Wait until FIFO is empty */ 1054 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY)) 1055 cpu_relax(); 1056 1057 spin_unlock_irqrestore(&port->lock, flags); 1058 1059 return; 1060 } 1061 #endif 1062 1063 static void cdns_uart_pm(struct uart_port *port, unsigned int state, 1064 unsigned int oldstate) 1065 { 1066 switch (state) { 1067 case UART_PM_STATE_OFF: 1068 pm_runtime_mark_last_busy(port->dev); 1069 pm_runtime_put_autosuspend(port->dev); 1070 break; 1071 default: 1072 pm_runtime_get_sync(port->dev); 1073 break; 1074 } 1075 } 1076 1077 static const struct uart_ops cdns_uart_ops = { 1078 .set_mctrl = cdns_uart_set_mctrl, 1079 .get_mctrl = cdns_uart_get_mctrl, 1080 .start_tx = cdns_uart_start_tx, 1081 .stop_tx = cdns_uart_stop_tx, 1082 .stop_rx = cdns_uart_stop_rx, 1083 .tx_empty = cdns_uart_tx_empty, 1084 .break_ctl = cdns_uart_break_ctl, 1085 .set_termios = cdns_uart_set_termios, 1086 .startup = cdns_uart_startup, 1087 .shutdown = cdns_uart_shutdown, 1088 .pm = cdns_uart_pm, 1089 .type = cdns_uart_type, 1090 .verify_port = cdns_uart_verify_port, 1091 .request_port = cdns_uart_request_port, 1092 .release_port = cdns_uart_release_port, 1093 .config_port = cdns_uart_config_port, 1094 #ifdef CONFIG_CONSOLE_POLL 1095 .poll_get_char = cdns_uart_poll_get_char, 1096 .poll_put_char = cdns_uart_poll_put_char, 1097 #endif 1098 }; 1099 1100 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE 1101 /** 1102 * cdns_uart_console_wait_tx - Wait for the TX to be full 1103 * @port: Handle to the uart port structure 1104 */ 1105 static void cdns_uart_console_wait_tx(struct uart_port *port) 1106 { 1107 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY)) 1108 barrier(); 1109 } 1110 1111 /** 1112 * cdns_uart_console_putchar - write the character to the FIFO buffer 1113 * @port: Handle to the uart port structure 1114 * @ch: Character to be written 1115 */ 1116 static void cdns_uart_console_putchar(struct uart_port *port, int ch) 1117 { 1118 cdns_uart_console_wait_tx(port); 1119 writel(ch, port->membase + CDNS_UART_FIFO); 1120 } 1121 1122 static void cdns_early_write(struct console *con, const char *s, 1123 unsigned n) 1124 { 1125 struct earlycon_device *dev = con->data; 1126 1127 uart_console_write(&dev->port, s, n, cdns_uart_console_putchar); 1128 } 1129 1130 static int __init cdns_early_console_setup(struct earlycon_device *device, 1131 const char *opt) 1132 { 1133 struct uart_port *port = &device->port; 1134 1135 if (!port->membase) 1136 return -ENODEV; 1137 1138 /* initialise control register */ 1139 writel(CDNS_UART_CR_TX_EN|CDNS_UART_CR_TXRST|CDNS_UART_CR_RXRST, 1140 port->membase + CDNS_UART_CR); 1141 1142 /* only set baud if specified on command line - otherwise 1143 * assume it has been initialized by a boot loader. 1144 */ 1145 if (port->uartclk && device->baud) { 1146 u32 cd = 0, bdiv = 0; 1147 u32 mr; 1148 int div8; 1149 1150 cdns_uart_calc_baud_divs(port->uartclk, device->baud, 1151 &bdiv, &cd, &div8); 1152 mr = CDNS_UART_MR_PARITY_NONE; 1153 if (div8) 1154 mr |= CDNS_UART_MR_CLKSEL; 1155 1156 writel(mr, port->membase + CDNS_UART_MR); 1157 writel(cd, port->membase + CDNS_UART_BAUDGEN); 1158 writel(bdiv, port->membase + CDNS_UART_BAUDDIV); 1159 } 1160 1161 device->con->write = cdns_early_write; 1162 1163 return 0; 1164 } 1165 OF_EARLYCON_DECLARE(cdns, "xlnx,xuartps", cdns_early_console_setup); 1166 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p8", cdns_early_console_setup); 1167 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p12", cdns_early_console_setup); 1168 OF_EARLYCON_DECLARE(cdns, "xlnx,zynqmp-uart", cdns_early_console_setup); 1169 1170 1171 /* Static pointer to console port */ 1172 static struct uart_port *console_port; 1173 1174 /** 1175 * cdns_uart_console_write - perform write operation 1176 * @co: Console handle 1177 * @s: Pointer to character array 1178 * @count: No of characters 1179 */ 1180 static void cdns_uart_console_write(struct console *co, const char *s, 1181 unsigned int count) 1182 { 1183 struct uart_port *port = console_port; 1184 unsigned long flags; 1185 unsigned int imr, ctrl; 1186 int locked = 1; 1187 1188 if (port->sysrq) 1189 locked = 0; 1190 else if (oops_in_progress) 1191 locked = spin_trylock_irqsave(&port->lock, flags); 1192 else 1193 spin_lock_irqsave(&port->lock, flags); 1194 1195 /* save and disable interrupt */ 1196 imr = readl(port->membase + CDNS_UART_IMR); 1197 writel(imr, port->membase + CDNS_UART_IDR); 1198 1199 /* 1200 * Make sure that the tx part is enabled. Set the TX enable bit and 1201 * clear the TX disable bit to enable the transmitter. 1202 */ 1203 ctrl = readl(port->membase + CDNS_UART_CR); 1204 ctrl &= ~CDNS_UART_CR_TX_DIS; 1205 ctrl |= CDNS_UART_CR_TX_EN; 1206 writel(ctrl, port->membase + CDNS_UART_CR); 1207 1208 uart_console_write(port, s, count, cdns_uart_console_putchar); 1209 cdns_uart_console_wait_tx(port); 1210 1211 writel(ctrl, port->membase + CDNS_UART_CR); 1212 1213 /* restore interrupt state */ 1214 writel(imr, port->membase + CDNS_UART_IER); 1215 1216 if (locked) 1217 spin_unlock_irqrestore(&port->lock, flags); 1218 } 1219 1220 /** 1221 * cdns_uart_console_setup - Initialize the uart to default config 1222 * @co: Console handle 1223 * @options: Initial settings of uart 1224 * 1225 * Return: 0 on success, negative errno otherwise. 1226 */ 1227 static int __init cdns_uart_console_setup(struct console *co, char *options) 1228 { 1229 struct uart_port *port = console_port; 1230 1231 int baud = 9600; 1232 int bits = 8; 1233 int parity = 'n'; 1234 int flow = 'n'; 1235 1236 if (!port->membase) { 1237 pr_debug("console on " CDNS_UART_TTY_NAME "%i not present\n", 1238 co->index); 1239 return -ENODEV; 1240 } 1241 1242 if (options) 1243 uart_parse_options(options, &baud, &parity, &bits, &flow); 1244 1245 return uart_set_options(port, co, baud, parity, bits, flow); 1246 } 1247 1248 static struct uart_driver cdns_uart_uart_driver; 1249 1250 static struct console cdns_uart_console = { 1251 .name = CDNS_UART_TTY_NAME, 1252 .write = cdns_uart_console_write, 1253 .device = uart_console_device, 1254 .setup = cdns_uart_console_setup, 1255 .flags = CON_PRINTBUFFER, 1256 .index = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */ 1257 .data = &cdns_uart_uart_driver, 1258 }; 1259 #endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */ 1260 1261 static struct uart_driver cdns_uart_uart_driver = { 1262 .owner = THIS_MODULE, 1263 .driver_name = CDNS_UART_NAME, 1264 .dev_name = CDNS_UART_TTY_NAME, 1265 .major = CDNS_UART_MAJOR, 1266 .minor = CDNS_UART_MINOR, 1267 .nr = CDNS_UART_NR_PORTS, 1268 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE 1269 .cons = &cdns_uart_console, 1270 #endif 1271 }; 1272 1273 #ifdef CONFIG_PM_SLEEP 1274 /** 1275 * cdns_uart_suspend - suspend event 1276 * @device: Pointer to the device structure 1277 * 1278 * Return: 0 1279 */ 1280 static int cdns_uart_suspend(struct device *device) 1281 { 1282 struct uart_port *port = dev_get_drvdata(device); 1283 struct tty_struct *tty; 1284 struct device *tty_dev; 1285 int may_wake = 0; 1286 1287 /* Get the tty which could be NULL so don't assume it's valid */ 1288 tty = tty_port_tty_get(&port->state->port); 1289 if (tty) { 1290 tty_dev = tty->dev; 1291 may_wake = device_may_wakeup(tty_dev); 1292 tty_kref_put(tty); 1293 } 1294 1295 /* 1296 * Call the API provided in serial_core.c file which handles 1297 * the suspend. 1298 */ 1299 uart_suspend_port(&cdns_uart_uart_driver, port); 1300 if (!(console_suspend_enabled && !may_wake)) { 1301 unsigned long flags = 0; 1302 1303 spin_lock_irqsave(&port->lock, flags); 1304 /* Empty the receive FIFO 1st before making changes */ 1305 while (!(readl(port->membase + CDNS_UART_SR) & 1306 CDNS_UART_SR_RXEMPTY)) 1307 readl(port->membase + CDNS_UART_FIFO); 1308 /* set RX trigger level to 1 */ 1309 writel(1, port->membase + CDNS_UART_RXWM); 1310 /* disable RX timeout interrups */ 1311 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IDR); 1312 spin_unlock_irqrestore(&port->lock, flags); 1313 } 1314 1315 return 0; 1316 } 1317 1318 /** 1319 * cdns_uart_resume - Resume after a previous suspend 1320 * @device: Pointer to the device structure 1321 * 1322 * Return: 0 1323 */ 1324 static int cdns_uart_resume(struct device *device) 1325 { 1326 struct uart_port *port = dev_get_drvdata(device); 1327 unsigned long flags = 0; 1328 u32 ctrl_reg; 1329 struct tty_struct *tty; 1330 struct device *tty_dev; 1331 int may_wake = 0; 1332 1333 /* Get the tty which could be NULL so don't assume it's valid */ 1334 tty = tty_port_tty_get(&port->state->port); 1335 if (tty) { 1336 tty_dev = tty->dev; 1337 may_wake = device_may_wakeup(tty_dev); 1338 tty_kref_put(tty); 1339 } 1340 1341 if (console_suspend_enabled && !may_wake) { 1342 struct cdns_uart *cdns_uart = port->private_data; 1343 1344 clk_enable(cdns_uart->pclk); 1345 clk_enable(cdns_uart->uartclk); 1346 1347 spin_lock_irqsave(&port->lock, flags); 1348 1349 /* Set TX/RX Reset */ 1350 ctrl_reg = readl(port->membase + CDNS_UART_CR); 1351 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST; 1352 writel(ctrl_reg, port->membase + CDNS_UART_CR); 1353 while (readl(port->membase + CDNS_UART_CR) & 1354 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST)) 1355 cpu_relax(); 1356 1357 /* restore rx timeout value */ 1358 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT); 1359 /* Enable Tx/Rx */ 1360 ctrl_reg = readl(port->membase + CDNS_UART_CR); 1361 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS); 1362 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN; 1363 writel(ctrl_reg, port->membase + CDNS_UART_CR); 1364 1365 clk_disable(cdns_uart->uartclk); 1366 clk_disable(cdns_uart->pclk); 1367 spin_unlock_irqrestore(&port->lock, flags); 1368 } else { 1369 spin_lock_irqsave(&port->lock, flags); 1370 /* restore original rx trigger level */ 1371 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM); 1372 /* enable RX timeout interrupt */ 1373 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IER); 1374 spin_unlock_irqrestore(&port->lock, flags); 1375 } 1376 1377 return uart_resume_port(&cdns_uart_uart_driver, port); 1378 } 1379 #endif /* ! CONFIG_PM_SLEEP */ 1380 static int __maybe_unused cdns_runtime_suspend(struct device *dev) 1381 { 1382 struct uart_port *port = dev_get_drvdata(dev); 1383 struct cdns_uart *cdns_uart = port->private_data; 1384 1385 clk_disable(cdns_uart->uartclk); 1386 clk_disable(cdns_uart->pclk); 1387 return 0; 1388 }; 1389 1390 static int __maybe_unused cdns_runtime_resume(struct device *dev) 1391 { 1392 struct uart_port *port = dev_get_drvdata(dev); 1393 struct cdns_uart *cdns_uart = port->private_data; 1394 1395 clk_enable(cdns_uart->pclk); 1396 clk_enable(cdns_uart->uartclk); 1397 return 0; 1398 }; 1399 1400 static const struct dev_pm_ops cdns_uart_dev_pm_ops = { 1401 SET_SYSTEM_SLEEP_PM_OPS(cdns_uart_suspend, cdns_uart_resume) 1402 SET_RUNTIME_PM_OPS(cdns_runtime_suspend, 1403 cdns_runtime_resume, NULL) 1404 }; 1405 1406 static const struct cdns_platform_data zynqmp_uart_def = { 1407 .quirks = CDNS_UART_RXBS_SUPPORT, }; 1408 1409 /* Match table for of_platform binding */ 1410 static const struct of_device_id cdns_uart_of_match[] = { 1411 { .compatible = "xlnx,xuartps", }, 1412 { .compatible = "cdns,uart-r1p8", }, 1413 { .compatible = "cdns,uart-r1p12", .data = &zynqmp_uart_def }, 1414 { .compatible = "xlnx,zynqmp-uart", .data = &zynqmp_uart_def }, 1415 {} 1416 }; 1417 MODULE_DEVICE_TABLE(of, cdns_uart_of_match); 1418 1419 /** 1420 * cdns_uart_probe - Platform driver probe 1421 * @pdev: Pointer to the platform device structure 1422 * 1423 * Return: 0 on success, negative errno otherwise 1424 */ 1425 static int cdns_uart_probe(struct platform_device *pdev) 1426 { 1427 int rc, id, irq; 1428 struct uart_port *port; 1429 struct resource *res; 1430 struct cdns_uart *cdns_uart_data; 1431 const struct of_device_id *match; 1432 1433 cdns_uart_data = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_data), 1434 GFP_KERNEL); 1435 if (!cdns_uart_data) 1436 return -ENOMEM; 1437 port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL); 1438 if (!port) 1439 return -ENOMEM; 1440 1441 match = of_match_node(cdns_uart_of_match, pdev->dev.of_node); 1442 if (match && match->data) { 1443 const struct cdns_platform_data *data = match->data; 1444 1445 cdns_uart_data->quirks = data->quirks; 1446 } 1447 1448 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "pclk"); 1449 if (IS_ERR(cdns_uart_data->pclk)) { 1450 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "aper_clk"); 1451 if (!IS_ERR(cdns_uart_data->pclk)) 1452 dev_err(&pdev->dev, "clock name 'aper_clk' is deprecated.\n"); 1453 } 1454 if (IS_ERR(cdns_uart_data->pclk)) { 1455 dev_err(&pdev->dev, "pclk clock not found.\n"); 1456 return PTR_ERR(cdns_uart_data->pclk); 1457 } 1458 1459 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "uart_clk"); 1460 if (IS_ERR(cdns_uart_data->uartclk)) { 1461 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "ref_clk"); 1462 if (!IS_ERR(cdns_uart_data->uartclk)) 1463 dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n"); 1464 } 1465 if (IS_ERR(cdns_uart_data->uartclk)) { 1466 dev_err(&pdev->dev, "uart_clk clock not found.\n"); 1467 return PTR_ERR(cdns_uart_data->uartclk); 1468 } 1469 1470 rc = clk_prepare_enable(cdns_uart_data->pclk); 1471 if (rc) { 1472 dev_err(&pdev->dev, "Unable to enable pclk clock.\n"); 1473 return rc; 1474 } 1475 rc = clk_prepare_enable(cdns_uart_data->uartclk); 1476 if (rc) { 1477 dev_err(&pdev->dev, "Unable to enable device clock.\n"); 1478 goto err_out_clk_dis_pclk; 1479 } 1480 1481 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1482 if (!res) { 1483 rc = -ENODEV; 1484 goto err_out_clk_disable; 1485 } 1486 1487 irq = platform_get_irq(pdev, 0); 1488 if (irq <= 0) { 1489 rc = -ENXIO; 1490 goto err_out_clk_disable; 1491 } 1492 1493 #ifdef CONFIG_COMMON_CLK 1494 cdns_uart_data->clk_rate_change_nb.notifier_call = 1495 cdns_uart_clk_notifier_cb; 1496 if (clk_notifier_register(cdns_uart_data->uartclk, 1497 &cdns_uart_data->clk_rate_change_nb)) 1498 dev_warn(&pdev->dev, "Unable to register clock notifier.\n"); 1499 #endif 1500 /* Look for a serialN alias */ 1501 id = of_alias_get_id(pdev->dev.of_node, "serial"); 1502 if (id < 0) 1503 id = 0; 1504 1505 if (id >= CDNS_UART_NR_PORTS) { 1506 dev_err(&pdev->dev, "Cannot get uart_port structure\n"); 1507 rc = -ENODEV; 1508 goto err_out_notif_unreg; 1509 } 1510 1511 /* At this point, we've got an empty uart_port struct, initialize it */ 1512 spin_lock_init(&port->lock); 1513 port->membase = NULL; 1514 port->irq = 0; 1515 port->type = PORT_UNKNOWN; 1516 port->iotype = UPIO_MEM32; 1517 port->flags = UPF_BOOT_AUTOCONF; 1518 port->ops = &cdns_uart_ops; 1519 port->fifosize = CDNS_UART_FIFO_SIZE; 1520 port->line = id; 1521 port->dev = NULL; 1522 1523 /* 1524 * Register the port. 1525 * This function also registers this device with the tty layer 1526 * and triggers invocation of the config_port() entry point. 1527 */ 1528 port->mapbase = res->start; 1529 port->irq = irq; 1530 port->dev = &pdev->dev; 1531 port->uartclk = clk_get_rate(cdns_uart_data->uartclk); 1532 port->private_data = cdns_uart_data; 1533 cdns_uart_data->port = port; 1534 platform_set_drvdata(pdev, port); 1535 1536 pm_runtime_use_autosuspend(&pdev->dev); 1537 pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT); 1538 pm_runtime_set_active(&pdev->dev); 1539 pm_runtime_enable(&pdev->dev); 1540 1541 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE 1542 /* 1543 * If console hasn't been found yet try to assign this port 1544 * because it is required to be assigned for console setup function. 1545 * If register_console() don't assign value, then console_port pointer 1546 * is cleanup. 1547 */ 1548 if (cdns_uart_uart_driver.cons->index == -1) 1549 console_port = port; 1550 #endif 1551 1552 rc = uart_add_one_port(&cdns_uart_uart_driver, port); 1553 if (rc) { 1554 dev_err(&pdev->dev, 1555 "uart_add_one_port() failed; err=%i\n", rc); 1556 goto err_out_pm_disable; 1557 } 1558 1559 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE 1560 /* This is not port which is used for console that's why clean it up */ 1561 if (cdns_uart_uart_driver.cons->index == -1) 1562 console_port = NULL; 1563 #endif 1564 1565 return 0; 1566 1567 err_out_pm_disable: 1568 pm_runtime_disable(&pdev->dev); 1569 pm_runtime_set_suspended(&pdev->dev); 1570 pm_runtime_dont_use_autosuspend(&pdev->dev); 1571 err_out_notif_unreg: 1572 #ifdef CONFIG_COMMON_CLK 1573 clk_notifier_unregister(cdns_uart_data->uartclk, 1574 &cdns_uart_data->clk_rate_change_nb); 1575 #endif 1576 err_out_clk_disable: 1577 clk_disable_unprepare(cdns_uart_data->uartclk); 1578 err_out_clk_dis_pclk: 1579 clk_disable_unprepare(cdns_uart_data->pclk); 1580 1581 return rc; 1582 } 1583 1584 /** 1585 * cdns_uart_remove - called when the platform driver is unregistered 1586 * @pdev: Pointer to the platform device structure 1587 * 1588 * Return: 0 on success, negative errno otherwise 1589 */ 1590 static int cdns_uart_remove(struct platform_device *pdev) 1591 { 1592 struct uart_port *port = platform_get_drvdata(pdev); 1593 struct cdns_uart *cdns_uart_data = port->private_data; 1594 int rc; 1595 1596 /* Remove the cdns_uart port from the serial core */ 1597 #ifdef CONFIG_COMMON_CLK 1598 clk_notifier_unregister(cdns_uart_data->uartclk, 1599 &cdns_uart_data->clk_rate_change_nb); 1600 #endif 1601 rc = uart_remove_one_port(&cdns_uart_uart_driver, port); 1602 port->mapbase = 0; 1603 clk_disable_unprepare(cdns_uart_data->uartclk); 1604 clk_disable_unprepare(cdns_uart_data->pclk); 1605 pm_runtime_disable(&pdev->dev); 1606 pm_runtime_set_suspended(&pdev->dev); 1607 pm_runtime_dont_use_autosuspend(&pdev->dev); 1608 return rc; 1609 } 1610 1611 static struct platform_driver cdns_uart_platform_driver = { 1612 .probe = cdns_uart_probe, 1613 .remove = cdns_uart_remove, 1614 .driver = { 1615 .name = CDNS_UART_NAME, 1616 .of_match_table = cdns_uart_of_match, 1617 .pm = &cdns_uart_dev_pm_ops, 1618 }, 1619 }; 1620 1621 static int __init cdns_uart_init(void) 1622 { 1623 int retval = 0; 1624 1625 /* Register the cdns_uart driver with the serial core */ 1626 retval = uart_register_driver(&cdns_uart_uart_driver); 1627 if (retval) 1628 return retval; 1629 1630 /* Register the platform driver */ 1631 retval = platform_driver_register(&cdns_uart_platform_driver); 1632 if (retval) 1633 uart_unregister_driver(&cdns_uart_uart_driver); 1634 1635 return retval; 1636 } 1637 1638 static void __exit cdns_uart_exit(void) 1639 { 1640 /* Unregister the platform driver */ 1641 platform_driver_unregister(&cdns_uart_platform_driver); 1642 1643 /* Unregister the cdns_uart driver */ 1644 uart_unregister_driver(&cdns_uart_uart_driver); 1645 } 1646 1647 arch_initcall(cdns_uart_init); 1648 module_exit(cdns_uart_exit); 1649 1650 MODULE_DESCRIPTION("Driver for Cadence UART"); 1651 MODULE_AUTHOR("Xilinx Inc."); 1652 MODULE_LICENSE("GPL"); 1653