1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Cadence UART driver (found in Xilinx Zynq) 4 * 5 * Copyright (c) 2011 - 2014 Xilinx, Inc. 6 * 7 * This driver has originally been pushed by Xilinx using a Zynq-branding. This 8 * still shows in the naming of this file, the kconfig symbols and some symbols 9 * in the code. 10 */ 11 12 #include <linux/platform_device.h> 13 #include <linux/serial.h> 14 #include <linux/console.h> 15 #include <linux/serial_core.h> 16 #include <linux/slab.h> 17 #include <linux/tty.h> 18 #include <linux/tty_flip.h> 19 #include <linux/clk.h> 20 #include <linux/irq.h> 21 #include <linux/io.h> 22 #include <linux/of.h> 23 #include <linux/module.h> 24 #include <linux/pm_runtime.h> 25 #include <linux/iopoll.h> 26 27 #define CDNS_UART_TTY_NAME "ttyPS" 28 #define CDNS_UART_NAME "xuartps" 29 #define CDNS_UART_MAJOR 0 /* use dynamic node allocation */ 30 #define CDNS_UART_MINOR 0 /* works best with devtmpfs */ 31 #define CDNS_UART_NR_PORTS 16 32 #define CDNS_UART_FIFO_SIZE 64 /* FIFO size */ 33 #define CDNS_UART_REGISTER_SPACE 0x1000 34 #define TX_TIMEOUT 500000 35 36 /* Rx Trigger level */ 37 static int rx_trigger_level = 56; 38 module_param(rx_trigger_level, uint, 0444); 39 MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes"); 40 41 /* Rx Timeout */ 42 static int rx_timeout = 10; 43 module_param(rx_timeout, uint, 0444); 44 MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255"); 45 46 /* Register offsets for the UART. */ 47 #define CDNS_UART_CR 0x00 /* Control Register */ 48 #define CDNS_UART_MR 0x04 /* Mode Register */ 49 #define CDNS_UART_IER 0x08 /* Interrupt Enable */ 50 #define CDNS_UART_IDR 0x0C /* Interrupt Disable */ 51 #define CDNS_UART_IMR 0x10 /* Interrupt Mask */ 52 #define CDNS_UART_ISR 0x14 /* Interrupt Status */ 53 #define CDNS_UART_BAUDGEN 0x18 /* Baud Rate Generator */ 54 #define CDNS_UART_RXTOUT 0x1C /* RX Timeout */ 55 #define CDNS_UART_RXWM 0x20 /* RX FIFO Trigger Level */ 56 #define CDNS_UART_MODEMCR 0x24 /* Modem Control */ 57 #define CDNS_UART_MODEMSR 0x28 /* Modem Status */ 58 #define CDNS_UART_SR 0x2C /* Channel Status */ 59 #define CDNS_UART_FIFO 0x30 /* FIFO */ 60 #define CDNS_UART_BAUDDIV 0x34 /* Baud Rate Divider */ 61 #define CDNS_UART_FLOWDEL 0x38 /* Flow Delay */ 62 #define CDNS_UART_IRRX_PWIDTH 0x3C /* IR Min Received Pulse Width */ 63 #define CDNS_UART_IRTX_PWIDTH 0x40 /* IR Transmitted pulse Width */ 64 #define CDNS_UART_TXWM 0x44 /* TX FIFO Trigger Level */ 65 #define CDNS_UART_RXBS 0x48 /* RX FIFO byte status register */ 66 67 /* Control Register Bit Definitions */ 68 #define CDNS_UART_CR_STOPBRK 0x00000100 /* Stop TX break */ 69 #define CDNS_UART_CR_STARTBRK 0x00000080 /* Set TX break */ 70 #define CDNS_UART_CR_TX_DIS 0x00000020 /* TX disabled. */ 71 #define CDNS_UART_CR_TX_EN 0x00000010 /* TX enabled */ 72 #define CDNS_UART_CR_RX_DIS 0x00000008 /* RX disabled. */ 73 #define CDNS_UART_CR_RX_EN 0x00000004 /* RX enabled */ 74 #define CDNS_UART_CR_TXRST 0x00000002 /* TX logic reset */ 75 #define CDNS_UART_CR_RXRST 0x00000001 /* RX logic reset */ 76 #define CDNS_UART_CR_RST_TO 0x00000040 /* Restart Timeout Counter */ 77 #define CDNS_UART_RXBS_PARITY 0x00000001 /* Parity error status */ 78 #define CDNS_UART_RXBS_FRAMING 0x00000002 /* Framing error status */ 79 #define CDNS_UART_RXBS_BRK 0x00000004 /* Overrun error status */ 80 81 /* 82 * Mode Register: 83 * The mode register (MR) defines the mode of transfer as well as the data 84 * format. If this register is modified during transmission or reception, 85 * data validity cannot be guaranteed. 86 */ 87 #define CDNS_UART_MR_CLKSEL 0x00000001 /* Pre-scalar selection */ 88 #define CDNS_UART_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */ 89 #define CDNS_UART_MR_CHMODE_NORM 0x00000000 /* Normal mode */ 90 #define CDNS_UART_MR_CHMODE_MASK 0x00000300 /* Mask for mode bits */ 91 92 #define CDNS_UART_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */ 93 #define CDNS_UART_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */ 94 95 #define CDNS_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */ 96 #define CDNS_UART_MR_PARITY_MARK 0x00000018 /* Mark parity mode */ 97 #define CDNS_UART_MR_PARITY_SPACE 0x00000010 /* Space parity mode */ 98 #define CDNS_UART_MR_PARITY_ODD 0x00000008 /* Odd parity mode */ 99 #define CDNS_UART_MR_PARITY_EVEN 0x00000000 /* Even parity mode */ 100 101 #define CDNS_UART_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */ 102 #define CDNS_UART_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */ 103 #define CDNS_UART_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */ 104 105 /* 106 * Interrupt Registers: 107 * Interrupt control logic uses the interrupt enable register (IER) and the 108 * interrupt disable register (IDR) to set the value of the bits in the 109 * interrupt mask register (IMR). The IMR determines whether to pass an 110 * interrupt to the interrupt status register (ISR). 111 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an 112 * interrupt. IMR and ISR are read only, and IER and IDR are write only. 113 * Reading either IER or IDR returns 0x00. 114 * All four registers have the same bit definitions. 115 */ 116 #define CDNS_UART_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */ 117 #define CDNS_UART_IXR_PARITY 0x00000080 /* Parity error interrupt */ 118 #define CDNS_UART_IXR_FRAMING 0x00000040 /* Framing error interrupt */ 119 #define CDNS_UART_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */ 120 #define CDNS_UART_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */ 121 #define CDNS_UART_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */ 122 #define CDNS_UART_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */ 123 #define CDNS_UART_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */ 124 #define CDNS_UART_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */ 125 #define CDNS_UART_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */ 126 #define CDNS_UART_IXR_RXMASK 0x000021e7 /* Valid RX bit mask */ 127 128 /* 129 * Do not enable parity error interrupt for the following 130 * reason: When parity error interrupt is enabled, each Rx 131 * parity error always results in 2 events. The first one 132 * being parity error interrupt and the second one with a 133 * proper Rx interrupt with the incoming data. Disabling 134 * parity error interrupt ensures better handling of parity 135 * error events. With this change, for a parity error case, we 136 * get a Rx interrupt with parity error set in ISR register 137 * and we still handle parity errors in the desired way. 138 */ 139 140 #define CDNS_UART_RX_IRQS (CDNS_UART_IXR_FRAMING | \ 141 CDNS_UART_IXR_OVERRUN | \ 142 CDNS_UART_IXR_RXTRIG | \ 143 CDNS_UART_IXR_TOUT) 144 145 /* Goes in read_status_mask for break detection as the HW doesn't do it*/ 146 #define CDNS_UART_IXR_BRK 0x00002000 147 148 #define CDNS_UART_RXBS_SUPPORT BIT(1) 149 /* 150 * Modem Control register: 151 * The read/write Modem Control register controls the interface with the modem 152 * or data set, or a peripheral device emulating a modem. 153 */ 154 #define CDNS_UART_MODEMCR_FCM 0x00000020 /* Automatic flow control mode */ 155 #define CDNS_UART_MODEMCR_RTS 0x00000002 /* Request to send output control */ 156 #define CDNS_UART_MODEMCR_DTR 0x00000001 /* Data Terminal Ready */ 157 158 /* 159 * Modem Status register: 160 * The read/write Modem Status register reports the interface with the modem 161 * or data set, or a peripheral device emulating a modem. 162 */ 163 #define CDNS_UART_MODEMSR_DCD BIT(7) /* Data Carrier Detect */ 164 #define CDNS_UART_MODEMSR_RI BIT(6) /* Ting Indicator */ 165 #define CDNS_UART_MODEMSR_DSR BIT(5) /* Data Set Ready */ 166 #define CDNS_UART_MODEMSR_CTS BIT(4) /* Clear To Send */ 167 168 /* 169 * Channel Status Register: 170 * The channel status register (CSR) is provided to enable the control logic 171 * to monitor the status of bits in the channel interrupt status register, 172 * even if these are masked out by the interrupt mask register. 173 */ 174 #define CDNS_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */ 175 #define CDNS_UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */ 176 #define CDNS_UART_SR_TXFULL 0x00000010 /* TX FIFO full */ 177 #define CDNS_UART_SR_RXTRIG 0x00000001 /* Rx Trigger */ 178 #define CDNS_UART_SR_TACTIVE 0x00000800 /* TX state machine active */ 179 180 /* baud dividers min/max values */ 181 #define CDNS_UART_BDIV_MIN 4 182 #define CDNS_UART_BDIV_MAX 255 183 #define CDNS_UART_CD_MAX 65535 184 #define UART_AUTOSUSPEND_TIMEOUT 3000 185 186 /** 187 * struct cdns_uart - device data 188 * @port: Pointer to the UART port 189 * @uartclk: Reference clock 190 * @pclk: APB clock 191 * @cdns_uart_driver: Pointer to UART driver 192 * @baud: Current baud rate 193 * @clk_rate_change_nb: Notifier block for clock changes 194 * @quirks: Flags for RXBS support. 195 * @cts_override: Modem control state override 196 */ 197 struct cdns_uart { 198 struct uart_port *port; 199 struct clk *uartclk; 200 struct clk *pclk; 201 struct uart_driver *cdns_uart_driver; 202 unsigned int baud; 203 struct notifier_block clk_rate_change_nb; 204 u32 quirks; 205 bool cts_override; 206 }; 207 struct cdns_platform_data { 208 u32 quirks; 209 }; 210 #define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \ 211 clk_rate_change_nb) 212 213 /** 214 * cdns_uart_handle_rx - Handle the received bytes along with Rx errors. 215 * @dev_id: Id of the UART port 216 * @isrstatus: The interrupt status register value as read 217 * Return: None 218 */ 219 static void cdns_uart_handle_rx(void *dev_id, unsigned int isrstatus) 220 { 221 struct uart_port *port = (struct uart_port *)dev_id; 222 struct cdns_uart *cdns_uart = port->private_data; 223 unsigned int data; 224 unsigned int rxbs_status = 0; 225 unsigned int status_mask; 226 unsigned int framerrprocessed = 0; 227 char status = TTY_NORMAL; 228 bool is_rxbs_support; 229 230 is_rxbs_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT; 231 232 while ((readl(port->membase + CDNS_UART_SR) & 233 CDNS_UART_SR_RXEMPTY) != CDNS_UART_SR_RXEMPTY) { 234 if (is_rxbs_support) 235 rxbs_status = readl(port->membase + CDNS_UART_RXBS); 236 data = readl(port->membase + CDNS_UART_FIFO); 237 port->icount.rx++; 238 /* 239 * There is no hardware break detection in Zynq, so we interpret 240 * framing error with all-zeros data as a break sequence. 241 * Most of the time, there's another non-zero byte at the 242 * end of the sequence. 243 */ 244 if (!is_rxbs_support && (isrstatus & CDNS_UART_IXR_FRAMING)) { 245 if (!data) { 246 port->read_status_mask |= CDNS_UART_IXR_BRK; 247 framerrprocessed = 1; 248 continue; 249 } 250 } 251 if (is_rxbs_support && (rxbs_status & CDNS_UART_RXBS_BRK)) { 252 port->icount.brk++; 253 status = TTY_BREAK; 254 if (uart_handle_break(port)) 255 continue; 256 } 257 258 isrstatus &= port->read_status_mask; 259 isrstatus &= ~port->ignore_status_mask; 260 status_mask = port->read_status_mask; 261 status_mask &= ~port->ignore_status_mask; 262 263 if (data && 264 (port->read_status_mask & CDNS_UART_IXR_BRK)) { 265 port->read_status_mask &= ~CDNS_UART_IXR_BRK; 266 port->icount.brk++; 267 if (uart_handle_break(port)) 268 continue; 269 } 270 271 if (uart_handle_sysrq_char(port, data)) 272 continue; 273 274 if (is_rxbs_support) { 275 if ((rxbs_status & CDNS_UART_RXBS_PARITY) 276 && (status_mask & CDNS_UART_IXR_PARITY)) { 277 port->icount.parity++; 278 status = TTY_PARITY; 279 } 280 if ((rxbs_status & CDNS_UART_RXBS_FRAMING) 281 && (status_mask & CDNS_UART_IXR_PARITY)) { 282 port->icount.frame++; 283 status = TTY_FRAME; 284 } 285 } else { 286 if (isrstatus & CDNS_UART_IXR_PARITY) { 287 port->icount.parity++; 288 status = TTY_PARITY; 289 } 290 if ((isrstatus & CDNS_UART_IXR_FRAMING) && 291 !framerrprocessed) { 292 port->icount.frame++; 293 status = TTY_FRAME; 294 } 295 } 296 if (isrstatus & CDNS_UART_IXR_OVERRUN) { 297 port->icount.overrun++; 298 tty_insert_flip_char(&port->state->port, 0, 299 TTY_OVERRUN); 300 } 301 tty_insert_flip_char(&port->state->port, data, status); 302 isrstatus = 0; 303 } 304 305 tty_flip_buffer_push(&port->state->port); 306 } 307 308 /** 309 * cdns_uart_handle_tx - Handle the bytes to be Txed. 310 * @dev_id: Id of the UART port 311 * Return: None 312 */ 313 static void cdns_uart_handle_tx(void *dev_id) 314 { 315 struct uart_port *port = (struct uart_port *)dev_id; 316 struct circ_buf *xmit = &port->state->xmit; 317 unsigned int numbytes; 318 319 if (uart_circ_empty(xmit)) { 320 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR); 321 return; 322 } 323 324 numbytes = port->fifosize; 325 while (numbytes && !uart_circ_empty(xmit) && 326 !(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL)) { 327 328 writel(xmit->buf[xmit->tail], port->membase + CDNS_UART_FIFO); 329 330 port->icount.tx++; 331 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 332 numbytes--; 333 } 334 335 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 336 uart_write_wakeup(port); 337 } 338 339 /** 340 * cdns_uart_isr - Interrupt handler 341 * @irq: Irq number 342 * @dev_id: Id of the port 343 * 344 * Return: IRQHANDLED 345 */ 346 static irqreturn_t cdns_uart_isr(int irq, void *dev_id) 347 { 348 struct uart_port *port = (struct uart_port *)dev_id; 349 unsigned int isrstatus; 350 351 spin_lock(&port->lock); 352 353 /* Read the interrupt status register to determine which 354 * interrupt(s) is/are active and clear them. 355 */ 356 isrstatus = readl(port->membase + CDNS_UART_ISR); 357 writel(isrstatus, port->membase + CDNS_UART_ISR); 358 359 if (isrstatus & CDNS_UART_IXR_TXEMPTY) { 360 cdns_uart_handle_tx(dev_id); 361 isrstatus &= ~CDNS_UART_IXR_TXEMPTY; 362 } 363 364 isrstatus &= port->read_status_mask; 365 isrstatus &= ~port->ignore_status_mask; 366 /* 367 * Skip RX processing if RX is disabled as RXEMPTY will never be set 368 * as read bytes will not be removed from the FIFO. 369 */ 370 if (isrstatus & CDNS_UART_IXR_RXMASK && 371 !(readl(port->membase + CDNS_UART_CR) & CDNS_UART_CR_RX_DIS)) 372 cdns_uart_handle_rx(dev_id, isrstatus); 373 374 spin_unlock(&port->lock); 375 return IRQ_HANDLED; 376 } 377 378 /** 379 * cdns_uart_calc_baud_divs - Calculate baud rate divisors 380 * @clk: UART module input clock 381 * @baud: Desired baud rate 382 * @rbdiv: BDIV value (return value) 383 * @rcd: CD value (return value) 384 * @div8: Value for clk_sel bit in mod (return value) 385 * Return: baud rate, requested baud when possible, or actual baud when there 386 * was too much error, zero if no valid divisors are found. 387 * 388 * Formula to obtain baud rate is 389 * baud_tx/rx rate = clk/CD * (BDIV + 1) 390 * input_clk = (Uart User Defined Clock or Apb Clock) 391 * depends on UCLKEN in MR Reg 392 * clk = input_clk or input_clk/8; 393 * depends on CLKS in MR reg 394 * CD and BDIV depends on values in 395 * baud rate generate register 396 * baud rate clock divisor register 397 */ 398 static unsigned int cdns_uart_calc_baud_divs(unsigned int clk, 399 unsigned int baud, u32 *rbdiv, u32 *rcd, int *div8) 400 { 401 u32 cd, bdiv; 402 unsigned int calc_baud; 403 unsigned int bestbaud = 0; 404 unsigned int bauderror; 405 unsigned int besterror = ~0; 406 407 if (baud < clk / ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX)) { 408 *div8 = 1; 409 clk /= 8; 410 } else { 411 *div8 = 0; 412 } 413 414 for (bdiv = CDNS_UART_BDIV_MIN; bdiv <= CDNS_UART_BDIV_MAX; bdiv++) { 415 cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1)); 416 if (cd < 1 || cd > CDNS_UART_CD_MAX) 417 continue; 418 419 calc_baud = clk / (cd * (bdiv + 1)); 420 421 if (baud > calc_baud) 422 bauderror = baud - calc_baud; 423 else 424 bauderror = calc_baud - baud; 425 426 if (besterror > bauderror) { 427 *rbdiv = bdiv; 428 *rcd = cd; 429 bestbaud = calc_baud; 430 besterror = bauderror; 431 } 432 } 433 /* use the values when percent error is acceptable */ 434 if (((besterror * 100) / baud) < 3) 435 bestbaud = baud; 436 437 return bestbaud; 438 } 439 440 /** 441 * cdns_uart_set_baud_rate - Calculate and set the baud rate 442 * @port: Handle to the uart port structure 443 * @baud: Baud rate to set 444 * Return: baud rate, requested baud when possible, or actual baud when there 445 * was too much error, zero if no valid divisors are found. 446 */ 447 static unsigned int cdns_uart_set_baud_rate(struct uart_port *port, 448 unsigned int baud) 449 { 450 unsigned int calc_baud; 451 u32 cd = 0, bdiv = 0; 452 u32 mreg; 453 int div8; 454 struct cdns_uart *cdns_uart = port->private_data; 455 456 calc_baud = cdns_uart_calc_baud_divs(port->uartclk, baud, &bdiv, &cd, 457 &div8); 458 459 /* Write new divisors to hardware */ 460 mreg = readl(port->membase + CDNS_UART_MR); 461 if (div8) 462 mreg |= CDNS_UART_MR_CLKSEL; 463 else 464 mreg &= ~CDNS_UART_MR_CLKSEL; 465 writel(mreg, port->membase + CDNS_UART_MR); 466 writel(cd, port->membase + CDNS_UART_BAUDGEN); 467 writel(bdiv, port->membase + CDNS_UART_BAUDDIV); 468 cdns_uart->baud = baud; 469 470 return calc_baud; 471 } 472 473 #ifdef CONFIG_COMMON_CLK 474 /** 475 * cdns_uart_clk_notifier_cb - Clock notifier callback 476 * @nb: Notifier block 477 * @event: Notify event 478 * @data: Notifier data 479 * Return: NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error. 480 */ 481 static int cdns_uart_clk_notifier_cb(struct notifier_block *nb, 482 unsigned long event, void *data) 483 { 484 u32 ctrl_reg; 485 struct uart_port *port; 486 int locked = 0; 487 struct clk_notifier_data *ndata = data; 488 struct cdns_uart *cdns_uart = to_cdns_uart(nb); 489 unsigned long flags; 490 491 port = cdns_uart->port; 492 if (port->suspended) 493 return NOTIFY_OK; 494 495 switch (event) { 496 case PRE_RATE_CHANGE: 497 { 498 u32 bdiv, cd; 499 int div8; 500 501 /* 502 * Find out if current baud-rate can be achieved with new clock 503 * frequency. 504 */ 505 if (!cdns_uart_calc_baud_divs(ndata->new_rate, cdns_uart->baud, 506 &bdiv, &cd, &div8)) { 507 dev_warn(port->dev, "clock rate change rejected\n"); 508 return NOTIFY_BAD; 509 } 510 511 spin_lock_irqsave(&cdns_uart->port->lock, flags); 512 513 /* Disable the TX and RX to set baud rate */ 514 ctrl_reg = readl(port->membase + CDNS_UART_CR); 515 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS; 516 writel(ctrl_reg, port->membase + CDNS_UART_CR); 517 518 spin_unlock_irqrestore(&cdns_uart->port->lock, flags); 519 520 return NOTIFY_OK; 521 } 522 case POST_RATE_CHANGE: 523 /* 524 * Set clk dividers to generate correct baud with new clock 525 * frequency. 526 */ 527 528 spin_lock_irqsave(&cdns_uart->port->lock, flags); 529 530 locked = 1; 531 port->uartclk = ndata->new_rate; 532 533 cdns_uart->baud = cdns_uart_set_baud_rate(cdns_uart->port, 534 cdns_uart->baud); 535 fallthrough; 536 case ABORT_RATE_CHANGE: 537 if (!locked) 538 spin_lock_irqsave(&cdns_uart->port->lock, flags); 539 540 /* Set TX/RX Reset */ 541 ctrl_reg = readl(port->membase + CDNS_UART_CR); 542 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST; 543 writel(ctrl_reg, port->membase + CDNS_UART_CR); 544 545 while (readl(port->membase + CDNS_UART_CR) & 546 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST)) 547 cpu_relax(); 548 549 /* 550 * Clear the RX disable and TX disable bits and then set the TX 551 * enable bit and RX enable bit to enable the transmitter and 552 * receiver. 553 */ 554 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT); 555 ctrl_reg = readl(port->membase + CDNS_UART_CR); 556 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS); 557 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN; 558 writel(ctrl_reg, port->membase + CDNS_UART_CR); 559 560 spin_unlock_irqrestore(&cdns_uart->port->lock, flags); 561 562 return NOTIFY_OK; 563 default: 564 return NOTIFY_DONE; 565 } 566 } 567 #endif 568 569 /** 570 * cdns_uart_start_tx - Start transmitting bytes 571 * @port: Handle to the uart port structure 572 */ 573 static void cdns_uart_start_tx(struct uart_port *port) 574 { 575 unsigned int status; 576 577 if (uart_tx_stopped(port)) 578 return; 579 580 /* 581 * Set the TX enable bit and clear the TX disable bit to enable the 582 * transmitter. 583 */ 584 status = readl(port->membase + CDNS_UART_CR); 585 status &= ~CDNS_UART_CR_TX_DIS; 586 status |= CDNS_UART_CR_TX_EN; 587 writel(status, port->membase + CDNS_UART_CR); 588 589 if (uart_circ_empty(&port->state->xmit)) 590 return; 591 592 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR); 593 594 cdns_uart_handle_tx(port); 595 596 /* Enable the TX Empty interrupt */ 597 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IER); 598 } 599 600 /** 601 * cdns_uart_stop_tx - Stop TX 602 * @port: Handle to the uart port structure 603 */ 604 static void cdns_uart_stop_tx(struct uart_port *port) 605 { 606 unsigned int regval; 607 608 regval = readl(port->membase + CDNS_UART_CR); 609 regval |= CDNS_UART_CR_TX_DIS; 610 /* Disable the transmitter */ 611 writel(regval, port->membase + CDNS_UART_CR); 612 } 613 614 /** 615 * cdns_uart_stop_rx - Stop RX 616 * @port: Handle to the uart port structure 617 */ 618 static void cdns_uart_stop_rx(struct uart_port *port) 619 { 620 unsigned int regval; 621 622 /* Disable RX IRQs */ 623 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IDR); 624 625 /* Disable the receiver */ 626 regval = readl(port->membase + CDNS_UART_CR); 627 regval |= CDNS_UART_CR_RX_DIS; 628 writel(regval, port->membase + CDNS_UART_CR); 629 } 630 631 /** 632 * cdns_uart_tx_empty - Check whether TX is empty 633 * @port: Handle to the uart port structure 634 * 635 * Return: TIOCSER_TEMT on success, 0 otherwise 636 */ 637 static unsigned int cdns_uart_tx_empty(struct uart_port *port) 638 { 639 unsigned int status; 640 641 status = readl(port->membase + CDNS_UART_SR) & 642 (CDNS_UART_SR_TXEMPTY | CDNS_UART_SR_TACTIVE); 643 return (status == CDNS_UART_SR_TXEMPTY) ? TIOCSER_TEMT : 0; 644 } 645 646 /** 647 * cdns_uart_break_ctl - Based on the input ctl we have to start or stop 648 * transmitting char breaks 649 * @port: Handle to the uart port structure 650 * @ctl: Value based on which start or stop decision is taken 651 */ 652 static void cdns_uart_break_ctl(struct uart_port *port, int ctl) 653 { 654 unsigned int status; 655 unsigned long flags; 656 657 spin_lock_irqsave(&port->lock, flags); 658 659 status = readl(port->membase + CDNS_UART_CR); 660 661 if (ctl == -1) 662 writel(CDNS_UART_CR_STARTBRK | status, 663 port->membase + CDNS_UART_CR); 664 else { 665 if ((status & CDNS_UART_CR_STOPBRK) == 0) 666 writel(CDNS_UART_CR_STOPBRK | status, 667 port->membase + CDNS_UART_CR); 668 } 669 spin_unlock_irqrestore(&port->lock, flags); 670 } 671 672 /** 673 * cdns_uart_set_termios - termios operations, handling data length, parity, 674 * stop bits, flow control, baud rate 675 * @port: Handle to the uart port structure 676 * @termios: Handle to the input termios structure 677 * @old: Values of the previously saved termios structure 678 */ 679 static void cdns_uart_set_termios(struct uart_port *port, 680 struct ktermios *termios, 681 const struct ktermios *old) 682 { 683 u32 cval = 0; 684 unsigned int baud, minbaud, maxbaud; 685 unsigned long flags; 686 unsigned int ctrl_reg, mode_reg; 687 688 spin_lock_irqsave(&port->lock, flags); 689 690 /* Disable the TX and RX to set baud rate */ 691 ctrl_reg = readl(port->membase + CDNS_UART_CR); 692 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS; 693 writel(ctrl_reg, port->membase + CDNS_UART_CR); 694 695 /* 696 * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk 697 * min and max baud should be calculated here based on port->uartclk. 698 * this way we get a valid baud and can safely call set_baud() 699 */ 700 minbaud = port->uartclk / 701 ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX * 8); 702 maxbaud = port->uartclk / (CDNS_UART_BDIV_MIN + 1); 703 baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud); 704 baud = cdns_uart_set_baud_rate(port, baud); 705 if (tty_termios_baud_rate(termios)) 706 tty_termios_encode_baud_rate(termios, baud, baud); 707 708 /* Update the per-port timeout. */ 709 uart_update_timeout(port, termios->c_cflag, baud); 710 711 /* Set TX/RX Reset */ 712 ctrl_reg = readl(port->membase + CDNS_UART_CR); 713 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST; 714 writel(ctrl_reg, port->membase + CDNS_UART_CR); 715 716 while (readl(port->membase + CDNS_UART_CR) & 717 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST)) 718 cpu_relax(); 719 720 /* 721 * Clear the RX disable and TX disable bits and then set the TX enable 722 * bit and RX enable bit to enable the transmitter and receiver. 723 */ 724 ctrl_reg = readl(port->membase + CDNS_UART_CR); 725 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS); 726 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN; 727 writel(ctrl_reg, port->membase + CDNS_UART_CR); 728 729 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT); 730 731 port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG | 732 CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT; 733 port->ignore_status_mask = 0; 734 735 if (termios->c_iflag & INPCK) 736 port->read_status_mask |= CDNS_UART_IXR_PARITY | 737 CDNS_UART_IXR_FRAMING; 738 739 if (termios->c_iflag & IGNPAR) 740 port->ignore_status_mask |= CDNS_UART_IXR_PARITY | 741 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN; 742 743 /* ignore all characters if CREAD is not set */ 744 if ((termios->c_cflag & CREAD) == 0) 745 port->ignore_status_mask |= CDNS_UART_IXR_RXTRIG | 746 CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY | 747 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN; 748 749 mode_reg = readl(port->membase + CDNS_UART_MR); 750 751 /* Handling Data Size */ 752 switch (termios->c_cflag & CSIZE) { 753 case CS6: 754 cval |= CDNS_UART_MR_CHARLEN_6_BIT; 755 break; 756 case CS7: 757 cval |= CDNS_UART_MR_CHARLEN_7_BIT; 758 break; 759 default: 760 case CS8: 761 cval |= CDNS_UART_MR_CHARLEN_8_BIT; 762 termios->c_cflag &= ~CSIZE; 763 termios->c_cflag |= CS8; 764 break; 765 } 766 767 /* Handling Parity and Stop Bits length */ 768 if (termios->c_cflag & CSTOPB) 769 cval |= CDNS_UART_MR_STOPMODE_2_BIT; /* 2 STOP bits */ 770 else 771 cval |= CDNS_UART_MR_STOPMODE_1_BIT; /* 1 STOP bit */ 772 773 if (termios->c_cflag & PARENB) { 774 /* Mark or Space parity */ 775 if (termios->c_cflag & CMSPAR) { 776 if (termios->c_cflag & PARODD) 777 cval |= CDNS_UART_MR_PARITY_MARK; 778 else 779 cval |= CDNS_UART_MR_PARITY_SPACE; 780 } else { 781 if (termios->c_cflag & PARODD) 782 cval |= CDNS_UART_MR_PARITY_ODD; 783 else 784 cval |= CDNS_UART_MR_PARITY_EVEN; 785 } 786 } else { 787 cval |= CDNS_UART_MR_PARITY_NONE; 788 } 789 cval |= mode_reg & 1; 790 writel(cval, port->membase + CDNS_UART_MR); 791 792 cval = readl(port->membase + CDNS_UART_MODEMCR); 793 if (termios->c_cflag & CRTSCTS) 794 cval |= CDNS_UART_MODEMCR_FCM; 795 else 796 cval &= ~CDNS_UART_MODEMCR_FCM; 797 writel(cval, port->membase + CDNS_UART_MODEMCR); 798 799 spin_unlock_irqrestore(&port->lock, flags); 800 } 801 802 /** 803 * cdns_uart_startup - Called when an application opens a cdns_uart port 804 * @port: Handle to the uart port structure 805 * 806 * Return: 0 on success, negative errno otherwise 807 */ 808 static int cdns_uart_startup(struct uart_port *port) 809 { 810 struct cdns_uart *cdns_uart = port->private_data; 811 bool is_brk_support; 812 int ret; 813 unsigned long flags; 814 unsigned int status = 0; 815 816 is_brk_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT; 817 818 spin_lock_irqsave(&port->lock, flags); 819 820 /* Disable the TX and RX */ 821 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS, 822 port->membase + CDNS_UART_CR); 823 824 /* Set the Control Register with TX/RX Enable, TX/RX Reset, 825 * no break chars. 826 */ 827 writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST, 828 port->membase + CDNS_UART_CR); 829 830 while (readl(port->membase + CDNS_UART_CR) & 831 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST)) 832 cpu_relax(); 833 834 /* 835 * Clear the RX disable bit and then set the RX enable bit to enable 836 * the receiver. 837 */ 838 status = readl(port->membase + CDNS_UART_CR); 839 status &= ~CDNS_UART_CR_RX_DIS; 840 status |= CDNS_UART_CR_RX_EN; 841 writel(status, port->membase + CDNS_UART_CR); 842 843 /* Set the Mode Register with normal mode,8 data bits,1 stop bit, 844 * no parity. 845 */ 846 writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT 847 | CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT, 848 port->membase + CDNS_UART_MR); 849 850 /* 851 * Set the RX FIFO Trigger level to use most of the FIFO, but it 852 * can be tuned with a module parameter 853 */ 854 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM); 855 856 /* 857 * Receive Timeout register is enabled but it 858 * can be tuned with a module parameter 859 */ 860 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT); 861 862 /* Clear out any pending interrupts before enabling them */ 863 writel(readl(port->membase + CDNS_UART_ISR), 864 port->membase + CDNS_UART_ISR); 865 866 spin_unlock_irqrestore(&port->lock, flags); 867 868 ret = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME, port); 869 if (ret) { 870 dev_err(port->dev, "request_irq '%d' failed with %d\n", 871 port->irq, ret); 872 return ret; 873 } 874 875 /* Set the Interrupt Registers with desired interrupts */ 876 if (is_brk_support) 877 writel(CDNS_UART_RX_IRQS | CDNS_UART_IXR_BRK, 878 port->membase + CDNS_UART_IER); 879 else 880 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IER); 881 882 return 0; 883 } 884 885 /** 886 * cdns_uart_shutdown - Called when an application closes a cdns_uart port 887 * @port: Handle to the uart port structure 888 */ 889 static void cdns_uart_shutdown(struct uart_port *port) 890 { 891 int status; 892 unsigned long flags; 893 894 spin_lock_irqsave(&port->lock, flags); 895 896 /* Disable interrupts */ 897 status = readl(port->membase + CDNS_UART_IMR); 898 writel(status, port->membase + CDNS_UART_IDR); 899 writel(0xffffffff, port->membase + CDNS_UART_ISR); 900 901 /* Disable the TX and RX */ 902 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS, 903 port->membase + CDNS_UART_CR); 904 905 spin_unlock_irqrestore(&port->lock, flags); 906 907 free_irq(port->irq, port); 908 } 909 910 /** 911 * cdns_uart_type - Set UART type to cdns_uart port 912 * @port: Handle to the uart port structure 913 * 914 * Return: string on success, NULL otherwise 915 */ 916 static const char *cdns_uart_type(struct uart_port *port) 917 { 918 return port->type == PORT_XUARTPS ? CDNS_UART_NAME : NULL; 919 } 920 921 /** 922 * cdns_uart_verify_port - Verify the port params 923 * @port: Handle to the uart port structure 924 * @ser: Handle to the structure whose members are compared 925 * 926 * Return: 0 on success, negative errno otherwise. 927 */ 928 static int cdns_uart_verify_port(struct uart_port *port, 929 struct serial_struct *ser) 930 { 931 if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS) 932 return -EINVAL; 933 if (port->irq != ser->irq) 934 return -EINVAL; 935 if (ser->io_type != UPIO_MEM) 936 return -EINVAL; 937 if (port->iobase != ser->port) 938 return -EINVAL; 939 if (ser->hub6 != 0) 940 return -EINVAL; 941 return 0; 942 } 943 944 /** 945 * cdns_uart_request_port - Claim the memory region attached to cdns_uart port, 946 * called when the driver adds a cdns_uart port via 947 * uart_add_one_port() 948 * @port: Handle to the uart port structure 949 * 950 * Return: 0 on success, negative errno otherwise. 951 */ 952 static int cdns_uart_request_port(struct uart_port *port) 953 { 954 if (!request_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE, 955 CDNS_UART_NAME)) { 956 return -ENOMEM; 957 } 958 959 port->membase = ioremap(port->mapbase, CDNS_UART_REGISTER_SPACE); 960 if (!port->membase) { 961 dev_err(port->dev, "Unable to map registers\n"); 962 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE); 963 return -ENOMEM; 964 } 965 return 0; 966 } 967 968 /** 969 * cdns_uart_release_port - Release UART port 970 * @port: Handle to the uart port structure 971 * 972 * Release the memory region attached to a cdns_uart port. Called when the 973 * driver removes a cdns_uart port via uart_remove_one_port(). 974 */ 975 static void cdns_uart_release_port(struct uart_port *port) 976 { 977 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE); 978 iounmap(port->membase); 979 port->membase = NULL; 980 } 981 982 /** 983 * cdns_uart_config_port - Configure UART port 984 * @port: Handle to the uart port structure 985 * @flags: If any 986 */ 987 static void cdns_uart_config_port(struct uart_port *port, int flags) 988 { 989 if (flags & UART_CONFIG_TYPE && cdns_uart_request_port(port) == 0) 990 port->type = PORT_XUARTPS; 991 } 992 993 /** 994 * cdns_uart_get_mctrl - Get the modem control state 995 * @port: Handle to the uart port structure 996 * 997 * Return: the modem control state 998 */ 999 static unsigned int cdns_uart_get_mctrl(struct uart_port *port) 1000 { 1001 u32 val; 1002 unsigned int mctrl = 0; 1003 struct cdns_uart *cdns_uart_data = port->private_data; 1004 1005 if (cdns_uart_data->cts_override) 1006 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; 1007 1008 val = readl(port->membase + CDNS_UART_MODEMSR); 1009 if (val & CDNS_UART_MODEMSR_CTS) 1010 mctrl |= TIOCM_CTS; 1011 if (val & CDNS_UART_MODEMSR_DSR) 1012 mctrl |= TIOCM_DSR; 1013 if (val & CDNS_UART_MODEMSR_RI) 1014 mctrl |= TIOCM_RNG; 1015 if (val & CDNS_UART_MODEMSR_DCD) 1016 mctrl |= TIOCM_CAR; 1017 1018 return mctrl; 1019 } 1020 1021 static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 1022 { 1023 u32 val; 1024 u32 mode_reg; 1025 struct cdns_uart *cdns_uart_data = port->private_data; 1026 1027 if (cdns_uart_data->cts_override) 1028 return; 1029 1030 val = readl(port->membase + CDNS_UART_MODEMCR); 1031 mode_reg = readl(port->membase + CDNS_UART_MR); 1032 1033 val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR); 1034 mode_reg &= ~CDNS_UART_MR_CHMODE_MASK; 1035 1036 if (mctrl & TIOCM_RTS) 1037 val |= CDNS_UART_MODEMCR_RTS; 1038 if (mctrl & TIOCM_DTR) 1039 val |= CDNS_UART_MODEMCR_DTR; 1040 if (mctrl & TIOCM_LOOP) 1041 mode_reg |= CDNS_UART_MR_CHMODE_L_LOOP; 1042 else 1043 mode_reg |= CDNS_UART_MR_CHMODE_NORM; 1044 1045 writel(val, port->membase + CDNS_UART_MODEMCR); 1046 writel(mode_reg, port->membase + CDNS_UART_MR); 1047 } 1048 1049 #ifdef CONFIG_CONSOLE_POLL 1050 static int cdns_uart_poll_get_char(struct uart_port *port) 1051 { 1052 int c; 1053 unsigned long flags; 1054 1055 spin_lock_irqsave(&port->lock, flags); 1056 1057 /* Check if FIFO is empty */ 1058 if (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_RXEMPTY) 1059 c = NO_POLL_CHAR; 1060 else /* Read a character */ 1061 c = (unsigned char) readl(port->membase + CDNS_UART_FIFO); 1062 1063 spin_unlock_irqrestore(&port->lock, flags); 1064 1065 return c; 1066 } 1067 1068 static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c) 1069 { 1070 unsigned long flags; 1071 1072 spin_lock_irqsave(&port->lock, flags); 1073 1074 /* Wait until FIFO is empty */ 1075 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY)) 1076 cpu_relax(); 1077 1078 /* Write a character */ 1079 writel(c, port->membase + CDNS_UART_FIFO); 1080 1081 /* Wait until FIFO is empty */ 1082 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY)) 1083 cpu_relax(); 1084 1085 spin_unlock_irqrestore(&port->lock, flags); 1086 } 1087 #endif 1088 1089 static void cdns_uart_pm(struct uart_port *port, unsigned int state, 1090 unsigned int oldstate) 1091 { 1092 switch (state) { 1093 case UART_PM_STATE_OFF: 1094 pm_runtime_mark_last_busy(port->dev); 1095 pm_runtime_put_autosuspend(port->dev); 1096 break; 1097 default: 1098 pm_runtime_get_sync(port->dev); 1099 break; 1100 } 1101 } 1102 1103 static const struct uart_ops cdns_uart_ops = { 1104 .set_mctrl = cdns_uart_set_mctrl, 1105 .get_mctrl = cdns_uart_get_mctrl, 1106 .start_tx = cdns_uart_start_tx, 1107 .stop_tx = cdns_uart_stop_tx, 1108 .stop_rx = cdns_uart_stop_rx, 1109 .tx_empty = cdns_uart_tx_empty, 1110 .break_ctl = cdns_uart_break_ctl, 1111 .set_termios = cdns_uart_set_termios, 1112 .startup = cdns_uart_startup, 1113 .shutdown = cdns_uart_shutdown, 1114 .pm = cdns_uart_pm, 1115 .type = cdns_uart_type, 1116 .verify_port = cdns_uart_verify_port, 1117 .request_port = cdns_uart_request_port, 1118 .release_port = cdns_uart_release_port, 1119 .config_port = cdns_uart_config_port, 1120 #ifdef CONFIG_CONSOLE_POLL 1121 .poll_get_char = cdns_uart_poll_get_char, 1122 .poll_put_char = cdns_uart_poll_put_char, 1123 #endif 1124 }; 1125 1126 static struct uart_driver cdns_uart_uart_driver; 1127 1128 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE 1129 /** 1130 * cdns_uart_console_putchar - write the character to the FIFO buffer 1131 * @port: Handle to the uart port structure 1132 * @ch: Character to be written 1133 */ 1134 static void cdns_uart_console_putchar(struct uart_port *port, unsigned char ch) 1135 { 1136 unsigned int ctrl_reg; 1137 unsigned long timeout; 1138 1139 timeout = jiffies + msecs_to_jiffies(1000); 1140 while (1) { 1141 ctrl_reg = readl(port->membase + CDNS_UART_CR); 1142 if (!(ctrl_reg & CDNS_UART_CR_TX_DIS)) 1143 break; 1144 if (time_after(jiffies, timeout)) { 1145 dev_warn(port->dev, 1146 "timeout waiting for Enable\n"); 1147 return; 1148 } 1149 cpu_relax(); 1150 } 1151 1152 timeout = jiffies + msecs_to_jiffies(1000); 1153 while (1) { 1154 ctrl_reg = readl(port->membase + CDNS_UART_SR); 1155 1156 if (!(ctrl_reg & CDNS_UART_SR_TXFULL)) 1157 break; 1158 if (time_after(jiffies, timeout)) { 1159 dev_warn(port->dev, 1160 "timeout waiting for TX fifo\n"); 1161 return; 1162 } 1163 cpu_relax(); 1164 } 1165 writel(ch, port->membase + CDNS_UART_FIFO); 1166 } 1167 1168 static void cdns_early_write(struct console *con, const char *s, 1169 unsigned int n) 1170 { 1171 struct earlycon_device *dev = con->data; 1172 1173 uart_console_write(&dev->port, s, n, cdns_uart_console_putchar); 1174 } 1175 1176 static int __init cdns_early_console_setup(struct earlycon_device *device, 1177 const char *opt) 1178 { 1179 struct uart_port *port = &device->port; 1180 1181 if (!port->membase) 1182 return -ENODEV; 1183 1184 /* initialise control register */ 1185 writel(CDNS_UART_CR_TX_EN|CDNS_UART_CR_TXRST|CDNS_UART_CR_RXRST, 1186 port->membase + CDNS_UART_CR); 1187 1188 /* only set baud if specified on command line - otherwise 1189 * assume it has been initialized by a boot loader. 1190 */ 1191 if (port->uartclk && device->baud) { 1192 u32 cd = 0, bdiv = 0; 1193 u32 mr; 1194 int div8; 1195 1196 cdns_uart_calc_baud_divs(port->uartclk, device->baud, 1197 &bdiv, &cd, &div8); 1198 mr = CDNS_UART_MR_PARITY_NONE; 1199 if (div8) 1200 mr |= CDNS_UART_MR_CLKSEL; 1201 1202 writel(mr, port->membase + CDNS_UART_MR); 1203 writel(cd, port->membase + CDNS_UART_BAUDGEN); 1204 writel(bdiv, port->membase + CDNS_UART_BAUDDIV); 1205 } 1206 1207 device->con->write = cdns_early_write; 1208 1209 return 0; 1210 } 1211 OF_EARLYCON_DECLARE(cdns, "xlnx,xuartps", cdns_early_console_setup); 1212 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p8", cdns_early_console_setup); 1213 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p12", cdns_early_console_setup); 1214 OF_EARLYCON_DECLARE(cdns, "xlnx,zynqmp-uart", cdns_early_console_setup); 1215 1216 1217 /* Static pointer to console port */ 1218 static struct uart_port *console_port; 1219 1220 /** 1221 * cdns_uart_console_write - perform write operation 1222 * @co: Console handle 1223 * @s: Pointer to character array 1224 * @count: No of characters 1225 */ 1226 static void cdns_uart_console_write(struct console *co, const char *s, 1227 unsigned int count) 1228 { 1229 struct uart_port *port = console_port; 1230 unsigned long flags; 1231 unsigned int imr, ctrl; 1232 int locked = 1; 1233 1234 if (port->sysrq) 1235 locked = 0; 1236 else if (oops_in_progress) 1237 locked = spin_trylock_irqsave(&port->lock, flags); 1238 else 1239 spin_lock_irqsave(&port->lock, flags); 1240 1241 /* save and disable interrupt */ 1242 imr = readl(port->membase + CDNS_UART_IMR); 1243 writel(imr, port->membase + CDNS_UART_IDR); 1244 1245 /* 1246 * Make sure that the tx part is enabled. Set the TX enable bit and 1247 * clear the TX disable bit to enable the transmitter. 1248 */ 1249 ctrl = readl(port->membase + CDNS_UART_CR); 1250 ctrl &= ~CDNS_UART_CR_TX_DIS; 1251 ctrl |= CDNS_UART_CR_TX_EN; 1252 writel(ctrl, port->membase + CDNS_UART_CR); 1253 1254 uart_console_write(port, s, count, cdns_uart_console_putchar); 1255 while (cdns_uart_tx_empty(port) != TIOCSER_TEMT) 1256 cpu_relax(); 1257 1258 /* restore interrupt state */ 1259 writel(imr, port->membase + CDNS_UART_IER); 1260 1261 if (locked) 1262 spin_unlock_irqrestore(&port->lock, flags); 1263 } 1264 1265 /** 1266 * cdns_uart_console_setup - Initialize the uart to default config 1267 * @co: Console handle 1268 * @options: Initial settings of uart 1269 * 1270 * Return: 0 on success, negative errno otherwise. 1271 */ 1272 static int cdns_uart_console_setup(struct console *co, char *options) 1273 { 1274 struct uart_port *port = console_port; 1275 1276 int baud = 9600; 1277 int bits = 8; 1278 int parity = 'n'; 1279 int flow = 'n'; 1280 unsigned long time_out; 1281 1282 if (!port->membase) { 1283 pr_debug("console on " CDNS_UART_TTY_NAME "%i not present\n", 1284 co->index); 1285 return -ENODEV; 1286 } 1287 1288 if (options) 1289 uart_parse_options(options, &baud, &parity, &bits, &flow); 1290 1291 /* Wait for tx_empty before setting up the console */ 1292 time_out = jiffies + usecs_to_jiffies(TX_TIMEOUT); 1293 1294 while (time_before(jiffies, time_out) && 1295 cdns_uart_tx_empty(port) != TIOCSER_TEMT) 1296 cpu_relax(); 1297 1298 return uart_set_options(port, co, baud, parity, bits, flow); 1299 } 1300 1301 static struct console cdns_uart_console = { 1302 .name = CDNS_UART_TTY_NAME, 1303 .write = cdns_uart_console_write, 1304 .device = uart_console_device, 1305 .setup = cdns_uart_console_setup, 1306 .flags = CON_PRINTBUFFER, 1307 .index = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */ 1308 .data = &cdns_uart_uart_driver, 1309 }; 1310 #endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */ 1311 1312 #ifdef CONFIG_PM_SLEEP 1313 /** 1314 * cdns_uart_suspend - suspend event 1315 * @device: Pointer to the device structure 1316 * 1317 * Return: 0 1318 */ 1319 static int cdns_uart_suspend(struct device *device) 1320 { 1321 struct uart_port *port = dev_get_drvdata(device); 1322 struct cdns_uart *cdns_uart = port->private_data; 1323 int may_wake; 1324 1325 may_wake = device_may_wakeup(device); 1326 1327 if (console_suspend_enabled && uart_console(port) && may_wake) { 1328 unsigned long flags; 1329 1330 spin_lock_irqsave(&port->lock, flags); 1331 /* Empty the receive FIFO 1st before making changes */ 1332 while (!(readl(port->membase + CDNS_UART_SR) & 1333 CDNS_UART_SR_RXEMPTY)) 1334 readl(port->membase + CDNS_UART_FIFO); 1335 /* set RX trigger level to 1 */ 1336 writel(1, port->membase + CDNS_UART_RXWM); 1337 /* disable RX timeout interrups */ 1338 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IDR); 1339 spin_unlock_irqrestore(&port->lock, flags); 1340 } 1341 1342 /* 1343 * Call the API provided in serial_core.c file which handles 1344 * the suspend. 1345 */ 1346 return uart_suspend_port(cdns_uart->cdns_uart_driver, port); 1347 } 1348 1349 /** 1350 * cdns_uart_resume - Resume after a previous suspend 1351 * @device: Pointer to the device structure 1352 * 1353 * Return: 0 1354 */ 1355 static int cdns_uart_resume(struct device *device) 1356 { 1357 struct uart_port *port = dev_get_drvdata(device); 1358 struct cdns_uart *cdns_uart = port->private_data; 1359 unsigned long flags; 1360 u32 ctrl_reg; 1361 int may_wake; 1362 int ret; 1363 1364 may_wake = device_may_wakeup(device); 1365 1366 if (console_suspend_enabled && uart_console(port) && !may_wake) { 1367 ret = clk_enable(cdns_uart->pclk); 1368 if (ret) 1369 return ret; 1370 1371 ret = clk_enable(cdns_uart->uartclk); 1372 if (ret) { 1373 clk_disable(cdns_uart->pclk); 1374 return ret; 1375 } 1376 1377 spin_lock_irqsave(&port->lock, flags); 1378 1379 /* Set TX/RX Reset */ 1380 ctrl_reg = readl(port->membase + CDNS_UART_CR); 1381 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST; 1382 writel(ctrl_reg, port->membase + CDNS_UART_CR); 1383 while (readl(port->membase + CDNS_UART_CR) & 1384 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST)) 1385 cpu_relax(); 1386 1387 /* restore rx timeout value */ 1388 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT); 1389 /* Enable Tx/Rx */ 1390 ctrl_reg = readl(port->membase + CDNS_UART_CR); 1391 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS); 1392 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN; 1393 writel(ctrl_reg, port->membase + CDNS_UART_CR); 1394 1395 clk_disable(cdns_uart->uartclk); 1396 clk_disable(cdns_uart->pclk); 1397 spin_unlock_irqrestore(&port->lock, flags); 1398 } else { 1399 spin_lock_irqsave(&port->lock, flags); 1400 /* restore original rx trigger level */ 1401 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM); 1402 /* enable RX timeout interrupt */ 1403 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IER); 1404 spin_unlock_irqrestore(&port->lock, flags); 1405 } 1406 1407 return uart_resume_port(cdns_uart->cdns_uart_driver, port); 1408 } 1409 #endif /* ! CONFIG_PM_SLEEP */ 1410 static int __maybe_unused cdns_runtime_suspend(struct device *dev) 1411 { 1412 struct uart_port *port = dev_get_drvdata(dev); 1413 struct cdns_uart *cdns_uart = port->private_data; 1414 1415 clk_disable(cdns_uart->uartclk); 1416 clk_disable(cdns_uart->pclk); 1417 return 0; 1418 }; 1419 1420 static int __maybe_unused cdns_runtime_resume(struct device *dev) 1421 { 1422 struct uart_port *port = dev_get_drvdata(dev); 1423 struct cdns_uart *cdns_uart = port->private_data; 1424 int ret; 1425 1426 ret = clk_enable(cdns_uart->pclk); 1427 if (ret) 1428 return ret; 1429 1430 ret = clk_enable(cdns_uart->uartclk); 1431 if (ret) { 1432 clk_disable(cdns_uart->pclk); 1433 return ret; 1434 } 1435 return 0; 1436 }; 1437 1438 static const struct dev_pm_ops cdns_uart_dev_pm_ops = { 1439 SET_SYSTEM_SLEEP_PM_OPS(cdns_uart_suspend, cdns_uart_resume) 1440 SET_RUNTIME_PM_OPS(cdns_runtime_suspend, 1441 cdns_runtime_resume, NULL) 1442 }; 1443 1444 static const struct cdns_platform_data zynqmp_uart_def = { 1445 .quirks = CDNS_UART_RXBS_SUPPORT, }; 1446 1447 /* Match table for of_platform binding */ 1448 static const struct of_device_id cdns_uart_of_match[] = { 1449 { .compatible = "xlnx,xuartps", }, 1450 { .compatible = "cdns,uart-r1p8", }, 1451 { .compatible = "cdns,uart-r1p12", .data = &zynqmp_uart_def }, 1452 { .compatible = "xlnx,zynqmp-uart", .data = &zynqmp_uart_def }, 1453 {} 1454 }; 1455 MODULE_DEVICE_TABLE(of, cdns_uart_of_match); 1456 1457 /* Temporary variable for storing number of instances */ 1458 static int instances; 1459 1460 /** 1461 * cdns_uart_probe - Platform driver probe 1462 * @pdev: Pointer to the platform device structure 1463 * 1464 * Return: 0 on success, negative errno otherwise 1465 */ 1466 static int cdns_uart_probe(struct platform_device *pdev) 1467 { 1468 int rc, id, irq; 1469 struct uart_port *port; 1470 struct resource *res; 1471 struct cdns_uart *cdns_uart_data; 1472 const struct of_device_id *match; 1473 1474 cdns_uart_data = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_data), 1475 GFP_KERNEL); 1476 if (!cdns_uart_data) 1477 return -ENOMEM; 1478 port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL); 1479 if (!port) 1480 return -ENOMEM; 1481 1482 /* Look for a serialN alias */ 1483 id = of_alias_get_id(pdev->dev.of_node, "serial"); 1484 if (id < 0) 1485 id = 0; 1486 1487 if (id >= CDNS_UART_NR_PORTS) { 1488 dev_err(&pdev->dev, "Cannot get uart_port structure\n"); 1489 return -ENODEV; 1490 } 1491 1492 if (!cdns_uart_uart_driver.state) { 1493 cdns_uart_uart_driver.owner = THIS_MODULE; 1494 cdns_uart_uart_driver.driver_name = CDNS_UART_NAME; 1495 cdns_uart_uart_driver.dev_name = CDNS_UART_TTY_NAME; 1496 cdns_uart_uart_driver.major = CDNS_UART_MAJOR; 1497 cdns_uart_uart_driver.minor = CDNS_UART_MINOR; 1498 cdns_uart_uart_driver.nr = CDNS_UART_NR_PORTS; 1499 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE 1500 cdns_uart_uart_driver.cons = &cdns_uart_console; 1501 #endif 1502 1503 rc = uart_register_driver(&cdns_uart_uart_driver); 1504 if (rc < 0) { 1505 dev_err(&pdev->dev, "Failed to register driver\n"); 1506 return rc; 1507 } 1508 } 1509 1510 cdns_uart_data->cdns_uart_driver = &cdns_uart_uart_driver; 1511 1512 match = of_match_node(cdns_uart_of_match, pdev->dev.of_node); 1513 if (match && match->data) { 1514 const struct cdns_platform_data *data = match->data; 1515 1516 cdns_uart_data->quirks = data->quirks; 1517 } 1518 1519 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "pclk"); 1520 if (PTR_ERR(cdns_uart_data->pclk) == -EPROBE_DEFER) { 1521 rc = PTR_ERR(cdns_uart_data->pclk); 1522 goto err_out_unregister_driver; 1523 } 1524 1525 if (IS_ERR(cdns_uart_data->pclk)) { 1526 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "aper_clk"); 1527 if (IS_ERR(cdns_uart_data->pclk)) { 1528 rc = PTR_ERR(cdns_uart_data->pclk); 1529 goto err_out_unregister_driver; 1530 } 1531 dev_err(&pdev->dev, "clock name 'aper_clk' is deprecated.\n"); 1532 } 1533 1534 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "uart_clk"); 1535 if (PTR_ERR(cdns_uart_data->uartclk) == -EPROBE_DEFER) { 1536 rc = PTR_ERR(cdns_uart_data->uartclk); 1537 goto err_out_unregister_driver; 1538 } 1539 1540 if (IS_ERR(cdns_uart_data->uartclk)) { 1541 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "ref_clk"); 1542 if (IS_ERR(cdns_uart_data->uartclk)) { 1543 rc = PTR_ERR(cdns_uart_data->uartclk); 1544 goto err_out_unregister_driver; 1545 } 1546 dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n"); 1547 } 1548 1549 rc = clk_prepare_enable(cdns_uart_data->pclk); 1550 if (rc) { 1551 dev_err(&pdev->dev, "Unable to enable pclk clock.\n"); 1552 goto err_out_unregister_driver; 1553 } 1554 rc = clk_prepare_enable(cdns_uart_data->uartclk); 1555 if (rc) { 1556 dev_err(&pdev->dev, "Unable to enable device clock.\n"); 1557 goto err_out_clk_dis_pclk; 1558 } 1559 1560 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1561 if (!res) { 1562 rc = -ENODEV; 1563 goto err_out_clk_disable; 1564 } 1565 1566 irq = platform_get_irq(pdev, 0); 1567 if (irq <= 0) { 1568 rc = -ENXIO; 1569 goto err_out_clk_disable; 1570 } 1571 1572 #ifdef CONFIG_COMMON_CLK 1573 cdns_uart_data->clk_rate_change_nb.notifier_call = 1574 cdns_uart_clk_notifier_cb; 1575 if (clk_notifier_register(cdns_uart_data->uartclk, 1576 &cdns_uart_data->clk_rate_change_nb)) 1577 dev_warn(&pdev->dev, "Unable to register clock notifier.\n"); 1578 #endif 1579 1580 /* At this point, we've got an empty uart_port struct, initialize it */ 1581 spin_lock_init(&port->lock); 1582 port->type = PORT_UNKNOWN; 1583 port->iotype = UPIO_MEM32; 1584 port->flags = UPF_BOOT_AUTOCONF; 1585 port->ops = &cdns_uart_ops; 1586 port->fifosize = CDNS_UART_FIFO_SIZE; 1587 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE); 1588 port->line = id; 1589 1590 /* 1591 * Register the port. 1592 * This function also registers this device with the tty layer 1593 * and triggers invocation of the config_port() entry point. 1594 */ 1595 port->mapbase = res->start; 1596 port->irq = irq; 1597 port->dev = &pdev->dev; 1598 port->uartclk = clk_get_rate(cdns_uart_data->uartclk); 1599 port->private_data = cdns_uart_data; 1600 port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG | 1601 CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT; 1602 cdns_uart_data->port = port; 1603 platform_set_drvdata(pdev, port); 1604 1605 pm_runtime_use_autosuspend(&pdev->dev); 1606 pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT); 1607 pm_runtime_set_active(&pdev->dev); 1608 pm_runtime_enable(&pdev->dev); 1609 device_init_wakeup(port->dev, true); 1610 1611 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE 1612 /* 1613 * If console hasn't been found yet try to assign this port 1614 * because it is required to be assigned for console setup function. 1615 * If register_console() don't assign value, then console_port pointer 1616 * is cleanup. 1617 */ 1618 if (!console_port) { 1619 cdns_uart_console.index = id; 1620 console_port = port; 1621 } 1622 #endif 1623 1624 rc = uart_add_one_port(&cdns_uart_uart_driver, port); 1625 if (rc) { 1626 dev_err(&pdev->dev, 1627 "uart_add_one_port() failed; err=%i\n", rc); 1628 goto err_out_pm_disable; 1629 } 1630 1631 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE 1632 /* This is not port which is used for console that's why clean it up */ 1633 if (console_port == port && 1634 !(cdns_uart_uart_driver.cons->flags & CON_ENABLED)) { 1635 console_port = NULL; 1636 cdns_uart_console.index = -1; 1637 } 1638 #endif 1639 1640 cdns_uart_data->cts_override = of_property_read_bool(pdev->dev.of_node, 1641 "cts-override"); 1642 1643 instances++; 1644 1645 return 0; 1646 1647 err_out_pm_disable: 1648 pm_runtime_disable(&pdev->dev); 1649 pm_runtime_set_suspended(&pdev->dev); 1650 pm_runtime_dont_use_autosuspend(&pdev->dev); 1651 #ifdef CONFIG_COMMON_CLK 1652 clk_notifier_unregister(cdns_uart_data->uartclk, 1653 &cdns_uart_data->clk_rate_change_nb); 1654 #endif 1655 err_out_clk_disable: 1656 clk_disable_unprepare(cdns_uart_data->uartclk); 1657 err_out_clk_dis_pclk: 1658 clk_disable_unprepare(cdns_uart_data->pclk); 1659 err_out_unregister_driver: 1660 if (!instances) 1661 uart_unregister_driver(cdns_uart_data->cdns_uart_driver); 1662 return rc; 1663 } 1664 1665 /** 1666 * cdns_uart_remove - called when the platform driver is unregistered 1667 * @pdev: Pointer to the platform device structure 1668 * 1669 * Return: 0 on success, negative errno otherwise 1670 */ 1671 static int cdns_uart_remove(struct platform_device *pdev) 1672 { 1673 struct uart_port *port = platform_get_drvdata(pdev); 1674 struct cdns_uart *cdns_uart_data = port->private_data; 1675 int rc; 1676 1677 /* Remove the cdns_uart port from the serial core */ 1678 #ifdef CONFIG_COMMON_CLK 1679 clk_notifier_unregister(cdns_uart_data->uartclk, 1680 &cdns_uart_data->clk_rate_change_nb); 1681 #endif 1682 rc = uart_remove_one_port(cdns_uart_data->cdns_uart_driver, port); 1683 port->mapbase = 0; 1684 clk_disable_unprepare(cdns_uart_data->uartclk); 1685 clk_disable_unprepare(cdns_uart_data->pclk); 1686 pm_runtime_disable(&pdev->dev); 1687 pm_runtime_set_suspended(&pdev->dev); 1688 pm_runtime_dont_use_autosuspend(&pdev->dev); 1689 device_init_wakeup(&pdev->dev, false); 1690 1691 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE 1692 if (console_port == port) 1693 console_port = NULL; 1694 #endif 1695 1696 if (!--instances) 1697 uart_unregister_driver(cdns_uart_data->cdns_uart_driver); 1698 return rc; 1699 } 1700 1701 static struct platform_driver cdns_uart_platform_driver = { 1702 .probe = cdns_uart_probe, 1703 .remove = cdns_uart_remove, 1704 .driver = { 1705 .name = CDNS_UART_NAME, 1706 .of_match_table = cdns_uart_of_match, 1707 .pm = &cdns_uart_dev_pm_ops, 1708 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_XILINX_PS_UART), 1709 }, 1710 }; 1711 1712 static int __init cdns_uart_init(void) 1713 { 1714 /* Register the platform driver */ 1715 return platform_driver_register(&cdns_uart_platform_driver); 1716 } 1717 1718 static void __exit cdns_uart_exit(void) 1719 { 1720 /* Unregister the platform driver */ 1721 platform_driver_unregister(&cdns_uart_platform_driver); 1722 } 1723 1724 arch_initcall(cdns_uart_init); 1725 module_exit(cdns_uart_exit); 1726 1727 MODULE_DESCRIPTION("Driver for Cadence UART"); 1728 MODULE_AUTHOR("Xilinx Inc."); 1729 MODULE_LICENSE("GPL"); 1730