1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Cadence UART driver (found in Xilinx Zynq) 4 * 5 * 2011 - 2014 (C) Xilinx Inc. 6 * 7 * This driver has originally been pushed by Xilinx using a Zynq-branding. This 8 * still shows in the naming of this file, the kconfig symbols and some symbols 9 * in the code. 10 */ 11 12 #include <linux/platform_device.h> 13 #include <linux/serial.h> 14 #include <linux/console.h> 15 #include <linux/serial_core.h> 16 #include <linux/slab.h> 17 #include <linux/tty.h> 18 #include <linux/tty_flip.h> 19 #include <linux/clk.h> 20 #include <linux/irq.h> 21 #include <linux/io.h> 22 #include <linux/of.h> 23 #include <linux/module.h> 24 #include <linux/pm_runtime.h> 25 #include <linux/iopoll.h> 26 27 #define CDNS_UART_TTY_NAME "ttyPS" 28 #define CDNS_UART_NAME "xuartps" 29 #define CDNS_UART_MAJOR 0 /* use dynamic node allocation */ 30 #define CDNS_UART_MINOR 0 /* works best with devtmpfs */ 31 #define CDNS_UART_NR_PORTS 16 32 #define CDNS_UART_FIFO_SIZE 64 /* FIFO size */ 33 #define CDNS_UART_REGISTER_SPACE 0x1000 34 #define TX_TIMEOUT 500000 35 36 /* Rx Trigger level */ 37 static int rx_trigger_level = 56; 38 module_param(rx_trigger_level, uint, 0444); 39 MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes"); 40 41 /* Rx Timeout */ 42 static int rx_timeout = 10; 43 module_param(rx_timeout, uint, 0444); 44 MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255"); 45 46 /* Register offsets for the UART. */ 47 #define CDNS_UART_CR 0x00 /* Control Register */ 48 #define CDNS_UART_MR 0x04 /* Mode Register */ 49 #define CDNS_UART_IER 0x08 /* Interrupt Enable */ 50 #define CDNS_UART_IDR 0x0C /* Interrupt Disable */ 51 #define CDNS_UART_IMR 0x10 /* Interrupt Mask */ 52 #define CDNS_UART_ISR 0x14 /* Interrupt Status */ 53 #define CDNS_UART_BAUDGEN 0x18 /* Baud Rate Generator */ 54 #define CDNS_UART_RXTOUT 0x1C /* RX Timeout */ 55 #define CDNS_UART_RXWM 0x20 /* RX FIFO Trigger Level */ 56 #define CDNS_UART_MODEMCR 0x24 /* Modem Control */ 57 #define CDNS_UART_MODEMSR 0x28 /* Modem Status */ 58 #define CDNS_UART_SR 0x2C /* Channel Status */ 59 #define CDNS_UART_FIFO 0x30 /* FIFO */ 60 #define CDNS_UART_BAUDDIV 0x34 /* Baud Rate Divider */ 61 #define CDNS_UART_FLOWDEL 0x38 /* Flow Delay */ 62 #define CDNS_UART_IRRX_PWIDTH 0x3C /* IR Min Received Pulse Width */ 63 #define CDNS_UART_IRTX_PWIDTH 0x40 /* IR Transmitted pulse Width */ 64 #define CDNS_UART_TXWM 0x44 /* TX FIFO Trigger Level */ 65 #define CDNS_UART_RXBS 0x48 /* RX FIFO byte status register */ 66 67 /* Control Register Bit Definitions */ 68 #define CDNS_UART_CR_STOPBRK 0x00000100 /* Stop TX break */ 69 #define CDNS_UART_CR_STARTBRK 0x00000080 /* Set TX break */ 70 #define CDNS_UART_CR_TX_DIS 0x00000020 /* TX disabled. */ 71 #define CDNS_UART_CR_TX_EN 0x00000010 /* TX enabled */ 72 #define CDNS_UART_CR_RX_DIS 0x00000008 /* RX disabled. */ 73 #define CDNS_UART_CR_RX_EN 0x00000004 /* RX enabled */ 74 #define CDNS_UART_CR_TXRST 0x00000002 /* TX logic reset */ 75 #define CDNS_UART_CR_RXRST 0x00000001 /* RX logic reset */ 76 #define CDNS_UART_CR_RST_TO 0x00000040 /* Restart Timeout Counter */ 77 #define CDNS_UART_RXBS_PARITY 0x00000001 /* Parity error status */ 78 #define CDNS_UART_RXBS_FRAMING 0x00000002 /* Framing error status */ 79 #define CDNS_UART_RXBS_BRK 0x00000004 /* Overrun error status */ 80 81 /* 82 * Mode Register: 83 * The mode register (MR) defines the mode of transfer as well as the data 84 * format. If this register is modified during transmission or reception, 85 * data validity cannot be guaranteed. 86 */ 87 #define CDNS_UART_MR_CLKSEL 0x00000001 /* Pre-scalar selection */ 88 #define CDNS_UART_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */ 89 #define CDNS_UART_MR_CHMODE_NORM 0x00000000 /* Normal mode */ 90 #define CDNS_UART_MR_CHMODE_MASK 0x00000300 /* Mask for mode bits */ 91 92 #define CDNS_UART_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */ 93 #define CDNS_UART_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */ 94 95 #define CDNS_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */ 96 #define CDNS_UART_MR_PARITY_MARK 0x00000018 /* Mark parity mode */ 97 #define CDNS_UART_MR_PARITY_SPACE 0x00000010 /* Space parity mode */ 98 #define CDNS_UART_MR_PARITY_ODD 0x00000008 /* Odd parity mode */ 99 #define CDNS_UART_MR_PARITY_EVEN 0x00000000 /* Even parity mode */ 100 101 #define CDNS_UART_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */ 102 #define CDNS_UART_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */ 103 #define CDNS_UART_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */ 104 105 /* 106 * Interrupt Registers: 107 * Interrupt control logic uses the interrupt enable register (IER) and the 108 * interrupt disable register (IDR) to set the value of the bits in the 109 * interrupt mask register (IMR). The IMR determines whether to pass an 110 * interrupt to the interrupt status register (ISR). 111 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an 112 * interrupt. IMR and ISR are read only, and IER and IDR are write only. 113 * Reading either IER or IDR returns 0x00. 114 * All four registers have the same bit definitions. 115 */ 116 #define CDNS_UART_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */ 117 #define CDNS_UART_IXR_PARITY 0x00000080 /* Parity error interrupt */ 118 #define CDNS_UART_IXR_FRAMING 0x00000040 /* Framing error interrupt */ 119 #define CDNS_UART_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */ 120 #define CDNS_UART_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */ 121 #define CDNS_UART_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */ 122 #define CDNS_UART_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */ 123 #define CDNS_UART_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */ 124 #define CDNS_UART_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */ 125 #define CDNS_UART_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */ 126 #define CDNS_UART_IXR_RXMASK 0x000021e7 /* Valid RX bit mask */ 127 128 /* 129 * Do not enable parity error interrupt for the following 130 * reason: When parity error interrupt is enabled, each Rx 131 * parity error always results in 2 events. The first one 132 * being parity error interrupt and the second one with a 133 * proper Rx interrupt with the incoming data. Disabling 134 * parity error interrupt ensures better handling of parity 135 * error events. With this change, for a parity error case, we 136 * get a Rx interrupt with parity error set in ISR register 137 * and we still handle parity errors in the desired way. 138 */ 139 140 #define CDNS_UART_RX_IRQS (CDNS_UART_IXR_FRAMING | \ 141 CDNS_UART_IXR_OVERRUN | \ 142 CDNS_UART_IXR_RXTRIG | \ 143 CDNS_UART_IXR_TOUT) 144 145 /* Goes in read_status_mask for break detection as the HW doesn't do it*/ 146 #define CDNS_UART_IXR_BRK 0x00002000 147 148 #define CDNS_UART_RXBS_SUPPORT BIT(1) 149 /* 150 * Modem Control register: 151 * The read/write Modem Control register controls the interface with the modem 152 * or data set, or a peripheral device emulating a modem. 153 */ 154 #define CDNS_UART_MODEMCR_FCM 0x00000020 /* Automatic flow control mode */ 155 #define CDNS_UART_MODEMCR_RTS 0x00000002 /* Request to send output control */ 156 #define CDNS_UART_MODEMCR_DTR 0x00000001 /* Data Terminal Ready */ 157 158 /* 159 * Modem Status register: 160 * The read/write Modem Status register reports the interface with the modem 161 * or data set, or a peripheral device emulating a modem. 162 */ 163 #define CDNS_UART_MODEMSR_DCD BIT(7) /* Data Carrier Detect */ 164 #define CDNS_UART_MODEMSR_RI BIT(6) /* Ting Indicator */ 165 #define CDNS_UART_MODEMSR_DSR BIT(5) /* Data Set Ready */ 166 #define CDNS_UART_MODEMSR_CTS BIT(4) /* Clear To Send */ 167 168 /* 169 * Channel Status Register: 170 * The channel status register (CSR) is provided to enable the control logic 171 * to monitor the status of bits in the channel interrupt status register, 172 * even if these are masked out by the interrupt mask register. 173 */ 174 #define CDNS_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */ 175 #define CDNS_UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */ 176 #define CDNS_UART_SR_TXFULL 0x00000010 /* TX FIFO full */ 177 #define CDNS_UART_SR_RXTRIG 0x00000001 /* Rx Trigger */ 178 #define CDNS_UART_SR_TACTIVE 0x00000800 /* TX state machine active */ 179 180 /* baud dividers min/max values */ 181 #define CDNS_UART_BDIV_MIN 4 182 #define CDNS_UART_BDIV_MAX 255 183 #define CDNS_UART_CD_MAX 65535 184 #define UART_AUTOSUSPEND_TIMEOUT 3000 185 186 /** 187 * struct cdns_uart - device data 188 * @port: Pointer to the UART port 189 * @uartclk: Reference clock 190 * @pclk: APB clock 191 * @cdns_uart_driver: Pointer to UART driver 192 * @baud: Current baud rate 193 * @clk_rate_change_nb: Notifier block for clock changes 194 * @quirks: Flags for RXBS support. 195 * @cts_override: Modem control state override 196 */ 197 struct cdns_uart { 198 struct uart_port *port; 199 struct clk *uartclk; 200 struct clk *pclk; 201 struct uart_driver *cdns_uart_driver; 202 unsigned int baud; 203 struct notifier_block clk_rate_change_nb; 204 u32 quirks; 205 bool cts_override; 206 }; 207 struct cdns_platform_data { 208 u32 quirks; 209 }; 210 #define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \ 211 clk_rate_change_nb) 212 213 /** 214 * cdns_uart_handle_rx - Handle the received bytes along with Rx errors. 215 * @dev_id: Id of the UART port 216 * @isrstatus: The interrupt status register value as read 217 * Return: None 218 */ 219 static void cdns_uart_handle_rx(void *dev_id, unsigned int isrstatus) 220 { 221 struct uart_port *port = (struct uart_port *)dev_id; 222 struct cdns_uart *cdns_uart = port->private_data; 223 unsigned int data; 224 unsigned int rxbs_status = 0; 225 unsigned int status_mask; 226 unsigned int framerrprocessed = 0; 227 char status = TTY_NORMAL; 228 bool is_rxbs_support; 229 230 is_rxbs_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT; 231 232 while ((readl(port->membase + CDNS_UART_SR) & 233 CDNS_UART_SR_RXEMPTY) != CDNS_UART_SR_RXEMPTY) { 234 if (is_rxbs_support) 235 rxbs_status = readl(port->membase + CDNS_UART_RXBS); 236 data = readl(port->membase + CDNS_UART_FIFO); 237 port->icount.rx++; 238 /* 239 * There is no hardware break detection in Zynq, so we interpret 240 * framing error with all-zeros data as a break sequence. 241 * Most of the time, there's another non-zero byte at the 242 * end of the sequence. 243 */ 244 if (!is_rxbs_support && (isrstatus & CDNS_UART_IXR_FRAMING)) { 245 if (!data) { 246 port->read_status_mask |= CDNS_UART_IXR_BRK; 247 framerrprocessed = 1; 248 continue; 249 } 250 } 251 if (is_rxbs_support && (rxbs_status & CDNS_UART_RXBS_BRK)) { 252 port->icount.brk++; 253 status = TTY_BREAK; 254 if (uart_handle_break(port)) 255 continue; 256 } 257 258 isrstatus &= port->read_status_mask; 259 isrstatus &= ~port->ignore_status_mask; 260 status_mask = port->read_status_mask; 261 status_mask &= ~port->ignore_status_mask; 262 263 if (data && 264 (port->read_status_mask & CDNS_UART_IXR_BRK)) { 265 port->read_status_mask &= ~CDNS_UART_IXR_BRK; 266 port->icount.brk++; 267 if (uart_handle_break(port)) 268 continue; 269 } 270 271 if (uart_handle_sysrq_char(port, data)) 272 continue; 273 274 if (is_rxbs_support) { 275 if ((rxbs_status & CDNS_UART_RXBS_PARITY) 276 && (status_mask & CDNS_UART_IXR_PARITY)) { 277 port->icount.parity++; 278 status = TTY_PARITY; 279 } 280 if ((rxbs_status & CDNS_UART_RXBS_FRAMING) 281 && (status_mask & CDNS_UART_IXR_PARITY)) { 282 port->icount.frame++; 283 status = TTY_FRAME; 284 } 285 } else { 286 if (isrstatus & CDNS_UART_IXR_PARITY) { 287 port->icount.parity++; 288 status = TTY_PARITY; 289 } 290 if ((isrstatus & CDNS_UART_IXR_FRAMING) && 291 !framerrprocessed) { 292 port->icount.frame++; 293 status = TTY_FRAME; 294 } 295 } 296 if (isrstatus & CDNS_UART_IXR_OVERRUN) { 297 port->icount.overrun++; 298 tty_insert_flip_char(&port->state->port, 0, 299 TTY_OVERRUN); 300 } 301 tty_insert_flip_char(&port->state->port, data, status); 302 isrstatus = 0; 303 } 304 305 tty_flip_buffer_push(&port->state->port); 306 } 307 308 /** 309 * cdns_uart_handle_tx - Handle the bytes to be Txed. 310 * @dev_id: Id of the UART port 311 * Return: None 312 */ 313 static void cdns_uart_handle_tx(void *dev_id) 314 { 315 struct uart_port *port = (struct uart_port *)dev_id; 316 struct circ_buf *xmit = &port->state->xmit; 317 unsigned int numbytes; 318 319 if (uart_circ_empty(xmit)) { 320 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR); 321 return; 322 } 323 324 numbytes = port->fifosize; 325 while (numbytes && !uart_circ_empty(xmit) && 326 !(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL)) { 327 328 writel(xmit->buf[xmit->tail], port->membase + CDNS_UART_FIFO); 329 330 port->icount.tx++; 331 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 332 numbytes--; 333 } 334 335 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 336 uart_write_wakeup(port); 337 } 338 339 /** 340 * cdns_uart_isr - Interrupt handler 341 * @irq: Irq number 342 * @dev_id: Id of the port 343 * 344 * Return: IRQHANDLED 345 */ 346 static irqreturn_t cdns_uart_isr(int irq, void *dev_id) 347 { 348 struct uart_port *port = (struct uart_port *)dev_id; 349 unsigned int isrstatus; 350 351 spin_lock(&port->lock); 352 353 /* Read the interrupt status register to determine which 354 * interrupt(s) is/are active and clear them. 355 */ 356 isrstatus = readl(port->membase + CDNS_UART_ISR); 357 writel(isrstatus, port->membase + CDNS_UART_ISR); 358 359 if (isrstatus & CDNS_UART_IXR_TXEMPTY) { 360 cdns_uart_handle_tx(dev_id); 361 isrstatus &= ~CDNS_UART_IXR_TXEMPTY; 362 } 363 364 /* 365 * Skip RX processing if RX is disabled as RXEMPTY will never be set 366 * as read bytes will not be removed from the FIFO. 367 */ 368 if (isrstatus & CDNS_UART_IXR_RXMASK && 369 !(readl(port->membase + CDNS_UART_CR) & CDNS_UART_CR_RX_DIS)) 370 cdns_uart_handle_rx(dev_id, isrstatus); 371 372 spin_unlock(&port->lock); 373 return IRQ_HANDLED; 374 } 375 376 /** 377 * cdns_uart_calc_baud_divs - Calculate baud rate divisors 378 * @clk: UART module input clock 379 * @baud: Desired baud rate 380 * @rbdiv: BDIV value (return value) 381 * @rcd: CD value (return value) 382 * @div8: Value for clk_sel bit in mod (return value) 383 * Return: baud rate, requested baud when possible, or actual baud when there 384 * was too much error, zero if no valid divisors are found. 385 * 386 * Formula to obtain baud rate is 387 * baud_tx/rx rate = clk/CD * (BDIV + 1) 388 * input_clk = (Uart User Defined Clock or Apb Clock) 389 * depends on UCLKEN in MR Reg 390 * clk = input_clk or input_clk/8; 391 * depends on CLKS in MR reg 392 * CD and BDIV depends on values in 393 * baud rate generate register 394 * baud rate clock divisor register 395 */ 396 static unsigned int cdns_uart_calc_baud_divs(unsigned int clk, 397 unsigned int baud, u32 *rbdiv, u32 *rcd, int *div8) 398 { 399 u32 cd, bdiv; 400 unsigned int calc_baud; 401 unsigned int bestbaud = 0; 402 unsigned int bauderror; 403 unsigned int besterror = ~0; 404 405 if (baud < clk / ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX)) { 406 *div8 = 1; 407 clk /= 8; 408 } else { 409 *div8 = 0; 410 } 411 412 for (bdiv = CDNS_UART_BDIV_MIN; bdiv <= CDNS_UART_BDIV_MAX; bdiv++) { 413 cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1)); 414 if (cd < 1 || cd > CDNS_UART_CD_MAX) 415 continue; 416 417 calc_baud = clk / (cd * (bdiv + 1)); 418 419 if (baud > calc_baud) 420 bauderror = baud - calc_baud; 421 else 422 bauderror = calc_baud - baud; 423 424 if (besterror > bauderror) { 425 *rbdiv = bdiv; 426 *rcd = cd; 427 bestbaud = calc_baud; 428 besterror = bauderror; 429 } 430 } 431 /* use the values when percent error is acceptable */ 432 if (((besterror * 100) / baud) < 3) 433 bestbaud = baud; 434 435 return bestbaud; 436 } 437 438 /** 439 * cdns_uart_set_baud_rate - Calculate and set the baud rate 440 * @port: Handle to the uart port structure 441 * @baud: Baud rate to set 442 * Return: baud rate, requested baud when possible, or actual baud when there 443 * was too much error, zero if no valid divisors are found. 444 */ 445 static unsigned int cdns_uart_set_baud_rate(struct uart_port *port, 446 unsigned int baud) 447 { 448 unsigned int calc_baud; 449 u32 cd = 0, bdiv = 0; 450 u32 mreg; 451 int div8; 452 struct cdns_uart *cdns_uart = port->private_data; 453 454 calc_baud = cdns_uart_calc_baud_divs(port->uartclk, baud, &bdiv, &cd, 455 &div8); 456 457 /* Write new divisors to hardware */ 458 mreg = readl(port->membase + CDNS_UART_MR); 459 if (div8) 460 mreg |= CDNS_UART_MR_CLKSEL; 461 else 462 mreg &= ~CDNS_UART_MR_CLKSEL; 463 writel(mreg, port->membase + CDNS_UART_MR); 464 writel(cd, port->membase + CDNS_UART_BAUDGEN); 465 writel(bdiv, port->membase + CDNS_UART_BAUDDIV); 466 cdns_uart->baud = baud; 467 468 return calc_baud; 469 } 470 471 #ifdef CONFIG_COMMON_CLK 472 /** 473 * cdns_uart_clk_notifier_cb - Clock notifier callback 474 * @nb: Notifier block 475 * @event: Notify event 476 * @data: Notifier data 477 * Return: NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error. 478 */ 479 static int cdns_uart_clk_notifier_cb(struct notifier_block *nb, 480 unsigned long event, void *data) 481 { 482 u32 ctrl_reg; 483 struct uart_port *port; 484 int locked = 0; 485 struct clk_notifier_data *ndata = data; 486 struct cdns_uart *cdns_uart = to_cdns_uart(nb); 487 unsigned long flags; 488 489 port = cdns_uart->port; 490 if (port->suspended) 491 return NOTIFY_OK; 492 493 switch (event) { 494 case PRE_RATE_CHANGE: 495 { 496 u32 bdiv, cd; 497 int div8; 498 499 /* 500 * Find out if current baud-rate can be achieved with new clock 501 * frequency. 502 */ 503 if (!cdns_uart_calc_baud_divs(ndata->new_rate, cdns_uart->baud, 504 &bdiv, &cd, &div8)) { 505 dev_warn(port->dev, "clock rate change rejected\n"); 506 return NOTIFY_BAD; 507 } 508 509 spin_lock_irqsave(&cdns_uart->port->lock, flags); 510 511 /* Disable the TX and RX to set baud rate */ 512 ctrl_reg = readl(port->membase + CDNS_UART_CR); 513 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS; 514 writel(ctrl_reg, port->membase + CDNS_UART_CR); 515 516 spin_unlock_irqrestore(&cdns_uart->port->lock, flags); 517 518 return NOTIFY_OK; 519 } 520 case POST_RATE_CHANGE: 521 /* 522 * Set clk dividers to generate correct baud with new clock 523 * frequency. 524 */ 525 526 spin_lock_irqsave(&cdns_uart->port->lock, flags); 527 528 locked = 1; 529 port->uartclk = ndata->new_rate; 530 531 cdns_uart->baud = cdns_uart_set_baud_rate(cdns_uart->port, 532 cdns_uart->baud); 533 fallthrough; 534 case ABORT_RATE_CHANGE: 535 if (!locked) 536 spin_lock_irqsave(&cdns_uart->port->lock, flags); 537 538 /* Set TX/RX Reset */ 539 ctrl_reg = readl(port->membase + CDNS_UART_CR); 540 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST; 541 writel(ctrl_reg, port->membase + CDNS_UART_CR); 542 543 while (readl(port->membase + CDNS_UART_CR) & 544 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST)) 545 cpu_relax(); 546 547 /* 548 * Clear the RX disable and TX disable bits and then set the TX 549 * enable bit and RX enable bit to enable the transmitter and 550 * receiver. 551 */ 552 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT); 553 ctrl_reg = readl(port->membase + CDNS_UART_CR); 554 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS); 555 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN; 556 writel(ctrl_reg, port->membase + CDNS_UART_CR); 557 558 spin_unlock_irqrestore(&cdns_uart->port->lock, flags); 559 560 return NOTIFY_OK; 561 default: 562 return NOTIFY_DONE; 563 } 564 } 565 #endif 566 567 /** 568 * cdns_uart_start_tx - Start transmitting bytes 569 * @port: Handle to the uart port structure 570 */ 571 static void cdns_uart_start_tx(struct uart_port *port) 572 { 573 unsigned int status; 574 575 if (uart_tx_stopped(port)) 576 return; 577 578 /* 579 * Set the TX enable bit and clear the TX disable bit to enable the 580 * transmitter. 581 */ 582 status = readl(port->membase + CDNS_UART_CR); 583 status &= ~CDNS_UART_CR_TX_DIS; 584 status |= CDNS_UART_CR_TX_EN; 585 writel(status, port->membase + CDNS_UART_CR); 586 587 if (uart_circ_empty(&port->state->xmit)) 588 return; 589 590 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR); 591 592 cdns_uart_handle_tx(port); 593 594 /* Enable the TX Empty interrupt */ 595 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IER); 596 } 597 598 /** 599 * cdns_uart_stop_tx - Stop TX 600 * @port: Handle to the uart port structure 601 */ 602 static void cdns_uart_stop_tx(struct uart_port *port) 603 { 604 unsigned int regval; 605 606 regval = readl(port->membase + CDNS_UART_CR); 607 regval |= CDNS_UART_CR_TX_DIS; 608 /* Disable the transmitter */ 609 writel(regval, port->membase + CDNS_UART_CR); 610 } 611 612 /** 613 * cdns_uart_stop_rx - Stop RX 614 * @port: Handle to the uart port structure 615 */ 616 static void cdns_uart_stop_rx(struct uart_port *port) 617 { 618 unsigned int regval; 619 620 /* Disable RX IRQs */ 621 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IDR); 622 623 /* Disable the receiver */ 624 regval = readl(port->membase + CDNS_UART_CR); 625 regval |= CDNS_UART_CR_RX_DIS; 626 writel(regval, port->membase + CDNS_UART_CR); 627 } 628 629 /** 630 * cdns_uart_tx_empty - Check whether TX is empty 631 * @port: Handle to the uart port structure 632 * 633 * Return: TIOCSER_TEMT on success, 0 otherwise 634 */ 635 static unsigned int cdns_uart_tx_empty(struct uart_port *port) 636 { 637 unsigned int status; 638 639 status = readl(port->membase + CDNS_UART_SR) & 640 (CDNS_UART_SR_TXEMPTY | CDNS_UART_SR_TACTIVE); 641 return (status == CDNS_UART_SR_TXEMPTY) ? TIOCSER_TEMT : 0; 642 } 643 644 /** 645 * cdns_uart_break_ctl - Based on the input ctl we have to start or stop 646 * transmitting char breaks 647 * @port: Handle to the uart port structure 648 * @ctl: Value based on which start or stop decision is taken 649 */ 650 static void cdns_uart_break_ctl(struct uart_port *port, int ctl) 651 { 652 unsigned int status; 653 unsigned long flags; 654 655 spin_lock_irqsave(&port->lock, flags); 656 657 status = readl(port->membase + CDNS_UART_CR); 658 659 if (ctl == -1) 660 writel(CDNS_UART_CR_STARTBRK | status, 661 port->membase + CDNS_UART_CR); 662 else { 663 if ((status & CDNS_UART_CR_STOPBRK) == 0) 664 writel(CDNS_UART_CR_STOPBRK | status, 665 port->membase + CDNS_UART_CR); 666 } 667 spin_unlock_irqrestore(&port->lock, flags); 668 } 669 670 /** 671 * cdns_uart_set_termios - termios operations, handling data length, parity, 672 * stop bits, flow control, baud rate 673 * @port: Handle to the uart port structure 674 * @termios: Handle to the input termios structure 675 * @old: Values of the previously saved termios structure 676 */ 677 static void cdns_uart_set_termios(struct uart_port *port, 678 struct ktermios *termios, struct ktermios *old) 679 { 680 u32 cval = 0; 681 unsigned int baud, minbaud, maxbaud; 682 unsigned long flags; 683 unsigned int ctrl_reg, mode_reg; 684 685 spin_lock_irqsave(&port->lock, flags); 686 687 /* Disable the TX and RX to set baud rate */ 688 ctrl_reg = readl(port->membase + CDNS_UART_CR); 689 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS; 690 writel(ctrl_reg, port->membase + CDNS_UART_CR); 691 692 /* 693 * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk 694 * min and max baud should be calculated here based on port->uartclk. 695 * this way we get a valid baud and can safely call set_baud() 696 */ 697 minbaud = port->uartclk / 698 ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX * 8); 699 maxbaud = port->uartclk / (CDNS_UART_BDIV_MIN + 1); 700 baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud); 701 baud = cdns_uart_set_baud_rate(port, baud); 702 if (tty_termios_baud_rate(termios)) 703 tty_termios_encode_baud_rate(termios, baud, baud); 704 705 /* Update the per-port timeout. */ 706 uart_update_timeout(port, termios->c_cflag, baud); 707 708 /* Set TX/RX Reset */ 709 ctrl_reg = readl(port->membase + CDNS_UART_CR); 710 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST; 711 writel(ctrl_reg, port->membase + CDNS_UART_CR); 712 713 while (readl(port->membase + CDNS_UART_CR) & 714 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST)) 715 cpu_relax(); 716 717 /* 718 * Clear the RX disable and TX disable bits and then set the TX enable 719 * bit and RX enable bit to enable the transmitter and receiver. 720 */ 721 ctrl_reg = readl(port->membase + CDNS_UART_CR); 722 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS); 723 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN; 724 writel(ctrl_reg, port->membase + CDNS_UART_CR); 725 726 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT); 727 728 port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG | 729 CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT; 730 port->ignore_status_mask = 0; 731 732 if (termios->c_iflag & INPCK) 733 port->read_status_mask |= CDNS_UART_IXR_PARITY | 734 CDNS_UART_IXR_FRAMING; 735 736 if (termios->c_iflag & IGNPAR) 737 port->ignore_status_mask |= CDNS_UART_IXR_PARITY | 738 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN; 739 740 /* ignore all characters if CREAD is not set */ 741 if ((termios->c_cflag & CREAD) == 0) 742 port->ignore_status_mask |= CDNS_UART_IXR_RXTRIG | 743 CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY | 744 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN; 745 746 mode_reg = readl(port->membase + CDNS_UART_MR); 747 748 /* Handling Data Size */ 749 switch (termios->c_cflag & CSIZE) { 750 case CS6: 751 cval |= CDNS_UART_MR_CHARLEN_6_BIT; 752 break; 753 case CS7: 754 cval |= CDNS_UART_MR_CHARLEN_7_BIT; 755 break; 756 default: 757 case CS8: 758 cval |= CDNS_UART_MR_CHARLEN_8_BIT; 759 termios->c_cflag &= ~CSIZE; 760 termios->c_cflag |= CS8; 761 break; 762 } 763 764 /* Handling Parity and Stop Bits length */ 765 if (termios->c_cflag & CSTOPB) 766 cval |= CDNS_UART_MR_STOPMODE_2_BIT; /* 2 STOP bits */ 767 else 768 cval |= CDNS_UART_MR_STOPMODE_1_BIT; /* 1 STOP bit */ 769 770 if (termios->c_cflag & PARENB) { 771 /* Mark or Space parity */ 772 if (termios->c_cflag & CMSPAR) { 773 if (termios->c_cflag & PARODD) 774 cval |= CDNS_UART_MR_PARITY_MARK; 775 else 776 cval |= CDNS_UART_MR_PARITY_SPACE; 777 } else { 778 if (termios->c_cflag & PARODD) 779 cval |= CDNS_UART_MR_PARITY_ODD; 780 else 781 cval |= CDNS_UART_MR_PARITY_EVEN; 782 } 783 } else { 784 cval |= CDNS_UART_MR_PARITY_NONE; 785 } 786 cval |= mode_reg & 1; 787 writel(cval, port->membase + CDNS_UART_MR); 788 789 cval = readl(port->membase + CDNS_UART_MODEMCR); 790 if (termios->c_cflag & CRTSCTS) 791 cval |= CDNS_UART_MODEMCR_FCM; 792 else 793 cval &= ~CDNS_UART_MODEMCR_FCM; 794 writel(cval, port->membase + CDNS_UART_MODEMCR); 795 796 spin_unlock_irqrestore(&port->lock, flags); 797 } 798 799 /** 800 * cdns_uart_startup - Called when an application opens a cdns_uart port 801 * @port: Handle to the uart port structure 802 * 803 * Return: 0 on success, negative errno otherwise 804 */ 805 static int cdns_uart_startup(struct uart_port *port) 806 { 807 struct cdns_uart *cdns_uart = port->private_data; 808 bool is_brk_support; 809 int ret; 810 unsigned long flags; 811 unsigned int status = 0; 812 813 is_brk_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT; 814 815 spin_lock_irqsave(&port->lock, flags); 816 817 /* Disable the TX and RX */ 818 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS, 819 port->membase + CDNS_UART_CR); 820 821 /* Set the Control Register with TX/RX Enable, TX/RX Reset, 822 * no break chars. 823 */ 824 writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST, 825 port->membase + CDNS_UART_CR); 826 827 while (readl(port->membase + CDNS_UART_CR) & 828 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST)) 829 cpu_relax(); 830 831 /* 832 * Clear the RX disable bit and then set the RX enable bit to enable 833 * the receiver. 834 */ 835 status = readl(port->membase + CDNS_UART_CR); 836 status &= ~CDNS_UART_CR_RX_DIS; 837 status |= CDNS_UART_CR_RX_EN; 838 writel(status, port->membase + CDNS_UART_CR); 839 840 /* Set the Mode Register with normal mode,8 data bits,1 stop bit, 841 * no parity. 842 */ 843 writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT 844 | CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT, 845 port->membase + CDNS_UART_MR); 846 847 /* 848 * Set the RX FIFO Trigger level to use most of the FIFO, but it 849 * can be tuned with a module parameter 850 */ 851 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM); 852 853 /* 854 * Receive Timeout register is enabled but it 855 * can be tuned with a module parameter 856 */ 857 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT); 858 859 /* Clear out any pending interrupts before enabling them */ 860 writel(readl(port->membase + CDNS_UART_ISR), 861 port->membase + CDNS_UART_ISR); 862 863 spin_unlock_irqrestore(&port->lock, flags); 864 865 ret = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME, port); 866 if (ret) { 867 dev_err(port->dev, "request_irq '%d' failed with %d\n", 868 port->irq, ret); 869 return ret; 870 } 871 872 /* Set the Interrupt Registers with desired interrupts */ 873 if (is_brk_support) 874 writel(CDNS_UART_RX_IRQS | CDNS_UART_IXR_BRK, 875 port->membase + CDNS_UART_IER); 876 else 877 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IER); 878 879 return 0; 880 } 881 882 /** 883 * cdns_uart_shutdown - Called when an application closes a cdns_uart port 884 * @port: Handle to the uart port structure 885 */ 886 static void cdns_uart_shutdown(struct uart_port *port) 887 { 888 int status; 889 unsigned long flags; 890 891 spin_lock_irqsave(&port->lock, flags); 892 893 /* Disable interrupts */ 894 status = readl(port->membase + CDNS_UART_IMR); 895 writel(status, port->membase + CDNS_UART_IDR); 896 writel(0xffffffff, port->membase + CDNS_UART_ISR); 897 898 /* Disable the TX and RX */ 899 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS, 900 port->membase + CDNS_UART_CR); 901 902 spin_unlock_irqrestore(&port->lock, flags); 903 904 free_irq(port->irq, port); 905 } 906 907 /** 908 * cdns_uart_type - Set UART type to cdns_uart port 909 * @port: Handle to the uart port structure 910 * 911 * Return: string on success, NULL otherwise 912 */ 913 static const char *cdns_uart_type(struct uart_port *port) 914 { 915 return port->type == PORT_XUARTPS ? CDNS_UART_NAME : NULL; 916 } 917 918 /** 919 * cdns_uart_verify_port - Verify the port params 920 * @port: Handle to the uart port structure 921 * @ser: Handle to the structure whose members are compared 922 * 923 * Return: 0 on success, negative errno otherwise. 924 */ 925 static int cdns_uart_verify_port(struct uart_port *port, 926 struct serial_struct *ser) 927 { 928 if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS) 929 return -EINVAL; 930 if (port->irq != ser->irq) 931 return -EINVAL; 932 if (ser->io_type != UPIO_MEM) 933 return -EINVAL; 934 if (port->iobase != ser->port) 935 return -EINVAL; 936 if (ser->hub6 != 0) 937 return -EINVAL; 938 return 0; 939 } 940 941 /** 942 * cdns_uart_request_port - Claim the memory region attached to cdns_uart port, 943 * called when the driver adds a cdns_uart port via 944 * uart_add_one_port() 945 * @port: Handle to the uart port structure 946 * 947 * Return: 0 on success, negative errno otherwise. 948 */ 949 static int cdns_uart_request_port(struct uart_port *port) 950 { 951 if (!request_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE, 952 CDNS_UART_NAME)) { 953 return -ENOMEM; 954 } 955 956 port->membase = ioremap(port->mapbase, CDNS_UART_REGISTER_SPACE); 957 if (!port->membase) { 958 dev_err(port->dev, "Unable to map registers\n"); 959 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE); 960 return -ENOMEM; 961 } 962 return 0; 963 } 964 965 /** 966 * cdns_uart_release_port - Release UART port 967 * @port: Handle to the uart port structure 968 * 969 * Release the memory region attached to a cdns_uart port. Called when the 970 * driver removes a cdns_uart port via uart_remove_one_port(). 971 */ 972 static void cdns_uart_release_port(struct uart_port *port) 973 { 974 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE); 975 iounmap(port->membase); 976 port->membase = NULL; 977 } 978 979 /** 980 * cdns_uart_config_port - Configure UART port 981 * @port: Handle to the uart port structure 982 * @flags: If any 983 */ 984 static void cdns_uart_config_port(struct uart_port *port, int flags) 985 { 986 if (flags & UART_CONFIG_TYPE && cdns_uart_request_port(port) == 0) 987 port->type = PORT_XUARTPS; 988 } 989 990 /** 991 * cdns_uart_get_mctrl - Get the modem control state 992 * @port: Handle to the uart port structure 993 * 994 * Return: the modem control state 995 */ 996 static unsigned int cdns_uart_get_mctrl(struct uart_port *port) 997 { 998 u32 val; 999 unsigned int mctrl = 0; 1000 struct cdns_uart *cdns_uart_data = port->private_data; 1001 1002 if (cdns_uart_data->cts_override) 1003 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; 1004 1005 val = readl(port->membase + CDNS_UART_MODEMSR); 1006 if (val & CDNS_UART_MODEMSR_CTS) 1007 mctrl |= TIOCM_CTS; 1008 if (val & CDNS_UART_MODEMSR_DSR) 1009 mctrl |= TIOCM_DSR; 1010 if (val & CDNS_UART_MODEMSR_RI) 1011 mctrl |= TIOCM_RNG; 1012 if (val & CDNS_UART_MODEMSR_DCD) 1013 mctrl |= TIOCM_CAR; 1014 1015 return mctrl; 1016 } 1017 1018 static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 1019 { 1020 u32 val; 1021 u32 mode_reg; 1022 struct cdns_uart *cdns_uart_data = port->private_data; 1023 1024 if (cdns_uart_data->cts_override) 1025 return; 1026 1027 val = readl(port->membase + CDNS_UART_MODEMCR); 1028 mode_reg = readl(port->membase + CDNS_UART_MR); 1029 1030 val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR); 1031 mode_reg &= ~CDNS_UART_MR_CHMODE_MASK; 1032 1033 if (mctrl & TIOCM_RTS) 1034 val |= CDNS_UART_MODEMCR_RTS; 1035 if (mctrl & TIOCM_DTR) 1036 val |= CDNS_UART_MODEMCR_DTR; 1037 if (mctrl & TIOCM_LOOP) 1038 mode_reg |= CDNS_UART_MR_CHMODE_L_LOOP; 1039 else 1040 mode_reg |= CDNS_UART_MR_CHMODE_NORM; 1041 1042 writel(val, port->membase + CDNS_UART_MODEMCR); 1043 writel(mode_reg, port->membase + CDNS_UART_MR); 1044 } 1045 1046 #ifdef CONFIG_CONSOLE_POLL 1047 static int cdns_uart_poll_get_char(struct uart_port *port) 1048 { 1049 int c; 1050 unsigned long flags; 1051 1052 spin_lock_irqsave(&port->lock, flags); 1053 1054 /* Check if FIFO is empty */ 1055 if (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_RXEMPTY) 1056 c = NO_POLL_CHAR; 1057 else /* Read a character */ 1058 c = (unsigned char) readl(port->membase + CDNS_UART_FIFO); 1059 1060 spin_unlock_irqrestore(&port->lock, flags); 1061 1062 return c; 1063 } 1064 1065 static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c) 1066 { 1067 unsigned long flags; 1068 1069 spin_lock_irqsave(&port->lock, flags); 1070 1071 /* Wait until FIFO is empty */ 1072 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY)) 1073 cpu_relax(); 1074 1075 /* Write a character */ 1076 writel(c, port->membase + CDNS_UART_FIFO); 1077 1078 /* Wait until FIFO is empty */ 1079 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY)) 1080 cpu_relax(); 1081 1082 spin_unlock_irqrestore(&port->lock, flags); 1083 } 1084 #endif 1085 1086 static void cdns_uart_pm(struct uart_port *port, unsigned int state, 1087 unsigned int oldstate) 1088 { 1089 switch (state) { 1090 case UART_PM_STATE_OFF: 1091 pm_runtime_mark_last_busy(port->dev); 1092 pm_runtime_put_autosuspend(port->dev); 1093 break; 1094 default: 1095 pm_runtime_get_sync(port->dev); 1096 break; 1097 } 1098 } 1099 1100 static const struct uart_ops cdns_uart_ops = { 1101 .set_mctrl = cdns_uart_set_mctrl, 1102 .get_mctrl = cdns_uart_get_mctrl, 1103 .start_tx = cdns_uart_start_tx, 1104 .stop_tx = cdns_uart_stop_tx, 1105 .stop_rx = cdns_uart_stop_rx, 1106 .tx_empty = cdns_uart_tx_empty, 1107 .break_ctl = cdns_uart_break_ctl, 1108 .set_termios = cdns_uart_set_termios, 1109 .startup = cdns_uart_startup, 1110 .shutdown = cdns_uart_shutdown, 1111 .pm = cdns_uart_pm, 1112 .type = cdns_uart_type, 1113 .verify_port = cdns_uart_verify_port, 1114 .request_port = cdns_uart_request_port, 1115 .release_port = cdns_uart_release_port, 1116 .config_port = cdns_uart_config_port, 1117 #ifdef CONFIG_CONSOLE_POLL 1118 .poll_get_char = cdns_uart_poll_get_char, 1119 .poll_put_char = cdns_uart_poll_put_char, 1120 #endif 1121 }; 1122 1123 static struct uart_driver cdns_uart_uart_driver; 1124 1125 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE 1126 /** 1127 * cdns_uart_console_putchar - write the character to the FIFO buffer 1128 * @port: Handle to the uart port structure 1129 * @ch: Character to be written 1130 */ 1131 static void cdns_uart_console_putchar(struct uart_port *port, unsigned char ch) 1132 { 1133 while (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL) 1134 cpu_relax(); 1135 writel(ch, port->membase + CDNS_UART_FIFO); 1136 } 1137 1138 static void cdns_early_write(struct console *con, const char *s, 1139 unsigned int n) 1140 { 1141 struct earlycon_device *dev = con->data; 1142 1143 uart_console_write(&dev->port, s, n, cdns_uart_console_putchar); 1144 } 1145 1146 static int __init cdns_early_console_setup(struct earlycon_device *device, 1147 const char *opt) 1148 { 1149 struct uart_port *port = &device->port; 1150 1151 if (!port->membase) 1152 return -ENODEV; 1153 1154 /* initialise control register */ 1155 writel(CDNS_UART_CR_TX_EN|CDNS_UART_CR_TXRST|CDNS_UART_CR_RXRST, 1156 port->membase + CDNS_UART_CR); 1157 1158 /* only set baud if specified on command line - otherwise 1159 * assume it has been initialized by a boot loader. 1160 */ 1161 if (port->uartclk && device->baud) { 1162 u32 cd = 0, bdiv = 0; 1163 u32 mr; 1164 int div8; 1165 1166 cdns_uart_calc_baud_divs(port->uartclk, device->baud, 1167 &bdiv, &cd, &div8); 1168 mr = CDNS_UART_MR_PARITY_NONE; 1169 if (div8) 1170 mr |= CDNS_UART_MR_CLKSEL; 1171 1172 writel(mr, port->membase + CDNS_UART_MR); 1173 writel(cd, port->membase + CDNS_UART_BAUDGEN); 1174 writel(bdiv, port->membase + CDNS_UART_BAUDDIV); 1175 } 1176 1177 device->con->write = cdns_early_write; 1178 1179 return 0; 1180 } 1181 OF_EARLYCON_DECLARE(cdns, "xlnx,xuartps", cdns_early_console_setup); 1182 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p8", cdns_early_console_setup); 1183 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p12", cdns_early_console_setup); 1184 OF_EARLYCON_DECLARE(cdns, "xlnx,zynqmp-uart", cdns_early_console_setup); 1185 1186 1187 /* Static pointer to console port */ 1188 static struct uart_port *console_port; 1189 1190 /** 1191 * cdns_uart_console_write - perform write operation 1192 * @co: Console handle 1193 * @s: Pointer to character array 1194 * @count: No of characters 1195 */ 1196 static void cdns_uart_console_write(struct console *co, const char *s, 1197 unsigned int count) 1198 { 1199 struct uart_port *port = console_port; 1200 unsigned long flags; 1201 unsigned int imr, ctrl; 1202 int locked = 1; 1203 1204 if (port->sysrq) 1205 locked = 0; 1206 else if (oops_in_progress) 1207 locked = spin_trylock_irqsave(&port->lock, flags); 1208 else 1209 spin_lock_irqsave(&port->lock, flags); 1210 1211 /* save and disable interrupt */ 1212 imr = readl(port->membase + CDNS_UART_IMR); 1213 writel(imr, port->membase + CDNS_UART_IDR); 1214 1215 /* 1216 * Make sure that the tx part is enabled. Set the TX enable bit and 1217 * clear the TX disable bit to enable the transmitter. 1218 */ 1219 ctrl = readl(port->membase + CDNS_UART_CR); 1220 ctrl &= ~CDNS_UART_CR_TX_DIS; 1221 ctrl |= CDNS_UART_CR_TX_EN; 1222 writel(ctrl, port->membase + CDNS_UART_CR); 1223 1224 uart_console_write(port, s, count, cdns_uart_console_putchar); 1225 while (cdns_uart_tx_empty(port) != TIOCSER_TEMT) 1226 cpu_relax(); 1227 1228 /* restore interrupt state */ 1229 writel(imr, port->membase + CDNS_UART_IER); 1230 1231 if (locked) 1232 spin_unlock_irqrestore(&port->lock, flags); 1233 } 1234 1235 /** 1236 * cdns_uart_console_setup - Initialize the uart to default config 1237 * @co: Console handle 1238 * @options: Initial settings of uart 1239 * 1240 * Return: 0 on success, negative errno otherwise. 1241 */ 1242 static int cdns_uart_console_setup(struct console *co, char *options) 1243 { 1244 struct uart_port *port = console_port; 1245 1246 int baud = 9600; 1247 int bits = 8; 1248 int parity = 'n'; 1249 int flow = 'n'; 1250 unsigned long time_out; 1251 1252 if (!port->membase) { 1253 pr_debug("console on " CDNS_UART_TTY_NAME "%i not present\n", 1254 co->index); 1255 return -ENODEV; 1256 } 1257 1258 if (options) 1259 uart_parse_options(options, &baud, &parity, &bits, &flow); 1260 1261 /* Wait for tx_empty before setting up the console */ 1262 time_out = jiffies + usecs_to_jiffies(TX_TIMEOUT); 1263 1264 while (time_before(jiffies, time_out) && 1265 cdns_uart_tx_empty(port) != TIOCSER_TEMT) 1266 cpu_relax(); 1267 1268 return uart_set_options(port, co, baud, parity, bits, flow); 1269 } 1270 1271 static struct console cdns_uart_console = { 1272 .name = CDNS_UART_TTY_NAME, 1273 .write = cdns_uart_console_write, 1274 .device = uart_console_device, 1275 .setup = cdns_uart_console_setup, 1276 .flags = CON_PRINTBUFFER, 1277 .index = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */ 1278 .data = &cdns_uart_uart_driver, 1279 }; 1280 #endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */ 1281 1282 #ifdef CONFIG_PM_SLEEP 1283 /** 1284 * cdns_uart_suspend - suspend event 1285 * @device: Pointer to the device structure 1286 * 1287 * Return: 0 1288 */ 1289 static int cdns_uart_suspend(struct device *device) 1290 { 1291 struct uart_port *port = dev_get_drvdata(device); 1292 struct cdns_uart *cdns_uart = port->private_data; 1293 int may_wake; 1294 1295 may_wake = device_may_wakeup(device); 1296 1297 if (console_suspend_enabled && uart_console(port) && may_wake) { 1298 unsigned long flags; 1299 1300 spin_lock_irqsave(&port->lock, flags); 1301 /* Empty the receive FIFO 1st before making changes */ 1302 while (!(readl(port->membase + CDNS_UART_SR) & 1303 CDNS_UART_SR_RXEMPTY)) 1304 readl(port->membase + CDNS_UART_FIFO); 1305 /* set RX trigger level to 1 */ 1306 writel(1, port->membase + CDNS_UART_RXWM); 1307 /* disable RX timeout interrups */ 1308 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IDR); 1309 spin_unlock_irqrestore(&port->lock, flags); 1310 } 1311 1312 /* 1313 * Call the API provided in serial_core.c file which handles 1314 * the suspend. 1315 */ 1316 return uart_suspend_port(cdns_uart->cdns_uart_driver, port); 1317 } 1318 1319 /** 1320 * cdns_uart_resume - Resume after a previous suspend 1321 * @device: Pointer to the device structure 1322 * 1323 * Return: 0 1324 */ 1325 static int cdns_uart_resume(struct device *device) 1326 { 1327 struct uart_port *port = dev_get_drvdata(device); 1328 struct cdns_uart *cdns_uart = port->private_data; 1329 unsigned long flags; 1330 u32 ctrl_reg; 1331 int may_wake; 1332 1333 may_wake = device_may_wakeup(device); 1334 1335 if (console_suspend_enabled && uart_console(port) && !may_wake) { 1336 clk_enable(cdns_uart->pclk); 1337 clk_enable(cdns_uart->uartclk); 1338 1339 spin_lock_irqsave(&port->lock, flags); 1340 1341 /* Set TX/RX Reset */ 1342 ctrl_reg = readl(port->membase + CDNS_UART_CR); 1343 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST; 1344 writel(ctrl_reg, port->membase + CDNS_UART_CR); 1345 while (readl(port->membase + CDNS_UART_CR) & 1346 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST)) 1347 cpu_relax(); 1348 1349 /* restore rx timeout value */ 1350 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT); 1351 /* Enable Tx/Rx */ 1352 ctrl_reg = readl(port->membase + CDNS_UART_CR); 1353 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS); 1354 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN; 1355 writel(ctrl_reg, port->membase + CDNS_UART_CR); 1356 1357 clk_disable(cdns_uart->uartclk); 1358 clk_disable(cdns_uart->pclk); 1359 spin_unlock_irqrestore(&port->lock, flags); 1360 } else { 1361 spin_lock_irqsave(&port->lock, flags); 1362 /* restore original rx trigger level */ 1363 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM); 1364 /* enable RX timeout interrupt */ 1365 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IER); 1366 spin_unlock_irqrestore(&port->lock, flags); 1367 } 1368 1369 return uart_resume_port(cdns_uart->cdns_uart_driver, port); 1370 } 1371 #endif /* ! CONFIG_PM_SLEEP */ 1372 static int __maybe_unused cdns_runtime_suspend(struct device *dev) 1373 { 1374 struct uart_port *port = dev_get_drvdata(dev); 1375 struct cdns_uart *cdns_uart = port->private_data; 1376 1377 clk_disable(cdns_uart->uartclk); 1378 clk_disable(cdns_uart->pclk); 1379 return 0; 1380 }; 1381 1382 static int __maybe_unused cdns_runtime_resume(struct device *dev) 1383 { 1384 struct uart_port *port = dev_get_drvdata(dev); 1385 struct cdns_uart *cdns_uart = port->private_data; 1386 1387 clk_enable(cdns_uart->pclk); 1388 clk_enable(cdns_uart->uartclk); 1389 return 0; 1390 }; 1391 1392 static const struct dev_pm_ops cdns_uart_dev_pm_ops = { 1393 SET_SYSTEM_SLEEP_PM_OPS(cdns_uart_suspend, cdns_uart_resume) 1394 SET_RUNTIME_PM_OPS(cdns_runtime_suspend, 1395 cdns_runtime_resume, NULL) 1396 }; 1397 1398 static const struct cdns_platform_data zynqmp_uart_def = { 1399 .quirks = CDNS_UART_RXBS_SUPPORT, }; 1400 1401 /* Match table for of_platform binding */ 1402 static const struct of_device_id cdns_uart_of_match[] = { 1403 { .compatible = "xlnx,xuartps", }, 1404 { .compatible = "cdns,uart-r1p8", }, 1405 { .compatible = "cdns,uart-r1p12", .data = &zynqmp_uart_def }, 1406 { .compatible = "xlnx,zynqmp-uart", .data = &zynqmp_uart_def }, 1407 {} 1408 }; 1409 MODULE_DEVICE_TABLE(of, cdns_uart_of_match); 1410 1411 /* Temporary variable for storing number of instances */ 1412 static int instances; 1413 1414 /** 1415 * cdns_uart_probe - Platform driver probe 1416 * @pdev: Pointer to the platform device structure 1417 * 1418 * Return: 0 on success, negative errno otherwise 1419 */ 1420 static int cdns_uart_probe(struct platform_device *pdev) 1421 { 1422 int rc, id, irq; 1423 struct uart_port *port; 1424 struct resource *res; 1425 struct cdns_uart *cdns_uart_data; 1426 const struct of_device_id *match; 1427 1428 cdns_uart_data = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_data), 1429 GFP_KERNEL); 1430 if (!cdns_uart_data) 1431 return -ENOMEM; 1432 port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL); 1433 if (!port) 1434 return -ENOMEM; 1435 1436 /* Look for a serialN alias */ 1437 id = of_alias_get_id(pdev->dev.of_node, "serial"); 1438 if (id < 0) 1439 id = 0; 1440 1441 if (id >= CDNS_UART_NR_PORTS) { 1442 dev_err(&pdev->dev, "Cannot get uart_port structure\n"); 1443 return -ENODEV; 1444 } 1445 1446 if (!cdns_uart_uart_driver.state) { 1447 cdns_uart_uart_driver.owner = THIS_MODULE; 1448 cdns_uart_uart_driver.driver_name = CDNS_UART_NAME; 1449 cdns_uart_uart_driver.dev_name = CDNS_UART_TTY_NAME; 1450 cdns_uart_uart_driver.major = CDNS_UART_MAJOR; 1451 cdns_uart_uart_driver.minor = CDNS_UART_MINOR; 1452 cdns_uart_uart_driver.nr = CDNS_UART_NR_PORTS; 1453 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE 1454 cdns_uart_uart_driver.cons = &cdns_uart_console; 1455 #endif 1456 1457 rc = uart_register_driver(&cdns_uart_uart_driver); 1458 if (rc < 0) { 1459 dev_err(&pdev->dev, "Failed to register driver\n"); 1460 return rc; 1461 } 1462 } 1463 1464 cdns_uart_data->cdns_uart_driver = &cdns_uart_uart_driver; 1465 1466 match = of_match_node(cdns_uart_of_match, pdev->dev.of_node); 1467 if (match && match->data) { 1468 const struct cdns_platform_data *data = match->data; 1469 1470 cdns_uart_data->quirks = data->quirks; 1471 } 1472 1473 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "pclk"); 1474 if (PTR_ERR(cdns_uart_data->pclk) == -EPROBE_DEFER) { 1475 rc = PTR_ERR(cdns_uart_data->pclk); 1476 goto err_out_unregister_driver; 1477 } 1478 1479 if (IS_ERR(cdns_uart_data->pclk)) { 1480 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "aper_clk"); 1481 if (IS_ERR(cdns_uart_data->pclk)) { 1482 rc = PTR_ERR(cdns_uart_data->pclk); 1483 goto err_out_unregister_driver; 1484 } 1485 dev_err(&pdev->dev, "clock name 'aper_clk' is deprecated.\n"); 1486 } 1487 1488 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "uart_clk"); 1489 if (PTR_ERR(cdns_uart_data->uartclk) == -EPROBE_DEFER) { 1490 rc = PTR_ERR(cdns_uart_data->uartclk); 1491 goto err_out_unregister_driver; 1492 } 1493 1494 if (IS_ERR(cdns_uart_data->uartclk)) { 1495 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "ref_clk"); 1496 if (IS_ERR(cdns_uart_data->uartclk)) { 1497 rc = PTR_ERR(cdns_uart_data->uartclk); 1498 goto err_out_unregister_driver; 1499 } 1500 dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n"); 1501 } 1502 1503 rc = clk_prepare_enable(cdns_uart_data->pclk); 1504 if (rc) { 1505 dev_err(&pdev->dev, "Unable to enable pclk clock.\n"); 1506 goto err_out_unregister_driver; 1507 } 1508 rc = clk_prepare_enable(cdns_uart_data->uartclk); 1509 if (rc) { 1510 dev_err(&pdev->dev, "Unable to enable device clock.\n"); 1511 goto err_out_clk_dis_pclk; 1512 } 1513 1514 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1515 if (!res) { 1516 rc = -ENODEV; 1517 goto err_out_clk_disable; 1518 } 1519 1520 irq = platform_get_irq(pdev, 0); 1521 if (irq <= 0) { 1522 rc = -ENXIO; 1523 goto err_out_clk_disable; 1524 } 1525 1526 #ifdef CONFIG_COMMON_CLK 1527 cdns_uart_data->clk_rate_change_nb.notifier_call = 1528 cdns_uart_clk_notifier_cb; 1529 if (clk_notifier_register(cdns_uart_data->uartclk, 1530 &cdns_uart_data->clk_rate_change_nb)) 1531 dev_warn(&pdev->dev, "Unable to register clock notifier.\n"); 1532 #endif 1533 1534 /* At this point, we've got an empty uart_port struct, initialize it */ 1535 spin_lock_init(&port->lock); 1536 port->type = PORT_UNKNOWN; 1537 port->iotype = UPIO_MEM32; 1538 port->flags = UPF_BOOT_AUTOCONF; 1539 port->ops = &cdns_uart_ops; 1540 port->fifosize = CDNS_UART_FIFO_SIZE; 1541 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE); 1542 port->line = id; 1543 1544 /* 1545 * Register the port. 1546 * This function also registers this device with the tty layer 1547 * and triggers invocation of the config_port() entry point. 1548 */ 1549 port->mapbase = res->start; 1550 port->irq = irq; 1551 port->dev = &pdev->dev; 1552 port->uartclk = clk_get_rate(cdns_uart_data->uartclk); 1553 port->private_data = cdns_uart_data; 1554 cdns_uart_data->port = port; 1555 platform_set_drvdata(pdev, port); 1556 1557 pm_runtime_use_autosuspend(&pdev->dev); 1558 pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT); 1559 pm_runtime_set_active(&pdev->dev); 1560 pm_runtime_enable(&pdev->dev); 1561 device_init_wakeup(port->dev, true); 1562 1563 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE 1564 /* 1565 * If console hasn't been found yet try to assign this port 1566 * because it is required to be assigned for console setup function. 1567 * If register_console() don't assign value, then console_port pointer 1568 * is cleanup. 1569 */ 1570 if (!console_port) { 1571 cdns_uart_console.index = id; 1572 console_port = port; 1573 } 1574 #endif 1575 1576 rc = uart_add_one_port(&cdns_uart_uart_driver, port); 1577 if (rc) { 1578 dev_err(&pdev->dev, 1579 "uart_add_one_port() failed; err=%i\n", rc); 1580 goto err_out_pm_disable; 1581 } 1582 1583 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE 1584 /* This is not port which is used for console that's why clean it up */ 1585 if (console_port == port && 1586 !(cdns_uart_uart_driver.cons->flags & CON_ENABLED)) { 1587 console_port = NULL; 1588 cdns_uart_console.index = -1; 1589 } 1590 #endif 1591 1592 cdns_uart_data->cts_override = of_property_read_bool(pdev->dev.of_node, 1593 "cts-override"); 1594 1595 instances++; 1596 1597 return 0; 1598 1599 err_out_pm_disable: 1600 pm_runtime_disable(&pdev->dev); 1601 pm_runtime_set_suspended(&pdev->dev); 1602 pm_runtime_dont_use_autosuspend(&pdev->dev); 1603 #ifdef CONFIG_COMMON_CLK 1604 clk_notifier_unregister(cdns_uart_data->uartclk, 1605 &cdns_uart_data->clk_rate_change_nb); 1606 #endif 1607 err_out_clk_disable: 1608 clk_disable_unprepare(cdns_uart_data->uartclk); 1609 err_out_clk_dis_pclk: 1610 clk_disable_unprepare(cdns_uart_data->pclk); 1611 err_out_unregister_driver: 1612 if (!instances) 1613 uart_unregister_driver(cdns_uart_data->cdns_uart_driver); 1614 return rc; 1615 } 1616 1617 /** 1618 * cdns_uart_remove - called when the platform driver is unregistered 1619 * @pdev: Pointer to the platform device structure 1620 * 1621 * Return: 0 on success, negative errno otherwise 1622 */ 1623 static int cdns_uart_remove(struct platform_device *pdev) 1624 { 1625 struct uart_port *port = platform_get_drvdata(pdev); 1626 struct cdns_uart *cdns_uart_data = port->private_data; 1627 int rc; 1628 1629 /* Remove the cdns_uart port from the serial core */ 1630 #ifdef CONFIG_COMMON_CLK 1631 clk_notifier_unregister(cdns_uart_data->uartclk, 1632 &cdns_uart_data->clk_rate_change_nb); 1633 #endif 1634 rc = uart_remove_one_port(cdns_uart_data->cdns_uart_driver, port); 1635 port->mapbase = 0; 1636 clk_disable_unprepare(cdns_uart_data->uartclk); 1637 clk_disable_unprepare(cdns_uart_data->pclk); 1638 pm_runtime_disable(&pdev->dev); 1639 pm_runtime_set_suspended(&pdev->dev); 1640 pm_runtime_dont_use_autosuspend(&pdev->dev); 1641 device_init_wakeup(&pdev->dev, false); 1642 1643 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE 1644 if (console_port == port) 1645 console_port = NULL; 1646 #endif 1647 1648 if (!--instances) 1649 uart_unregister_driver(cdns_uart_data->cdns_uart_driver); 1650 return rc; 1651 } 1652 1653 static struct platform_driver cdns_uart_platform_driver = { 1654 .probe = cdns_uart_probe, 1655 .remove = cdns_uart_remove, 1656 .driver = { 1657 .name = CDNS_UART_NAME, 1658 .of_match_table = cdns_uart_of_match, 1659 .pm = &cdns_uart_dev_pm_ops, 1660 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_XILINX_PS_UART), 1661 }, 1662 }; 1663 1664 static int __init cdns_uart_init(void) 1665 { 1666 /* Register the platform driver */ 1667 return platform_driver_register(&cdns_uart_platform_driver); 1668 } 1669 1670 static void __exit cdns_uart_exit(void) 1671 { 1672 /* Unregister the platform driver */ 1673 platform_driver_unregister(&cdns_uart_platform_driver); 1674 } 1675 1676 arch_initcall(cdns_uart_init); 1677 module_exit(cdns_uart_exit); 1678 1679 MODULE_DESCRIPTION("Driver for Cadence UART"); 1680 MODULE_AUTHOR("Xilinx Inc."); 1681 MODULE_LICENSE("GPL"); 1682