1 /* 2 * Xilinx PS UART driver 3 * 4 * 2011 - 2013 (C) Xilinx Inc. 5 * 6 * This program is free software; you can redistribute it 7 * and/or modify it under the terms of the GNU General Public 8 * License as published by the Free Software Foundation; 9 * either version 2 of the License, or (at your option) any 10 * later version. 11 * 12 */ 13 14 #if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 15 #define SUPPORT_SYSRQ 16 #endif 17 18 #include <linux/platform_device.h> 19 #include <linux/serial.h> 20 #include <linux/console.h> 21 #include <linux/serial_core.h> 22 #include <linux/slab.h> 23 #include <linux/tty.h> 24 #include <linux/tty_flip.h> 25 #include <linux/clk.h> 26 #include <linux/irq.h> 27 #include <linux/io.h> 28 #include <linux/of.h> 29 #include <linux/module.h> 30 31 #define XUARTPS_TTY_NAME "ttyPS" 32 #define XUARTPS_NAME "xuartps" 33 #define XUARTPS_MAJOR 0 /* use dynamic node allocation */ 34 #define XUARTPS_MINOR 0 /* works best with devtmpfs */ 35 #define XUARTPS_NR_PORTS 2 36 #define XUARTPS_FIFO_SIZE 64 /* FIFO size */ 37 #define XUARTPS_REGISTER_SPACE 0xFFF 38 39 #define xuartps_readl(offset) ioread32(port->membase + offset) 40 #define xuartps_writel(val, offset) iowrite32(val, port->membase + offset) 41 42 /* Rx Trigger level */ 43 static int rx_trigger_level = 56; 44 module_param(rx_trigger_level, uint, S_IRUGO); 45 MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes"); 46 47 /* Rx Timeout */ 48 static int rx_timeout = 10; 49 module_param(rx_timeout, uint, S_IRUGO); 50 MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255"); 51 52 /********************************Register Map********************************/ 53 /** UART 54 * 55 * Register offsets for the UART. 56 * 57 */ 58 #define XUARTPS_CR_OFFSET 0x00 /* Control Register [8:0] */ 59 #define XUARTPS_MR_OFFSET 0x04 /* Mode Register [10:0] */ 60 #define XUARTPS_IER_OFFSET 0x08 /* Interrupt Enable [10:0] */ 61 #define XUARTPS_IDR_OFFSET 0x0C /* Interrupt Disable [10:0] */ 62 #define XUARTPS_IMR_OFFSET 0x10 /* Interrupt Mask [10:0] */ 63 #define XUARTPS_ISR_OFFSET 0x14 /* Interrupt Status [10:0]*/ 64 #define XUARTPS_BAUDGEN_OFFSET 0x18 /* Baud Rate Generator [15:0] */ 65 #define XUARTPS_RXTOUT_OFFSET 0x1C /* RX Timeout [7:0] */ 66 #define XUARTPS_RXWM_OFFSET 0x20 /* RX FIFO Trigger Level [5:0] */ 67 #define XUARTPS_MODEMCR_OFFSET 0x24 /* Modem Control [5:0] */ 68 #define XUARTPS_MODEMSR_OFFSET 0x28 /* Modem Status [8:0] */ 69 #define XUARTPS_SR_OFFSET 0x2C /* Channel Status [11:0] */ 70 #define XUARTPS_FIFO_OFFSET 0x30 /* FIFO [15:0] or [7:0] */ 71 #define XUARTPS_BAUDDIV_OFFSET 0x34 /* Baud Rate Divider [7:0] */ 72 #define XUARTPS_FLOWDEL_OFFSET 0x38 /* Flow Delay [15:0] */ 73 #define XUARTPS_IRRX_PWIDTH_OFFSET 0x3C /* IR Minimum Received Pulse 74 Width [15:0] */ 75 #define XUARTPS_IRTX_PWIDTH_OFFSET 0x40 /* IR Transmitted pulse 76 Width [7:0] */ 77 #define XUARTPS_TXWM_OFFSET 0x44 /* TX FIFO Trigger Level [5:0] */ 78 79 /** Control Register 80 * 81 * The Control register (CR) controls the major functions of the device. 82 * 83 * Control Register Bit Definitions 84 */ 85 #define XUARTPS_CR_STOPBRK 0x00000100 /* Stop TX break */ 86 #define XUARTPS_CR_STARTBRK 0x00000080 /* Set TX break */ 87 #define XUARTPS_CR_TX_DIS 0x00000020 /* TX disabled. */ 88 #define XUARTPS_CR_TX_EN 0x00000010 /* TX enabled */ 89 #define XUARTPS_CR_RX_DIS 0x00000008 /* RX disabled. */ 90 #define XUARTPS_CR_RX_EN 0x00000004 /* RX enabled */ 91 #define XUARTPS_CR_TXRST 0x00000002 /* TX logic reset */ 92 #define XUARTPS_CR_RXRST 0x00000001 /* RX logic reset */ 93 #define XUARTPS_CR_RST_TO 0x00000040 /* Restart Timeout Counter */ 94 95 /** Mode Register 96 * 97 * The mode register (MR) defines the mode of transfer as well as the data 98 * format. If this register is modified during transmission or reception, 99 * data validity cannot be guaranteed. 100 * 101 * Mode Register Bit Definitions 102 * 103 */ 104 #define XUARTPS_MR_CLKSEL 0x00000001 /* Pre-scalar selection */ 105 #define XUARTPS_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */ 106 #define XUARTPS_MR_CHMODE_NORM 0x00000000 /* Normal mode */ 107 108 #define XUARTPS_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */ 109 #define XUARTPS_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */ 110 111 #define XUARTPS_MR_PARITY_NONE 0x00000020 /* No parity mode */ 112 #define XUARTPS_MR_PARITY_MARK 0x00000018 /* Mark parity mode */ 113 #define XUARTPS_MR_PARITY_SPACE 0x00000010 /* Space parity mode */ 114 #define XUARTPS_MR_PARITY_ODD 0x00000008 /* Odd parity mode */ 115 #define XUARTPS_MR_PARITY_EVEN 0x00000000 /* Even parity mode */ 116 117 #define XUARTPS_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */ 118 #define XUARTPS_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */ 119 #define XUARTPS_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */ 120 121 /** Interrupt Registers 122 * 123 * Interrupt control logic uses the interrupt enable register (IER) and the 124 * interrupt disable register (IDR) to set the value of the bits in the 125 * interrupt mask register (IMR). The IMR determines whether to pass an 126 * interrupt to the interrupt status register (ISR). 127 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an 128 * interrupt. IMR and ISR are read only, and IER and IDR are write only. 129 * Reading either IER or IDR returns 0x00. 130 * 131 * All four registers have the same bit definitions. 132 */ 133 #define XUARTPS_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */ 134 #define XUARTPS_IXR_PARITY 0x00000080 /* Parity error interrupt */ 135 #define XUARTPS_IXR_FRAMING 0x00000040 /* Framing error interrupt */ 136 #define XUARTPS_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */ 137 #define XUARTPS_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */ 138 #define XUARTPS_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */ 139 #define XUARTPS_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */ 140 #define XUARTPS_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */ 141 #define XUARTPS_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */ 142 #define XUARTPS_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */ 143 #define XUARTPS_IXR_MASK 0x00001FFF /* Valid bit mask */ 144 145 /* Goes in read_status_mask for break detection as the HW doesn't do it*/ 146 #define XUARTPS_IXR_BRK 0x80000000 147 148 /** Channel Status Register 149 * 150 * The channel status register (CSR) is provided to enable the control logic 151 * to monitor the status of bits in the channel interrupt status register, 152 * even if these are masked out by the interrupt mask register. 153 */ 154 #define XUARTPS_SR_RXEMPTY 0x00000002 /* RX FIFO empty */ 155 #define XUARTPS_SR_TXEMPTY 0x00000008 /* TX FIFO empty */ 156 #define XUARTPS_SR_TXFULL 0x00000010 /* TX FIFO full */ 157 #define XUARTPS_SR_RXTRIG 0x00000001 /* Rx Trigger */ 158 159 /* baud dividers min/max values */ 160 #define XUARTPS_BDIV_MIN 4 161 #define XUARTPS_BDIV_MAX 255 162 #define XUARTPS_CD_MAX 65535 163 164 /** 165 * struct xuartps - device data 166 * @port Pointer to the UART port 167 * @refclk Reference clock 168 * @aperclk APB clock 169 * @baud Current baud rate 170 * @clk_rate_change_nb Notifier block for clock changes 171 */ 172 struct xuartps { 173 struct uart_port *port; 174 struct clk *refclk; 175 struct clk *aperclk; 176 unsigned int baud; 177 struct notifier_block clk_rate_change_nb; 178 }; 179 #define to_xuartps(_nb) container_of(_nb, struct xuartps, clk_rate_change_nb); 180 181 /** 182 * xuartps_isr - Interrupt handler 183 * @irq: Irq number 184 * @dev_id: Id of the port 185 * 186 * Returns IRQHANDLED 187 **/ 188 static irqreturn_t xuartps_isr(int irq, void *dev_id) 189 { 190 struct uart_port *port = (struct uart_port *)dev_id; 191 unsigned long flags; 192 unsigned int isrstatus, numbytes; 193 unsigned int data; 194 char status = TTY_NORMAL; 195 196 spin_lock_irqsave(&port->lock, flags); 197 198 /* Read the interrupt status register to determine which 199 * interrupt(s) is/are active. 200 */ 201 isrstatus = xuartps_readl(XUARTPS_ISR_OFFSET); 202 203 /* 204 * There is no hardware break detection, so we interpret framing 205 * error with all-zeros data as a break sequence. Most of the time, 206 * there's another non-zero byte at the end of the sequence. 207 */ 208 209 if (isrstatus & XUARTPS_IXR_FRAMING) { 210 while (!(xuartps_readl(XUARTPS_SR_OFFSET) & 211 XUARTPS_SR_RXEMPTY)) { 212 if (!xuartps_readl(XUARTPS_FIFO_OFFSET)) { 213 port->read_status_mask |= XUARTPS_IXR_BRK; 214 isrstatus &= ~XUARTPS_IXR_FRAMING; 215 } 216 } 217 xuartps_writel(XUARTPS_IXR_FRAMING, XUARTPS_ISR_OFFSET); 218 } 219 220 /* drop byte with parity error if IGNPAR specified */ 221 if (isrstatus & port->ignore_status_mask & XUARTPS_IXR_PARITY) 222 isrstatus &= ~(XUARTPS_IXR_RXTRIG | XUARTPS_IXR_TOUT); 223 224 isrstatus &= port->read_status_mask; 225 isrstatus &= ~port->ignore_status_mask; 226 227 if ((isrstatus & XUARTPS_IXR_TOUT) || 228 (isrstatus & XUARTPS_IXR_RXTRIG)) { 229 /* Receive Timeout Interrupt */ 230 while ((xuartps_readl(XUARTPS_SR_OFFSET) & 231 XUARTPS_SR_RXEMPTY) != XUARTPS_SR_RXEMPTY) { 232 data = xuartps_readl(XUARTPS_FIFO_OFFSET); 233 234 /* Non-NULL byte after BREAK is garbage (99%) */ 235 if (data && (port->read_status_mask & 236 XUARTPS_IXR_BRK)) { 237 port->read_status_mask &= ~XUARTPS_IXR_BRK; 238 port->icount.brk++; 239 if (uart_handle_break(port)) 240 continue; 241 } 242 243 /* 244 * uart_handle_sysrq_char() doesn't work if 245 * spinlocked, for some reason 246 */ 247 if (port->sysrq) { 248 spin_unlock(&port->lock); 249 if (uart_handle_sysrq_char(port, 250 (unsigned char)data)) { 251 spin_lock(&port->lock); 252 continue; 253 } 254 spin_lock(&port->lock); 255 } 256 257 port->icount.rx++; 258 259 if (isrstatus & XUARTPS_IXR_PARITY) { 260 port->icount.parity++; 261 status = TTY_PARITY; 262 } else if (isrstatus & XUARTPS_IXR_FRAMING) { 263 port->icount.frame++; 264 status = TTY_FRAME; 265 } else if (isrstatus & XUARTPS_IXR_OVERRUN) 266 port->icount.overrun++; 267 268 uart_insert_char(port, isrstatus, XUARTPS_IXR_OVERRUN, 269 data, status); 270 } 271 spin_unlock(&port->lock); 272 tty_flip_buffer_push(&port->state->port); 273 spin_lock(&port->lock); 274 } 275 276 /* Dispatch an appropriate handler */ 277 if ((isrstatus & XUARTPS_IXR_TXEMPTY) == XUARTPS_IXR_TXEMPTY) { 278 if (uart_circ_empty(&port->state->xmit)) { 279 xuartps_writel(XUARTPS_IXR_TXEMPTY, 280 XUARTPS_IDR_OFFSET); 281 } else { 282 numbytes = port->fifosize; 283 /* Break if no more data available in the UART buffer */ 284 while (numbytes--) { 285 if (uart_circ_empty(&port->state->xmit)) 286 break; 287 /* Get the data from the UART circular buffer 288 * and write it to the xuartps's TX_FIFO 289 * register. 290 */ 291 xuartps_writel( 292 port->state->xmit.buf[port->state->xmit. 293 tail], XUARTPS_FIFO_OFFSET); 294 295 port->icount.tx++; 296 297 /* Adjust the tail of the UART buffer and wrap 298 * the buffer if it reaches limit. 299 */ 300 port->state->xmit.tail = 301 (port->state->xmit.tail + 1) & \ 302 (UART_XMIT_SIZE - 1); 303 } 304 305 if (uart_circ_chars_pending( 306 &port->state->xmit) < WAKEUP_CHARS) 307 uart_write_wakeup(port); 308 } 309 } 310 311 xuartps_writel(isrstatus, XUARTPS_ISR_OFFSET); 312 313 /* be sure to release the lock and tty before leaving */ 314 spin_unlock_irqrestore(&port->lock, flags); 315 316 return IRQ_HANDLED; 317 } 318 319 /** 320 * xuartps_calc_baud_divs - Calculate baud rate divisors 321 * @clk: UART module input clock 322 * @baud: Desired baud rate 323 * @rbdiv: BDIV value (return value) 324 * @rcd: CD value (return value) 325 * @div8: Value for clk_sel bit in mod (return value) 326 * Returns baud rate, requested baud when possible, or actual baud when there 327 * was too much error, zero if no valid divisors are found. 328 * 329 * Formula to obtain baud rate is 330 * baud_tx/rx rate = clk/CD * (BDIV + 1) 331 * input_clk = (Uart User Defined Clock or Apb Clock) 332 * depends on UCLKEN in MR Reg 333 * clk = input_clk or input_clk/8; 334 * depends on CLKS in MR reg 335 * CD and BDIV depends on values in 336 * baud rate generate register 337 * baud rate clock divisor register 338 */ 339 static unsigned int xuartps_calc_baud_divs(unsigned int clk, unsigned int baud, 340 u32 *rbdiv, u32 *rcd, int *div8) 341 { 342 u32 cd, bdiv; 343 unsigned int calc_baud; 344 unsigned int bestbaud = 0; 345 unsigned int bauderror; 346 unsigned int besterror = ~0; 347 348 if (baud < clk / ((XUARTPS_BDIV_MAX + 1) * XUARTPS_CD_MAX)) { 349 *div8 = 1; 350 clk /= 8; 351 } else { 352 *div8 = 0; 353 } 354 355 for (bdiv = XUARTPS_BDIV_MIN; bdiv <= XUARTPS_BDIV_MAX; bdiv++) { 356 cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1)); 357 if (cd < 1 || cd > XUARTPS_CD_MAX) 358 continue; 359 360 calc_baud = clk / (cd * (bdiv + 1)); 361 362 if (baud > calc_baud) 363 bauderror = baud - calc_baud; 364 else 365 bauderror = calc_baud - baud; 366 367 if (besterror > bauderror) { 368 *rbdiv = bdiv; 369 *rcd = cd; 370 bestbaud = calc_baud; 371 besterror = bauderror; 372 } 373 } 374 /* use the values when percent error is acceptable */ 375 if (((besterror * 100) / baud) < 3) 376 bestbaud = baud; 377 378 return bestbaud; 379 } 380 381 /** 382 * xuartps_set_baud_rate - Calculate and set the baud rate 383 * @port: Handle to the uart port structure 384 * @baud: Baud rate to set 385 * Returns baud rate, requested baud when possible, or actual baud when there 386 * was too much error, zero if no valid divisors are found. 387 */ 388 static unsigned int xuartps_set_baud_rate(struct uart_port *port, 389 unsigned int baud) 390 { 391 unsigned int calc_baud; 392 u32 cd = 0, bdiv = 0; 393 u32 mreg; 394 int div8; 395 struct xuartps *xuartps = port->private_data; 396 397 calc_baud = xuartps_calc_baud_divs(port->uartclk, baud, &bdiv, &cd, 398 &div8); 399 400 /* Write new divisors to hardware */ 401 mreg = xuartps_readl(XUARTPS_MR_OFFSET); 402 if (div8) 403 mreg |= XUARTPS_MR_CLKSEL; 404 else 405 mreg &= ~XUARTPS_MR_CLKSEL; 406 xuartps_writel(mreg, XUARTPS_MR_OFFSET); 407 xuartps_writel(cd, XUARTPS_BAUDGEN_OFFSET); 408 xuartps_writel(bdiv, XUARTPS_BAUDDIV_OFFSET); 409 xuartps->baud = baud; 410 411 return calc_baud; 412 } 413 414 #ifdef CONFIG_COMMON_CLK 415 /** 416 * xuartps_clk_notitifer_cb - Clock notifier callback 417 * @nb: Notifier block 418 * @event: Notify event 419 * @data: Notifier data 420 * Returns NOTIFY_OK on success, NOTIFY_BAD on error. 421 */ 422 static int xuartps_clk_notifier_cb(struct notifier_block *nb, 423 unsigned long event, void *data) 424 { 425 u32 ctrl_reg; 426 struct uart_port *port; 427 int locked = 0; 428 struct clk_notifier_data *ndata = data; 429 unsigned long flags = 0; 430 struct xuartps *xuartps = to_xuartps(nb); 431 432 port = xuartps->port; 433 if (port->suspended) 434 return NOTIFY_OK; 435 436 switch (event) { 437 case PRE_RATE_CHANGE: 438 { 439 u32 bdiv; 440 u32 cd; 441 int div8; 442 443 /* 444 * Find out if current baud-rate can be achieved with new clock 445 * frequency. 446 */ 447 if (!xuartps_calc_baud_divs(ndata->new_rate, xuartps->baud, 448 &bdiv, &cd, &div8)) 449 return NOTIFY_BAD; 450 451 spin_lock_irqsave(&xuartps->port->lock, flags); 452 453 /* Disable the TX and RX to set baud rate */ 454 xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) | 455 (XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS), 456 XUARTPS_CR_OFFSET); 457 458 spin_unlock_irqrestore(&xuartps->port->lock, flags); 459 460 return NOTIFY_OK; 461 } 462 case POST_RATE_CHANGE: 463 /* 464 * Set clk dividers to generate correct baud with new clock 465 * frequency. 466 */ 467 468 spin_lock_irqsave(&xuartps->port->lock, flags); 469 470 locked = 1; 471 port->uartclk = ndata->new_rate; 472 473 xuartps->baud = xuartps_set_baud_rate(xuartps->port, 474 xuartps->baud); 475 /* fall through */ 476 case ABORT_RATE_CHANGE: 477 if (!locked) 478 spin_lock_irqsave(&xuartps->port->lock, flags); 479 480 /* Set TX/RX Reset */ 481 xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) | 482 (XUARTPS_CR_TXRST | XUARTPS_CR_RXRST), 483 XUARTPS_CR_OFFSET); 484 485 while (xuartps_readl(XUARTPS_CR_OFFSET) & 486 (XUARTPS_CR_TXRST | XUARTPS_CR_RXRST)) 487 cpu_relax(); 488 489 /* 490 * Clear the RX disable and TX disable bits and then set the TX 491 * enable bit and RX enable bit to enable the transmitter and 492 * receiver. 493 */ 494 xuartps_writel(rx_timeout, XUARTPS_RXTOUT_OFFSET); 495 ctrl_reg = xuartps_readl(XUARTPS_CR_OFFSET); 496 xuartps_writel( 497 (ctrl_reg & ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS)) | 498 (XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN), 499 XUARTPS_CR_OFFSET); 500 501 spin_unlock_irqrestore(&xuartps->port->lock, flags); 502 503 return NOTIFY_OK; 504 default: 505 return NOTIFY_DONE; 506 } 507 } 508 #endif 509 510 /*----------------------Uart Operations---------------------------*/ 511 512 /** 513 * xuartps_start_tx - Start transmitting bytes 514 * @port: Handle to the uart port structure 515 * 516 **/ 517 static void xuartps_start_tx(struct uart_port *port) 518 { 519 unsigned int status, numbytes = port->fifosize; 520 521 if (uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port)) 522 return; 523 524 status = xuartps_readl(XUARTPS_CR_OFFSET); 525 /* Set the TX enable bit and clear the TX disable bit to enable the 526 * transmitter. 527 */ 528 xuartps_writel((status & ~XUARTPS_CR_TX_DIS) | XUARTPS_CR_TX_EN, 529 XUARTPS_CR_OFFSET); 530 531 while (numbytes-- && ((xuartps_readl(XUARTPS_SR_OFFSET) 532 & XUARTPS_SR_TXFULL)) != XUARTPS_SR_TXFULL) { 533 534 /* Break if no more data available in the UART buffer */ 535 if (uart_circ_empty(&port->state->xmit)) 536 break; 537 538 /* Get the data from the UART circular buffer and 539 * write it to the xuartps's TX_FIFO register. 540 */ 541 xuartps_writel( 542 port->state->xmit.buf[port->state->xmit.tail], 543 XUARTPS_FIFO_OFFSET); 544 port->icount.tx++; 545 546 /* Adjust the tail of the UART buffer and wrap 547 * the buffer if it reaches limit. 548 */ 549 port->state->xmit.tail = (port->state->xmit.tail + 1) & 550 (UART_XMIT_SIZE - 1); 551 } 552 xuartps_writel(XUARTPS_IXR_TXEMPTY, XUARTPS_ISR_OFFSET); 553 /* Enable the TX Empty interrupt */ 554 xuartps_writel(XUARTPS_IXR_TXEMPTY, XUARTPS_IER_OFFSET); 555 556 if (uart_circ_chars_pending(&port->state->xmit) < WAKEUP_CHARS) 557 uart_write_wakeup(port); 558 } 559 560 /** 561 * xuartps_stop_tx - Stop TX 562 * @port: Handle to the uart port structure 563 * 564 **/ 565 static void xuartps_stop_tx(struct uart_port *port) 566 { 567 unsigned int regval; 568 569 regval = xuartps_readl(XUARTPS_CR_OFFSET); 570 regval |= XUARTPS_CR_TX_DIS; 571 /* Disable the transmitter */ 572 xuartps_writel(regval, XUARTPS_CR_OFFSET); 573 } 574 575 /** 576 * xuartps_stop_rx - Stop RX 577 * @port: Handle to the uart port structure 578 * 579 **/ 580 static void xuartps_stop_rx(struct uart_port *port) 581 { 582 unsigned int regval; 583 584 regval = xuartps_readl(XUARTPS_CR_OFFSET); 585 regval |= XUARTPS_CR_RX_DIS; 586 /* Disable the receiver */ 587 xuartps_writel(regval, XUARTPS_CR_OFFSET); 588 } 589 590 /** 591 * xuartps_tx_empty - Check whether TX is empty 592 * @port: Handle to the uart port structure 593 * 594 * Returns TIOCSER_TEMT on success, 0 otherwise 595 **/ 596 static unsigned int xuartps_tx_empty(struct uart_port *port) 597 { 598 unsigned int status; 599 600 status = xuartps_readl(XUARTPS_ISR_OFFSET) & XUARTPS_IXR_TXEMPTY; 601 return status ? TIOCSER_TEMT : 0; 602 } 603 604 /** 605 * xuartps_break_ctl - Based on the input ctl we have to start or stop 606 * transmitting char breaks 607 * @port: Handle to the uart port structure 608 * @ctl: Value based on which start or stop decision is taken 609 * 610 **/ 611 static void xuartps_break_ctl(struct uart_port *port, int ctl) 612 { 613 unsigned int status; 614 unsigned long flags; 615 616 spin_lock_irqsave(&port->lock, flags); 617 618 status = xuartps_readl(XUARTPS_CR_OFFSET); 619 620 if (ctl == -1) 621 xuartps_writel(XUARTPS_CR_STARTBRK | status, 622 XUARTPS_CR_OFFSET); 623 else { 624 if ((status & XUARTPS_CR_STOPBRK) == 0) 625 xuartps_writel(XUARTPS_CR_STOPBRK | status, 626 XUARTPS_CR_OFFSET); 627 } 628 spin_unlock_irqrestore(&port->lock, flags); 629 } 630 631 /** 632 * xuartps_set_termios - termios operations, handling data length, parity, 633 * stop bits, flow control, baud rate 634 * @port: Handle to the uart port structure 635 * @termios: Handle to the input termios structure 636 * @old: Values of the previously saved termios structure 637 * 638 **/ 639 static void xuartps_set_termios(struct uart_port *port, 640 struct ktermios *termios, struct ktermios *old) 641 { 642 unsigned int cval = 0; 643 unsigned int baud, minbaud, maxbaud; 644 unsigned long flags; 645 unsigned int ctrl_reg, mode_reg; 646 647 spin_lock_irqsave(&port->lock, flags); 648 649 /* Empty the receive FIFO 1st before making changes */ 650 while ((xuartps_readl(XUARTPS_SR_OFFSET) & 651 XUARTPS_SR_RXEMPTY) != XUARTPS_SR_RXEMPTY) { 652 xuartps_readl(XUARTPS_FIFO_OFFSET); 653 } 654 655 /* Disable the TX and RX to set baud rate */ 656 xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) | 657 (XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS), 658 XUARTPS_CR_OFFSET); 659 660 /* 661 * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk 662 * min and max baud should be calculated here based on port->uartclk. 663 * this way we get a valid baud and can safely call set_baud() 664 */ 665 minbaud = port->uartclk / ((XUARTPS_BDIV_MAX + 1) * XUARTPS_CD_MAX * 8); 666 maxbaud = port->uartclk / (XUARTPS_BDIV_MIN + 1); 667 baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud); 668 baud = xuartps_set_baud_rate(port, baud); 669 if (tty_termios_baud_rate(termios)) 670 tty_termios_encode_baud_rate(termios, baud, baud); 671 672 /* 673 * Update the per-port timeout. 674 */ 675 uart_update_timeout(port, termios->c_cflag, baud); 676 677 /* Set TX/RX Reset */ 678 xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) | 679 (XUARTPS_CR_TXRST | XUARTPS_CR_RXRST), 680 XUARTPS_CR_OFFSET); 681 682 ctrl_reg = xuartps_readl(XUARTPS_CR_OFFSET); 683 684 /* Clear the RX disable and TX disable bits and then set the TX enable 685 * bit and RX enable bit to enable the transmitter and receiver. 686 */ 687 xuartps_writel( 688 (ctrl_reg & ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS)) 689 | (XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN), 690 XUARTPS_CR_OFFSET); 691 692 xuartps_writel(rx_timeout, XUARTPS_RXTOUT_OFFSET); 693 694 port->read_status_mask = XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_RXTRIG | 695 XUARTPS_IXR_OVERRUN | XUARTPS_IXR_TOUT; 696 port->ignore_status_mask = 0; 697 698 if (termios->c_iflag & INPCK) 699 port->read_status_mask |= XUARTPS_IXR_PARITY | 700 XUARTPS_IXR_FRAMING; 701 702 if (termios->c_iflag & IGNPAR) 703 port->ignore_status_mask |= XUARTPS_IXR_PARITY | 704 XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN; 705 706 /* ignore all characters if CREAD is not set */ 707 if ((termios->c_cflag & CREAD) == 0) 708 port->ignore_status_mask |= XUARTPS_IXR_RXTRIG | 709 XUARTPS_IXR_TOUT | XUARTPS_IXR_PARITY | 710 XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN; 711 712 mode_reg = xuartps_readl(XUARTPS_MR_OFFSET); 713 714 /* Handling Data Size */ 715 switch (termios->c_cflag & CSIZE) { 716 case CS6: 717 cval |= XUARTPS_MR_CHARLEN_6_BIT; 718 break; 719 case CS7: 720 cval |= XUARTPS_MR_CHARLEN_7_BIT; 721 break; 722 default: 723 case CS8: 724 cval |= XUARTPS_MR_CHARLEN_8_BIT; 725 termios->c_cflag &= ~CSIZE; 726 termios->c_cflag |= CS8; 727 break; 728 } 729 730 /* Handling Parity and Stop Bits length */ 731 if (termios->c_cflag & CSTOPB) 732 cval |= XUARTPS_MR_STOPMODE_2_BIT; /* 2 STOP bits */ 733 else 734 cval |= XUARTPS_MR_STOPMODE_1_BIT; /* 1 STOP bit */ 735 736 if (termios->c_cflag & PARENB) { 737 /* Mark or Space parity */ 738 if (termios->c_cflag & CMSPAR) { 739 if (termios->c_cflag & PARODD) 740 cval |= XUARTPS_MR_PARITY_MARK; 741 else 742 cval |= XUARTPS_MR_PARITY_SPACE; 743 } else { 744 if (termios->c_cflag & PARODD) 745 cval |= XUARTPS_MR_PARITY_ODD; 746 else 747 cval |= XUARTPS_MR_PARITY_EVEN; 748 } 749 } else { 750 cval |= XUARTPS_MR_PARITY_NONE; 751 } 752 cval |= mode_reg & 1; 753 xuartps_writel(cval, XUARTPS_MR_OFFSET); 754 755 spin_unlock_irqrestore(&port->lock, flags); 756 } 757 758 /** 759 * xuartps_startup - Called when an application opens a xuartps port 760 * @port: Handle to the uart port structure 761 * 762 * Returns 0 on success, negative error otherwise 763 **/ 764 static int xuartps_startup(struct uart_port *port) 765 { 766 unsigned int retval = 0, status = 0; 767 768 retval = request_irq(port->irq, xuartps_isr, 0, XUARTPS_NAME, 769 (void *)port); 770 if (retval) 771 return retval; 772 773 /* Disable the TX and RX */ 774 xuartps_writel(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS, 775 XUARTPS_CR_OFFSET); 776 777 /* Set the Control Register with TX/RX Enable, TX/RX Reset, 778 * no break chars. 779 */ 780 xuartps_writel(XUARTPS_CR_TXRST | XUARTPS_CR_RXRST, 781 XUARTPS_CR_OFFSET); 782 783 status = xuartps_readl(XUARTPS_CR_OFFSET); 784 785 /* Clear the RX disable and TX disable bits and then set the TX enable 786 * bit and RX enable bit to enable the transmitter and receiver. 787 */ 788 xuartps_writel((status & ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS)) 789 | (XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN | 790 XUARTPS_CR_STOPBRK), XUARTPS_CR_OFFSET); 791 792 /* Set the Mode Register with normal mode,8 data bits,1 stop bit, 793 * no parity. 794 */ 795 xuartps_writel(XUARTPS_MR_CHMODE_NORM | XUARTPS_MR_STOPMODE_1_BIT 796 | XUARTPS_MR_PARITY_NONE | XUARTPS_MR_CHARLEN_8_BIT, 797 XUARTPS_MR_OFFSET); 798 799 /* 800 * Set the RX FIFO Trigger level to use most of the FIFO, but it 801 * can be tuned with a module parameter 802 */ 803 xuartps_writel(rx_trigger_level, XUARTPS_RXWM_OFFSET); 804 805 /* 806 * Receive Timeout register is enabled but it 807 * can be tuned with a module parameter 808 */ 809 xuartps_writel(rx_timeout, XUARTPS_RXTOUT_OFFSET); 810 811 /* Clear out any pending interrupts before enabling them */ 812 xuartps_writel(xuartps_readl(XUARTPS_ISR_OFFSET), XUARTPS_ISR_OFFSET); 813 814 /* Set the Interrupt Registers with desired interrupts */ 815 xuartps_writel(XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_PARITY | 816 XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN | 817 XUARTPS_IXR_RXTRIG | XUARTPS_IXR_TOUT, XUARTPS_IER_OFFSET); 818 819 return retval; 820 } 821 822 /** 823 * xuartps_shutdown - Called when an application closes a xuartps port 824 * @port: Handle to the uart port structure 825 * 826 **/ 827 static void xuartps_shutdown(struct uart_port *port) 828 { 829 int status; 830 831 /* Disable interrupts */ 832 status = xuartps_readl(XUARTPS_IMR_OFFSET); 833 xuartps_writel(status, XUARTPS_IDR_OFFSET); 834 835 /* Disable the TX and RX */ 836 xuartps_writel(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS, 837 XUARTPS_CR_OFFSET); 838 free_irq(port->irq, port); 839 } 840 841 /** 842 * xuartps_type - Set UART type to xuartps port 843 * @port: Handle to the uart port structure 844 * 845 * Returns string on success, NULL otherwise 846 **/ 847 static const char *xuartps_type(struct uart_port *port) 848 { 849 return port->type == PORT_XUARTPS ? XUARTPS_NAME : NULL; 850 } 851 852 /** 853 * xuartps_verify_port - Verify the port params 854 * @port: Handle to the uart port structure 855 * @ser: Handle to the structure whose members are compared 856 * 857 * Returns 0 if success otherwise -EINVAL 858 **/ 859 static int xuartps_verify_port(struct uart_port *port, 860 struct serial_struct *ser) 861 { 862 if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS) 863 return -EINVAL; 864 if (port->irq != ser->irq) 865 return -EINVAL; 866 if (ser->io_type != UPIO_MEM) 867 return -EINVAL; 868 if (port->iobase != ser->port) 869 return -EINVAL; 870 if (ser->hub6 != 0) 871 return -EINVAL; 872 return 0; 873 } 874 875 /** 876 * xuartps_request_port - Claim the memory region attached to xuartps port, 877 * called when the driver adds a xuartps port via 878 * uart_add_one_port() 879 * @port: Handle to the uart port structure 880 * 881 * Returns 0, -ENOMEM if request fails 882 **/ 883 static int xuartps_request_port(struct uart_port *port) 884 { 885 if (!request_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE, 886 XUARTPS_NAME)) { 887 return -ENOMEM; 888 } 889 890 port->membase = ioremap(port->mapbase, XUARTPS_REGISTER_SPACE); 891 if (!port->membase) { 892 dev_err(port->dev, "Unable to map registers\n"); 893 release_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE); 894 return -ENOMEM; 895 } 896 return 0; 897 } 898 899 /** 900 * xuartps_release_port - Release the memory region attached to a xuartps 901 * port, called when the driver removes a xuartps 902 * port via uart_remove_one_port(). 903 * @port: Handle to the uart port structure 904 * 905 **/ 906 static void xuartps_release_port(struct uart_port *port) 907 { 908 release_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE); 909 iounmap(port->membase); 910 port->membase = NULL; 911 } 912 913 /** 914 * xuartps_config_port - Configure xuartps, called when the driver adds a 915 * xuartps port 916 * @port: Handle to the uart port structure 917 * @flags: If any 918 * 919 **/ 920 static void xuartps_config_port(struct uart_port *port, int flags) 921 { 922 if (flags & UART_CONFIG_TYPE && xuartps_request_port(port) == 0) 923 port->type = PORT_XUARTPS; 924 } 925 926 /** 927 * xuartps_get_mctrl - Get the modem control state 928 * 929 * @port: Handle to the uart port structure 930 * 931 * Returns the modem control state 932 * 933 **/ 934 static unsigned int xuartps_get_mctrl(struct uart_port *port) 935 { 936 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; 937 } 938 939 static void xuartps_set_mctrl(struct uart_port *port, unsigned int mctrl) 940 { 941 /* N/A */ 942 } 943 944 static void xuartps_enable_ms(struct uart_port *port) 945 { 946 /* N/A */ 947 } 948 949 #ifdef CONFIG_CONSOLE_POLL 950 static int xuartps_poll_get_char(struct uart_port *port) 951 { 952 u32 imr; 953 int c; 954 955 /* Disable all interrupts */ 956 imr = xuartps_readl(XUARTPS_IMR_OFFSET); 957 xuartps_writel(imr, XUARTPS_IDR_OFFSET); 958 959 /* Check if FIFO is empty */ 960 if (xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_RXEMPTY) 961 c = NO_POLL_CHAR; 962 else /* Read a character */ 963 c = (unsigned char) xuartps_readl(XUARTPS_FIFO_OFFSET); 964 965 /* Enable interrupts */ 966 xuartps_writel(imr, XUARTPS_IER_OFFSET); 967 968 return c; 969 } 970 971 static void xuartps_poll_put_char(struct uart_port *port, unsigned char c) 972 { 973 u32 imr; 974 975 /* Disable all interrupts */ 976 imr = xuartps_readl(XUARTPS_IMR_OFFSET); 977 xuartps_writel(imr, XUARTPS_IDR_OFFSET); 978 979 /* Wait until FIFO is empty */ 980 while (!(xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_TXEMPTY)) 981 cpu_relax(); 982 983 /* Write a character */ 984 xuartps_writel(c, XUARTPS_FIFO_OFFSET); 985 986 /* Wait until FIFO is empty */ 987 while (!(xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_TXEMPTY)) 988 cpu_relax(); 989 990 /* Enable interrupts */ 991 xuartps_writel(imr, XUARTPS_IER_OFFSET); 992 993 return; 994 } 995 #endif 996 997 /** The UART operations structure 998 */ 999 static struct uart_ops xuartps_ops = { 1000 .set_mctrl = xuartps_set_mctrl, 1001 .get_mctrl = xuartps_get_mctrl, 1002 .enable_ms = xuartps_enable_ms, 1003 1004 .start_tx = xuartps_start_tx, /* Start transmitting */ 1005 .stop_tx = xuartps_stop_tx, /* Stop transmission */ 1006 .stop_rx = xuartps_stop_rx, /* Stop reception */ 1007 .tx_empty = xuartps_tx_empty, /* Transmitter busy? */ 1008 .break_ctl = xuartps_break_ctl, /* Start/stop 1009 * transmitting break 1010 */ 1011 .set_termios = xuartps_set_termios, /* Set termios */ 1012 .startup = xuartps_startup, /* App opens xuartps */ 1013 .shutdown = xuartps_shutdown, /* App closes xuartps */ 1014 .type = xuartps_type, /* Set UART type */ 1015 .verify_port = xuartps_verify_port, /* Verification of port 1016 * params 1017 */ 1018 .request_port = xuartps_request_port, /* Claim resources 1019 * associated with a 1020 * xuartps port 1021 */ 1022 .release_port = xuartps_release_port, /* Release resources 1023 * associated with a 1024 * xuartps port 1025 */ 1026 .config_port = xuartps_config_port, /* Configure when driver 1027 * adds a xuartps port 1028 */ 1029 #ifdef CONFIG_CONSOLE_POLL 1030 .poll_get_char = xuartps_poll_get_char, 1031 .poll_put_char = xuartps_poll_put_char, 1032 #endif 1033 }; 1034 1035 static struct uart_port xuartps_port[2]; 1036 1037 /** 1038 * xuartps_get_port - Configure the port from the platform device resource 1039 * info 1040 * 1041 * Returns a pointer to a uart_port or NULL for failure 1042 **/ 1043 static struct uart_port *xuartps_get_port(void) 1044 { 1045 struct uart_port *port; 1046 int id; 1047 1048 /* Find the next unused port */ 1049 for (id = 0; id < XUARTPS_NR_PORTS; id++) 1050 if (xuartps_port[id].mapbase == 0) 1051 break; 1052 1053 if (id >= XUARTPS_NR_PORTS) 1054 return NULL; 1055 1056 port = &xuartps_port[id]; 1057 1058 /* At this point, we've got an empty uart_port struct, initialize it */ 1059 spin_lock_init(&port->lock); 1060 port->membase = NULL; 1061 port->iobase = 1; /* mark port in use */ 1062 port->irq = 0; 1063 port->type = PORT_UNKNOWN; 1064 port->iotype = UPIO_MEM32; 1065 port->flags = UPF_BOOT_AUTOCONF; 1066 port->ops = &xuartps_ops; 1067 port->fifosize = XUARTPS_FIFO_SIZE; 1068 port->line = id; 1069 port->dev = NULL; 1070 return port; 1071 } 1072 1073 /*-----------------------Console driver operations--------------------------*/ 1074 1075 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE 1076 /** 1077 * xuartps_console_wait_tx - Wait for the TX to be full 1078 * @port: Handle to the uart port structure 1079 * 1080 **/ 1081 static void xuartps_console_wait_tx(struct uart_port *port) 1082 { 1083 while ((xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_TXEMPTY) 1084 != XUARTPS_SR_TXEMPTY) 1085 barrier(); 1086 } 1087 1088 /** 1089 * xuartps_console_putchar - write the character to the FIFO buffer 1090 * @port: Handle to the uart port structure 1091 * @ch: Character to be written 1092 * 1093 **/ 1094 static void xuartps_console_putchar(struct uart_port *port, int ch) 1095 { 1096 xuartps_console_wait_tx(port); 1097 xuartps_writel(ch, XUARTPS_FIFO_OFFSET); 1098 } 1099 1100 /** 1101 * xuartps_console_write - perform write operation 1102 * @port: Handle to the uart port structure 1103 * @s: Pointer to character array 1104 * @count: No of characters 1105 **/ 1106 static void xuartps_console_write(struct console *co, const char *s, 1107 unsigned int count) 1108 { 1109 struct uart_port *port = &xuartps_port[co->index]; 1110 unsigned long flags; 1111 unsigned int imr, ctrl; 1112 int locked = 1; 1113 1114 if (oops_in_progress) 1115 locked = spin_trylock_irqsave(&port->lock, flags); 1116 else 1117 spin_lock_irqsave(&port->lock, flags); 1118 1119 /* save and disable interrupt */ 1120 imr = xuartps_readl(XUARTPS_IMR_OFFSET); 1121 xuartps_writel(imr, XUARTPS_IDR_OFFSET); 1122 1123 /* 1124 * Make sure that the tx part is enabled. Set the TX enable bit and 1125 * clear the TX disable bit to enable the transmitter. 1126 */ 1127 ctrl = xuartps_readl(XUARTPS_CR_OFFSET); 1128 xuartps_writel((ctrl & ~XUARTPS_CR_TX_DIS) | XUARTPS_CR_TX_EN, 1129 XUARTPS_CR_OFFSET); 1130 1131 uart_console_write(port, s, count, xuartps_console_putchar); 1132 xuartps_console_wait_tx(port); 1133 1134 xuartps_writel(ctrl, XUARTPS_CR_OFFSET); 1135 1136 /* restore interrupt state, it seems like there may be a h/w bug 1137 * in that the interrupt enable register should not need to be 1138 * written based on the data sheet 1139 */ 1140 xuartps_writel(~imr, XUARTPS_IDR_OFFSET); 1141 xuartps_writel(imr, XUARTPS_IER_OFFSET); 1142 1143 if (locked) 1144 spin_unlock_irqrestore(&port->lock, flags); 1145 } 1146 1147 /** 1148 * xuartps_console_setup - Initialize the uart to default config 1149 * @co: Console handle 1150 * @options: Initial settings of uart 1151 * 1152 * Returns 0, -ENODEV if no device 1153 **/ 1154 static int __init xuartps_console_setup(struct console *co, char *options) 1155 { 1156 struct uart_port *port = &xuartps_port[co->index]; 1157 int baud = 9600; 1158 int bits = 8; 1159 int parity = 'n'; 1160 int flow = 'n'; 1161 1162 if (co->index < 0 || co->index >= XUARTPS_NR_PORTS) 1163 return -EINVAL; 1164 1165 if (!port->mapbase) { 1166 pr_debug("console on ttyPS%i not present\n", co->index); 1167 return -ENODEV; 1168 } 1169 1170 if (options) 1171 uart_parse_options(options, &baud, &parity, &bits, &flow); 1172 1173 return uart_set_options(port, co, baud, parity, bits, flow); 1174 } 1175 1176 static struct uart_driver xuartps_uart_driver; 1177 1178 static struct console xuartps_console = { 1179 .name = XUARTPS_TTY_NAME, 1180 .write = xuartps_console_write, 1181 .device = uart_console_device, 1182 .setup = xuartps_console_setup, 1183 .flags = CON_PRINTBUFFER, 1184 .index = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */ 1185 .data = &xuartps_uart_driver, 1186 }; 1187 1188 /** 1189 * xuartps_console_init - Initialization call 1190 * 1191 * Returns 0 on success, negative error otherwise 1192 **/ 1193 static int __init xuartps_console_init(void) 1194 { 1195 register_console(&xuartps_console); 1196 return 0; 1197 } 1198 1199 console_initcall(xuartps_console_init); 1200 1201 #endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */ 1202 1203 /** Structure Definitions 1204 */ 1205 static struct uart_driver xuartps_uart_driver = { 1206 .owner = THIS_MODULE, /* Owner */ 1207 .driver_name = XUARTPS_NAME, /* Driver name */ 1208 .dev_name = XUARTPS_TTY_NAME, /* Node name */ 1209 .major = XUARTPS_MAJOR, /* Major number */ 1210 .minor = XUARTPS_MINOR, /* Minor number */ 1211 .nr = XUARTPS_NR_PORTS, /* Number of UART ports */ 1212 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE 1213 .cons = &xuartps_console, /* Console */ 1214 #endif 1215 }; 1216 1217 #ifdef CONFIG_PM_SLEEP 1218 /** 1219 * xuartps_suspend - suspend event 1220 * @device: Pointer to the device structure 1221 * 1222 * Returns 0 1223 */ 1224 static int xuartps_suspend(struct device *device) 1225 { 1226 struct uart_port *port = dev_get_drvdata(device); 1227 struct tty_struct *tty; 1228 struct device *tty_dev; 1229 int may_wake = 0; 1230 1231 /* Get the tty which could be NULL so don't assume it's valid */ 1232 tty = tty_port_tty_get(&port->state->port); 1233 if (tty) { 1234 tty_dev = tty->dev; 1235 may_wake = device_may_wakeup(tty_dev); 1236 tty_kref_put(tty); 1237 } 1238 1239 /* 1240 * Call the API provided in serial_core.c file which handles 1241 * the suspend. 1242 */ 1243 uart_suspend_port(&xuartps_uart_driver, port); 1244 if (console_suspend_enabled && !may_wake) { 1245 struct xuartps *xuartps = port->private_data; 1246 1247 clk_disable(xuartps->refclk); 1248 clk_disable(xuartps->aperclk); 1249 } else { 1250 unsigned long flags = 0; 1251 1252 spin_lock_irqsave(&port->lock, flags); 1253 /* Empty the receive FIFO 1st before making changes */ 1254 while (!(xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_RXEMPTY)) 1255 xuartps_readl(XUARTPS_FIFO_OFFSET); 1256 /* set RX trigger level to 1 */ 1257 xuartps_writel(1, XUARTPS_RXWM_OFFSET); 1258 /* disable RX timeout interrups */ 1259 xuartps_writel(XUARTPS_IXR_TOUT, XUARTPS_IDR_OFFSET); 1260 spin_unlock_irqrestore(&port->lock, flags); 1261 } 1262 1263 return 0; 1264 } 1265 1266 /** 1267 * xuartps_resume - Resume after a previous suspend 1268 * @device: Pointer to the device structure 1269 * 1270 * Returns 0 1271 */ 1272 static int xuartps_resume(struct device *device) 1273 { 1274 struct uart_port *port = dev_get_drvdata(device); 1275 unsigned long flags = 0; 1276 u32 ctrl_reg; 1277 struct tty_struct *tty; 1278 struct device *tty_dev; 1279 int may_wake = 0; 1280 1281 /* Get the tty which could be NULL so don't assume it's valid */ 1282 tty = tty_port_tty_get(&port->state->port); 1283 if (tty) { 1284 tty_dev = tty->dev; 1285 may_wake = device_may_wakeup(tty_dev); 1286 tty_kref_put(tty); 1287 } 1288 1289 if (console_suspend_enabled && !may_wake) { 1290 struct xuartps *xuartps = port->private_data; 1291 1292 clk_enable(xuartps->aperclk); 1293 clk_enable(xuartps->refclk); 1294 1295 spin_lock_irqsave(&port->lock, flags); 1296 1297 /* Set TX/RX Reset */ 1298 xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) | 1299 (XUARTPS_CR_TXRST | XUARTPS_CR_RXRST), 1300 XUARTPS_CR_OFFSET); 1301 while (xuartps_readl(XUARTPS_CR_OFFSET) & 1302 (XUARTPS_CR_TXRST | XUARTPS_CR_RXRST)) 1303 cpu_relax(); 1304 1305 /* restore rx timeout value */ 1306 xuartps_writel(rx_timeout, XUARTPS_RXTOUT_OFFSET); 1307 /* Enable Tx/Rx */ 1308 ctrl_reg = xuartps_readl(XUARTPS_CR_OFFSET); 1309 xuartps_writel( 1310 (ctrl_reg & ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS)) | 1311 (XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN), 1312 XUARTPS_CR_OFFSET); 1313 1314 spin_unlock_irqrestore(&port->lock, flags); 1315 } else { 1316 spin_lock_irqsave(&port->lock, flags); 1317 /* restore original rx trigger level */ 1318 xuartps_writel(rx_trigger_level, XUARTPS_RXWM_OFFSET); 1319 /* enable RX timeout interrupt */ 1320 xuartps_writel(XUARTPS_IXR_TOUT, XUARTPS_IER_OFFSET); 1321 spin_unlock_irqrestore(&port->lock, flags); 1322 } 1323 1324 return uart_resume_port(&xuartps_uart_driver, port); 1325 } 1326 #endif /* ! CONFIG_PM_SLEEP */ 1327 1328 static SIMPLE_DEV_PM_OPS(xuartps_dev_pm_ops, xuartps_suspend, xuartps_resume); 1329 1330 /* --------------------------------------------------------------------- 1331 * Platform bus binding 1332 */ 1333 /** 1334 * xuartps_probe - Platform driver probe 1335 * @pdev: Pointer to the platform device structure 1336 * 1337 * Returns 0 on success, negative error otherwise 1338 **/ 1339 static int xuartps_probe(struct platform_device *pdev) 1340 { 1341 int rc; 1342 struct uart_port *port; 1343 struct resource *res, *res2; 1344 struct xuartps *xuartps_data; 1345 1346 xuartps_data = devm_kzalloc(&pdev->dev, sizeof(*xuartps_data), 1347 GFP_KERNEL); 1348 if (!xuartps_data) 1349 return -ENOMEM; 1350 1351 xuartps_data->aperclk = devm_clk_get(&pdev->dev, "aper_clk"); 1352 if (IS_ERR(xuartps_data->aperclk)) { 1353 dev_err(&pdev->dev, "aper_clk clock not found.\n"); 1354 return PTR_ERR(xuartps_data->aperclk); 1355 } 1356 xuartps_data->refclk = devm_clk_get(&pdev->dev, "ref_clk"); 1357 if (IS_ERR(xuartps_data->refclk)) { 1358 dev_err(&pdev->dev, "ref_clk clock not found.\n"); 1359 return PTR_ERR(xuartps_data->refclk); 1360 } 1361 1362 rc = clk_prepare_enable(xuartps_data->aperclk); 1363 if (rc) { 1364 dev_err(&pdev->dev, "Unable to enable APER clock.\n"); 1365 return rc; 1366 } 1367 rc = clk_prepare_enable(xuartps_data->refclk); 1368 if (rc) { 1369 dev_err(&pdev->dev, "Unable to enable device clock.\n"); 1370 goto err_out_clk_dis_aper; 1371 } 1372 1373 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1374 if (!res) { 1375 rc = -ENODEV; 1376 goto err_out_clk_disable; 1377 } 1378 1379 res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1380 if (!res2) { 1381 rc = -ENODEV; 1382 goto err_out_clk_disable; 1383 } 1384 1385 #ifdef CONFIG_COMMON_CLK 1386 xuartps_data->clk_rate_change_nb.notifier_call = 1387 xuartps_clk_notifier_cb; 1388 if (clk_notifier_register(xuartps_data->refclk, 1389 &xuartps_data->clk_rate_change_nb)) 1390 dev_warn(&pdev->dev, "Unable to register clock notifier.\n"); 1391 #endif 1392 1393 /* Initialize the port structure */ 1394 port = xuartps_get_port(); 1395 1396 if (!port) { 1397 dev_err(&pdev->dev, "Cannot get uart_port structure\n"); 1398 rc = -ENODEV; 1399 goto err_out_notif_unreg; 1400 } else { 1401 /* Register the port. 1402 * This function also registers this device with the tty layer 1403 * and triggers invocation of the config_port() entry point. 1404 */ 1405 port->mapbase = res->start; 1406 port->irq = res2->start; 1407 port->dev = &pdev->dev; 1408 port->uartclk = clk_get_rate(xuartps_data->refclk); 1409 port->private_data = xuartps_data; 1410 xuartps_data->port = port; 1411 platform_set_drvdata(pdev, port); 1412 rc = uart_add_one_port(&xuartps_uart_driver, port); 1413 if (rc) { 1414 dev_err(&pdev->dev, 1415 "uart_add_one_port() failed; err=%i\n", rc); 1416 goto err_out_notif_unreg; 1417 } 1418 return 0; 1419 } 1420 1421 err_out_notif_unreg: 1422 #ifdef CONFIG_COMMON_CLK 1423 clk_notifier_unregister(xuartps_data->refclk, 1424 &xuartps_data->clk_rate_change_nb); 1425 #endif 1426 err_out_clk_disable: 1427 clk_disable_unprepare(xuartps_data->refclk); 1428 err_out_clk_dis_aper: 1429 clk_disable_unprepare(xuartps_data->aperclk); 1430 1431 return rc; 1432 } 1433 1434 /** 1435 * xuartps_remove - called when the platform driver is unregistered 1436 * @pdev: Pointer to the platform device structure 1437 * 1438 * Returns 0 on success, negative error otherwise 1439 **/ 1440 static int xuartps_remove(struct platform_device *pdev) 1441 { 1442 struct uart_port *port = platform_get_drvdata(pdev); 1443 struct xuartps *xuartps_data = port->private_data; 1444 int rc; 1445 1446 /* Remove the xuartps port from the serial core */ 1447 #ifdef CONFIG_COMMON_CLK 1448 clk_notifier_unregister(xuartps_data->refclk, 1449 &xuartps_data->clk_rate_change_nb); 1450 #endif 1451 rc = uart_remove_one_port(&xuartps_uart_driver, port); 1452 port->mapbase = 0; 1453 clk_disable_unprepare(xuartps_data->refclk); 1454 clk_disable_unprepare(xuartps_data->aperclk); 1455 return rc; 1456 } 1457 1458 /* Match table for of_platform binding */ 1459 static struct of_device_id xuartps_of_match[] = { 1460 { .compatible = "xlnx,xuartps", }, 1461 {} 1462 }; 1463 MODULE_DEVICE_TABLE(of, xuartps_of_match); 1464 1465 static struct platform_driver xuartps_platform_driver = { 1466 .probe = xuartps_probe, /* Probe method */ 1467 .remove = xuartps_remove, /* Detach method */ 1468 .driver = { 1469 .owner = THIS_MODULE, 1470 .name = XUARTPS_NAME, /* Driver name */ 1471 .of_match_table = xuartps_of_match, 1472 .pm = &xuartps_dev_pm_ops, 1473 }, 1474 }; 1475 1476 /* --------------------------------------------------------------------- 1477 * Module Init and Exit 1478 */ 1479 /** 1480 * xuartps_init - Initial driver registration call 1481 * 1482 * Returns whether the registration was successful or not 1483 **/ 1484 static int __init xuartps_init(void) 1485 { 1486 int retval = 0; 1487 1488 /* Register the xuartps driver with the serial core */ 1489 retval = uart_register_driver(&xuartps_uart_driver); 1490 if (retval) 1491 return retval; 1492 1493 /* Register the platform driver */ 1494 retval = platform_driver_register(&xuartps_platform_driver); 1495 if (retval) 1496 uart_unregister_driver(&xuartps_uart_driver); 1497 1498 return retval; 1499 } 1500 1501 /** 1502 * xuartps_exit - Driver unregistration call 1503 **/ 1504 static void __exit xuartps_exit(void) 1505 { 1506 /* The order of unregistration is important. Unregister the 1507 * UART driver before the platform driver crashes the system. 1508 */ 1509 1510 /* Unregister the platform driver */ 1511 platform_driver_unregister(&xuartps_platform_driver); 1512 1513 /* Unregister the xuartps driver */ 1514 uart_unregister_driver(&xuartps_uart_driver); 1515 } 1516 1517 module_init(xuartps_init); 1518 module_exit(xuartps_exit); 1519 1520 MODULE_DESCRIPTION("Driver for PS UART"); 1521 MODULE_AUTHOR("Xilinx Inc."); 1522 MODULE_LICENSE("GPL"); 1523