1 /* 2 * Xilinx PS UART driver 3 * 4 * 2011 (c) Xilinx Inc. 5 * 6 * This program is free software; you can redistribute it 7 * and/or modify it under the terms of the GNU General Public 8 * License as published by the Free Software Foundation; 9 * either version 2 of the License, or (at your option) any 10 * later version. 11 * 12 */ 13 14 #include <linux/platform_device.h> 15 #include <linux/serial.h> 16 #include <linux/serial_core.h> 17 #include <linux/slab.h> 18 #include <linux/tty.h> 19 #include <linux/tty_flip.h> 20 #include <linux/console.h> 21 #include <linux/clk.h> 22 #include <linux/irq.h> 23 #include <linux/io.h> 24 #include <linux/of.h> 25 #include <linux/module.h> 26 27 #define XUARTPS_TTY_NAME "ttyPS" 28 #define XUARTPS_NAME "xuartps" 29 #define XUARTPS_MAJOR 0 /* use dynamic node allocation */ 30 #define XUARTPS_MINOR 0 /* works best with devtmpfs */ 31 #define XUARTPS_NR_PORTS 2 32 #define XUARTPS_FIFO_SIZE 16 /* FIFO size */ 33 #define XUARTPS_REGISTER_SPACE 0xFFF 34 35 #define xuartps_readl(offset) ioread32(port->membase + offset) 36 #define xuartps_writel(val, offset) iowrite32(val, port->membase + offset) 37 38 /********************************Register Map********************************/ 39 /** UART 40 * 41 * Register offsets for the UART. 42 * 43 */ 44 #define XUARTPS_CR_OFFSET 0x00 /* Control Register [8:0] */ 45 #define XUARTPS_MR_OFFSET 0x04 /* Mode Register [10:0] */ 46 #define XUARTPS_IER_OFFSET 0x08 /* Interrupt Enable [10:0] */ 47 #define XUARTPS_IDR_OFFSET 0x0C /* Interrupt Disable [10:0] */ 48 #define XUARTPS_IMR_OFFSET 0x10 /* Interrupt Mask [10:0] */ 49 #define XUARTPS_ISR_OFFSET 0x14 /* Interrupt Status [10:0]*/ 50 #define XUARTPS_BAUDGEN_OFFSET 0x18 /* Baud Rate Generator [15:0] */ 51 #define XUARTPS_RXTOUT_OFFSET 0x1C /* RX Timeout [7:0] */ 52 #define XUARTPS_RXWM_OFFSET 0x20 /* RX FIFO Trigger Level [5:0] */ 53 #define XUARTPS_MODEMCR_OFFSET 0x24 /* Modem Control [5:0] */ 54 #define XUARTPS_MODEMSR_OFFSET 0x28 /* Modem Status [8:0] */ 55 #define XUARTPS_SR_OFFSET 0x2C /* Channel Status [11:0] */ 56 #define XUARTPS_FIFO_OFFSET 0x30 /* FIFO [15:0] or [7:0] */ 57 #define XUARTPS_BAUDDIV_OFFSET 0x34 /* Baud Rate Divider [7:0] */ 58 #define XUARTPS_FLOWDEL_OFFSET 0x38 /* Flow Delay [15:0] */ 59 #define XUARTPS_IRRX_PWIDTH_OFFSET 0x3C /* IR Minimum Received Pulse 60 Width [15:0] */ 61 #define XUARTPS_IRTX_PWIDTH_OFFSET 0x40 /* IR Transmitted pulse 62 Width [7:0] */ 63 #define XUARTPS_TXWM_OFFSET 0x44 /* TX FIFO Trigger Level [5:0] */ 64 65 /** Control Register 66 * 67 * The Control register (CR) controls the major functions of the device. 68 * 69 * Control Register Bit Definitions 70 */ 71 #define XUARTPS_CR_STOPBRK 0x00000100 /* Stop TX break */ 72 #define XUARTPS_CR_STARTBRK 0x00000080 /* Set TX break */ 73 #define XUARTPS_CR_TX_DIS 0x00000020 /* TX disabled. */ 74 #define XUARTPS_CR_TX_EN 0x00000010 /* TX enabled */ 75 #define XUARTPS_CR_RX_DIS 0x00000008 /* RX disabled. */ 76 #define XUARTPS_CR_RX_EN 0x00000004 /* RX enabled */ 77 #define XUARTPS_CR_TXRST 0x00000002 /* TX logic reset */ 78 #define XUARTPS_CR_RXRST 0x00000001 /* RX logic reset */ 79 #define XUARTPS_CR_RST_TO 0x00000040 /* Restart Timeout Counter */ 80 81 /** Mode Register 82 * 83 * The mode register (MR) defines the mode of transfer as well as the data 84 * format. If this register is modified during transmission or reception, 85 * data validity cannot be guaranteed. 86 * 87 * Mode Register Bit Definitions 88 * 89 */ 90 #define XUARTPS_MR_CLKSEL 0x00000001 /* Pre-scalar selection */ 91 #define XUARTPS_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */ 92 #define XUARTPS_MR_CHMODE_NORM 0x00000000 /* Normal mode */ 93 94 #define XUARTPS_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */ 95 #define XUARTPS_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */ 96 97 #define XUARTPS_MR_PARITY_NONE 0x00000020 /* No parity mode */ 98 #define XUARTPS_MR_PARITY_MARK 0x00000018 /* Mark parity mode */ 99 #define XUARTPS_MR_PARITY_SPACE 0x00000010 /* Space parity mode */ 100 #define XUARTPS_MR_PARITY_ODD 0x00000008 /* Odd parity mode */ 101 #define XUARTPS_MR_PARITY_EVEN 0x00000000 /* Even parity mode */ 102 103 #define XUARTPS_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */ 104 #define XUARTPS_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */ 105 #define XUARTPS_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */ 106 107 /** Interrupt Registers 108 * 109 * Interrupt control logic uses the interrupt enable register (IER) and the 110 * interrupt disable register (IDR) to set the value of the bits in the 111 * interrupt mask register (IMR). The IMR determines whether to pass an 112 * interrupt to the interrupt status register (ISR). 113 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an 114 * interrupt. IMR and ISR are read only, and IER and IDR are write only. 115 * Reading either IER or IDR returns 0x00. 116 * 117 * All four registers have the same bit definitions. 118 */ 119 #define XUARTPS_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */ 120 #define XUARTPS_IXR_PARITY 0x00000080 /* Parity error interrupt */ 121 #define XUARTPS_IXR_FRAMING 0x00000040 /* Framing error interrupt */ 122 #define XUARTPS_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */ 123 #define XUARTPS_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */ 124 #define XUARTPS_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */ 125 #define XUARTPS_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */ 126 #define XUARTPS_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */ 127 #define XUARTPS_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */ 128 #define XUARTPS_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */ 129 #define XUARTPS_IXR_MASK 0x00001FFF /* Valid bit mask */ 130 131 /** Channel Status Register 132 * 133 * The channel status register (CSR) is provided to enable the control logic 134 * to monitor the status of bits in the channel interrupt status register, 135 * even if these are masked out by the interrupt mask register. 136 */ 137 #define XUARTPS_SR_RXEMPTY 0x00000002 /* RX FIFO empty */ 138 #define XUARTPS_SR_TXEMPTY 0x00000008 /* TX FIFO empty */ 139 #define XUARTPS_SR_TXFULL 0x00000010 /* TX FIFO full */ 140 #define XUARTPS_SR_RXTRIG 0x00000001 /* Rx Trigger */ 141 142 /** 143 * struct xuartps - device data 144 * @refclk Reference clock 145 * @aperclk APB clock 146 */ 147 struct xuartps { 148 struct clk *refclk; 149 struct clk *aperclk; 150 }; 151 152 /** 153 * xuartps_isr - Interrupt handler 154 * @irq: Irq number 155 * @dev_id: Id of the port 156 * 157 * Returns IRQHANDLED 158 **/ 159 static irqreturn_t xuartps_isr(int irq, void *dev_id) 160 { 161 struct uart_port *port = (struct uart_port *)dev_id; 162 unsigned long flags; 163 unsigned int isrstatus, numbytes; 164 unsigned int data; 165 char status = TTY_NORMAL; 166 167 spin_lock_irqsave(&port->lock, flags); 168 169 /* Read the interrupt status register to determine which 170 * interrupt(s) is/are active. 171 */ 172 isrstatus = xuartps_readl(XUARTPS_ISR_OFFSET); 173 174 /* drop byte with parity error if IGNPAR specified */ 175 if (isrstatus & port->ignore_status_mask & XUARTPS_IXR_PARITY) 176 isrstatus &= ~(XUARTPS_IXR_RXTRIG | XUARTPS_IXR_TOUT); 177 178 isrstatus &= port->read_status_mask; 179 isrstatus &= ~port->ignore_status_mask; 180 181 if ((isrstatus & XUARTPS_IXR_TOUT) || 182 (isrstatus & XUARTPS_IXR_RXTRIG)) { 183 /* Receive Timeout Interrupt */ 184 while ((xuartps_readl(XUARTPS_SR_OFFSET) & 185 XUARTPS_SR_RXEMPTY) != XUARTPS_SR_RXEMPTY) { 186 data = xuartps_readl(XUARTPS_FIFO_OFFSET); 187 port->icount.rx++; 188 189 if (isrstatus & XUARTPS_IXR_PARITY) { 190 port->icount.parity++; 191 status = TTY_PARITY; 192 } else if (isrstatus & XUARTPS_IXR_FRAMING) { 193 port->icount.frame++; 194 status = TTY_FRAME; 195 } else if (isrstatus & XUARTPS_IXR_OVERRUN) 196 port->icount.overrun++; 197 198 uart_insert_char(port, isrstatus, XUARTPS_IXR_OVERRUN, 199 data, status); 200 } 201 spin_unlock(&port->lock); 202 tty_flip_buffer_push(&port->state->port); 203 spin_lock(&port->lock); 204 } 205 206 /* Dispatch an appropriate handler */ 207 if ((isrstatus & XUARTPS_IXR_TXEMPTY) == XUARTPS_IXR_TXEMPTY) { 208 if (uart_circ_empty(&port->state->xmit)) { 209 xuartps_writel(XUARTPS_IXR_TXEMPTY, 210 XUARTPS_IDR_OFFSET); 211 } else { 212 numbytes = port->fifosize; 213 /* Break if no more data available in the UART buffer */ 214 while (numbytes--) { 215 if (uart_circ_empty(&port->state->xmit)) 216 break; 217 /* Get the data from the UART circular buffer 218 * and write it to the xuartps's TX_FIFO 219 * register. 220 */ 221 xuartps_writel( 222 port->state->xmit.buf[port->state->xmit. 223 tail], XUARTPS_FIFO_OFFSET); 224 225 port->icount.tx++; 226 227 /* Adjust the tail of the UART buffer and wrap 228 * the buffer if it reaches limit. 229 */ 230 port->state->xmit.tail = 231 (port->state->xmit.tail + 1) & \ 232 (UART_XMIT_SIZE - 1); 233 } 234 235 if (uart_circ_chars_pending( 236 &port->state->xmit) < WAKEUP_CHARS) 237 uart_write_wakeup(port); 238 } 239 } 240 241 xuartps_writel(isrstatus, XUARTPS_ISR_OFFSET); 242 243 /* be sure to release the lock and tty before leaving */ 244 spin_unlock_irqrestore(&port->lock, flags); 245 246 return IRQ_HANDLED; 247 } 248 249 /** 250 * xuartps_set_baud_rate - Calculate and set the baud rate 251 * @port: Handle to the uart port structure 252 * @baud: Baud rate to set 253 * 254 * Returns baud rate, requested baud when possible, or actual baud when there 255 * was too much error 256 **/ 257 static unsigned int xuartps_set_baud_rate(struct uart_port *port, 258 unsigned int baud) 259 { 260 unsigned int sel_clk; 261 unsigned int calc_baud = 0; 262 unsigned int brgr_val, brdiv_val; 263 unsigned int bauderror; 264 265 /* Formula to obtain baud rate is 266 * baud_tx/rx rate = sel_clk/CD * (BDIV + 1) 267 * input_clk = (Uart User Defined Clock or Apb Clock) 268 * depends on UCLKEN in MR Reg 269 * sel_clk = input_clk or input_clk/8; 270 * depends on CLKS in MR reg 271 * CD and BDIV depends on values in 272 * baud rate generate register 273 * baud rate clock divisor register 274 */ 275 sel_clk = port->uartclk; 276 if (xuartps_readl(XUARTPS_MR_OFFSET) & XUARTPS_MR_CLKSEL) 277 sel_clk = sel_clk / 8; 278 279 /* Find the best values for baud generation */ 280 for (brdiv_val = 4; brdiv_val < 255; brdiv_val++) { 281 282 brgr_val = sel_clk / (baud * (brdiv_val + 1)); 283 if (brgr_val < 2 || brgr_val > 65535) 284 continue; 285 286 calc_baud = sel_clk / (brgr_val * (brdiv_val + 1)); 287 288 if (baud > calc_baud) 289 bauderror = baud - calc_baud; 290 else 291 bauderror = calc_baud - baud; 292 293 /* use the values when percent error is acceptable */ 294 if (((bauderror * 100) / baud) < 3) { 295 calc_baud = baud; 296 break; 297 } 298 } 299 300 /* Set the values for the new baud rate */ 301 xuartps_writel(brgr_val, XUARTPS_BAUDGEN_OFFSET); 302 xuartps_writel(brdiv_val, XUARTPS_BAUDDIV_OFFSET); 303 304 return calc_baud; 305 } 306 307 /*----------------------Uart Operations---------------------------*/ 308 309 /** 310 * xuartps_start_tx - Start transmitting bytes 311 * @port: Handle to the uart port structure 312 * 313 **/ 314 static void xuartps_start_tx(struct uart_port *port) 315 { 316 unsigned int status, numbytes = port->fifosize; 317 318 if (uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port)) 319 return; 320 321 status = xuartps_readl(XUARTPS_CR_OFFSET); 322 /* Set the TX enable bit and clear the TX disable bit to enable the 323 * transmitter. 324 */ 325 xuartps_writel((status & ~XUARTPS_CR_TX_DIS) | XUARTPS_CR_TX_EN, 326 XUARTPS_CR_OFFSET); 327 328 while (numbytes-- && ((xuartps_readl(XUARTPS_SR_OFFSET) 329 & XUARTPS_SR_TXFULL)) != XUARTPS_SR_TXFULL) { 330 331 /* Break if no more data available in the UART buffer */ 332 if (uart_circ_empty(&port->state->xmit)) 333 break; 334 335 /* Get the data from the UART circular buffer and 336 * write it to the xuartps's TX_FIFO register. 337 */ 338 xuartps_writel( 339 port->state->xmit.buf[port->state->xmit.tail], 340 XUARTPS_FIFO_OFFSET); 341 port->icount.tx++; 342 343 /* Adjust the tail of the UART buffer and wrap 344 * the buffer if it reaches limit. 345 */ 346 port->state->xmit.tail = (port->state->xmit.tail + 1) & 347 (UART_XMIT_SIZE - 1); 348 } 349 350 /* Enable the TX Empty interrupt */ 351 xuartps_writel(XUARTPS_IXR_TXEMPTY, XUARTPS_IER_OFFSET); 352 353 if (uart_circ_chars_pending(&port->state->xmit) < WAKEUP_CHARS) 354 uart_write_wakeup(port); 355 } 356 357 /** 358 * xuartps_stop_tx - Stop TX 359 * @port: Handle to the uart port structure 360 * 361 **/ 362 static void xuartps_stop_tx(struct uart_port *port) 363 { 364 unsigned int regval; 365 366 regval = xuartps_readl(XUARTPS_CR_OFFSET); 367 regval |= XUARTPS_CR_TX_DIS; 368 /* Disable the transmitter */ 369 xuartps_writel(regval, XUARTPS_CR_OFFSET); 370 } 371 372 /** 373 * xuartps_stop_rx - Stop RX 374 * @port: Handle to the uart port structure 375 * 376 **/ 377 static void xuartps_stop_rx(struct uart_port *port) 378 { 379 unsigned int regval; 380 381 regval = xuartps_readl(XUARTPS_CR_OFFSET); 382 regval |= XUARTPS_CR_RX_DIS; 383 /* Disable the receiver */ 384 xuartps_writel(regval, XUARTPS_CR_OFFSET); 385 } 386 387 /** 388 * xuartps_tx_empty - Check whether TX is empty 389 * @port: Handle to the uart port structure 390 * 391 * Returns TIOCSER_TEMT on success, 0 otherwise 392 **/ 393 static unsigned int xuartps_tx_empty(struct uart_port *port) 394 { 395 unsigned int status; 396 397 status = xuartps_readl(XUARTPS_ISR_OFFSET) & XUARTPS_IXR_TXEMPTY; 398 return status ? TIOCSER_TEMT : 0; 399 } 400 401 /** 402 * xuartps_break_ctl - Based on the input ctl we have to start or stop 403 * transmitting char breaks 404 * @port: Handle to the uart port structure 405 * @ctl: Value based on which start or stop decision is taken 406 * 407 **/ 408 static void xuartps_break_ctl(struct uart_port *port, int ctl) 409 { 410 unsigned int status; 411 unsigned long flags; 412 413 spin_lock_irqsave(&port->lock, flags); 414 415 status = xuartps_readl(XUARTPS_CR_OFFSET); 416 417 if (ctl == -1) 418 xuartps_writel(XUARTPS_CR_STARTBRK | status, 419 XUARTPS_CR_OFFSET); 420 else { 421 if ((status & XUARTPS_CR_STOPBRK) == 0) 422 xuartps_writel(XUARTPS_CR_STOPBRK | status, 423 XUARTPS_CR_OFFSET); 424 } 425 spin_unlock_irqrestore(&port->lock, flags); 426 } 427 428 /** 429 * xuartps_set_termios - termios operations, handling data length, parity, 430 * stop bits, flow control, baud rate 431 * @port: Handle to the uart port structure 432 * @termios: Handle to the input termios structure 433 * @old: Values of the previously saved termios structure 434 * 435 **/ 436 static void xuartps_set_termios(struct uart_port *port, 437 struct ktermios *termios, struct ktermios *old) 438 { 439 unsigned int cval = 0; 440 unsigned int baud; 441 unsigned long flags; 442 unsigned int ctrl_reg, mode_reg; 443 444 spin_lock_irqsave(&port->lock, flags); 445 446 /* Empty the receive FIFO 1st before making changes */ 447 while ((xuartps_readl(XUARTPS_SR_OFFSET) & 448 XUARTPS_SR_RXEMPTY) != XUARTPS_SR_RXEMPTY) { 449 xuartps_readl(XUARTPS_FIFO_OFFSET); 450 } 451 452 /* Disable the TX and RX to set baud rate */ 453 xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) | 454 (XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS), 455 XUARTPS_CR_OFFSET); 456 457 /* Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk */ 458 baud = uart_get_baud_rate(port, termios, old, 0, 10000000); 459 baud = xuartps_set_baud_rate(port, baud); 460 if (tty_termios_baud_rate(termios)) 461 tty_termios_encode_baud_rate(termios, baud, baud); 462 463 /* 464 * Update the per-port timeout. 465 */ 466 uart_update_timeout(port, termios->c_cflag, baud); 467 468 /* Set TX/RX Reset */ 469 xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) | 470 (XUARTPS_CR_TXRST | XUARTPS_CR_RXRST), 471 XUARTPS_CR_OFFSET); 472 473 ctrl_reg = xuartps_readl(XUARTPS_CR_OFFSET); 474 475 /* Clear the RX disable and TX disable bits and then set the TX enable 476 * bit and RX enable bit to enable the transmitter and receiver. 477 */ 478 xuartps_writel( 479 (ctrl_reg & ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS)) 480 | (XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN), 481 XUARTPS_CR_OFFSET); 482 483 xuartps_writel(10, XUARTPS_RXTOUT_OFFSET); 484 485 port->read_status_mask = XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_RXTRIG | 486 XUARTPS_IXR_OVERRUN | XUARTPS_IXR_TOUT; 487 port->ignore_status_mask = 0; 488 489 if (termios->c_iflag & INPCK) 490 port->read_status_mask |= XUARTPS_IXR_PARITY | 491 XUARTPS_IXR_FRAMING; 492 493 if (termios->c_iflag & IGNPAR) 494 port->ignore_status_mask |= XUARTPS_IXR_PARITY | 495 XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN; 496 497 /* ignore all characters if CREAD is not set */ 498 if ((termios->c_cflag & CREAD) == 0) 499 port->ignore_status_mask |= XUARTPS_IXR_RXTRIG | 500 XUARTPS_IXR_TOUT | XUARTPS_IXR_PARITY | 501 XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN; 502 503 mode_reg = xuartps_readl(XUARTPS_MR_OFFSET); 504 505 /* Handling Data Size */ 506 switch (termios->c_cflag & CSIZE) { 507 case CS6: 508 cval |= XUARTPS_MR_CHARLEN_6_BIT; 509 break; 510 case CS7: 511 cval |= XUARTPS_MR_CHARLEN_7_BIT; 512 break; 513 default: 514 case CS8: 515 cval |= XUARTPS_MR_CHARLEN_8_BIT; 516 termios->c_cflag &= ~CSIZE; 517 termios->c_cflag |= CS8; 518 break; 519 } 520 521 /* Handling Parity and Stop Bits length */ 522 if (termios->c_cflag & CSTOPB) 523 cval |= XUARTPS_MR_STOPMODE_2_BIT; /* 2 STOP bits */ 524 else 525 cval |= XUARTPS_MR_STOPMODE_1_BIT; /* 1 STOP bit */ 526 527 if (termios->c_cflag & PARENB) { 528 /* Mark or Space parity */ 529 if (termios->c_cflag & CMSPAR) { 530 if (termios->c_cflag & PARODD) 531 cval |= XUARTPS_MR_PARITY_MARK; 532 else 533 cval |= XUARTPS_MR_PARITY_SPACE; 534 } else if (termios->c_cflag & PARODD) 535 cval |= XUARTPS_MR_PARITY_ODD; 536 else 537 cval |= XUARTPS_MR_PARITY_EVEN; 538 } else 539 cval |= XUARTPS_MR_PARITY_NONE; 540 xuartps_writel(cval , XUARTPS_MR_OFFSET); 541 542 spin_unlock_irqrestore(&port->lock, flags); 543 } 544 545 /** 546 * xuartps_startup - Called when an application opens a xuartps port 547 * @port: Handle to the uart port structure 548 * 549 * Returns 0 on success, negative error otherwise 550 **/ 551 static int xuartps_startup(struct uart_port *port) 552 { 553 unsigned int retval = 0, status = 0; 554 555 retval = request_irq(port->irq, xuartps_isr, 0, XUARTPS_NAME, 556 (void *)port); 557 if (retval) 558 return retval; 559 560 /* Disable the TX and RX */ 561 xuartps_writel(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS, 562 XUARTPS_CR_OFFSET); 563 564 /* Set the Control Register with TX/RX Enable, TX/RX Reset, 565 * no break chars. 566 */ 567 xuartps_writel(XUARTPS_CR_TXRST | XUARTPS_CR_RXRST, 568 XUARTPS_CR_OFFSET); 569 570 status = xuartps_readl(XUARTPS_CR_OFFSET); 571 572 /* Clear the RX disable and TX disable bits and then set the TX enable 573 * bit and RX enable bit to enable the transmitter and receiver. 574 */ 575 xuartps_writel((status & ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS)) 576 | (XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN | 577 XUARTPS_CR_STOPBRK), XUARTPS_CR_OFFSET); 578 579 /* Set the Mode Register with normal mode,8 data bits,1 stop bit, 580 * no parity. 581 */ 582 xuartps_writel(XUARTPS_MR_CHMODE_NORM | XUARTPS_MR_STOPMODE_1_BIT 583 | XUARTPS_MR_PARITY_NONE | XUARTPS_MR_CHARLEN_8_BIT, 584 XUARTPS_MR_OFFSET); 585 586 /* Set the RX FIFO Trigger level to 14 assuming FIFO size as 16 */ 587 xuartps_writel(14, XUARTPS_RXWM_OFFSET); 588 589 /* Receive Timeout register is enabled with value of 10 */ 590 xuartps_writel(10, XUARTPS_RXTOUT_OFFSET); 591 592 /* Clear out any pending interrupts before enabling them */ 593 xuartps_writel(xuartps_readl(XUARTPS_ISR_OFFSET), XUARTPS_ISR_OFFSET); 594 595 /* Set the Interrupt Registers with desired interrupts */ 596 xuartps_writel(XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_PARITY | 597 XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN | 598 XUARTPS_IXR_RXTRIG | XUARTPS_IXR_TOUT, XUARTPS_IER_OFFSET); 599 600 return retval; 601 } 602 603 /** 604 * xuartps_shutdown - Called when an application closes a xuartps port 605 * @port: Handle to the uart port structure 606 * 607 **/ 608 static void xuartps_shutdown(struct uart_port *port) 609 { 610 int status; 611 612 /* Disable interrupts */ 613 status = xuartps_readl(XUARTPS_IMR_OFFSET); 614 xuartps_writel(status, XUARTPS_IDR_OFFSET); 615 616 /* Disable the TX and RX */ 617 xuartps_writel(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS, 618 XUARTPS_CR_OFFSET); 619 free_irq(port->irq, port); 620 } 621 622 /** 623 * xuartps_type - Set UART type to xuartps port 624 * @port: Handle to the uart port structure 625 * 626 * Returns string on success, NULL otherwise 627 **/ 628 static const char *xuartps_type(struct uart_port *port) 629 { 630 return port->type == PORT_XUARTPS ? XUARTPS_NAME : NULL; 631 } 632 633 /** 634 * xuartps_verify_port - Verify the port params 635 * @port: Handle to the uart port structure 636 * @ser: Handle to the structure whose members are compared 637 * 638 * Returns 0 if success otherwise -EINVAL 639 **/ 640 static int xuartps_verify_port(struct uart_port *port, 641 struct serial_struct *ser) 642 { 643 if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS) 644 return -EINVAL; 645 if (port->irq != ser->irq) 646 return -EINVAL; 647 if (ser->io_type != UPIO_MEM) 648 return -EINVAL; 649 if (port->iobase != ser->port) 650 return -EINVAL; 651 if (ser->hub6 != 0) 652 return -EINVAL; 653 return 0; 654 } 655 656 /** 657 * xuartps_request_port - Claim the memory region attached to xuartps port, 658 * called when the driver adds a xuartps port via 659 * uart_add_one_port() 660 * @port: Handle to the uart port structure 661 * 662 * Returns 0, -ENOMEM if request fails 663 **/ 664 static int xuartps_request_port(struct uart_port *port) 665 { 666 if (!request_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE, 667 XUARTPS_NAME)) { 668 return -ENOMEM; 669 } 670 671 port->membase = ioremap(port->mapbase, XUARTPS_REGISTER_SPACE); 672 if (!port->membase) { 673 dev_err(port->dev, "Unable to map registers\n"); 674 release_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE); 675 return -ENOMEM; 676 } 677 return 0; 678 } 679 680 /** 681 * xuartps_release_port - Release the memory region attached to a xuartps 682 * port, called when the driver removes a xuartps 683 * port via uart_remove_one_port(). 684 * @port: Handle to the uart port structure 685 * 686 **/ 687 static void xuartps_release_port(struct uart_port *port) 688 { 689 release_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE); 690 iounmap(port->membase); 691 port->membase = NULL; 692 } 693 694 /** 695 * xuartps_config_port - Configure xuartps, called when the driver adds a 696 * xuartps port 697 * @port: Handle to the uart port structure 698 * @flags: If any 699 * 700 **/ 701 static void xuartps_config_port(struct uart_port *port, int flags) 702 { 703 if (flags & UART_CONFIG_TYPE && xuartps_request_port(port) == 0) 704 port->type = PORT_XUARTPS; 705 } 706 707 /** 708 * xuartps_get_mctrl - Get the modem control state 709 * 710 * @port: Handle to the uart port structure 711 * 712 * Returns the modem control state 713 * 714 **/ 715 static unsigned int xuartps_get_mctrl(struct uart_port *port) 716 { 717 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; 718 } 719 720 static void xuartps_set_mctrl(struct uart_port *port, unsigned int mctrl) 721 { 722 /* N/A */ 723 } 724 725 static void xuartps_enable_ms(struct uart_port *port) 726 { 727 /* N/A */ 728 } 729 730 /** The UART operations structure 731 */ 732 static struct uart_ops xuartps_ops = { 733 .set_mctrl = xuartps_set_mctrl, 734 .get_mctrl = xuartps_get_mctrl, 735 .enable_ms = xuartps_enable_ms, 736 737 .start_tx = xuartps_start_tx, /* Start transmitting */ 738 .stop_tx = xuartps_stop_tx, /* Stop transmission */ 739 .stop_rx = xuartps_stop_rx, /* Stop reception */ 740 .tx_empty = xuartps_tx_empty, /* Transmitter busy? */ 741 .break_ctl = xuartps_break_ctl, /* Start/stop 742 * transmitting break 743 */ 744 .set_termios = xuartps_set_termios, /* Set termios */ 745 .startup = xuartps_startup, /* App opens xuartps */ 746 .shutdown = xuartps_shutdown, /* App closes xuartps */ 747 .type = xuartps_type, /* Set UART type */ 748 .verify_port = xuartps_verify_port, /* Verification of port 749 * params 750 */ 751 .request_port = xuartps_request_port, /* Claim resources 752 * associated with a 753 * xuartps port 754 */ 755 .release_port = xuartps_release_port, /* Release resources 756 * associated with a 757 * xuartps port 758 */ 759 .config_port = xuartps_config_port, /* Configure when driver 760 * adds a xuartps port 761 */ 762 }; 763 764 static struct uart_port xuartps_port[2]; 765 766 /** 767 * xuartps_get_port - Configure the port from the platform device resource 768 * info 769 * 770 * Returns a pointer to a uart_port or NULL for failure 771 **/ 772 static struct uart_port *xuartps_get_port(void) 773 { 774 struct uart_port *port; 775 int id; 776 777 /* Find the next unused port */ 778 for (id = 0; id < XUARTPS_NR_PORTS; id++) 779 if (xuartps_port[id].mapbase == 0) 780 break; 781 782 if (id >= XUARTPS_NR_PORTS) 783 return NULL; 784 785 port = &xuartps_port[id]; 786 787 /* At this point, we've got an empty uart_port struct, initialize it */ 788 spin_lock_init(&port->lock); 789 port->membase = NULL; 790 port->iobase = 1; /* mark port in use */ 791 port->irq = 0; 792 port->type = PORT_UNKNOWN; 793 port->iotype = UPIO_MEM32; 794 port->flags = UPF_BOOT_AUTOCONF; 795 port->ops = &xuartps_ops; 796 port->fifosize = XUARTPS_FIFO_SIZE; 797 port->line = id; 798 port->dev = NULL; 799 return port; 800 } 801 802 /*-----------------------Console driver operations--------------------------*/ 803 804 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE 805 /** 806 * xuartps_console_wait_tx - Wait for the TX to be full 807 * @port: Handle to the uart port structure 808 * 809 **/ 810 static void xuartps_console_wait_tx(struct uart_port *port) 811 { 812 while ((xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_TXEMPTY) 813 != XUARTPS_SR_TXEMPTY) 814 barrier(); 815 } 816 817 /** 818 * xuartps_console_putchar - write the character to the FIFO buffer 819 * @port: Handle to the uart port structure 820 * @ch: Character to be written 821 * 822 **/ 823 static void xuartps_console_putchar(struct uart_port *port, int ch) 824 { 825 xuartps_console_wait_tx(port); 826 xuartps_writel(ch, XUARTPS_FIFO_OFFSET); 827 } 828 829 /** 830 * xuartps_console_write - perform write operation 831 * @port: Handle to the uart port structure 832 * @s: Pointer to character array 833 * @count: No of characters 834 **/ 835 static void xuartps_console_write(struct console *co, const char *s, 836 unsigned int count) 837 { 838 struct uart_port *port = &xuartps_port[co->index]; 839 unsigned long flags; 840 unsigned int imr; 841 int locked = 1; 842 843 if (oops_in_progress) 844 locked = spin_trylock_irqsave(&port->lock, flags); 845 else 846 spin_lock_irqsave(&port->lock, flags); 847 848 /* save and disable interrupt */ 849 imr = xuartps_readl(XUARTPS_IMR_OFFSET); 850 xuartps_writel(imr, XUARTPS_IDR_OFFSET); 851 852 uart_console_write(port, s, count, xuartps_console_putchar); 853 xuartps_console_wait_tx(port); 854 855 /* restore interrupt state, it seems like there may be a h/w bug 856 * in that the interrupt enable register should not need to be 857 * written based on the data sheet 858 */ 859 xuartps_writel(~imr, XUARTPS_IDR_OFFSET); 860 xuartps_writel(imr, XUARTPS_IER_OFFSET); 861 862 if (locked) 863 spin_unlock_irqrestore(&port->lock, flags); 864 } 865 866 /** 867 * xuartps_console_setup - Initialize the uart to default config 868 * @co: Console handle 869 * @options: Initial settings of uart 870 * 871 * Returns 0, -ENODEV if no device 872 **/ 873 static int __init xuartps_console_setup(struct console *co, char *options) 874 { 875 struct uart_port *port = &xuartps_port[co->index]; 876 int baud = 9600; 877 int bits = 8; 878 int parity = 'n'; 879 int flow = 'n'; 880 881 if (co->index < 0 || co->index >= XUARTPS_NR_PORTS) 882 return -EINVAL; 883 884 if (!port->mapbase) { 885 pr_debug("console on ttyPS%i not present\n", co->index); 886 return -ENODEV; 887 } 888 889 if (options) 890 uart_parse_options(options, &baud, &parity, &bits, &flow); 891 892 return uart_set_options(port, co, baud, parity, bits, flow); 893 } 894 895 static struct uart_driver xuartps_uart_driver; 896 897 static struct console xuartps_console = { 898 .name = XUARTPS_TTY_NAME, 899 .write = xuartps_console_write, 900 .device = uart_console_device, 901 .setup = xuartps_console_setup, 902 .flags = CON_PRINTBUFFER, 903 .index = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */ 904 .data = &xuartps_uart_driver, 905 }; 906 907 /** 908 * xuartps_console_init - Initialization call 909 * 910 * Returns 0 on success, negative error otherwise 911 **/ 912 static int __init xuartps_console_init(void) 913 { 914 register_console(&xuartps_console); 915 return 0; 916 } 917 918 console_initcall(xuartps_console_init); 919 920 #endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */ 921 922 /** Structure Definitions 923 */ 924 static struct uart_driver xuartps_uart_driver = { 925 .owner = THIS_MODULE, /* Owner */ 926 .driver_name = XUARTPS_NAME, /* Driver name */ 927 .dev_name = XUARTPS_TTY_NAME, /* Node name */ 928 .major = XUARTPS_MAJOR, /* Major number */ 929 .minor = XUARTPS_MINOR, /* Minor number */ 930 .nr = XUARTPS_NR_PORTS, /* Number of UART ports */ 931 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE 932 .cons = &xuartps_console, /* Console */ 933 #endif 934 }; 935 936 /* --------------------------------------------------------------------- 937 * Platform bus binding 938 */ 939 /** 940 * xuartps_probe - Platform driver probe 941 * @pdev: Pointer to the platform device structure 942 * 943 * Returns 0 on success, negative error otherwise 944 **/ 945 static int xuartps_probe(struct platform_device *pdev) 946 { 947 int rc; 948 struct uart_port *port; 949 struct resource *res, *res2; 950 struct xuartps *xuartps_data; 951 952 xuartps_data = kzalloc(sizeof(*xuartps_data), GFP_KERNEL); 953 if (!xuartps_data) 954 return -ENOMEM; 955 956 xuartps_data->aperclk = clk_get(&pdev->dev, "aper_clk"); 957 if (IS_ERR(xuartps_data->aperclk)) { 958 dev_err(&pdev->dev, "aper_clk clock not found.\n"); 959 rc = PTR_ERR(xuartps_data->aperclk); 960 goto err_out_free; 961 } 962 xuartps_data->refclk = clk_get(&pdev->dev, "ref_clk"); 963 if (IS_ERR(xuartps_data->refclk)) { 964 dev_err(&pdev->dev, "ref_clk clock not found.\n"); 965 rc = PTR_ERR(xuartps_data->refclk); 966 goto err_out_clk_put_aper; 967 } 968 969 rc = clk_prepare_enable(xuartps_data->aperclk); 970 if (rc) { 971 dev_err(&pdev->dev, "Unable to enable APER clock.\n"); 972 goto err_out_clk_put; 973 } 974 rc = clk_prepare_enable(xuartps_data->refclk); 975 if (rc) { 976 dev_err(&pdev->dev, "Unable to enable device clock.\n"); 977 goto err_out_clk_dis_aper; 978 } 979 980 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 981 if (!res) { 982 rc = -ENODEV; 983 goto err_out_clk_disable; 984 } 985 986 res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 987 if (!res2) { 988 rc = -ENODEV; 989 goto err_out_clk_disable; 990 } 991 992 /* Initialize the port structure */ 993 port = xuartps_get_port(); 994 995 if (!port) { 996 dev_err(&pdev->dev, "Cannot get uart_port structure\n"); 997 rc = -ENODEV; 998 goto err_out_clk_disable; 999 } else { 1000 /* Register the port. 1001 * This function also registers this device with the tty layer 1002 * and triggers invocation of the config_port() entry point. 1003 */ 1004 port->mapbase = res->start; 1005 port->irq = res2->start; 1006 port->dev = &pdev->dev; 1007 port->uartclk = clk_get_rate(xuartps_data->refclk); 1008 port->private_data = xuartps_data; 1009 platform_set_drvdata(pdev, port); 1010 rc = uart_add_one_port(&xuartps_uart_driver, port); 1011 if (rc) { 1012 dev_err(&pdev->dev, 1013 "uart_add_one_port() failed; err=%i\n", rc); 1014 goto err_out_clk_disable; 1015 } 1016 return 0; 1017 } 1018 1019 err_out_clk_disable: 1020 clk_disable_unprepare(xuartps_data->refclk); 1021 err_out_clk_dis_aper: 1022 clk_disable_unprepare(xuartps_data->aperclk); 1023 err_out_clk_put: 1024 clk_put(xuartps_data->refclk); 1025 err_out_clk_put_aper: 1026 clk_put(xuartps_data->aperclk); 1027 err_out_free: 1028 kfree(xuartps_data); 1029 1030 return rc; 1031 } 1032 1033 /** 1034 * xuartps_remove - called when the platform driver is unregistered 1035 * @pdev: Pointer to the platform device structure 1036 * 1037 * Returns 0 on success, negative error otherwise 1038 **/ 1039 static int xuartps_remove(struct platform_device *pdev) 1040 { 1041 struct uart_port *port = platform_get_drvdata(pdev); 1042 struct xuartps *xuartps_data = port->private_data; 1043 int rc; 1044 1045 /* Remove the xuartps port from the serial core */ 1046 rc = uart_remove_one_port(&xuartps_uart_driver, port); 1047 port->mapbase = 0; 1048 clk_disable_unprepare(xuartps_data->refclk); 1049 clk_disable_unprepare(xuartps_data->aperclk); 1050 clk_put(xuartps_data->refclk); 1051 clk_put(xuartps_data->aperclk); 1052 kfree(xuartps_data); 1053 return rc; 1054 } 1055 1056 /* Match table for of_platform binding */ 1057 static struct of_device_id xuartps_of_match[] = { 1058 { .compatible = "xlnx,xuartps", }, 1059 {} 1060 }; 1061 MODULE_DEVICE_TABLE(of, xuartps_of_match); 1062 1063 static struct platform_driver xuartps_platform_driver = { 1064 .probe = xuartps_probe, /* Probe method */ 1065 .remove = xuartps_remove, /* Detach method */ 1066 .driver = { 1067 .owner = THIS_MODULE, 1068 .name = XUARTPS_NAME, /* Driver name */ 1069 .of_match_table = xuartps_of_match, 1070 }, 1071 }; 1072 1073 /* --------------------------------------------------------------------- 1074 * Module Init and Exit 1075 */ 1076 /** 1077 * xuartps_init - Initial driver registration call 1078 * 1079 * Returns whether the registration was successful or not 1080 **/ 1081 static int __init xuartps_init(void) 1082 { 1083 int retval = 0; 1084 1085 /* Register the xuartps driver with the serial core */ 1086 retval = uart_register_driver(&xuartps_uart_driver); 1087 if (retval) 1088 return retval; 1089 1090 /* Register the platform driver */ 1091 retval = platform_driver_register(&xuartps_platform_driver); 1092 if (retval) 1093 uart_unregister_driver(&xuartps_uart_driver); 1094 1095 return retval; 1096 } 1097 1098 /** 1099 * xuartps_exit - Driver unregistration call 1100 **/ 1101 static void __exit xuartps_exit(void) 1102 { 1103 /* The order of unregistration is important. Unregister the 1104 * UART driver before the platform driver crashes the system. 1105 */ 1106 1107 /* Unregister the platform driver */ 1108 platform_driver_unregister(&xuartps_platform_driver); 1109 1110 /* Unregister the xuartps driver */ 1111 uart_unregister_driver(&xuartps_uart_driver); 1112 } 1113 1114 module_init(xuartps_init); 1115 module_exit(xuartps_exit); 1116 1117 MODULE_DESCRIPTION("Driver for PS UART"); 1118 MODULE_AUTHOR("Xilinx Inc."); 1119 MODULE_LICENSE("GPL"); 1120