1 /* 2 * Cadence UART driver (found in Xilinx Zynq) 3 * 4 * 2011 - 2014 (C) Xilinx Inc. 5 * 6 * This program is free software; you can redistribute it 7 * and/or modify it under the terms of the GNU General Public 8 * License as published by the Free Software Foundation; 9 * either version 2 of the License, or (at your option) any 10 * later version. 11 * 12 * This driver has originally been pushed by Xilinx using a Zynq-branding. This 13 * still shows in the naming of this file, the kconfig symbols and some symbols 14 * in the code. 15 */ 16 17 #if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 18 #define SUPPORT_SYSRQ 19 #endif 20 21 #include <linux/platform_device.h> 22 #include <linux/serial.h> 23 #include <linux/console.h> 24 #include <linux/serial_core.h> 25 #include <linux/slab.h> 26 #include <linux/tty.h> 27 #include <linux/tty_flip.h> 28 #include <linux/clk.h> 29 #include <linux/irq.h> 30 #include <linux/io.h> 31 #include <linux/of.h> 32 #include <linux/module.h> 33 #include <linux/pm_runtime.h> 34 35 #define CDNS_UART_TTY_NAME "ttyPS" 36 #define CDNS_UART_NAME "xuartps" 37 #define CDNS_UART_MAJOR 0 /* use dynamic node allocation */ 38 #define CDNS_UART_MINOR 0 /* works best with devtmpfs */ 39 #define CDNS_UART_NR_PORTS 2 40 #define CDNS_UART_FIFO_SIZE 64 /* FIFO size */ 41 #define CDNS_UART_REGISTER_SPACE 0x1000 42 43 /* Rx Trigger level */ 44 static int rx_trigger_level = 56; 45 module_param(rx_trigger_level, uint, S_IRUGO); 46 MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes"); 47 48 /* Rx Timeout */ 49 static int rx_timeout = 10; 50 module_param(rx_timeout, uint, S_IRUGO); 51 MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255"); 52 53 /* Register offsets for the UART. */ 54 #define CDNS_UART_CR 0x00 /* Control Register */ 55 #define CDNS_UART_MR 0x04 /* Mode Register */ 56 #define CDNS_UART_IER 0x08 /* Interrupt Enable */ 57 #define CDNS_UART_IDR 0x0C /* Interrupt Disable */ 58 #define CDNS_UART_IMR 0x10 /* Interrupt Mask */ 59 #define CDNS_UART_ISR 0x14 /* Interrupt Status */ 60 #define CDNS_UART_BAUDGEN 0x18 /* Baud Rate Generator */ 61 #define CDNS_UART_RXTOUT 0x1C /* RX Timeout */ 62 #define CDNS_UART_RXWM 0x20 /* RX FIFO Trigger Level */ 63 #define CDNS_UART_MODEMCR 0x24 /* Modem Control */ 64 #define CDNS_UART_MODEMSR 0x28 /* Modem Status */ 65 #define CDNS_UART_SR 0x2C /* Channel Status */ 66 #define CDNS_UART_FIFO 0x30 /* FIFO */ 67 #define CDNS_UART_BAUDDIV 0x34 /* Baud Rate Divider */ 68 #define CDNS_UART_FLOWDEL 0x38 /* Flow Delay */ 69 #define CDNS_UART_IRRX_PWIDTH 0x3C /* IR Min Received Pulse Width */ 70 #define CDNS_UART_IRTX_PWIDTH 0x40 /* IR Transmitted pulse Width */ 71 #define CDNS_UART_TXWM 0x44 /* TX FIFO Trigger Level */ 72 #define CDNS_UART_RXBS 0x48 /* RX FIFO byte status register */ 73 74 /* Control Register Bit Definitions */ 75 #define CDNS_UART_CR_STOPBRK 0x00000100 /* Stop TX break */ 76 #define CDNS_UART_CR_STARTBRK 0x00000080 /* Set TX break */ 77 #define CDNS_UART_CR_TX_DIS 0x00000020 /* TX disabled. */ 78 #define CDNS_UART_CR_TX_EN 0x00000010 /* TX enabled */ 79 #define CDNS_UART_CR_RX_DIS 0x00000008 /* RX disabled. */ 80 #define CDNS_UART_CR_RX_EN 0x00000004 /* RX enabled */ 81 #define CDNS_UART_CR_TXRST 0x00000002 /* TX logic reset */ 82 #define CDNS_UART_CR_RXRST 0x00000001 /* RX logic reset */ 83 #define CDNS_UART_CR_RST_TO 0x00000040 /* Restart Timeout Counter */ 84 #define CDNS_UART_RXBS_PARITY 0x00000001 /* Parity error status */ 85 #define CDNS_UART_RXBS_FRAMING 0x00000002 /* Framing error status */ 86 #define CDNS_UART_RXBS_BRK 0x00000004 /* Overrun error status */ 87 88 /* 89 * Mode Register: 90 * The mode register (MR) defines the mode of transfer as well as the data 91 * format. If this register is modified during transmission or reception, 92 * data validity cannot be guaranteed. 93 */ 94 #define CDNS_UART_MR_CLKSEL 0x00000001 /* Pre-scalar selection */ 95 #define CDNS_UART_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */ 96 #define CDNS_UART_MR_CHMODE_NORM 0x00000000 /* Normal mode */ 97 #define CDNS_UART_MR_CHMODE_MASK 0x00000300 /* Mask for mode bits */ 98 99 #define CDNS_UART_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */ 100 #define CDNS_UART_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */ 101 102 #define CDNS_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */ 103 #define CDNS_UART_MR_PARITY_MARK 0x00000018 /* Mark parity mode */ 104 #define CDNS_UART_MR_PARITY_SPACE 0x00000010 /* Space parity mode */ 105 #define CDNS_UART_MR_PARITY_ODD 0x00000008 /* Odd parity mode */ 106 #define CDNS_UART_MR_PARITY_EVEN 0x00000000 /* Even parity mode */ 107 108 #define CDNS_UART_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */ 109 #define CDNS_UART_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */ 110 #define CDNS_UART_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */ 111 112 /* 113 * Interrupt Registers: 114 * Interrupt control logic uses the interrupt enable register (IER) and the 115 * interrupt disable register (IDR) to set the value of the bits in the 116 * interrupt mask register (IMR). The IMR determines whether to pass an 117 * interrupt to the interrupt status register (ISR). 118 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an 119 * interrupt. IMR and ISR are read only, and IER and IDR are write only. 120 * Reading either IER or IDR returns 0x00. 121 * All four registers have the same bit definitions. 122 */ 123 #define CDNS_UART_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */ 124 #define CDNS_UART_IXR_PARITY 0x00000080 /* Parity error interrupt */ 125 #define CDNS_UART_IXR_FRAMING 0x00000040 /* Framing error interrupt */ 126 #define CDNS_UART_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */ 127 #define CDNS_UART_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */ 128 #define CDNS_UART_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */ 129 #define CDNS_UART_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */ 130 #define CDNS_UART_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */ 131 #define CDNS_UART_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */ 132 #define CDNS_UART_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */ 133 #define CDNS_UART_IXR_MASK 0x00001FFF /* Valid bit mask */ 134 135 /* 136 * Do not enable parity error interrupt for the following 137 * reason: When parity error interrupt is enabled, each Rx 138 * parity error always results in 2 events. The first one 139 * being parity error interrupt and the second one with a 140 * proper Rx interrupt with the incoming data. Disabling 141 * parity error interrupt ensures better handling of parity 142 * error events. With this change, for a parity error case, we 143 * get a Rx interrupt with parity error set in ISR register 144 * and we still handle parity errors in the desired way. 145 */ 146 147 #define CDNS_UART_RX_IRQS (CDNS_UART_IXR_FRAMING | \ 148 CDNS_UART_IXR_OVERRUN | \ 149 CDNS_UART_IXR_RXTRIG | \ 150 CDNS_UART_IXR_TOUT) 151 152 /* Goes in read_status_mask for break detection as the HW doesn't do it*/ 153 #define CDNS_UART_IXR_BRK 0x00002000 154 155 #define CDNS_UART_RXBS_SUPPORT BIT(1) 156 /* 157 * Modem Control register: 158 * The read/write Modem Control register controls the interface with the modem 159 * or data set, or a peripheral device emulating a modem. 160 */ 161 #define CDNS_UART_MODEMCR_FCM 0x00000020 /* Automatic flow control mode */ 162 #define CDNS_UART_MODEMCR_RTS 0x00000002 /* Request to send output control */ 163 #define CDNS_UART_MODEMCR_DTR 0x00000001 /* Data Terminal Ready */ 164 165 /* 166 * Channel Status Register: 167 * The channel status register (CSR) is provided to enable the control logic 168 * to monitor the status of bits in the channel interrupt status register, 169 * even if these are masked out by the interrupt mask register. 170 */ 171 #define CDNS_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */ 172 #define CDNS_UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */ 173 #define CDNS_UART_SR_TXFULL 0x00000010 /* TX FIFO full */ 174 #define CDNS_UART_SR_RXTRIG 0x00000001 /* Rx Trigger */ 175 176 /* baud dividers min/max values */ 177 #define CDNS_UART_BDIV_MIN 4 178 #define CDNS_UART_BDIV_MAX 255 179 #define CDNS_UART_CD_MAX 65535 180 #define UART_AUTOSUSPEND_TIMEOUT 3000 181 182 /** 183 * struct cdns_uart - device data 184 * @port: Pointer to the UART port 185 * @uartclk: Reference clock 186 * @pclk: APB clock 187 * @baud: Current baud rate 188 * @clk_rate_change_nb: Notifier block for clock changes 189 * @quirks: Flags for RXBS support. 190 */ 191 struct cdns_uart { 192 struct uart_port *port; 193 struct clk *uartclk; 194 struct clk *pclk; 195 unsigned int baud; 196 struct notifier_block clk_rate_change_nb; 197 u32 quirks; 198 }; 199 struct cdns_platform_data { 200 u32 quirks; 201 }; 202 #define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \ 203 clk_rate_change_nb); 204 205 /** 206 * cdns_uart_handle_rx - Handle the received bytes along with Rx errors. 207 * @dev_id: Id of the UART port 208 * @isrstatus: The interrupt status register value as read 209 * Return: None 210 */ 211 static void cdns_uart_handle_rx(void *dev_id, unsigned int isrstatus) 212 { 213 struct uart_port *port = (struct uart_port *)dev_id; 214 struct cdns_uart *cdns_uart = port->private_data; 215 unsigned int data; 216 unsigned int rxbs_status = 0; 217 unsigned int status_mask; 218 unsigned int framerrprocessed = 0; 219 char status = TTY_NORMAL; 220 bool is_rxbs_support; 221 222 is_rxbs_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT; 223 224 while ((readl(port->membase + CDNS_UART_SR) & 225 CDNS_UART_SR_RXEMPTY) != CDNS_UART_SR_RXEMPTY) { 226 if (is_rxbs_support) 227 rxbs_status = readl(port->membase + CDNS_UART_RXBS); 228 data = readl(port->membase + CDNS_UART_FIFO); 229 port->icount.rx++; 230 /* 231 * There is no hardware break detection in Zynq, so we interpret 232 * framing error with all-zeros data as a break sequence. 233 * Most of the time, there's another non-zero byte at the 234 * end of the sequence. 235 */ 236 if (!is_rxbs_support && (isrstatus & CDNS_UART_IXR_FRAMING)) { 237 if (!data) { 238 port->read_status_mask |= CDNS_UART_IXR_BRK; 239 framerrprocessed = 1; 240 continue; 241 } 242 } 243 if (is_rxbs_support && (rxbs_status & CDNS_UART_RXBS_BRK)) { 244 port->icount.brk++; 245 status = TTY_BREAK; 246 if (uart_handle_break(port)) 247 continue; 248 } 249 250 isrstatus &= port->read_status_mask; 251 isrstatus &= ~port->ignore_status_mask; 252 status_mask = port->read_status_mask; 253 status_mask &= ~port->ignore_status_mask; 254 255 if (data && 256 (port->read_status_mask & CDNS_UART_IXR_BRK)) { 257 port->read_status_mask &= ~CDNS_UART_IXR_BRK; 258 port->icount.brk++; 259 if (uart_handle_break(port)) 260 continue; 261 } 262 263 if (uart_handle_sysrq_char(port, data)) 264 continue; 265 266 if (is_rxbs_support) { 267 if ((rxbs_status & CDNS_UART_RXBS_PARITY) 268 && (status_mask & CDNS_UART_IXR_PARITY)) { 269 port->icount.parity++; 270 status = TTY_PARITY; 271 } 272 if ((rxbs_status & CDNS_UART_RXBS_FRAMING) 273 && (status_mask & CDNS_UART_IXR_PARITY)) { 274 port->icount.frame++; 275 status = TTY_FRAME; 276 } 277 } else { 278 if (isrstatus & CDNS_UART_IXR_PARITY) { 279 port->icount.parity++; 280 status = TTY_PARITY; 281 } 282 if ((isrstatus & CDNS_UART_IXR_FRAMING) && 283 !framerrprocessed) { 284 port->icount.frame++; 285 status = TTY_FRAME; 286 } 287 } 288 if (isrstatus & CDNS_UART_IXR_OVERRUN) { 289 port->icount.overrun++; 290 tty_insert_flip_char(&port->state->port, 0, 291 TTY_OVERRUN); 292 } 293 tty_insert_flip_char(&port->state->port, data, status); 294 isrstatus = 0; 295 } 296 spin_unlock(&port->lock); 297 tty_flip_buffer_push(&port->state->port); 298 spin_lock(&port->lock); 299 } 300 301 /** 302 * cdns_uart_handle_tx - Handle the bytes to be Txed. 303 * @dev_id: Id of the UART port 304 * Return: None 305 */ 306 static void cdns_uart_handle_tx(void *dev_id) 307 { 308 struct uart_port *port = (struct uart_port *)dev_id; 309 unsigned int numbytes; 310 311 if (uart_circ_empty(&port->state->xmit)) { 312 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR); 313 } else { 314 numbytes = port->fifosize; 315 while (numbytes && !uart_circ_empty(&port->state->xmit) && 316 !(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL)) { 317 /* 318 * Get the data from the UART circular buffer 319 * and write it to the cdns_uart's TX_FIFO 320 * register. 321 */ 322 writel( 323 port->state->xmit.buf[port->state->xmit. 324 tail], port->membase + CDNS_UART_FIFO); 325 326 port->icount.tx++; 327 328 /* 329 * Adjust the tail of the UART buffer and wrap 330 * the buffer if it reaches limit. 331 */ 332 port->state->xmit.tail = 333 (port->state->xmit.tail + 1) & 334 (UART_XMIT_SIZE - 1); 335 336 numbytes--; 337 } 338 339 if (uart_circ_chars_pending( 340 &port->state->xmit) < WAKEUP_CHARS) 341 uart_write_wakeup(port); 342 } 343 } 344 345 /** 346 * cdns_uart_isr - Interrupt handler 347 * @irq: Irq number 348 * @dev_id: Id of the port 349 * 350 * Return: IRQHANDLED 351 */ 352 static irqreturn_t cdns_uart_isr(int irq, void *dev_id) 353 { 354 struct uart_port *port = (struct uart_port *)dev_id; 355 unsigned int isrstatus; 356 357 spin_lock(&port->lock); 358 359 /* Read the interrupt status register to determine which 360 * interrupt(s) is/are active and clear them. 361 */ 362 isrstatus = readl(port->membase + CDNS_UART_ISR); 363 writel(isrstatus, port->membase + CDNS_UART_ISR); 364 365 if (isrstatus & CDNS_UART_IXR_TXEMPTY) { 366 cdns_uart_handle_tx(dev_id); 367 isrstatus &= ~CDNS_UART_IXR_TXEMPTY; 368 } 369 if (isrstatus & CDNS_UART_IXR_MASK) 370 cdns_uart_handle_rx(dev_id, isrstatus); 371 372 spin_unlock(&port->lock); 373 return IRQ_HANDLED; 374 } 375 376 /** 377 * cdns_uart_calc_baud_divs - Calculate baud rate divisors 378 * @clk: UART module input clock 379 * @baud: Desired baud rate 380 * @rbdiv: BDIV value (return value) 381 * @rcd: CD value (return value) 382 * @div8: Value for clk_sel bit in mod (return value) 383 * Return: baud rate, requested baud when possible, or actual baud when there 384 * was too much error, zero if no valid divisors are found. 385 * 386 * Formula to obtain baud rate is 387 * baud_tx/rx rate = clk/CD * (BDIV + 1) 388 * input_clk = (Uart User Defined Clock or Apb Clock) 389 * depends on UCLKEN in MR Reg 390 * clk = input_clk or input_clk/8; 391 * depends on CLKS in MR reg 392 * CD and BDIV depends on values in 393 * baud rate generate register 394 * baud rate clock divisor register 395 */ 396 static unsigned int cdns_uart_calc_baud_divs(unsigned int clk, 397 unsigned int baud, u32 *rbdiv, u32 *rcd, int *div8) 398 { 399 u32 cd, bdiv; 400 unsigned int calc_baud; 401 unsigned int bestbaud = 0; 402 unsigned int bauderror; 403 unsigned int besterror = ~0; 404 405 if (baud < clk / ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX)) { 406 *div8 = 1; 407 clk /= 8; 408 } else { 409 *div8 = 0; 410 } 411 412 for (bdiv = CDNS_UART_BDIV_MIN; bdiv <= CDNS_UART_BDIV_MAX; bdiv++) { 413 cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1)); 414 if (cd < 1 || cd > CDNS_UART_CD_MAX) 415 continue; 416 417 calc_baud = clk / (cd * (bdiv + 1)); 418 419 if (baud > calc_baud) 420 bauderror = baud - calc_baud; 421 else 422 bauderror = calc_baud - baud; 423 424 if (besterror > bauderror) { 425 *rbdiv = bdiv; 426 *rcd = cd; 427 bestbaud = calc_baud; 428 besterror = bauderror; 429 } 430 } 431 /* use the values when percent error is acceptable */ 432 if (((besterror * 100) / baud) < 3) 433 bestbaud = baud; 434 435 return bestbaud; 436 } 437 438 /** 439 * cdns_uart_set_baud_rate - Calculate and set the baud rate 440 * @port: Handle to the uart port structure 441 * @baud: Baud rate to set 442 * Return: baud rate, requested baud when possible, or actual baud when there 443 * was too much error, zero if no valid divisors are found. 444 */ 445 static unsigned int cdns_uart_set_baud_rate(struct uart_port *port, 446 unsigned int baud) 447 { 448 unsigned int calc_baud; 449 u32 cd = 0, bdiv = 0; 450 u32 mreg; 451 int div8; 452 struct cdns_uart *cdns_uart = port->private_data; 453 454 calc_baud = cdns_uart_calc_baud_divs(port->uartclk, baud, &bdiv, &cd, 455 &div8); 456 457 /* Write new divisors to hardware */ 458 mreg = readl(port->membase + CDNS_UART_MR); 459 if (div8) 460 mreg |= CDNS_UART_MR_CLKSEL; 461 else 462 mreg &= ~CDNS_UART_MR_CLKSEL; 463 writel(mreg, port->membase + CDNS_UART_MR); 464 writel(cd, port->membase + CDNS_UART_BAUDGEN); 465 writel(bdiv, port->membase + CDNS_UART_BAUDDIV); 466 cdns_uart->baud = baud; 467 468 return calc_baud; 469 } 470 471 #ifdef CONFIG_COMMON_CLK 472 /** 473 * cdns_uart_clk_notitifer_cb - Clock notifier callback 474 * @nb: Notifier block 475 * @event: Notify event 476 * @data: Notifier data 477 * Return: NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error. 478 */ 479 static int cdns_uart_clk_notifier_cb(struct notifier_block *nb, 480 unsigned long event, void *data) 481 { 482 u32 ctrl_reg; 483 struct uart_port *port; 484 int locked = 0; 485 struct clk_notifier_data *ndata = data; 486 unsigned long flags = 0; 487 struct cdns_uart *cdns_uart = to_cdns_uart(nb); 488 489 port = cdns_uart->port; 490 if (port->suspended) 491 return NOTIFY_OK; 492 493 switch (event) { 494 case PRE_RATE_CHANGE: 495 { 496 u32 bdiv, cd; 497 int div8; 498 499 /* 500 * Find out if current baud-rate can be achieved with new clock 501 * frequency. 502 */ 503 if (!cdns_uart_calc_baud_divs(ndata->new_rate, cdns_uart->baud, 504 &bdiv, &cd, &div8)) { 505 dev_warn(port->dev, "clock rate change rejected\n"); 506 return NOTIFY_BAD; 507 } 508 509 spin_lock_irqsave(&cdns_uart->port->lock, flags); 510 511 /* Disable the TX and RX to set baud rate */ 512 ctrl_reg = readl(port->membase + CDNS_UART_CR); 513 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS; 514 writel(ctrl_reg, port->membase + CDNS_UART_CR); 515 516 spin_unlock_irqrestore(&cdns_uart->port->lock, flags); 517 518 return NOTIFY_OK; 519 } 520 case POST_RATE_CHANGE: 521 /* 522 * Set clk dividers to generate correct baud with new clock 523 * frequency. 524 */ 525 526 spin_lock_irqsave(&cdns_uart->port->lock, flags); 527 528 locked = 1; 529 port->uartclk = ndata->new_rate; 530 531 cdns_uart->baud = cdns_uart_set_baud_rate(cdns_uart->port, 532 cdns_uart->baud); 533 /* fall through */ 534 case ABORT_RATE_CHANGE: 535 if (!locked) 536 spin_lock_irqsave(&cdns_uart->port->lock, flags); 537 538 /* Set TX/RX Reset */ 539 ctrl_reg = readl(port->membase + CDNS_UART_CR); 540 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST; 541 writel(ctrl_reg, port->membase + CDNS_UART_CR); 542 543 while (readl(port->membase + CDNS_UART_CR) & 544 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST)) 545 cpu_relax(); 546 547 /* 548 * Clear the RX disable and TX disable bits and then set the TX 549 * enable bit and RX enable bit to enable the transmitter and 550 * receiver. 551 */ 552 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT); 553 ctrl_reg = readl(port->membase + CDNS_UART_CR); 554 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS); 555 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN; 556 writel(ctrl_reg, port->membase + CDNS_UART_CR); 557 558 spin_unlock_irqrestore(&cdns_uart->port->lock, flags); 559 560 return NOTIFY_OK; 561 default: 562 return NOTIFY_DONE; 563 } 564 } 565 #endif 566 567 /** 568 * cdns_uart_start_tx - Start transmitting bytes 569 * @port: Handle to the uart port structure 570 */ 571 static void cdns_uart_start_tx(struct uart_port *port) 572 { 573 unsigned int status; 574 575 if (uart_tx_stopped(port)) 576 return; 577 578 /* 579 * Set the TX enable bit and clear the TX disable bit to enable the 580 * transmitter. 581 */ 582 status = readl(port->membase + CDNS_UART_CR); 583 status &= ~CDNS_UART_CR_TX_DIS; 584 status |= CDNS_UART_CR_TX_EN; 585 writel(status, port->membase + CDNS_UART_CR); 586 587 if (uart_circ_empty(&port->state->xmit)) 588 return; 589 590 cdns_uart_handle_tx(port); 591 592 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR); 593 /* Enable the TX Empty interrupt */ 594 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IER); 595 } 596 597 /** 598 * cdns_uart_stop_tx - Stop TX 599 * @port: Handle to the uart port structure 600 */ 601 static void cdns_uart_stop_tx(struct uart_port *port) 602 { 603 unsigned int regval; 604 605 regval = readl(port->membase + CDNS_UART_CR); 606 regval |= CDNS_UART_CR_TX_DIS; 607 /* Disable the transmitter */ 608 writel(regval, port->membase + CDNS_UART_CR); 609 } 610 611 /** 612 * cdns_uart_stop_rx - Stop RX 613 * @port: Handle to the uart port structure 614 */ 615 static void cdns_uart_stop_rx(struct uart_port *port) 616 { 617 unsigned int regval; 618 619 /* Disable RX IRQs */ 620 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IDR); 621 622 /* Disable the receiver */ 623 regval = readl(port->membase + CDNS_UART_CR); 624 regval |= CDNS_UART_CR_RX_DIS; 625 writel(regval, port->membase + CDNS_UART_CR); 626 } 627 628 /** 629 * cdns_uart_tx_empty - Check whether TX is empty 630 * @port: Handle to the uart port structure 631 * 632 * Return: TIOCSER_TEMT on success, 0 otherwise 633 */ 634 static unsigned int cdns_uart_tx_empty(struct uart_port *port) 635 { 636 unsigned int status; 637 638 status = readl(port->membase + CDNS_UART_SR) & 639 CDNS_UART_SR_TXEMPTY; 640 return status ? TIOCSER_TEMT : 0; 641 } 642 643 /** 644 * cdns_uart_break_ctl - Based on the input ctl we have to start or stop 645 * transmitting char breaks 646 * @port: Handle to the uart port structure 647 * @ctl: Value based on which start or stop decision is taken 648 */ 649 static void cdns_uart_break_ctl(struct uart_port *port, int ctl) 650 { 651 unsigned int status; 652 unsigned long flags; 653 654 spin_lock_irqsave(&port->lock, flags); 655 656 status = readl(port->membase + CDNS_UART_CR); 657 658 if (ctl == -1) 659 writel(CDNS_UART_CR_STARTBRK | status, 660 port->membase + CDNS_UART_CR); 661 else { 662 if ((status & CDNS_UART_CR_STOPBRK) == 0) 663 writel(CDNS_UART_CR_STOPBRK | status, 664 port->membase + CDNS_UART_CR); 665 } 666 spin_unlock_irqrestore(&port->lock, flags); 667 } 668 669 /** 670 * cdns_uart_set_termios - termios operations, handling data length, parity, 671 * stop bits, flow control, baud rate 672 * @port: Handle to the uart port structure 673 * @termios: Handle to the input termios structure 674 * @old: Values of the previously saved termios structure 675 */ 676 static void cdns_uart_set_termios(struct uart_port *port, 677 struct ktermios *termios, struct ktermios *old) 678 { 679 unsigned int cval = 0; 680 unsigned int baud, minbaud, maxbaud; 681 unsigned long flags; 682 unsigned int ctrl_reg, mode_reg; 683 684 spin_lock_irqsave(&port->lock, flags); 685 686 /* Wait for the transmit FIFO to empty before making changes */ 687 if (!(readl(port->membase + CDNS_UART_CR) & 688 CDNS_UART_CR_TX_DIS)) { 689 while (!(readl(port->membase + CDNS_UART_SR) & 690 CDNS_UART_SR_TXEMPTY)) { 691 cpu_relax(); 692 } 693 } 694 695 /* Disable the TX and RX to set baud rate */ 696 ctrl_reg = readl(port->membase + CDNS_UART_CR); 697 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS; 698 writel(ctrl_reg, port->membase + CDNS_UART_CR); 699 700 /* 701 * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk 702 * min and max baud should be calculated here based on port->uartclk. 703 * this way we get a valid baud and can safely call set_baud() 704 */ 705 minbaud = port->uartclk / 706 ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX * 8); 707 maxbaud = port->uartclk / (CDNS_UART_BDIV_MIN + 1); 708 baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud); 709 baud = cdns_uart_set_baud_rate(port, baud); 710 if (tty_termios_baud_rate(termios)) 711 tty_termios_encode_baud_rate(termios, baud, baud); 712 713 /* Update the per-port timeout. */ 714 uart_update_timeout(port, termios->c_cflag, baud); 715 716 /* Set TX/RX Reset */ 717 ctrl_reg = readl(port->membase + CDNS_UART_CR); 718 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST; 719 writel(ctrl_reg, port->membase + CDNS_UART_CR); 720 721 while (readl(port->membase + CDNS_UART_CR) & 722 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST)) 723 cpu_relax(); 724 725 /* 726 * Clear the RX disable and TX disable bits and then set the TX enable 727 * bit and RX enable bit to enable the transmitter and receiver. 728 */ 729 ctrl_reg = readl(port->membase + CDNS_UART_CR); 730 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS); 731 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN; 732 writel(ctrl_reg, port->membase + CDNS_UART_CR); 733 734 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT); 735 736 port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG | 737 CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT; 738 port->ignore_status_mask = 0; 739 740 if (termios->c_iflag & INPCK) 741 port->read_status_mask |= CDNS_UART_IXR_PARITY | 742 CDNS_UART_IXR_FRAMING; 743 744 if (termios->c_iflag & IGNPAR) 745 port->ignore_status_mask |= CDNS_UART_IXR_PARITY | 746 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN; 747 748 /* ignore all characters if CREAD is not set */ 749 if ((termios->c_cflag & CREAD) == 0) 750 port->ignore_status_mask |= CDNS_UART_IXR_RXTRIG | 751 CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY | 752 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN; 753 754 mode_reg = readl(port->membase + CDNS_UART_MR); 755 756 /* Handling Data Size */ 757 switch (termios->c_cflag & CSIZE) { 758 case CS6: 759 cval |= CDNS_UART_MR_CHARLEN_6_BIT; 760 break; 761 case CS7: 762 cval |= CDNS_UART_MR_CHARLEN_7_BIT; 763 break; 764 default: 765 case CS8: 766 cval |= CDNS_UART_MR_CHARLEN_8_BIT; 767 termios->c_cflag &= ~CSIZE; 768 termios->c_cflag |= CS8; 769 break; 770 } 771 772 /* Handling Parity and Stop Bits length */ 773 if (termios->c_cflag & CSTOPB) 774 cval |= CDNS_UART_MR_STOPMODE_2_BIT; /* 2 STOP bits */ 775 else 776 cval |= CDNS_UART_MR_STOPMODE_1_BIT; /* 1 STOP bit */ 777 778 if (termios->c_cflag & PARENB) { 779 /* Mark or Space parity */ 780 if (termios->c_cflag & CMSPAR) { 781 if (termios->c_cflag & PARODD) 782 cval |= CDNS_UART_MR_PARITY_MARK; 783 else 784 cval |= CDNS_UART_MR_PARITY_SPACE; 785 } else { 786 if (termios->c_cflag & PARODD) 787 cval |= CDNS_UART_MR_PARITY_ODD; 788 else 789 cval |= CDNS_UART_MR_PARITY_EVEN; 790 } 791 } else { 792 cval |= CDNS_UART_MR_PARITY_NONE; 793 } 794 cval |= mode_reg & 1; 795 writel(cval, port->membase + CDNS_UART_MR); 796 797 spin_unlock_irqrestore(&port->lock, flags); 798 } 799 800 /** 801 * cdns_uart_startup - Called when an application opens a cdns_uart port 802 * @port: Handle to the uart port structure 803 * 804 * Return: 0 on success, negative errno otherwise 805 */ 806 static int cdns_uart_startup(struct uart_port *port) 807 { 808 struct cdns_uart *cdns_uart = port->private_data; 809 bool is_brk_support; 810 int ret; 811 unsigned long flags; 812 unsigned int status = 0; 813 814 is_brk_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT; 815 816 spin_lock_irqsave(&port->lock, flags); 817 818 /* Disable the TX and RX */ 819 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS, 820 port->membase + CDNS_UART_CR); 821 822 /* Set the Control Register with TX/RX Enable, TX/RX Reset, 823 * no break chars. 824 */ 825 writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST, 826 port->membase + CDNS_UART_CR); 827 828 while (readl(port->membase + CDNS_UART_CR) & 829 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST)) 830 cpu_relax(); 831 832 /* 833 * Clear the RX disable bit and then set the RX enable bit to enable 834 * the receiver. 835 */ 836 status = readl(port->membase + CDNS_UART_CR); 837 status &= CDNS_UART_CR_RX_DIS; 838 status |= CDNS_UART_CR_RX_EN; 839 writel(status, port->membase + CDNS_UART_CR); 840 841 /* Set the Mode Register with normal mode,8 data bits,1 stop bit, 842 * no parity. 843 */ 844 writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT 845 | CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT, 846 port->membase + CDNS_UART_MR); 847 848 /* 849 * Set the RX FIFO Trigger level to use most of the FIFO, but it 850 * can be tuned with a module parameter 851 */ 852 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM); 853 854 /* 855 * Receive Timeout register is enabled but it 856 * can be tuned with a module parameter 857 */ 858 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT); 859 860 /* Clear out any pending interrupts before enabling them */ 861 writel(readl(port->membase + CDNS_UART_ISR), 862 port->membase + CDNS_UART_ISR); 863 864 spin_unlock_irqrestore(&port->lock, flags); 865 866 ret = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME, port); 867 if (ret) { 868 dev_err(port->dev, "request_irq '%d' failed with %d\n", 869 port->irq, ret); 870 return ret; 871 } 872 873 /* Set the Interrupt Registers with desired interrupts */ 874 if (is_brk_support) 875 writel(CDNS_UART_RX_IRQS | CDNS_UART_IXR_BRK, 876 port->membase + CDNS_UART_IER); 877 else 878 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IER); 879 880 return 0; 881 } 882 883 /** 884 * cdns_uart_shutdown - Called when an application closes a cdns_uart port 885 * @port: Handle to the uart port structure 886 */ 887 static void cdns_uart_shutdown(struct uart_port *port) 888 { 889 int status; 890 unsigned long flags; 891 892 spin_lock_irqsave(&port->lock, flags); 893 894 /* Disable interrupts */ 895 status = readl(port->membase + CDNS_UART_IMR); 896 writel(status, port->membase + CDNS_UART_IDR); 897 writel(0xffffffff, port->membase + CDNS_UART_ISR); 898 899 /* Disable the TX and RX */ 900 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS, 901 port->membase + CDNS_UART_CR); 902 903 spin_unlock_irqrestore(&port->lock, flags); 904 905 free_irq(port->irq, port); 906 } 907 908 /** 909 * cdns_uart_type - Set UART type to cdns_uart port 910 * @port: Handle to the uart port structure 911 * 912 * Return: string on success, NULL otherwise 913 */ 914 static const char *cdns_uart_type(struct uart_port *port) 915 { 916 return port->type == PORT_XUARTPS ? CDNS_UART_NAME : NULL; 917 } 918 919 /** 920 * cdns_uart_verify_port - Verify the port params 921 * @port: Handle to the uart port structure 922 * @ser: Handle to the structure whose members are compared 923 * 924 * Return: 0 on success, negative errno otherwise. 925 */ 926 static int cdns_uart_verify_port(struct uart_port *port, 927 struct serial_struct *ser) 928 { 929 if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS) 930 return -EINVAL; 931 if (port->irq != ser->irq) 932 return -EINVAL; 933 if (ser->io_type != UPIO_MEM) 934 return -EINVAL; 935 if (port->iobase != ser->port) 936 return -EINVAL; 937 if (ser->hub6 != 0) 938 return -EINVAL; 939 return 0; 940 } 941 942 /** 943 * cdns_uart_request_port - Claim the memory region attached to cdns_uart port, 944 * called when the driver adds a cdns_uart port via 945 * uart_add_one_port() 946 * @port: Handle to the uart port structure 947 * 948 * Return: 0 on success, negative errno otherwise. 949 */ 950 static int cdns_uart_request_port(struct uart_port *port) 951 { 952 if (!request_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE, 953 CDNS_UART_NAME)) { 954 return -ENOMEM; 955 } 956 957 port->membase = ioremap(port->mapbase, CDNS_UART_REGISTER_SPACE); 958 if (!port->membase) { 959 dev_err(port->dev, "Unable to map registers\n"); 960 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE); 961 return -ENOMEM; 962 } 963 return 0; 964 } 965 966 /** 967 * cdns_uart_release_port - Release UART port 968 * @port: Handle to the uart port structure 969 * 970 * Release the memory region attached to a cdns_uart port. Called when the 971 * driver removes a cdns_uart port via uart_remove_one_port(). 972 */ 973 static void cdns_uart_release_port(struct uart_port *port) 974 { 975 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE); 976 iounmap(port->membase); 977 port->membase = NULL; 978 } 979 980 /** 981 * cdns_uart_config_port - Configure UART port 982 * @port: Handle to the uart port structure 983 * @flags: If any 984 */ 985 static void cdns_uart_config_port(struct uart_port *port, int flags) 986 { 987 if (flags & UART_CONFIG_TYPE && cdns_uart_request_port(port) == 0) 988 port->type = PORT_XUARTPS; 989 } 990 991 /** 992 * cdns_uart_get_mctrl - Get the modem control state 993 * @port: Handle to the uart port structure 994 * 995 * Return: the modem control state 996 */ 997 static unsigned int cdns_uart_get_mctrl(struct uart_port *port) 998 { 999 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; 1000 } 1001 1002 static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 1003 { 1004 u32 val; 1005 u32 mode_reg; 1006 1007 val = readl(port->membase + CDNS_UART_MODEMCR); 1008 mode_reg = readl(port->membase + CDNS_UART_MR); 1009 1010 val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR); 1011 mode_reg &= ~CDNS_UART_MR_CHMODE_MASK; 1012 1013 if (mctrl & TIOCM_RTS) 1014 val |= CDNS_UART_MODEMCR_RTS; 1015 if (mctrl & TIOCM_DTR) 1016 val |= CDNS_UART_MODEMCR_DTR; 1017 if (mctrl & TIOCM_LOOP) 1018 mode_reg |= CDNS_UART_MR_CHMODE_L_LOOP; 1019 else 1020 mode_reg |= CDNS_UART_MR_CHMODE_NORM; 1021 1022 writel(val, port->membase + CDNS_UART_MODEMCR); 1023 writel(mode_reg, port->membase + CDNS_UART_MR); 1024 } 1025 1026 #ifdef CONFIG_CONSOLE_POLL 1027 static int cdns_uart_poll_get_char(struct uart_port *port) 1028 { 1029 int c; 1030 unsigned long flags; 1031 1032 spin_lock_irqsave(&port->lock, flags); 1033 1034 /* Check if FIFO is empty */ 1035 if (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_RXEMPTY) 1036 c = NO_POLL_CHAR; 1037 else /* Read a character */ 1038 c = (unsigned char) readl(port->membase + CDNS_UART_FIFO); 1039 1040 spin_unlock_irqrestore(&port->lock, flags); 1041 1042 return c; 1043 } 1044 1045 static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c) 1046 { 1047 unsigned long flags; 1048 1049 spin_lock_irqsave(&port->lock, flags); 1050 1051 /* Wait until FIFO is empty */ 1052 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY)) 1053 cpu_relax(); 1054 1055 /* Write a character */ 1056 writel(c, port->membase + CDNS_UART_FIFO); 1057 1058 /* Wait until FIFO is empty */ 1059 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY)) 1060 cpu_relax(); 1061 1062 spin_unlock_irqrestore(&port->lock, flags); 1063 1064 return; 1065 } 1066 #endif 1067 1068 static void cdns_uart_pm(struct uart_port *port, unsigned int state, 1069 unsigned int oldstate) 1070 { 1071 switch (state) { 1072 case UART_PM_STATE_OFF: 1073 pm_runtime_mark_last_busy(port->dev); 1074 pm_runtime_put_autosuspend(port->dev); 1075 break; 1076 default: 1077 pm_runtime_get_sync(port->dev); 1078 break; 1079 } 1080 } 1081 1082 static const struct uart_ops cdns_uart_ops = { 1083 .set_mctrl = cdns_uart_set_mctrl, 1084 .get_mctrl = cdns_uart_get_mctrl, 1085 .start_tx = cdns_uart_start_tx, 1086 .stop_tx = cdns_uart_stop_tx, 1087 .stop_rx = cdns_uart_stop_rx, 1088 .tx_empty = cdns_uart_tx_empty, 1089 .break_ctl = cdns_uart_break_ctl, 1090 .set_termios = cdns_uart_set_termios, 1091 .startup = cdns_uart_startup, 1092 .shutdown = cdns_uart_shutdown, 1093 .pm = cdns_uart_pm, 1094 .type = cdns_uart_type, 1095 .verify_port = cdns_uart_verify_port, 1096 .request_port = cdns_uart_request_port, 1097 .release_port = cdns_uart_release_port, 1098 .config_port = cdns_uart_config_port, 1099 #ifdef CONFIG_CONSOLE_POLL 1100 .poll_get_char = cdns_uart_poll_get_char, 1101 .poll_put_char = cdns_uart_poll_put_char, 1102 #endif 1103 }; 1104 1105 static struct uart_port cdns_uart_port[CDNS_UART_NR_PORTS]; 1106 1107 /** 1108 * cdns_uart_get_port - Configure the port from platform device resource info 1109 * @id: Port id 1110 * 1111 * Return: a pointer to a uart_port or NULL for failure 1112 */ 1113 static struct uart_port *cdns_uart_get_port(int id) 1114 { 1115 struct uart_port *port; 1116 1117 /* Try the given port id if failed use default method */ 1118 if (cdns_uart_port[id].mapbase != 0) { 1119 /* Find the next unused port */ 1120 for (id = 0; id < CDNS_UART_NR_PORTS; id++) 1121 if (cdns_uart_port[id].mapbase == 0) 1122 break; 1123 } 1124 1125 if (id >= CDNS_UART_NR_PORTS) 1126 return NULL; 1127 1128 port = &cdns_uart_port[id]; 1129 1130 /* At this point, we've got an empty uart_port struct, initialize it */ 1131 spin_lock_init(&port->lock); 1132 port->membase = NULL; 1133 port->irq = 0; 1134 port->type = PORT_UNKNOWN; 1135 port->iotype = UPIO_MEM32; 1136 port->flags = UPF_BOOT_AUTOCONF; 1137 port->ops = &cdns_uart_ops; 1138 port->fifosize = CDNS_UART_FIFO_SIZE; 1139 port->line = id; 1140 port->dev = NULL; 1141 return port; 1142 } 1143 1144 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE 1145 /** 1146 * cdns_uart_console_wait_tx - Wait for the TX to be full 1147 * @port: Handle to the uart port structure 1148 */ 1149 static void cdns_uart_console_wait_tx(struct uart_port *port) 1150 { 1151 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY)) 1152 barrier(); 1153 } 1154 1155 /** 1156 * cdns_uart_console_putchar - write the character to the FIFO buffer 1157 * @port: Handle to the uart port structure 1158 * @ch: Character to be written 1159 */ 1160 static void cdns_uart_console_putchar(struct uart_port *port, int ch) 1161 { 1162 cdns_uart_console_wait_tx(port); 1163 writel(ch, port->membase + CDNS_UART_FIFO); 1164 } 1165 1166 static void __init cdns_early_write(struct console *con, const char *s, 1167 unsigned n) 1168 { 1169 struct earlycon_device *dev = con->data; 1170 1171 uart_console_write(&dev->port, s, n, cdns_uart_console_putchar); 1172 } 1173 1174 static int __init cdns_early_console_setup(struct earlycon_device *device, 1175 const char *opt) 1176 { 1177 struct uart_port *port = &device->port; 1178 1179 if (!port->membase) 1180 return -ENODEV; 1181 1182 /* initialise control register */ 1183 writel(CDNS_UART_CR_TX_EN|CDNS_UART_CR_TXRST|CDNS_UART_CR_RXRST, 1184 port->membase + CDNS_UART_CR); 1185 1186 /* only set baud if specified on command line - otherwise 1187 * assume it has been initialized by a boot loader. 1188 */ 1189 if (device->baud) { 1190 u32 cd = 0, bdiv = 0; 1191 u32 mr; 1192 int div8; 1193 1194 cdns_uart_calc_baud_divs(port->uartclk, device->baud, 1195 &bdiv, &cd, &div8); 1196 mr = CDNS_UART_MR_PARITY_NONE; 1197 if (div8) 1198 mr |= CDNS_UART_MR_CLKSEL; 1199 1200 writel(mr, port->membase + CDNS_UART_MR); 1201 writel(cd, port->membase + CDNS_UART_BAUDGEN); 1202 writel(bdiv, port->membase + CDNS_UART_BAUDDIV); 1203 } 1204 1205 device->con->write = cdns_early_write; 1206 1207 return 0; 1208 } 1209 OF_EARLYCON_DECLARE(cdns, "xlnx,xuartps", cdns_early_console_setup); 1210 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p8", cdns_early_console_setup); 1211 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p12", cdns_early_console_setup); 1212 OF_EARLYCON_DECLARE(cdns, "xlnx,zynqmp-uart", cdns_early_console_setup); 1213 1214 /** 1215 * cdns_uart_console_write - perform write operation 1216 * @co: Console handle 1217 * @s: Pointer to character array 1218 * @count: No of characters 1219 */ 1220 static void cdns_uart_console_write(struct console *co, const char *s, 1221 unsigned int count) 1222 { 1223 struct uart_port *port = &cdns_uart_port[co->index]; 1224 unsigned long flags; 1225 unsigned int imr, ctrl; 1226 int locked = 1; 1227 1228 if (port->sysrq) 1229 locked = 0; 1230 else if (oops_in_progress) 1231 locked = spin_trylock_irqsave(&port->lock, flags); 1232 else 1233 spin_lock_irqsave(&port->lock, flags); 1234 1235 /* save and disable interrupt */ 1236 imr = readl(port->membase + CDNS_UART_IMR); 1237 writel(imr, port->membase + CDNS_UART_IDR); 1238 1239 /* 1240 * Make sure that the tx part is enabled. Set the TX enable bit and 1241 * clear the TX disable bit to enable the transmitter. 1242 */ 1243 ctrl = readl(port->membase + CDNS_UART_CR); 1244 ctrl &= ~CDNS_UART_CR_TX_DIS; 1245 ctrl |= CDNS_UART_CR_TX_EN; 1246 writel(ctrl, port->membase + CDNS_UART_CR); 1247 1248 uart_console_write(port, s, count, cdns_uart_console_putchar); 1249 cdns_uart_console_wait_tx(port); 1250 1251 writel(ctrl, port->membase + CDNS_UART_CR); 1252 1253 /* restore interrupt state */ 1254 writel(imr, port->membase + CDNS_UART_IER); 1255 1256 if (locked) 1257 spin_unlock_irqrestore(&port->lock, flags); 1258 } 1259 1260 /** 1261 * cdns_uart_console_setup - Initialize the uart to default config 1262 * @co: Console handle 1263 * @options: Initial settings of uart 1264 * 1265 * Return: 0 on success, negative errno otherwise. 1266 */ 1267 static int __init cdns_uart_console_setup(struct console *co, char *options) 1268 { 1269 struct uart_port *port = &cdns_uart_port[co->index]; 1270 int baud = 9600; 1271 int bits = 8; 1272 int parity = 'n'; 1273 int flow = 'n'; 1274 1275 if (co->index < 0 || co->index >= CDNS_UART_NR_PORTS) 1276 return -EINVAL; 1277 1278 if (!port->membase) { 1279 pr_debug("console on " CDNS_UART_TTY_NAME "%i not present\n", 1280 co->index); 1281 return -ENODEV; 1282 } 1283 1284 if (options) 1285 uart_parse_options(options, &baud, &parity, &bits, &flow); 1286 1287 return uart_set_options(port, co, baud, parity, bits, flow); 1288 } 1289 1290 static struct uart_driver cdns_uart_uart_driver; 1291 1292 static struct console cdns_uart_console = { 1293 .name = CDNS_UART_TTY_NAME, 1294 .write = cdns_uart_console_write, 1295 .device = uart_console_device, 1296 .setup = cdns_uart_console_setup, 1297 .flags = CON_PRINTBUFFER, 1298 .index = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */ 1299 .data = &cdns_uart_uart_driver, 1300 }; 1301 1302 /** 1303 * cdns_uart_console_init - Initialization call 1304 * 1305 * Return: 0 on success, negative errno otherwise 1306 */ 1307 static int __init cdns_uart_console_init(void) 1308 { 1309 register_console(&cdns_uart_console); 1310 return 0; 1311 } 1312 1313 console_initcall(cdns_uart_console_init); 1314 1315 #endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */ 1316 1317 static struct uart_driver cdns_uart_uart_driver = { 1318 .owner = THIS_MODULE, 1319 .driver_name = CDNS_UART_NAME, 1320 .dev_name = CDNS_UART_TTY_NAME, 1321 .major = CDNS_UART_MAJOR, 1322 .minor = CDNS_UART_MINOR, 1323 .nr = CDNS_UART_NR_PORTS, 1324 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE 1325 .cons = &cdns_uart_console, 1326 #endif 1327 }; 1328 1329 #ifdef CONFIG_PM_SLEEP 1330 /** 1331 * cdns_uart_suspend - suspend event 1332 * @device: Pointer to the device structure 1333 * 1334 * Return: 0 1335 */ 1336 static int cdns_uart_suspend(struct device *device) 1337 { 1338 struct uart_port *port = dev_get_drvdata(device); 1339 struct tty_struct *tty; 1340 struct device *tty_dev; 1341 int may_wake = 0; 1342 1343 /* Get the tty which could be NULL so don't assume it's valid */ 1344 tty = tty_port_tty_get(&port->state->port); 1345 if (tty) { 1346 tty_dev = tty->dev; 1347 may_wake = device_may_wakeup(tty_dev); 1348 tty_kref_put(tty); 1349 } 1350 1351 /* 1352 * Call the API provided in serial_core.c file which handles 1353 * the suspend. 1354 */ 1355 uart_suspend_port(&cdns_uart_uart_driver, port); 1356 if (!(console_suspend_enabled && !may_wake)) { 1357 unsigned long flags = 0; 1358 1359 spin_lock_irqsave(&port->lock, flags); 1360 /* Empty the receive FIFO 1st before making changes */ 1361 while (!(readl(port->membase + CDNS_UART_SR) & 1362 CDNS_UART_SR_RXEMPTY)) 1363 readl(port->membase + CDNS_UART_FIFO); 1364 /* set RX trigger level to 1 */ 1365 writel(1, port->membase + CDNS_UART_RXWM); 1366 /* disable RX timeout interrups */ 1367 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IDR); 1368 spin_unlock_irqrestore(&port->lock, flags); 1369 } 1370 1371 return 0; 1372 } 1373 1374 /** 1375 * cdns_uart_resume - Resume after a previous suspend 1376 * @device: Pointer to the device structure 1377 * 1378 * Return: 0 1379 */ 1380 static int cdns_uart_resume(struct device *device) 1381 { 1382 struct uart_port *port = dev_get_drvdata(device); 1383 unsigned long flags = 0; 1384 u32 ctrl_reg; 1385 struct tty_struct *tty; 1386 struct device *tty_dev; 1387 int may_wake = 0; 1388 1389 /* Get the tty which could be NULL so don't assume it's valid */ 1390 tty = tty_port_tty_get(&port->state->port); 1391 if (tty) { 1392 tty_dev = tty->dev; 1393 may_wake = device_may_wakeup(tty_dev); 1394 tty_kref_put(tty); 1395 } 1396 1397 if (console_suspend_enabled && !may_wake) { 1398 struct cdns_uart *cdns_uart = port->private_data; 1399 1400 clk_enable(cdns_uart->pclk); 1401 clk_enable(cdns_uart->uartclk); 1402 1403 spin_lock_irqsave(&port->lock, flags); 1404 1405 /* Set TX/RX Reset */ 1406 ctrl_reg = readl(port->membase + CDNS_UART_CR); 1407 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST; 1408 writel(ctrl_reg, port->membase + CDNS_UART_CR); 1409 while (readl(port->membase + CDNS_UART_CR) & 1410 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST)) 1411 cpu_relax(); 1412 1413 /* restore rx timeout value */ 1414 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT); 1415 /* Enable Tx/Rx */ 1416 ctrl_reg = readl(port->membase + CDNS_UART_CR); 1417 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS); 1418 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN; 1419 writel(ctrl_reg, port->membase + CDNS_UART_CR); 1420 1421 clk_disable(cdns_uart->uartclk); 1422 clk_disable(cdns_uart->pclk); 1423 spin_unlock_irqrestore(&port->lock, flags); 1424 } else { 1425 spin_lock_irqsave(&port->lock, flags); 1426 /* restore original rx trigger level */ 1427 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM); 1428 /* enable RX timeout interrupt */ 1429 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IER); 1430 spin_unlock_irqrestore(&port->lock, flags); 1431 } 1432 1433 return uart_resume_port(&cdns_uart_uart_driver, port); 1434 } 1435 #endif /* ! CONFIG_PM_SLEEP */ 1436 static int __maybe_unused cdns_runtime_suspend(struct device *dev) 1437 { 1438 struct platform_device *pdev = to_platform_device(dev); 1439 struct uart_port *port = platform_get_drvdata(pdev); 1440 struct cdns_uart *cdns_uart = port->private_data; 1441 1442 clk_disable(cdns_uart->uartclk); 1443 clk_disable(cdns_uart->pclk); 1444 return 0; 1445 }; 1446 1447 static int __maybe_unused cdns_runtime_resume(struct device *dev) 1448 { 1449 struct platform_device *pdev = to_platform_device(dev); 1450 struct uart_port *port = platform_get_drvdata(pdev); 1451 struct cdns_uart *cdns_uart = port->private_data; 1452 1453 clk_enable(cdns_uart->pclk); 1454 clk_enable(cdns_uart->uartclk); 1455 return 0; 1456 }; 1457 1458 static const struct dev_pm_ops cdns_uart_dev_pm_ops = { 1459 SET_SYSTEM_SLEEP_PM_OPS(cdns_uart_suspend, cdns_uart_resume) 1460 SET_RUNTIME_PM_OPS(cdns_runtime_suspend, 1461 cdns_runtime_resume, NULL) 1462 }; 1463 1464 static const struct cdns_platform_data zynqmp_uart_def = { 1465 .quirks = CDNS_UART_RXBS_SUPPORT, }; 1466 1467 /* Match table for of_platform binding */ 1468 static const struct of_device_id cdns_uart_of_match[] = { 1469 { .compatible = "xlnx,xuartps", }, 1470 { .compatible = "cdns,uart-r1p8", }, 1471 { .compatible = "cdns,uart-r1p12", .data = &zynqmp_uart_def }, 1472 { .compatible = "xlnx,zynqmp-uart", .data = &zynqmp_uart_def }, 1473 {} 1474 }; 1475 MODULE_DEVICE_TABLE(of, cdns_uart_of_match); 1476 1477 /** 1478 * cdns_uart_probe - Platform driver probe 1479 * @pdev: Pointer to the platform device structure 1480 * 1481 * Return: 0 on success, negative errno otherwise 1482 */ 1483 static int cdns_uart_probe(struct platform_device *pdev) 1484 { 1485 int rc, id, irq; 1486 struct uart_port *port; 1487 struct resource *res; 1488 struct cdns_uart *cdns_uart_data; 1489 const struct of_device_id *match; 1490 1491 cdns_uart_data = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_data), 1492 GFP_KERNEL); 1493 if (!cdns_uart_data) 1494 return -ENOMEM; 1495 1496 match = of_match_node(cdns_uart_of_match, pdev->dev.of_node); 1497 if (match && match->data) { 1498 const struct cdns_platform_data *data = match->data; 1499 1500 cdns_uart_data->quirks = data->quirks; 1501 } 1502 1503 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "pclk"); 1504 if (IS_ERR(cdns_uart_data->pclk)) { 1505 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "aper_clk"); 1506 if (!IS_ERR(cdns_uart_data->pclk)) 1507 dev_err(&pdev->dev, "clock name 'aper_clk' is deprecated.\n"); 1508 } 1509 if (IS_ERR(cdns_uart_data->pclk)) { 1510 dev_err(&pdev->dev, "pclk clock not found.\n"); 1511 return PTR_ERR(cdns_uart_data->pclk); 1512 } 1513 1514 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "uart_clk"); 1515 if (IS_ERR(cdns_uart_data->uartclk)) { 1516 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "ref_clk"); 1517 if (!IS_ERR(cdns_uart_data->uartclk)) 1518 dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n"); 1519 } 1520 if (IS_ERR(cdns_uart_data->uartclk)) { 1521 dev_err(&pdev->dev, "uart_clk clock not found.\n"); 1522 return PTR_ERR(cdns_uart_data->uartclk); 1523 } 1524 1525 rc = clk_prepare_enable(cdns_uart_data->pclk); 1526 if (rc) { 1527 dev_err(&pdev->dev, "Unable to enable pclk clock.\n"); 1528 return rc; 1529 } 1530 rc = clk_prepare_enable(cdns_uart_data->uartclk); 1531 if (rc) { 1532 dev_err(&pdev->dev, "Unable to enable device clock.\n"); 1533 goto err_out_clk_dis_pclk; 1534 } 1535 1536 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1537 if (!res) { 1538 rc = -ENODEV; 1539 goto err_out_clk_disable; 1540 } 1541 1542 irq = platform_get_irq(pdev, 0); 1543 if (irq <= 0) { 1544 rc = -ENXIO; 1545 goto err_out_clk_disable; 1546 } 1547 1548 #ifdef CONFIG_COMMON_CLK 1549 cdns_uart_data->clk_rate_change_nb.notifier_call = 1550 cdns_uart_clk_notifier_cb; 1551 if (clk_notifier_register(cdns_uart_data->uartclk, 1552 &cdns_uart_data->clk_rate_change_nb)) 1553 dev_warn(&pdev->dev, "Unable to register clock notifier.\n"); 1554 #endif 1555 /* Look for a serialN alias */ 1556 id = of_alias_get_id(pdev->dev.of_node, "serial"); 1557 if (id < 0) 1558 id = 0; 1559 1560 /* Initialize the port structure */ 1561 port = cdns_uart_get_port(id); 1562 1563 if (!port) { 1564 dev_err(&pdev->dev, "Cannot get uart_port structure\n"); 1565 rc = -ENODEV; 1566 goto err_out_notif_unreg; 1567 } 1568 1569 /* 1570 * Register the port. 1571 * This function also registers this device with the tty layer 1572 * and triggers invocation of the config_port() entry point. 1573 */ 1574 port->mapbase = res->start; 1575 port->irq = irq; 1576 port->dev = &pdev->dev; 1577 port->uartclk = clk_get_rate(cdns_uart_data->uartclk); 1578 port->private_data = cdns_uart_data; 1579 cdns_uart_data->port = port; 1580 platform_set_drvdata(pdev, port); 1581 1582 pm_runtime_use_autosuspend(&pdev->dev); 1583 pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT); 1584 pm_runtime_set_active(&pdev->dev); 1585 pm_runtime_enable(&pdev->dev); 1586 1587 rc = uart_add_one_port(&cdns_uart_uart_driver, port); 1588 if (rc) { 1589 dev_err(&pdev->dev, 1590 "uart_add_one_port() failed; err=%i\n", rc); 1591 goto err_out_pm_disable; 1592 } 1593 1594 return 0; 1595 1596 err_out_pm_disable: 1597 pm_runtime_disable(&pdev->dev); 1598 pm_runtime_set_suspended(&pdev->dev); 1599 pm_runtime_dont_use_autosuspend(&pdev->dev); 1600 err_out_notif_unreg: 1601 #ifdef CONFIG_COMMON_CLK 1602 clk_notifier_unregister(cdns_uart_data->uartclk, 1603 &cdns_uart_data->clk_rate_change_nb); 1604 #endif 1605 err_out_clk_disable: 1606 clk_disable_unprepare(cdns_uart_data->uartclk); 1607 err_out_clk_dis_pclk: 1608 clk_disable_unprepare(cdns_uart_data->pclk); 1609 1610 return rc; 1611 } 1612 1613 /** 1614 * cdns_uart_remove - called when the platform driver is unregistered 1615 * @pdev: Pointer to the platform device structure 1616 * 1617 * Return: 0 on success, negative errno otherwise 1618 */ 1619 static int cdns_uart_remove(struct platform_device *pdev) 1620 { 1621 struct uart_port *port = platform_get_drvdata(pdev); 1622 struct cdns_uart *cdns_uart_data = port->private_data; 1623 int rc; 1624 1625 /* Remove the cdns_uart port from the serial core */ 1626 #ifdef CONFIG_COMMON_CLK 1627 clk_notifier_unregister(cdns_uart_data->uartclk, 1628 &cdns_uart_data->clk_rate_change_nb); 1629 #endif 1630 rc = uart_remove_one_port(&cdns_uart_uart_driver, port); 1631 port->mapbase = 0; 1632 clk_disable_unprepare(cdns_uart_data->uartclk); 1633 clk_disable_unprepare(cdns_uart_data->pclk); 1634 pm_runtime_disable(&pdev->dev); 1635 pm_runtime_set_suspended(&pdev->dev); 1636 pm_runtime_dont_use_autosuspend(&pdev->dev); 1637 return rc; 1638 } 1639 1640 static struct platform_driver cdns_uart_platform_driver = { 1641 .probe = cdns_uart_probe, 1642 .remove = cdns_uart_remove, 1643 .driver = { 1644 .name = CDNS_UART_NAME, 1645 .of_match_table = cdns_uart_of_match, 1646 .pm = &cdns_uart_dev_pm_ops, 1647 }, 1648 }; 1649 1650 static int __init cdns_uart_init(void) 1651 { 1652 int retval = 0; 1653 1654 /* Register the cdns_uart driver with the serial core */ 1655 retval = uart_register_driver(&cdns_uart_uart_driver); 1656 if (retval) 1657 return retval; 1658 1659 /* Register the platform driver */ 1660 retval = platform_driver_register(&cdns_uart_platform_driver); 1661 if (retval) 1662 uart_unregister_driver(&cdns_uart_uart_driver); 1663 1664 return retval; 1665 } 1666 1667 static void __exit cdns_uart_exit(void) 1668 { 1669 /* Unregister the platform driver */ 1670 platform_driver_unregister(&cdns_uart_platform_driver); 1671 1672 /* Unregister the cdns_uart driver */ 1673 uart_unregister_driver(&cdns_uart_uart_driver); 1674 } 1675 1676 module_init(cdns_uart_init); 1677 module_exit(cdns_uart_exit); 1678 1679 MODULE_DESCRIPTION("Driver for Cadence UART"); 1680 MODULE_AUTHOR("Xilinx Inc."); 1681 MODULE_LICENSE("GPL"); 1682