1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Cadence UART driver (found in Xilinx Zynq)
4  *
5  * 2011 - 2014 (C) Xilinx Inc.
6  *
7  * This driver has originally been pushed by Xilinx using a Zynq-branding. This
8  * still shows in the naming of this file, the kconfig symbols and some symbols
9  * in the code.
10  */
11 
12 #include <linux/platform_device.h>
13 #include <linux/serial.h>
14 #include <linux/console.h>
15 #include <linux/serial_core.h>
16 #include <linux/slab.h>
17 #include <linux/tty.h>
18 #include <linux/tty_flip.h>
19 #include <linux/clk.h>
20 #include <linux/irq.h>
21 #include <linux/io.h>
22 #include <linux/of.h>
23 #include <linux/module.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/iopoll.h>
26 
27 #define CDNS_UART_TTY_NAME	"ttyPS"
28 #define CDNS_UART_NAME		"xuartps"
29 #define CDNS_UART_MAJOR		0	/* use dynamic node allocation */
30 #define CDNS_UART_MINOR		0	/* works best with devtmpfs */
31 #define CDNS_UART_NR_PORTS	16
32 #define CDNS_UART_FIFO_SIZE	64	/* FIFO size */
33 #define CDNS_UART_REGISTER_SPACE	0x1000
34 #define TX_TIMEOUT		500000
35 
36 /* Rx Trigger level */
37 static int rx_trigger_level = 56;
38 module_param(rx_trigger_level, uint, 0444);
39 MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");
40 
41 /* Rx Timeout */
42 static int rx_timeout = 10;
43 module_param(rx_timeout, uint, 0444);
44 MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
45 
46 /* Register offsets for the UART. */
47 #define CDNS_UART_CR		0x00  /* Control Register */
48 #define CDNS_UART_MR		0x04  /* Mode Register */
49 #define CDNS_UART_IER		0x08  /* Interrupt Enable */
50 #define CDNS_UART_IDR		0x0C  /* Interrupt Disable */
51 #define CDNS_UART_IMR		0x10  /* Interrupt Mask */
52 #define CDNS_UART_ISR		0x14  /* Interrupt Status */
53 #define CDNS_UART_BAUDGEN	0x18  /* Baud Rate Generator */
54 #define CDNS_UART_RXTOUT	0x1C  /* RX Timeout */
55 #define CDNS_UART_RXWM		0x20  /* RX FIFO Trigger Level */
56 #define CDNS_UART_MODEMCR	0x24  /* Modem Control */
57 #define CDNS_UART_MODEMSR	0x28  /* Modem Status */
58 #define CDNS_UART_SR		0x2C  /* Channel Status */
59 #define CDNS_UART_FIFO		0x30  /* FIFO */
60 #define CDNS_UART_BAUDDIV	0x34  /* Baud Rate Divider */
61 #define CDNS_UART_FLOWDEL	0x38  /* Flow Delay */
62 #define CDNS_UART_IRRX_PWIDTH	0x3C  /* IR Min Received Pulse Width */
63 #define CDNS_UART_IRTX_PWIDTH	0x40  /* IR Transmitted pulse Width */
64 #define CDNS_UART_TXWM		0x44  /* TX FIFO Trigger Level */
65 #define CDNS_UART_RXBS		0x48  /* RX FIFO byte status register */
66 
67 /* Control Register Bit Definitions */
68 #define CDNS_UART_CR_STOPBRK	0x00000100  /* Stop TX break */
69 #define CDNS_UART_CR_STARTBRK	0x00000080  /* Set TX break */
70 #define CDNS_UART_CR_TX_DIS	0x00000020  /* TX disabled. */
71 #define CDNS_UART_CR_TX_EN	0x00000010  /* TX enabled */
72 #define CDNS_UART_CR_RX_DIS	0x00000008  /* RX disabled. */
73 #define CDNS_UART_CR_RX_EN	0x00000004  /* RX enabled */
74 #define CDNS_UART_CR_TXRST	0x00000002  /* TX logic reset */
75 #define CDNS_UART_CR_RXRST	0x00000001  /* RX logic reset */
76 #define CDNS_UART_CR_RST_TO	0x00000040  /* Restart Timeout Counter */
77 #define CDNS_UART_RXBS_PARITY    0x00000001 /* Parity error status */
78 #define CDNS_UART_RXBS_FRAMING   0x00000002 /* Framing error status */
79 #define CDNS_UART_RXBS_BRK       0x00000004 /* Overrun error status */
80 
81 /*
82  * Mode Register:
83  * The mode register (MR) defines the mode of transfer as well as the data
84  * format. If this register is modified during transmission or reception,
85  * data validity cannot be guaranteed.
86  */
87 #define CDNS_UART_MR_CLKSEL		0x00000001  /* Pre-scalar selection */
88 #define CDNS_UART_MR_CHMODE_L_LOOP	0x00000200  /* Local loop back mode */
89 #define CDNS_UART_MR_CHMODE_NORM	0x00000000  /* Normal mode */
90 #define CDNS_UART_MR_CHMODE_MASK	0x00000300  /* Mask for mode bits */
91 
92 #define CDNS_UART_MR_STOPMODE_2_BIT	0x00000080  /* 2 stop bits */
93 #define CDNS_UART_MR_STOPMODE_1_BIT	0x00000000  /* 1 stop bit */
94 
95 #define CDNS_UART_MR_PARITY_NONE	0x00000020  /* No parity mode */
96 #define CDNS_UART_MR_PARITY_MARK	0x00000018  /* Mark parity mode */
97 #define CDNS_UART_MR_PARITY_SPACE	0x00000010  /* Space parity mode */
98 #define CDNS_UART_MR_PARITY_ODD		0x00000008  /* Odd parity mode */
99 #define CDNS_UART_MR_PARITY_EVEN	0x00000000  /* Even parity mode */
100 
101 #define CDNS_UART_MR_CHARLEN_6_BIT	0x00000006  /* 6 bits data */
102 #define CDNS_UART_MR_CHARLEN_7_BIT	0x00000004  /* 7 bits data */
103 #define CDNS_UART_MR_CHARLEN_8_BIT	0x00000000  /* 8 bits data */
104 
105 /*
106  * Interrupt Registers:
107  * Interrupt control logic uses the interrupt enable register (IER) and the
108  * interrupt disable register (IDR) to set the value of the bits in the
109  * interrupt mask register (IMR). The IMR determines whether to pass an
110  * interrupt to the interrupt status register (ISR).
111  * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an
112  * interrupt. IMR and ISR are read only, and IER and IDR are write only.
113  * Reading either IER or IDR returns 0x00.
114  * All four registers have the same bit definitions.
115  */
116 #define CDNS_UART_IXR_TOUT	0x00000100 /* RX Timeout error interrupt */
117 #define CDNS_UART_IXR_PARITY	0x00000080 /* Parity error interrupt */
118 #define CDNS_UART_IXR_FRAMING	0x00000040 /* Framing error interrupt */
119 #define CDNS_UART_IXR_OVERRUN	0x00000020 /* Overrun error interrupt */
120 #define CDNS_UART_IXR_TXFULL	0x00000010 /* TX FIFO Full interrupt */
121 #define CDNS_UART_IXR_TXEMPTY	0x00000008 /* TX FIFO empty interrupt */
122 #define CDNS_UART_ISR_RXEMPTY	0x00000002 /* RX FIFO empty interrupt */
123 #define CDNS_UART_IXR_RXTRIG	0x00000001 /* RX FIFO trigger interrupt */
124 #define CDNS_UART_IXR_RXFULL	0x00000004 /* RX FIFO full interrupt. */
125 #define CDNS_UART_IXR_RXEMPTY	0x00000002 /* RX FIFO empty interrupt. */
126 #define CDNS_UART_IXR_RXMASK	0x000021e7 /* Valid RX bit mask */
127 
128 	/*
129 	 * Do not enable parity error interrupt for the following
130 	 * reason: When parity error interrupt is enabled, each Rx
131 	 * parity error always results in 2 events. The first one
132 	 * being parity error interrupt and the second one with a
133 	 * proper Rx interrupt with the incoming data.  Disabling
134 	 * parity error interrupt ensures better handling of parity
135 	 * error events. With this change, for a parity error case, we
136 	 * get a Rx interrupt with parity error set in ISR register
137 	 * and we still handle parity errors in the desired way.
138 	 */
139 
140 #define CDNS_UART_RX_IRQS	(CDNS_UART_IXR_FRAMING | \
141 				 CDNS_UART_IXR_OVERRUN | \
142 				 CDNS_UART_IXR_RXTRIG |	 \
143 				 CDNS_UART_IXR_TOUT)
144 
145 /* Goes in read_status_mask for break detection as the HW doesn't do it*/
146 #define CDNS_UART_IXR_BRK	0x00002000
147 
148 #define CDNS_UART_RXBS_SUPPORT BIT(1)
149 /*
150  * Modem Control register:
151  * The read/write Modem Control register controls the interface with the modem
152  * or data set, or a peripheral device emulating a modem.
153  */
154 #define CDNS_UART_MODEMCR_FCM	0x00000020 /* Automatic flow control mode */
155 #define CDNS_UART_MODEMCR_RTS	0x00000002 /* Request to send output control */
156 #define CDNS_UART_MODEMCR_DTR	0x00000001 /* Data Terminal Ready */
157 
158 /*
159  * Modem Status register:
160  * The read/write Modem Status register reports the interface with the modem
161  * or data set, or a peripheral device emulating a modem.
162  */
163 #define CDNS_UART_MODEMSR_DCD	BIT(7) /* Data Carrier Detect */
164 #define CDNS_UART_MODEMSR_RI	BIT(6) /* Ting Indicator */
165 #define CDNS_UART_MODEMSR_DSR	BIT(5) /* Data Set Ready */
166 #define CDNS_UART_MODEMSR_CTS	BIT(4) /* Clear To Send */
167 
168 /*
169  * Channel Status Register:
170  * The channel status register (CSR) is provided to enable the control logic
171  * to monitor the status of bits in the channel interrupt status register,
172  * even if these are masked out by the interrupt mask register.
173  */
174 #define CDNS_UART_SR_RXEMPTY	0x00000002 /* RX FIFO empty */
175 #define CDNS_UART_SR_TXEMPTY	0x00000008 /* TX FIFO empty */
176 #define CDNS_UART_SR_TXFULL	0x00000010 /* TX FIFO full */
177 #define CDNS_UART_SR_RXTRIG	0x00000001 /* Rx Trigger */
178 #define CDNS_UART_SR_TACTIVE	0x00000800 /* TX state machine active */
179 
180 /* baud dividers min/max values */
181 #define CDNS_UART_BDIV_MIN	4
182 #define CDNS_UART_BDIV_MAX	255
183 #define CDNS_UART_CD_MAX	65535
184 #define UART_AUTOSUSPEND_TIMEOUT	3000
185 
186 /**
187  * struct cdns_uart - device data
188  * @port:		Pointer to the UART port
189  * @uartclk:		Reference clock
190  * @pclk:		APB clock
191  * @cdns_uart_driver:	Pointer to UART driver
192  * @baud:		Current baud rate
193  * @clk_rate_change_nb:	Notifier block for clock changes
194  * @quirks:		Flags for RXBS support.
195  * @cts_override:	Modem control state override
196  */
197 struct cdns_uart {
198 	struct uart_port	*port;
199 	struct clk		*uartclk;
200 	struct clk		*pclk;
201 	struct uart_driver	*cdns_uart_driver;
202 	unsigned int		baud;
203 	struct notifier_block	clk_rate_change_nb;
204 	u32			quirks;
205 	bool cts_override;
206 };
207 struct cdns_platform_data {
208 	u32 quirks;
209 };
210 #define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \
211 		clk_rate_change_nb)
212 
213 /**
214  * cdns_uart_handle_rx - Handle the received bytes along with Rx errors.
215  * @dev_id: Id of the UART port
216  * @isrstatus: The interrupt status register value as read
217  * Return: None
218  */
219 static void cdns_uart_handle_rx(void *dev_id, unsigned int isrstatus)
220 {
221 	struct uart_port *port = (struct uart_port *)dev_id;
222 	struct cdns_uart *cdns_uart = port->private_data;
223 	unsigned int data;
224 	unsigned int rxbs_status = 0;
225 	unsigned int status_mask;
226 	unsigned int framerrprocessed = 0;
227 	char status = TTY_NORMAL;
228 	bool is_rxbs_support;
229 
230 	is_rxbs_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
231 
232 	while ((readl(port->membase + CDNS_UART_SR) &
233 		CDNS_UART_SR_RXEMPTY) != CDNS_UART_SR_RXEMPTY) {
234 		if (is_rxbs_support)
235 			rxbs_status = readl(port->membase + CDNS_UART_RXBS);
236 		data = readl(port->membase + CDNS_UART_FIFO);
237 		port->icount.rx++;
238 		/*
239 		 * There is no hardware break detection in Zynq, so we interpret
240 		 * framing error with all-zeros data as a break sequence.
241 		 * Most of the time, there's another non-zero byte at the
242 		 * end of the sequence.
243 		 */
244 		if (!is_rxbs_support && (isrstatus & CDNS_UART_IXR_FRAMING)) {
245 			if (!data) {
246 				port->read_status_mask |= CDNS_UART_IXR_BRK;
247 				framerrprocessed = 1;
248 				continue;
249 			}
250 		}
251 		if (is_rxbs_support && (rxbs_status & CDNS_UART_RXBS_BRK)) {
252 			port->icount.brk++;
253 			status = TTY_BREAK;
254 			if (uart_handle_break(port))
255 				continue;
256 		}
257 
258 		isrstatus &= port->read_status_mask;
259 		isrstatus &= ~port->ignore_status_mask;
260 		status_mask = port->read_status_mask;
261 		status_mask &= ~port->ignore_status_mask;
262 
263 		if (data &&
264 		    (port->read_status_mask & CDNS_UART_IXR_BRK)) {
265 			port->read_status_mask &= ~CDNS_UART_IXR_BRK;
266 			port->icount.brk++;
267 			if (uart_handle_break(port))
268 				continue;
269 		}
270 
271 		if (uart_handle_sysrq_char(port, data))
272 			continue;
273 
274 		if (is_rxbs_support) {
275 			if ((rxbs_status & CDNS_UART_RXBS_PARITY)
276 			    && (status_mask & CDNS_UART_IXR_PARITY)) {
277 				port->icount.parity++;
278 				status = TTY_PARITY;
279 			}
280 			if ((rxbs_status & CDNS_UART_RXBS_FRAMING)
281 			    && (status_mask & CDNS_UART_IXR_PARITY)) {
282 				port->icount.frame++;
283 				status = TTY_FRAME;
284 			}
285 		} else {
286 			if (isrstatus & CDNS_UART_IXR_PARITY) {
287 				port->icount.parity++;
288 				status = TTY_PARITY;
289 			}
290 			if ((isrstatus & CDNS_UART_IXR_FRAMING) &&
291 			    !framerrprocessed) {
292 				port->icount.frame++;
293 				status = TTY_FRAME;
294 			}
295 		}
296 		if (isrstatus & CDNS_UART_IXR_OVERRUN) {
297 			port->icount.overrun++;
298 			tty_insert_flip_char(&port->state->port, 0,
299 					     TTY_OVERRUN);
300 		}
301 		tty_insert_flip_char(&port->state->port, data, status);
302 		isrstatus = 0;
303 	}
304 	spin_unlock(&port->lock);
305 	tty_flip_buffer_push(&port->state->port);
306 	spin_lock(&port->lock);
307 }
308 
309 /**
310  * cdns_uart_handle_tx - Handle the bytes to be Txed.
311  * @dev_id: Id of the UART port
312  * Return: None
313  */
314 static void cdns_uart_handle_tx(void *dev_id)
315 {
316 	struct uart_port *port = (struct uart_port *)dev_id;
317 	unsigned int numbytes;
318 
319 	if (uart_circ_empty(&port->state->xmit)) {
320 		writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR);
321 	} else {
322 		numbytes = port->fifosize;
323 		while (numbytes && !uart_circ_empty(&port->state->xmit) &&
324 		       !(readl(port->membase + CDNS_UART_SR) &
325 						CDNS_UART_SR_TXFULL)) {
326 			/*
327 			 * Get the data from the UART circular buffer
328 			 * and write it to the cdns_uart's TX_FIFO
329 			 * register.
330 			 */
331 			writel(
332 				port->state->xmit.buf[port->state->xmit.tail],
333 					port->membase + CDNS_UART_FIFO);
334 
335 			port->icount.tx++;
336 
337 			/*
338 			 * Adjust the tail of the UART buffer and wrap
339 			 * the buffer if it reaches limit.
340 			 */
341 			port->state->xmit.tail =
342 				(port->state->xmit.tail + 1) &
343 					(UART_XMIT_SIZE - 1);
344 
345 			numbytes--;
346 		}
347 
348 		if (uart_circ_chars_pending(
349 				&port->state->xmit) < WAKEUP_CHARS)
350 			uart_write_wakeup(port);
351 	}
352 }
353 
354 /**
355  * cdns_uart_isr - Interrupt handler
356  * @irq: Irq number
357  * @dev_id: Id of the port
358  *
359  * Return: IRQHANDLED
360  */
361 static irqreturn_t cdns_uart_isr(int irq, void *dev_id)
362 {
363 	struct uart_port *port = (struct uart_port *)dev_id;
364 	unsigned int isrstatus;
365 
366 	spin_lock(&port->lock);
367 
368 	/* Read the interrupt status register to determine which
369 	 * interrupt(s) is/are active and clear them.
370 	 */
371 	isrstatus = readl(port->membase + CDNS_UART_ISR);
372 	writel(isrstatus, port->membase + CDNS_UART_ISR);
373 
374 	if (isrstatus & CDNS_UART_IXR_TXEMPTY) {
375 		cdns_uart_handle_tx(dev_id);
376 		isrstatus &= ~CDNS_UART_IXR_TXEMPTY;
377 	}
378 
379 	/*
380 	 * Skip RX processing if RX is disabled as RXEMPTY will never be set
381 	 * as read bytes will not be removed from the FIFO.
382 	 */
383 	if (isrstatus & CDNS_UART_IXR_RXMASK &&
384 	    !(readl(port->membase + CDNS_UART_CR) & CDNS_UART_CR_RX_DIS))
385 		cdns_uart_handle_rx(dev_id, isrstatus);
386 
387 	spin_unlock(&port->lock);
388 	return IRQ_HANDLED;
389 }
390 
391 /**
392  * cdns_uart_calc_baud_divs - Calculate baud rate divisors
393  * @clk: UART module input clock
394  * @baud: Desired baud rate
395  * @rbdiv: BDIV value (return value)
396  * @rcd: CD value (return value)
397  * @div8: Value for clk_sel bit in mod (return value)
398  * Return: baud rate, requested baud when possible, or actual baud when there
399  *	was too much error, zero if no valid divisors are found.
400  *
401  * Formula to obtain baud rate is
402  *	baud_tx/rx rate = clk/CD * (BDIV + 1)
403  *	input_clk = (Uart User Defined Clock or Apb Clock)
404  *		depends on UCLKEN in MR Reg
405  *	clk = input_clk or input_clk/8;
406  *		depends on CLKS in MR reg
407  *	CD and BDIV depends on values in
408  *			baud rate generate register
409  *			baud rate clock divisor register
410  */
411 static unsigned int cdns_uart_calc_baud_divs(unsigned int clk,
412 		unsigned int baud, u32 *rbdiv, u32 *rcd, int *div8)
413 {
414 	u32 cd, bdiv;
415 	unsigned int calc_baud;
416 	unsigned int bestbaud = 0;
417 	unsigned int bauderror;
418 	unsigned int besterror = ~0;
419 
420 	if (baud < clk / ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX)) {
421 		*div8 = 1;
422 		clk /= 8;
423 	} else {
424 		*div8 = 0;
425 	}
426 
427 	for (bdiv = CDNS_UART_BDIV_MIN; bdiv <= CDNS_UART_BDIV_MAX; bdiv++) {
428 		cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1));
429 		if (cd < 1 || cd > CDNS_UART_CD_MAX)
430 			continue;
431 
432 		calc_baud = clk / (cd * (bdiv + 1));
433 
434 		if (baud > calc_baud)
435 			bauderror = baud - calc_baud;
436 		else
437 			bauderror = calc_baud - baud;
438 
439 		if (besterror > bauderror) {
440 			*rbdiv = bdiv;
441 			*rcd = cd;
442 			bestbaud = calc_baud;
443 			besterror = bauderror;
444 		}
445 	}
446 	/* use the values when percent error is acceptable */
447 	if (((besterror * 100) / baud) < 3)
448 		bestbaud = baud;
449 
450 	return bestbaud;
451 }
452 
453 /**
454  * cdns_uart_set_baud_rate - Calculate and set the baud rate
455  * @port: Handle to the uart port structure
456  * @baud: Baud rate to set
457  * Return: baud rate, requested baud when possible, or actual baud when there
458  *	   was too much error, zero if no valid divisors are found.
459  */
460 static unsigned int cdns_uart_set_baud_rate(struct uart_port *port,
461 		unsigned int baud)
462 {
463 	unsigned int calc_baud;
464 	u32 cd = 0, bdiv = 0;
465 	u32 mreg;
466 	int div8;
467 	struct cdns_uart *cdns_uart = port->private_data;
468 
469 	calc_baud = cdns_uart_calc_baud_divs(port->uartclk, baud, &bdiv, &cd,
470 			&div8);
471 
472 	/* Write new divisors to hardware */
473 	mreg = readl(port->membase + CDNS_UART_MR);
474 	if (div8)
475 		mreg |= CDNS_UART_MR_CLKSEL;
476 	else
477 		mreg &= ~CDNS_UART_MR_CLKSEL;
478 	writel(mreg, port->membase + CDNS_UART_MR);
479 	writel(cd, port->membase + CDNS_UART_BAUDGEN);
480 	writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
481 	cdns_uart->baud = baud;
482 
483 	return calc_baud;
484 }
485 
486 #ifdef CONFIG_COMMON_CLK
487 /**
488  * cdns_uart_clk_notitifer_cb - Clock notifier callback
489  * @nb:		Notifier block
490  * @event:	Notify event
491  * @data:	Notifier data
492  * Return:	NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error.
493  */
494 static int cdns_uart_clk_notifier_cb(struct notifier_block *nb,
495 		unsigned long event, void *data)
496 {
497 	u32 ctrl_reg;
498 	struct uart_port *port;
499 	int locked = 0;
500 	struct clk_notifier_data *ndata = data;
501 	unsigned long flags = 0;
502 	struct cdns_uart *cdns_uart = to_cdns_uart(nb);
503 
504 	port = cdns_uart->port;
505 	if (port->suspended)
506 		return NOTIFY_OK;
507 
508 	switch (event) {
509 	case PRE_RATE_CHANGE:
510 	{
511 		u32 bdiv, cd;
512 		int div8;
513 
514 		/*
515 		 * Find out if current baud-rate can be achieved with new clock
516 		 * frequency.
517 		 */
518 		if (!cdns_uart_calc_baud_divs(ndata->new_rate, cdns_uart->baud,
519 					&bdiv, &cd, &div8)) {
520 			dev_warn(port->dev, "clock rate change rejected\n");
521 			return NOTIFY_BAD;
522 		}
523 
524 		spin_lock_irqsave(&cdns_uart->port->lock, flags);
525 
526 		/* Disable the TX and RX to set baud rate */
527 		ctrl_reg = readl(port->membase + CDNS_UART_CR);
528 		ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
529 		writel(ctrl_reg, port->membase + CDNS_UART_CR);
530 
531 		spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
532 
533 		return NOTIFY_OK;
534 	}
535 	case POST_RATE_CHANGE:
536 		/*
537 		 * Set clk dividers to generate correct baud with new clock
538 		 * frequency.
539 		 */
540 
541 		spin_lock_irqsave(&cdns_uart->port->lock, flags);
542 
543 		locked = 1;
544 		port->uartclk = ndata->new_rate;
545 
546 		cdns_uart->baud = cdns_uart_set_baud_rate(cdns_uart->port,
547 				cdns_uart->baud);
548 		fallthrough;
549 	case ABORT_RATE_CHANGE:
550 		if (!locked)
551 			spin_lock_irqsave(&cdns_uart->port->lock, flags);
552 
553 		/* Set TX/RX Reset */
554 		ctrl_reg = readl(port->membase + CDNS_UART_CR);
555 		ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
556 		writel(ctrl_reg, port->membase + CDNS_UART_CR);
557 
558 		while (readl(port->membase + CDNS_UART_CR) &
559 				(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
560 			cpu_relax();
561 
562 		/*
563 		 * Clear the RX disable and TX disable bits and then set the TX
564 		 * enable bit and RX enable bit to enable the transmitter and
565 		 * receiver.
566 		 */
567 		writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
568 		ctrl_reg = readl(port->membase + CDNS_UART_CR);
569 		ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
570 		ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
571 		writel(ctrl_reg, port->membase + CDNS_UART_CR);
572 
573 		spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
574 
575 		return NOTIFY_OK;
576 	default:
577 		return NOTIFY_DONE;
578 	}
579 }
580 #endif
581 
582 /**
583  * cdns_uart_start_tx -  Start transmitting bytes
584  * @port: Handle to the uart port structure
585  */
586 static void cdns_uart_start_tx(struct uart_port *port)
587 {
588 	unsigned int status;
589 
590 	if (uart_tx_stopped(port))
591 		return;
592 
593 	/*
594 	 * Set the TX enable bit and clear the TX disable bit to enable the
595 	 * transmitter.
596 	 */
597 	status = readl(port->membase + CDNS_UART_CR);
598 	status &= ~CDNS_UART_CR_TX_DIS;
599 	status |= CDNS_UART_CR_TX_EN;
600 	writel(status, port->membase + CDNS_UART_CR);
601 
602 	if (uart_circ_empty(&port->state->xmit))
603 		return;
604 
605 	cdns_uart_handle_tx(port);
606 
607 	writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR);
608 	/* Enable the TX Empty interrupt */
609 	writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IER);
610 }
611 
612 /**
613  * cdns_uart_stop_tx - Stop TX
614  * @port: Handle to the uart port structure
615  */
616 static void cdns_uart_stop_tx(struct uart_port *port)
617 {
618 	unsigned int regval;
619 
620 	regval = readl(port->membase + CDNS_UART_CR);
621 	regval |= CDNS_UART_CR_TX_DIS;
622 	/* Disable the transmitter */
623 	writel(regval, port->membase + CDNS_UART_CR);
624 }
625 
626 /**
627  * cdns_uart_stop_rx - Stop RX
628  * @port: Handle to the uart port structure
629  */
630 static void cdns_uart_stop_rx(struct uart_port *port)
631 {
632 	unsigned int regval;
633 
634 	/* Disable RX IRQs */
635 	writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IDR);
636 
637 	/* Disable the receiver */
638 	regval = readl(port->membase + CDNS_UART_CR);
639 	regval |= CDNS_UART_CR_RX_DIS;
640 	writel(regval, port->membase + CDNS_UART_CR);
641 }
642 
643 /**
644  * cdns_uart_tx_empty -  Check whether TX is empty
645  * @port: Handle to the uart port structure
646  *
647  * Return: TIOCSER_TEMT on success, 0 otherwise
648  */
649 static unsigned int cdns_uart_tx_empty(struct uart_port *port)
650 {
651 	unsigned int status;
652 
653 	status = readl(port->membase + CDNS_UART_SR) &
654 		       (CDNS_UART_SR_TXEMPTY | CDNS_UART_SR_TACTIVE);
655 	return (status == CDNS_UART_SR_TXEMPTY) ? TIOCSER_TEMT : 0;
656 }
657 
658 /**
659  * cdns_uart_break_ctl - Based on the input ctl we have to start or stop
660  *			transmitting char breaks
661  * @port: Handle to the uart port structure
662  * @ctl: Value based on which start or stop decision is taken
663  */
664 static void cdns_uart_break_ctl(struct uart_port *port, int ctl)
665 {
666 	unsigned int status;
667 	unsigned long flags;
668 
669 	spin_lock_irqsave(&port->lock, flags);
670 
671 	status = readl(port->membase + CDNS_UART_CR);
672 
673 	if (ctl == -1)
674 		writel(CDNS_UART_CR_STARTBRK | status,
675 				port->membase + CDNS_UART_CR);
676 	else {
677 		if ((status & CDNS_UART_CR_STOPBRK) == 0)
678 			writel(CDNS_UART_CR_STOPBRK | status,
679 					port->membase + CDNS_UART_CR);
680 	}
681 	spin_unlock_irqrestore(&port->lock, flags);
682 }
683 
684 /**
685  * cdns_uart_set_termios - termios operations, handling data length, parity,
686  *				stop bits, flow control, baud rate
687  * @port: Handle to the uart port structure
688  * @termios: Handle to the input termios structure
689  * @old: Values of the previously saved termios structure
690  */
691 static void cdns_uart_set_termios(struct uart_port *port,
692 				struct ktermios *termios, struct ktermios *old)
693 {
694 	u32 cval = 0;
695 	unsigned int baud, minbaud, maxbaud;
696 	unsigned long flags;
697 	unsigned int ctrl_reg, mode_reg;
698 
699 	spin_lock_irqsave(&port->lock, flags);
700 
701 	/* Disable the TX and RX to set baud rate */
702 	ctrl_reg = readl(port->membase + CDNS_UART_CR);
703 	ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
704 	writel(ctrl_reg, port->membase + CDNS_UART_CR);
705 
706 	/*
707 	 * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk
708 	 * min and max baud should be calculated here based on port->uartclk.
709 	 * this way we get a valid baud and can safely call set_baud()
710 	 */
711 	minbaud = port->uartclk /
712 			((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX * 8);
713 	maxbaud = port->uartclk / (CDNS_UART_BDIV_MIN + 1);
714 	baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud);
715 	baud = cdns_uart_set_baud_rate(port, baud);
716 	if (tty_termios_baud_rate(termios))
717 		tty_termios_encode_baud_rate(termios, baud, baud);
718 
719 	/* Update the per-port timeout. */
720 	uart_update_timeout(port, termios->c_cflag, baud);
721 
722 	/* Set TX/RX Reset */
723 	ctrl_reg = readl(port->membase + CDNS_UART_CR);
724 	ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
725 	writel(ctrl_reg, port->membase + CDNS_UART_CR);
726 
727 	while (readl(port->membase + CDNS_UART_CR) &
728 		(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
729 		cpu_relax();
730 
731 	/*
732 	 * Clear the RX disable and TX disable bits and then set the TX enable
733 	 * bit and RX enable bit to enable the transmitter and receiver.
734 	 */
735 	ctrl_reg = readl(port->membase + CDNS_UART_CR);
736 	ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
737 	ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
738 	writel(ctrl_reg, port->membase + CDNS_UART_CR);
739 
740 	writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
741 
742 	port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG |
743 			CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT;
744 	port->ignore_status_mask = 0;
745 
746 	if (termios->c_iflag & INPCK)
747 		port->read_status_mask |= CDNS_UART_IXR_PARITY |
748 		CDNS_UART_IXR_FRAMING;
749 
750 	if (termios->c_iflag & IGNPAR)
751 		port->ignore_status_mask |= CDNS_UART_IXR_PARITY |
752 			CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
753 
754 	/* ignore all characters if CREAD is not set */
755 	if ((termios->c_cflag & CREAD) == 0)
756 		port->ignore_status_mask |= CDNS_UART_IXR_RXTRIG |
757 			CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY |
758 			CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
759 
760 	mode_reg = readl(port->membase + CDNS_UART_MR);
761 
762 	/* Handling Data Size */
763 	switch (termios->c_cflag & CSIZE) {
764 	case CS6:
765 		cval |= CDNS_UART_MR_CHARLEN_6_BIT;
766 		break;
767 	case CS7:
768 		cval |= CDNS_UART_MR_CHARLEN_7_BIT;
769 		break;
770 	default:
771 	case CS8:
772 		cval |= CDNS_UART_MR_CHARLEN_8_BIT;
773 		termios->c_cflag &= ~CSIZE;
774 		termios->c_cflag |= CS8;
775 		break;
776 	}
777 
778 	/* Handling Parity and Stop Bits length */
779 	if (termios->c_cflag & CSTOPB)
780 		cval |= CDNS_UART_MR_STOPMODE_2_BIT; /* 2 STOP bits */
781 	else
782 		cval |= CDNS_UART_MR_STOPMODE_1_BIT; /* 1 STOP bit */
783 
784 	if (termios->c_cflag & PARENB) {
785 		/* Mark or Space parity */
786 		if (termios->c_cflag & CMSPAR) {
787 			if (termios->c_cflag & PARODD)
788 				cval |= CDNS_UART_MR_PARITY_MARK;
789 			else
790 				cval |= CDNS_UART_MR_PARITY_SPACE;
791 		} else {
792 			if (termios->c_cflag & PARODD)
793 				cval |= CDNS_UART_MR_PARITY_ODD;
794 			else
795 				cval |= CDNS_UART_MR_PARITY_EVEN;
796 		}
797 	} else {
798 		cval |= CDNS_UART_MR_PARITY_NONE;
799 	}
800 	cval |= mode_reg & 1;
801 	writel(cval, port->membase + CDNS_UART_MR);
802 
803 	cval = readl(port->membase + CDNS_UART_MODEMCR);
804 	if (termios->c_cflag & CRTSCTS)
805 		cval |= CDNS_UART_MODEMCR_FCM;
806 	else
807 		cval &= ~CDNS_UART_MODEMCR_FCM;
808 	writel(cval, port->membase + CDNS_UART_MODEMCR);
809 
810 	spin_unlock_irqrestore(&port->lock, flags);
811 }
812 
813 /**
814  * cdns_uart_startup - Called when an application opens a cdns_uart port
815  * @port: Handle to the uart port structure
816  *
817  * Return: 0 on success, negative errno otherwise
818  */
819 static int cdns_uart_startup(struct uart_port *port)
820 {
821 	struct cdns_uart *cdns_uart = port->private_data;
822 	bool is_brk_support;
823 	int ret;
824 	unsigned long flags;
825 	unsigned int status = 0;
826 
827 	is_brk_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
828 
829 	spin_lock_irqsave(&port->lock, flags);
830 
831 	/* Disable the TX and RX */
832 	writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
833 			port->membase + CDNS_UART_CR);
834 
835 	/* Set the Control Register with TX/RX Enable, TX/RX Reset,
836 	 * no break chars.
837 	 */
838 	writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST,
839 			port->membase + CDNS_UART_CR);
840 
841 	while (readl(port->membase + CDNS_UART_CR) &
842 		(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
843 		cpu_relax();
844 
845 	/*
846 	 * Clear the RX disable bit and then set the RX enable bit to enable
847 	 * the receiver.
848 	 */
849 	status = readl(port->membase + CDNS_UART_CR);
850 	status &= ~CDNS_UART_CR_RX_DIS;
851 	status |= CDNS_UART_CR_RX_EN;
852 	writel(status, port->membase + CDNS_UART_CR);
853 
854 	/* Set the Mode Register with normal mode,8 data bits,1 stop bit,
855 	 * no parity.
856 	 */
857 	writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT
858 		| CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT,
859 		port->membase + CDNS_UART_MR);
860 
861 	/*
862 	 * Set the RX FIFO Trigger level to use most of the FIFO, but it
863 	 * can be tuned with a module parameter
864 	 */
865 	writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
866 
867 	/*
868 	 * Receive Timeout register is enabled but it
869 	 * can be tuned with a module parameter
870 	 */
871 	writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
872 
873 	/* Clear out any pending interrupts before enabling them */
874 	writel(readl(port->membase + CDNS_UART_ISR),
875 			port->membase + CDNS_UART_ISR);
876 
877 	spin_unlock_irqrestore(&port->lock, flags);
878 
879 	ret = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME, port);
880 	if (ret) {
881 		dev_err(port->dev, "request_irq '%d' failed with %d\n",
882 			port->irq, ret);
883 		return ret;
884 	}
885 
886 	/* Set the Interrupt Registers with desired interrupts */
887 	if (is_brk_support)
888 		writel(CDNS_UART_RX_IRQS | CDNS_UART_IXR_BRK,
889 					port->membase + CDNS_UART_IER);
890 	else
891 		writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IER);
892 
893 	return 0;
894 }
895 
896 /**
897  * cdns_uart_shutdown - Called when an application closes a cdns_uart port
898  * @port: Handle to the uart port structure
899  */
900 static void cdns_uart_shutdown(struct uart_port *port)
901 {
902 	int status;
903 	unsigned long flags;
904 
905 	spin_lock_irqsave(&port->lock, flags);
906 
907 	/* Disable interrupts */
908 	status = readl(port->membase + CDNS_UART_IMR);
909 	writel(status, port->membase + CDNS_UART_IDR);
910 	writel(0xffffffff, port->membase + CDNS_UART_ISR);
911 
912 	/* Disable the TX and RX */
913 	writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
914 			port->membase + CDNS_UART_CR);
915 
916 	spin_unlock_irqrestore(&port->lock, flags);
917 
918 	free_irq(port->irq, port);
919 }
920 
921 /**
922  * cdns_uart_type - Set UART type to cdns_uart port
923  * @port: Handle to the uart port structure
924  *
925  * Return: string on success, NULL otherwise
926  */
927 static const char *cdns_uart_type(struct uart_port *port)
928 {
929 	return port->type == PORT_XUARTPS ? CDNS_UART_NAME : NULL;
930 }
931 
932 /**
933  * cdns_uart_verify_port - Verify the port params
934  * @port: Handle to the uart port structure
935  * @ser: Handle to the structure whose members are compared
936  *
937  * Return: 0 on success, negative errno otherwise.
938  */
939 static int cdns_uart_verify_port(struct uart_port *port,
940 					struct serial_struct *ser)
941 {
942 	if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS)
943 		return -EINVAL;
944 	if (port->irq != ser->irq)
945 		return -EINVAL;
946 	if (ser->io_type != UPIO_MEM)
947 		return -EINVAL;
948 	if (port->iobase != ser->port)
949 		return -EINVAL;
950 	if (ser->hub6 != 0)
951 		return -EINVAL;
952 	return 0;
953 }
954 
955 /**
956  * cdns_uart_request_port - Claim the memory region attached to cdns_uart port,
957  *				called when the driver adds a cdns_uart port via
958  *				uart_add_one_port()
959  * @port: Handle to the uart port structure
960  *
961  * Return: 0 on success, negative errno otherwise.
962  */
963 static int cdns_uart_request_port(struct uart_port *port)
964 {
965 	if (!request_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE,
966 					 CDNS_UART_NAME)) {
967 		return -ENOMEM;
968 	}
969 
970 	port->membase = ioremap(port->mapbase, CDNS_UART_REGISTER_SPACE);
971 	if (!port->membase) {
972 		dev_err(port->dev, "Unable to map registers\n");
973 		release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
974 		return -ENOMEM;
975 	}
976 	return 0;
977 }
978 
979 /**
980  * cdns_uart_release_port - Release UART port
981  * @port: Handle to the uart port structure
982  *
983  * Release the memory region attached to a cdns_uart port. Called when the
984  * driver removes a cdns_uart port via uart_remove_one_port().
985  */
986 static void cdns_uart_release_port(struct uart_port *port)
987 {
988 	release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
989 	iounmap(port->membase);
990 	port->membase = NULL;
991 }
992 
993 /**
994  * cdns_uart_config_port - Configure UART port
995  * @port: Handle to the uart port structure
996  * @flags: If any
997  */
998 static void cdns_uart_config_port(struct uart_port *port, int flags)
999 {
1000 	if (flags & UART_CONFIG_TYPE && cdns_uart_request_port(port) == 0)
1001 		port->type = PORT_XUARTPS;
1002 }
1003 
1004 /**
1005  * cdns_uart_get_mctrl - Get the modem control state
1006  * @port: Handle to the uart port structure
1007  *
1008  * Return: the modem control state
1009  */
1010 static unsigned int cdns_uart_get_mctrl(struct uart_port *port)
1011 {
1012 	u32 val;
1013 	unsigned int mctrl = 0;
1014 	struct cdns_uart *cdns_uart_data = port->private_data;
1015 
1016 	if (cdns_uart_data->cts_override)
1017 		return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
1018 
1019 	val = readl(port->membase + CDNS_UART_MODEMSR);
1020 	if (val & CDNS_UART_MODEMSR_CTS)
1021 		mctrl |= TIOCM_CTS;
1022 	if (val & CDNS_UART_MODEMSR_DSR)
1023 		mctrl |= TIOCM_DSR;
1024 	if (val & CDNS_UART_MODEMSR_RI)
1025 		mctrl |= TIOCM_RNG;
1026 	if (val & CDNS_UART_MODEMSR_DCD)
1027 		mctrl |= TIOCM_CAR;
1028 
1029 	return mctrl;
1030 }
1031 
1032 static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1033 {
1034 	u32 val;
1035 	u32 mode_reg;
1036 	struct cdns_uart *cdns_uart_data = port->private_data;
1037 
1038 	if (cdns_uart_data->cts_override)
1039 		return;
1040 
1041 	val = readl(port->membase + CDNS_UART_MODEMCR);
1042 	mode_reg = readl(port->membase + CDNS_UART_MR);
1043 
1044 	val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR);
1045 	mode_reg &= ~CDNS_UART_MR_CHMODE_MASK;
1046 
1047 	if (mctrl & TIOCM_RTS)
1048 		val |= CDNS_UART_MODEMCR_RTS;
1049 	if (mctrl & TIOCM_DTR)
1050 		val |= CDNS_UART_MODEMCR_DTR;
1051 	if (mctrl & TIOCM_LOOP)
1052 		mode_reg |= CDNS_UART_MR_CHMODE_L_LOOP;
1053 	else
1054 		mode_reg |= CDNS_UART_MR_CHMODE_NORM;
1055 
1056 	writel(val, port->membase + CDNS_UART_MODEMCR);
1057 	writel(mode_reg, port->membase + CDNS_UART_MR);
1058 }
1059 
1060 #ifdef CONFIG_CONSOLE_POLL
1061 static int cdns_uart_poll_get_char(struct uart_port *port)
1062 {
1063 	int c;
1064 	unsigned long flags;
1065 
1066 	spin_lock_irqsave(&port->lock, flags);
1067 
1068 	/* Check if FIFO is empty */
1069 	if (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_RXEMPTY)
1070 		c = NO_POLL_CHAR;
1071 	else /* Read a character */
1072 		c = (unsigned char) readl(port->membase + CDNS_UART_FIFO);
1073 
1074 	spin_unlock_irqrestore(&port->lock, flags);
1075 
1076 	return c;
1077 }
1078 
1079 static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c)
1080 {
1081 	unsigned long flags;
1082 
1083 	spin_lock_irqsave(&port->lock, flags);
1084 
1085 	/* Wait until FIFO is empty */
1086 	while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1087 		cpu_relax();
1088 
1089 	/* Write a character */
1090 	writel(c, port->membase + CDNS_UART_FIFO);
1091 
1092 	/* Wait until FIFO is empty */
1093 	while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1094 		cpu_relax();
1095 
1096 	spin_unlock_irqrestore(&port->lock, flags);
1097 }
1098 #endif
1099 
1100 static void cdns_uart_pm(struct uart_port *port, unsigned int state,
1101 		   unsigned int oldstate)
1102 {
1103 	switch (state) {
1104 	case UART_PM_STATE_OFF:
1105 		pm_runtime_mark_last_busy(port->dev);
1106 		pm_runtime_put_autosuspend(port->dev);
1107 		break;
1108 	default:
1109 		pm_runtime_get_sync(port->dev);
1110 		break;
1111 	}
1112 }
1113 
1114 static const struct uart_ops cdns_uart_ops = {
1115 	.set_mctrl	= cdns_uart_set_mctrl,
1116 	.get_mctrl	= cdns_uart_get_mctrl,
1117 	.start_tx	= cdns_uart_start_tx,
1118 	.stop_tx	= cdns_uart_stop_tx,
1119 	.stop_rx	= cdns_uart_stop_rx,
1120 	.tx_empty	= cdns_uart_tx_empty,
1121 	.break_ctl	= cdns_uart_break_ctl,
1122 	.set_termios	= cdns_uart_set_termios,
1123 	.startup	= cdns_uart_startup,
1124 	.shutdown	= cdns_uart_shutdown,
1125 	.pm		= cdns_uart_pm,
1126 	.type		= cdns_uart_type,
1127 	.verify_port	= cdns_uart_verify_port,
1128 	.request_port	= cdns_uart_request_port,
1129 	.release_port	= cdns_uart_release_port,
1130 	.config_port	= cdns_uart_config_port,
1131 #ifdef CONFIG_CONSOLE_POLL
1132 	.poll_get_char	= cdns_uart_poll_get_char,
1133 	.poll_put_char	= cdns_uart_poll_put_char,
1134 #endif
1135 };
1136 
1137 static struct uart_driver cdns_uart_uart_driver;
1138 
1139 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1140 /**
1141  * cdns_uart_console_putchar - write the character to the FIFO buffer
1142  * @port: Handle to the uart port structure
1143  * @ch: Character to be written
1144  */
1145 static void cdns_uart_console_putchar(struct uart_port *port, int ch)
1146 {
1147 	while (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL)
1148 		cpu_relax();
1149 	writel(ch, port->membase + CDNS_UART_FIFO);
1150 }
1151 
1152 static void cdns_early_write(struct console *con, const char *s,
1153 				    unsigned n)
1154 {
1155 	struct earlycon_device *dev = con->data;
1156 
1157 	uart_console_write(&dev->port, s, n, cdns_uart_console_putchar);
1158 }
1159 
1160 static int __init cdns_early_console_setup(struct earlycon_device *device,
1161 					   const char *opt)
1162 {
1163 	struct uart_port *port = &device->port;
1164 
1165 	if (!port->membase)
1166 		return -ENODEV;
1167 
1168 	/* initialise control register */
1169 	writel(CDNS_UART_CR_TX_EN|CDNS_UART_CR_TXRST|CDNS_UART_CR_RXRST,
1170 	       port->membase + CDNS_UART_CR);
1171 
1172 	/* only set baud if specified on command line - otherwise
1173 	 * assume it has been initialized by a boot loader.
1174 	 */
1175 	if (port->uartclk && device->baud) {
1176 		u32 cd = 0, bdiv = 0;
1177 		u32 mr;
1178 		int div8;
1179 
1180 		cdns_uart_calc_baud_divs(port->uartclk, device->baud,
1181 					 &bdiv, &cd, &div8);
1182 		mr = CDNS_UART_MR_PARITY_NONE;
1183 		if (div8)
1184 			mr |= CDNS_UART_MR_CLKSEL;
1185 
1186 		writel(mr,   port->membase + CDNS_UART_MR);
1187 		writel(cd,   port->membase + CDNS_UART_BAUDGEN);
1188 		writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
1189 	}
1190 
1191 	device->con->write = cdns_early_write;
1192 
1193 	return 0;
1194 }
1195 OF_EARLYCON_DECLARE(cdns, "xlnx,xuartps", cdns_early_console_setup);
1196 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p8", cdns_early_console_setup);
1197 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p12", cdns_early_console_setup);
1198 OF_EARLYCON_DECLARE(cdns, "xlnx,zynqmp-uart", cdns_early_console_setup);
1199 
1200 
1201 /* Static pointer to console port */
1202 static struct uart_port *console_port;
1203 
1204 /**
1205  * cdns_uart_console_write - perform write operation
1206  * @co: Console handle
1207  * @s: Pointer to character array
1208  * @count: No of characters
1209  */
1210 static void cdns_uart_console_write(struct console *co, const char *s,
1211 				unsigned int count)
1212 {
1213 	struct uart_port *port = console_port;
1214 	unsigned long flags = 0;
1215 	unsigned int imr, ctrl;
1216 	int locked = 1;
1217 
1218 	if (port->sysrq)
1219 		locked = 0;
1220 	else if (oops_in_progress)
1221 		locked = spin_trylock_irqsave(&port->lock, flags);
1222 	else
1223 		spin_lock_irqsave(&port->lock, flags);
1224 
1225 	/* save and disable interrupt */
1226 	imr = readl(port->membase + CDNS_UART_IMR);
1227 	writel(imr, port->membase + CDNS_UART_IDR);
1228 
1229 	/*
1230 	 * Make sure that the tx part is enabled. Set the TX enable bit and
1231 	 * clear the TX disable bit to enable the transmitter.
1232 	 */
1233 	ctrl = readl(port->membase + CDNS_UART_CR);
1234 	ctrl &= ~CDNS_UART_CR_TX_DIS;
1235 	ctrl |= CDNS_UART_CR_TX_EN;
1236 	writel(ctrl, port->membase + CDNS_UART_CR);
1237 
1238 	uart_console_write(port, s, count, cdns_uart_console_putchar);
1239 	while (cdns_uart_tx_empty(port) != TIOCSER_TEMT)
1240 		cpu_relax();
1241 
1242 	/* restore interrupt state */
1243 	writel(imr, port->membase + CDNS_UART_IER);
1244 
1245 	if (locked)
1246 		spin_unlock_irqrestore(&port->lock, flags);
1247 }
1248 
1249 /**
1250  * cdns_uart_console_setup - Initialize the uart to default config
1251  * @co: Console handle
1252  * @options: Initial settings of uart
1253  *
1254  * Return: 0 on success, negative errno otherwise.
1255  */
1256 static int cdns_uart_console_setup(struct console *co, char *options)
1257 {
1258 	struct uart_port *port = console_port;
1259 
1260 	int baud = 9600;
1261 	int bits = 8;
1262 	int parity = 'n';
1263 	int flow = 'n';
1264 	unsigned long time_out;
1265 
1266 	if (!port->membase) {
1267 		pr_debug("console on " CDNS_UART_TTY_NAME "%i not present\n",
1268 			 co->index);
1269 		return -ENODEV;
1270 	}
1271 
1272 	if (options)
1273 		uart_parse_options(options, &baud, &parity, &bits, &flow);
1274 
1275 	/* Wait for tx_empty before setting up the console */
1276 	time_out = jiffies + usecs_to_jiffies(TX_TIMEOUT);
1277 
1278 	while (time_before(jiffies, time_out) &&
1279 	       cdns_uart_tx_empty(port) != TIOCSER_TEMT)
1280 		cpu_relax();
1281 
1282 	return uart_set_options(port, co, baud, parity, bits, flow);
1283 }
1284 
1285 static struct console cdns_uart_console = {
1286 	.name	= CDNS_UART_TTY_NAME,
1287 	.write	= cdns_uart_console_write,
1288 	.device	= uart_console_device,
1289 	.setup	= cdns_uart_console_setup,
1290 	.flags	= CON_PRINTBUFFER,
1291 	.index	= -1, /* Specified on the cmdline (e.g. console=ttyPS ) */
1292 	.data	= &cdns_uart_uart_driver,
1293 };
1294 #endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */
1295 
1296 #ifdef CONFIG_PM_SLEEP
1297 /**
1298  * cdns_uart_suspend - suspend event
1299  * @device: Pointer to the device structure
1300  *
1301  * Return: 0
1302  */
1303 static int cdns_uart_suspend(struct device *device)
1304 {
1305 	struct uart_port *port = dev_get_drvdata(device);
1306 	struct cdns_uart *cdns_uart = port->private_data;
1307 	int may_wake;
1308 
1309 	may_wake = device_may_wakeup(device);
1310 
1311 	if (console_suspend_enabled && uart_console(port) && may_wake) {
1312 		unsigned long flags = 0;
1313 
1314 		spin_lock_irqsave(&port->lock, flags);
1315 		/* Empty the receive FIFO 1st before making changes */
1316 		while (!(readl(port->membase + CDNS_UART_SR) &
1317 					CDNS_UART_SR_RXEMPTY))
1318 			readl(port->membase + CDNS_UART_FIFO);
1319 		/* set RX trigger level to 1 */
1320 		writel(1, port->membase + CDNS_UART_RXWM);
1321 		/* disable RX timeout interrups */
1322 		writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IDR);
1323 		spin_unlock_irqrestore(&port->lock, flags);
1324 	}
1325 
1326 	/*
1327 	 * Call the API provided in serial_core.c file which handles
1328 	 * the suspend.
1329 	 */
1330 	return uart_suspend_port(cdns_uart->cdns_uart_driver, port);
1331 }
1332 
1333 /**
1334  * cdns_uart_resume - Resume after a previous suspend
1335  * @device: Pointer to the device structure
1336  *
1337  * Return: 0
1338  */
1339 static int cdns_uart_resume(struct device *device)
1340 {
1341 	struct uart_port *port = dev_get_drvdata(device);
1342 	struct cdns_uart *cdns_uart = port->private_data;
1343 	unsigned long flags = 0;
1344 	u32 ctrl_reg;
1345 	int may_wake;
1346 
1347 	may_wake = device_may_wakeup(device);
1348 
1349 	if (console_suspend_enabled && uart_console(port) && !may_wake) {
1350 		clk_enable(cdns_uart->pclk);
1351 		clk_enable(cdns_uart->uartclk);
1352 
1353 		spin_lock_irqsave(&port->lock, flags);
1354 
1355 		/* Set TX/RX Reset */
1356 		ctrl_reg = readl(port->membase + CDNS_UART_CR);
1357 		ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
1358 		writel(ctrl_reg, port->membase + CDNS_UART_CR);
1359 		while (readl(port->membase + CDNS_UART_CR) &
1360 				(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
1361 			cpu_relax();
1362 
1363 		/* restore rx timeout value */
1364 		writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
1365 		/* Enable Tx/Rx */
1366 		ctrl_reg = readl(port->membase + CDNS_UART_CR);
1367 		ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
1368 		ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
1369 		writel(ctrl_reg, port->membase + CDNS_UART_CR);
1370 
1371 		clk_disable(cdns_uart->uartclk);
1372 		clk_disable(cdns_uart->pclk);
1373 		spin_unlock_irqrestore(&port->lock, flags);
1374 	} else {
1375 		spin_lock_irqsave(&port->lock, flags);
1376 		/* restore original rx trigger level */
1377 		writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
1378 		/* enable RX timeout interrupt */
1379 		writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IER);
1380 		spin_unlock_irqrestore(&port->lock, flags);
1381 	}
1382 
1383 	return uart_resume_port(cdns_uart->cdns_uart_driver, port);
1384 }
1385 #endif /* ! CONFIG_PM_SLEEP */
1386 static int __maybe_unused cdns_runtime_suspend(struct device *dev)
1387 {
1388 	struct uart_port *port = dev_get_drvdata(dev);
1389 	struct cdns_uart *cdns_uart = port->private_data;
1390 
1391 	clk_disable(cdns_uart->uartclk);
1392 	clk_disable(cdns_uart->pclk);
1393 	return 0;
1394 };
1395 
1396 static int __maybe_unused cdns_runtime_resume(struct device *dev)
1397 {
1398 	struct uart_port *port = dev_get_drvdata(dev);
1399 	struct cdns_uart *cdns_uart = port->private_data;
1400 
1401 	clk_enable(cdns_uart->pclk);
1402 	clk_enable(cdns_uart->uartclk);
1403 	return 0;
1404 };
1405 
1406 static const struct dev_pm_ops cdns_uart_dev_pm_ops = {
1407 	SET_SYSTEM_SLEEP_PM_OPS(cdns_uart_suspend, cdns_uart_resume)
1408 	SET_RUNTIME_PM_OPS(cdns_runtime_suspend,
1409 			   cdns_runtime_resume, NULL)
1410 };
1411 
1412 static const struct cdns_platform_data zynqmp_uart_def = {
1413 				.quirks = CDNS_UART_RXBS_SUPPORT, };
1414 
1415 /* Match table for of_platform binding */
1416 static const struct of_device_id cdns_uart_of_match[] = {
1417 	{ .compatible = "xlnx,xuartps", },
1418 	{ .compatible = "cdns,uart-r1p8", },
1419 	{ .compatible = "cdns,uart-r1p12", .data = &zynqmp_uart_def },
1420 	{ .compatible = "xlnx,zynqmp-uart", .data = &zynqmp_uart_def },
1421 	{}
1422 };
1423 MODULE_DEVICE_TABLE(of, cdns_uart_of_match);
1424 
1425 /* Temporary variable for storing number of instances */
1426 static int instances;
1427 
1428 /**
1429  * cdns_uart_probe - Platform driver probe
1430  * @pdev: Pointer to the platform device structure
1431  *
1432  * Return: 0 on success, negative errno otherwise
1433  */
1434 static int cdns_uart_probe(struct platform_device *pdev)
1435 {
1436 	int rc, id, irq;
1437 	struct uart_port *port;
1438 	struct resource *res;
1439 	struct cdns_uart *cdns_uart_data;
1440 	const struct of_device_id *match;
1441 
1442 	cdns_uart_data = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_data),
1443 			GFP_KERNEL);
1444 	if (!cdns_uart_data)
1445 		return -ENOMEM;
1446 	port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
1447 	if (!port)
1448 		return -ENOMEM;
1449 
1450 	/* Look for a serialN alias */
1451 	id = of_alias_get_id(pdev->dev.of_node, "serial");
1452 	if (id < 0)
1453 		id = 0;
1454 
1455 	if (id >= CDNS_UART_NR_PORTS) {
1456 		dev_err(&pdev->dev, "Cannot get uart_port structure\n");
1457 		return -ENODEV;
1458 	}
1459 
1460 	if (!cdns_uart_uart_driver.state) {
1461 		cdns_uart_uart_driver.owner = THIS_MODULE;
1462 		cdns_uart_uart_driver.driver_name = CDNS_UART_NAME;
1463 		cdns_uart_uart_driver.dev_name = CDNS_UART_TTY_NAME;
1464 		cdns_uart_uart_driver.major = CDNS_UART_MAJOR;
1465 		cdns_uart_uart_driver.minor = CDNS_UART_MINOR;
1466 		cdns_uart_uart_driver.nr = CDNS_UART_NR_PORTS;
1467 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1468 		cdns_uart_uart_driver.cons = &cdns_uart_console;
1469 #endif
1470 
1471 		rc = uart_register_driver(&cdns_uart_uart_driver);
1472 		if (rc < 0) {
1473 			dev_err(&pdev->dev, "Failed to register driver\n");
1474 			return rc;
1475 		}
1476 	}
1477 
1478 	cdns_uart_data->cdns_uart_driver = &cdns_uart_uart_driver;
1479 
1480 	match = of_match_node(cdns_uart_of_match, pdev->dev.of_node);
1481 	if (match && match->data) {
1482 		const struct cdns_platform_data *data = match->data;
1483 
1484 		cdns_uart_data->quirks = data->quirks;
1485 	}
1486 
1487 	cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "pclk");
1488 	if (PTR_ERR(cdns_uart_data->pclk) == -EPROBE_DEFER) {
1489 		rc = PTR_ERR(cdns_uart_data->pclk);
1490 		goto err_out_unregister_driver;
1491 	}
1492 
1493 	if (IS_ERR(cdns_uart_data->pclk)) {
1494 		cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "aper_clk");
1495 		if (IS_ERR(cdns_uart_data->pclk)) {
1496 			rc = PTR_ERR(cdns_uart_data->pclk);
1497 			goto err_out_unregister_driver;
1498 		}
1499 		dev_err(&pdev->dev, "clock name 'aper_clk' is deprecated.\n");
1500 	}
1501 
1502 	cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "uart_clk");
1503 	if (PTR_ERR(cdns_uart_data->uartclk) == -EPROBE_DEFER) {
1504 		rc = PTR_ERR(cdns_uart_data->uartclk);
1505 		goto err_out_unregister_driver;
1506 	}
1507 
1508 	if (IS_ERR(cdns_uart_data->uartclk)) {
1509 		cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "ref_clk");
1510 		if (IS_ERR(cdns_uart_data->uartclk)) {
1511 			rc = PTR_ERR(cdns_uart_data->uartclk);
1512 			goto err_out_unregister_driver;
1513 		}
1514 		dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n");
1515 	}
1516 
1517 	rc = clk_prepare_enable(cdns_uart_data->pclk);
1518 	if (rc) {
1519 		dev_err(&pdev->dev, "Unable to enable pclk clock.\n");
1520 		goto err_out_unregister_driver;
1521 	}
1522 	rc = clk_prepare_enable(cdns_uart_data->uartclk);
1523 	if (rc) {
1524 		dev_err(&pdev->dev, "Unable to enable device clock.\n");
1525 		goto err_out_clk_dis_pclk;
1526 	}
1527 
1528 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1529 	if (!res) {
1530 		rc = -ENODEV;
1531 		goto err_out_clk_disable;
1532 	}
1533 
1534 	irq = platform_get_irq(pdev, 0);
1535 	if (irq <= 0) {
1536 		rc = -ENXIO;
1537 		goto err_out_clk_disable;
1538 	}
1539 
1540 #ifdef CONFIG_COMMON_CLK
1541 	cdns_uart_data->clk_rate_change_nb.notifier_call =
1542 			cdns_uart_clk_notifier_cb;
1543 	if (clk_notifier_register(cdns_uart_data->uartclk,
1544 				&cdns_uart_data->clk_rate_change_nb))
1545 		dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
1546 #endif
1547 
1548 	/* At this point, we've got an empty uart_port struct, initialize it */
1549 	spin_lock_init(&port->lock);
1550 	port->type	= PORT_UNKNOWN;
1551 	port->iotype	= UPIO_MEM32;
1552 	port->flags	= UPF_BOOT_AUTOCONF;
1553 	port->ops	= &cdns_uart_ops;
1554 	port->fifosize	= CDNS_UART_FIFO_SIZE;
1555 	port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE);
1556 	port->line	= id;
1557 
1558 	/*
1559 	 * Register the port.
1560 	 * This function also registers this device with the tty layer
1561 	 * and triggers invocation of the config_port() entry point.
1562 	 */
1563 	port->mapbase = res->start;
1564 	port->irq = irq;
1565 	port->dev = &pdev->dev;
1566 	port->uartclk = clk_get_rate(cdns_uart_data->uartclk);
1567 	port->private_data = cdns_uart_data;
1568 	cdns_uart_data->port = port;
1569 	platform_set_drvdata(pdev, port);
1570 
1571 	pm_runtime_use_autosuspend(&pdev->dev);
1572 	pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT);
1573 	pm_runtime_set_active(&pdev->dev);
1574 	pm_runtime_enable(&pdev->dev);
1575 	device_init_wakeup(port->dev, true);
1576 
1577 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1578 	/*
1579 	 * If console hasn't been found yet try to assign this port
1580 	 * because it is required to be assigned for console setup function.
1581 	 * If register_console() don't assign value, then console_port pointer
1582 	 * is cleanup.
1583 	 */
1584 	if (!console_port) {
1585 		cdns_uart_console.index = id;
1586 		console_port = port;
1587 	}
1588 #endif
1589 
1590 	rc = uart_add_one_port(&cdns_uart_uart_driver, port);
1591 	if (rc) {
1592 		dev_err(&pdev->dev,
1593 			"uart_add_one_port() failed; err=%i\n", rc);
1594 		goto err_out_pm_disable;
1595 	}
1596 
1597 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1598 	/* This is not port which is used for console that's why clean it up */
1599 	if (console_port == port &&
1600 	    !(cdns_uart_uart_driver.cons->flags & CON_ENABLED)) {
1601 		console_port = NULL;
1602 		cdns_uart_console.index = -1;
1603 	}
1604 #endif
1605 
1606 	cdns_uart_data->cts_override = of_property_read_bool(pdev->dev.of_node,
1607 							     "cts-override");
1608 
1609 	instances++;
1610 
1611 	return 0;
1612 
1613 err_out_pm_disable:
1614 	pm_runtime_disable(&pdev->dev);
1615 	pm_runtime_set_suspended(&pdev->dev);
1616 	pm_runtime_dont_use_autosuspend(&pdev->dev);
1617 #ifdef CONFIG_COMMON_CLK
1618 	clk_notifier_unregister(cdns_uart_data->uartclk,
1619 			&cdns_uart_data->clk_rate_change_nb);
1620 #endif
1621 err_out_clk_disable:
1622 	clk_disable_unprepare(cdns_uart_data->uartclk);
1623 err_out_clk_dis_pclk:
1624 	clk_disable_unprepare(cdns_uart_data->pclk);
1625 err_out_unregister_driver:
1626 	if (!instances)
1627 		uart_unregister_driver(cdns_uart_data->cdns_uart_driver);
1628 	return rc;
1629 }
1630 
1631 /**
1632  * cdns_uart_remove - called when the platform driver is unregistered
1633  * @pdev: Pointer to the platform device structure
1634  *
1635  * Return: 0 on success, negative errno otherwise
1636  */
1637 static int cdns_uart_remove(struct platform_device *pdev)
1638 {
1639 	struct uart_port *port = platform_get_drvdata(pdev);
1640 	struct cdns_uart *cdns_uart_data = port->private_data;
1641 	int rc;
1642 
1643 	/* Remove the cdns_uart port from the serial core */
1644 #ifdef CONFIG_COMMON_CLK
1645 	clk_notifier_unregister(cdns_uart_data->uartclk,
1646 			&cdns_uart_data->clk_rate_change_nb);
1647 #endif
1648 	rc = uart_remove_one_port(cdns_uart_data->cdns_uart_driver, port);
1649 	port->mapbase = 0;
1650 	clk_disable_unprepare(cdns_uart_data->uartclk);
1651 	clk_disable_unprepare(cdns_uart_data->pclk);
1652 	pm_runtime_disable(&pdev->dev);
1653 	pm_runtime_set_suspended(&pdev->dev);
1654 	pm_runtime_dont_use_autosuspend(&pdev->dev);
1655 	device_init_wakeup(&pdev->dev, false);
1656 
1657 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1658 	if (console_port == port)
1659 		console_port = NULL;
1660 #endif
1661 
1662 	if (!--instances)
1663 		uart_unregister_driver(cdns_uart_data->cdns_uart_driver);
1664 	return rc;
1665 }
1666 
1667 static struct platform_driver cdns_uart_platform_driver = {
1668 	.probe   = cdns_uart_probe,
1669 	.remove  = cdns_uart_remove,
1670 	.driver  = {
1671 		.name = CDNS_UART_NAME,
1672 		.of_match_table = cdns_uart_of_match,
1673 		.pm = &cdns_uart_dev_pm_ops,
1674 		.suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_XILINX_PS_UART),
1675 		},
1676 };
1677 
1678 static int __init cdns_uart_init(void)
1679 {
1680 	/* Register the platform driver */
1681 	return platform_driver_register(&cdns_uart_platform_driver);
1682 }
1683 
1684 static void __exit cdns_uart_exit(void)
1685 {
1686 	/* Unregister the platform driver */
1687 	platform_driver_unregister(&cdns_uart_platform_driver);
1688 }
1689 
1690 arch_initcall(cdns_uart_init);
1691 module_exit(cdns_uart_exit);
1692 
1693 MODULE_DESCRIPTION("Driver for Cadence UART");
1694 MODULE_AUTHOR("Xilinx Inc.");
1695 MODULE_LICENSE("GPL");
1696