1 /* 2 * Cadence UART driver (found in Xilinx Zynq) 3 * 4 * 2011 - 2014 (C) Xilinx Inc. 5 * 6 * This program is free software; you can redistribute it 7 * and/or modify it under the terms of the GNU General Public 8 * License as published by the Free Software Foundation; 9 * either version 2 of the License, or (at your option) any 10 * later version. 11 * 12 * This driver has originally been pushed by Xilinx using a Zynq-branding. This 13 * still shows in the naming of this file, the kconfig symbols and some symbols 14 * in the code. 15 */ 16 17 #if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 18 #define SUPPORT_SYSRQ 19 #endif 20 21 #include <linux/platform_device.h> 22 #include <linux/serial.h> 23 #include <linux/console.h> 24 #include <linux/serial_core.h> 25 #include <linux/slab.h> 26 #include <linux/tty.h> 27 #include <linux/tty_flip.h> 28 #include <linux/clk.h> 29 #include <linux/irq.h> 30 #include <linux/io.h> 31 #include <linux/of.h> 32 #include <linux/module.h> 33 34 #define CDNS_UART_TTY_NAME "ttyPS" 35 #define CDNS_UART_NAME "xuartps" 36 #define CDNS_UART_MAJOR 0 /* use dynamic node allocation */ 37 #define CDNS_UART_MINOR 0 /* works best with devtmpfs */ 38 #define CDNS_UART_NR_PORTS 2 39 #define CDNS_UART_FIFO_SIZE 64 /* FIFO size */ 40 #define CDNS_UART_REGISTER_SPACE 0x1000 41 42 /* Rx Trigger level */ 43 static int rx_trigger_level = 56; 44 module_param(rx_trigger_level, uint, S_IRUGO); 45 MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes"); 46 47 /* Rx Timeout */ 48 static int rx_timeout = 10; 49 module_param(rx_timeout, uint, S_IRUGO); 50 MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255"); 51 52 /* Register offsets for the UART. */ 53 #define CDNS_UART_CR 0x00 /* Control Register */ 54 #define CDNS_UART_MR 0x04 /* Mode Register */ 55 #define CDNS_UART_IER 0x08 /* Interrupt Enable */ 56 #define CDNS_UART_IDR 0x0C /* Interrupt Disable */ 57 #define CDNS_UART_IMR 0x10 /* Interrupt Mask */ 58 #define CDNS_UART_ISR 0x14 /* Interrupt Status */ 59 #define CDNS_UART_BAUDGEN 0x18 /* Baud Rate Generator */ 60 #define CDNS_UART_RXTOUT 0x1C /* RX Timeout */ 61 #define CDNS_UART_RXWM 0x20 /* RX FIFO Trigger Level */ 62 #define CDNS_UART_MODEMCR 0x24 /* Modem Control */ 63 #define CDNS_UART_MODEMSR 0x28 /* Modem Status */ 64 #define CDNS_UART_SR 0x2C /* Channel Status */ 65 #define CDNS_UART_FIFO 0x30 /* FIFO */ 66 #define CDNS_UART_BAUDDIV 0x34 /* Baud Rate Divider */ 67 #define CDNS_UART_FLOWDEL 0x38 /* Flow Delay */ 68 #define CDNS_UART_IRRX_PWIDTH 0x3C /* IR Min Received Pulse Width */ 69 #define CDNS_UART_IRTX_PWIDTH 0x40 /* IR Transmitted pulse Width */ 70 #define CDNS_UART_TXWM 0x44 /* TX FIFO Trigger Level */ 71 #define CDNS_UART_RXBS 0x48 /* RX FIFO byte status register */ 72 73 /* Control Register Bit Definitions */ 74 #define CDNS_UART_CR_STOPBRK 0x00000100 /* Stop TX break */ 75 #define CDNS_UART_CR_STARTBRK 0x00000080 /* Set TX break */ 76 #define CDNS_UART_CR_TX_DIS 0x00000020 /* TX disabled. */ 77 #define CDNS_UART_CR_TX_EN 0x00000010 /* TX enabled */ 78 #define CDNS_UART_CR_RX_DIS 0x00000008 /* RX disabled. */ 79 #define CDNS_UART_CR_RX_EN 0x00000004 /* RX enabled */ 80 #define CDNS_UART_CR_TXRST 0x00000002 /* TX logic reset */ 81 #define CDNS_UART_CR_RXRST 0x00000001 /* RX logic reset */ 82 #define CDNS_UART_CR_RST_TO 0x00000040 /* Restart Timeout Counter */ 83 #define CDNS_UART_RXBS_PARITY 0x00000001 /* Parity error status */ 84 #define CDNS_UART_RXBS_FRAMING 0x00000002 /* Framing error status */ 85 #define CDNS_UART_RXBS_BRK 0x00000004 /* Overrun error status */ 86 87 /* 88 * Mode Register: 89 * The mode register (MR) defines the mode of transfer as well as the data 90 * format. If this register is modified during transmission or reception, 91 * data validity cannot be guaranteed. 92 */ 93 #define CDNS_UART_MR_CLKSEL 0x00000001 /* Pre-scalar selection */ 94 #define CDNS_UART_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */ 95 #define CDNS_UART_MR_CHMODE_NORM 0x00000000 /* Normal mode */ 96 #define CDNS_UART_MR_CHMODE_MASK 0x00000300 /* Mask for mode bits */ 97 98 #define CDNS_UART_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */ 99 #define CDNS_UART_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */ 100 101 #define CDNS_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */ 102 #define CDNS_UART_MR_PARITY_MARK 0x00000018 /* Mark parity mode */ 103 #define CDNS_UART_MR_PARITY_SPACE 0x00000010 /* Space parity mode */ 104 #define CDNS_UART_MR_PARITY_ODD 0x00000008 /* Odd parity mode */ 105 #define CDNS_UART_MR_PARITY_EVEN 0x00000000 /* Even parity mode */ 106 107 #define CDNS_UART_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */ 108 #define CDNS_UART_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */ 109 #define CDNS_UART_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */ 110 111 /* 112 * Interrupt Registers: 113 * Interrupt control logic uses the interrupt enable register (IER) and the 114 * interrupt disable register (IDR) to set the value of the bits in the 115 * interrupt mask register (IMR). The IMR determines whether to pass an 116 * interrupt to the interrupt status register (ISR). 117 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an 118 * interrupt. IMR and ISR are read only, and IER and IDR are write only. 119 * Reading either IER or IDR returns 0x00. 120 * All four registers have the same bit definitions. 121 */ 122 #define CDNS_UART_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */ 123 #define CDNS_UART_IXR_PARITY 0x00000080 /* Parity error interrupt */ 124 #define CDNS_UART_IXR_FRAMING 0x00000040 /* Framing error interrupt */ 125 #define CDNS_UART_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */ 126 #define CDNS_UART_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */ 127 #define CDNS_UART_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */ 128 #define CDNS_UART_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */ 129 #define CDNS_UART_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */ 130 #define CDNS_UART_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */ 131 #define CDNS_UART_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */ 132 #define CDNS_UART_IXR_MASK 0x00001FFF /* Valid bit mask */ 133 134 /* 135 * Do not enable parity error interrupt for the following 136 * reason: When parity error interrupt is enabled, each Rx 137 * parity error always results in 2 events. The first one 138 * being parity error interrupt and the second one with a 139 * proper Rx interrupt with the incoming data. Disabling 140 * parity error interrupt ensures better handling of parity 141 * error events. With this change, for a parity error case, we 142 * get a Rx interrupt with parity error set in ISR register 143 * and we still handle parity errors in the desired way. 144 */ 145 146 #define CDNS_UART_RX_IRQS (CDNS_UART_IXR_FRAMING | \ 147 CDNS_UART_IXR_OVERRUN | \ 148 CDNS_UART_IXR_RXTRIG | \ 149 CDNS_UART_IXR_TOUT) 150 151 /* Goes in read_status_mask for break detection as the HW doesn't do it*/ 152 #define CDNS_UART_IXR_BRK 0x00002000 153 154 #define CDNS_UART_RXBS_SUPPORT BIT(1) 155 /* 156 * Modem Control register: 157 * The read/write Modem Control register controls the interface with the modem 158 * or data set, or a peripheral device emulating a modem. 159 */ 160 #define CDNS_UART_MODEMCR_FCM 0x00000020 /* Automatic flow control mode */ 161 #define CDNS_UART_MODEMCR_RTS 0x00000002 /* Request to send output control */ 162 #define CDNS_UART_MODEMCR_DTR 0x00000001 /* Data Terminal Ready */ 163 164 /* 165 * Channel Status Register: 166 * The channel status register (CSR) is provided to enable the control logic 167 * to monitor the status of bits in the channel interrupt status register, 168 * even if these are masked out by the interrupt mask register. 169 */ 170 #define CDNS_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */ 171 #define CDNS_UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */ 172 #define CDNS_UART_SR_TXFULL 0x00000010 /* TX FIFO full */ 173 #define CDNS_UART_SR_RXTRIG 0x00000001 /* Rx Trigger */ 174 175 /* baud dividers min/max values */ 176 #define CDNS_UART_BDIV_MIN 4 177 #define CDNS_UART_BDIV_MAX 255 178 #define CDNS_UART_CD_MAX 65535 179 180 /** 181 * struct cdns_uart - device data 182 * @port: Pointer to the UART port 183 * @uartclk: Reference clock 184 * @pclk: APB clock 185 * @baud: Current baud rate 186 * @clk_rate_change_nb: Notifier block for clock changes 187 */ 188 struct cdns_uart { 189 struct uart_port *port; 190 struct clk *uartclk; 191 struct clk *pclk; 192 unsigned int baud; 193 struct notifier_block clk_rate_change_nb; 194 u32 quirks; 195 }; 196 struct cdns_platform_data { 197 u32 quirks; 198 }; 199 #define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \ 200 clk_rate_change_nb); 201 202 /** 203 * cdns_uart_handle_rx - Handle the received bytes along with Rx errors. 204 * @dev_id: Id of the UART port 205 * @isrstatus: The interrupt status register value as read 206 * Return: None 207 */ 208 static void cdns_uart_handle_rx(void *dev_id, unsigned int isrstatus) 209 { 210 struct uart_port *port = (struct uart_port *)dev_id; 211 struct cdns_uart *cdns_uart = port->private_data; 212 unsigned int data; 213 unsigned int rxbs_status = 0; 214 unsigned int status_mask; 215 unsigned int framerrprocessed = 0; 216 char status = TTY_NORMAL; 217 bool is_rxbs_support; 218 219 is_rxbs_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT; 220 221 while ((readl(port->membase + CDNS_UART_SR) & 222 CDNS_UART_SR_RXEMPTY) != CDNS_UART_SR_RXEMPTY) { 223 if (is_rxbs_support) 224 rxbs_status = readl(port->membase + CDNS_UART_RXBS); 225 data = readl(port->membase + CDNS_UART_FIFO); 226 port->icount.rx++; 227 /* 228 * There is no hardware break detection in Zynq, so we interpret 229 * framing error with all-zeros data as a break sequence. 230 * Most of the time, there's another non-zero byte at the 231 * end of the sequence. 232 */ 233 if (!is_rxbs_support && (isrstatus & CDNS_UART_IXR_FRAMING)) { 234 if (!data) { 235 port->read_status_mask |= CDNS_UART_IXR_BRK; 236 framerrprocessed = 1; 237 continue; 238 } 239 } 240 if (is_rxbs_support && (rxbs_status & CDNS_UART_RXBS_BRK)) { 241 port->icount.brk++; 242 status = TTY_BREAK; 243 if (uart_handle_break(port)) 244 continue; 245 } 246 247 isrstatus &= port->read_status_mask; 248 isrstatus &= ~port->ignore_status_mask; 249 status_mask = port->read_status_mask; 250 status_mask &= ~port->ignore_status_mask; 251 252 if (data && 253 (port->read_status_mask & CDNS_UART_IXR_BRK)) { 254 port->read_status_mask &= ~CDNS_UART_IXR_BRK; 255 port->icount.brk++; 256 if (uart_handle_break(port)) 257 continue; 258 } 259 260 if (uart_handle_sysrq_char(port, data)) 261 continue; 262 263 if (is_rxbs_support) { 264 if ((rxbs_status & CDNS_UART_RXBS_PARITY) 265 && (status_mask & CDNS_UART_IXR_PARITY)) { 266 port->icount.parity++; 267 status = TTY_PARITY; 268 } 269 if ((rxbs_status & CDNS_UART_RXBS_FRAMING) 270 && (status_mask & CDNS_UART_IXR_PARITY)) { 271 port->icount.frame++; 272 status = TTY_FRAME; 273 } 274 } else { 275 if (isrstatus & CDNS_UART_IXR_PARITY) { 276 port->icount.parity++; 277 status = TTY_PARITY; 278 } 279 if ((isrstatus & CDNS_UART_IXR_FRAMING) && 280 !framerrprocessed) { 281 port->icount.frame++; 282 status = TTY_FRAME; 283 } 284 } 285 if (isrstatus & CDNS_UART_IXR_OVERRUN) { 286 port->icount.overrun++; 287 tty_insert_flip_char(&port->state->port, 0, 288 TTY_OVERRUN); 289 } 290 tty_insert_flip_char(&port->state->port, data, status); 291 isrstatus = 0; 292 } 293 spin_unlock(&port->lock); 294 tty_flip_buffer_push(&port->state->port); 295 spin_lock(&port->lock); 296 } 297 298 /** 299 * cdns_uart_handle_tx - Handle the bytes to be Txed. 300 * @dev_id: Id of the UART port 301 * Return: None 302 */ 303 static void cdns_uart_handle_tx(void *dev_id) 304 { 305 struct uart_port *port = (struct uart_port *)dev_id; 306 unsigned int numbytes; 307 308 if (uart_circ_empty(&port->state->xmit)) { 309 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR); 310 } else { 311 numbytes = port->fifosize; 312 while (numbytes && !uart_circ_empty(&port->state->xmit) && 313 !(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL)) { 314 /* 315 * Get the data from the UART circular buffer 316 * and write it to the cdns_uart's TX_FIFO 317 * register. 318 */ 319 writel( 320 port->state->xmit.buf[port->state->xmit. 321 tail], port->membase + CDNS_UART_FIFO); 322 323 port->icount.tx++; 324 325 /* 326 * Adjust the tail of the UART buffer and wrap 327 * the buffer if it reaches limit. 328 */ 329 port->state->xmit.tail = 330 (port->state->xmit.tail + 1) & 331 (UART_XMIT_SIZE - 1); 332 333 numbytes--; 334 } 335 336 if (uart_circ_chars_pending( 337 &port->state->xmit) < WAKEUP_CHARS) 338 uart_write_wakeup(port); 339 } 340 } 341 342 /** 343 * cdns_uart_isr - Interrupt handler 344 * @irq: Irq number 345 * @dev_id: Id of the port 346 * 347 * Return: IRQHANDLED 348 */ 349 static irqreturn_t cdns_uart_isr(int irq, void *dev_id) 350 { 351 struct uart_port *port = (struct uart_port *)dev_id; 352 unsigned int isrstatus; 353 354 spin_lock(&port->lock); 355 356 /* Read the interrupt status register to determine which 357 * interrupt(s) is/are active and clear them. 358 */ 359 isrstatus = readl(port->membase + CDNS_UART_ISR); 360 writel(isrstatus, port->membase + CDNS_UART_ISR); 361 362 if (isrstatus & CDNS_UART_IXR_TXEMPTY) { 363 cdns_uart_handle_tx(dev_id); 364 isrstatus &= ~CDNS_UART_IXR_TXEMPTY; 365 } 366 if (isrstatus & CDNS_UART_IXR_MASK) 367 cdns_uart_handle_rx(dev_id, isrstatus); 368 369 spin_unlock(&port->lock); 370 return IRQ_HANDLED; 371 } 372 373 /** 374 * cdns_uart_calc_baud_divs - Calculate baud rate divisors 375 * @clk: UART module input clock 376 * @baud: Desired baud rate 377 * @rbdiv: BDIV value (return value) 378 * @rcd: CD value (return value) 379 * @div8: Value for clk_sel bit in mod (return value) 380 * Return: baud rate, requested baud when possible, or actual baud when there 381 * was too much error, zero if no valid divisors are found. 382 * 383 * Formula to obtain baud rate is 384 * baud_tx/rx rate = clk/CD * (BDIV + 1) 385 * input_clk = (Uart User Defined Clock or Apb Clock) 386 * depends on UCLKEN in MR Reg 387 * clk = input_clk or input_clk/8; 388 * depends on CLKS in MR reg 389 * CD and BDIV depends on values in 390 * baud rate generate register 391 * baud rate clock divisor register 392 */ 393 static unsigned int cdns_uart_calc_baud_divs(unsigned int clk, 394 unsigned int baud, u32 *rbdiv, u32 *rcd, int *div8) 395 { 396 u32 cd, bdiv; 397 unsigned int calc_baud; 398 unsigned int bestbaud = 0; 399 unsigned int bauderror; 400 unsigned int besterror = ~0; 401 402 if (baud < clk / ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX)) { 403 *div8 = 1; 404 clk /= 8; 405 } else { 406 *div8 = 0; 407 } 408 409 for (bdiv = CDNS_UART_BDIV_MIN; bdiv <= CDNS_UART_BDIV_MAX; bdiv++) { 410 cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1)); 411 if (cd < 1 || cd > CDNS_UART_CD_MAX) 412 continue; 413 414 calc_baud = clk / (cd * (bdiv + 1)); 415 416 if (baud > calc_baud) 417 bauderror = baud - calc_baud; 418 else 419 bauderror = calc_baud - baud; 420 421 if (besterror > bauderror) { 422 *rbdiv = bdiv; 423 *rcd = cd; 424 bestbaud = calc_baud; 425 besterror = bauderror; 426 } 427 } 428 /* use the values when percent error is acceptable */ 429 if (((besterror * 100) / baud) < 3) 430 bestbaud = baud; 431 432 return bestbaud; 433 } 434 435 /** 436 * cdns_uart_set_baud_rate - Calculate and set the baud rate 437 * @port: Handle to the uart port structure 438 * @baud: Baud rate to set 439 * Return: baud rate, requested baud when possible, or actual baud when there 440 * was too much error, zero if no valid divisors are found. 441 */ 442 static unsigned int cdns_uart_set_baud_rate(struct uart_port *port, 443 unsigned int baud) 444 { 445 unsigned int calc_baud; 446 u32 cd = 0, bdiv = 0; 447 u32 mreg; 448 int div8; 449 struct cdns_uart *cdns_uart = port->private_data; 450 451 calc_baud = cdns_uart_calc_baud_divs(port->uartclk, baud, &bdiv, &cd, 452 &div8); 453 454 /* Write new divisors to hardware */ 455 mreg = readl(port->membase + CDNS_UART_MR); 456 if (div8) 457 mreg |= CDNS_UART_MR_CLKSEL; 458 else 459 mreg &= ~CDNS_UART_MR_CLKSEL; 460 writel(mreg, port->membase + CDNS_UART_MR); 461 writel(cd, port->membase + CDNS_UART_BAUDGEN); 462 writel(bdiv, port->membase + CDNS_UART_BAUDDIV); 463 cdns_uart->baud = baud; 464 465 return calc_baud; 466 } 467 468 #ifdef CONFIG_COMMON_CLK 469 /** 470 * cdns_uart_clk_notitifer_cb - Clock notifier callback 471 * @nb: Notifier block 472 * @event: Notify event 473 * @data: Notifier data 474 * Return: NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error. 475 */ 476 static int cdns_uart_clk_notifier_cb(struct notifier_block *nb, 477 unsigned long event, void *data) 478 { 479 u32 ctrl_reg; 480 struct uart_port *port; 481 int locked = 0; 482 struct clk_notifier_data *ndata = data; 483 unsigned long flags = 0; 484 struct cdns_uart *cdns_uart = to_cdns_uart(nb); 485 486 port = cdns_uart->port; 487 if (port->suspended) 488 return NOTIFY_OK; 489 490 switch (event) { 491 case PRE_RATE_CHANGE: 492 { 493 u32 bdiv, cd; 494 int div8; 495 496 /* 497 * Find out if current baud-rate can be achieved with new clock 498 * frequency. 499 */ 500 if (!cdns_uart_calc_baud_divs(ndata->new_rate, cdns_uart->baud, 501 &bdiv, &cd, &div8)) { 502 dev_warn(port->dev, "clock rate change rejected\n"); 503 return NOTIFY_BAD; 504 } 505 506 spin_lock_irqsave(&cdns_uart->port->lock, flags); 507 508 /* Disable the TX and RX to set baud rate */ 509 ctrl_reg = readl(port->membase + CDNS_UART_CR); 510 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS; 511 writel(ctrl_reg, port->membase + CDNS_UART_CR); 512 513 spin_unlock_irqrestore(&cdns_uart->port->lock, flags); 514 515 return NOTIFY_OK; 516 } 517 case POST_RATE_CHANGE: 518 /* 519 * Set clk dividers to generate correct baud with new clock 520 * frequency. 521 */ 522 523 spin_lock_irqsave(&cdns_uart->port->lock, flags); 524 525 locked = 1; 526 port->uartclk = ndata->new_rate; 527 528 cdns_uart->baud = cdns_uart_set_baud_rate(cdns_uart->port, 529 cdns_uart->baud); 530 /* fall through */ 531 case ABORT_RATE_CHANGE: 532 if (!locked) 533 spin_lock_irqsave(&cdns_uart->port->lock, flags); 534 535 /* Set TX/RX Reset */ 536 ctrl_reg = readl(port->membase + CDNS_UART_CR); 537 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST; 538 writel(ctrl_reg, port->membase + CDNS_UART_CR); 539 540 while (readl(port->membase + CDNS_UART_CR) & 541 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST)) 542 cpu_relax(); 543 544 /* 545 * Clear the RX disable and TX disable bits and then set the TX 546 * enable bit and RX enable bit to enable the transmitter and 547 * receiver. 548 */ 549 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT); 550 ctrl_reg = readl(port->membase + CDNS_UART_CR); 551 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS); 552 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN; 553 writel(ctrl_reg, port->membase + CDNS_UART_CR); 554 555 spin_unlock_irqrestore(&cdns_uart->port->lock, flags); 556 557 return NOTIFY_OK; 558 default: 559 return NOTIFY_DONE; 560 } 561 } 562 #endif 563 564 /** 565 * cdns_uart_start_tx - Start transmitting bytes 566 * @port: Handle to the uart port structure 567 */ 568 static void cdns_uart_start_tx(struct uart_port *port) 569 { 570 unsigned int status; 571 572 if (uart_tx_stopped(port)) 573 return; 574 575 /* 576 * Set the TX enable bit and clear the TX disable bit to enable the 577 * transmitter. 578 */ 579 status = readl(port->membase + CDNS_UART_CR); 580 status &= ~CDNS_UART_CR_TX_DIS; 581 status |= CDNS_UART_CR_TX_EN; 582 writel(status, port->membase + CDNS_UART_CR); 583 584 if (uart_circ_empty(&port->state->xmit)) 585 return; 586 587 cdns_uart_handle_tx(port); 588 589 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR); 590 /* Enable the TX Empty interrupt */ 591 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IER); 592 } 593 594 /** 595 * cdns_uart_stop_tx - Stop TX 596 * @port: Handle to the uart port structure 597 */ 598 static void cdns_uart_stop_tx(struct uart_port *port) 599 { 600 unsigned int regval; 601 602 regval = readl(port->membase + CDNS_UART_CR); 603 regval |= CDNS_UART_CR_TX_DIS; 604 /* Disable the transmitter */ 605 writel(regval, port->membase + CDNS_UART_CR); 606 } 607 608 /** 609 * cdns_uart_stop_rx - Stop RX 610 * @port: Handle to the uart port structure 611 */ 612 static void cdns_uart_stop_rx(struct uart_port *port) 613 { 614 unsigned int regval; 615 616 /* Disable RX IRQs */ 617 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IDR); 618 619 /* Disable the receiver */ 620 regval = readl(port->membase + CDNS_UART_CR); 621 regval |= CDNS_UART_CR_RX_DIS; 622 writel(regval, port->membase + CDNS_UART_CR); 623 } 624 625 /** 626 * cdns_uart_tx_empty - Check whether TX is empty 627 * @port: Handle to the uart port structure 628 * 629 * Return: TIOCSER_TEMT on success, 0 otherwise 630 */ 631 static unsigned int cdns_uart_tx_empty(struct uart_port *port) 632 { 633 unsigned int status; 634 635 status = readl(port->membase + CDNS_UART_SR) & 636 CDNS_UART_SR_TXEMPTY; 637 return status ? TIOCSER_TEMT : 0; 638 } 639 640 /** 641 * cdns_uart_break_ctl - Based on the input ctl we have to start or stop 642 * transmitting char breaks 643 * @port: Handle to the uart port structure 644 * @ctl: Value based on which start or stop decision is taken 645 */ 646 static void cdns_uart_break_ctl(struct uart_port *port, int ctl) 647 { 648 unsigned int status; 649 unsigned long flags; 650 651 spin_lock_irqsave(&port->lock, flags); 652 653 status = readl(port->membase + CDNS_UART_CR); 654 655 if (ctl == -1) 656 writel(CDNS_UART_CR_STARTBRK | status, 657 port->membase + CDNS_UART_CR); 658 else { 659 if ((status & CDNS_UART_CR_STOPBRK) == 0) 660 writel(CDNS_UART_CR_STOPBRK | status, 661 port->membase + CDNS_UART_CR); 662 } 663 spin_unlock_irqrestore(&port->lock, flags); 664 } 665 666 /** 667 * cdns_uart_set_termios - termios operations, handling data length, parity, 668 * stop bits, flow control, baud rate 669 * @port: Handle to the uart port structure 670 * @termios: Handle to the input termios structure 671 * @old: Values of the previously saved termios structure 672 */ 673 static void cdns_uart_set_termios(struct uart_port *port, 674 struct ktermios *termios, struct ktermios *old) 675 { 676 unsigned int cval = 0; 677 unsigned int baud, minbaud, maxbaud; 678 unsigned long flags; 679 unsigned int ctrl_reg, mode_reg; 680 681 spin_lock_irqsave(&port->lock, flags); 682 683 /* Wait for the transmit FIFO to empty before making changes */ 684 if (!(readl(port->membase + CDNS_UART_CR) & 685 CDNS_UART_CR_TX_DIS)) { 686 while (!(readl(port->membase + CDNS_UART_SR) & 687 CDNS_UART_SR_TXEMPTY)) { 688 cpu_relax(); 689 } 690 } 691 692 /* Disable the TX and RX to set baud rate */ 693 ctrl_reg = readl(port->membase + CDNS_UART_CR); 694 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS; 695 writel(ctrl_reg, port->membase + CDNS_UART_CR); 696 697 /* 698 * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk 699 * min and max baud should be calculated here based on port->uartclk. 700 * this way we get a valid baud and can safely call set_baud() 701 */ 702 minbaud = port->uartclk / 703 ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX * 8); 704 maxbaud = port->uartclk / (CDNS_UART_BDIV_MIN + 1); 705 baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud); 706 baud = cdns_uart_set_baud_rate(port, baud); 707 if (tty_termios_baud_rate(termios)) 708 tty_termios_encode_baud_rate(termios, baud, baud); 709 710 /* Update the per-port timeout. */ 711 uart_update_timeout(port, termios->c_cflag, baud); 712 713 /* Set TX/RX Reset */ 714 ctrl_reg = readl(port->membase + CDNS_UART_CR); 715 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST; 716 writel(ctrl_reg, port->membase + CDNS_UART_CR); 717 718 while (readl(port->membase + CDNS_UART_CR) & 719 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST)) 720 cpu_relax(); 721 722 /* 723 * Clear the RX disable and TX disable bits and then set the TX enable 724 * bit and RX enable bit to enable the transmitter and receiver. 725 */ 726 ctrl_reg = readl(port->membase + CDNS_UART_CR); 727 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS); 728 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN; 729 writel(ctrl_reg, port->membase + CDNS_UART_CR); 730 731 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT); 732 733 port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG | 734 CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT; 735 port->ignore_status_mask = 0; 736 737 if (termios->c_iflag & INPCK) 738 port->read_status_mask |= CDNS_UART_IXR_PARITY | 739 CDNS_UART_IXR_FRAMING; 740 741 if (termios->c_iflag & IGNPAR) 742 port->ignore_status_mask |= CDNS_UART_IXR_PARITY | 743 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN; 744 745 /* ignore all characters if CREAD is not set */ 746 if ((termios->c_cflag & CREAD) == 0) 747 port->ignore_status_mask |= CDNS_UART_IXR_RXTRIG | 748 CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY | 749 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN; 750 751 mode_reg = readl(port->membase + CDNS_UART_MR); 752 753 /* Handling Data Size */ 754 switch (termios->c_cflag & CSIZE) { 755 case CS6: 756 cval |= CDNS_UART_MR_CHARLEN_6_BIT; 757 break; 758 case CS7: 759 cval |= CDNS_UART_MR_CHARLEN_7_BIT; 760 break; 761 default: 762 case CS8: 763 cval |= CDNS_UART_MR_CHARLEN_8_BIT; 764 termios->c_cflag &= ~CSIZE; 765 termios->c_cflag |= CS8; 766 break; 767 } 768 769 /* Handling Parity and Stop Bits length */ 770 if (termios->c_cflag & CSTOPB) 771 cval |= CDNS_UART_MR_STOPMODE_2_BIT; /* 2 STOP bits */ 772 else 773 cval |= CDNS_UART_MR_STOPMODE_1_BIT; /* 1 STOP bit */ 774 775 if (termios->c_cflag & PARENB) { 776 /* Mark or Space parity */ 777 if (termios->c_cflag & CMSPAR) { 778 if (termios->c_cflag & PARODD) 779 cval |= CDNS_UART_MR_PARITY_MARK; 780 else 781 cval |= CDNS_UART_MR_PARITY_SPACE; 782 } else { 783 if (termios->c_cflag & PARODD) 784 cval |= CDNS_UART_MR_PARITY_ODD; 785 else 786 cval |= CDNS_UART_MR_PARITY_EVEN; 787 } 788 } else { 789 cval |= CDNS_UART_MR_PARITY_NONE; 790 } 791 cval |= mode_reg & 1; 792 writel(cval, port->membase + CDNS_UART_MR); 793 794 spin_unlock_irqrestore(&port->lock, flags); 795 } 796 797 /** 798 * cdns_uart_startup - Called when an application opens a cdns_uart port 799 * @port: Handle to the uart port structure 800 * 801 * Return: 0 on success, negative errno otherwise 802 */ 803 static int cdns_uart_startup(struct uart_port *port) 804 { 805 struct cdns_uart *cdns_uart = port->private_data; 806 bool is_brk_support; 807 int ret; 808 unsigned long flags; 809 unsigned int status = 0; 810 811 is_brk_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT; 812 813 spin_lock_irqsave(&port->lock, flags); 814 815 /* Disable the TX and RX */ 816 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS, 817 port->membase + CDNS_UART_CR); 818 819 /* Set the Control Register with TX/RX Enable, TX/RX Reset, 820 * no break chars. 821 */ 822 writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST, 823 port->membase + CDNS_UART_CR); 824 825 while (readl(port->membase + CDNS_UART_CR) & 826 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST)) 827 cpu_relax(); 828 829 /* 830 * Clear the RX disable bit and then set the RX enable bit to enable 831 * the receiver. 832 */ 833 status = readl(port->membase + CDNS_UART_CR); 834 status &= CDNS_UART_CR_RX_DIS; 835 status |= CDNS_UART_CR_RX_EN; 836 writel(status, port->membase + CDNS_UART_CR); 837 838 /* Set the Mode Register with normal mode,8 data bits,1 stop bit, 839 * no parity. 840 */ 841 writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT 842 | CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT, 843 port->membase + CDNS_UART_MR); 844 845 /* 846 * Set the RX FIFO Trigger level to use most of the FIFO, but it 847 * can be tuned with a module parameter 848 */ 849 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM); 850 851 /* 852 * Receive Timeout register is enabled but it 853 * can be tuned with a module parameter 854 */ 855 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT); 856 857 /* Clear out any pending interrupts before enabling them */ 858 writel(readl(port->membase + CDNS_UART_ISR), 859 port->membase + CDNS_UART_ISR); 860 861 spin_unlock_irqrestore(&port->lock, flags); 862 863 ret = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME, port); 864 if (ret) { 865 dev_err(port->dev, "request_irq '%d' failed with %d\n", 866 port->irq, ret); 867 return ret; 868 } 869 870 /* Set the Interrupt Registers with desired interrupts */ 871 if (is_brk_support) 872 writel(CDNS_UART_RX_IRQS | CDNS_UART_IXR_BRK, 873 port->membase + CDNS_UART_IER); 874 else 875 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IER); 876 877 return 0; 878 } 879 880 /** 881 * cdns_uart_shutdown - Called when an application closes a cdns_uart port 882 * @port: Handle to the uart port structure 883 */ 884 static void cdns_uart_shutdown(struct uart_port *port) 885 { 886 int status; 887 unsigned long flags; 888 889 spin_lock_irqsave(&port->lock, flags); 890 891 /* Disable interrupts */ 892 status = readl(port->membase + CDNS_UART_IMR); 893 writel(status, port->membase + CDNS_UART_IDR); 894 writel(0xffffffff, port->membase + CDNS_UART_ISR); 895 896 /* Disable the TX and RX */ 897 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS, 898 port->membase + CDNS_UART_CR); 899 900 spin_unlock_irqrestore(&port->lock, flags); 901 902 free_irq(port->irq, port); 903 } 904 905 /** 906 * cdns_uart_type - Set UART type to cdns_uart port 907 * @port: Handle to the uart port structure 908 * 909 * Return: string on success, NULL otherwise 910 */ 911 static const char *cdns_uart_type(struct uart_port *port) 912 { 913 return port->type == PORT_XUARTPS ? CDNS_UART_NAME : NULL; 914 } 915 916 /** 917 * cdns_uart_verify_port - Verify the port params 918 * @port: Handle to the uart port structure 919 * @ser: Handle to the structure whose members are compared 920 * 921 * Return: 0 on success, negative errno otherwise. 922 */ 923 static int cdns_uart_verify_port(struct uart_port *port, 924 struct serial_struct *ser) 925 { 926 if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS) 927 return -EINVAL; 928 if (port->irq != ser->irq) 929 return -EINVAL; 930 if (ser->io_type != UPIO_MEM) 931 return -EINVAL; 932 if (port->iobase != ser->port) 933 return -EINVAL; 934 if (ser->hub6 != 0) 935 return -EINVAL; 936 return 0; 937 } 938 939 /** 940 * cdns_uart_request_port - Claim the memory region attached to cdns_uart port, 941 * called when the driver adds a cdns_uart port via 942 * uart_add_one_port() 943 * @port: Handle to the uart port structure 944 * 945 * Return: 0 on success, negative errno otherwise. 946 */ 947 static int cdns_uart_request_port(struct uart_port *port) 948 { 949 if (!request_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE, 950 CDNS_UART_NAME)) { 951 return -ENOMEM; 952 } 953 954 port->membase = ioremap(port->mapbase, CDNS_UART_REGISTER_SPACE); 955 if (!port->membase) { 956 dev_err(port->dev, "Unable to map registers\n"); 957 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE); 958 return -ENOMEM; 959 } 960 return 0; 961 } 962 963 /** 964 * cdns_uart_release_port - Release UART port 965 * @port: Handle to the uart port structure 966 * 967 * Release the memory region attached to a cdns_uart port. Called when the 968 * driver removes a cdns_uart port via uart_remove_one_port(). 969 */ 970 static void cdns_uart_release_port(struct uart_port *port) 971 { 972 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE); 973 iounmap(port->membase); 974 port->membase = NULL; 975 } 976 977 /** 978 * cdns_uart_config_port - Configure UART port 979 * @port: Handle to the uart port structure 980 * @flags: If any 981 */ 982 static void cdns_uart_config_port(struct uart_port *port, int flags) 983 { 984 if (flags & UART_CONFIG_TYPE && cdns_uart_request_port(port) == 0) 985 port->type = PORT_XUARTPS; 986 } 987 988 /** 989 * cdns_uart_get_mctrl - Get the modem control state 990 * @port: Handle to the uart port structure 991 * 992 * Return: the modem control state 993 */ 994 static unsigned int cdns_uart_get_mctrl(struct uart_port *port) 995 { 996 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; 997 } 998 999 static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 1000 { 1001 u32 val; 1002 u32 mode_reg; 1003 1004 val = readl(port->membase + CDNS_UART_MODEMCR); 1005 mode_reg = readl(port->membase + CDNS_UART_MR); 1006 1007 val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR); 1008 mode_reg &= ~CDNS_UART_MR_CHMODE_MASK; 1009 1010 if (mctrl & TIOCM_RTS) 1011 val |= CDNS_UART_MODEMCR_RTS; 1012 if (mctrl & TIOCM_DTR) 1013 val |= CDNS_UART_MODEMCR_DTR; 1014 if (mctrl & TIOCM_LOOP) 1015 mode_reg |= CDNS_UART_MR_CHMODE_L_LOOP; 1016 else 1017 mode_reg |= CDNS_UART_MR_CHMODE_NORM; 1018 1019 writel(val, port->membase + CDNS_UART_MODEMCR); 1020 writel(mode_reg, port->membase + CDNS_UART_MR); 1021 } 1022 1023 #ifdef CONFIG_CONSOLE_POLL 1024 static int cdns_uart_poll_get_char(struct uart_port *port) 1025 { 1026 int c; 1027 unsigned long flags; 1028 1029 spin_lock_irqsave(&port->lock, flags); 1030 1031 /* Check if FIFO is empty */ 1032 if (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_RXEMPTY) 1033 c = NO_POLL_CHAR; 1034 else /* Read a character */ 1035 c = (unsigned char) readl(port->membase + CDNS_UART_FIFO); 1036 1037 spin_unlock_irqrestore(&port->lock, flags); 1038 1039 return c; 1040 } 1041 1042 static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c) 1043 { 1044 unsigned long flags; 1045 1046 spin_lock_irqsave(&port->lock, flags); 1047 1048 /* Wait until FIFO is empty */ 1049 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY)) 1050 cpu_relax(); 1051 1052 /* Write a character */ 1053 writel(c, port->membase + CDNS_UART_FIFO); 1054 1055 /* Wait until FIFO is empty */ 1056 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY)) 1057 cpu_relax(); 1058 1059 spin_unlock_irqrestore(&port->lock, flags); 1060 1061 return; 1062 } 1063 #endif 1064 1065 static void cdns_uart_pm(struct uart_port *port, unsigned int state, 1066 unsigned int oldstate) 1067 { 1068 struct cdns_uart *cdns_uart = port->private_data; 1069 1070 switch (state) { 1071 case UART_PM_STATE_OFF: 1072 clk_disable(cdns_uart->uartclk); 1073 clk_disable(cdns_uart->pclk); 1074 break; 1075 default: 1076 clk_enable(cdns_uart->pclk); 1077 clk_enable(cdns_uart->uartclk); 1078 break; 1079 } 1080 } 1081 1082 static const struct uart_ops cdns_uart_ops = { 1083 .set_mctrl = cdns_uart_set_mctrl, 1084 .get_mctrl = cdns_uart_get_mctrl, 1085 .start_tx = cdns_uart_start_tx, 1086 .stop_tx = cdns_uart_stop_tx, 1087 .stop_rx = cdns_uart_stop_rx, 1088 .tx_empty = cdns_uart_tx_empty, 1089 .break_ctl = cdns_uart_break_ctl, 1090 .set_termios = cdns_uart_set_termios, 1091 .startup = cdns_uart_startup, 1092 .shutdown = cdns_uart_shutdown, 1093 .pm = cdns_uart_pm, 1094 .type = cdns_uart_type, 1095 .verify_port = cdns_uart_verify_port, 1096 .request_port = cdns_uart_request_port, 1097 .release_port = cdns_uart_release_port, 1098 .config_port = cdns_uart_config_port, 1099 #ifdef CONFIG_CONSOLE_POLL 1100 .poll_get_char = cdns_uart_poll_get_char, 1101 .poll_put_char = cdns_uart_poll_put_char, 1102 #endif 1103 }; 1104 1105 static struct uart_port cdns_uart_port[CDNS_UART_NR_PORTS]; 1106 1107 /** 1108 * cdns_uart_get_port - Configure the port from platform device resource info 1109 * @id: Port id 1110 * 1111 * Return: a pointer to a uart_port or NULL for failure 1112 */ 1113 static struct uart_port *cdns_uart_get_port(int id) 1114 { 1115 struct uart_port *port; 1116 1117 /* Try the given port id if failed use default method */ 1118 if (cdns_uart_port[id].mapbase != 0) { 1119 /* Find the next unused port */ 1120 for (id = 0; id < CDNS_UART_NR_PORTS; id++) 1121 if (cdns_uart_port[id].mapbase == 0) 1122 break; 1123 } 1124 1125 if (id >= CDNS_UART_NR_PORTS) 1126 return NULL; 1127 1128 port = &cdns_uart_port[id]; 1129 1130 /* At this point, we've got an empty uart_port struct, initialize it */ 1131 spin_lock_init(&port->lock); 1132 port->membase = NULL; 1133 port->irq = 0; 1134 port->type = PORT_UNKNOWN; 1135 port->iotype = UPIO_MEM32; 1136 port->flags = UPF_BOOT_AUTOCONF; 1137 port->ops = &cdns_uart_ops; 1138 port->fifosize = CDNS_UART_FIFO_SIZE; 1139 port->line = id; 1140 port->dev = NULL; 1141 return port; 1142 } 1143 1144 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE 1145 /** 1146 * cdns_uart_console_wait_tx - Wait for the TX to be full 1147 * @port: Handle to the uart port structure 1148 */ 1149 static void cdns_uart_console_wait_tx(struct uart_port *port) 1150 { 1151 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY)) 1152 barrier(); 1153 } 1154 1155 /** 1156 * cdns_uart_console_putchar - write the character to the FIFO buffer 1157 * @port: Handle to the uart port structure 1158 * @ch: Character to be written 1159 */ 1160 static void cdns_uart_console_putchar(struct uart_port *port, int ch) 1161 { 1162 cdns_uart_console_wait_tx(port); 1163 writel(ch, port->membase + CDNS_UART_FIFO); 1164 } 1165 1166 static void __init cdns_early_write(struct console *con, const char *s, 1167 unsigned n) 1168 { 1169 struct earlycon_device *dev = con->data; 1170 1171 uart_console_write(&dev->port, s, n, cdns_uart_console_putchar); 1172 } 1173 1174 static int __init cdns_early_console_setup(struct earlycon_device *device, 1175 const char *opt) 1176 { 1177 struct uart_port *port = &device->port; 1178 1179 if (!port->membase) 1180 return -ENODEV; 1181 1182 /* initialise control register */ 1183 writel(CDNS_UART_CR_TX_EN|CDNS_UART_CR_TXRST|CDNS_UART_CR_RXRST, 1184 port->membase + CDNS_UART_CR); 1185 1186 /* only set baud if specified on command line - otherwise 1187 * assume it has been initialized by a boot loader. 1188 */ 1189 if (device->baud) { 1190 u32 cd = 0, bdiv = 0; 1191 u32 mr; 1192 int div8; 1193 1194 cdns_uart_calc_baud_divs(port->uartclk, device->baud, 1195 &bdiv, &cd, &div8); 1196 mr = CDNS_UART_MR_PARITY_NONE; 1197 if (div8) 1198 mr |= CDNS_UART_MR_CLKSEL; 1199 1200 writel(mr, port->membase + CDNS_UART_MR); 1201 writel(cd, port->membase + CDNS_UART_BAUDGEN); 1202 writel(bdiv, port->membase + CDNS_UART_BAUDDIV); 1203 } 1204 1205 device->con->write = cdns_early_write; 1206 1207 return 0; 1208 } 1209 OF_EARLYCON_DECLARE(cdns, "xlnx,xuartps", cdns_early_console_setup); 1210 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p8", cdns_early_console_setup); 1211 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p12", cdns_early_console_setup); 1212 OF_EARLYCON_DECLARE(cdns, "xlnx,zynqmp-uart", cdns_early_console_setup); 1213 1214 /** 1215 * cdns_uart_console_write - perform write operation 1216 * @co: Console handle 1217 * @s: Pointer to character array 1218 * @count: No of characters 1219 */ 1220 static void cdns_uart_console_write(struct console *co, const char *s, 1221 unsigned int count) 1222 { 1223 struct uart_port *port = &cdns_uart_port[co->index]; 1224 unsigned long flags; 1225 unsigned int imr, ctrl; 1226 int locked = 1; 1227 1228 if (port->sysrq) 1229 locked = 0; 1230 else if (oops_in_progress) 1231 locked = spin_trylock_irqsave(&port->lock, flags); 1232 else 1233 spin_lock_irqsave(&port->lock, flags); 1234 1235 /* save and disable interrupt */ 1236 imr = readl(port->membase + CDNS_UART_IMR); 1237 writel(imr, port->membase + CDNS_UART_IDR); 1238 1239 /* 1240 * Make sure that the tx part is enabled. Set the TX enable bit and 1241 * clear the TX disable bit to enable the transmitter. 1242 */ 1243 ctrl = readl(port->membase + CDNS_UART_CR); 1244 ctrl &= ~CDNS_UART_CR_TX_DIS; 1245 ctrl |= CDNS_UART_CR_TX_EN; 1246 writel(ctrl, port->membase + CDNS_UART_CR); 1247 1248 uart_console_write(port, s, count, cdns_uart_console_putchar); 1249 cdns_uart_console_wait_tx(port); 1250 1251 writel(ctrl, port->membase + CDNS_UART_CR); 1252 1253 /* restore interrupt state */ 1254 writel(imr, port->membase + CDNS_UART_IER); 1255 1256 if (locked) 1257 spin_unlock_irqrestore(&port->lock, flags); 1258 } 1259 1260 /** 1261 * cdns_uart_console_setup - Initialize the uart to default config 1262 * @co: Console handle 1263 * @options: Initial settings of uart 1264 * 1265 * Return: 0 on success, negative errno otherwise. 1266 */ 1267 static int __init cdns_uart_console_setup(struct console *co, char *options) 1268 { 1269 struct uart_port *port = &cdns_uart_port[co->index]; 1270 int baud = 9600; 1271 int bits = 8; 1272 int parity = 'n'; 1273 int flow = 'n'; 1274 1275 if (co->index < 0 || co->index >= CDNS_UART_NR_PORTS) 1276 return -EINVAL; 1277 1278 if (!port->membase) { 1279 pr_debug("console on " CDNS_UART_TTY_NAME "%i not present\n", 1280 co->index); 1281 return -ENODEV; 1282 } 1283 1284 if (options) 1285 uart_parse_options(options, &baud, &parity, &bits, &flow); 1286 1287 return uart_set_options(port, co, baud, parity, bits, flow); 1288 } 1289 1290 static struct uart_driver cdns_uart_uart_driver; 1291 1292 static struct console cdns_uart_console = { 1293 .name = CDNS_UART_TTY_NAME, 1294 .write = cdns_uart_console_write, 1295 .device = uart_console_device, 1296 .setup = cdns_uart_console_setup, 1297 .flags = CON_PRINTBUFFER, 1298 .index = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */ 1299 .data = &cdns_uart_uart_driver, 1300 }; 1301 1302 /** 1303 * cdns_uart_console_init - Initialization call 1304 * 1305 * Return: 0 on success, negative errno otherwise 1306 */ 1307 static int __init cdns_uart_console_init(void) 1308 { 1309 register_console(&cdns_uart_console); 1310 return 0; 1311 } 1312 1313 console_initcall(cdns_uart_console_init); 1314 1315 #endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */ 1316 1317 static struct uart_driver cdns_uart_uart_driver = { 1318 .owner = THIS_MODULE, 1319 .driver_name = CDNS_UART_NAME, 1320 .dev_name = CDNS_UART_TTY_NAME, 1321 .major = CDNS_UART_MAJOR, 1322 .minor = CDNS_UART_MINOR, 1323 .nr = CDNS_UART_NR_PORTS, 1324 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE 1325 .cons = &cdns_uart_console, 1326 #endif 1327 }; 1328 1329 #ifdef CONFIG_PM_SLEEP 1330 /** 1331 * cdns_uart_suspend - suspend event 1332 * @device: Pointer to the device structure 1333 * 1334 * Return: 0 1335 */ 1336 static int cdns_uart_suspend(struct device *device) 1337 { 1338 struct uart_port *port = dev_get_drvdata(device); 1339 struct tty_struct *tty; 1340 struct device *tty_dev; 1341 int may_wake = 0; 1342 1343 /* Get the tty which could be NULL so don't assume it's valid */ 1344 tty = tty_port_tty_get(&port->state->port); 1345 if (tty) { 1346 tty_dev = tty->dev; 1347 may_wake = device_may_wakeup(tty_dev); 1348 tty_kref_put(tty); 1349 } 1350 1351 /* 1352 * Call the API provided in serial_core.c file which handles 1353 * the suspend. 1354 */ 1355 uart_suspend_port(&cdns_uart_uart_driver, port); 1356 if (console_suspend_enabled && !may_wake) { 1357 struct cdns_uart *cdns_uart = port->private_data; 1358 1359 clk_disable(cdns_uart->uartclk); 1360 clk_disable(cdns_uart->pclk); 1361 } else { 1362 unsigned long flags = 0; 1363 1364 spin_lock_irqsave(&port->lock, flags); 1365 /* Empty the receive FIFO 1st before making changes */ 1366 while (!(readl(port->membase + CDNS_UART_SR) & 1367 CDNS_UART_SR_RXEMPTY)) 1368 readl(port->membase + CDNS_UART_FIFO); 1369 /* set RX trigger level to 1 */ 1370 writel(1, port->membase + CDNS_UART_RXWM); 1371 /* disable RX timeout interrups */ 1372 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IDR); 1373 spin_unlock_irqrestore(&port->lock, flags); 1374 } 1375 1376 return 0; 1377 } 1378 1379 /** 1380 * cdns_uart_resume - Resume after a previous suspend 1381 * @device: Pointer to the device structure 1382 * 1383 * Return: 0 1384 */ 1385 static int cdns_uart_resume(struct device *device) 1386 { 1387 struct uart_port *port = dev_get_drvdata(device); 1388 unsigned long flags = 0; 1389 u32 ctrl_reg; 1390 struct tty_struct *tty; 1391 struct device *tty_dev; 1392 int may_wake = 0; 1393 1394 /* Get the tty which could be NULL so don't assume it's valid */ 1395 tty = tty_port_tty_get(&port->state->port); 1396 if (tty) { 1397 tty_dev = tty->dev; 1398 may_wake = device_may_wakeup(tty_dev); 1399 tty_kref_put(tty); 1400 } 1401 1402 if (console_suspend_enabled && !may_wake) { 1403 struct cdns_uart *cdns_uart = port->private_data; 1404 1405 clk_enable(cdns_uart->pclk); 1406 clk_enable(cdns_uart->uartclk); 1407 1408 spin_lock_irqsave(&port->lock, flags); 1409 1410 /* Set TX/RX Reset */ 1411 ctrl_reg = readl(port->membase + CDNS_UART_CR); 1412 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST; 1413 writel(ctrl_reg, port->membase + CDNS_UART_CR); 1414 while (readl(port->membase + CDNS_UART_CR) & 1415 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST)) 1416 cpu_relax(); 1417 1418 /* restore rx timeout value */ 1419 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT); 1420 /* Enable Tx/Rx */ 1421 ctrl_reg = readl(port->membase + CDNS_UART_CR); 1422 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS); 1423 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN; 1424 writel(ctrl_reg, port->membase + CDNS_UART_CR); 1425 1426 spin_unlock_irqrestore(&port->lock, flags); 1427 } else { 1428 spin_lock_irqsave(&port->lock, flags); 1429 /* restore original rx trigger level */ 1430 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM); 1431 /* enable RX timeout interrupt */ 1432 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IER); 1433 spin_unlock_irqrestore(&port->lock, flags); 1434 } 1435 1436 return uart_resume_port(&cdns_uart_uart_driver, port); 1437 } 1438 #endif /* ! CONFIG_PM_SLEEP */ 1439 1440 static SIMPLE_DEV_PM_OPS(cdns_uart_dev_pm_ops, cdns_uart_suspend, 1441 cdns_uart_resume); 1442 1443 static const struct cdns_platform_data zynqmp_uart_def = { 1444 .quirks = CDNS_UART_RXBS_SUPPORT, }; 1445 1446 /* Match table for of_platform binding */ 1447 static const struct of_device_id cdns_uart_of_match[] = { 1448 { .compatible = "xlnx,xuartps", }, 1449 { .compatible = "cdns,uart-r1p8", }, 1450 { .compatible = "cdns,uart-r1p12", .data = &zynqmp_uart_def }, 1451 { .compatible = "xlnx,zynqmp-uart", .data = &zynqmp_uart_def }, 1452 {} 1453 }; 1454 MODULE_DEVICE_TABLE(of, cdns_uart_of_match); 1455 1456 /** 1457 * cdns_uart_probe - Platform driver probe 1458 * @pdev: Pointer to the platform device structure 1459 * 1460 * Return: 0 on success, negative errno otherwise 1461 */ 1462 static int cdns_uart_probe(struct platform_device *pdev) 1463 { 1464 int rc, id, irq; 1465 struct uart_port *port; 1466 struct resource *res; 1467 struct cdns_uart *cdns_uart_data; 1468 const struct of_device_id *match; 1469 1470 cdns_uart_data = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_data), 1471 GFP_KERNEL); 1472 if (!cdns_uart_data) 1473 return -ENOMEM; 1474 1475 match = of_match_node(cdns_uart_of_match, pdev->dev.of_node); 1476 if (match && match->data) { 1477 const struct cdns_platform_data *data = match->data; 1478 1479 cdns_uart_data->quirks = data->quirks; 1480 } 1481 1482 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "pclk"); 1483 if (IS_ERR(cdns_uart_data->pclk)) { 1484 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "aper_clk"); 1485 if (!IS_ERR(cdns_uart_data->pclk)) 1486 dev_err(&pdev->dev, "clock name 'aper_clk' is deprecated.\n"); 1487 } 1488 if (IS_ERR(cdns_uart_data->pclk)) { 1489 dev_err(&pdev->dev, "pclk clock not found.\n"); 1490 return PTR_ERR(cdns_uart_data->pclk); 1491 } 1492 1493 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "uart_clk"); 1494 if (IS_ERR(cdns_uart_data->uartclk)) { 1495 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "ref_clk"); 1496 if (!IS_ERR(cdns_uart_data->uartclk)) 1497 dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n"); 1498 } 1499 if (IS_ERR(cdns_uart_data->uartclk)) { 1500 dev_err(&pdev->dev, "uart_clk clock not found.\n"); 1501 return PTR_ERR(cdns_uart_data->uartclk); 1502 } 1503 1504 rc = clk_prepare(cdns_uart_data->pclk); 1505 if (rc) { 1506 dev_err(&pdev->dev, "Unable to enable pclk clock.\n"); 1507 return rc; 1508 } 1509 rc = clk_prepare(cdns_uart_data->uartclk); 1510 if (rc) { 1511 dev_err(&pdev->dev, "Unable to enable device clock.\n"); 1512 goto err_out_clk_dis_pclk; 1513 } 1514 1515 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1516 if (!res) { 1517 rc = -ENODEV; 1518 goto err_out_clk_disable; 1519 } 1520 1521 irq = platform_get_irq(pdev, 0); 1522 if (irq <= 0) { 1523 rc = -ENXIO; 1524 goto err_out_clk_disable; 1525 } 1526 1527 #ifdef CONFIG_COMMON_CLK 1528 cdns_uart_data->clk_rate_change_nb.notifier_call = 1529 cdns_uart_clk_notifier_cb; 1530 if (clk_notifier_register(cdns_uart_data->uartclk, 1531 &cdns_uart_data->clk_rate_change_nb)) 1532 dev_warn(&pdev->dev, "Unable to register clock notifier.\n"); 1533 #endif 1534 /* Look for a serialN alias */ 1535 id = of_alias_get_id(pdev->dev.of_node, "serial"); 1536 if (id < 0) 1537 id = 0; 1538 1539 /* Initialize the port structure */ 1540 port = cdns_uart_get_port(id); 1541 1542 if (!port) { 1543 dev_err(&pdev->dev, "Cannot get uart_port structure\n"); 1544 rc = -ENODEV; 1545 goto err_out_notif_unreg; 1546 } 1547 1548 /* 1549 * Register the port. 1550 * This function also registers this device with the tty layer 1551 * and triggers invocation of the config_port() entry point. 1552 */ 1553 port->mapbase = res->start; 1554 port->irq = irq; 1555 port->dev = &pdev->dev; 1556 port->uartclk = clk_get_rate(cdns_uart_data->uartclk); 1557 port->private_data = cdns_uart_data; 1558 cdns_uart_data->port = port; 1559 platform_set_drvdata(pdev, port); 1560 1561 rc = uart_add_one_port(&cdns_uart_uart_driver, port); 1562 if (rc) { 1563 dev_err(&pdev->dev, 1564 "uart_add_one_port() failed; err=%i\n", rc); 1565 goto err_out_notif_unreg; 1566 } 1567 1568 return 0; 1569 1570 err_out_notif_unreg: 1571 #ifdef CONFIG_COMMON_CLK 1572 clk_notifier_unregister(cdns_uart_data->uartclk, 1573 &cdns_uart_data->clk_rate_change_nb); 1574 #endif 1575 err_out_clk_disable: 1576 clk_unprepare(cdns_uart_data->uartclk); 1577 err_out_clk_dis_pclk: 1578 clk_unprepare(cdns_uart_data->pclk); 1579 1580 return rc; 1581 } 1582 1583 /** 1584 * cdns_uart_remove - called when the platform driver is unregistered 1585 * @pdev: Pointer to the platform device structure 1586 * 1587 * Return: 0 on success, negative errno otherwise 1588 */ 1589 static int cdns_uart_remove(struct platform_device *pdev) 1590 { 1591 struct uart_port *port = platform_get_drvdata(pdev); 1592 struct cdns_uart *cdns_uart_data = port->private_data; 1593 int rc; 1594 1595 /* Remove the cdns_uart port from the serial core */ 1596 #ifdef CONFIG_COMMON_CLK 1597 clk_notifier_unregister(cdns_uart_data->uartclk, 1598 &cdns_uart_data->clk_rate_change_nb); 1599 #endif 1600 rc = uart_remove_one_port(&cdns_uart_uart_driver, port); 1601 port->mapbase = 0; 1602 clk_unprepare(cdns_uart_data->uartclk); 1603 clk_unprepare(cdns_uart_data->pclk); 1604 return rc; 1605 } 1606 1607 static struct platform_driver cdns_uart_platform_driver = { 1608 .probe = cdns_uart_probe, 1609 .remove = cdns_uart_remove, 1610 .driver = { 1611 .name = CDNS_UART_NAME, 1612 .of_match_table = cdns_uart_of_match, 1613 .pm = &cdns_uart_dev_pm_ops, 1614 }, 1615 }; 1616 1617 static int __init cdns_uart_init(void) 1618 { 1619 int retval = 0; 1620 1621 /* Register the cdns_uart driver with the serial core */ 1622 retval = uart_register_driver(&cdns_uart_uart_driver); 1623 if (retval) 1624 return retval; 1625 1626 /* Register the platform driver */ 1627 retval = platform_driver_register(&cdns_uart_platform_driver); 1628 if (retval) 1629 uart_unregister_driver(&cdns_uart_uart_driver); 1630 1631 return retval; 1632 } 1633 1634 static void __exit cdns_uart_exit(void) 1635 { 1636 /* Unregister the platform driver */ 1637 platform_driver_unregister(&cdns_uart_platform_driver); 1638 1639 /* Unregister the cdns_uart driver */ 1640 uart_unregister_driver(&cdns_uart_uart_driver); 1641 } 1642 1643 module_init(cdns_uart_init); 1644 module_exit(cdns_uart_exit); 1645 1646 MODULE_DESCRIPTION("Driver for Cadence UART"); 1647 MODULE_AUTHOR("Xilinx Inc."); 1648 MODULE_LICENSE("GPL"); 1649