1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Cadence UART driver (found in Xilinx Zynq)
4  *
5  * 2011 - 2014 (C) Xilinx Inc.
6  *
7  * This driver has originally been pushed by Xilinx using a Zynq-branding. This
8  * still shows in the naming of this file, the kconfig symbols and some symbols
9  * in the code.
10  */
11 
12 #include <linux/platform_device.h>
13 #include <linux/serial.h>
14 #include <linux/console.h>
15 #include <linux/serial_core.h>
16 #include <linux/slab.h>
17 #include <linux/tty.h>
18 #include <linux/tty_flip.h>
19 #include <linux/clk.h>
20 #include <linux/irq.h>
21 #include <linux/io.h>
22 #include <linux/of.h>
23 #include <linux/module.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/iopoll.h>
26 
27 #define CDNS_UART_TTY_NAME	"ttyPS"
28 #define CDNS_UART_NAME		"xuartps"
29 #define CDNS_UART_MAJOR		0	/* use dynamic node allocation */
30 #define CDNS_UART_MINOR		0	/* works best with devtmpfs */
31 #define CDNS_UART_NR_PORTS	16
32 #define CDNS_UART_FIFO_SIZE	64	/* FIFO size */
33 #define CDNS_UART_REGISTER_SPACE	0x1000
34 #define TX_TIMEOUT		500000
35 
36 /* Rx Trigger level */
37 static int rx_trigger_level = 56;
38 module_param(rx_trigger_level, uint, 0444);
39 MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");
40 
41 /* Rx Timeout */
42 static int rx_timeout = 10;
43 module_param(rx_timeout, uint, 0444);
44 MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
45 
46 /* Register offsets for the UART. */
47 #define CDNS_UART_CR		0x00  /* Control Register */
48 #define CDNS_UART_MR		0x04  /* Mode Register */
49 #define CDNS_UART_IER		0x08  /* Interrupt Enable */
50 #define CDNS_UART_IDR		0x0C  /* Interrupt Disable */
51 #define CDNS_UART_IMR		0x10  /* Interrupt Mask */
52 #define CDNS_UART_ISR		0x14  /* Interrupt Status */
53 #define CDNS_UART_BAUDGEN	0x18  /* Baud Rate Generator */
54 #define CDNS_UART_RXTOUT	0x1C  /* RX Timeout */
55 #define CDNS_UART_RXWM		0x20  /* RX FIFO Trigger Level */
56 #define CDNS_UART_MODEMCR	0x24  /* Modem Control */
57 #define CDNS_UART_MODEMSR	0x28  /* Modem Status */
58 #define CDNS_UART_SR		0x2C  /* Channel Status */
59 #define CDNS_UART_FIFO		0x30  /* FIFO */
60 #define CDNS_UART_BAUDDIV	0x34  /* Baud Rate Divider */
61 #define CDNS_UART_FLOWDEL	0x38  /* Flow Delay */
62 #define CDNS_UART_IRRX_PWIDTH	0x3C  /* IR Min Received Pulse Width */
63 #define CDNS_UART_IRTX_PWIDTH	0x40  /* IR Transmitted pulse Width */
64 #define CDNS_UART_TXWM		0x44  /* TX FIFO Trigger Level */
65 #define CDNS_UART_RXBS		0x48  /* RX FIFO byte status register */
66 
67 /* Control Register Bit Definitions */
68 #define CDNS_UART_CR_STOPBRK	0x00000100  /* Stop TX break */
69 #define CDNS_UART_CR_STARTBRK	0x00000080  /* Set TX break */
70 #define CDNS_UART_CR_TX_DIS	0x00000020  /* TX disabled. */
71 #define CDNS_UART_CR_TX_EN	0x00000010  /* TX enabled */
72 #define CDNS_UART_CR_RX_DIS	0x00000008  /* RX disabled. */
73 #define CDNS_UART_CR_RX_EN	0x00000004  /* RX enabled */
74 #define CDNS_UART_CR_TXRST	0x00000002  /* TX logic reset */
75 #define CDNS_UART_CR_RXRST	0x00000001  /* RX logic reset */
76 #define CDNS_UART_CR_RST_TO	0x00000040  /* Restart Timeout Counter */
77 #define CDNS_UART_RXBS_PARITY    0x00000001 /* Parity error status */
78 #define CDNS_UART_RXBS_FRAMING   0x00000002 /* Framing error status */
79 #define CDNS_UART_RXBS_BRK       0x00000004 /* Overrun error status */
80 
81 /*
82  * Mode Register:
83  * The mode register (MR) defines the mode of transfer as well as the data
84  * format. If this register is modified during transmission or reception,
85  * data validity cannot be guaranteed.
86  */
87 #define CDNS_UART_MR_CLKSEL		0x00000001  /* Pre-scalar selection */
88 #define CDNS_UART_MR_CHMODE_L_LOOP	0x00000200  /* Local loop back mode */
89 #define CDNS_UART_MR_CHMODE_NORM	0x00000000  /* Normal mode */
90 #define CDNS_UART_MR_CHMODE_MASK	0x00000300  /* Mask for mode bits */
91 
92 #define CDNS_UART_MR_STOPMODE_2_BIT	0x00000080  /* 2 stop bits */
93 #define CDNS_UART_MR_STOPMODE_1_BIT	0x00000000  /* 1 stop bit */
94 
95 #define CDNS_UART_MR_PARITY_NONE	0x00000020  /* No parity mode */
96 #define CDNS_UART_MR_PARITY_MARK	0x00000018  /* Mark parity mode */
97 #define CDNS_UART_MR_PARITY_SPACE	0x00000010  /* Space parity mode */
98 #define CDNS_UART_MR_PARITY_ODD		0x00000008  /* Odd parity mode */
99 #define CDNS_UART_MR_PARITY_EVEN	0x00000000  /* Even parity mode */
100 
101 #define CDNS_UART_MR_CHARLEN_6_BIT	0x00000006  /* 6 bits data */
102 #define CDNS_UART_MR_CHARLEN_7_BIT	0x00000004  /* 7 bits data */
103 #define CDNS_UART_MR_CHARLEN_8_BIT	0x00000000  /* 8 bits data */
104 
105 /*
106  * Interrupt Registers:
107  * Interrupt control logic uses the interrupt enable register (IER) and the
108  * interrupt disable register (IDR) to set the value of the bits in the
109  * interrupt mask register (IMR). The IMR determines whether to pass an
110  * interrupt to the interrupt status register (ISR).
111  * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an
112  * interrupt. IMR and ISR are read only, and IER and IDR are write only.
113  * Reading either IER or IDR returns 0x00.
114  * All four registers have the same bit definitions.
115  */
116 #define CDNS_UART_IXR_TOUT	0x00000100 /* RX Timeout error interrupt */
117 #define CDNS_UART_IXR_PARITY	0x00000080 /* Parity error interrupt */
118 #define CDNS_UART_IXR_FRAMING	0x00000040 /* Framing error interrupt */
119 #define CDNS_UART_IXR_OVERRUN	0x00000020 /* Overrun error interrupt */
120 #define CDNS_UART_IXR_TXFULL	0x00000010 /* TX FIFO Full interrupt */
121 #define CDNS_UART_IXR_TXEMPTY	0x00000008 /* TX FIFO empty interrupt */
122 #define CDNS_UART_ISR_RXEMPTY	0x00000002 /* RX FIFO empty interrupt */
123 #define CDNS_UART_IXR_RXTRIG	0x00000001 /* RX FIFO trigger interrupt */
124 #define CDNS_UART_IXR_RXFULL	0x00000004 /* RX FIFO full interrupt. */
125 #define CDNS_UART_IXR_RXEMPTY	0x00000002 /* RX FIFO empty interrupt. */
126 #define CDNS_UART_IXR_RXMASK	0x000021e7 /* Valid RX bit mask */
127 
128 	/*
129 	 * Do not enable parity error interrupt for the following
130 	 * reason: When parity error interrupt is enabled, each Rx
131 	 * parity error always results in 2 events. The first one
132 	 * being parity error interrupt and the second one with a
133 	 * proper Rx interrupt with the incoming data.  Disabling
134 	 * parity error interrupt ensures better handling of parity
135 	 * error events. With this change, for a parity error case, we
136 	 * get a Rx interrupt with parity error set in ISR register
137 	 * and we still handle parity errors in the desired way.
138 	 */
139 
140 #define CDNS_UART_RX_IRQS	(CDNS_UART_IXR_FRAMING | \
141 				 CDNS_UART_IXR_OVERRUN | \
142 				 CDNS_UART_IXR_RXTRIG |	 \
143 				 CDNS_UART_IXR_TOUT)
144 
145 /* Goes in read_status_mask for break detection as the HW doesn't do it*/
146 #define CDNS_UART_IXR_BRK	0x00002000
147 
148 #define CDNS_UART_RXBS_SUPPORT BIT(1)
149 /*
150  * Modem Control register:
151  * The read/write Modem Control register controls the interface with the modem
152  * or data set, or a peripheral device emulating a modem.
153  */
154 #define CDNS_UART_MODEMCR_FCM	0x00000020 /* Automatic flow control mode */
155 #define CDNS_UART_MODEMCR_RTS	0x00000002 /* Request to send output control */
156 #define CDNS_UART_MODEMCR_DTR	0x00000001 /* Data Terminal Ready */
157 
158 /*
159  * Modem Status register:
160  * The read/write Modem Status register reports the interface with the modem
161  * or data set, or a peripheral device emulating a modem.
162  */
163 #define CDNS_UART_MODEMSR_DCD	BIT(7) /* Data Carrier Detect */
164 #define CDNS_UART_MODEMSR_RI	BIT(6) /* Ting Indicator */
165 #define CDNS_UART_MODEMSR_DSR	BIT(5) /* Data Set Ready */
166 #define CDNS_UART_MODEMSR_CTS	BIT(4) /* Clear To Send */
167 
168 /*
169  * Channel Status Register:
170  * The channel status register (CSR) is provided to enable the control logic
171  * to monitor the status of bits in the channel interrupt status register,
172  * even if these are masked out by the interrupt mask register.
173  */
174 #define CDNS_UART_SR_RXEMPTY	0x00000002 /* RX FIFO empty */
175 #define CDNS_UART_SR_TXEMPTY	0x00000008 /* TX FIFO empty */
176 #define CDNS_UART_SR_TXFULL	0x00000010 /* TX FIFO full */
177 #define CDNS_UART_SR_RXTRIG	0x00000001 /* Rx Trigger */
178 #define CDNS_UART_SR_TACTIVE	0x00000800 /* TX state machine active */
179 
180 /* baud dividers min/max values */
181 #define CDNS_UART_BDIV_MIN	4
182 #define CDNS_UART_BDIV_MAX	255
183 #define CDNS_UART_CD_MAX	65535
184 #define UART_AUTOSUSPEND_TIMEOUT	3000
185 
186 /**
187  * struct cdns_uart - device data
188  * @port:		Pointer to the UART port
189  * @uartclk:		Reference clock
190  * @pclk:		APB clock
191  * @cdns_uart_driver:	Pointer to UART driver
192  * @baud:		Current baud rate
193  * @clk_rate_change_nb:	Notifier block for clock changes
194  * @quirks:		Flags for RXBS support.
195  */
196 struct cdns_uart {
197 	struct uart_port	*port;
198 	struct clk		*uartclk;
199 	struct clk		*pclk;
200 	struct uart_driver	*cdns_uart_driver;
201 	unsigned int		baud;
202 	struct notifier_block	clk_rate_change_nb;
203 	u32			quirks;
204 	bool cts_override;
205 };
206 struct cdns_platform_data {
207 	u32 quirks;
208 };
209 #define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \
210 		clk_rate_change_nb)
211 
212 /**
213  * cdns_uart_handle_rx - Handle the received bytes along with Rx errors.
214  * @dev_id: Id of the UART port
215  * @isrstatus: The interrupt status register value as read
216  * Return: None
217  */
218 static void cdns_uart_handle_rx(void *dev_id, unsigned int isrstatus)
219 {
220 	struct uart_port *port = (struct uart_port *)dev_id;
221 	struct cdns_uart *cdns_uart = port->private_data;
222 	unsigned int data;
223 	unsigned int rxbs_status = 0;
224 	unsigned int status_mask;
225 	unsigned int framerrprocessed = 0;
226 	char status = TTY_NORMAL;
227 	bool is_rxbs_support;
228 
229 	is_rxbs_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
230 
231 	while ((readl(port->membase + CDNS_UART_SR) &
232 		CDNS_UART_SR_RXEMPTY) != CDNS_UART_SR_RXEMPTY) {
233 		if (is_rxbs_support)
234 			rxbs_status = readl(port->membase + CDNS_UART_RXBS);
235 		data = readl(port->membase + CDNS_UART_FIFO);
236 		port->icount.rx++;
237 		/*
238 		 * There is no hardware break detection in Zynq, so we interpret
239 		 * framing error with all-zeros data as a break sequence.
240 		 * Most of the time, there's another non-zero byte at the
241 		 * end of the sequence.
242 		 */
243 		if (!is_rxbs_support && (isrstatus & CDNS_UART_IXR_FRAMING)) {
244 			if (!data) {
245 				port->read_status_mask |= CDNS_UART_IXR_BRK;
246 				framerrprocessed = 1;
247 				continue;
248 			}
249 		}
250 		if (is_rxbs_support && (rxbs_status & CDNS_UART_RXBS_BRK)) {
251 			port->icount.brk++;
252 			status = TTY_BREAK;
253 			if (uart_handle_break(port))
254 				continue;
255 		}
256 
257 		isrstatus &= port->read_status_mask;
258 		isrstatus &= ~port->ignore_status_mask;
259 		status_mask = port->read_status_mask;
260 		status_mask &= ~port->ignore_status_mask;
261 
262 		if (data &&
263 		    (port->read_status_mask & CDNS_UART_IXR_BRK)) {
264 			port->read_status_mask &= ~CDNS_UART_IXR_BRK;
265 			port->icount.brk++;
266 			if (uart_handle_break(port))
267 				continue;
268 		}
269 
270 		if (uart_handle_sysrq_char(port, data))
271 			continue;
272 
273 		if (is_rxbs_support) {
274 			if ((rxbs_status & CDNS_UART_RXBS_PARITY)
275 			    && (status_mask & CDNS_UART_IXR_PARITY)) {
276 				port->icount.parity++;
277 				status = TTY_PARITY;
278 			}
279 			if ((rxbs_status & CDNS_UART_RXBS_FRAMING)
280 			    && (status_mask & CDNS_UART_IXR_PARITY)) {
281 				port->icount.frame++;
282 				status = TTY_FRAME;
283 			}
284 		} else {
285 			if (isrstatus & CDNS_UART_IXR_PARITY) {
286 				port->icount.parity++;
287 				status = TTY_PARITY;
288 			}
289 			if ((isrstatus & CDNS_UART_IXR_FRAMING) &&
290 			    !framerrprocessed) {
291 				port->icount.frame++;
292 				status = TTY_FRAME;
293 			}
294 		}
295 		if (isrstatus & CDNS_UART_IXR_OVERRUN) {
296 			port->icount.overrun++;
297 			tty_insert_flip_char(&port->state->port, 0,
298 					     TTY_OVERRUN);
299 		}
300 		tty_insert_flip_char(&port->state->port, data, status);
301 		isrstatus = 0;
302 	}
303 	spin_unlock(&port->lock);
304 	tty_flip_buffer_push(&port->state->port);
305 	spin_lock(&port->lock);
306 }
307 
308 /**
309  * cdns_uart_handle_tx - Handle the bytes to be Txed.
310  * @dev_id: Id of the UART port
311  * Return: None
312  */
313 static void cdns_uart_handle_tx(void *dev_id)
314 {
315 	struct uart_port *port = (struct uart_port *)dev_id;
316 	unsigned int numbytes;
317 
318 	if (uart_circ_empty(&port->state->xmit)) {
319 		writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR);
320 	} else {
321 		numbytes = port->fifosize;
322 		while (numbytes && !uart_circ_empty(&port->state->xmit) &&
323 		       !(readl(port->membase + CDNS_UART_SR) &
324 						CDNS_UART_SR_TXFULL)) {
325 			/*
326 			 * Get the data from the UART circular buffer
327 			 * and write it to the cdns_uart's TX_FIFO
328 			 * register.
329 			 */
330 			writel(
331 				port->state->xmit.buf[port->state->xmit.tail],
332 					port->membase + CDNS_UART_FIFO);
333 
334 			port->icount.tx++;
335 
336 			/*
337 			 * Adjust the tail of the UART buffer and wrap
338 			 * the buffer if it reaches limit.
339 			 */
340 			port->state->xmit.tail =
341 				(port->state->xmit.tail + 1) &
342 					(UART_XMIT_SIZE - 1);
343 
344 			numbytes--;
345 		}
346 
347 		if (uart_circ_chars_pending(
348 				&port->state->xmit) < WAKEUP_CHARS)
349 			uart_write_wakeup(port);
350 	}
351 }
352 
353 /**
354  * cdns_uart_isr - Interrupt handler
355  * @irq: Irq number
356  * @dev_id: Id of the port
357  *
358  * Return: IRQHANDLED
359  */
360 static irqreturn_t cdns_uart_isr(int irq, void *dev_id)
361 {
362 	struct uart_port *port = (struct uart_port *)dev_id;
363 	unsigned int isrstatus;
364 
365 	spin_lock(&port->lock);
366 
367 	/* Read the interrupt status register to determine which
368 	 * interrupt(s) is/are active and clear them.
369 	 */
370 	isrstatus = readl(port->membase + CDNS_UART_ISR);
371 	writel(isrstatus, port->membase + CDNS_UART_ISR);
372 
373 	if (isrstatus & CDNS_UART_IXR_TXEMPTY) {
374 		cdns_uart_handle_tx(dev_id);
375 		isrstatus &= ~CDNS_UART_IXR_TXEMPTY;
376 	}
377 
378 	/*
379 	 * Skip RX processing if RX is disabled as RXEMPTY will never be set
380 	 * as read bytes will not be removed from the FIFO.
381 	 */
382 	if (isrstatus & CDNS_UART_IXR_RXMASK &&
383 	    !(readl(port->membase + CDNS_UART_CR) & CDNS_UART_CR_RX_DIS))
384 		cdns_uart_handle_rx(dev_id, isrstatus);
385 
386 	spin_unlock(&port->lock);
387 	return IRQ_HANDLED;
388 }
389 
390 /**
391  * cdns_uart_calc_baud_divs - Calculate baud rate divisors
392  * @clk: UART module input clock
393  * @baud: Desired baud rate
394  * @rbdiv: BDIV value (return value)
395  * @rcd: CD value (return value)
396  * @div8: Value for clk_sel bit in mod (return value)
397  * Return: baud rate, requested baud when possible, or actual baud when there
398  *	was too much error, zero if no valid divisors are found.
399  *
400  * Formula to obtain baud rate is
401  *	baud_tx/rx rate = clk/CD * (BDIV + 1)
402  *	input_clk = (Uart User Defined Clock or Apb Clock)
403  *		depends on UCLKEN in MR Reg
404  *	clk = input_clk or input_clk/8;
405  *		depends on CLKS in MR reg
406  *	CD and BDIV depends on values in
407  *			baud rate generate register
408  *			baud rate clock divisor register
409  */
410 static unsigned int cdns_uart_calc_baud_divs(unsigned int clk,
411 		unsigned int baud, u32 *rbdiv, u32 *rcd, int *div8)
412 {
413 	u32 cd, bdiv;
414 	unsigned int calc_baud;
415 	unsigned int bestbaud = 0;
416 	unsigned int bauderror;
417 	unsigned int besterror = ~0;
418 
419 	if (baud < clk / ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX)) {
420 		*div8 = 1;
421 		clk /= 8;
422 	} else {
423 		*div8 = 0;
424 	}
425 
426 	for (bdiv = CDNS_UART_BDIV_MIN; bdiv <= CDNS_UART_BDIV_MAX; bdiv++) {
427 		cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1));
428 		if (cd < 1 || cd > CDNS_UART_CD_MAX)
429 			continue;
430 
431 		calc_baud = clk / (cd * (bdiv + 1));
432 
433 		if (baud > calc_baud)
434 			bauderror = baud - calc_baud;
435 		else
436 			bauderror = calc_baud - baud;
437 
438 		if (besterror > bauderror) {
439 			*rbdiv = bdiv;
440 			*rcd = cd;
441 			bestbaud = calc_baud;
442 			besterror = bauderror;
443 		}
444 	}
445 	/* use the values when percent error is acceptable */
446 	if (((besterror * 100) / baud) < 3)
447 		bestbaud = baud;
448 
449 	return bestbaud;
450 }
451 
452 /**
453  * cdns_uart_set_baud_rate - Calculate and set the baud rate
454  * @port: Handle to the uart port structure
455  * @baud: Baud rate to set
456  * Return: baud rate, requested baud when possible, or actual baud when there
457  *	   was too much error, zero if no valid divisors are found.
458  */
459 static unsigned int cdns_uart_set_baud_rate(struct uart_port *port,
460 		unsigned int baud)
461 {
462 	unsigned int calc_baud;
463 	u32 cd = 0, bdiv = 0;
464 	u32 mreg;
465 	int div8;
466 	struct cdns_uart *cdns_uart = port->private_data;
467 
468 	calc_baud = cdns_uart_calc_baud_divs(port->uartclk, baud, &bdiv, &cd,
469 			&div8);
470 
471 	/* Write new divisors to hardware */
472 	mreg = readl(port->membase + CDNS_UART_MR);
473 	if (div8)
474 		mreg |= CDNS_UART_MR_CLKSEL;
475 	else
476 		mreg &= ~CDNS_UART_MR_CLKSEL;
477 	writel(mreg, port->membase + CDNS_UART_MR);
478 	writel(cd, port->membase + CDNS_UART_BAUDGEN);
479 	writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
480 	cdns_uart->baud = baud;
481 
482 	return calc_baud;
483 }
484 
485 #ifdef CONFIG_COMMON_CLK
486 /**
487  * cdns_uart_clk_notitifer_cb - Clock notifier callback
488  * @nb:		Notifier block
489  * @event:	Notify event
490  * @data:	Notifier data
491  * Return:	NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error.
492  */
493 static int cdns_uart_clk_notifier_cb(struct notifier_block *nb,
494 		unsigned long event, void *data)
495 {
496 	u32 ctrl_reg;
497 	struct uart_port *port;
498 	int locked = 0;
499 	struct clk_notifier_data *ndata = data;
500 	unsigned long flags = 0;
501 	struct cdns_uart *cdns_uart = to_cdns_uart(nb);
502 
503 	port = cdns_uart->port;
504 	if (port->suspended)
505 		return NOTIFY_OK;
506 
507 	switch (event) {
508 	case PRE_RATE_CHANGE:
509 	{
510 		u32 bdiv, cd;
511 		int div8;
512 
513 		/*
514 		 * Find out if current baud-rate can be achieved with new clock
515 		 * frequency.
516 		 */
517 		if (!cdns_uart_calc_baud_divs(ndata->new_rate, cdns_uart->baud,
518 					&bdiv, &cd, &div8)) {
519 			dev_warn(port->dev, "clock rate change rejected\n");
520 			return NOTIFY_BAD;
521 		}
522 
523 		spin_lock_irqsave(&cdns_uart->port->lock, flags);
524 
525 		/* Disable the TX and RX to set baud rate */
526 		ctrl_reg = readl(port->membase + CDNS_UART_CR);
527 		ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
528 		writel(ctrl_reg, port->membase + CDNS_UART_CR);
529 
530 		spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
531 
532 		return NOTIFY_OK;
533 	}
534 	case POST_RATE_CHANGE:
535 		/*
536 		 * Set clk dividers to generate correct baud with new clock
537 		 * frequency.
538 		 */
539 
540 		spin_lock_irqsave(&cdns_uart->port->lock, flags);
541 
542 		locked = 1;
543 		port->uartclk = ndata->new_rate;
544 
545 		cdns_uart->baud = cdns_uart_set_baud_rate(cdns_uart->port,
546 				cdns_uart->baud);
547 		/* fall through */
548 	case ABORT_RATE_CHANGE:
549 		if (!locked)
550 			spin_lock_irqsave(&cdns_uart->port->lock, flags);
551 
552 		/* Set TX/RX Reset */
553 		ctrl_reg = readl(port->membase + CDNS_UART_CR);
554 		ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
555 		writel(ctrl_reg, port->membase + CDNS_UART_CR);
556 
557 		while (readl(port->membase + CDNS_UART_CR) &
558 				(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
559 			cpu_relax();
560 
561 		/*
562 		 * Clear the RX disable and TX disable bits and then set the TX
563 		 * enable bit and RX enable bit to enable the transmitter and
564 		 * receiver.
565 		 */
566 		writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
567 		ctrl_reg = readl(port->membase + CDNS_UART_CR);
568 		ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
569 		ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
570 		writel(ctrl_reg, port->membase + CDNS_UART_CR);
571 
572 		spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
573 
574 		return NOTIFY_OK;
575 	default:
576 		return NOTIFY_DONE;
577 	}
578 }
579 #endif
580 
581 /**
582  * cdns_uart_start_tx -  Start transmitting bytes
583  * @port: Handle to the uart port structure
584  */
585 static void cdns_uart_start_tx(struct uart_port *port)
586 {
587 	unsigned int status;
588 
589 	if (uart_tx_stopped(port))
590 		return;
591 
592 	/*
593 	 * Set the TX enable bit and clear the TX disable bit to enable the
594 	 * transmitter.
595 	 */
596 	status = readl(port->membase + CDNS_UART_CR);
597 	status &= ~CDNS_UART_CR_TX_DIS;
598 	status |= CDNS_UART_CR_TX_EN;
599 	writel(status, port->membase + CDNS_UART_CR);
600 
601 	if (uart_circ_empty(&port->state->xmit))
602 		return;
603 
604 	cdns_uart_handle_tx(port);
605 
606 	writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR);
607 	/* Enable the TX Empty interrupt */
608 	writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IER);
609 }
610 
611 /**
612  * cdns_uart_stop_tx - Stop TX
613  * @port: Handle to the uart port structure
614  */
615 static void cdns_uart_stop_tx(struct uart_port *port)
616 {
617 	unsigned int regval;
618 
619 	regval = readl(port->membase + CDNS_UART_CR);
620 	regval |= CDNS_UART_CR_TX_DIS;
621 	/* Disable the transmitter */
622 	writel(regval, port->membase + CDNS_UART_CR);
623 }
624 
625 /**
626  * cdns_uart_stop_rx - Stop RX
627  * @port: Handle to the uart port structure
628  */
629 static void cdns_uart_stop_rx(struct uart_port *port)
630 {
631 	unsigned int regval;
632 
633 	/* Disable RX IRQs */
634 	writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IDR);
635 
636 	/* Disable the receiver */
637 	regval = readl(port->membase + CDNS_UART_CR);
638 	regval |= CDNS_UART_CR_RX_DIS;
639 	writel(regval, port->membase + CDNS_UART_CR);
640 }
641 
642 /**
643  * cdns_uart_tx_empty -  Check whether TX is empty
644  * @port: Handle to the uart port structure
645  *
646  * Return: TIOCSER_TEMT on success, 0 otherwise
647  */
648 static unsigned int cdns_uart_tx_empty(struct uart_port *port)
649 {
650 	unsigned int status;
651 
652 	status = readl(port->membase + CDNS_UART_SR) &
653 		       (CDNS_UART_SR_TXEMPTY | CDNS_UART_SR_TACTIVE);
654 	return (status == CDNS_UART_SR_TXEMPTY) ? TIOCSER_TEMT : 0;
655 }
656 
657 /**
658  * cdns_uart_break_ctl - Based on the input ctl we have to start or stop
659  *			transmitting char breaks
660  * @port: Handle to the uart port structure
661  * @ctl: Value based on which start or stop decision is taken
662  */
663 static void cdns_uart_break_ctl(struct uart_port *port, int ctl)
664 {
665 	unsigned int status;
666 	unsigned long flags;
667 
668 	spin_lock_irqsave(&port->lock, flags);
669 
670 	status = readl(port->membase + CDNS_UART_CR);
671 
672 	if (ctl == -1)
673 		writel(CDNS_UART_CR_STARTBRK | status,
674 				port->membase + CDNS_UART_CR);
675 	else {
676 		if ((status & CDNS_UART_CR_STOPBRK) == 0)
677 			writel(CDNS_UART_CR_STOPBRK | status,
678 					port->membase + CDNS_UART_CR);
679 	}
680 	spin_unlock_irqrestore(&port->lock, flags);
681 }
682 
683 /**
684  * cdns_uart_set_termios - termios operations, handling data length, parity,
685  *				stop bits, flow control, baud rate
686  * @port: Handle to the uart port structure
687  * @termios: Handle to the input termios structure
688  * @old: Values of the previously saved termios structure
689  */
690 static void cdns_uart_set_termios(struct uart_port *port,
691 				struct ktermios *termios, struct ktermios *old)
692 {
693 	u32 cval = 0;
694 	unsigned int baud, minbaud, maxbaud;
695 	unsigned long flags;
696 	unsigned int ctrl_reg, mode_reg;
697 
698 	spin_lock_irqsave(&port->lock, flags);
699 
700 	/* Disable the TX and RX to set baud rate */
701 	ctrl_reg = readl(port->membase + CDNS_UART_CR);
702 	ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
703 	writel(ctrl_reg, port->membase + CDNS_UART_CR);
704 
705 	/*
706 	 * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk
707 	 * min and max baud should be calculated here based on port->uartclk.
708 	 * this way we get a valid baud and can safely call set_baud()
709 	 */
710 	minbaud = port->uartclk /
711 			((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX * 8);
712 	maxbaud = port->uartclk / (CDNS_UART_BDIV_MIN + 1);
713 	baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud);
714 	baud = cdns_uart_set_baud_rate(port, baud);
715 	if (tty_termios_baud_rate(termios))
716 		tty_termios_encode_baud_rate(termios, baud, baud);
717 
718 	/* Update the per-port timeout. */
719 	uart_update_timeout(port, termios->c_cflag, baud);
720 
721 	/* Set TX/RX Reset */
722 	ctrl_reg = readl(port->membase + CDNS_UART_CR);
723 	ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
724 	writel(ctrl_reg, port->membase + CDNS_UART_CR);
725 
726 	while (readl(port->membase + CDNS_UART_CR) &
727 		(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
728 		cpu_relax();
729 
730 	/*
731 	 * Clear the RX disable and TX disable bits and then set the TX enable
732 	 * bit and RX enable bit to enable the transmitter and receiver.
733 	 */
734 	ctrl_reg = readl(port->membase + CDNS_UART_CR);
735 	ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
736 	ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
737 	writel(ctrl_reg, port->membase + CDNS_UART_CR);
738 
739 	writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
740 
741 	port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG |
742 			CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT;
743 	port->ignore_status_mask = 0;
744 
745 	if (termios->c_iflag & INPCK)
746 		port->read_status_mask |= CDNS_UART_IXR_PARITY |
747 		CDNS_UART_IXR_FRAMING;
748 
749 	if (termios->c_iflag & IGNPAR)
750 		port->ignore_status_mask |= CDNS_UART_IXR_PARITY |
751 			CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
752 
753 	/* ignore all characters if CREAD is not set */
754 	if ((termios->c_cflag & CREAD) == 0)
755 		port->ignore_status_mask |= CDNS_UART_IXR_RXTRIG |
756 			CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY |
757 			CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
758 
759 	mode_reg = readl(port->membase + CDNS_UART_MR);
760 
761 	/* Handling Data Size */
762 	switch (termios->c_cflag & CSIZE) {
763 	case CS6:
764 		cval |= CDNS_UART_MR_CHARLEN_6_BIT;
765 		break;
766 	case CS7:
767 		cval |= CDNS_UART_MR_CHARLEN_7_BIT;
768 		break;
769 	default:
770 	case CS8:
771 		cval |= CDNS_UART_MR_CHARLEN_8_BIT;
772 		termios->c_cflag &= ~CSIZE;
773 		termios->c_cflag |= CS8;
774 		break;
775 	}
776 
777 	/* Handling Parity and Stop Bits length */
778 	if (termios->c_cflag & CSTOPB)
779 		cval |= CDNS_UART_MR_STOPMODE_2_BIT; /* 2 STOP bits */
780 	else
781 		cval |= CDNS_UART_MR_STOPMODE_1_BIT; /* 1 STOP bit */
782 
783 	if (termios->c_cflag & PARENB) {
784 		/* Mark or Space parity */
785 		if (termios->c_cflag & CMSPAR) {
786 			if (termios->c_cflag & PARODD)
787 				cval |= CDNS_UART_MR_PARITY_MARK;
788 			else
789 				cval |= CDNS_UART_MR_PARITY_SPACE;
790 		} else {
791 			if (termios->c_cflag & PARODD)
792 				cval |= CDNS_UART_MR_PARITY_ODD;
793 			else
794 				cval |= CDNS_UART_MR_PARITY_EVEN;
795 		}
796 	} else {
797 		cval |= CDNS_UART_MR_PARITY_NONE;
798 	}
799 	cval |= mode_reg & 1;
800 	writel(cval, port->membase + CDNS_UART_MR);
801 
802 	cval = readl(port->membase + CDNS_UART_MODEMCR);
803 	if (termios->c_cflag & CRTSCTS)
804 		cval |= CDNS_UART_MODEMCR_FCM;
805 	else
806 		cval &= ~CDNS_UART_MODEMCR_FCM;
807 	writel(cval, port->membase + CDNS_UART_MODEMCR);
808 
809 	spin_unlock_irqrestore(&port->lock, flags);
810 }
811 
812 /**
813  * cdns_uart_startup - Called when an application opens a cdns_uart port
814  * @port: Handle to the uart port structure
815  *
816  * Return: 0 on success, negative errno otherwise
817  */
818 static int cdns_uart_startup(struct uart_port *port)
819 {
820 	struct cdns_uart *cdns_uart = port->private_data;
821 	bool is_brk_support;
822 	int ret;
823 	unsigned long flags;
824 	unsigned int status = 0;
825 
826 	is_brk_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
827 
828 	spin_lock_irqsave(&port->lock, flags);
829 
830 	/* Disable the TX and RX */
831 	writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
832 			port->membase + CDNS_UART_CR);
833 
834 	/* Set the Control Register with TX/RX Enable, TX/RX Reset,
835 	 * no break chars.
836 	 */
837 	writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST,
838 			port->membase + CDNS_UART_CR);
839 
840 	while (readl(port->membase + CDNS_UART_CR) &
841 		(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
842 		cpu_relax();
843 
844 	/*
845 	 * Clear the RX disable bit and then set the RX enable bit to enable
846 	 * the receiver.
847 	 */
848 	status = readl(port->membase + CDNS_UART_CR);
849 	status &= ~CDNS_UART_CR_RX_DIS;
850 	status |= CDNS_UART_CR_RX_EN;
851 	writel(status, port->membase + CDNS_UART_CR);
852 
853 	/* Set the Mode Register with normal mode,8 data bits,1 stop bit,
854 	 * no parity.
855 	 */
856 	writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT
857 		| CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT,
858 		port->membase + CDNS_UART_MR);
859 
860 	/*
861 	 * Set the RX FIFO Trigger level to use most of the FIFO, but it
862 	 * can be tuned with a module parameter
863 	 */
864 	writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
865 
866 	/*
867 	 * Receive Timeout register is enabled but it
868 	 * can be tuned with a module parameter
869 	 */
870 	writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
871 
872 	/* Clear out any pending interrupts before enabling them */
873 	writel(readl(port->membase + CDNS_UART_ISR),
874 			port->membase + CDNS_UART_ISR);
875 
876 	spin_unlock_irqrestore(&port->lock, flags);
877 
878 	ret = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME, port);
879 	if (ret) {
880 		dev_err(port->dev, "request_irq '%d' failed with %d\n",
881 			port->irq, ret);
882 		return ret;
883 	}
884 
885 	/* Set the Interrupt Registers with desired interrupts */
886 	if (is_brk_support)
887 		writel(CDNS_UART_RX_IRQS | CDNS_UART_IXR_BRK,
888 					port->membase + CDNS_UART_IER);
889 	else
890 		writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IER);
891 
892 	return 0;
893 }
894 
895 /**
896  * cdns_uart_shutdown - Called when an application closes a cdns_uart port
897  * @port: Handle to the uart port structure
898  */
899 static void cdns_uart_shutdown(struct uart_port *port)
900 {
901 	int status;
902 	unsigned long flags;
903 
904 	spin_lock_irqsave(&port->lock, flags);
905 
906 	/* Disable interrupts */
907 	status = readl(port->membase + CDNS_UART_IMR);
908 	writel(status, port->membase + CDNS_UART_IDR);
909 	writel(0xffffffff, port->membase + CDNS_UART_ISR);
910 
911 	/* Disable the TX and RX */
912 	writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
913 			port->membase + CDNS_UART_CR);
914 
915 	spin_unlock_irqrestore(&port->lock, flags);
916 
917 	free_irq(port->irq, port);
918 }
919 
920 /**
921  * cdns_uart_type - Set UART type to cdns_uart port
922  * @port: Handle to the uart port structure
923  *
924  * Return: string on success, NULL otherwise
925  */
926 static const char *cdns_uart_type(struct uart_port *port)
927 {
928 	return port->type == PORT_XUARTPS ? CDNS_UART_NAME : NULL;
929 }
930 
931 /**
932  * cdns_uart_verify_port - Verify the port params
933  * @port: Handle to the uart port structure
934  * @ser: Handle to the structure whose members are compared
935  *
936  * Return: 0 on success, negative errno otherwise.
937  */
938 static int cdns_uart_verify_port(struct uart_port *port,
939 					struct serial_struct *ser)
940 {
941 	if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS)
942 		return -EINVAL;
943 	if (port->irq != ser->irq)
944 		return -EINVAL;
945 	if (ser->io_type != UPIO_MEM)
946 		return -EINVAL;
947 	if (port->iobase != ser->port)
948 		return -EINVAL;
949 	if (ser->hub6 != 0)
950 		return -EINVAL;
951 	return 0;
952 }
953 
954 /**
955  * cdns_uart_request_port - Claim the memory region attached to cdns_uart port,
956  *				called when the driver adds a cdns_uart port via
957  *				uart_add_one_port()
958  * @port: Handle to the uart port structure
959  *
960  * Return: 0 on success, negative errno otherwise.
961  */
962 static int cdns_uart_request_port(struct uart_port *port)
963 {
964 	if (!request_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE,
965 					 CDNS_UART_NAME)) {
966 		return -ENOMEM;
967 	}
968 
969 	port->membase = ioremap(port->mapbase, CDNS_UART_REGISTER_SPACE);
970 	if (!port->membase) {
971 		dev_err(port->dev, "Unable to map registers\n");
972 		release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
973 		return -ENOMEM;
974 	}
975 	return 0;
976 }
977 
978 /**
979  * cdns_uart_release_port - Release UART port
980  * @port: Handle to the uart port structure
981  *
982  * Release the memory region attached to a cdns_uart port. Called when the
983  * driver removes a cdns_uart port via uart_remove_one_port().
984  */
985 static void cdns_uart_release_port(struct uart_port *port)
986 {
987 	release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
988 	iounmap(port->membase);
989 	port->membase = NULL;
990 }
991 
992 /**
993  * cdns_uart_config_port - Configure UART port
994  * @port: Handle to the uart port structure
995  * @flags: If any
996  */
997 static void cdns_uart_config_port(struct uart_port *port, int flags)
998 {
999 	if (flags & UART_CONFIG_TYPE && cdns_uart_request_port(port) == 0)
1000 		port->type = PORT_XUARTPS;
1001 }
1002 
1003 /**
1004  * cdns_uart_get_mctrl - Get the modem control state
1005  * @port: Handle to the uart port structure
1006  *
1007  * Return: the modem control state
1008  */
1009 static unsigned int cdns_uart_get_mctrl(struct uart_port *port)
1010 {
1011 	u32 val;
1012 	unsigned int mctrl = 0;
1013 	struct cdns_uart *cdns_uart_data = port->private_data;
1014 
1015 	if (cdns_uart_data->cts_override)
1016 		return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
1017 
1018 	val = readl(port->membase + CDNS_UART_MODEMSR);
1019 	if (val & CDNS_UART_MODEMSR_CTS)
1020 		mctrl |= TIOCM_CTS;
1021 	if (val & CDNS_UART_MODEMSR_DSR)
1022 		mctrl |= TIOCM_DSR;
1023 	if (val & CDNS_UART_MODEMSR_RI)
1024 		mctrl |= TIOCM_RNG;
1025 	if (val & CDNS_UART_MODEMSR_DCD)
1026 		mctrl |= TIOCM_CAR;
1027 
1028 	return mctrl;
1029 }
1030 
1031 static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1032 {
1033 	u32 val;
1034 	u32 mode_reg;
1035 	struct cdns_uart *cdns_uart_data = port->private_data;
1036 
1037 	if (cdns_uart_data->cts_override)
1038 		return;
1039 
1040 	val = readl(port->membase + CDNS_UART_MODEMCR);
1041 	mode_reg = readl(port->membase + CDNS_UART_MR);
1042 
1043 	val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR);
1044 	mode_reg &= ~CDNS_UART_MR_CHMODE_MASK;
1045 
1046 	if (mctrl & TIOCM_RTS)
1047 		val |= CDNS_UART_MODEMCR_RTS;
1048 	if (mctrl & TIOCM_DTR)
1049 		val |= CDNS_UART_MODEMCR_DTR;
1050 	if (mctrl & TIOCM_LOOP)
1051 		mode_reg |= CDNS_UART_MR_CHMODE_L_LOOP;
1052 	else
1053 		mode_reg |= CDNS_UART_MR_CHMODE_NORM;
1054 
1055 	writel(val, port->membase + CDNS_UART_MODEMCR);
1056 	writel(mode_reg, port->membase + CDNS_UART_MR);
1057 }
1058 
1059 #ifdef CONFIG_CONSOLE_POLL
1060 static int cdns_uart_poll_get_char(struct uart_port *port)
1061 {
1062 	int c;
1063 	unsigned long flags;
1064 
1065 	spin_lock_irqsave(&port->lock, flags);
1066 
1067 	/* Check if FIFO is empty */
1068 	if (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_RXEMPTY)
1069 		c = NO_POLL_CHAR;
1070 	else /* Read a character */
1071 		c = (unsigned char) readl(port->membase + CDNS_UART_FIFO);
1072 
1073 	spin_unlock_irqrestore(&port->lock, flags);
1074 
1075 	return c;
1076 }
1077 
1078 static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c)
1079 {
1080 	unsigned long flags;
1081 
1082 	spin_lock_irqsave(&port->lock, flags);
1083 
1084 	/* Wait until FIFO is empty */
1085 	while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1086 		cpu_relax();
1087 
1088 	/* Write a character */
1089 	writel(c, port->membase + CDNS_UART_FIFO);
1090 
1091 	/* Wait until FIFO is empty */
1092 	while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1093 		cpu_relax();
1094 
1095 	spin_unlock_irqrestore(&port->lock, flags);
1096 }
1097 #endif
1098 
1099 static void cdns_uart_pm(struct uart_port *port, unsigned int state,
1100 		   unsigned int oldstate)
1101 {
1102 	switch (state) {
1103 	case UART_PM_STATE_OFF:
1104 		pm_runtime_mark_last_busy(port->dev);
1105 		pm_runtime_put_autosuspend(port->dev);
1106 		break;
1107 	default:
1108 		pm_runtime_get_sync(port->dev);
1109 		break;
1110 	}
1111 }
1112 
1113 static const struct uart_ops cdns_uart_ops = {
1114 	.set_mctrl	= cdns_uart_set_mctrl,
1115 	.get_mctrl	= cdns_uart_get_mctrl,
1116 	.start_tx	= cdns_uart_start_tx,
1117 	.stop_tx	= cdns_uart_stop_tx,
1118 	.stop_rx	= cdns_uart_stop_rx,
1119 	.tx_empty	= cdns_uart_tx_empty,
1120 	.break_ctl	= cdns_uart_break_ctl,
1121 	.set_termios	= cdns_uart_set_termios,
1122 	.startup	= cdns_uart_startup,
1123 	.shutdown	= cdns_uart_shutdown,
1124 	.pm		= cdns_uart_pm,
1125 	.type		= cdns_uart_type,
1126 	.verify_port	= cdns_uart_verify_port,
1127 	.request_port	= cdns_uart_request_port,
1128 	.release_port	= cdns_uart_release_port,
1129 	.config_port	= cdns_uart_config_port,
1130 #ifdef CONFIG_CONSOLE_POLL
1131 	.poll_get_char	= cdns_uart_poll_get_char,
1132 	.poll_put_char	= cdns_uart_poll_put_char,
1133 #endif
1134 };
1135 
1136 static struct uart_driver cdns_uart_uart_driver;
1137 
1138 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1139 /**
1140  * cdns_uart_console_putchar - write the character to the FIFO buffer
1141  * @port: Handle to the uart port structure
1142  * @ch: Character to be written
1143  */
1144 static void cdns_uart_console_putchar(struct uart_port *port, int ch)
1145 {
1146 	while (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL)
1147 		cpu_relax();
1148 	writel(ch, port->membase + CDNS_UART_FIFO);
1149 }
1150 
1151 static void cdns_early_write(struct console *con, const char *s,
1152 				    unsigned n)
1153 {
1154 	struct earlycon_device *dev = con->data;
1155 
1156 	uart_console_write(&dev->port, s, n, cdns_uart_console_putchar);
1157 }
1158 
1159 static int __init cdns_early_console_setup(struct earlycon_device *device,
1160 					   const char *opt)
1161 {
1162 	struct uart_port *port = &device->port;
1163 
1164 	if (!port->membase)
1165 		return -ENODEV;
1166 
1167 	/* initialise control register */
1168 	writel(CDNS_UART_CR_TX_EN|CDNS_UART_CR_TXRST|CDNS_UART_CR_RXRST,
1169 	       port->membase + CDNS_UART_CR);
1170 
1171 	/* only set baud if specified on command line - otherwise
1172 	 * assume it has been initialized by a boot loader.
1173 	 */
1174 	if (port->uartclk && device->baud) {
1175 		u32 cd = 0, bdiv = 0;
1176 		u32 mr;
1177 		int div8;
1178 
1179 		cdns_uart_calc_baud_divs(port->uartclk, device->baud,
1180 					 &bdiv, &cd, &div8);
1181 		mr = CDNS_UART_MR_PARITY_NONE;
1182 		if (div8)
1183 			mr |= CDNS_UART_MR_CLKSEL;
1184 
1185 		writel(mr,   port->membase + CDNS_UART_MR);
1186 		writel(cd,   port->membase + CDNS_UART_BAUDGEN);
1187 		writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
1188 	}
1189 
1190 	device->con->write = cdns_early_write;
1191 
1192 	return 0;
1193 }
1194 OF_EARLYCON_DECLARE(cdns, "xlnx,xuartps", cdns_early_console_setup);
1195 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p8", cdns_early_console_setup);
1196 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p12", cdns_early_console_setup);
1197 OF_EARLYCON_DECLARE(cdns, "xlnx,zynqmp-uart", cdns_early_console_setup);
1198 
1199 
1200 /* Static pointer to console port */
1201 static struct uart_port *console_port;
1202 
1203 /**
1204  * cdns_uart_console_write - perform write operation
1205  * @co: Console handle
1206  * @s: Pointer to character array
1207  * @count: No of characters
1208  */
1209 static void cdns_uart_console_write(struct console *co, const char *s,
1210 				unsigned int count)
1211 {
1212 	struct uart_port *port = console_port;
1213 	unsigned long flags = 0;
1214 	unsigned int imr, ctrl;
1215 	int locked = 1;
1216 
1217 	if (port->sysrq)
1218 		locked = 0;
1219 	else if (oops_in_progress)
1220 		locked = spin_trylock_irqsave(&port->lock, flags);
1221 	else
1222 		spin_lock_irqsave(&port->lock, flags);
1223 
1224 	/* save and disable interrupt */
1225 	imr = readl(port->membase + CDNS_UART_IMR);
1226 	writel(imr, port->membase + CDNS_UART_IDR);
1227 
1228 	/*
1229 	 * Make sure that the tx part is enabled. Set the TX enable bit and
1230 	 * clear the TX disable bit to enable the transmitter.
1231 	 */
1232 	ctrl = readl(port->membase + CDNS_UART_CR);
1233 	ctrl &= ~CDNS_UART_CR_TX_DIS;
1234 	ctrl |= CDNS_UART_CR_TX_EN;
1235 	writel(ctrl, port->membase + CDNS_UART_CR);
1236 
1237 	uart_console_write(port, s, count, cdns_uart_console_putchar);
1238 	while (cdns_uart_tx_empty(port) != TIOCSER_TEMT)
1239 		cpu_relax();
1240 
1241 	/* restore interrupt state */
1242 	writel(imr, port->membase + CDNS_UART_IER);
1243 
1244 	if (locked)
1245 		spin_unlock_irqrestore(&port->lock, flags);
1246 }
1247 
1248 /**
1249  * cdns_uart_console_setup - Initialize the uart to default config
1250  * @co: Console handle
1251  * @options: Initial settings of uart
1252  *
1253  * Return: 0 on success, negative errno otherwise.
1254  */
1255 static int cdns_uart_console_setup(struct console *co, char *options)
1256 {
1257 	struct uart_port *port = console_port;
1258 
1259 	int baud = 9600;
1260 	int bits = 8;
1261 	int parity = 'n';
1262 	int flow = 'n';
1263 	unsigned long time_out;
1264 
1265 	if (!port->membase) {
1266 		pr_debug("console on " CDNS_UART_TTY_NAME "%i not present\n",
1267 			 co->index);
1268 		return -ENODEV;
1269 	}
1270 
1271 	if (options)
1272 		uart_parse_options(options, &baud, &parity, &bits, &flow);
1273 
1274 	/* Wait for tx_empty before setting up the console */
1275 	time_out = jiffies + usecs_to_jiffies(TX_TIMEOUT);
1276 
1277 	while (time_before(jiffies, time_out) &&
1278 	       cdns_uart_tx_empty(port) != TIOCSER_TEMT)
1279 		cpu_relax();
1280 
1281 	return uart_set_options(port, co, baud, parity, bits, flow);
1282 }
1283 
1284 static struct console cdns_uart_console = {
1285 	.name	= CDNS_UART_TTY_NAME,
1286 	.write	= cdns_uart_console_write,
1287 	.device	= uart_console_device,
1288 	.setup	= cdns_uart_console_setup,
1289 	.flags	= CON_PRINTBUFFER,
1290 	.index	= -1, /* Specified on the cmdline (e.g. console=ttyPS ) */
1291 	.data	= &cdns_uart_uart_driver,
1292 };
1293 #endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */
1294 
1295 #ifdef CONFIG_PM_SLEEP
1296 /**
1297  * cdns_uart_suspend - suspend event
1298  * @device: Pointer to the device structure
1299  *
1300  * Return: 0
1301  */
1302 static int cdns_uart_suspend(struct device *device)
1303 {
1304 	struct uart_port *port = dev_get_drvdata(device);
1305 	struct cdns_uart *cdns_uart = port->private_data;
1306 	int may_wake;
1307 
1308 	may_wake = device_may_wakeup(device);
1309 
1310 	if (console_suspend_enabled && uart_console(port) && may_wake) {
1311 		unsigned long flags = 0;
1312 
1313 		spin_lock_irqsave(&port->lock, flags);
1314 		/* Empty the receive FIFO 1st before making changes */
1315 		while (!(readl(port->membase + CDNS_UART_SR) &
1316 					CDNS_UART_SR_RXEMPTY))
1317 			readl(port->membase + CDNS_UART_FIFO);
1318 		/* set RX trigger level to 1 */
1319 		writel(1, port->membase + CDNS_UART_RXWM);
1320 		/* disable RX timeout interrups */
1321 		writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IDR);
1322 		spin_unlock_irqrestore(&port->lock, flags);
1323 	}
1324 
1325 	/*
1326 	 * Call the API provided in serial_core.c file which handles
1327 	 * the suspend.
1328 	 */
1329 	return uart_suspend_port(cdns_uart->cdns_uart_driver, port);
1330 }
1331 
1332 /**
1333  * cdns_uart_resume - Resume after a previous suspend
1334  * @device: Pointer to the device structure
1335  *
1336  * Return: 0
1337  */
1338 static int cdns_uart_resume(struct device *device)
1339 {
1340 	struct uart_port *port = dev_get_drvdata(device);
1341 	struct cdns_uart *cdns_uart = port->private_data;
1342 	unsigned long flags = 0;
1343 	u32 ctrl_reg;
1344 	int may_wake;
1345 
1346 	may_wake = device_may_wakeup(device);
1347 
1348 	if (console_suspend_enabled && uart_console(port) && !may_wake) {
1349 		clk_enable(cdns_uart->pclk);
1350 		clk_enable(cdns_uart->uartclk);
1351 
1352 		spin_lock_irqsave(&port->lock, flags);
1353 
1354 		/* Set TX/RX Reset */
1355 		ctrl_reg = readl(port->membase + CDNS_UART_CR);
1356 		ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
1357 		writel(ctrl_reg, port->membase + CDNS_UART_CR);
1358 		while (readl(port->membase + CDNS_UART_CR) &
1359 				(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
1360 			cpu_relax();
1361 
1362 		/* restore rx timeout value */
1363 		writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
1364 		/* Enable Tx/Rx */
1365 		ctrl_reg = readl(port->membase + CDNS_UART_CR);
1366 		ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
1367 		ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
1368 		writel(ctrl_reg, port->membase + CDNS_UART_CR);
1369 
1370 		clk_disable(cdns_uart->uartclk);
1371 		clk_disable(cdns_uart->pclk);
1372 		spin_unlock_irqrestore(&port->lock, flags);
1373 	} else {
1374 		spin_lock_irqsave(&port->lock, flags);
1375 		/* restore original rx trigger level */
1376 		writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
1377 		/* enable RX timeout interrupt */
1378 		writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IER);
1379 		spin_unlock_irqrestore(&port->lock, flags);
1380 	}
1381 
1382 	return uart_resume_port(cdns_uart->cdns_uart_driver, port);
1383 }
1384 #endif /* ! CONFIG_PM_SLEEP */
1385 static int __maybe_unused cdns_runtime_suspend(struct device *dev)
1386 {
1387 	struct uart_port *port = dev_get_drvdata(dev);
1388 	struct cdns_uart *cdns_uart = port->private_data;
1389 
1390 	clk_disable(cdns_uart->uartclk);
1391 	clk_disable(cdns_uart->pclk);
1392 	return 0;
1393 };
1394 
1395 static int __maybe_unused cdns_runtime_resume(struct device *dev)
1396 {
1397 	struct uart_port *port = dev_get_drvdata(dev);
1398 	struct cdns_uart *cdns_uart = port->private_data;
1399 
1400 	clk_enable(cdns_uart->pclk);
1401 	clk_enable(cdns_uart->uartclk);
1402 	return 0;
1403 };
1404 
1405 static const struct dev_pm_ops cdns_uart_dev_pm_ops = {
1406 	SET_SYSTEM_SLEEP_PM_OPS(cdns_uart_suspend, cdns_uart_resume)
1407 	SET_RUNTIME_PM_OPS(cdns_runtime_suspend,
1408 			   cdns_runtime_resume, NULL)
1409 };
1410 
1411 static const struct cdns_platform_data zynqmp_uart_def = {
1412 				.quirks = CDNS_UART_RXBS_SUPPORT, };
1413 
1414 /* Match table for of_platform binding */
1415 static const struct of_device_id cdns_uart_of_match[] = {
1416 	{ .compatible = "xlnx,xuartps", },
1417 	{ .compatible = "cdns,uart-r1p8", },
1418 	{ .compatible = "cdns,uart-r1p12", .data = &zynqmp_uart_def },
1419 	{ .compatible = "xlnx,zynqmp-uart", .data = &zynqmp_uart_def },
1420 	{}
1421 };
1422 MODULE_DEVICE_TABLE(of, cdns_uart_of_match);
1423 
1424 /* Temporary variable for storing number of instances */
1425 static int instances;
1426 
1427 /**
1428  * cdns_uart_probe - Platform driver probe
1429  * @pdev: Pointer to the platform device structure
1430  *
1431  * Return: 0 on success, negative errno otherwise
1432  */
1433 static int cdns_uart_probe(struct platform_device *pdev)
1434 {
1435 	int rc, id, irq;
1436 	struct uart_port *port;
1437 	struct resource *res;
1438 	struct cdns_uart *cdns_uart_data;
1439 	const struct of_device_id *match;
1440 
1441 	cdns_uart_data = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_data),
1442 			GFP_KERNEL);
1443 	if (!cdns_uart_data)
1444 		return -ENOMEM;
1445 	port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
1446 	if (!port)
1447 		return -ENOMEM;
1448 
1449 	/* Look for a serialN alias */
1450 	id = of_alias_get_id(pdev->dev.of_node, "serial");
1451 	if (id < 0)
1452 		id = 0;
1453 
1454 	if (id >= CDNS_UART_NR_PORTS) {
1455 		dev_err(&pdev->dev, "Cannot get uart_port structure\n");
1456 		return -ENODEV;
1457 	}
1458 
1459 	if (!cdns_uart_uart_driver.state) {
1460 		cdns_uart_uart_driver.owner = THIS_MODULE;
1461 		cdns_uart_uart_driver.driver_name = CDNS_UART_NAME;
1462 		cdns_uart_uart_driver.dev_name = CDNS_UART_TTY_NAME;
1463 		cdns_uart_uart_driver.major = CDNS_UART_MAJOR;
1464 		cdns_uart_uart_driver.minor = CDNS_UART_MINOR;
1465 		cdns_uart_uart_driver.nr = CDNS_UART_NR_PORTS;
1466 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1467 		cdns_uart_uart_driver.cons = &cdns_uart_console;
1468 		cdns_uart_console.index = id;
1469 #endif
1470 
1471 		rc = uart_register_driver(&cdns_uart_uart_driver);
1472 		if (rc < 0) {
1473 			dev_err(&pdev->dev, "Failed to register driver\n");
1474 			return rc;
1475 		}
1476 	}
1477 
1478 	cdns_uart_data->cdns_uart_driver = &cdns_uart_uart_driver;
1479 
1480 	match = of_match_node(cdns_uart_of_match, pdev->dev.of_node);
1481 	if (match && match->data) {
1482 		const struct cdns_platform_data *data = match->data;
1483 
1484 		cdns_uart_data->quirks = data->quirks;
1485 	}
1486 
1487 	cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "pclk");
1488 	if (PTR_ERR(cdns_uart_data->pclk) == -EPROBE_DEFER) {
1489 		rc = PTR_ERR(cdns_uart_data->pclk);
1490 		goto err_out_unregister_driver;
1491 	}
1492 
1493 	if (IS_ERR(cdns_uart_data->pclk)) {
1494 		cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "aper_clk");
1495 		if (IS_ERR(cdns_uart_data->pclk)) {
1496 			rc = PTR_ERR(cdns_uart_data->pclk);
1497 			goto err_out_unregister_driver;
1498 		}
1499 		dev_err(&pdev->dev, "clock name 'aper_clk' is deprecated.\n");
1500 	}
1501 
1502 	cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "uart_clk");
1503 	if (PTR_ERR(cdns_uart_data->uartclk) == -EPROBE_DEFER) {
1504 		rc = PTR_ERR(cdns_uart_data->uartclk);
1505 		goto err_out_unregister_driver;
1506 	}
1507 
1508 	if (IS_ERR(cdns_uart_data->uartclk)) {
1509 		cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "ref_clk");
1510 		if (IS_ERR(cdns_uart_data->uartclk)) {
1511 			rc = PTR_ERR(cdns_uart_data->uartclk);
1512 			goto err_out_unregister_driver;
1513 		}
1514 		dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n");
1515 	}
1516 
1517 	rc = clk_prepare_enable(cdns_uart_data->pclk);
1518 	if (rc) {
1519 		dev_err(&pdev->dev, "Unable to enable pclk clock.\n");
1520 		goto err_out_unregister_driver;
1521 	}
1522 	rc = clk_prepare_enable(cdns_uart_data->uartclk);
1523 	if (rc) {
1524 		dev_err(&pdev->dev, "Unable to enable device clock.\n");
1525 		goto err_out_clk_dis_pclk;
1526 	}
1527 
1528 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1529 	if (!res) {
1530 		rc = -ENODEV;
1531 		goto err_out_clk_disable;
1532 	}
1533 
1534 	irq = platform_get_irq(pdev, 0);
1535 	if (irq <= 0) {
1536 		rc = -ENXIO;
1537 		goto err_out_clk_disable;
1538 	}
1539 
1540 #ifdef CONFIG_COMMON_CLK
1541 	cdns_uart_data->clk_rate_change_nb.notifier_call =
1542 			cdns_uart_clk_notifier_cb;
1543 	if (clk_notifier_register(cdns_uart_data->uartclk,
1544 				&cdns_uart_data->clk_rate_change_nb))
1545 		dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
1546 #endif
1547 
1548 	/* At this point, we've got an empty uart_port struct, initialize it */
1549 	spin_lock_init(&port->lock);
1550 	port->type	= PORT_UNKNOWN;
1551 	port->iotype	= UPIO_MEM32;
1552 	port->flags	= UPF_BOOT_AUTOCONF;
1553 	port->ops	= &cdns_uart_ops;
1554 	port->fifosize	= CDNS_UART_FIFO_SIZE;
1555 	port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE);
1556 	port->line	= id;
1557 
1558 	/*
1559 	 * Register the port.
1560 	 * This function also registers this device with the tty layer
1561 	 * and triggers invocation of the config_port() entry point.
1562 	 */
1563 	port->mapbase = res->start;
1564 	port->irq = irq;
1565 	port->dev = &pdev->dev;
1566 	port->uartclk = clk_get_rate(cdns_uart_data->uartclk);
1567 	port->private_data = cdns_uart_data;
1568 	cdns_uart_data->port = port;
1569 	platform_set_drvdata(pdev, port);
1570 
1571 	pm_runtime_use_autosuspend(&pdev->dev);
1572 	pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT);
1573 	pm_runtime_set_active(&pdev->dev);
1574 	pm_runtime_enable(&pdev->dev);
1575 	device_init_wakeup(port->dev, true);
1576 
1577 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1578 	/*
1579 	 * If console hasn't been found yet try to assign this port
1580 	 * because it is required to be assigned for console setup function.
1581 	 * If register_console() don't assign value, then console_port pointer
1582 	 * is cleanup.
1583 	 */
1584 	if (!console_port)
1585 		console_port = port;
1586 #endif
1587 
1588 	rc = uart_add_one_port(&cdns_uart_uart_driver, port);
1589 	if (rc) {
1590 		dev_err(&pdev->dev,
1591 			"uart_add_one_port() failed; err=%i\n", rc);
1592 		goto err_out_pm_disable;
1593 	}
1594 
1595 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1596 	/* This is not port which is used for console that's why clean it up */
1597 	if (console_port == port &&
1598 	    !(cdns_uart_uart_driver.cons->flags & CON_ENABLED))
1599 		console_port = NULL;
1600 #endif
1601 
1602 	cdns_uart_data->cts_override = of_property_read_bool(pdev->dev.of_node,
1603 							     "cts-override");
1604 
1605 	instances++;
1606 
1607 	return 0;
1608 
1609 err_out_pm_disable:
1610 	pm_runtime_disable(&pdev->dev);
1611 	pm_runtime_set_suspended(&pdev->dev);
1612 	pm_runtime_dont_use_autosuspend(&pdev->dev);
1613 #ifdef CONFIG_COMMON_CLK
1614 	clk_notifier_unregister(cdns_uart_data->uartclk,
1615 			&cdns_uart_data->clk_rate_change_nb);
1616 #endif
1617 err_out_clk_disable:
1618 	clk_disable_unprepare(cdns_uart_data->uartclk);
1619 err_out_clk_dis_pclk:
1620 	clk_disable_unprepare(cdns_uart_data->pclk);
1621 err_out_unregister_driver:
1622 	if (!instances)
1623 		uart_unregister_driver(cdns_uart_data->cdns_uart_driver);
1624 	return rc;
1625 }
1626 
1627 /**
1628  * cdns_uart_remove - called when the platform driver is unregistered
1629  * @pdev: Pointer to the platform device structure
1630  *
1631  * Return: 0 on success, negative errno otherwise
1632  */
1633 static int cdns_uart_remove(struct platform_device *pdev)
1634 {
1635 	struct uart_port *port = platform_get_drvdata(pdev);
1636 	struct cdns_uart *cdns_uart_data = port->private_data;
1637 	int rc;
1638 
1639 	/* Remove the cdns_uart port from the serial core */
1640 #ifdef CONFIG_COMMON_CLK
1641 	clk_notifier_unregister(cdns_uart_data->uartclk,
1642 			&cdns_uart_data->clk_rate_change_nb);
1643 #endif
1644 	rc = uart_remove_one_port(cdns_uart_data->cdns_uart_driver, port);
1645 	port->mapbase = 0;
1646 	clk_disable_unprepare(cdns_uart_data->uartclk);
1647 	clk_disable_unprepare(cdns_uart_data->pclk);
1648 	pm_runtime_disable(&pdev->dev);
1649 	pm_runtime_set_suspended(&pdev->dev);
1650 	pm_runtime_dont_use_autosuspend(&pdev->dev);
1651 	device_init_wakeup(&pdev->dev, false);
1652 
1653 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1654 	if (console_port == port)
1655 		console_port = NULL;
1656 #endif
1657 
1658 	if (!--instances)
1659 		uart_unregister_driver(cdns_uart_data->cdns_uart_driver);
1660 	return rc;
1661 }
1662 
1663 static struct platform_driver cdns_uart_platform_driver = {
1664 	.probe   = cdns_uart_probe,
1665 	.remove  = cdns_uart_remove,
1666 	.driver  = {
1667 		.name = CDNS_UART_NAME,
1668 		.of_match_table = cdns_uart_of_match,
1669 		.pm = &cdns_uart_dev_pm_ops,
1670 		.suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_XILINX_PS_UART),
1671 		},
1672 };
1673 
1674 static int __init cdns_uart_init(void)
1675 {
1676 	/* Register the platform driver */
1677 	return platform_driver_register(&cdns_uart_platform_driver);
1678 }
1679 
1680 static void __exit cdns_uart_exit(void)
1681 {
1682 	/* Unregister the platform driver */
1683 	platform_driver_unregister(&cdns_uart_platform_driver);
1684 }
1685 
1686 arch_initcall(cdns_uart_init);
1687 module_exit(cdns_uart_exit);
1688 
1689 MODULE_DESCRIPTION("Driver for Cadence UART");
1690 MODULE_AUTHOR("Xilinx Inc.");
1691 MODULE_LICENSE("GPL");
1692