1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Freescale QUICC Engine UART device driver 4 * 5 * Author: Timur Tabi <timur@freescale.com> 6 * 7 * Copyright 2007 Freescale Semiconductor, Inc. 8 * 9 * This driver adds support for UART devices via Freescale's QUICC Engine 10 * found on some Freescale SOCs. 11 * 12 * If Soft-UART support is needed but not already present, then this driver 13 * will request and upload the "Soft-UART" microcode upon probe. The 14 * filename of the microcode should be fsl_qe_ucode_uart_X_YZ.bin, where "X" 15 * is the name of the SOC (e.g. 8323), and YZ is the revision of the SOC, 16 * (e.g. "11" for 1.1). 17 */ 18 19 #include <linux/module.h> 20 #include <linux/serial.h> 21 #include <linux/serial_core.h> 22 #include <linux/slab.h> 23 #include <linux/tty.h> 24 #include <linux/tty_flip.h> 25 #include <linux/io.h> 26 #include <linux/of_address.h> 27 #include <linux/of_irq.h> 28 #include <linux/of_platform.h> 29 #include <linux/dma-mapping.h> 30 31 #include <linux/fs_uart_pd.h> 32 #include <soc/fsl/qe/ucc_slow.h> 33 34 #include <linux/firmware.h> 35 #include <asm/reg.h> 36 37 /* 38 * The GUMR flag for Soft UART. This would normally be defined in qe.h, 39 * but Soft-UART is a hack and we want to keep everything related to it in 40 * this file. 41 */ 42 #define UCC_SLOW_GUMR_H_SUART 0x00004000 /* Soft-UART */ 43 44 /* 45 * soft_uart is 1 if we need to use Soft-UART mode 46 */ 47 static int soft_uart; 48 /* 49 * firmware_loaded is 1 if the firmware has been loaded, 0 otherwise. 50 */ 51 static int firmware_loaded; 52 53 /* Enable this macro to configure all serial ports in internal loopback 54 mode */ 55 /* #define LOOPBACK */ 56 57 /* The major and minor device numbers are defined in 58 * http://www.lanana.org/docs/device-list/devices-2.6+.txt. For the QE 59 * UART, we have major number 204 and minor numbers 46 - 49, which are the 60 * same as for the CPM2. This decision was made because no Freescale part 61 * has both a CPM and a QE. 62 */ 63 #define SERIAL_QE_MAJOR 204 64 #define SERIAL_QE_MINOR 46 65 66 /* Since we only have minor numbers 46 - 49, there is a hard limit of 4 ports */ 67 #define UCC_MAX_UART 4 68 69 /* The number of buffer descriptors for receiving characters. */ 70 #define RX_NUM_FIFO 4 71 72 /* The number of buffer descriptors for transmitting characters. */ 73 #define TX_NUM_FIFO 4 74 75 /* The maximum size of the character buffer for a single RX BD. */ 76 #define RX_BUF_SIZE 32 77 78 /* The maximum size of the character buffer for a single TX BD. */ 79 #define TX_BUF_SIZE 32 80 81 /* 82 * The number of jiffies to wait after receiving a close command before the 83 * device is actually closed. This allows the last few characters to be 84 * sent over the wire. 85 */ 86 #define UCC_WAIT_CLOSING 100 87 88 struct ucc_uart_pram { 89 struct ucc_slow_pram common; 90 u8 res1[8]; /* reserved */ 91 __be16 maxidl; /* Maximum idle chars */ 92 __be16 idlc; /* temp idle counter */ 93 __be16 brkcr; /* Break count register */ 94 __be16 parec; /* receive parity error counter */ 95 __be16 frmec; /* receive framing error counter */ 96 __be16 nosec; /* receive noise counter */ 97 __be16 brkec; /* receive break condition counter */ 98 __be16 brkln; /* last received break length */ 99 __be16 uaddr[2]; /* UART address character 1 & 2 */ 100 __be16 rtemp; /* Temp storage */ 101 __be16 toseq; /* Transmit out of sequence char */ 102 __be16 cchars[8]; /* control characters 1-8 */ 103 __be16 rccm; /* receive control character mask */ 104 __be16 rccr; /* receive control character register */ 105 __be16 rlbc; /* receive last break character */ 106 __be16 res2; /* reserved */ 107 __be32 res3; /* reserved, should be cleared */ 108 u8 res4; /* reserved, should be cleared */ 109 u8 res5[3]; /* reserved, should be cleared */ 110 __be32 res6; /* reserved, should be cleared */ 111 __be32 res7; /* reserved, should be cleared */ 112 __be32 res8; /* reserved, should be cleared */ 113 __be32 res9; /* reserved, should be cleared */ 114 __be32 res10; /* reserved, should be cleared */ 115 __be32 res11; /* reserved, should be cleared */ 116 __be32 res12; /* reserved, should be cleared */ 117 __be32 res13; /* reserved, should be cleared */ 118 /* The rest is for Soft-UART only */ 119 __be16 supsmr; /* 0x90, Shadow UPSMR */ 120 __be16 res92; /* 0x92, reserved, initialize to 0 */ 121 __be32 rx_state; /* 0x94, RX state, initialize to 0 */ 122 __be32 rx_cnt; /* 0x98, RX count, initialize to 0 */ 123 u8 rx_length; /* 0x9C, Char length, set to 1+CL+PEN+1+SL */ 124 u8 rx_bitmark; /* 0x9D, reserved, initialize to 0 */ 125 u8 rx_temp_dlst_qe; /* 0x9E, reserved, initialize to 0 */ 126 u8 res14[0xBC - 0x9F]; /* reserved */ 127 __be32 dump_ptr; /* 0xBC, Dump pointer */ 128 __be32 rx_frame_rem; /* 0xC0, reserved, initialize to 0 */ 129 u8 rx_frame_rem_size; /* 0xC4, reserved, initialize to 0 */ 130 u8 tx_mode; /* 0xC5, mode, 0=AHDLC, 1=UART */ 131 __be16 tx_state; /* 0xC6, TX state */ 132 u8 res15[0xD0 - 0xC8]; /* reserved */ 133 __be32 resD0; /* 0xD0, reserved, initialize to 0 */ 134 u8 resD4; /* 0xD4, reserved, initialize to 0 */ 135 __be16 resD5; /* 0xD5, reserved, initialize to 0 */ 136 } __attribute__ ((packed)); 137 138 /* SUPSMR definitions, for Soft-UART only */ 139 #define UCC_UART_SUPSMR_SL 0x8000 140 #define UCC_UART_SUPSMR_RPM_MASK 0x6000 141 #define UCC_UART_SUPSMR_RPM_ODD 0x0000 142 #define UCC_UART_SUPSMR_RPM_LOW 0x2000 143 #define UCC_UART_SUPSMR_RPM_EVEN 0x4000 144 #define UCC_UART_SUPSMR_RPM_HIGH 0x6000 145 #define UCC_UART_SUPSMR_PEN 0x1000 146 #define UCC_UART_SUPSMR_TPM_MASK 0x0C00 147 #define UCC_UART_SUPSMR_TPM_ODD 0x0000 148 #define UCC_UART_SUPSMR_TPM_LOW 0x0400 149 #define UCC_UART_SUPSMR_TPM_EVEN 0x0800 150 #define UCC_UART_SUPSMR_TPM_HIGH 0x0C00 151 #define UCC_UART_SUPSMR_FRZ 0x0100 152 #define UCC_UART_SUPSMR_UM_MASK 0x00c0 153 #define UCC_UART_SUPSMR_UM_NORMAL 0x0000 154 #define UCC_UART_SUPSMR_UM_MAN_MULTI 0x0040 155 #define UCC_UART_SUPSMR_UM_AUTO_MULTI 0x00c0 156 #define UCC_UART_SUPSMR_CL_MASK 0x0030 157 #define UCC_UART_SUPSMR_CL_8 0x0030 158 #define UCC_UART_SUPSMR_CL_7 0x0020 159 #define UCC_UART_SUPSMR_CL_6 0x0010 160 #define UCC_UART_SUPSMR_CL_5 0x0000 161 162 #define UCC_UART_TX_STATE_AHDLC 0x00 163 #define UCC_UART_TX_STATE_UART 0x01 164 #define UCC_UART_TX_STATE_X1 0x00 165 #define UCC_UART_TX_STATE_X16 0x80 166 167 #define UCC_UART_PRAM_ALIGNMENT 0x100 168 169 #define UCC_UART_SIZE_OF_BD UCC_SLOW_SIZE_OF_BD 170 #define NUM_CONTROL_CHARS 8 171 172 /* Private per-port data structure */ 173 struct uart_qe_port { 174 struct uart_port port; 175 struct ucc_slow __iomem *uccp; 176 struct ucc_uart_pram __iomem *uccup; 177 struct ucc_slow_info us_info; 178 struct ucc_slow_private *us_private; 179 struct device_node *np; 180 unsigned int ucc_num; /* First ucc is 0, not 1 */ 181 182 u16 rx_nrfifos; 183 u16 rx_fifosize; 184 u16 tx_nrfifos; 185 u16 tx_fifosize; 186 int wait_closing; 187 u32 flags; 188 struct qe_bd *rx_bd_base; 189 struct qe_bd *rx_cur; 190 struct qe_bd *tx_bd_base; 191 struct qe_bd *tx_cur; 192 unsigned char *tx_buf; 193 unsigned char *rx_buf; 194 void *bd_virt; /* virtual address of the BD buffers */ 195 dma_addr_t bd_dma_addr; /* bus address of the BD buffers */ 196 unsigned int bd_size; /* size of BD buffer space */ 197 }; 198 199 static struct uart_driver ucc_uart_driver = { 200 .owner = THIS_MODULE, 201 .driver_name = "ucc_uart", 202 .dev_name = "ttyQE", 203 .major = SERIAL_QE_MAJOR, 204 .minor = SERIAL_QE_MINOR, 205 .nr = UCC_MAX_UART, 206 }; 207 208 /* 209 * Virtual to physical address translation. 210 * 211 * Given the virtual address for a character buffer, this function returns 212 * the physical (DMA) equivalent. 213 */ 214 static inline dma_addr_t cpu2qe_addr(void *addr, struct uart_qe_port *qe_port) 215 { 216 if (likely((addr >= qe_port->bd_virt)) && 217 (addr < (qe_port->bd_virt + qe_port->bd_size))) 218 return qe_port->bd_dma_addr + (addr - qe_port->bd_virt); 219 220 /* something nasty happened */ 221 printk(KERN_ERR "%s: addr=%p\n", __func__, addr); 222 BUG(); 223 return 0; 224 } 225 226 /* 227 * Physical to virtual address translation. 228 * 229 * Given the physical (DMA) address for a character buffer, this function 230 * returns the virtual equivalent. 231 */ 232 static inline void *qe2cpu_addr(dma_addr_t addr, struct uart_qe_port *qe_port) 233 { 234 /* sanity check */ 235 if (likely((addr >= qe_port->bd_dma_addr) && 236 (addr < (qe_port->bd_dma_addr + qe_port->bd_size)))) 237 return qe_port->bd_virt + (addr - qe_port->bd_dma_addr); 238 239 /* something nasty happened */ 240 printk(KERN_ERR "%s: addr=%llx\n", __func__, (u64)addr); 241 BUG(); 242 return NULL; 243 } 244 245 /* 246 * Return 1 if the QE is done transmitting all buffers for this port 247 * 248 * This function scans each BD in sequence. If we find a BD that is not 249 * ready (READY=1), then we return 0 indicating that the QE is still sending 250 * data. If we reach the last BD (WRAP=1), then we know we've scanned 251 * the entire list, and all BDs are done. 252 */ 253 static unsigned int qe_uart_tx_empty(struct uart_port *port) 254 { 255 struct uart_qe_port *qe_port = 256 container_of(port, struct uart_qe_port, port); 257 struct qe_bd *bdp = qe_port->tx_bd_base; 258 259 while (1) { 260 if (in_be16(&bdp->status) & BD_SC_READY) 261 /* This BD is not done, so return "not done" */ 262 return 0; 263 264 if (in_be16(&bdp->status) & BD_SC_WRAP) 265 /* 266 * This BD is done and it's the last one, so return 267 * "done" 268 */ 269 return 1; 270 271 bdp++; 272 } 273 } 274 275 /* 276 * Set the modem control lines 277 * 278 * Although the QE can control the modem control lines (e.g. CTS), we 279 * don't need that support. This function must exist, however, otherwise 280 * the kernel will panic. 281 */ 282 void qe_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 283 { 284 } 285 286 /* 287 * Get the current modem control line status 288 * 289 * Although the QE can control the modem control lines (e.g. CTS), this 290 * driver currently doesn't support that, so we always return Carrier 291 * Detect, Data Set Ready, and Clear To Send. 292 */ 293 static unsigned int qe_uart_get_mctrl(struct uart_port *port) 294 { 295 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; 296 } 297 298 /* 299 * Disable the transmit interrupt. 300 * 301 * Although this function is called "stop_tx", it does not actually stop 302 * transmission of data. Instead, it tells the QE to not generate an 303 * interrupt when the UCC is finished sending characters. 304 */ 305 static void qe_uart_stop_tx(struct uart_port *port) 306 { 307 struct uart_qe_port *qe_port = 308 container_of(port, struct uart_qe_port, port); 309 310 clrbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX); 311 } 312 313 /* 314 * Transmit as many characters to the HW as possible. 315 * 316 * This function will attempt to stuff of all the characters from the 317 * kernel's transmit buffer into TX BDs. 318 * 319 * A return value of non-zero indicates that it successfully stuffed all 320 * characters from the kernel buffer. 321 * 322 * A return value of zero indicates that there are still characters in the 323 * kernel's buffer that have not been transmitted, but there are no more BDs 324 * available. This function should be called again after a BD has been made 325 * available. 326 */ 327 static int qe_uart_tx_pump(struct uart_qe_port *qe_port) 328 { 329 struct qe_bd *bdp; 330 unsigned char *p; 331 unsigned int count; 332 struct uart_port *port = &qe_port->port; 333 struct circ_buf *xmit = &port->state->xmit; 334 335 /* Handle xon/xoff */ 336 if (port->x_char) { 337 /* Pick next descriptor and fill from buffer */ 338 bdp = qe_port->tx_cur; 339 340 p = qe2cpu_addr(bdp->buf, qe_port); 341 342 *p++ = port->x_char; 343 out_be16(&bdp->length, 1); 344 setbits16(&bdp->status, BD_SC_READY); 345 /* Get next BD. */ 346 if (in_be16(&bdp->status) & BD_SC_WRAP) 347 bdp = qe_port->tx_bd_base; 348 else 349 bdp++; 350 qe_port->tx_cur = bdp; 351 352 port->icount.tx++; 353 port->x_char = 0; 354 return 1; 355 } 356 357 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 358 qe_uart_stop_tx(port); 359 return 0; 360 } 361 362 /* Pick next descriptor and fill from buffer */ 363 bdp = qe_port->tx_cur; 364 365 while (!(in_be16(&bdp->status) & BD_SC_READY) && 366 (xmit->tail != xmit->head)) { 367 count = 0; 368 p = qe2cpu_addr(bdp->buf, qe_port); 369 while (count < qe_port->tx_fifosize) { 370 *p++ = xmit->buf[xmit->tail]; 371 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 372 port->icount.tx++; 373 count++; 374 if (xmit->head == xmit->tail) 375 break; 376 } 377 378 out_be16(&bdp->length, count); 379 setbits16(&bdp->status, BD_SC_READY); 380 381 /* Get next BD. */ 382 if (in_be16(&bdp->status) & BD_SC_WRAP) 383 bdp = qe_port->tx_bd_base; 384 else 385 bdp++; 386 } 387 qe_port->tx_cur = bdp; 388 389 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 390 uart_write_wakeup(port); 391 392 if (uart_circ_empty(xmit)) { 393 /* The kernel buffer is empty, so turn off TX interrupts. We 394 don't need to be told when the QE is finished transmitting 395 the data. */ 396 qe_uart_stop_tx(port); 397 return 0; 398 } 399 400 return 1; 401 } 402 403 /* 404 * Start transmitting data 405 * 406 * This function will start transmitting any available data, if the port 407 * isn't already transmitting data. 408 */ 409 static void qe_uart_start_tx(struct uart_port *port) 410 { 411 struct uart_qe_port *qe_port = 412 container_of(port, struct uart_qe_port, port); 413 414 /* If we currently are transmitting, then just return */ 415 if (in_be16(&qe_port->uccp->uccm) & UCC_UART_UCCE_TX) 416 return; 417 418 /* Otherwise, pump the port and start transmission */ 419 if (qe_uart_tx_pump(qe_port)) 420 setbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX); 421 } 422 423 /* 424 * Stop transmitting data 425 */ 426 static void qe_uart_stop_rx(struct uart_port *port) 427 { 428 struct uart_qe_port *qe_port = 429 container_of(port, struct uart_qe_port, port); 430 431 clrbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX); 432 } 433 434 /* Start or stop sending break signal 435 * 436 * This function controls the sending of a break signal. If break_state=1, 437 * then we start sending a break signal. If break_state=0, then we stop 438 * sending the break signal. 439 */ 440 static void qe_uart_break_ctl(struct uart_port *port, int break_state) 441 { 442 struct uart_qe_port *qe_port = 443 container_of(port, struct uart_qe_port, port); 444 445 if (break_state) 446 ucc_slow_stop_tx(qe_port->us_private); 447 else 448 ucc_slow_restart_tx(qe_port->us_private); 449 } 450 451 /* ISR helper function for receiving character. 452 * 453 * This function is called by the ISR to handling receiving characters 454 */ 455 static void qe_uart_int_rx(struct uart_qe_port *qe_port) 456 { 457 int i; 458 unsigned char ch, *cp; 459 struct uart_port *port = &qe_port->port; 460 struct tty_port *tport = &port->state->port; 461 struct qe_bd *bdp; 462 u16 status; 463 unsigned int flg; 464 465 /* Just loop through the closed BDs and copy the characters into 466 * the buffer. 467 */ 468 bdp = qe_port->rx_cur; 469 while (1) { 470 status = in_be16(&bdp->status); 471 472 /* If this one is empty, then we assume we've read them all */ 473 if (status & BD_SC_EMPTY) 474 break; 475 476 /* get number of characters, and check space in RX buffer */ 477 i = in_be16(&bdp->length); 478 479 /* If we don't have enough room in RX buffer for the entire BD, 480 * then we try later, which will be the next RX interrupt. 481 */ 482 if (tty_buffer_request_room(tport, i) < i) { 483 dev_dbg(port->dev, "ucc-uart: no room in RX buffer\n"); 484 return; 485 } 486 487 /* get pointer */ 488 cp = qe2cpu_addr(bdp->buf, qe_port); 489 490 /* loop through the buffer */ 491 while (i-- > 0) { 492 ch = *cp++; 493 port->icount.rx++; 494 flg = TTY_NORMAL; 495 496 if (!i && status & 497 (BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV)) 498 goto handle_error; 499 if (uart_handle_sysrq_char(port, ch)) 500 continue; 501 502 error_return: 503 tty_insert_flip_char(tport, ch, flg); 504 505 } 506 507 /* This BD is ready to be used again. Clear status. get next */ 508 clrsetbits_be16(&bdp->status, BD_SC_BR | BD_SC_FR | BD_SC_PR | 509 BD_SC_OV | BD_SC_ID, BD_SC_EMPTY); 510 if (in_be16(&bdp->status) & BD_SC_WRAP) 511 bdp = qe_port->rx_bd_base; 512 else 513 bdp++; 514 515 } 516 517 /* Write back buffer pointer */ 518 qe_port->rx_cur = bdp; 519 520 /* Activate BH processing */ 521 tty_flip_buffer_push(tport); 522 523 return; 524 525 /* Error processing */ 526 527 handle_error: 528 /* Statistics */ 529 if (status & BD_SC_BR) 530 port->icount.brk++; 531 if (status & BD_SC_PR) 532 port->icount.parity++; 533 if (status & BD_SC_FR) 534 port->icount.frame++; 535 if (status & BD_SC_OV) 536 port->icount.overrun++; 537 538 /* Mask out ignored conditions */ 539 status &= port->read_status_mask; 540 541 /* Handle the remaining ones */ 542 if (status & BD_SC_BR) 543 flg = TTY_BREAK; 544 else if (status & BD_SC_PR) 545 flg = TTY_PARITY; 546 else if (status & BD_SC_FR) 547 flg = TTY_FRAME; 548 549 /* Overrun does not affect the current character ! */ 550 if (status & BD_SC_OV) 551 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 552 port->sysrq = 0; 553 goto error_return; 554 } 555 556 /* Interrupt handler 557 * 558 * This interrupt handler is called after a BD is processed. 559 */ 560 static irqreturn_t qe_uart_int(int irq, void *data) 561 { 562 struct uart_qe_port *qe_port = (struct uart_qe_port *) data; 563 struct ucc_slow __iomem *uccp = qe_port->uccp; 564 u16 events; 565 566 /* Clear the interrupts */ 567 events = in_be16(&uccp->ucce); 568 out_be16(&uccp->ucce, events); 569 570 if (events & UCC_UART_UCCE_BRKE) 571 uart_handle_break(&qe_port->port); 572 573 if (events & UCC_UART_UCCE_RX) 574 qe_uart_int_rx(qe_port); 575 576 if (events & UCC_UART_UCCE_TX) 577 qe_uart_tx_pump(qe_port); 578 579 return events ? IRQ_HANDLED : IRQ_NONE; 580 } 581 582 /* Initialize buffer descriptors 583 * 584 * This function initializes all of the RX and TX buffer descriptors. 585 */ 586 static void qe_uart_initbd(struct uart_qe_port *qe_port) 587 { 588 int i; 589 void *bd_virt; 590 struct qe_bd *bdp; 591 592 /* Set the physical address of the host memory buffers in the buffer 593 * descriptors, and the virtual address for us to work with. 594 */ 595 bd_virt = qe_port->bd_virt; 596 bdp = qe_port->rx_bd_base; 597 qe_port->rx_cur = qe_port->rx_bd_base; 598 for (i = 0; i < (qe_port->rx_nrfifos - 1); i++) { 599 out_be16(&bdp->status, BD_SC_EMPTY | BD_SC_INTRPT); 600 out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port)); 601 out_be16(&bdp->length, 0); 602 bd_virt += qe_port->rx_fifosize; 603 bdp++; 604 } 605 606 /* */ 607 out_be16(&bdp->status, BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT); 608 out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port)); 609 out_be16(&bdp->length, 0); 610 611 /* Set the physical address of the host memory 612 * buffers in the buffer descriptors, and the 613 * virtual address for us to work with. 614 */ 615 bd_virt = qe_port->bd_virt + 616 L1_CACHE_ALIGN(qe_port->rx_nrfifos * qe_port->rx_fifosize); 617 qe_port->tx_cur = qe_port->tx_bd_base; 618 bdp = qe_port->tx_bd_base; 619 for (i = 0; i < (qe_port->tx_nrfifos - 1); i++) { 620 out_be16(&bdp->status, BD_SC_INTRPT); 621 out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port)); 622 out_be16(&bdp->length, 0); 623 bd_virt += qe_port->tx_fifosize; 624 bdp++; 625 } 626 627 /* Loopback requires the preamble bit to be set on the first TX BD */ 628 #ifdef LOOPBACK 629 setbits16(&qe_port->tx_cur->status, BD_SC_P); 630 #endif 631 632 out_be16(&bdp->status, BD_SC_WRAP | BD_SC_INTRPT); 633 out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port)); 634 out_be16(&bdp->length, 0); 635 } 636 637 /* 638 * Initialize a UCC for UART. 639 * 640 * This function configures a given UCC to be used as a UART device. Basic 641 * UCC initialization is handled in qe_uart_request_port(). This function 642 * does all the UART-specific stuff. 643 */ 644 static void qe_uart_init_ucc(struct uart_qe_port *qe_port) 645 { 646 u32 cecr_subblock; 647 struct ucc_slow __iomem *uccp = qe_port->uccp; 648 struct ucc_uart_pram *uccup = qe_port->uccup; 649 650 unsigned int i; 651 652 /* First, disable TX and RX in the UCC */ 653 ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX); 654 655 /* Program the UCC UART parameter RAM */ 656 out_8(&uccup->common.rbmr, UCC_BMR_GBL | UCC_BMR_BO_BE); 657 out_8(&uccup->common.tbmr, UCC_BMR_GBL | UCC_BMR_BO_BE); 658 out_be16(&uccup->common.mrblr, qe_port->rx_fifosize); 659 out_be16(&uccup->maxidl, 0x10); 660 out_be16(&uccup->brkcr, 1); 661 out_be16(&uccup->parec, 0); 662 out_be16(&uccup->frmec, 0); 663 out_be16(&uccup->nosec, 0); 664 out_be16(&uccup->brkec, 0); 665 out_be16(&uccup->uaddr[0], 0); 666 out_be16(&uccup->uaddr[1], 0); 667 out_be16(&uccup->toseq, 0); 668 for (i = 0; i < 8; i++) 669 out_be16(&uccup->cchars[i], 0xC000); 670 out_be16(&uccup->rccm, 0xc0ff); 671 672 /* Configure the GUMR registers for UART */ 673 if (soft_uart) { 674 /* Soft-UART requires a 1X multiplier for TX */ 675 clrsetbits_be32(&uccp->gumr_l, 676 UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK | 677 UCC_SLOW_GUMR_L_RDCR_MASK, 678 UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_1 | 679 UCC_SLOW_GUMR_L_RDCR_16); 680 681 clrsetbits_be32(&uccp->gumr_h, UCC_SLOW_GUMR_H_RFW, 682 UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX); 683 } else { 684 clrsetbits_be32(&uccp->gumr_l, 685 UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK | 686 UCC_SLOW_GUMR_L_RDCR_MASK, 687 UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_16 | 688 UCC_SLOW_GUMR_L_RDCR_16); 689 690 clrsetbits_be32(&uccp->gumr_h, 691 UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX, 692 UCC_SLOW_GUMR_H_RFW); 693 } 694 695 #ifdef LOOPBACK 696 clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK, 697 UCC_SLOW_GUMR_L_DIAG_LOOP); 698 clrsetbits_be32(&uccp->gumr_h, 699 UCC_SLOW_GUMR_H_CTSP | UCC_SLOW_GUMR_H_RSYN, 700 UCC_SLOW_GUMR_H_CDS); 701 #endif 702 703 /* Disable rx interrupts and clear all pending events. */ 704 out_be16(&uccp->uccm, 0); 705 out_be16(&uccp->ucce, 0xffff); 706 out_be16(&uccp->udsr, 0x7e7e); 707 708 /* Initialize UPSMR */ 709 out_be16(&uccp->upsmr, 0); 710 711 if (soft_uart) { 712 out_be16(&uccup->supsmr, 0x30); 713 out_be16(&uccup->res92, 0); 714 out_be32(&uccup->rx_state, 0); 715 out_be32(&uccup->rx_cnt, 0); 716 out_8(&uccup->rx_bitmark, 0); 717 out_8(&uccup->rx_length, 10); 718 out_be32(&uccup->dump_ptr, 0x4000); 719 out_8(&uccup->rx_temp_dlst_qe, 0); 720 out_be32(&uccup->rx_frame_rem, 0); 721 out_8(&uccup->rx_frame_rem_size, 0); 722 /* Soft-UART requires TX to be 1X */ 723 out_8(&uccup->tx_mode, 724 UCC_UART_TX_STATE_UART | UCC_UART_TX_STATE_X1); 725 out_be16(&uccup->tx_state, 0); 726 out_8(&uccup->resD4, 0); 727 out_be16(&uccup->resD5, 0); 728 729 /* Set UART mode. 730 * Enable receive and transmit. 731 */ 732 733 /* From the microcode errata: 734 * 1.GUMR_L register, set mode=0010 (QMC). 735 * 2.Set GUMR_H[17] bit. (UART/AHDLC mode). 736 * 3.Set GUMR_H[19:20] (Transparent mode) 737 * 4.Clear GUMR_H[26] (RFW) 738 * ... 739 * 6.Receiver must use 16x over sampling 740 */ 741 clrsetbits_be32(&uccp->gumr_l, 742 UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK | 743 UCC_SLOW_GUMR_L_RDCR_MASK, 744 UCC_SLOW_GUMR_L_MODE_QMC | UCC_SLOW_GUMR_L_TDCR_16 | 745 UCC_SLOW_GUMR_L_RDCR_16); 746 747 clrsetbits_be32(&uccp->gumr_h, 748 UCC_SLOW_GUMR_H_RFW | UCC_SLOW_GUMR_H_RSYN, 749 UCC_SLOW_GUMR_H_SUART | UCC_SLOW_GUMR_H_TRX | 750 UCC_SLOW_GUMR_H_TTX | UCC_SLOW_GUMR_H_TFL); 751 752 #ifdef LOOPBACK 753 clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK, 754 UCC_SLOW_GUMR_L_DIAG_LOOP); 755 clrbits32(&uccp->gumr_h, UCC_SLOW_GUMR_H_CTSP | 756 UCC_SLOW_GUMR_H_CDS); 757 #endif 758 759 cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num); 760 qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock, 761 QE_CR_PROTOCOL_UNSPECIFIED, 0); 762 } else { 763 cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num); 764 qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock, 765 QE_CR_PROTOCOL_UART, 0); 766 } 767 } 768 769 /* 770 * Initialize the port. 771 */ 772 static int qe_uart_startup(struct uart_port *port) 773 { 774 struct uart_qe_port *qe_port = 775 container_of(port, struct uart_qe_port, port); 776 int ret; 777 778 /* 779 * If we're using Soft-UART mode, then we need to make sure the 780 * firmware has been uploaded first. 781 */ 782 if (soft_uart && !firmware_loaded) { 783 dev_err(port->dev, "Soft-UART firmware not uploaded\n"); 784 return -ENODEV; 785 } 786 787 qe_uart_initbd(qe_port); 788 qe_uart_init_ucc(qe_port); 789 790 /* Install interrupt handler. */ 791 ret = request_irq(port->irq, qe_uart_int, IRQF_SHARED, "ucc-uart", 792 qe_port); 793 if (ret) { 794 dev_err(port->dev, "could not claim IRQ %u\n", port->irq); 795 return ret; 796 } 797 798 /* Startup rx-int */ 799 setbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX); 800 ucc_slow_enable(qe_port->us_private, COMM_DIR_RX_AND_TX); 801 802 return 0; 803 } 804 805 /* 806 * Shutdown the port. 807 */ 808 static void qe_uart_shutdown(struct uart_port *port) 809 { 810 struct uart_qe_port *qe_port = 811 container_of(port, struct uart_qe_port, port); 812 struct ucc_slow __iomem *uccp = qe_port->uccp; 813 unsigned int timeout = 20; 814 815 /* Disable RX and TX */ 816 817 /* Wait for all the BDs marked sent */ 818 while (!qe_uart_tx_empty(port)) { 819 if (!--timeout) { 820 dev_warn(port->dev, "shutdown timeout\n"); 821 break; 822 } 823 set_current_state(TASK_UNINTERRUPTIBLE); 824 schedule_timeout(2); 825 } 826 827 if (qe_port->wait_closing) { 828 /* Wait a bit longer */ 829 set_current_state(TASK_UNINTERRUPTIBLE); 830 schedule_timeout(qe_port->wait_closing); 831 } 832 833 /* Stop uarts */ 834 ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX); 835 clrbits16(&uccp->uccm, UCC_UART_UCCE_TX | UCC_UART_UCCE_RX); 836 837 /* Shut them really down and reinit buffer descriptors */ 838 ucc_slow_graceful_stop_tx(qe_port->us_private); 839 qe_uart_initbd(qe_port); 840 841 free_irq(port->irq, qe_port); 842 } 843 844 /* 845 * Set the serial port parameters. 846 */ 847 static void qe_uart_set_termios(struct uart_port *port, 848 struct ktermios *termios, struct ktermios *old) 849 { 850 struct uart_qe_port *qe_port = 851 container_of(port, struct uart_qe_port, port); 852 struct ucc_slow __iomem *uccp = qe_port->uccp; 853 unsigned int baud; 854 unsigned long flags; 855 u16 upsmr = in_be16(&uccp->upsmr); 856 struct ucc_uart_pram __iomem *uccup = qe_port->uccup; 857 u16 supsmr = in_be16(&uccup->supsmr); 858 u8 char_length = 2; /* 1 + CL + PEN + 1 + SL */ 859 860 /* Character length programmed into the mode register is the 861 * sum of: 1 start bit, number of data bits, 0 or 1 parity bit, 862 * 1 or 2 stop bits, minus 1. 863 * The value 'bits' counts this for us. 864 */ 865 866 /* byte size */ 867 upsmr &= UCC_UART_UPSMR_CL_MASK; 868 supsmr &= UCC_UART_SUPSMR_CL_MASK; 869 870 switch (termios->c_cflag & CSIZE) { 871 case CS5: 872 upsmr |= UCC_UART_UPSMR_CL_5; 873 supsmr |= UCC_UART_SUPSMR_CL_5; 874 char_length += 5; 875 break; 876 case CS6: 877 upsmr |= UCC_UART_UPSMR_CL_6; 878 supsmr |= UCC_UART_SUPSMR_CL_6; 879 char_length += 6; 880 break; 881 case CS7: 882 upsmr |= UCC_UART_UPSMR_CL_7; 883 supsmr |= UCC_UART_SUPSMR_CL_7; 884 char_length += 7; 885 break; 886 default: /* case CS8 */ 887 upsmr |= UCC_UART_UPSMR_CL_8; 888 supsmr |= UCC_UART_SUPSMR_CL_8; 889 char_length += 8; 890 break; 891 } 892 893 /* If CSTOPB is set, we want two stop bits */ 894 if (termios->c_cflag & CSTOPB) { 895 upsmr |= UCC_UART_UPSMR_SL; 896 supsmr |= UCC_UART_SUPSMR_SL; 897 char_length++; /* + SL */ 898 } 899 900 if (termios->c_cflag & PARENB) { 901 upsmr |= UCC_UART_UPSMR_PEN; 902 supsmr |= UCC_UART_SUPSMR_PEN; 903 char_length++; /* + PEN */ 904 905 if (!(termios->c_cflag & PARODD)) { 906 upsmr &= ~(UCC_UART_UPSMR_RPM_MASK | 907 UCC_UART_UPSMR_TPM_MASK); 908 upsmr |= UCC_UART_UPSMR_RPM_EVEN | 909 UCC_UART_UPSMR_TPM_EVEN; 910 supsmr &= ~(UCC_UART_SUPSMR_RPM_MASK | 911 UCC_UART_SUPSMR_TPM_MASK); 912 supsmr |= UCC_UART_SUPSMR_RPM_EVEN | 913 UCC_UART_SUPSMR_TPM_EVEN; 914 } 915 } 916 917 /* 918 * Set up parity check flag 919 */ 920 port->read_status_mask = BD_SC_EMPTY | BD_SC_OV; 921 if (termios->c_iflag & INPCK) 922 port->read_status_mask |= BD_SC_FR | BD_SC_PR; 923 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 924 port->read_status_mask |= BD_SC_BR; 925 926 /* 927 * Characters to ignore 928 */ 929 port->ignore_status_mask = 0; 930 if (termios->c_iflag & IGNPAR) 931 port->ignore_status_mask |= BD_SC_PR | BD_SC_FR; 932 if (termios->c_iflag & IGNBRK) { 933 port->ignore_status_mask |= BD_SC_BR; 934 /* 935 * If we're ignore parity and break indicators, ignore 936 * overruns too. (For real raw support). 937 */ 938 if (termios->c_iflag & IGNPAR) 939 port->ignore_status_mask |= BD_SC_OV; 940 } 941 /* 942 * !!! ignore all characters if CREAD is not set 943 */ 944 if ((termios->c_cflag & CREAD) == 0) 945 port->read_status_mask &= ~BD_SC_EMPTY; 946 947 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); 948 949 /* Do we really need a spinlock here? */ 950 spin_lock_irqsave(&port->lock, flags); 951 952 /* Update the per-port timeout. */ 953 uart_update_timeout(port, termios->c_cflag, baud); 954 955 out_be16(&uccp->upsmr, upsmr); 956 if (soft_uart) { 957 out_be16(&uccup->supsmr, supsmr); 958 out_8(&uccup->rx_length, char_length); 959 960 /* Soft-UART requires a 1X multiplier for TX */ 961 qe_setbrg(qe_port->us_info.rx_clock, baud, 16); 962 qe_setbrg(qe_port->us_info.tx_clock, baud, 1); 963 } else { 964 qe_setbrg(qe_port->us_info.rx_clock, baud, 16); 965 qe_setbrg(qe_port->us_info.tx_clock, baud, 16); 966 } 967 968 spin_unlock_irqrestore(&port->lock, flags); 969 } 970 971 /* 972 * Return a pointer to a string that describes what kind of port this is. 973 */ 974 static const char *qe_uart_type(struct uart_port *port) 975 { 976 return "QE"; 977 } 978 979 /* 980 * Allocate any memory and I/O resources required by the port. 981 */ 982 static int qe_uart_request_port(struct uart_port *port) 983 { 984 int ret; 985 struct uart_qe_port *qe_port = 986 container_of(port, struct uart_qe_port, port); 987 struct ucc_slow_info *us_info = &qe_port->us_info; 988 struct ucc_slow_private *uccs; 989 unsigned int rx_size, tx_size; 990 void *bd_virt; 991 dma_addr_t bd_dma_addr = 0; 992 993 ret = ucc_slow_init(us_info, &uccs); 994 if (ret) { 995 dev_err(port->dev, "could not initialize UCC%u\n", 996 qe_port->ucc_num); 997 return ret; 998 } 999 1000 qe_port->us_private = uccs; 1001 qe_port->uccp = uccs->us_regs; 1002 qe_port->uccup = (struct ucc_uart_pram *) uccs->us_pram; 1003 qe_port->rx_bd_base = uccs->rx_bd; 1004 qe_port->tx_bd_base = uccs->tx_bd; 1005 1006 /* 1007 * Allocate the transmit and receive data buffers. 1008 */ 1009 1010 rx_size = L1_CACHE_ALIGN(qe_port->rx_nrfifos * qe_port->rx_fifosize); 1011 tx_size = L1_CACHE_ALIGN(qe_port->tx_nrfifos * qe_port->tx_fifosize); 1012 1013 bd_virt = dma_alloc_coherent(port->dev, rx_size + tx_size, &bd_dma_addr, 1014 GFP_KERNEL); 1015 if (!bd_virt) { 1016 dev_err(port->dev, "could not allocate buffer descriptors\n"); 1017 return -ENOMEM; 1018 } 1019 1020 qe_port->bd_virt = bd_virt; 1021 qe_port->bd_dma_addr = bd_dma_addr; 1022 qe_port->bd_size = rx_size + tx_size; 1023 1024 qe_port->rx_buf = bd_virt; 1025 qe_port->tx_buf = qe_port->rx_buf + rx_size; 1026 1027 return 0; 1028 } 1029 1030 /* 1031 * Configure the port. 1032 * 1033 * We say we're a CPM-type port because that's mostly true. Once the device 1034 * is configured, this driver operates almost identically to the CPM serial 1035 * driver. 1036 */ 1037 static void qe_uart_config_port(struct uart_port *port, int flags) 1038 { 1039 if (flags & UART_CONFIG_TYPE) { 1040 port->type = PORT_CPM; 1041 qe_uart_request_port(port); 1042 } 1043 } 1044 1045 /* 1046 * Release any memory and I/O resources that were allocated in 1047 * qe_uart_request_port(). 1048 */ 1049 static void qe_uart_release_port(struct uart_port *port) 1050 { 1051 struct uart_qe_port *qe_port = 1052 container_of(port, struct uart_qe_port, port); 1053 struct ucc_slow_private *uccs = qe_port->us_private; 1054 1055 dma_free_coherent(port->dev, qe_port->bd_size, qe_port->bd_virt, 1056 qe_port->bd_dma_addr); 1057 1058 ucc_slow_free(uccs); 1059 } 1060 1061 /* 1062 * Verify that the data in serial_struct is suitable for this device. 1063 */ 1064 static int qe_uart_verify_port(struct uart_port *port, 1065 struct serial_struct *ser) 1066 { 1067 if (ser->type != PORT_UNKNOWN && ser->type != PORT_CPM) 1068 return -EINVAL; 1069 1070 if (ser->irq < 0 || ser->irq >= nr_irqs) 1071 return -EINVAL; 1072 1073 if (ser->baud_base < 9600) 1074 return -EINVAL; 1075 1076 return 0; 1077 } 1078 /* UART operations 1079 * 1080 * Details on these functions can be found in Documentation/driver-api/serial/driver.rst 1081 */ 1082 static const struct uart_ops qe_uart_pops = { 1083 .tx_empty = qe_uart_tx_empty, 1084 .set_mctrl = qe_uart_set_mctrl, 1085 .get_mctrl = qe_uart_get_mctrl, 1086 .stop_tx = qe_uart_stop_tx, 1087 .start_tx = qe_uart_start_tx, 1088 .stop_rx = qe_uart_stop_rx, 1089 .break_ctl = qe_uart_break_ctl, 1090 .startup = qe_uart_startup, 1091 .shutdown = qe_uart_shutdown, 1092 .set_termios = qe_uart_set_termios, 1093 .type = qe_uart_type, 1094 .release_port = qe_uart_release_port, 1095 .request_port = qe_uart_request_port, 1096 .config_port = qe_uart_config_port, 1097 .verify_port = qe_uart_verify_port, 1098 }; 1099 1100 /* 1101 * Obtain the SOC model number and revision level 1102 * 1103 * This function parses the device tree to obtain the SOC model. It then 1104 * reads the SVR register to the revision. 1105 * 1106 * The device tree stores the SOC model two different ways. 1107 * 1108 * The new way is: 1109 * 1110 * cpu@0 { 1111 * compatible = "PowerPC,8323"; 1112 * device_type = "cpu"; 1113 * ... 1114 * 1115 * 1116 * The old way is: 1117 * PowerPC,8323@0 { 1118 * device_type = "cpu"; 1119 * ... 1120 * 1121 * This code first checks the new way, and then the old way. 1122 */ 1123 static unsigned int soc_info(unsigned int *rev_h, unsigned int *rev_l) 1124 { 1125 struct device_node *np; 1126 const char *soc_string; 1127 unsigned int svr; 1128 unsigned int soc; 1129 1130 /* Find the CPU node */ 1131 np = of_find_node_by_type(NULL, "cpu"); 1132 if (!np) 1133 return 0; 1134 /* Find the compatible property */ 1135 soc_string = of_get_property(np, "compatible", NULL); 1136 if (!soc_string) 1137 /* No compatible property, so try the name. */ 1138 soc_string = np->name; 1139 1140 /* Extract the SOC number from the "PowerPC," string */ 1141 if ((sscanf(soc_string, "PowerPC,%u", &soc) != 1) || !soc) 1142 return 0; 1143 1144 /* Get the revision from the SVR */ 1145 svr = mfspr(SPRN_SVR); 1146 *rev_h = (svr >> 4) & 0xf; 1147 *rev_l = svr & 0xf; 1148 1149 return soc; 1150 } 1151 1152 /* 1153 * requst_firmware_nowait() callback function 1154 * 1155 * This function is called by the kernel when a firmware is made available, 1156 * or if it times out waiting for the firmware. 1157 */ 1158 static void uart_firmware_cont(const struct firmware *fw, void *context) 1159 { 1160 struct qe_firmware *firmware; 1161 struct device *dev = context; 1162 int ret; 1163 1164 if (!fw) { 1165 dev_err(dev, "firmware not found\n"); 1166 return; 1167 } 1168 1169 firmware = (struct qe_firmware *) fw->data; 1170 1171 if (firmware->header.length != fw->size) { 1172 dev_err(dev, "invalid firmware\n"); 1173 goto out; 1174 } 1175 1176 ret = qe_upload_firmware(firmware); 1177 if (ret) { 1178 dev_err(dev, "could not load firmware\n"); 1179 goto out; 1180 } 1181 1182 firmware_loaded = 1; 1183 out: 1184 release_firmware(fw); 1185 } 1186 1187 static int ucc_uart_probe(struct platform_device *ofdev) 1188 { 1189 struct device_node *np = ofdev->dev.of_node; 1190 const unsigned int *iprop; /* Integer OF properties */ 1191 const char *sprop; /* String OF properties */ 1192 struct uart_qe_port *qe_port = NULL; 1193 struct resource res; 1194 int ret; 1195 1196 /* 1197 * Determine if we need Soft-UART mode 1198 */ 1199 if (of_find_property(np, "soft-uart", NULL)) { 1200 dev_dbg(&ofdev->dev, "using Soft-UART mode\n"); 1201 soft_uart = 1; 1202 } 1203 1204 /* 1205 * If we are using Soft-UART, determine if we need to upload the 1206 * firmware, too. 1207 */ 1208 if (soft_uart) { 1209 struct qe_firmware_info *qe_fw_info; 1210 1211 qe_fw_info = qe_get_firmware_info(); 1212 1213 /* Check if the firmware has been uploaded. */ 1214 if (qe_fw_info && strstr(qe_fw_info->id, "Soft-UART")) { 1215 firmware_loaded = 1; 1216 } else { 1217 char filename[32]; 1218 unsigned int soc; 1219 unsigned int rev_h; 1220 unsigned int rev_l; 1221 1222 soc = soc_info(&rev_h, &rev_l); 1223 if (!soc) { 1224 dev_err(&ofdev->dev, "unknown CPU model\n"); 1225 return -ENXIO; 1226 } 1227 sprintf(filename, "fsl_qe_ucode_uart_%u_%u%u.bin", 1228 soc, rev_h, rev_l); 1229 1230 dev_info(&ofdev->dev, "waiting for firmware %s\n", 1231 filename); 1232 1233 /* 1234 * We call request_firmware_nowait instead of 1235 * request_firmware so that the driver can load and 1236 * initialize the ports without holding up the rest of 1237 * the kernel. If hotplug support is enabled in the 1238 * kernel, then we use it. 1239 */ 1240 ret = request_firmware_nowait(THIS_MODULE, 1241 FW_ACTION_HOTPLUG, filename, &ofdev->dev, 1242 GFP_KERNEL, &ofdev->dev, uart_firmware_cont); 1243 if (ret) { 1244 dev_err(&ofdev->dev, 1245 "could not load firmware %s\n", 1246 filename); 1247 return ret; 1248 } 1249 } 1250 } 1251 1252 qe_port = kzalloc(sizeof(struct uart_qe_port), GFP_KERNEL); 1253 if (!qe_port) { 1254 dev_err(&ofdev->dev, "can't allocate QE port structure\n"); 1255 return -ENOMEM; 1256 } 1257 1258 /* Search for IRQ and mapbase */ 1259 ret = of_address_to_resource(np, 0, &res); 1260 if (ret) { 1261 dev_err(&ofdev->dev, "missing 'reg' property in device tree\n"); 1262 goto out_free; 1263 } 1264 if (!res.start) { 1265 dev_err(&ofdev->dev, "invalid 'reg' property in device tree\n"); 1266 ret = -EINVAL; 1267 goto out_free; 1268 } 1269 qe_port->port.mapbase = res.start; 1270 1271 /* Get the UCC number (device ID) */ 1272 /* UCCs are numbered 1-7 */ 1273 iprop = of_get_property(np, "cell-index", NULL); 1274 if (!iprop) { 1275 iprop = of_get_property(np, "device-id", NULL); 1276 if (!iprop) { 1277 dev_err(&ofdev->dev, "UCC is unspecified in " 1278 "device tree\n"); 1279 ret = -EINVAL; 1280 goto out_free; 1281 } 1282 } 1283 1284 if ((*iprop < 1) || (*iprop > UCC_MAX_NUM)) { 1285 dev_err(&ofdev->dev, "no support for UCC%u\n", *iprop); 1286 ret = -ENODEV; 1287 goto out_free; 1288 } 1289 qe_port->ucc_num = *iprop - 1; 1290 1291 /* 1292 * In the future, we should not require the BRG to be specified in the 1293 * device tree. If no clock-source is specified, then just pick a BRG 1294 * to use. This requires a new QE library function that manages BRG 1295 * assignments. 1296 */ 1297 1298 sprop = of_get_property(np, "rx-clock-name", NULL); 1299 if (!sprop) { 1300 dev_err(&ofdev->dev, "missing rx-clock-name in device tree\n"); 1301 ret = -ENODEV; 1302 goto out_free; 1303 } 1304 1305 qe_port->us_info.rx_clock = qe_clock_source(sprop); 1306 if ((qe_port->us_info.rx_clock < QE_BRG1) || 1307 (qe_port->us_info.rx_clock > QE_BRG16)) { 1308 dev_err(&ofdev->dev, "rx-clock-name must be a BRG for UART\n"); 1309 ret = -ENODEV; 1310 goto out_free; 1311 } 1312 1313 #ifdef LOOPBACK 1314 /* In internal loopback mode, TX and RX must use the same clock */ 1315 qe_port->us_info.tx_clock = qe_port->us_info.rx_clock; 1316 #else 1317 sprop = of_get_property(np, "tx-clock-name", NULL); 1318 if (!sprop) { 1319 dev_err(&ofdev->dev, "missing tx-clock-name in device tree\n"); 1320 ret = -ENODEV; 1321 goto out_free; 1322 } 1323 qe_port->us_info.tx_clock = qe_clock_source(sprop); 1324 #endif 1325 if ((qe_port->us_info.tx_clock < QE_BRG1) || 1326 (qe_port->us_info.tx_clock > QE_BRG16)) { 1327 dev_err(&ofdev->dev, "tx-clock-name must be a BRG for UART\n"); 1328 ret = -ENODEV; 1329 goto out_free; 1330 } 1331 1332 /* Get the port number, numbered 0-3 */ 1333 iprop = of_get_property(np, "port-number", NULL); 1334 if (!iprop) { 1335 dev_err(&ofdev->dev, "missing port-number in device tree\n"); 1336 ret = -EINVAL; 1337 goto out_free; 1338 } 1339 qe_port->port.line = *iprop; 1340 if (qe_port->port.line >= UCC_MAX_UART) { 1341 dev_err(&ofdev->dev, "port-number must be 0-%u\n", 1342 UCC_MAX_UART - 1); 1343 ret = -EINVAL; 1344 goto out_free; 1345 } 1346 1347 qe_port->port.irq = irq_of_parse_and_map(np, 0); 1348 if (qe_port->port.irq == 0) { 1349 dev_err(&ofdev->dev, "could not map IRQ for UCC%u\n", 1350 qe_port->ucc_num + 1); 1351 ret = -EINVAL; 1352 goto out_free; 1353 } 1354 1355 /* 1356 * Newer device trees have an "fsl,qe" compatible property for the QE 1357 * node, but we still need to support older device trees. 1358 */ 1359 np = of_find_compatible_node(NULL, NULL, "fsl,qe"); 1360 if (!np) { 1361 np = of_find_node_by_type(NULL, "qe"); 1362 if (!np) { 1363 dev_err(&ofdev->dev, "could not find 'qe' node\n"); 1364 ret = -EINVAL; 1365 goto out_free; 1366 } 1367 } 1368 1369 iprop = of_get_property(np, "brg-frequency", NULL); 1370 if (!iprop) { 1371 dev_err(&ofdev->dev, 1372 "missing brg-frequency in device tree\n"); 1373 ret = -EINVAL; 1374 goto out_np; 1375 } 1376 1377 if (*iprop) 1378 qe_port->port.uartclk = *iprop; 1379 else { 1380 /* 1381 * Older versions of U-Boot do not initialize the brg-frequency 1382 * property, so in this case we assume the BRG frequency is 1383 * half the QE bus frequency. 1384 */ 1385 iprop = of_get_property(np, "bus-frequency", NULL); 1386 if (!iprop) { 1387 dev_err(&ofdev->dev, 1388 "missing QE bus-frequency in device tree\n"); 1389 ret = -EINVAL; 1390 goto out_np; 1391 } 1392 if (*iprop) 1393 qe_port->port.uartclk = *iprop / 2; 1394 else { 1395 dev_err(&ofdev->dev, 1396 "invalid QE bus-frequency in device tree\n"); 1397 ret = -EINVAL; 1398 goto out_np; 1399 } 1400 } 1401 1402 spin_lock_init(&qe_port->port.lock); 1403 qe_port->np = np; 1404 qe_port->port.dev = &ofdev->dev; 1405 qe_port->port.ops = &qe_uart_pops; 1406 qe_port->port.iotype = UPIO_MEM; 1407 1408 qe_port->tx_nrfifos = TX_NUM_FIFO; 1409 qe_port->tx_fifosize = TX_BUF_SIZE; 1410 qe_port->rx_nrfifos = RX_NUM_FIFO; 1411 qe_port->rx_fifosize = RX_BUF_SIZE; 1412 1413 qe_port->wait_closing = UCC_WAIT_CLOSING; 1414 qe_port->port.fifosize = 512; 1415 qe_port->port.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP; 1416 1417 qe_port->us_info.ucc_num = qe_port->ucc_num; 1418 qe_port->us_info.regs = (phys_addr_t) res.start; 1419 qe_port->us_info.irq = qe_port->port.irq; 1420 1421 qe_port->us_info.rx_bd_ring_len = qe_port->rx_nrfifos; 1422 qe_port->us_info.tx_bd_ring_len = qe_port->tx_nrfifos; 1423 1424 /* Make sure ucc_slow_init() initializes both TX and RX */ 1425 qe_port->us_info.init_tx = 1; 1426 qe_port->us_info.init_rx = 1; 1427 1428 /* Add the port to the uart sub-system. This will cause 1429 * qe_uart_config_port() to be called, so the us_info structure must 1430 * be initialized. 1431 */ 1432 ret = uart_add_one_port(&ucc_uart_driver, &qe_port->port); 1433 if (ret) { 1434 dev_err(&ofdev->dev, "could not add /dev/ttyQE%u\n", 1435 qe_port->port.line); 1436 goto out_np; 1437 } 1438 1439 platform_set_drvdata(ofdev, qe_port); 1440 1441 dev_info(&ofdev->dev, "UCC%u assigned to /dev/ttyQE%u\n", 1442 qe_port->ucc_num + 1, qe_port->port.line); 1443 1444 /* Display the mknod command for this device */ 1445 dev_dbg(&ofdev->dev, "mknod command is 'mknod /dev/ttyQE%u c %u %u'\n", 1446 qe_port->port.line, SERIAL_QE_MAJOR, 1447 SERIAL_QE_MINOR + qe_port->port.line); 1448 1449 return 0; 1450 out_np: 1451 of_node_put(np); 1452 out_free: 1453 kfree(qe_port); 1454 return ret; 1455 } 1456 1457 static int ucc_uart_remove(struct platform_device *ofdev) 1458 { 1459 struct uart_qe_port *qe_port = platform_get_drvdata(ofdev); 1460 1461 dev_info(&ofdev->dev, "removing /dev/ttyQE%u\n", qe_port->port.line); 1462 1463 uart_remove_one_port(&ucc_uart_driver, &qe_port->port); 1464 1465 kfree(qe_port); 1466 1467 return 0; 1468 } 1469 1470 static const struct of_device_id ucc_uart_match[] = { 1471 { 1472 .type = "serial", 1473 .compatible = "ucc_uart", 1474 }, 1475 { 1476 .compatible = "fsl,t1040-ucc-uart", 1477 }, 1478 {}, 1479 }; 1480 MODULE_DEVICE_TABLE(of, ucc_uart_match); 1481 1482 static struct platform_driver ucc_uart_of_driver = { 1483 .driver = { 1484 .name = "ucc_uart", 1485 .of_match_table = ucc_uart_match, 1486 }, 1487 .probe = ucc_uart_probe, 1488 .remove = ucc_uart_remove, 1489 }; 1490 1491 static int __init ucc_uart_init(void) 1492 { 1493 int ret; 1494 1495 printk(KERN_INFO "Freescale QUICC Engine UART device driver\n"); 1496 #ifdef LOOPBACK 1497 printk(KERN_INFO "ucc-uart: Using loopback mode\n"); 1498 #endif 1499 1500 ret = uart_register_driver(&ucc_uart_driver); 1501 if (ret) { 1502 printk(KERN_ERR "ucc-uart: could not register UART driver\n"); 1503 return ret; 1504 } 1505 1506 ret = platform_driver_register(&ucc_uart_of_driver); 1507 if (ret) { 1508 printk(KERN_ERR 1509 "ucc-uart: could not register platform driver\n"); 1510 uart_unregister_driver(&ucc_uart_driver); 1511 } 1512 1513 return ret; 1514 } 1515 1516 static void __exit ucc_uart_exit(void) 1517 { 1518 printk(KERN_INFO 1519 "Freescale QUICC Engine UART device driver unloading\n"); 1520 1521 platform_driver_unregister(&ucc_uart_of_driver); 1522 uart_unregister_driver(&ucc_uart_driver); 1523 } 1524 1525 module_init(ucc_uart_init); 1526 module_exit(ucc_uart_exit); 1527 1528 MODULE_DESCRIPTION("Freescale QUICC Engine (QE) UART"); 1529 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>"); 1530 MODULE_LICENSE("GPL v2"); 1531 MODULE_ALIAS_CHARDEV_MAJOR(SERIAL_QE_MAJOR); 1532 1533