1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * uartlite.c: Serial driver for Xilinx uartlite serial controller 4 * 5 * Copyright (C) 2006 Peter Korsgaard <jacmet@sunsite.dk> 6 * Copyright (C) 2007 Secret Lab Technologies Ltd. 7 */ 8 9 #include <linux/platform_device.h> 10 #include <linux/module.h> 11 #include <linux/bitfield.h> 12 #include <linux/console.h> 13 #include <linux/serial.h> 14 #include <linux/serial_core.h> 15 #include <linux/tty.h> 16 #include <linux/tty_flip.h> 17 #include <linux/delay.h> 18 #include <linux/interrupt.h> 19 #include <linux/init.h> 20 #include <linux/io.h> 21 #include <linux/iopoll.h> 22 #include <linux/of.h> 23 #include <linux/of_address.h> 24 #include <linux/of_device.h> 25 #include <linux/of_platform.h> 26 #include <linux/clk.h> 27 #include <linux/pm_runtime.h> 28 29 #define ULITE_NAME "ttyUL" 30 #define ULITE_MAJOR 204 31 #define ULITE_MINOR 187 32 #define ULITE_NR_UARTS CONFIG_SERIAL_UARTLITE_NR_UARTS 33 34 /* --------------------------------------------------------------------- 35 * Register definitions 36 * 37 * For register details see datasheet: 38 * https://www.xilinx.com/support/documentation/ip_documentation/opb_uartlite.pdf 39 */ 40 41 #define ULITE_RX 0x00 42 #define ULITE_TX 0x04 43 #define ULITE_STATUS 0x08 44 #define ULITE_CONTROL 0x0c 45 46 #define ULITE_REGION 16 47 48 #define ULITE_STATUS_RXVALID 0x01 49 #define ULITE_STATUS_RXFULL 0x02 50 #define ULITE_STATUS_TXEMPTY 0x04 51 #define ULITE_STATUS_TXFULL 0x08 52 #define ULITE_STATUS_IE 0x10 53 #define ULITE_STATUS_OVERRUN 0x20 54 #define ULITE_STATUS_FRAME 0x40 55 #define ULITE_STATUS_PARITY 0x80 56 57 #define ULITE_CONTROL_RST_TX 0x01 58 #define ULITE_CONTROL_RST_RX 0x02 59 #define ULITE_CONTROL_IE 0x10 60 #define UART_AUTOSUSPEND_TIMEOUT 3000 /* ms */ 61 62 /* Static pointer to console port */ 63 #ifdef CONFIG_SERIAL_UARTLITE_CONSOLE 64 static struct uart_port *console_port; 65 #endif 66 67 /** 68 * struct uartlite_data: Driver private data 69 * reg_ops: Functions to read/write registers 70 * clk: Our parent clock, if present 71 * baud: The baud rate configured when this device was synthesized 72 * cflags: The cflags for parity and data bits 73 */ 74 struct uartlite_data { 75 const struct uartlite_reg_ops *reg_ops; 76 struct clk *clk; 77 unsigned int baud; 78 tcflag_t cflags; 79 }; 80 81 struct uartlite_reg_ops { 82 u32 (*in)(void __iomem *addr); 83 void (*out)(u32 val, void __iomem *addr); 84 }; 85 86 static u32 uartlite_inbe32(void __iomem *addr) 87 { 88 return ioread32be(addr); 89 } 90 91 static void uartlite_outbe32(u32 val, void __iomem *addr) 92 { 93 iowrite32be(val, addr); 94 } 95 96 static const struct uartlite_reg_ops uartlite_be = { 97 .in = uartlite_inbe32, 98 .out = uartlite_outbe32, 99 }; 100 101 static u32 uartlite_inle32(void __iomem *addr) 102 { 103 return ioread32(addr); 104 } 105 106 static void uartlite_outle32(u32 val, void __iomem *addr) 107 { 108 iowrite32(val, addr); 109 } 110 111 static const struct uartlite_reg_ops uartlite_le = { 112 .in = uartlite_inle32, 113 .out = uartlite_outle32, 114 }; 115 116 static inline u32 uart_in32(u32 offset, struct uart_port *port) 117 { 118 struct uartlite_data *pdata = port->private_data; 119 120 return pdata->reg_ops->in(port->membase + offset); 121 } 122 123 static inline void uart_out32(u32 val, u32 offset, struct uart_port *port) 124 { 125 struct uartlite_data *pdata = port->private_data; 126 127 pdata->reg_ops->out(val, port->membase + offset); 128 } 129 130 static struct uart_port ulite_ports[ULITE_NR_UARTS]; 131 132 static struct uart_driver ulite_uart_driver; 133 134 /* --------------------------------------------------------------------- 135 * Core UART driver operations 136 */ 137 138 static int ulite_receive(struct uart_port *port, int stat) 139 { 140 struct tty_port *tport = &port->state->port; 141 unsigned char ch = 0; 142 char flag = TTY_NORMAL; 143 144 if ((stat & (ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN 145 | ULITE_STATUS_FRAME)) == 0) 146 return 0; 147 148 /* stats */ 149 if (stat & ULITE_STATUS_RXVALID) { 150 port->icount.rx++; 151 ch = uart_in32(ULITE_RX, port); 152 153 if (stat & ULITE_STATUS_PARITY) 154 port->icount.parity++; 155 } 156 157 if (stat & ULITE_STATUS_OVERRUN) 158 port->icount.overrun++; 159 160 if (stat & ULITE_STATUS_FRAME) 161 port->icount.frame++; 162 163 164 /* drop byte with parity error if IGNPAR specificed */ 165 if (stat & port->ignore_status_mask & ULITE_STATUS_PARITY) 166 stat &= ~ULITE_STATUS_RXVALID; 167 168 stat &= port->read_status_mask; 169 170 if (stat & ULITE_STATUS_PARITY) 171 flag = TTY_PARITY; 172 173 174 stat &= ~port->ignore_status_mask; 175 176 if (stat & ULITE_STATUS_RXVALID) 177 tty_insert_flip_char(tport, ch, flag); 178 179 if (stat & ULITE_STATUS_FRAME) 180 tty_insert_flip_char(tport, 0, TTY_FRAME); 181 182 if (stat & ULITE_STATUS_OVERRUN) 183 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 184 185 return 1; 186 } 187 188 static int ulite_transmit(struct uart_port *port, int stat) 189 { 190 struct circ_buf *xmit = &port->state->xmit; 191 192 if (stat & ULITE_STATUS_TXFULL) 193 return 0; 194 195 if (port->x_char) { 196 uart_out32(port->x_char, ULITE_TX, port); 197 port->x_char = 0; 198 port->icount.tx++; 199 return 1; 200 } 201 202 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) 203 return 0; 204 205 uart_out32(xmit->buf[xmit->tail], ULITE_TX, port); 206 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE-1); 207 port->icount.tx++; 208 209 /* wake up */ 210 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 211 uart_write_wakeup(port); 212 213 return 1; 214 } 215 216 static irqreturn_t ulite_isr(int irq, void *dev_id) 217 { 218 struct uart_port *port = dev_id; 219 int stat, busy, n = 0; 220 unsigned long flags; 221 222 do { 223 spin_lock_irqsave(&port->lock, flags); 224 stat = uart_in32(ULITE_STATUS, port); 225 busy = ulite_receive(port, stat); 226 busy |= ulite_transmit(port, stat); 227 spin_unlock_irqrestore(&port->lock, flags); 228 n++; 229 } while (busy); 230 231 /* work done? */ 232 if (n > 1) { 233 tty_flip_buffer_push(&port->state->port); 234 return IRQ_HANDLED; 235 } else { 236 return IRQ_NONE; 237 } 238 } 239 240 static unsigned int ulite_tx_empty(struct uart_port *port) 241 { 242 unsigned long flags; 243 unsigned int ret; 244 245 spin_lock_irqsave(&port->lock, flags); 246 ret = uart_in32(ULITE_STATUS, port); 247 spin_unlock_irqrestore(&port->lock, flags); 248 249 return ret & ULITE_STATUS_TXEMPTY ? TIOCSER_TEMT : 0; 250 } 251 252 static unsigned int ulite_get_mctrl(struct uart_port *port) 253 { 254 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; 255 } 256 257 static void ulite_set_mctrl(struct uart_port *port, unsigned int mctrl) 258 { 259 /* N/A */ 260 } 261 262 static void ulite_stop_tx(struct uart_port *port) 263 { 264 /* N/A */ 265 } 266 267 static void ulite_start_tx(struct uart_port *port) 268 { 269 ulite_transmit(port, uart_in32(ULITE_STATUS, port)); 270 } 271 272 static void ulite_stop_rx(struct uart_port *port) 273 { 274 /* don't forward any more data (like !CREAD) */ 275 port->ignore_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY 276 | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN; 277 } 278 279 static void ulite_break_ctl(struct uart_port *port, int ctl) 280 { 281 /* N/A */ 282 } 283 284 static int ulite_startup(struct uart_port *port) 285 { 286 struct uartlite_data *pdata = port->private_data; 287 int ret; 288 289 ret = clk_enable(pdata->clk); 290 if (ret) { 291 dev_err(port->dev, "Failed to enable clock\n"); 292 return ret; 293 } 294 295 ret = request_irq(port->irq, ulite_isr, IRQF_SHARED | IRQF_TRIGGER_RISING, 296 "uartlite", port); 297 if (ret) 298 return ret; 299 300 uart_out32(ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX, 301 ULITE_CONTROL, port); 302 uart_out32(ULITE_CONTROL_IE, ULITE_CONTROL, port); 303 304 return 0; 305 } 306 307 static void ulite_shutdown(struct uart_port *port) 308 { 309 struct uartlite_data *pdata = port->private_data; 310 311 uart_out32(0, ULITE_CONTROL, port); 312 uart_in32(ULITE_CONTROL, port); /* dummy */ 313 free_irq(port->irq, port); 314 clk_disable(pdata->clk); 315 } 316 317 static void ulite_set_termios(struct uart_port *port, struct ktermios *termios, 318 struct ktermios *old) 319 { 320 unsigned long flags; 321 struct uartlite_data *pdata = port->private_data; 322 323 /* Set termios to what the hardware supports */ 324 termios->c_cflag &= ~(BRKINT | CSTOPB | PARENB | PARODD | CSIZE); 325 termios->c_cflag |= pdata->cflags & (PARENB | PARODD | CSIZE); 326 tty_termios_encode_baud_rate(termios, pdata->baud, pdata->baud); 327 328 spin_lock_irqsave(&port->lock, flags); 329 330 port->read_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN 331 | ULITE_STATUS_TXFULL; 332 333 if (termios->c_iflag & INPCK) 334 port->read_status_mask |= 335 ULITE_STATUS_PARITY | ULITE_STATUS_FRAME; 336 337 port->ignore_status_mask = 0; 338 if (termios->c_iflag & IGNPAR) 339 port->ignore_status_mask |= ULITE_STATUS_PARITY 340 | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN; 341 342 /* ignore all characters if CREAD is not set */ 343 if ((termios->c_cflag & CREAD) == 0) 344 port->ignore_status_mask |= 345 ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY 346 | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN; 347 348 /* update timeout */ 349 uart_update_timeout(port, termios->c_cflag, pdata->baud); 350 351 spin_unlock_irqrestore(&port->lock, flags); 352 } 353 354 static const char *ulite_type(struct uart_port *port) 355 { 356 return port->type == PORT_UARTLITE ? "uartlite" : NULL; 357 } 358 359 static void ulite_release_port(struct uart_port *port) 360 { 361 release_mem_region(port->mapbase, ULITE_REGION); 362 iounmap(port->membase); 363 port->membase = NULL; 364 } 365 366 static int ulite_request_port(struct uart_port *port) 367 { 368 struct uartlite_data *pdata = port->private_data; 369 int ret; 370 371 pr_debug("ulite console: port=%p; port->mapbase=%llx\n", 372 port, (unsigned long long) port->mapbase); 373 374 if (!request_mem_region(port->mapbase, ULITE_REGION, "uartlite")) { 375 dev_err(port->dev, "Memory region busy\n"); 376 return -EBUSY; 377 } 378 379 port->membase = ioremap(port->mapbase, ULITE_REGION); 380 if (!port->membase) { 381 dev_err(port->dev, "Unable to map registers\n"); 382 release_mem_region(port->mapbase, ULITE_REGION); 383 return -EBUSY; 384 } 385 386 pdata->reg_ops = &uartlite_be; 387 ret = uart_in32(ULITE_CONTROL, port); 388 uart_out32(ULITE_CONTROL_RST_TX, ULITE_CONTROL, port); 389 ret = uart_in32(ULITE_STATUS, port); 390 /* Endianess detection */ 391 if ((ret & ULITE_STATUS_TXEMPTY) != ULITE_STATUS_TXEMPTY) 392 pdata->reg_ops = &uartlite_le; 393 394 return 0; 395 } 396 397 static void ulite_config_port(struct uart_port *port, int flags) 398 { 399 if (!ulite_request_port(port)) 400 port->type = PORT_UARTLITE; 401 } 402 403 static int ulite_verify_port(struct uart_port *port, struct serial_struct *ser) 404 { 405 /* we don't want the core code to modify any port params */ 406 return -EINVAL; 407 } 408 409 static void ulite_pm(struct uart_port *port, unsigned int state, 410 unsigned int oldstate) 411 { 412 int ret; 413 414 if (!state) { 415 ret = pm_runtime_get_sync(port->dev); 416 if (ret < 0) 417 dev_err(port->dev, "Failed to enable clocks\n"); 418 } else { 419 pm_runtime_mark_last_busy(port->dev); 420 pm_runtime_put_autosuspend(port->dev); 421 } 422 } 423 424 #ifdef CONFIG_CONSOLE_POLL 425 static int ulite_get_poll_char(struct uart_port *port) 426 { 427 if (!(uart_in32(ULITE_STATUS, port) & ULITE_STATUS_RXVALID)) 428 return NO_POLL_CHAR; 429 430 return uart_in32(ULITE_RX, port); 431 } 432 433 static void ulite_put_poll_char(struct uart_port *port, unsigned char ch) 434 { 435 while (uart_in32(ULITE_STATUS, port) & ULITE_STATUS_TXFULL) 436 cpu_relax(); 437 438 /* write char to device */ 439 uart_out32(ch, ULITE_TX, port); 440 } 441 #endif 442 443 static const struct uart_ops ulite_ops = { 444 .tx_empty = ulite_tx_empty, 445 .set_mctrl = ulite_set_mctrl, 446 .get_mctrl = ulite_get_mctrl, 447 .stop_tx = ulite_stop_tx, 448 .start_tx = ulite_start_tx, 449 .stop_rx = ulite_stop_rx, 450 .break_ctl = ulite_break_ctl, 451 .startup = ulite_startup, 452 .shutdown = ulite_shutdown, 453 .set_termios = ulite_set_termios, 454 .type = ulite_type, 455 .release_port = ulite_release_port, 456 .request_port = ulite_request_port, 457 .config_port = ulite_config_port, 458 .verify_port = ulite_verify_port, 459 .pm = ulite_pm, 460 #ifdef CONFIG_CONSOLE_POLL 461 .poll_get_char = ulite_get_poll_char, 462 .poll_put_char = ulite_put_poll_char, 463 #endif 464 }; 465 466 /* --------------------------------------------------------------------- 467 * Console driver operations 468 */ 469 470 #ifdef CONFIG_SERIAL_UARTLITE_CONSOLE 471 static void ulite_console_wait_tx(struct uart_port *port) 472 { 473 u8 val; 474 475 /* 476 * Spin waiting for TX fifo to have space available. 477 * When using the Microblaze Debug Module this can take up to 1s 478 */ 479 if (read_poll_timeout_atomic(uart_in32, val, !(val & ULITE_STATUS_TXFULL), 480 0, 1000000, false, ULITE_STATUS, port)) 481 dev_warn(port->dev, 482 "timeout waiting for TX buffer empty\n"); 483 } 484 485 static void ulite_console_putchar(struct uart_port *port, int ch) 486 { 487 ulite_console_wait_tx(port); 488 uart_out32(ch, ULITE_TX, port); 489 } 490 491 static void ulite_console_write(struct console *co, const char *s, 492 unsigned int count) 493 { 494 struct uart_port *port = console_port; 495 unsigned long flags; 496 unsigned int ier; 497 int locked = 1; 498 499 if (oops_in_progress) { 500 locked = spin_trylock_irqsave(&port->lock, flags); 501 } else 502 spin_lock_irqsave(&port->lock, flags); 503 504 /* save and disable interrupt */ 505 ier = uart_in32(ULITE_STATUS, port) & ULITE_STATUS_IE; 506 uart_out32(0, ULITE_CONTROL, port); 507 508 uart_console_write(port, s, count, ulite_console_putchar); 509 510 ulite_console_wait_tx(port); 511 512 /* restore interrupt state */ 513 if (ier) 514 uart_out32(ULITE_CONTROL_IE, ULITE_CONTROL, port); 515 516 if (locked) 517 spin_unlock_irqrestore(&port->lock, flags); 518 } 519 520 static int ulite_console_setup(struct console *co, char *options) 521 { 522 struct uart_port *port = NULL; 523 int baud = 9600; 524 int bits = 8; 525 int parity = 'n'; 526 int flow = 'n'; 527 528 if (co->index >= 0 && co->index < ULITE_NR_UARTS) 529 port = ulite_ports + co->index; 530 531 /* Has the device been initialized yet? */ 532 if (!port || !port->mapbase) { 533 pr_debug("console on ttyUL%i not present\n", co->index); 534 return -ENODEV; 535 } 536 537 console_port = port; 538 539 /* not initialized yet? */ 540 if (!port->membase) { 541 if (ulite_request_port(port)) 542 return -ENODEV; 543 } 544 545 if (options) 546 uart_parse_options(options, &baud, &parity, &bits, &flow); 547 548 return uart_set_options(port, co, baud, parity, bits, flow); 549 } 550 551 static struct console ulite_console = { 552 .name = ULITE_NAME, 553 .write = ulite_console_write, 554 .device = uart_console_device, 555 .setup = ulite_console_setup, 556 .flags = CON_PRINTBUFFER, 557 .index = -1, /* Specified on the cmdline (e.g. console=ttyUL0 ) */ 558 .data = &ulite_uart_driver, 559 }; 560 561 static void early_uartlite_putc(struct uart_port *port, int c) 562 { 563 /* 564 * Limit how many times we'll spin waiting for TX FIFO status. 565 * This will prevent lockups if the base address is incorrectly 566 * set, or any other issue on the UARTLITE. 567 * This limit is pretty arbitrary, unless we are at about 10 baud 568 * we'll never timeout on a working UART. 569 */ 570 unsigned retries = 1000000; 571 572 while (--retries && 573 (readl(port->membase + ULITE_STATUS) & ULITE_STATUS_TXFULL)) 574 ; 575 576 /* Only attempt the iowrite if we didn't timeout */ 577 if (retries) 578 writel(c & 0xff, port->membase + ULITE_TX); 579 } 580 581 static void early_uartlite_write(struct console *console, 582 const char *s, unsigned n) 583 { 584 struct earlycon_device *device = console->data; 585 uart_console_write(&device->port, s, n, early_uartlite_putc); 586 } 587 588 static int __init early_uartlite_setup(struct earlycon_device *device, 589 const char *options) 590 { 591 if (!device->port.membase) 592 return -ENODEV; 593 594 device->con->write = early_uartlite_write; 595 return 0; 596 } 597 EARLYCON_DECLARE(uartlite, early_uartlite_setup); 598 OF_EARLYCON_DECLARE(uartlite_b, "xlnx,opb-uartlite-1.00.b", early_uartlite_setup); 599 OF_EARLYCON_DECLARE(uartlite_a, "xlnx,xps-uartlite-1.00.a", early_uartlite_setup); 600 601 #endif /* CONFIG_SERIAL_UARTLITE_CONSOLE */ 602 603 static struct uart_driver ulite_uart_driver = { 604 .owner = THIS_MODULE, 605 .driver_name = "uartlite", 606 .dev_name = ULITE_NAME, 607 .major = ULITE_MAJOR, 608 .minor = ULITE_MINOR, 609 .nr = ULITE_NR_UARTS, 610 #ifdef CONFIG_SERIAL_UARTLITE_CONSOLE 611 .cons = &ulite_console, 612 #endif 613 }; 614 615 /* --------------------------------------------------------------------- 616 * Port assignment functions (mapping devices to uart_port structures) 617 */ 618 619 /** ulite_assign: register a uartlite device with the driver 620 * 621 * @dev: pointer to device structure 622 * @id: requested id number. Pass -1 for automatic port assignment 623 * @base: base address of uartlite registers 624 * @irq: irq number for uartlite 625 * @pdata: private data for uartlite 626 * 627 * Returns: 0 on success, <0 otherwise 628 */ 629 static int ulite_assign(struct device *dev, int id, phys_addr_t base, int irq, 630 struct uartlite_data *pdata) 631 { 632 struct uart_port *port; 633 int rc; 634 635 /* if id = -1; then scan for a free id and use that */ 636 if (id < 0) { 637 for (id = 0; id < ULITE_NR_UARTS; id++) 638 if (ulite_ports[id].mapbase == 0) 639 break; 640 } 641 if (id < 0 || id >= ULITE_NR_UARTS) { 642 dev_err(dev, "%s%i too large\n", ULITE_NAME, id); 643 return -EINVAL; 644 } 645 646 if ((ulite_ports[id].mapbase) && (ulite_ports[id].mapbase != base)) { 647 dev_err(dev, "cannot assign to %s%i; it is already in use\n", 648 ULITE_NAME, id); 649 return -EBUSY; 650 } 651 652 port = &ulite_ports[id]; 653 654 spin_lock_init(&port->lock); 655 port->fifosize = 16; 656 port->regshift = 2; 657 port->iotype = UPIO_MEM; 658 port->iobase = 1; /* mark port in use */ 659 port->mapbase = base; 660 port->membase = NULL; 661 port->ops = &ulite_ops; 662 port->irq = irq; 663 port->flags = UPF_BOOT_AUTOCONF; 664 port->dev = dev; 665 port->type = PORT_UNKNOWN; 666 port->line = id; 667 port->private_data = pdata; 668 669 dev_set_drvdata(dev, port); 670 671 /* Register the port */ 672 rc = uart_add_one_port(&ulite_uart_driver, port); 673 if (rc) { 674 dev_err(dev, "uart_add_one_port() failed; err=%i\n", rc); 675 port->mapbase = 0; 676 dev_set_drvdata(dev, NULL); 677 return rc; 678 } 679 680 return 0; 681 } 682 683 /** ulite_release: register a uartlite device with the driver 684 * 685 * @dev: pointer to device structure 686 */ 687 static int ulite_release(struct device *dev) 688 { 689 struct uart_port *port = dev_get_drvdata(dev); 690 int rc = 0; 691 692 if (port) { 693 rc = uart_remove_one_port(&ulite_uart_driver, port); 694 dev_set_drvdata(dev, NULL); 695 port->mapbase = 0; 696 } 697 698 return rc; 699 } 700 701 /** 702 * ulite_suspend - Stop the device. 703 * 704 * @dev: handle to the device structure. 705 * Return: 0 always. 706 */ 707 static int __maybe_unused ulite_suspend(struct device *dev) 708 { 709 struct uart_port *port = dev_get_drvdata(dev); 710 711 if (port) 712 uart_suspend_port(&ulite_uart_driver, port); 713 714 return 0; 715 } 716 717 /** 718 * ulite_resume - Resume the device. 719 * 720 * @dev: handle to the device structure. 721 * Return: 0 on success, errno otherwise. 722 */ 723 static int __maybe_unused ulite_resume(struct device *dev) 724 { 725 struct uart_port *port = dev_get_drvdata(dev); 726 727 if (port) 728 uart_resume_port(&ulite_uart_driver, port); 729 730 return 0; 731 } 732 733 static int __maybe_unused ulite_runtime_suspend(struct device *dev) 734 { 735 struct uart_port *port = dev_get_drvdata(dev); 736 struct uartlite_data *pdata = port->private_data; 737 738 clk_disable(pdata->clk); 739 return 0; 740 }; 741 742 static int __maybe_unused ulite_runtime_resume(struct device *dev) 743 { 744 struct uart_port *port = dev_get_drvdata(dev); 745 struct uartlite_data *pdata = port->private_data; 746 int ret; 747 748 ret = clk_enable(pdata->clk); 749 if (ret) { 750 dev_err(dev, "Cannot enable clock.\n"); 751 return ret; 752 } 753 return 0; 754 } 755 756 /* --------------------------------------------------------------------- 757 * Platform bus binding 758 */ 759 760 static const struct dev_pm_ops ulite_pm_ops = { 761 SET_SYSTEM_SLEEP_PM_OPS(ulite_suspend, ulite_resume) 762 SET_RUNTIME_PM_OPS(ulite_runtime_suspend, 763 ulite_runtime_resume, NULL) 764 }; 765 766 #if defined(CONFIG_OF) 767 /* Match table for of_platform binding */ 768 static const struct of_device_id ulite_of_match[] = { 769 { .compatible = "xlnx,opb-uartlite-1.00.b", }, 770 { .compatible = "xlnx,xps-uartlite-1.00.a", }, 771 {} 772 }; 773 MODULE_DEVICE_TABLE(of, ulite_of_match); 774 #endif /* CONFIG_OF */ 775 776 static int ulite_probe(struct platform_device *pdev) 777 { 778 struct resource *res; 779 struct uartlite_data *pdata; 780 int irq, ret; 781 int id = pdev->id; 782 783 pdata = devm_kzalloc(&pdev->dev, sizeof(struct uartlite_data), 784 GFP_KERNEL); 785 if (!pdata) 786 return -ENOMEM; 787 788 if (IS_ENABLED(CONFIG_OF)) { 789 const char *prop; 790 struct device_node *np = pdev->dev.of_node; 791 u32 val = 0; 792 793 prop = "port-number"; 794 ret = of_property_read_u32(np, prop, &id); 795 if (ret && ret != -EINVAL) 796 of_err: 797 return dev_err_probe(&pdev->dev, ret, 798 "could not read %s\n", prop); 799 800 prop = "current-speed"; 801 ret = of_property_read_u32(np, prop, &pdata->baud); 802 if (ret) 803 goto of_err; 804 805 prop = "xlnx,use-parity"; 806 ret = of_property_read_u32(np, prop, &val); 807 if (ret && ret != -EINVAL) 808 goto of_err; 809 810 if (val) { 811 prop = "xlnx,odd-parity"; 812 ret = of_property_read_u32(np, prop, &val); 813 if (ret) 814 goto of_err; 815 816 if (val) 817 pdata->cflags |= PARODD; 818 pdata->cflags |= PARENB; 819 } 820 821 val = 8; 822 prop = "xlnx,data-bits"; 823 ret = of_property_read_u32(np, prop, &val); 824 if (ret && ret != -EINVAL) 825 goto of_err; 826 827 switch (val) { 828 case 5: 829 pdata->cflags |= CS5; 830 break; 831 case 6: 832 pdata->cflags |= CS6; 833 break; 834 case 7: 835 pdata->cflags |= CS7; 836 break; 837 case 8: 838 pdata->cflags |= CS8; 839 break; 840 default: 841 return dev_err_probe(&pdev->dev, -EINVAL, 842 "bad data bits %d\n", val); 843 } 844 } else { 845 pdata->baud = 9600; 846 pdata->cflags = CS8; 847 } 848 849 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 850 if (!res) 851 return -ENODEV; 852 853 irq = platform_get_irq(pdev, 0); 854 if (irq < 0) 855 return irq; 856 857 pdata->clk = devm_clk_get(&pdev->dev, "s_axi_aclk"); 858 if (IS_ERR(pdata->clk)) { 859 if (PTR_ERR(pdata->clk) != -ENOENT) 860 return PTR_ERR(pdata->clk); 861 862 /* 863 * Clock framework support is optional, continue on 864 * anyways if we don't find a matching clock. 865 */ 866 pdata->clk = NULL; 867 } 868 869 ret = clk_prepare_enable(pdata->clk); 870 if (ret) { 871 dev_err(&pdev->dev, "Failed to prepare clock\n"); 872 return ret; 873 } 874 875 pm_runtime_use_autosuspend(&pdev->dev); 876 pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT); 877 pm_runtime_set_active(&pdev->dev); 878 pm_runtime_enable(&pdev->dev); 879 880 if (!ulite_uart_driver.state) { 881 dev_dbg(&pdev->dev, "uartlite: calling uart_register_driver()\n"); 882 ret = uart_register_driver(&ulite_uart_driver); 883 if (ret < 0) { 884 dev_err(&pdev->dev, "Failed to register driver\n"); 885 clk_disable_unprepare(pdata->clk); 886 return ret; 887 } 888 } 889 890 ret = ulite_assign(&pdev->dev, id, res->start, irq, pdata); 891 892 pm_runtime_mark_last_busy(&pdev->dev); 893 pm_runtime_put_autosuspend(&pdev->dev); 894 895 return ret; 896 } 897 898 static int ulite_remove(struct platform_device *pdev) 899 { 900 struct uart_port *port = dev_get_drvdata(&pdev->dev); 901 struct uartlite_data *pdata = port->private_data; 902 int rc; 903 904 clk_disable_unprepare(pdata->clk); 905 rc = ulite_release(&pdev->dev); 906 pm_runtime_disable(&pdev->dev); 907 pm_runtime_set_suspended(&pdev->dev); 908 pm_runtime_dont_use_autosuspend(&pdev->dev); 909 return rc; 910 } 911 912 /* work with hotplug and coldplug */ 913 MODULE_ALIAS("platform:uartlite"); 914 915 static struct platform_driver ulite_platform_driver = { 916 .probe = ulite_probe, 917 .remove = ulite_remove, 918 .driver = { 919 .name = "uartlite", 920 .of_match_table = of_match_ptr(ulite_of_match), 921 .pm = &ulite_pm_ops, 922 }, 923 }; 924 925 /* --------------------------------------------------------------------- 926 * Module setup/teardown 927 */ 928 929 static int __init ulite_init(void) 930 { 931 932 pr_debug("uartlite: calling platform_driver_register()\n"); 933 return platform_driver_register(&ulite_platform_driver); 934 } 935 936 static void __exit ulite_exit(void) 937 { 938 platform_driver_unregister(&ulite_platform_driver); 939 if (ulite_uart_driver.state) 940 uart_unregister_driver(&ulite_uart_driver); 941 } 942 943 module_init(ulite_init); 944 module_exit(ulite_exit); 945 946 MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>"); 947 MODULE_DESCRIPTION("Xilinx uartlite serial driver"); 948 MODULE_LICENSE("GPL"); 949