1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * uartlite.c: Serial driver for Xilinx uartlite serial controller 4 * 5 * Copyright (C) 2006 Peter Korsgaard <jacmet@sunsite.dk> 6 * Copyright (C) 2007 Secret Lab Technologies Ltd. 7 */ 8 9 #include <linux/platform_device.h> 10 #include <linux/module.h> 11 #include <linux/bitfield.h> 12 #include <linux/console.h> 13 #include <linux/serial.h> 14 #include <linux/serial_core.h> 15 #include <linux/tty.h> 16 #include <linux/tty_flip.h> 17 #include <linux/delay.h> 18 #include <linux/interrupt.h> 19 #include <linux/init.h> 20 #include <linux/io.h> 21 #include <linux/iopoll.h> 22 #include <linux/of.h> 23 #include <linux/of_address.h> 24 #include <linux/of_device.h> 25 #include <linux/of_platform.h> 26 #include <linux/clk.h> 27 #include <linux/pm_runtime.h> 28 29 #define ULITE_NAME "ttyUL" 30 #define ULITE_MAJOR 204 31 #define ULITE_MINOR 187 32 #define ULITE_NR_UARTS CONFIG_SERIAL_UARTLITE_NR_UARTS 33 34 /* --------------------------------------------------------------------- 35 * Register definitions 36 * 37 * For register details see datasheet: 38 * https://www.xilinx.com/support/documentation/ip_documentation/opb_uartlite.pdf 39 */ 40 41 #define ULITE_RX 0x00 42 #define ULITE_TX 0x04 43 #define ULITE_STATUS 0x08 44 #define ULITE_CONTROL 0x0c 45 46 #define ULITE_REGION 16 47 48 #define ULITE_STATUS_RXVALID 0x01 49 #define ULITE_STATUS_RXFULL 0x02 50 #define ULITE_STATUS_TXEMPTY 0x04 51 #define ULITE_STATUS_TXFULL 0x08 52 #define ULITE_STATUS_IE 0x10 53 #define ULITE_STATUS_OVERRUN 0x20 54 #define ULITE_STATUS_FRAME 0x40 55 #define ULITE_STATUS_PARITY 0x80 56 57 #define ULITE_CONTROL_RST_TX 0x01 58 #define ULITE_CONTROL_RST_RX 0x02 59 #define ULITE_CONTROL_IE 0x10 60 #define UART_AUTOSUSPEND_TIMEOUT 3000 /* ms */ 61 62 /* Static pointer to console port */ 63 #ifdef CONFIG_SERIAL_UARTLITE_CONSOLE 64 static struct uart_port *console_port; 65 #endif 66 67 /** 68 * struct uartlite_data: Driver private data 69 * reg_ops: Functions to read/write registers 70 * clk: Our parent clock, if present 71 * baud: The baud rate configured when this device was synthesized 72 * cflags: The cflags for parity and data bits 73 */ 74 struct uartlite_data { 75 const struct uartlite_reg_ops *reg_ops; 76 struct clk *clk; 77 unsigned int baud; 78 tcflag_t cflags; 79 }; 80 81 struct uartlite_reg_ops { 82 u32 (*in)(void __iomem *addr); 83 void (*out)(u32 val, void __iomem *addr); 84 }; 85 86 static u32 uartlite_inbe32(void __iomem *addr) 87 { 88 return ioread32be(addr); 89 } 90 91 static void uartlite_outbe32(u32 val, void __iomem *addr) 92 { 93 iowrite32be(val, addr); 94 } 95 96 static const struct uartlite_reg_ops uartlite_be = { 97 .in = uartlite_inbe32, 98 .out = uartlite_outbe32, 99 }; 100 101 static u32 uartlite_inle32(void __iomem *addr) 102 { 103 return ioread32(addr); 104 } 105 106 static void uartlite_outle32(u32 val, void __iomem *addr) 107 { 108 iowrite32(val, addr); 109 } 110 111 static const struct uartlite_reg_ops uartlite_le = { 112 .in = uartlite_inle32, 113 .out = uartlite_outle32, 114 }; 115 116 static inline u32 uart_in32(u32 offset, struct uart_port *port) 117 { 118 struct uartlite_data *pdata = port->private_data; 119 120 return pdata->reg_ops->in(port->membase + offset); 121 } 122 123 static inline void uart_out32(u32 val, u32 offset, struct uart_port *port) 124 { 125 struct uartlite_data *pdata = port->private_data; 126 127 pdata->reg_ops->out(val, port->membase + offset); 128 } 129 130 static struct uart_port ulite_ports[ULITE_NR_UARTS]; 131 132 static struct uart_driver ulite_uart_driver; 133 134 /* --------------------------------------------------------------------- 135 * Core UART driver operations 136 */ 137 138 static int ulite_receive(struct uart_port *port, int stat) 139 { 140 struct tty_port *tport = &port->state->port; 141 unsigned char ch = 0; 142 char flag = TTY_NORMAL; 143 144 if ((stat & (ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN 145 | ULITE_STATUS_FRAME)) == 0) 146 return 0; 147 148 /* stats */ 149 if (stat & ULITE_STATUS_RXVALID) { 150 port->icount.rx++; 151 ch = uart_in32(ULITE_RX, port); 152 153 if (stat & ULITE_STATUS_PARITY) 154 port->icount.parity++; 155 } 156 157 if (stat & ULITE_STATUS_OVERRUN) 158 port->icount.overrun++; 159 160 if (stat & ULITE_STATUS_FRAME) 161 port->icount.frame++; 162 163 164 /* drop byte with parity error if IGNPAR specificed */ 165 if (stat & port->ignore_status_mask & ULITE_STATUS_PARITY) 166 stat &= ~ULITE_STATUS_RXVALID; 167 168 stat &= port->read_status_mask; 169 170 if (stat & ULITE_STATUS_PARITY) 171 flag = TTY_PARITY; 172 173 174 stat &= ~port->ignore_status_mask; 175 176 if (stat & ULITE_STATUS_RXVALID) 177 tty_insert_flip_char(tport, ch, flag); 178 179 if (stat & ULITE_STATUS_FRAME) 180 tty_insert_flip_char(tport, 0, TTY_FRAME); 181 182 if (stat & ULITE_STATUS_OVERRUN) 183 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 184 185 return 1; 186 } 187 188 static int ulite_transmit(struct uart_port *port, int stat) 189 { 190 struct circ_buf *xmit = &port->state->xmit; 191 192 if (stat & ULITE_STATUS_TXFULL) 193 return 0; 194 195 if (port->x_char) { 196 uart_out32(port->x_char, ULITE_TX, port); 197 port->x_char = 0; 198 port->icount.tx++; 199 return 1; 200 } 201 202 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) 203 return 0; 204 205 uart_out32(xmit->buf[xmit->tail], ULITE_TX, port); 206 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE-1); 207 port->icount.tx++; 208 209 /* wake up */ 210 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 211 uart_write_wakeup(port); 212 213 return 1; 214 } 215 216 static irqreturn_t ulite_isr(int irq, void *dev_id) 217 { 218 struct uart_port *port = dev_id; 219 int stat, busy, n = 0; 220 unsigned long flags; 221 222 do { 223 spin_lock_irqsave(&port->lock, flags); 224 stat = uart_in32(ULITE_STATUS, port); 225 busy = ulite_receive(port, stat); 226 busy |= ulite_transmit(port, stat); 227 spin_unlock_irqrestore(&port->lock, flags); 228 n++; 229 } while (busy); 230 231 /* work done? */ 232 if (n > 1) { 233 tty_flip_buffer_push(&port->state->port); 234 return IRQ_HANDLED; 235 } else { 236 return IRQ_NONE; 237 } 238 } 239 240 static unsigned int ulite_tx_empty(struct uart_port *port) 241 { 242 unsigned long flags; 243 unsigned int ret; 244 245 spin_lock_irqsave(&port->lock, flags); 246 ret = uart_in32(ULITE_STATUS, port); 247 spin_unlock_irqrestore(&port->lock, flags); 248 249 return ret & ULITE_STATUS_TXEMPTY ? TIOCSER_TEMT : 0; 250 } 251 252 static unsigned int ulite_get_mctrl(struct uart_port *port) 253 { 254 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; 255 } 256 257 static void ulite_set_mctrl(struct uart_port *port, unsigned int mctrl) 258 { 259 /* N/A */ 260 } 261 262 static void ulite_stop_tx(struct uart_port *port) 263 { 264 /* N/A */ 265 } 266 267 static void ulite_start_tx(struct uart_port *port) 268 { 269 ulite_transmit(port, uart_in32(ULITE_STATUS, port)); 270 } 271 272 static void ulite_stop_rx(struct uart_port *port) 273 { 274 /* don't forward any more data (like !CREAD) */ 275 port->ignore_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY 276 | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN; 277 } 278 279 static void ulite_break_ctl(struct uart_port *port, int ctl) 280 { 281 /* N/A */ 282 } 283 284 static int ulite_startup(struct uart_port *port) 285 { 286 struct uartlite_data *pdata = port->private_data; 287 int ret; 288 289 ret = clk_enable(pdata->clk); 290 if (ret) { 291 dev_err(port->dev, "Failed to enable clock\n"); 292 return ret; 293 } 294 295 ret = request_irq(port->irq, ulite_isr, IRQF_SHARED | IRQF_TRIGGER_RISING, 296 "uartlite", port); 297 if (ret) 298 return ret; 299 300 uart_out32(ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX, 301 ULITE_CONTROL, port); 302 uart_out32(ULITE_CONTROL_IE, ULITE_CONTROL, port); 303 304 return 0; 305 } 306 307 static void ulite_shutdown(struct uart_port *port) 308 { 309 struct uartlite_data *pdata = port->private_data; 310 311 uart_out32(0, ULITE_CONTROL, port); 312 uart_in32(ULITE_CONTROL, port); /* dummy */ 313 free_irq(port->irq, port); 314 clk_disable(pdata->clk); 315 } 316 317 static void ulite_set_termios(struct uart_port *port, 318 struct ktermios *termios, 319 const struct ktermios *old) 320 { 321 unsigned long flags; 322 struct uartlite_data *pdata = port->private_data; 323 324 /* Set termios to what the hardware supports */ 325 termios->c_iflag &= ~BRKINT; 326 termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CSIZE); 327 termios->c_cflag |= pdata->cflags & (PARENB | PARODD | CSIZE); 328 tty_termios_encode_baud_rate(termios, pdata->baud, pdata->baud); 329 330 spin_lock_irqsave(&port->lock, flags); 331 332 port->read_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN 333 | ULITE_STATUS_TXFULL; 334 335 if (termios->c_iflag & INPCK) 336 port->read_status_mask |= 337 ULITE_STATUS_PARITY | ULITE_STATUS_FRAME; 338 339 port->ignore_status_mask = 0; 340 if (termios->c_iflag & IGNPAR) 341 port->ignore_status_mask |= ULITE_STATUS_PARITY 342 | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN; 343 344 /* ignore all characters if CREAD is not set */ 345 if ((termios->c_cflag & CREAD) == 0) 346 port->ignore_status_mask |= 347 ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY 348 | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN; 349 350 /* update timeout */ 351 uart_update_timeout(port, termios->c_cflag, pdata->baud); 352 353 spin_unlock_irqrestore(&port->lock, flags); 354 } 355 356 static const char *ulite_type(struct uart_port *port) 357 { 358 return port->type == PORT_UARTLITE ? "uartlite" : NULL; 359 } 360 361 static void ulite_release_port(struct uart_port *port) 362 { 363 release_mem_region(port->mapbase, ULITE_REGION); 364 iounmap(port->membase); 365 port->membase = NULL; 366 } 367 368 static int ulite_request_port(struct uart_port *port) 369 { 370 struct uartlite_data *pdata = port->private_data; 371 int ret; 372 373 pr_debug("ulite console: port=%p; port->mapbase=%llx\n", 374 port, (unsigned long long) port->mapbase); 375 376 if (!request_mem_region(port->mapbase, ULITE_REGION, "uartlite")) { 377 dev_err(port->dev, "Memory region busy\n"); 378 return -EBUSY; 379 } 380 381 port->membase = ioremap(port->mapbase, ULITE_REGION); 382 if (!port->membase) { 383 dev_err(port->dev, "Unable to map registers\n"); 384 release_mem_region(port->mapbase, ULITE_REGION); 385 return -EBUSY; 386 } 387 388 pdata->reg_ops = &uartlite_be; 389 ret = uart_in32(ULITE_CONTROL, port); 390 uart_out32(ULITE_CONTROL_RST_TX, ULITE_CONTROL, port); 391 ret = uart_in32(ULITE_STATUS, port); 392 /* Endianess detection */ 393 if ((ret & ULITE_STATUS_TXEMPTY) != ULITE_STATUS_TXEMPTY) 394 pdata->reg_ops = &uartlite_le; 395 396 return 0; 397 } 398 399 static void ulite_config_port(struct uart_port *port, int flags) 400 { 401 if (!ulite_request_port(port)) 402 port->type = PORT_UARTLITE; 403 } 404 405 static int ulite_verify_port(struct uart_port *port, struct serial_struct *ser) 406 { 407 /* we don't want the core code to modify any port params */ 408 return -EINVAL; 409 } 410 411 static void ulite_pm(struct uart_port *port, unsigned int state, 412 unsigned int oldstate) 413 { 414 int ret; 415 416 if (!state) { 417 ret = pm_runtime_get_sync(port->dev); 418 if (ret < 0) 419 dev_err(port->dev, "Failed to enable clocks\n"); 420 } else { 421 pm_runtime_mark_last_busy(port->dev); 422 pm_runtime_put_autosuspend(port->dev); 423 } 424 } 425 426 #ifdef CONFIG_CONSOLE_POLL 427 static int ulite_get_poll_char(struct uart_port *port) 428 { 429 if (!(uart_in32(ULITE_STATUS, port) & ULITE_STATUS_RXVALID)) 430 return NO_POLL_CHAR; 431 432 return uart_in32(ULITE_RX, port); 433 } 434 435 static void ulite_put_poll_char(struct uart_port *port, unsigned char ch) 436 { 437 while (uart_in32(ULITE_STATUS, port) & ULITE_STATUS_TXFULL) 438 cpu_relax(); 439 440 /* write char to device */ 441 uart_out32(ch, ULITE_TX, port); 442 } 443 #endif 444 445 static const struct uart_ops ulite_ops = { 446 .tx_empty = ulite_tx_empty, 447 .set_mctrl = ulite_set_mctrl, 448 .get_mctrl = ulite_get_mctrl, 449 .stop_tx = ulite_stop_tx, 450 .start_tx = ulite_start_tx, 451 .stop_rx = ulite_stop_rx, 452 .break_ctl = ulite_break_ctl, 453 .startup = ulite_startup, 454 .shutdown = ulite_shutdown, 455 .set_termios = ulite_set_termios, 456 .type = ulite_type, 457 .release_port = ulite_release_port, 458 .request_port = ulite_request_port, 459 .config_port = ulite_config_port, 460 .verify_port = ulite_verify_port, 461 .pm = ulite_pm, 462 #ifdef CONFIG_CONSOLE_POLL 463 .poll_get_char = ulite_get_poll_char, 464 .poll_put_char = ulite_put_poll_char, 465 #endif 466 }; 467 468 /* --------------------------------------------------------------------- 469 * Console driver operations 470 */ 471 472 #ifdef CONFIG_SERIAL_UARTLITE_CONSOLE 473 static void ulite_console_wait_tx(struct uart_port *port) 474 { 475 u8 val; 476 477 /* 478 * Spin waiting for TX fifo to have space available. 479 * When using the Microblaze Debug Module this can take up to 1s 480 */ 481 if (read_poll_timeout_atomic(uart_in32, val, !(val & ULITE_STATUS_TXFULL), 482 0, 1000000, false, ULITE_STATUS, port)) 483 dev_warn(port->dev, 484 "timeout waiting for TX buffer empty\n"); 485 } 486 487 static void ulite_console_putchar(struct uart_port *port, unsigned char ch) 488 { 489 ulite_console_wait_tx(port); 490 uart_out32(ch, ULITE_TX, port); 491 } 492 493 static void ulite_console_write(struct console *co, const char *s, 494 unsigned int count) 495 { 496 struct uart_port *port = console_port; 497 unsigned long flags; 498 unsigned int ier; 499 int locked = 1; 500 501 if (oops_in_progress) { 502 locked = spin_trylock_irqsave(&port->lock, flags); 503 } else 504 spin_lock_irqsave(&port->lock, flags); 505 506 /* save and disable interrupt */ 507 ier = uart_in32(ULITE_STATUS, port) & ULITE_STATUS_IE; 508 uart_out32(0, ULITE_CONTROL, port); 509 510 uart_console_write(port, s, count, ulite_console_putchar); 511 512 ulite_console_wait_tx(port); 513 514 /* restore interrupt state */ 515 if (ier) 516 uart_out32(ULITE_CONTROL_IE, ULITE_CONTROL, port); 517 518 if (locked) 519 spin_unlock_irqrestore(&port->lock, flags); 520 } 521 522 static int ulite_console_setup(struct console *co, char *options) 523 { 524 struct uart_port *port = NULL; 525 int baud = 9600; 526 int bits = 8; 527 int parity = 'n'; 528 int flow = 'n'; 529 530 if (co->index >= 0 && co->index < ULITE_NR_UARTS) 531 port = ulite_ports + co->index; 532 533 /* Has the device been initialized yet? */ 534 if (!port || !port->mapbase) { 535 pr_debug("console on ttyUL%i not present\n", co->index); 536 return -ENODEV; 537 } 538 539 console_port = port; 540 541 /* not initialized yet? */ 542 if (!port->membase) { 543 if (ulite_request_port(port)) 544 return -ENODEV; 545 } 546 547 if (options) 548 uart_parse_options(options, &baud, &parity, &bits, &flow); 549 550 return uart_set_options(port, co, baud, parity, bits, flow); 551 } 552 553 static struct console ulite_console = { 554 .name = ULITE_NAME, 555 .write = ulite_console_write, 556 .device = uart_console_device, 557 .setup = ulite_console_setup, 558 .flags = CON_PRINTBUFFER, 559 .index = -1, /* Specified on the cmdline (e.g. console=ttyUL0 ) */ 560 .data = &ulite_uart_driver, 561 }; 562 563 static void early_uartlite_putc(struct uart_port *port, unsigned char c) 564 { 565 /* 566 * Limit how many times we'll spin waiting for TX FIFO status. 567 * This will prevent lockups if the base address is incorrectly 568 * set, or any other issue on the UARTLITE. 569 * This limit is pretty arbitrary, unless we are at about 10 baud 570 * we'll never timeout on a working UART. 571 */ 572 unsigned retries = 1000000; 573 574 while (--retries && 575 (readl(port->membase + ULITE_STATUS) & ULITE_STATUS_TXFULL)) 576 ; 577 578 /* Only attempt the iowrite if we didn't timeout */ 579 if (retries) 580 writel(c & 0xff, port->membase + ULITE_TX); 581 } 582 583 static void early_uartlite_write(struct console *console, 584 const char *s, unsigned n) 585 { 586 struct earlycon_device *device = console->data; 587 uart_console_write(&device->port, s, n, early_uartlite_putc); 588 } 589 590 static int __init early_uartlite_setup(struct earlycon_device *device, 591 const char *options) 592 { 593 if (!device->port.membase) 594 return -ENODEV; 595 596 device->con->write = early_uartlite_write; 597 return 0; 598 } 599 EARLYCON_DECLARE(uartlite, early_uartlite_setup); 600 OF_EARLYCON_DECLARE(uartlite_b, "xlnx,opb-uartlite-1.00.b", early_uartlite_setup); 601 OF_EARLYCON_DECLARE(uartlite_a, "xlnx,xps-uartlite-1.00.a", early_uartlite_setup); 602 603 #endif /* CONFIG_SERIAL_UARTLITE_CONSOLE */ 604 605 static struct uart_driver ulite_uart_driver = { 606 .owner = THIS_MODULE, 607 .driver_name = "uartlite", 608 .dev_name = ULITE_NAME, 609 .major = ULITE_MAJOR, 610 .minor = ULITE_MINOR, 611 .nr = ULITE_NR_UARTS, 612 #ifdef CONFIG_SERIAL_UARTLITE_CONSOLE 613 .cons = &ulite_console, 614 #endif 615 }; 616 617 /* --------------------------------------------------------------------- 618 * Port assignment functions (mapping devices to uart_port structures) 619 */ 620 621 /** ulite_assign: register a uartlite device with the driver 622 * 623 * @dev: pointer to device structure 624 * @id: requested id number. Pass -1 for automatic port assignment 625 * @base: base address of uartlite registers 626 * @irq: irq number for uartlite 627 * @pdata: private data for uartlite 628 * 629 * Returns: 0 on success, <0 otherwise 630 */ 631 static int ulite_assign(struct device *dev, int id, phys_addr_t base, int irq, 632 struct uartlite_data *pdata) 633 { 634 struct uart_port *port; 635 int rc; 636 637 /* if id = -1; then scan for a free id and use that */ 638 if (id < 0) { 639 for (id = 0; id < ULITE_NR_UARTS; id++) 640 if (ulite_ports[id].mapbase == 0) 641 break; 642 } 643 if (id < 0 || id >= ULITE_NR_UARTS) { 644 dev_err(dev, "%s%i too large\n", ULITE_NAME, id); 645 return -EINVAL; 646 } 647 648 if ((ulite_ports[id].mapbase) && (ulite_ports[id].mapbase != base)) { 649 dev_err(dev, "cannot assign to %s%i; it is already in use\n", 650 ULITE_NAME, id); 651 return -EBUSY; 652 } 653 654 port = &ulite_ports[id]; 655 656 spin_lock_init(&port->lock); 657 port->fifosize = 16; 658 port->regshift = 2; 659 port->iotype = UPIO_MEM; 660 port->iobase = 1; /* mark port in use */ 661 port->mapbase = base; 662 port->membase = NULL; 663 port->ops = &ulite_ops; 664 port->irq = irq; 665 port->flags = UPF_BOOT_AUTOCONF; 666 port->dev = dev; 667 port->type = PORT_UNKNOWN; 668 port->line = id; 669 port->private_data = pdata; 670 671 dev_set_drvdata(dev, port); 672 673 /* Register the port */ 674 rc = uart_add_one_port(&ulite_uart_driver, port); 675 if (rc) { 676 dev_err(dev, "uart_add_one_port() failed; err=%i\n", rc); 677 port->mapbase = 0; 678 dev_set_drvdata(dev, NULL); 679 return rc; 680 } 681 682 return 0; 683 } 684 685 /** ulite_release: register a uartlite device with the driver 686 * 687 * @dev: pointer to device structure 688 */ 689 static int ulite_release(struct device *dev) 690 { 691 struct uart_port *port = dev_get_drvdata(dev); 692 int rc = 0; 693 694 if (port) { 695 rc = uart_remove_one_port(&ulite_uart_driver, port); 696 dev_set_drvdata(dev, NULL); 697 port->mapbase = 0; 698 } 699 700 return rc; 701 } 702 703 /** 704 * ulite_suspend - Stop the device. 705 * 706 * @dev: handle to the device structure. 707 * Return: 0 always. 708 */ 709 static int __maybe_unused ulite_suspend(struct device *dev) 710 { 711 struct uart_port *port = dev_get_drvdata(dev); 712 713 if (port) 714 uart_suspend_port(&ulite_uart_driver, port); 715 716 return 0; 717 } 718 719 /** 720 * ulite_resume - Resume the device. 721 * 722 * @dev: handle to the device structure. 723 * Return: 0 on success, errno otherwise. 724 */ 725 static int __maybe_unused ulite_resume(struct device *dev) 726 { 727 struct uart_port *port = dev_get_drvdata(dev); 728 729 if (port) 730 uart_resume_port(&ulite_uart_driver, port); 731 732 return 0; 733 } 734 735 static int __maybe_unused ulite_runtime_suspend(struct device *dev) 736 { 737 struct uart_port *port = dev_get_drvdata(dev); 738 struct uartlite_data *pdata = port->private_data; 739 740 clk_disable(pdata->clk); 741 return 0; 742 }; 743 744 static int __maybe_unused ulite_runtime_resume(struct device *dev) 745 { 746 struct uart_port *port = dev_get_drvdata(dev); 747 struct uartlite_data *pdata = port->private_data; 748 int ret; 749 750 ret = clk_enable(pdata->clk); 751 if (ret) { 752 dev_err(dev, "Cannot enable clock.\n"); 753 return ret; 754 } 755 return 0; 756 } 757 758 /* --------------------------------------------------------------------- 759 * Platform bus binding 760 */ 761 762 static const struct dev_pm_ops ulite_pm_ops = { 763 SET_SYSTEM_SLEEP_PM_OPS(ulite_suspend, ulite_resume) 764 SET_RUNTIME_PM_OPS(ulite_runtime_suspend, 765 ulite_runtime_resume, NULL) 766 }; 767 768 #if defined(CONFIG_OF) 769 /* Match table for of_platform binding */ 770 static const struct of_device_id ulite_of_match[] = { 771 { .compatible = "xlnx,opb-uartlite-1.00.b", }, 772 { .compatible = "xlnx,xps-uartlite-1.00.a", }, 773 {} 774 }; 775 MODULE_DEVICE_TABLE(of, ulite_of_match); 776 #endif /* CONFIG_OF */ 777 778 static int ulite_probe(struct platform_device *pdev) 779 { 780 struct resource *res; 781 struct uartlite_data *pdata; 782 int irq, ret; 783 int id = pdev->id; 784 785 pdata = devm_kzalloc(&pdev->dev, sizeof(struct uartlite_data), 786 GFP_KERNEL); 787 if (!pdata) 788 return -ENOMEM; 789 790 if (IS_ENABLED(CONFIG_OF)) { 791 const char *prop; 792 struct device_node *np = pdev->dev.of_node; 793 u32 val = 0; 794 795 prop = "port-number"; 796 ret = of_property_read_u32(np, prop, &id); 797 if (ret && ret != -EINVAL) 798 of_err: 799 return dev_err_probe(&pdev->dev, ret, 800 "could not read %s\n", prop); 801 802 prop = "current-speed"; 803 ret = of_property_read_u32(np, prop, &pdata->baud); 804 if (ret) 805 goto of_err; 806 807 prop = "xlnx,use-parity"; 808 ret = of_property_read_u32(np, prop, &val); 809 if (ret && ret != -EINVAL) 810 goto of_err; 811 812 if (val) { 813 prop = "xlnx,odd-parity"; 814 ret = of_property_read_u32(np, prop, &val); 815 if (ret) 816 goto of_err; 817 818 if (val) 819 pdata->cflags |= PARODD; 820 pdata->cflags |= PARENB; 821 } 822 823 val = 8; 824 prop = "xlnx,data-bits"; 825 ret = of_property_read_u32(np, prop, &val); 826 if (ret && ret != -EINVAL) 827 goto of_err; 828 829 switch (val) { 830 case 5: 831 pdata->cflags |= CS5; 832 break; 833 case 6: 834 pdata->cflags |= CS6; 835 break; 836 case 7: 837 pdata->cflags |= CS7; 838 break; 839 case 8: 840 pdata->cflags |= CS8; 841 break; 842 default: 843 return dev_err_probe(&pdev->dev, -EINVAL, 844 "bad data bits %d\n", val); 845 } 846 } else { 847 pdata->baud = 9600; 848 pdata->cflags = CS8; 849 } 850 851 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 852 if (!res) 853 return -ENODEV; 854 855 irq = platform_get_irq(pdev, 0); 856 if (irq < 0) 857 return irq; 858 859 pdata->clk = devm_clk_get(&pdev->dev, "s_axi_aclk"); 860 if (IS_ERR(pdata->clk)) { 861 if (PTR_ERR(pdata->clk) != -ENOENT) 862 return PTR_ERR(pdata->clk); 863 864 /* 865 * Clock framework support is optional, continue on 866 * anyways if we don't find a matching clock. 867 */ 868 pdata->clk = NULL; 869 } 870 871 ret = clk_prepare_enable(pdata->clk); 872 if (ret) { 873 dev_err(&pdev->dev, "Failed to prepare clock\n"); 874 return ret; 875 } 876 877 pm_runtime_use_autosuspend(&pdev->dev); 878 pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT); 879 pm_runtime_set_active(&pdev->dev); 880 pm_runtime_enable(&pdev->dev); 881 882 if (!ulite_uart_driver.state) { 883 dev_dbg(&pdev->dev, "uartlite: calling uart_register_driver()\n"); 884 ret = uart_register_driver(&ulite_uart_driver); 885 if (ret < 0) { 886 dev_err(&pdev->dev, "Failed to register driver\n"); 887 clk_disable_unprepare(pdata->clk); 888 return ret; 889 } 890 } 891 892 ret = ulite_assign(&pdev->dev, id, res->start, irq, pdata); 893 894 pm_runtime_mark_last_busy(&pdev->dev); 895 pm_runtime_put_autosuspend(&pdev->dev); 896 897 return ret; 898 } 899 900 static int ulite_remove(struct platform_device *pdev) 901 { 902 struct uart_port *port = dev_get_drvdata(&pdev->dev); 903 struct uartlite_data *pdata = port->private_data; 904 int rc; 905 906 clk_disable_unprepare(pdata->clk); 907 rc = ulite_release(&pdev->dev); 908 pm_runtime_disable(&pdev->dev); 909 pm_runtime_set_suspended(&pdev->dev); 910 pm_runtime_dont_use_autosuspend(&pdev->dev); 911 return rc; 912 } 913 914 /* work with hotplug and coldplug */ 915 MODULE_ALIAS("platform:uartlite"); 916 917 static struct platform_driver ulite_platform_driver = { 918 .probe = ulite_probe, 919 .remove = ulite_remove, 920 .driver = { 921 .name = "uartlite", 922 .of_match_table = of_match_ptr(ulite_of_match), 923 .pm = &ulite_pm_ops, 924 }, 925 }; 926 927 /* --------------------------------------------------------------------- 928 * Module setup/teardown 929 */ 930 931 static int __init ulite_init(void) 932 { 933 934 pr_debug("uartlite: calling platform_driver_register()\n"); 935 return platform_driver_register(&ulite_platform_driver); 936 } 937 938 static void __exit ulite_exit(void) 939 { 940 platform_driver_unregister(&ulite_platform_driver); 941 if (ulite_uart_driver.state) 942 uart_unregister_driver(&ulite_uart_driver); 943 } 944 945 module_init(ulite_init); 946 module_exit(ulite_exit); 947 948 MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>"); 949 MODULE_DESCRIPTION("Xilinx uartlite serial driver"); 950 MODULE_LICENSE("GPL"); 951