1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * uartlite.c: Serial driver for Xilinx uartlite serial controller 4 * 5 * Copyright (C) 2006 Peter Korsgaard <jacmet@sunsite.dk> 6 * Copyright (C) 2007 Secret Lab Technologies Ltd. 7 */ 8 9 #include <linux/platform_device.h> 10 #include <linux/module.h> 11 #include <linux/bitfield.h> 12 #include <linux/console.h> 13 #include <linux/serial.h> 14 #include <linux/serial_core.h> 15 #include <linux/tty.h> 16 #include <linux/tty_flip.h> 17 #include <linux/delay.h> 18 #include <linux/interrupt.h> 19 #include <linux/init.h> 20 #include <linux/io.h> 21 #include <linux/iopoll.h> 22 #include <linux/of.h> 23 #include <linux/of_address.h> 24 #include <linux/of_device.h> 25 #include <linux/of_platform.h> 26 #include <linux/clk.h> 27 #include <linux/pm_runtime.h> 28 29 #define ULITE_NAME "ttyUL" 30 #define ULITE_MAJOR 204 31 #define ULITE_MINOR 187 32 #define ULITE_NR_UARTS CONFIG_SERIAL_UARTLITE_NR_UARTS 33 34 /* --------------------------------------------------------------------- 35 * Register definitions 36 * 37 * For register details see datasheet: 38 * https://www.xilinx.com/support/documentation/ip_documentation/opb_uartlite.pdf 39 */ 40 41 #define ULITE_RX 0x00 42 #define ULITE_TX 0x04 43 #define ULITE_STATUS 0x08 44 #define ULITE_CONTROL 0x0c 45 46 #define ULITE_REGION 16 47 48 #define ULITE_STATUS_RXVALID 0x01 49 #define ULITE_STATUS_RXFULL 0x02 50 #define ULITE_STATUS_TXEMPTY 0x04 51 #define ULITE_STATUS_TXFULL 0x08 52 #define ULITE_STATUS_IE 0x10 53 #define ULITE_STATUS_OVERRUN 0x20 54 #define ULITE_STATUS_FRAME 0x40 55 #define ULITE_STATUS_PARITY 0x80 56 57 #define ULITE_CONTROL_RST_TX 0x01 58 #define ULITE_CONTROL_RST_RX 0x02 59 #define ULITE_CONTROL_IE 0x10 60 #define UART_AUTOSUSPEND_TIMEOUT 3000 /* ms */ 61 62 /* Static pointer to console port */ 63 #ifdef CONFIG_SERIAL_UARTLITE_CONSOLE 64 static struct uart_port *console_port; 65 #endif 66 67 /** 68 * struct uartlite_data: Driver private data 69 * reg_ops: Functions to read/write registers 70 * clk: Our parent clock, if present 71 * baud: The baud rate configured when this device was synthesized 72 * cflags: The cflags for parity and data bits 73 */ 74 struct uartlite_data { 75 const struct uartlite_reg_ops *reg_ops; 76 struct clk *clk; 77 unsigned int baud; 78 tcflag_t cflags; 79 }; 80 81 struct uartlite_reg_ops { 82 u32 (*in)(void __iomem *addr); 83 void (*out)(u32 val, void __iomem *addr); 84 }; 85 86 static u32 uartlite_inbe32(void __iomem *addr) 87 { 88 return ioread32be(addr); 89 } 90 91 static void uartlite_outbe32(u32 val, void __iomem *addr) 92 { 93 iowrite32be(val, addr); 94 } 95 96 static const struct uartlite_reg_ops uartlite_be = { 97 .in = uartlite_inbe32, 98 .out = uartlite_outbe32, 99 }; 100 101 static u32 uartlite_inle32(void __iomem *addr) 102 { 103 return ioread32(addr); 104 } 105 106 static void uartlite_outle32(u32 val, void __iomem *addr) 107 { 108 iowrite32(val, addr); 109 } 110 111 static const struct uartlite_reg_ops uartlite_le = { 112 .in = uartlite_inle32, 113 .out = uartlite_outle32, 114 }; 115 116 static inline u32 uart_in32(u32 offset, struct uart_port *port) 117 { 118 struct uartlite_data *pdata = port->private_data; 119 120 return pdata->reg_ops->in(port->membase + offset); 121 } 122 123 static inline void uart_out32(u32 val, u32 offset, struct uart_port *port) 124 { 125 struct uartlite_data *pdata = port->private_data; 126 127 pdata->reg_ops->out(val, port->membase + offset); 128 } 129 130 static struct uart_port ulite_ports[ULITE_NR_UARTS]; 131 132 static struct uart_driver ulite_uart_driver; 133 134 /* --------------------------------------------------------------------- 135 * Core UART driver operations 136 */ 137 138 static int ulite_receive(struct uart_port *port, int stat) 139 { 140 struct tty_port *tport = &port->state->port; 141 unsigned char ch = 0; 142 char flag = TTY_NORMAL; 143 144 if ((stat & (ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN 145 | ULITE_STATUS_FRAME)) == 0) 146 return 0; 147 148 /* stats */ 149 if (stat & ULITE_STATUS_RXVALID) { 150 port->icount.rx++; 151 ch = uart_in32(ULITE_RX, port); 152 153 if (stat & ULITE_STATUS_PARITY) 154 port->icount.parity++; 155 } 156 157 if (stat & ULITE_STATUS_OVERRUN) 158 port->icount.overrun++; 159 160 if (stat & ULITE_STATUS_FRAME) 161 port->icount.frame++; 162 163 164 /* drop byte with parity error if IGNPAR specificed */ 165 if (stat & port->ignore_status_mask & ULITE_STATUS_PARITY) 166 stat &= ~ULITE_STATUS_RXVALID; 167 168 stat &= port->read_status_mask; 169 170 if (stat & ULITE_STATUS_PARITY) 171 flag = TTY_PARITY; 172 173 174 stat &= ~port->ignore_status_mask; 175 176 if (stat & ULITE_STATUS_RXVALID) 177 tty_insert_flip_char(tport, ch, flag); 178 179 if (stat & ULITE_STATUS_FRAME) 180 tty_insert_flip_char(tport, 0, TTY_FRAME); 181 182 if (stat & ULITE_STATUS_OVERRUN) 183 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 184 185 return 1; 186 } 187 188 static int ulite_transmit(struct uart_port *port, int stat) 189 { 190 struct circ_buf *xmit = &port->state->xmit; 191 192 if (stat & ULITE_STATUS_TXFULL) 193 return 0; 194 195 if (port->x_char) { 196 uart_out32(port->x_char, ULITE_TX, port); 197 port->x_char = 0; 198 port->icount.tx++; 199 return 1; 200 } 201 202 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) 203 return 0; 204 205 uart_out32(xmit->buf[xmit->tail], ULITE_TX, port); 206 uart_xmit_advance(port, 1); 207 208 /* wake up */ 209 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 210 uart_write_wakeup(port); 211 212 return 1; 213 } 214 215 static irqreturn_t ulite_isr(int irq, void *dev_id) 216 { 217 struct uart_port *port = dev_id; 218 int stat, busy, n = 0; 219 unsigned long flags; 220 221 do { 222 spin_lock_irqsave(&port->lock, flags); 223 stat = uart_in32(ULITE_STATUS, port); 224 busy = ulite_receive(port, stat); 225 busy |= ulite_transmit(port, stat); 226 spin_unlock_irqrestore(&port->lock, flags); 227 n++; 228 } while (busy); 229 230 /* work done? */ 231 if (n > 1) { 232 tty_flip_buffer_push(&port->state->port); 233 return IRQ_HANDLED; 234 } else { 235 return IRQ_NONE; 236 } 237 } 238 239 static unsigned int ulite_tx_empty(struct uart_port *port) 240 { 241 unsigned long flags; 242 unsigned int ret; 243 244 spin_lock_irqsave(&port->lock, flags); 245 ret = uart_in32(ULITE_STATUS, port); 246 spin_unlock_irqrestore(&port->lock, flags); 247 248 return ret & ULITE_STATUS_TXEMPTY ? TIOCSER_TEMT : 0; 249 } 250 251 static unsigned int ulite_get_mctrl(struct uart_port *port) 252 { 253 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; 254 } 255 256 static void ulite_set_mctrl(struct uart_port *port, unsigned int mctrl) 257 { 258 /* N/A */ 259 } 260 261 static void ulite_stop_tx(struct uart_port *port) 262 { 263 /* N/A */ 264 } 265 266 static void ulite_start_tx(struct uart_port *port) 267 { 268 ulite_transmit(port, uart_in32(ULITE_STATUS, port)); 269 } 270 271 static void ulite_stop_rx(struct uart_port *port) 272 { 273 /* don't forward any more data (like !CREAD) */ 274 port->ignore_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY 275 | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN; 276 } 277 278 static void ulite_break_ctl(struct uart_port *port, int ctl) 279 { 280 /* N/A */ 281 } 282 283 static int ulite_startup(struct uart_port *port) 284 { 285 struct uartlite_data *pdata = port->private_data; 286 int ret; 287 288 ret = clk_enable(pdata->clk); 289 if (ret) { 290 dev_err(port->dev, "Failed to enable clock\n"); 291 return ret; 292 } 293 294 ret = request_irq(port->irq, ulite_isr, IRQF_SHARED | IRQF_TRIGGER_RISING, 295 "uartlite", port); 296 if (ret) 297 return ret; 298 299 uart_out32(ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX, 300 ULITE_CONTROL, port); 301 uart_out32(ULITE_CONTROL_IE, ULITE_CONTROL, port); 302 303 return 0; 304 } 305 306 static void ulite_shutdown(struct uart_port *port) 307 { 308 struct uartlite_data *pdata = port->private_data; 309 310 uart_out32(0, ULITE_CONTROL, port); 311 uart_in32(ULITE_CONTROL, port); /* dummy */ 312 free_irq(port->irq, port); 313 clk_disable(pdata->clk); 314 } 315 316 static void ulite_set_termios(struct uart_port *port, 317 struct ktermios *termios, 318 const struct ktermios *old) 319 { 320 unsigned long flags; 321 struct uartlite_data *pdata = port->private_data; 322 323 /* Set termios to what the hardware supports */ 324 termios->c_iflag &= ~BRKINT; 325 termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CSIZE); 326 termios->c_cflag |= pdata->cflags & (PARENB | PARODD | CSIZE); 327 tty_termios_encode_baud_rate(termios, pdata->baud, pdata->baud); 328 329 spin_lock_irqsave(&port->lock, flags); 330 331 port->read_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN 332 | ULITE_STATUS_TXFULL; 333 334 if (termios->c_iflag & INPCK) 335 port->read_status_mask |= 336 ULITE_STATUS_PARITY | ULITE_STATUS_FRAME; 337 338 port->ignore_status_mask = 0; 339 if (termios->c_iflag & IGNPAR) 340 port->ignore_status_mask |= ULITE_STATUS_PARITY 341 | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN; 342 343 /* ignore all characters if CREAD is not set */ 344 if ((termios->c_cflag & CREAD) == 0) 345 port->ignore_status_mask |= 346 ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY 347 | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN; 348 349 /* update timeout */ 350 uart_update_timeout(port, termios->c_cflag, pdata->baud); 351 352 spin_unlock_irqrestore(&port->lock, flags); 353 } 354 355 static const char *ulite_type(struct uart_port *port) 356 { 357 return port->type == PORT_UARTLITE ? "uartlite" : NULL; 358 } 359 360 static void ulite_release_port(struct uart_port *port) 361 { 362 release_mem_region(port->mapbase, ULITE_REGION); 363 iounmap(port->membase); 364 port->membase = NULL; 365 } 366 367 static int ulite_request_port(struct uart_port *port) 368 { 369 struct uartlite_data *pdata = port->private_data; 370 int ret; 371 372 pr_debug("ulite console: port=%p; port->mapbase=%llx\n", 373 port, (unsigned long long) port->mapbase); 374 375 if (!request_mem_region(port->mapbase, ULITE_REGION, "uartlite")) { 376 dev_err(port->dev, "Memory region busy\n"); 377 return -EBUSY; 378 } 379 380 port->membase = ioremap(port->mapbase, ULITE_REGION); 381 if (!port->membase) { 382 dev_err(port->dev, "Unable to map registers\n"); 383 release_mem_region(port->mapbase, ULITE_REGION); 384 return -EBUSY; 385 } 386 387 pdata->reg_ops = &uartlite_be; 388 ret = uart_in32(ULITE_CONTROL, port); 389 uart_out32(ULITE_CONTROL_RST_TX, ULITE_CONTROL, port); 390 ret = uart_in32(ULITE_STATUS, port); 391 /* Endianess detection */ 392 if ((ret & ULITE_STATUS_TXEMPTY) != ULITE_STATUS_TXEMPTY) 393 pdata->reg_ops = &uartlite_le; 394 395 return 0; 396 } 397 398 static void ulite_config_port(struct uart_port *port, int flags) 399 { 400 if (!ulite_request_port(port)) 401 port->type = PORT_UARTLITE; 402 } 403 404 static int ulite_verify_port(struct uart_port *port, struct serial_struct *ser) 405 { 406 /* we don't want the core code to modify any port params */ 407 return -EINVAL; 408 } 409 410 static void ulite_pm(struct uart_port *port, unsigned int state, 411 unsigned int oldstate) 412 { 413 int ret; 414 415 if (!state) { 416 ret = pm_runtime_get_sync(port->dev); 417 if (ret < 0) 418 dev_err(port->dev, "Failed to enable clocks\n"); 419 } else { 420 pm_runtime_mark_last_busy(port->dev); 421 pm_runtime_put_autosuspend(port->dev); 422 } 423 } 424 425 #ifdef CONFIG_CONSOLE_POLL 426 static int ulite_get_poll_char(struct uart_port *port) 427 { 428 if (!(uart_in32(ULITE_STATUS, port) & ULITE_STATUS_RXVALID)) 429 return NO_POLL_CHAR; 430 431 return uart_in32(ULITE_RX, port); 432 } 433 434 static void ulite_put_poll_char(struct uart_port *port, unsigned char ch) 435 { 436 while (uart_in32(ULITE_STATUS, port) & ULITE_STATUS_TXFULL) 437 cpu_relax(); 438 439 /* write char to device */ 440 uart_out32(ch, ULITE_TX, port); 441 } 442 #endif 443 444 static const struct uart_ops ulite_ops = { 445 .tx_empty = ulite_tx_empty, 446 .set_mctrl = ulite_set_mctrl, 447 .get_mctrl = ulite_get_mctrl, 448 .stop_tx = ulite_stop_tx, 449 .start_tx = ulite_start_tx, 450 .stop_rx = ulite_stop_rx, 451 .break_ctl = ulite_break_ctl, 452 .startup = ulite_startup, 453 .shutdown = ulite_shutdown, 454 .set_termios = ulite_set_termios, 455 .type = ulite_type, 456 .release_port = ulite_release_port, 457 .request_port = ulite_request_port, 458 .config_port = ulite_config_port, 459 .verify_port = ulite_verify_port, 460 .pm = ulite_pm, 461 #ifdef CONFIG_CONSOLE_POLL 462 .poll_get_char = ulite_get_poll_char, 463 .poll_put_char = ulite_put_poll_char, 464 #endif 465 }; 466 467 /* --------------------------------------------------------------------- 468 * Console driver operations 469 */ 470 471 #ifdef CONFIG_SERIAL_UARTLITE_CONSOLE 472 static void ulite_console_wait_tx(struct uart_port *port) 473 { 474 u8 val; 475 476 /* 477 * Spin waiting for TX fifo to have space available. 478 * When using the Microblaze Debug Module this can take up to 1s 479 */ 480 if (read_poll_timeout_atomic(uart_in32, val, !(val & ULITE_STATUS_TXFULL), 481 0, 1000000, false, ULITE_STATUS, port)) 482 dev_warn(port->dev, 483 "timeout waiting for TX buffer empty\n"); 484 } 485 486 static void ulite_console_putchar(struct uart_port *port, unsigned char ch) 487 { 488 ulite_console_wait_tx(port); 489 uart_out32(ch, ULITE_TX, port); 490 } 491 492 static void ulite_console_write(struct console *co, const char *s, 493 unsigned int count) 494 { 495 struct uart_port *port = console_port; 496 unsigned long flags; 497 unsigned int ier; 498 int locked = 1; 499 500 if (oops_in_progress) { 501 locked = spin_trylock_irqsave(&port->lock, flags); 502 } else 503 spin_lock_irqsave(&port->lock, flags); 504 505 /* save and disable interrupt */ 506 ier = uart_in32(ULITE_STATUS, port) & ULITE_STATUS_IE; 507 uart_out32(0, ULITE_CONTROL, port); 508 509 uart_console_write(port, s, count, ulite_console_putchar); 510 511 ulite_console_wait_tx(port); 512 513 /* restore interrupt state */ 514 if (ier) 515 uart_out32(ULITE_CONTROL_IE, ULITE_CONTROL, port); 516 517 if (locked) 518 spin_unlock_irqrestore(&port->lock, flags); 519 } 520 521 static int ulite_console_setup(struct console *co, char *options) 522 { 523 struct uart_port *port = NULL; 524 int baud = 9600; 525 int bits = 8; 526 int parity = 'n'; 527 int flow = 'n'; 528 529 if (co->index >= 0 && co->index < ULITE_NR_UARTS) 530 port = ulite_ports + co->index; 531 532 /* Has the device been initialized yet? */ 533 if (!port || !port->mapbase) { 534 pr_debug("console on ttyUL%i not present\n", co->index); 535 return -ENODEV; 536 } 537 538 console_port = port; 539 540 /* not initialized yet? */ 541 if (!port->membase) { 542 if (ulite_request_port(port)) 543 return -ENODEV; 544 } 545 546 if (options) 547 uart_parse_options(options, &baud, &parity, &bits, &flow); 548 549 return uart_set_options(port, co, baud, parity, bits, flow); 550 } 551 552 static struct console ulite_console = { 553 .name = ULITE_NAME, 554 .write = ulite_console_write, 555 .device = uart_console_device, 556 .setup = ulite_console_setup, 557 .flags = CON_PRINTBUFFER, 558 .index = -1, /* Specified on the cmdline (e.g. console=ttyUL0 ) */ 559 .data = &ulite_uart_driver, 560 }; 561 562 static void early_uartlite_putc(struct uart_port *port, unsigned char c) 563 { 564 /* 565 * Limit how many times we'll spin waiting for TX FIFO status. 566 * This will prevent lockups if the base address is incorrectly 567 * set, or any other issue on the UARTLITE. 568 * This limit is pretty arbitrary, unless we are at about 10 baud 569 * we'll never timeout on a working UART. 570 */ 571 unsigned retries = 1000000; 572 573 while (--retries && 574 (readl(port->membase + ULITE_STATUS) & ULITE_STATUS_TXFULL)) 575 ; 576 577 /* Only attempt the iowrite if we didn't timeout */ 578 if (retries) 579 writel(c & 0xff, port->membase + ULITE_TX); 580 } 581 582 static void early_uartlite_write(struct console *console, 583 const char *s, unsigned n) 584 { 585 struct earlycon_device *device = console->data; 586 uart_console_write(&device->port, s, n, early_uartlite_putc); 587 } 588 589 static int __init early_uartlite_setup(struct earlycon_device *device, 590 const char *options) 591 { 592 if (!device->port.membase) 593 return -ENODEV; 594 595 device->con->write = early_uartlite_write; 596 return 0; 597 } 598 EARLYCON_DECLARE(uartlite, early_uartlite_setup); 599 OF_EARLYCON_DECLARE(uartlite_b, "xlnx,opb-uartlite-1.00.b", early_uartlite_setup); 600 OF_EARLYCON_DECLARE(uartlite_a, "xlnx,xps-uartlite-1.00.a", early_uartlite_setup); 601 602 #endif /* CONFIG_SERIAL_UARTLITE_CONSOLE */ 603 604 static struct uart_driver ulite_uart_driver = { 605 .owner = THIS_MODULE, 606 .driver_name = "uartlite", 607 .dev_name = ULITE_NAME, 608 .major = ULITE_MAJOR, 609 .minor = ULITE_MINOR, 610 .nr = ULITE_NR_UARTS, 611 #ifdef CONFIG_SERIAL_UARTLITE_CONSOLE 612 .cons = &ulite_console, 613 #endif 614 }; 615 616 /* --------------------------------------------------------------------- 617 * Port assignment functions (mapping devices to uart_port structures) 618 */ 619 620 /** ulite_assign: register a uartlite device with the driver 621 * 622 * @dev: pointer to device structure 623 * @id: requested id number. Pass -1 for automatic port assignment 624 * @base: base address of uartlite registers 625 * @irq: irq number for uartlite 626 * @pdata: private data for uartlite 627 * 628 * Returns: 0 on success, <0 otherwise 629 */ 630 static int ulite_assign(struct device *dev, int id, phys_addr_t base, int irq, 631 struct uartlite_data *pdata) 632 { 633 struct uart_port *port; 634 int rc; 635 636 /* if id = -1; then scan for a free id and use that */ 637 if (id < 0) { 638 for (id = 0; id < ULITE_NR_UARTS; id++) 639 if (ulite_ports[id].mapbase == 0) 640 break; 641 } 642 if (id < 0 || id >= ULITE_NR_UARTS) { 643 dev_err(dev, "%s%i too large\n", ULITE_NAME, id); 644 return -EINVAL; 645 } 646 647 if ((ulite_ports[id].mapbase) && (ulite_ports[id].mapbase != base)) { 648 dev_err(dev, "cannot assign to %s%i; it is already in use\n", 649 ULITE_NAME, id); 650 return -EBUSY; 651 } 652 653 port = &ulite_ports[id]; 654 655 spin_lock_init(&port->lock); 656 port->fifosize = 16; 657 port->regshift = 2; 658 port->iotype = UPIO_MEM; 659 port->iobase = 1; /* mark port in use */ 660 port->mapbase = base; 661 port->membase = NULL; 662 port->ops = &ulite_ops; 663 port->irq = irq; 664 port->flags = UPF_BOOT_AUTOCONF; 665 port->dev = dev; 666 port->type = PORT_UNKNOWN; 667 port->line = id; 668 port->private_data = pdata; 669 670 dev_set_drvdata(dev, port); 671 672 /* Register the port */ 673 rc = uart_add_one_port(&ulite_uart_driver, port); 674 if (rc) { 675 dev_err(dev, "uart_add_one_port() failed; err=%i\n", rc); 676 port->mapbase = 0; 677 dev_set_drvdata(dev, NULL); 678 return rc; 679 } 680 681 return 0; 682 } 683 684 /** ulite_release: register a uartlite device with the driver 685 * 686 * @dev: pointer to device structure 687 */ 688 static int ulite_release(struct device *dev) 689 { 690 struct uart_port *port = dev_get_drvdata(dev); 691 int rc = 0; 692 693 if (port) { 694 rc = uart_remove_one_port(&ulite_uart_driver, port); 695 dev_set_drvdata(dev, NULL); 696 port->mapbase = 0; 697 } 698 699 return rc; 700 } 701 702 /** 703 * ulite_suspend - Stop the device. 704 * 705 * @dev: handle to the device structure. 706 * Return: 0 always. 707 */ 708 static int __maybe_unused ulite_suspend(struct device *dev) 709 { 710 struct uart_port *port = dev_get_drvdata(dev); 711 712 if (port) 713 uart_suspend_port(&ulite_uart_driver, port); 714 715 return 0; 716 } 717 718 /** 719 * ulite_resume - Resume the device. 720 * 721 * @dev: handle to the device structure. 722 * Return: 0 on success, errno otherwise. 723 */ 724 static int __maybe_unused ulite_resume(struct device *dev) 725 { 726 struct uart_port *port = dev_get_drvdata(dev); 727 728 if (port) 729 uart_resume_port(&ulite_uart_driver, port); 730 731 return 0; 732 } 733 734 static int __maybe_unused ulite_runtime_suspend(struct device *dev) 735 { 736 struct uart_port *port = dev_get_drvdata(dev); 737 struct uartlite_data *pdata = port->private_data; 738 739 clk_disable(pdata->clk); 740 return 0; 741 }; 742 743 static int __maybe_unused ulite_runtime_resume(struct device *dev) 744 { 745 struct uart_port *port = dev_get_drvdata(dev); 746 struct uartlite_data *pdata = port->private_data; 747 int ret; 748 749 ret = clk_enable(pdata->clk); 750 if (ret) { 751 dev_err(dev, "Cannot enable clock.\n"); 752 return ret; 753 } 754 return 0; 755 } 756 757 /* --------------------------------------------------------------------- 758 * Platform bus binding 759 */ 760 761 static const struct dev_pm_ops ulite_pm_ops = { 762 SET_SYSTEM_SLEEP_PM_OPS(ulite_suspend, ulite_resume) 763 SET_RUNTIME_PM_OPS(ulite_runtime_suspend, 764 ulite_runtime_resume, NULL) 765 }; 766 767 #if defined(CONFIG_OF) 768 /* Match table for of_platform binding */ 769 static const struct of_device_id ulite_of_match[] = { 770 { .compatible = "xlnx,opb-uartlite-1.00.b", }, 771 { .compatible = "xlnx,xps-uartlite-1.00.a", }, 772 {} 773 }; 774 MODULE_DEVICE_TABLE(of, ulite_of_match); 775 #endif /* CONFIG_OF */ 776 777 static int ulite_probe(struct platform_device *pdev) 778 { 779 struct resource *res; 780 struct uartlite_data *pdata; 781 int irq, ret; 782 int id = pdev->id; 783 784 pdata = devm_kzalloc(&pdev->dev, sizeof(struct uartlite_data), 785 GFP_KERNEL); 786 if (!pdata) 787 return -ENOMEM; 788 789 if (IS_ENABLED(CONFIG_OF)) { 790 const char *prop; 791 struct device_node *np = pdev->dev.of_node; 792 u32 val = 0; 793 794 prop = "port-number"; 795 ret = of_property_read_u32(np, prop, &id); 796 if (ret && ret != -EINVAL) 797 of_err: 798 return dev_err_probe(&pdev->dev, ret, 799 "could not read %s\n", prop); 800 801 prop = "current-speed"; 802 ret = of_property_read_u32(np, prop, &pdata->baud); 803 if (ret) 804 goto of_err; 805 806 prop = "xlnx,use-parity"; 807 ret = of_property_read_u32(np, prop, &val); 808 if (ret && ret != -EINVAL) 809 goto of_err; 810 811 if (val) { 812 prop = "xlnx,odd-parity"; 813 ret = of_property_read_u32(np, prop, &val); 814 if (ret) 815 goto of_err; 816 817 if (val) 818 pdata->cflags |= PARODD; 819 pdata->cflags |= PARENB; 820 } 821 822 val = 8; 823 prop = "xlnx,data-bits"; 824 ret = of_property_read_u32(np, prop, &val); 825 if (ret && ret != -EINVAL) 826 goto of_err; 827 828 switch (val) { 829 case 5: 830 pdata->cflags |= CS5; 831 break; 832 case 6: 833 pdata->cflags |= CS6; 834 break; 835 case 7: 836 pdata->cflags |= CS7; 837 break; 838 case 8: 839 pdata->cflags |= CS8; 840 break; 841 default: 842 return dev_err_probe(&pdev->dev, -EINVAL, 843 "bad data bits %d\n", val); 844 } 845 } else { 846 pdata->baud = 9600; 847 pdata->cflags = CS8; 848 } 849 850 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 851 if (!res) 852 return -ENODEV; 853 854 irq = platform_get_irq(pdev, 0); 855 if (irq < 0) 856 return irq; 857 858 pdata->clk = devm_clk_get(&pdev->dev, "s_axi_aclk"); 859 if (IS_ERR(pdata->clk)) { 860 if (PTR_ERR(pdata->clk) != -ENOENT) 861 return PTR_ERR(pdata->clk); 862 863 /* 864 * Clock framework support is optional, continue on 865 * anyways if we don't find a matching clock. 866 */ 867 pdata->clk = NULL; 868 } 869 870 ret = clk_prepare_enable(pdata->clk); 871 if (ret) { 872 dev_err(&pdev->dev, "Failed to prepare clock\n"); 873 return ret; 874 } 875 876 pm_runtime_use_autosuspend(&pdev->dev); 877 pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT); 878 pm_runtime_set_active(&pdev->dev); 879 pm_runtime_enable(&pdev->dev); 880 881 if (!ulite_uart_driver.state) { 882 dev_dbg(&pdev->dev, "uartlite: calling uart_register_driver()\n"); 883 ret = uart_register_driver(&ulite_uart_driver); 884 if (ret < 0) { 885 dev_err(&pdev->dev, "Failed to register driver\n"); 886 clk_disable_unprepare(pdata->clk); 887 return ret; 888 } 889 } 890 891 ret = ulite_assign(&pdev->dev, id, res->start, irq, pdata); 892 893 pm_runtime_mark_last_busy(&pdev->dev); 894 pm_runtime_put_autosuspend(&pdev->dev); 895 896 return ret; 897 } 898 899 static int ulite_remove(struct platform_device *pdev) 900 { 901 struct uart_port *port = dev_get_drvdata(&pdev->dev); 902 struct uartlite_data *pdata = port->private_data; 903 int rc; 904 905 clk_disable_unprepare(pdata->clk); 906 rc = ulite_release(&pdev->dev); 907 pm_runtime_disable(&pdev->dev); 908 pm_runtime_set_suspended(&pdev->dev); 909 pm_runtime_dont_use_autosuspend(&pdev->dev); 910 return rc; 911 } 912 913 /* work with hotplug and coldplug */ 914 MODULE_ALIAS("platform:uartlite"); 915 916 static struct platform_driver ulite_platform_driver = { 917 .probe = ulite_probe, 918 .remove = ulite_remove, 919 .driver = { 920 .name = "uartlite", 921 .of_match_table = of_match_ptr(ulite_of_match), 922 .pm = &ulite_pm_ops, 923 }, 924 }; 925 926 /* --------------------------------------------------------------------- 927 * Module setup/teardown 928 */ 929 930 static int __init ulite_init(void) 931 { 932 933 pr_debug("uartlite: calling platform_driver_register()\n"); 934 return platform_driver_register(&ulite_platform_driver); 935 } 936 937 static void __exit ulite_exit(void) 938 { 939 platform_driver_unregister(&ulite_platform_driver); 940 if (ulite_uart_driver.state) 941 uart_unregister_driver(&ulite_uart_driver); 942 } 943 944 module_init(ulite_init); 945 module_exit(ulite_exit); 946 947 MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>"); 948 MODULE_DESCRIPTION("Xilinx uartlite serial driver"); 949 MODULE_LICENSE("GPL"); 950