1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * uartlite.c: Serial driver for Xilinx uartlite serial controller 4 * 5 * Copyright (C) 2006 Peter Korsgaard <jacmet@sunsite.dk> 6 * Copyright (C) 2007 Secret Lab Technologies Ltd. 7 */ 8 9 #include <linux/platform_device.h> 10 #include <linux/module.h> 11 #include <linux/console.h> 12 #include <linux/serial.h> 13 #include <linux/serial_core.h> 14 #include <linux/tty.h> 15 #include <linux/tty_flip.h> 16 #include <linux/delay.h> 17 #include <linux/interrupt.h> 18 #include <linux/init.h> 19 #include <linux/io.h> 20 #include <linux/iopoll.h> 21 #include <linux/of.h> 22 #include <linux/of_address.h> 23 #include <linux/of_device.h> 24 #include <linux/of_platform.h> 25 #include <linux/clk.h> 26 #include <linux/pm_runtime.h> 27 28 #define ULITE_NAME "ttyUL" 29 #define ULITE_MAJOR 204 30 #define ULITE_MINOR 187 31 #define ULITE_NR_UARTS CONFIG_SERIAL_UARTLITE_NR_UARTS 32 33 /* --------------------------------------------------------------------- 34 * Register definitions 35 * 36 * For register details see datasheet: 37 * https://www.xilinx.com/support/documentation/ip_documentation/opb_uartlite.pdf 38 */ 39 40 #define ULITE_RX 0x00 41 #define ULITE_TX 0x04 42 #define ULITE_STATUS 0x08 43 #define ULITE_CONTROL 0x0c 44 45 #define ULITE_REGION 16 46 47 #define ULITE_STATUS_RXVALID 0x01 48 #define ULITE_STATUS_RXFULL 0x02 49 #define ULITE_STATUS_TXEMPTY 0x04 50 #define ULITE_STATUS_TXFULL 0x08 51 #define ULITE_STATUS_IE 0x10 52 #define ULITE_STATUS_OVERRUN 0x20 53 #define ULITE_STATUS_FRAME 0x40 54 #define ULITE_STATUS_PARITY 0x80 55 56 #define ULITE_CONTROL_RST_TX 0x01 57 #define ULITE_CONTROL_RST_RX 0x02 58 #define ULITE_CONTROL_IE 0x10 59 #define UART_AUTOSUSPEND_TIMEOUT 3000 /* ms */ 60 61 /* Static pointer to console port */ 62 #ifdef CONFIG_SERIAL_UARTLITE_CONSOLE 63 static struct uart_port *console_port; 64 #endif 65 66 struct uartlite_data { 67 const struct uartlite_reg_ops *reg_ops; 68 struct clk *clk; 69 }; 70 71 struct uartlite_reg_ops { 72 u32 (*in)(void __iomem *addr); 73 void (*out)(u32 val, void __iomem *addr); 74 }; 75 76 static u32 uartlite_inbe32(void __iomem *addr) 77 { 78 return ioread32be(addr); 79 } 80 81 static void uartlite_outbe32(u32 val, void __iomem *addr) 82 { 83 iowrite32be(val, addr); 84 } 85 86 static const struct uartlite_reg_ops uartlite_be = { 87 .in = uartlite_inbe32, 88 .out = uartlite_outbe32, 89 }; 90 91 static u32 uartlite_inle32(void __iomem *addr) 92 { 93 return ioread32(addr); 94 } 95 96 static void uartlite_outle32(u32 val, void __iomem *addr) 97 { 98 iowrite32(val, addr); 99 } 100 101 static const struct uartlite_reg_ops uartlite_le = { 102 .in = uartlite_inle32, 103 .out = uartlite_outle32, 104 }; 105 106 static inline u32 uart_in32(u32 offset, struct uart_port *port) 107 { 108 struct uartlite_data *pdata = port->private_data; 109 110 return pdata->reg_ops->in(port->membase + offset); 111 } 112 113 static inline void uart_out32(u32 val, u32 offset, struct uart_port *port) 114 { 115 struct uartlite_data *pdata = port->private_data; 116 117 pdata->reg_ops->out(val, port->membase + offset); 118 } 119 120 static struct uart_port ulite_ports[ULITE_NR_UARTS]; 121 122 /* --------------------------------------------------------------------- 123 * Core UART driver operations 124 */ 125 126 static int ulite_receive(struct uart_port *port, int stat) 127 { 128 struct tty_port *tport = &port->state->port; 129 unsigned char ch = 0; 130 char flag = TTY_NORMAL; 131 132 if ((stat & (ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN 133 | ULITE_STATUS_FRAME)) == 0) 134 return 0; 135 136 /* stats */ 137 if (stat & ULITE_STATUS_RXVALID) { 138 port->icount.rx++; 139 ch = uart_in32(ULITE_RX, port); 140 141 if (stat & ULITE_STATUS_PARITY) 142 port->icount.parity++; 143 } 144 145 if (stat & ULITE_STATUS_OVERRUN) 146 port->icount.overrun++; 147 148 if (stat & ULITE_STATUS_FRAME) 149 port->icount.frame++; 150 151 152 /* drop byte with parity error if IGNPAR specificed */ 153 if (stat & port->ignore_status_mask & ULITE_STATUS_PARITY) 154 stat &= ~ULITE_STATUS_RXVALID; 155 156 stat &= port->read_status_mask; 157 158 if (stat & ULITE_STATUS_PARITY) 159 flag = TTY_PARITY; 160 161 162 stat &= ~port->ignore_status_mask; 163 164 if (stat & ULITE_STATUS_RXVALID) 165 tty_insert_flip_char(tport, ch, flag); 166 167 if (stat & ULITE_STATUS_FRAME) 168 tty_insert_flip_char(tport, 0, TTY_FRAME); 169 170 if (stat & ULITE_STATUS_OVERRUN) 171 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 172 173 return 1; 174 } 175 176 static int ulite_transmit(struct uart_port *port, int stat) 177 { 178 struct circ_buf *xmit = &port->state->xmit; 179 180 if (stat & ULITE_STATUS_TXFULL) 181 return 0; 182 183 if (port->x_char) { 184 uart_out32(port->x_char, ULITE_TX, port); 185 port->x_char = 0; 186 port->icount.tx++; 187 return 1; 188 } 189 190 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) 191 return 0; 192 193 uart_out32(xmit->buf[xmit->tail], ULITE_TX, port); 194 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE-1); 195 port->icount.tx++; 196 197 /* wake up */ 198 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 199 uart_write_wakeup(port); 200 201 return 1; 202 } 203 204 static irqreturn_t ulite_isr(int irq, void *dev_id) 205 { 206 struct uart_port *port = dev_id; 207 int stat, busy, n = 0; 208 unsigned long flags; 209 210 do { 211 spin_lock_irqsave(&port->lock, flags); 212 stat = uart_in32(ULITE_STATUS, port); 213 busy = ulite_receive(port, stat); 214 busy |= ulite_transmit(port, stat); 215 spin_unlock_irqrestore(&port->lock, flags); 216 n++; 217 } while (busy); 218 219 /* work done? */ 220 if (n > 1) { 221 tty_flip_buffer_push(&port->state->port); 222 return IRQ_HANDLED; 223 } else { 224 return IRQ_NONE; 225 } 226 } 227 228 static unsigned int ulite_tx_empty(struct uart_port *port) 229 { 230 unsigned long flags; 231 unsigned int ret; 232 233 spin_lock_irqsave(&port->lock, flags); 234 ret = uart_in32(ULITE_STATUS, port); 235 spin_unlock_irqrestore(&port->lock, flags); 236 237 return ret & ULITE_STATUS_TXEMPTY ? TIOCSER_TEMT : 0; 238 } 239 240 static unsigned int ulite_get_mctrl(struct uart_port *port) 241 { 242 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; 243 } 244 245 static void ulite_set_mctrl(struct uart_port *port, unsigned int mctrl) 246 { 247 /* N/A */ 248 } 249 250 static void ulite_stop_tx(struct uart_port *port) 251 { 252 /* N/A */ 253 } 254 255 static void ulite_start_tx(struct uart_port *port) 256 { 257 ulite_transmit(port, uart_in32(ULITE_STATUS, port)); 258 } 259 260 static void ulite_stop_rx(struct uart_port *port) 261 { 262 /* don't forward any more data (like !CREAD) */ 263 port->ignore_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY 264 | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN; 265 } 266 267 static void ulite_break_ctl(struct uart_port *port, int ctl) 268 { 269 /* N/A */ 270 } 271 272 static int ulite_startup(struct uart_port *port) 273 { 274 struct uartlite_data *pdata = port->private_data; 275 int ret; 276 277 ret = clk_enable(pdata->clk); 278 if (ret) { 279 dev_err(port->dev, "Failed to enable clock\n"); 280 return ret; 281 } 282 283 ret = request_irq(port->irq, ulite_isr, IRQF_SHARED | IRQF_TRIGGER_RISING, 284 "uartlite", port); 285 if (ret) 286 return ret; 287 288 uart_out32(ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX, 289 ULITE_CONTROL, port); 290 uart_out32(ULITE_CONTROL_IE, ULITE_CONTROL, port); 291 292 return 0; 293 } 294 295 static void ulite_shutdown(struct uart_port *port) 296 { 297 struct uartlite_data *pdata = port->private_data; 298 299 uart_out32(0, ULITE_CONTROL, port); 300 uart_in32(ULITE_CONTROL, port); /* dummy */ 301 free_irq(port->irq, port); 302 clk_disable(pdata->clk); 303 } 304 305 static void ulite_set_termios(struct uart_port *port, struct ktermios *termios, 306 struct ktermios *old) 307 { 308 unsigned long flags; 309 unsigned int baud; 310 311 spin_lock_irqsave(&port->lock, flags); 312 313 port->read_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN 314 | ULITE_STATUS_TXFULL; 315 316 if (termios->c_iflag & INPCK) 317 port->read_status_mask |= 318 ULITE_STATUS_PARITY | ULITE_STATUS_FRAME; 319 320 port->ignore_status_mask = 0; 321 if (termios->c_iflag & IGNPAR) 322 port->ignore_status_mask |= ULITE_STATUS_PARITY 323 | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN; 324 325 /* ignore all characters if CREAD is not set */ 326 if ((termios->c_cflag & CREAD) == 0) 327 port->ignore_status_mask |= 328 ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY 329 | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN; 330 331 /* update timeout */ 332 baud = uart_get_baud_rate(port, termios, old, 0, 460800); 333 uart_update_timeout(port, termios->c_cflag, baud); 334 335 spin_unlock_irqrestore(&port->lock, flags); 336 } 337 338 static const char *ulite_type(struct uart_port *port) 339 { 340 return port->type == PORT_UARTLITE ? "uartlite" : NULL; 341 } 342 343 static void ulite_release_port(struct uart_port *port) 344 { 345 release_mem_region(port->mapbase, ULITE_REGION); 346 iounmap(port->membase); 347 port->membase = NULL; 348 } 349 350 static int ulite_request_port(struct uart_port *port) 351 { 352 struct uartlite_data *pdata = port->private_data; 353 int ret; 354 355 pr_debug("ulite console: port=%p; port->mapbase=%llx\n", 356 port, (unsigned long long) port->mapbase); 357 358 if (!request_mem_region(port->mapbase, ULITE_REGION, "uartlite")) { 359 dev_err(port->dev, "Memory region busy\n"); 360 return -EBUSY; 361 } 362 363 port->membase = ioremap(port->mapbase, ULITE_REGION); 364 if (!port->membase) { 365 dev_err(port->dev, "Unable to map registers\n"); 366 release_mem_region(port->mapbase, ULITE_REGION); 367 return -EBUSY; 368 } 369 370 pdata->reg_ops = &uartlite_be; 371 ret = uart_in32(ULITE_CONTROL, port); 372 uart_out32(ULITE_CONTROL_RST_TX, ULITE_CONTROL, port); 373 ret = uart_in32(ULITE_STATUS, port); 374 /* Endianess detection */ 375 if ((ret & ULITE_STATUS_TXEMPTY) != ULITE_STATUS_TXEMPTY) 376 pdata->reg_ops = &uartlite_le; 377 378 return 0; 379 } 380 381 static void ulite_config_port(struct uart_port *port, int flags) 382 { 383 if (!ulite_request_port(port)) 384 port->type = PORT_UARTLITE; 385 } 386 387 static int ulite_verify_port(struct uart_port *port, struct serial_struct *ser) 388 { 389 /* we don't want the core code to modify any port params */ 390 return -EINVAL; 391 } 392 393 static void ulite_pm(struct uart_port *port, unsigned int state, 394 unsigned int oldstate) 395 { 396 int ret; 397 398 if (!state) { 399 ret = pm_runtime_get_sync(port->dev); 400 if (ret < 0) 401 dev_err(port->dev, "Failed to enable clocks\n"); 402 } else { 403 pm_runtime_mark_last_busy(port->dev); 404 pm_runtime_put_autosuspend(port->dev); 405 } 406 } 407 408 #ifdef CONFIG_CONSOLE_POLL 409 static int ulite_get_poll_char(struct uart_port *port) 410 { 411 if (!(uart_in32(ULITE_STATUS, port) & ULITE_STATUS_RXVALID)) 412 return NO_POLL_CHAR; 413 414 return uart_in32(ULITE_RX, port); 415 } 416 417 static void ulite_put_poll_char(struct uart_port *port, unsigned char ch) 418 { 419 while (uart_in32(ULITE_STATUS, port) & ULITE_STATUS_TXFULL) 420 cpu_relax(); 421 422 /* write char to device */ 423 uart_out32(ch, ULITE_TX, port); 424 } 425 #endif 426 427 static const struct uart_ops ulite_ops = { 428 .tx_empty = ulite_tx_empty, 429 .set_mctrl = ulite_set_mctrl, 430 .get_mctrl = ulite_get_mctrl, 431 .stop_tx = ulite_stop_tx, 432 .start_tx = ulite_start_tx, 433 .stop_rx = ulite_stop_rx, 434 .break_ctl = ulite_break_ctl, 435 .startup = ulite_startup, 436 .shutdown = ulite_shutdown, 437 .set_termios = ulite_set_termios, 438 .type = ulite_type, 439 .release_port = ulite_release_port, 440 .request_port = ulite_request_port, 441 .config_port = ulite_config_port, 442 .verify_port = ulite_verify_port, 443 .pm = ulite_pm, 444 #ifdef CONFIG_CONSOLE_POLL 445 .poll_get_char = ulite_get_poll_char, 446 .poll_put_char = ulite_put_poll_char, 447 #endif 448 }; 449 450 /* --------------------------------------------------------------------- 451 * Console driver operations 452 */ 453 454 #ifdef CONFIG_SERIAL_UARTLITE_CONSOLE 455 static void ulite_console_wait_tx(struct uart_port *port) 456 { 457 u8 val; 458 459 /* 460 * Spin waiting for TX fifo to have space available. 461 * When using the Microblaze Debug Module this can take up to 1s 462 */ 463 if (read_poll_timeout_atomic(uart_in32, val, !(val & ULITE_STATUS_TXFULL), 464 0, 1000000, false, ULITE_STATUS, port)) 465 dev_warn(port->dev, 466 "timeout waiting for TX buffer empty\n"); 467 } 468 469 static void ulite_console_putchar(struct uart_port *port, int ch) 470 { 471 ulite_console_wait_tx(port); 472 uart_out32(ch, ULITE_TX, port); 473 } 474 475 static void ulite_console_write(struct console *co, const char *s, 476 unsigned int count) 477 { 478 struct uart_port *port = console_port; 479 unsigned long flags; 480 unsigned int ier; 481 int locked = 1; 482 483 if (oops_in_progress) { 484 locked = spin_trylock_irqsave(&port->lock, flags); 485 } else 486 spin_lock_irqsave(&port->lock, flags); 487 488 /* save and disable interrupt */ 489 ier = uart_in32(ULITE_STATUS, port) & ULITE_STATUS_IE; 490 uart_out32(0, ULITE_CONTROL, port); 491 492 uart_console_write(port, s, count, ulite_console_putchar); 493 494 ulite_console_wait_tx(port); 495 496 /* restore interrupt state */ 497 if (ier) 498 uart_out32(ULITE_CONTROL_IE, ULITE_CONTROL, port); 499 500 if (locked) 501 spin_unlock_irqrestore(&port->lock, flags); 502 } 503 504 static int ulite_console_setup(struct console *co, char *options) 505 { 506 struct uart_port *port = NULL; 507 int baud = 9600; 508 int bits = 8; 509 int parity = 'n'; 510 int flow = 'n'; 511 512 if (co->index >= 0 && co->index < ULITE_NR_UARTS) 513 port = ulite_ports + co->index; 514 515 /* Has the device been initialized yet? */ 516 if (!port || !port->mapbase) { 517 pr_debug("console on ttyUL%i not present\n", co->index); 518 return -ENODEV; 519 } 520 521 console_port = port; 522 523 /* not initialized yet? */ 524 if (!port->membase) { 525 if (ulite_request_port(port)) 526 return -ENODEV; 527 } 528 529 if (options) 530 uart_parse_options(options, &baud, &parity, &bits, &flow); 531 532 return uart_set_options(port, co, baud, parity, bits, flow); 533 } 534 535 static struct uart_driver ulite_uart_driver; 536 537 static struct console ulite_console = { 538 .name = ULITE_NAME, 539 .write = ulite_console_write, 540 .device = uart_console_device, 541 .setup = ulite_console_setup, 542 .flags = CON_PRINTBUFFER, 543 .index = -1, /* Specified on the cmdline (e.g. console=ttyUL0 ) */ 544 .data = &ulite_uart_driver, 545 }; 546 547 static void early_uartlite_putc(struct uart_port *port, int c) 548 { 549 /* 550 * Limit how many times we'll spin waiting for TX FIFO status. 551 * This will prevent lockups if the base address is incorrectly 552 * set, or any other issue on the UARTLITE. 553 * This limit is pretty arbitrary, unless we are at about 10 baud 554 * we'll never timeout on a working UART. 555 */ 556 unsigned retries = 1000000; 557 558 while (--retries && 559 (readl(port->membase + ULITE_STATUS) & ULITE_STATUS_TXFULL)) 560 ; 561 562 /* Only attempt the iowrite if we didn't timeout */ 563 if (retries) 564 writel(c & 0xff, port->membase + ULITE_TX); 565 } 566 567 static void early_uartlite_write(struct console *console, 568 const char *s, unsigned n) 569 { 570 struct earlycon_device *device = console->data; 571 uart_console_write(&device->port, s, n, early_uartlite_putc); 572 } 573 574 static int __init early_uartlite_setup(struct earlycon_device *device, 575 const char *options) 576 { 577 if (!device->port.membase) 578 return -ENODEV; 579 580 device->con->write = early_uartlite_write; 581 return 0; 582 } 583 EARLYCON_DECLARE(uartlite, early_uartlite_setup); 584 OF_EARLYCON_DECLARE(uartlite_b, "xlnx,opb-uartlite-1.00.b", early_uartlite_setup); 585 OF_EARLYCON_DECLARE(uartlite_a, "xlnx,xps-uartlite-1.00.a", early_uartlite_setup); 586 587 #endif /* CONFIG_SERIAL_UARTLITE_CONSOLE */ 588 589 static struct uart_driver ulite_uart_driver = { 590 .owner = THIS_MODULE, 591 .driver_name = "uartlite", 592 .dev_name = ULITE_NAME, 593 .major = ULITE_MAJOR, 594 .minor = ULITE_MINOR, 595 .nr = ULITE_NR_UARTS, 596 #ifdef CONFIG_SERIAL_UARTLITE_CONSOLE 597 .cons = &ulite_console, 598 #endif 599 }; 600 601 /* --------------------------------------------------------------------- 602 * Port assignment functions (mapping devices to uart_port structures) 603 */ 604 605 /** ulite_assign: register a uartlite device with the driver 606 * 607 * @dev: pointer to device structure 608 * @id: requested id number. Pass -1 for automatic port assignment 609 * @base: base address of uartlite registers 610 * @irq: irq number for uartlite 611 * @pdata: private data for uartlite 612 * 613 * Returns: 0 on success, <0 otherwise 614 */ 615 static int ulite_assign(struct device *dev, int id, u32 base, int irq, 616 struct uartlite_data *pdata) 617 { 618 struct uart_port *port; 619 int rc; 620 621 /* if id = -1; then scan for a free id and use that */ 622 if (id < 0) { 623 for (id = 0; id < ULITE_NR_UARTS; id++) 624 if (ulite_ports[id].mapbase == 0) 625 break; 626 } 627 if (id < 0 || id >= ULITE_NR_UARTS) { 628 dev_err(dev, "%s%i too large\n", ULITE_NAME, id); 629 return -EINVAL; 630 } 631 632 if ((ulite_ports[id].mapbase) && (ulite_ports[id].mapbase != base)) { 633 dev_err(dev, "cannot assign to %s%i; it is already in use\n", 634 ULITE_NAME, id); 635 return -EBUSY; 636 } 637 638 port = &ulite_ports[id]; 639 640 spin_lock_init(&port->lock); 641 port->fifosize = 16; 642 port->regshift = 2; 643 port->iotype = UPIO_MEM; 644 port->iobase = 1; /* mark port in use */ 645 port->mapbase = base; 646 port->membase = NULL; 647 port->ops = &ulite_ops; 648 port->irq = irq; 649 port->flags = UPF_BOOT_AUTOCONF; 650 port->dev = dev; 651 port->type = PORT_UNKNOWN; 652 port->line = id; 653 port->private_data = pdata; 654 655 dev_set_drvdata(dev, port); 656 657 /* Register the port */ 658 rc = uart_add_one_port(&ulite_uart_driver, port); 659 if (rc) { 660 dev_err(dev, "uart_add_one_port() failed; err=%i\n", rc); 661 port->mapbase = 0; 662 dev_set_drvdata(dev, NULL); 663 return rc; 664 } 665 666 return 0; 667 } 668 669 /** ulite_release: register a uartlite device with the driver 670 * 671 * @dev: pointer to device structure 672 */ 673 static int ulite_release(struct device *dev) 674 { 675 struct uart_port *port = dev_get_drvdata(dev); 676 int rc = 0; 677 678 if (port) { 679 rc = uart_remove_one_port(&ulite_uart_driver, port); 680 dev_set_drvdata(dev, NULL); 681 port->mapbase = 0; 682 } 683 684 return rc; 685 } 686 687 /** 688 * ulite_suspend - Stop the device. 689 * 690 * @dev: handle to the device structure. 691 * Return: 0 always. 692 */ 693 static int __maybe_unused ulite_suspend(struct device *dev) 694 { 695 struct uart_port *port = dev_get_drvdata(dev); 696 697 if (port) 698 uart_suspend_port(&ulite_uart_driver, port); 699 700 return 0; 701 } 702 703 /** 704 * ulite_resume - Resume the device. 705 * 706 * @dev: handle to the device structure. 707 * Return: 0 on success, errno otherwise. 708 */ 709 static int __maybe_unused ulite_resume(struct device *dev) 710 { 711 struct uart_port *port = dev_get_drvdata(dev); 712 713 if (port) 714 uart_resume_port(&ulite_uart_driver, port); 715 716 return 0; 717 } 718 719 static int __maybe_unused ulite_runtime_suspend(struct device *dev) 720 { 721 struct uart_port *port = dev_get_drvdata(dev); 722 struct uartlite_data *pdata = port->private_data; 723 724 clk_disable(pdata->clk); 725 return 0; 726 }; 727 728 static int __maybe_unused ulite_runtime_resume(struct device *dev) 729 { 730 struct uart_port *port = dev_get_drvdata(dev); 731 struct uartlite_data *pdata = port->private_data; 732 int ret; 733 734 ret = clk_enable(pdata->clk); 735 if (ret) { 736 dev_err(dev, "Cannot enable clock.\n"); 737 return ret; 738 } 739 return 0; 740 } 741 742 /* --------------------------------------------------------------------- 743 * Platform bus binding 744 */ 745 746 static const struct dev_pm_ops ulite_pm_ops = { 747 SET_SYSTEM_SLEEP_PM_OPS(ulite_suspend, ulite_resume) 748 SET_RUNTIME_PM_OPS(ulite_runtime_suspend, 749 ulite_runtime_resume, NULL) 750 }; 751 752 #if defined(CONFIG_OF) 753 /* Match table for of_platform binding */ 754 static const struct of_device_id ulite_of_match[] = { 755 { .compatible = "xlnx,opb-uartlite-1.00.b", }, 756 { .compatible = "xlnx,xps-uartlite-1.00.a", }, 757 {} 758 }; 759 MODULE_DEVICE_TABLE(of, ulite_of_match); 760 #endif /* CONFIG_OF */ 761 762 static int ulite_probe(struct platform_device *pdev) 763 { 764 struct resource *res; 765 struct uartlite_data *pdata; 766 int irq, ret; 767 int id = pdev->id; 768 #ifdef CONFIG_OF 769 const __be32 *prop; 770 771 prop = of_get_property(pdev->dev.of_node, "port-number", NULL); 772 if (prop) 773 id = be32_to_cpup(prop); 774 #endif 775 pdata = devm_kzalloc(&pdev->dev, sizeof(struct uartlite_data), 776 GFP_KERNEL); 777 if (!pdata) 778 return -ENOMEM; 779 780 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 781 if (!res) 782 return -ENODEV; 783 784 irq = platform_get_irq(pdev, 0); 785 if (irq < 0) 786 return irq; 787 788 pdata->clk = devm_clk_get(&pdev->dev, "s_axi_aclk"); 789 if (IS_ERR(pdata->clk)) { 790 if (PTR_ERR(pdata->clk) != -ENOENT) 791 return PTR_ERR(pdata->clk); 792 793 /* 794 * Clock framework support is optional, continue on 795 * anyways if we don't find a matching clock. 796 */ 797 pdata->clk = NULL; 798 } 799 800 ret = clk_prepare_enable(pdata->clk); 801 if (ret) { 802 dev_err(&pdev->dev, "Failed to prepare clock\n"); 803 return ret; 804 } 805 806 pm_runtime_use_autosuspend(&pdev->dev); 807 pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT); 808 pm_runtime_set_active(&pdev->dev); 809 pm_runtime_enable(&pdev->dev); 810 811 if (!ulite_uart_driver.state) { 812 dev_dbg(&pdev->dev, "uartlite: calling uart_register_driver()\n"); 813 ret = uart_register_driver(&ulite_uart_driver); 814 if (ret < 0) { 815 dev_err(&pdev->dev, "Failed to register driver\n"); 816 clk_disable_unprepare(pdata->clk); 817 return ret; 818 } 819 } 820 821 ret = ulite_assign(&pdev->dev, id, res->start, irq, pdata); 822 823 pm_runtime_mark_last_busy(&pdev->dev); 824 pm_runtime_put_autosuspend(&pdev->dev); 825 826 return ret; 827 } 828 829 static int ulite_remove(struct platform_device *pdev) 830 { 831 struct uart_port *port = dev_get_drvdata(&pdev->dev); 832 struct uartlite_data *pdata = port->private_data; 833 int rc; 834 835 clk_disable_unprepare(pdata->clk); 836 rc = ulite_release(&pdev->dev); 837 pm_runtime_disable(&pdev->dev); 838 pm_runtime_set_suspended(&pdev->dev); 839 pm_runtime_dont_use_autosuspend(&pdev->dev); 840 return rc; 841 } 842 843 /* work with hotplug and coldplug */ 844 MODULE_ALIAS("platform:uartlite"); 845 846 static struct platform_driver ulite_platform_driver = { 847 .probe = ulite_probe, 848 .remove = ulite_remove, 849 .driver = { 850 .name = "uartlite", 851 .of_match_table = of_match_ptr(ulite_of_match), 852 .pm = &ulite_pm_ops, 853 }, 854 }; 855 856 /* --------------------------------------------------------------------- 857 * Module setup/teardown 858 */ 859 860 static int __init ulite_init(void) 861 { 862 863 pr_debug("uartlite: calling platform_driver_register()\n"); 864 return platform_driver_register(&ulite_platform_driver); 865 } 866 867 static void __exit ulite_exit(void) 868 { 869 platform_driver_unregister(&ulite_platform_driver); 870 if (ulite_uart_driver.state) 871 uart_unregister_driver(&ulite_uart_driver); 872 } 873 874 module_init(ulite_init); 875 module_exit(ulite_exit); 876 877 MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>"); 878 MODULE_DESCRIPTION("Xilinx uartlite serial driver"); 879 MODULE_LICENSE("GPL"); 880