xref: /openbmc/linux/drivers/tty/serial/sunzilog.c (revision d2999e1b)
1 /* sunzilog.c: Zilog serial driver for Sparc systems.
2  *
3  * Driver for Zilog serial chips found on Sun workstations and
4  * servers.  This driver could actually be made more generic.
5  *
6  * This is based on the old drivers/sbus/char/zs.c code.  A lot
7  * of code has been simply moved over directly from there but
8  * much has been rewritten.  Credits therefore go out to Eddie
9  * C. Dost, Pete Zaitcev, Ted Ts'o and Alex Buell for their
10  * work there.
11  *
12  * Copyright (C) 2002, 2006, 2007 David S. Miller (davem@davemloft.net)
13  */
14 
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/errno.h>
18 #include <linux/delay.h>
19 #include <linux/tty.h>
20 #include <linux/tty_flip.h>
21 #include <linux/major.h>
22 #include <linux/string.h>
23 #include <linux/ptrace.h>
24 #include <linux/ioport.h>
25 #include <linux/slab.h>
26 #include <linux/circ_buf.h>
27 #include <linux/serial.h>
28 #include <linux/sysrq.h>
29 #include <linux/console.h>
30 #include <linux/spinlock.h>
31 #ifdef CONFIG_SERIO
32 #include <linux/serio.h>
33 #endif
34 #include <linux/init.h>
35 #include <linux/of_device.h>
36 
37 #include <asm/io.h>
38 #include <asm/irq.h>
39 #include <asm/prom.h>
40 #include <asm/setup.h>
41 
42 #if defined(CONFIG_SERIAL_SUNZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
43 #define SUPPORT_SYSRQ
44 #endif
45 
46 #include <linux/serial_core.h>
47 #include <linux/sunserialcore.h>
48 
49 #include "sunzilog.h"
50 
51 /* On 32-bit sparcs we need to delay after register accesses
52  * to accommodate sun4 systems, but we do not need to flush writes.
53  * On 64-bit sparc we only need to flush single writes to ensure
54  * completion.
55  */
56 #ifndef CONFIG_SPARC64
57 #define ZSDELAY()		udelay(5)
58 #define ZSDELAY_LONG()		udelay(20)
59 #define ZS_WSYNC(channel)	do { } while (0)
60 #else
61 #define ZSDELAY()
62 #define ZSDELAY_LONG()
63 #define ZS_WSYNC(__channel) \
64 	readb(&((__channel)->control))
65 #endif
66 
67 #define ZS_CLOCK		4915200 /* Zilog input clock rate. */
68 #define ZS_CLOCK_DIVISOR	16      /* Divisor this driver uses. */
69 
70 /*
71  * We wrap our port structure around the generic uart_port.
72  */
73 struct uart_sunzilog_port {
74 	struct uart_port		port;
75 
76 	/* IRQ servicing chain.  */
77 	struct uart_sunzilog_port	*next;
78 
79 	/* Current values of Zilog write registers.  */
80 	unsigned char			curregs[NUM_ZSREGS];
81 
82 	unsigned int			flags;
83 #define SUNZILOG_FLAG_CONS_KEYB		0x00000001
84 #define SUNZILOG_FLAG_CONS_MOUSE	0x00000002
85 #define SUNZILOG_FLAG_IS_CONS		0x00000004
86 #define SUNZILOG_FLAG_IS_KGDB		0x00000008
87 #define SUNZILOG_FLAG_MODEM_STATUS	0x00000010
88 #define SUNZILOG_FLAG_IS_CHANNEL_A	0x00000020
89 #define SUNZILOG_FLAG_REGS_HELD		0x00000040
90 #define SUNZILOG_FLAG_TX_STOPPED	0x00000080
91 #define SUNZILOG_FLAG_TX_ACTIVE		0x00000100
92 #define SUNZILOG_FLAG_ESCC		0x00000200
93 #define SUNZILOG_FLAG_ISR_HANDLER	0x00000400
94 
95 	unsigned int cflag;
96 
97 	unsigned char			parity_mask;
98 	unsigned char			prev_status;
99 
100 #ifdef CONFIG_SERIO
101 	struct serio			serio;
102 	int				serio_open;
103 #endif
104 };
105 
106 static void sunzilog_putchar(struct uart_port *port, int ch);
107 
108 #define ZILOG_CHANNEL_FROM_PORT(PORT)	((struct zilog_channel __iomem *)((PORT)->membase))
109 #define UART_ZILOG(PORT)		((struct uart_sunzilog_port *)(PORT))
110 
111 #define ZS_IS_KEYB(UP)	((UP)->flags & SUNZILOG_FLAG_CONS_KEYB)
112 #define ZS_IS_MOUSE(UP)	((UP)->flags & SUNZILOG_FLAG_CONS_MOUSE)
113 #define ZS_IS_CONS(UP)	((UP)->flags & SUNZILOG_FLAG_IS_CONS)
114 #define ZS_IS_KGDB(UP)	((UP)->flags & SUNZILOG_FLAG_IS_KGDB)
115 #define ZS_WANTS_MODEM_STATUS(UP)	((UP)->flags & SUNZILOG_FLAG_MODEM_STATUS)
116 #define ZS_IS_CHANNEL_A(UP)	((UP)->flags & SUNZILOG_FLAG_IS_CHANNEL_A)
117 #define ZS_REGS_HELD(UP)	((UP)->flags & SUNZILOG_FLAG_REGS_HELD)
118 #define ZS_TX_STOPPED(UP)	((UP)->flags & SUNZILOG_FLAG_TX_STOPPED)
119 #define ZS_TX_ACTIVE(UP)	((UP)->flags & SUNZILOG_FLAG_TX_ACTIVE)
120 
121 /* Reading and writing Zilog8530 registers.  The delays are to make this
122  * driver work on the Sun4 which needs a settling delay after each chip
123  * register access, other machines handle this in hardware via auxiliary
124  * flip-flops which implement the settle time we do in software.
125  *
126  * The port lock must be held and local IRQs must be disabled
127  * when {read,write}_zsreg is invoked.
128  */
129 static unsigned char read_zsreg(struct zilog_channel __iomem *channel,
130 				unsigned char reg)
131 {
132 	unsigned char retval;
133 
134 	writeb(reg, &channel->control);
135 	ZSDELAY();
136 	retval = readb(&channel->control);
137 	ZSDELAY();
138 
139 	return retval;
140 }
141 
142 static void write_zsreg(struct zilog_channel __iomem *channel,
143 			unsigned char reg, unsigned char value)
144 {
145 	writeb(reg, &channel->control);
146 	ZSDELAY();
147 	writeb(value, &channel->control);
148 	ZSDELAY();
149 }
150 
151 static void sunzilog_clear_fifo(struct zilog_channel __iomem *channel)
152 {
153 	int i;
154 
155 	for (i = 0; i < 32; i++) {
156 		unsigned char regval;
157 
158 		regval = readb(&channel->control);
159 		ZSDELAY();
160 		if (regval & Rx_CH_AV)
161 			break;
162 
163 		regval = read_zsreg(channel, R1);
164 		readb(&channel->data);
165 		ZSDELAY();
166 
167 		if (regval & (PAR_ERR | Rx_OVR | CRC_ERR)) {
168 			writeb(ERR_RES, &channel->control);
169 			ZSDELAY();
170 			ZS_WSYNC(channel);
171 		}
172 	}
173 }
174 
175 /* This function must only be called when the TX is not busy.  The UART
176  * port lock must be held and local interrupts disabled.
177  */
178 static int __load_zsregs(struct zilog_channel __iomem *channel, unsigned char *regs)
179 {
180 	int i;
181 	int escc;
182 	unsigned char r15;
183 
184 	/* Let pending transmits finish.  */
185 	for (i = 0; i < 1000; i++) {
186 		unsigned char stat = read_zsreg(channel, R1);
187 		if (stat & ALL_SNT)
188 			break;
189 		udelay(100);
190 	}
191 
192 	writeb(ERR_RES, &channel->control);
193 	ZSDELAY();
194 	ZS_WSYNC(channel);
195 
196 	sunzilog_clear_fifo(channel);
197 
198 	/* Disable all interrupts.  */
199 	write_zsreg(channel, R1,
200 		    regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));
201 
202 	/* Set parity, sync config, stop bits, and clock divisor.  */
203 	write_zsreg(channel, R4, regs[R4]);
204 
205 	/* Set misc. TX/RX control bits.  */
206 	write_zsreg(channel, R10, regs[R10]);
207 
208 	/* Set TX/RX controls sans the enable bits.  */
209 	write_zsreg(channel, R3, regs[R3] & ~RxENAB);
210 	write_zsreg(channel, R5, regs[R5] & ~TxENAB);
211 
212 	/* Synchronous mode config.  */
213 	write_zsreg(channel, R6, regs[R6]);
214 	write_zsreg(channel, R7, regs[R7]);
215 
216 	/* Don't mess with the interrupt vector (R2, unused by us) and
217 	 * master interrupt control (R9).  We make sure this is setup
218 	 * properly at probe time then never touch it again.
219 	 */
220 
221 	/* Disable baud generator.  */
222 	write_zsreg(channel, R14, regs[R14] & ~BRENAB);
223 
224 	/* Clock mode control.  */
225 	write_zsreg(channel, R11, regs[R11]);
226 
227 	/* Lower and upper byte of baud rate generator divisor.  */
228 	write_zsreg(channel, R12, regs[R12]);
229 	write_zsreg(channel, R13, regs[R13]);
230 
231 	/* Now rewrite R14, with BRENAB (if set).  */
232 	write_zsreg(channel, R14, regs[R14]);
233 
234 	/* External status interrupt control.  */
235 	write_zsreg(channel, R15, (regs[R15] | WR7pEN) & ~FIFOEN);
236 
237 	/* ESCC Extension Register */
238 	r15 = read_zsreg(channel, R15);
239 	if (r15 & 0x01)	{
240 		write_zsreg(channel, R7,  regs[R7p]);
241 
242 		/* External status interrupt and FIFO control.  */
243 		write_zsreg(channel, R15, regs[R15] & ~WR7pEN);
244 		escc = 1;
245 	} else {
246 		 /* Clear FIFO bit case it is an issue */
247 		regs[R15] &= ~FIFOEN;
248 		escc = 0;
249 	}
250 
251 	/* Reset external status interrupts.  */
252 	write_zsreg(channel, R0, RES_EXT_INT); /* First Latch  */
253 	write_zsreg(channel, R0, RES_EXT_INT); /* Second Latch */
254 
255 	/* Rewrite R3/R5, this time without enables masked.  */
256 	write_zsreg(channel, R3, regs[R3]);
257 	write_zsreg(channel, R5, regs[R5]);
258 
259 	/* Rewrite R1, this time without IRQ enabled masked.  */
260 	write_zsreg(channel, R1, regs[R1]);
261 
262 	return escc;
263 }
264 
265 /* Reprogram the Zilog channel HW registers with the copies found in the
266  * software state struct.  If the transmitter is busy, we defer this update
267  * until the next TX complete interrupt.  Else, we do it right now.
268  *
269  * The UART port lock must be held and local interrupts disabled.
270  */
271 static void sunzilog_maybe_update_regs(struct uart_sunzilog_port *up,
272 				       struct zilog_channel __iomem *channel)
273 {
274 	if (!ZS_REGS_HELD(up)) {
275 		if (ZS_TX_ACTIVE(up)) {
276 			up->flags |= SUNZILOG_FLAG_REGS_HELD;
277 		} else {
278 			__load_zsregs(channel, up->curregs);
279 		}
280 	}
281 }
282 
283 static void sunzilog_change_mouse_baud(struct uart_sunzilog_port *up)
284 {
285 	unsigned int cur_cflag = up->cflag;
286 	int brg, new_baud;
287 
288 	up->cflag &= ~CBAUD;
289 	up->cflag |= suncore_mouse_baud_cflag_next(cur_cflag, &new_baud);
290 
291 	brg = BPS_TO_BRG(new_baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
292 	up->curregs[R12] = (brg & 0xff);
293 	up->curregs[R13] = (brg >> 8) & 0xff;
294 	sunzilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(&up->port));
295 }
296 
297 static void sunzilog_kbdms_receive_chars(struct uart_sunzilog_port *up,
298 					 unsigned char ch, int is_break)
299 {
300 	if (ZS_IS_KEYB(up)) {
301 		/* Stop-A is handled by drivers/char/keyboard.c now. */
302 #ifdef CONFIG_SERIO
303 		if (up->serio_open)
304 			serio_interrupt(&up->serio, ch, 0);
305 #endif
306 	} else if (ZS_IS_MOUSE(up)) {
307 		int ret = suncore_mouse_baud_detection(ch, is_break);
308 
309 		switch (ret) {
310 		case 2:
311 			sunzilog_change_mouse_baud(up);
312 			/* fallthru */
313 		case 1:
314 			break;
315 
316 		case 0:
317 #ifdef CONFIG_SERIO
318 			if (up->serio_open)
319 				serio_interrupt(&up->serio, ch, 0);
320 #endif
321 			break;
322 		}
323 	}
324 }
325 
326 static struct tty_port *
327 sunzilog_receive_chars(struct uart_sunzilog_port *up,
328 		       struct zilog_channel __iomem *channel)
329 {
330 	struct tty_port *port = NULL;
331 	unsigned char ch, r1, flag;
332 
333 	if (up->port.state != NULL)		/* Unopened serial console */
334 		port = &up->port.state->port;
335 
336 	for (;;) {
337 
338 		r1 = read_zsreg(channel, R1);
339 		if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
340 			writeb(ERR_RES, &channel->control);
341 			ZSDELAY();
342 			ZS_WSYNC(channel);
343 		}
344 
345 		ch = readb(&channel->control);
346 		ZSDELAY();
347 
348 		/* This funny hack depends upon BRK_ABRT not interfering
349 		 * with the other bits we care about in R1.
350 		 */
351 		if (ch & BRK_ABRT)
352 			r1 |= BRK_ABRT;
353 
354 		if (!(ch & Rx_CH_AV))
355 			break;
356 
357 		ch = readb(&channel->data);
358 		ZSDELAY();
359 
360 		ch &= up->parity_mask;
361 
362 		if (unlikely(ZS_IS_KEYB(up)) || unlikely(ZS_IS_MOUSE(up))) {
363 			sunzilog_kbdms_receive_chars(up, ch, 0);
364 			continue;
365 		}
366 
367 		/* A real serial line, record the character and status.  */
368 		flag = TTY_NORMAL;
369 		up->port.icount.rx++;
370 		if (r1 & (BRK_ABRT | PAR_ERR | Rx_OVR | CRC_ERR)) {
371 			if (r1 & BRK_ABRT) {
372 				r1 &= ~(PAR_ERR | CRC_ERR);
373 				up->port.icount.brk++;
374 				if (uart_handle_break(&up->port))
375 					continue;
376 			}
377 			else if (r1 & PAR_ERR)
378 				up->port.icount.parity++;
379 			else if (r1 & CRC_ERR)
380 				up->port.icount.frame++;
381 			if (r1 & Rx_OVR)
382 				up->port.icount.overrun++;
383 			r1 &= up->port.read_status_mask;
384 			if (r1 & BRK_ABRT)
385 				flag = TTY_BREAK;
386 			else if (r1 & PAR_ERR)
387 				flag = TTY_PARITY;
388 			else if (r1 & CRC_ERR)
389 				flag = TTY_FRAME;
390 		}
391 		if (uart_handle_sysrq_char(&up->port, ch) || !port)
392 			continue;
393 
394 		if (up->port.ignore_status_mask == 0xff ||
395 		    (r1 & up->port.ignore_status_mask) == 0) {
396 		    	tty_insert_flip_char(port, ch, flag);
397 		}
398 		if (r1 & Rx_OVR)
399 			tty_insert_flip_char(port, 0, TTY_OVERRUN);
400 	}
401 
402 	return port;
403 }
404 
405 static void sunzilog_status_handle(struct uart_sunzilog_port *up,
406 				   struct zilog_channel __iomem *channel)
407 {
408 	unsigned char status;
409 
410 	status = readb(&channel->control);
411 	ZSDELAY();
412 
413 	writeb(RES_EXT_INT, &channel->control);
414 	ZSDELAY();
415 	ZS_WSYNC(channel);
416 
417 	if (status & BRK_ABRT) {
418 		if (ZS_IS_MOUSE(up))
419 			sunzilog_kbdms_receive_chars(up, 0, 1);
420 		if (ZS_IS_CONS(up)) {
421 			/* Wait for BREAK to deassert to avoid potentially
422 			 * confusing the PROM.
423 			 */
424 			while (1) {
425 				status = readb(&channel->control);
426 				ZSDELAY();
427 				if (!(status & BRK_ABRT))
428 					break;
429 			}
430 			sun_do_break();
431 			return;
432 		}
433 	}
434 
435 	if (ZS_WANTS_MODEM_STATUS(up)) {
436 		if (status & SYNC)
437 			up->port.icount.dsr++;
438 
439 		/* The Zilog just gives us an interrupt when DCD/CTS/etc. change.
440 		 * But it does not tell us which bit has changed, we have to keep
441 		 * track of this ourselves.
442 		 */
443 		if ((status ^ up->prev_status) ^ DCD)
444 			uart_handle_dcd_change(&up->port,
445 					       (status & DCD));
446 		if ((status ^ up->prev_status) ^ CTS)
447 			uart_handle_cts_change(&up->port,
448 					       (status & CTS));
449 
450 		wake_up_interruptible(&up->port.state->port.delta_msr_wait);
451 	}
452 
453 	up->prev_status = status;
454 }
455 
456 static void sunzilog_transmit_chars(struct uart_sunzilog_port *up,
457 				    struct zilog_channel __iomem *channel)
458 {
459 	struct circ_buf *xmit;
460 
461 	if (ZS_IS_CONS(up)) {
462 		unsigned char status = readb(&channel->control);
463 		ZSDELAY();
464 
465 		/* TX still busy?  Just wait for the next TX done interrupt.
466 		 *
467 		 * It can occur because of how we do serial console writes.  It would
468 		 * be nice to transmit console writes just like we normally would for
469 		 * a TTY line. (ie. buffered and TX interrupt driven).  That is not
470 		 * easy because console writes cannot sleep.  One solution might be
471 		 * to poll on enough port->xmit space becoming free.  -DaveM
472 		 */
473 		if (!(status & Tx_BUF_EMP))
474 			return;
475 	}
476 
477 	up->flags &= ~SUNZILOG_FLAG_TX_ACTIVE;
478 
479 	if (ZS_REGS_HELD(up)) {
480 		__load_zsregs(channel, up->curregs);
481 		up->flags &= ~SUNZILOG_FLAG_REGS_HELD;
482 	}
483 
484 	if (ZS_TX_STOPPED(up)) {
485 		up->flags &= ~SUNZILOG_FLAG_TX_STOPPED;
486 		goto ack_tx_int;
487 	}
488 
489 	if (up->port.x_char) {
490 		up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
491 		writeb(up->port.x_char, &channel->data);
492 		ZSDELAY();
493 		ZS_WSYNC(channel);
494 
495 		up->port.icount.tx++;
496 		up->port.x_char = 0;
497 		return;
498 	}
499 
500 	if (up->port.state == NULL)
501 		goto ack_tx_int;
502 	xmit = &up->port.state->xmit;
503 	if (uart_circ_empty(xmit))
504 		goto ack_tx_int;
505 
506 	if (uart_tx_stopped(&up->port))
507 		goto ack_tx_int;
508 
509 	up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
510 	writeb(xmit->buf[xmit->tail], &channel->data);
511 	ZSDELAY();
512 	ZS_WSYNC(channel);
513 
514 	xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
515 	up->port.icount.tx++;
516 
517 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
518 		uart_write_wakeup(&up->port);
519 
520 	return;
521 
522 ack_tx_int:
523 	writeb(RES_Tx_P, &channel->control);
524 	ZSDELAY();
525 	ZS_WSYNC(channel);
526 }
527 
528 static irqreturn_t sunzilog_interrupt(int irq, void *dev_id)
529 {
530 	struct uart_sunzilog_port *up = dev_id;
531 
532 	while (up) {
533 		struct zilog_channel __iomem *channel
534 			= ZILOG_CHANNEL_FROM_PORT(&up->port);
535 		struct tty_port *port;
536 		unsigned char r3;
537 
538 		spin_lock(&up->port.lock);
539 		r3 = read_zsreg(channel, R3);
540 
541 		/* Channel A */
542 		port = NULL;
543 		if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
544 			writeb(RES_H_IUS, &channel->control);
545 			ZSDELAY();
546 			ZS_WSYNC(channel);
547 
548 			if (r3 & CHARxIP)
549 				port = sunzilog_receive_chars(up, channel);
550 			if (r3 & CHAEXT)
551 				sunzilog_status_handle(up, channel);
552 			if (r3 & CHATxIP)
553 				sunzilog_transmit_chars(up, channel);
554 		}
555 		spin_unlock(&up->port.lock);
556 
557 		if (port)
558 			tty_flip_buffer_push(port);
559 
560 		/* Channel B */
561 		up = up->next;
562 		channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
563 
564 		spin_lock(&up->port.lock);
565 		port = NULL;
566 		if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
567 			writeb(RES_H_IUS, &channel->control);
568 			ZSDELAY();
569 			ZS_WSYNC(channel);
570 
571 			if (r3 & CHBRxIP)
572 				port = sunzilog_receive_chars(up, channel);
573 			if (r3 & CHBEXT)
574 				sunzilog_status_handle(up, channel);
575 			if (r3 & CHBTxIP)
576 				sunzilog_transmit_chars(up, channel);
577 		}
578 		spin_unlock(&up->port.lock);
579 
580 		if (port)
581 			tty_flip_buffer_push(port);
582 
583 		up = up->next;
584 	}
585 
586 	return IRQ_HANDLED;
587 }
588 
589 /* A convenient way to quickly get R0 status.  The caller must _not_ hold the
590  * port lock, it is acquired here.
591  */
592 static __inline__ unsigned char sunzilog_read_channel_status(struct uart_port *port)
593 {
594 	struct zilog_channel __iomem *channel;
595 	unsigned char status;
596 
597 	channel = ZILOG_CHANNEL_FROM_PORT(port);
598 	status = readb(&channel->control);
599 	ZSDELAY();
600 
601 	return status;
602 }
603 
604 /* The port lock is not held.  */
605 static unsigned int sunzilog_tx_empty(struct uart_port *port)
606 {
607 	unsigned long flags;
608 	unsigned char status;
609 	unsigned int ret;
610 
611 	spin_lock_irqsave(&port->lock, flags);
612 
613 	status = sunzilog_read_channel_status(port);
614 
615 	spin_unlock_irqrestore(&port->lock, flags);
616 
617 	if (status & Tx_BUF_EMP)
618 		ret = TIOCSER_TEMT;
619 	else
620 		ret = 0;
621 
622 	return ret;
623 }
624 
625 /* The port lock is held and interrupts are disabled.  */
626 static unsigned int sunzilog_get_mctrl(struct uart_port *port)
627 {
628 	unsigned char status;
629 	unsigned int ret;
630 
631 	status = sunzilog_read_channel_status(port);
632 
633 	ret = 0;
634 	if (status & DCD)
635 		ret |= TIOCM_CAR;
636 	if (status & SYNC)
637 		ret |= TIOCM_DSR;
638 	if (status & CTS)
639 		ret |= TIOCM_CTS;
640 
641 	return ret;
642 }
643 
644 /* The port lock is held and interrupts are disabled.  */
645 static void sunzilog_set_mctrl(struct uart_port *port, unsigned int mctrl)
646 {
647 	struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
648 	struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
649 	unsigned char set_bits, clear_bits;
650 
651 	set_bits = clear_bits = 0;
652 
653 	if (mctrl & TIOCM_RTS)
654 		set_bits |= RTS;
655 	else
656 		clear_bits |= RTS;
657 	if (mctrl & TIOCM_DTR)
658 		set_bits |= DTR;
659 	else
660 		clear_bits |= DTR;
661 
662 	/* NOTE: Not subject to 'transmitter active' rule.  */
663 	up->curregs[R5] |= set_bits;
664 	up->curregs[R5] &= ~clear_bits;
665 	write_zsreg(channel, R5, up->curregs[R5]);
666 }
667 
668 /* The port lock is held and interrupts are disabled.  */
669 static void sunzilog_stop_tx(struct uart_port *port)
670 {
671 	struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
672 
673 	up->flags |= SUNZILOG_FLAG_TX_STOPPED;
674 }
675 
676 /* The port lock is held and interrupts are disabled.  */
677 static void sunzilog_start_tx(struct uart_port *port)
678 {
679 	struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
680 	struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
681 	unsigned char status;
682 
683 	up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
684 	up->flags &= ~SUNZILOG_FLAG_TX_STOPPED;
685 
686 	status = readb(&channel->control);
687 	ZSDELAY();
688 
689 	/* TX busy?  Just wait for the TX done interrupt.  */
690 	if (!(status & Tx_BUF_EMP))
691 		return;
692 
693 	/* Send the first character to jump-start the TX done
694 	 * IRQ sending engine.
695 	 */
696 	if (port->x_char) {
697 		writeb(port->x_char, &channel->data);
698 		ZSDELAY();
699 		ZS_WSYNC(channel);
700 
701 		port->icount.tx++;
702 		port->x_char = 0;
703 	} else {
704 		struct circ_buf *xmit = &port->state->xmit;
705 
706 		writeb(xmit->buf[xmit->tail], &channel->data);
707 		ZSDELAY();
708 		ZS_WSYNC(channel);
709 
710 		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
711 		port->icount.tx++;
712 
713 		if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
714 			uart_write_wakeup(&up->port);
715 	}
716 }
717 
718 /* The port lock is held.  */
719 static void sunzilog_stop_rx(struct uart_port *port)
720 {
721 	struct uart_sunzilog_port *up = UART_ZILOG(port);
722 	struct zilog_channel __iomem *channel;
723 
724 	if (ZS_IS_CONS(up))
725 		return;
726 
727 	channel = ZILOG_CHANNEL_FROM_PORT(port);
728 
729 	/* Disable all RX interrupts.  */
730 	up->curregs[R1] &= ~RxINT_MASK;
731 	sunzilog_maybe_update_regs(up, channel);
732 }
733 
734 /* The port lock is held.  */
735 static void sunzilog_enable_ms(struct uart_port *port)
736 {
737 	struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
738 	struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
739 	unsigned char new_reg;
740 
741 	new_reg = up->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
742 	if (new_reg != up->curregs[R15]) {
743 		up->curregs[R15] = new_reg;
744 
745 		/* NOTE: Not subject to 'transmitter active' rule.  */
746 		write_zsreg(channel, R15, up->curregs[R15] & ~WR7pEN);
747 	}
748 }
749 
750 /* The port lock is not held.  */
751 static void sunzilog_break_ctl(struct uart_port *port, int break_state)
752 {
753 	struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
754 	struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
755 	unsigned char set_bits, clear_bits, new_reg;
756 	unsigned long flags;
757 
758 	set_bits = clear_bits = 0;
759 
760 	if (break_state)
761 		set_bits |= SND_BRK;
762 	else
763 		clear_bits |= SND_BRK;
764 
765 	spin_lock_irqsave(&port->lock, flags);
766 
767 	new_reg = (up->curregs[R5] | set_bits) & ~clear_bits;
768 	if (new_reg != up->curregs[R5]) {
769 		up->curregs[R5] = new_reg;
770 
771 		/* NOTE: Not subject to 'transmitter active' rule.  */
772 		write_zsreg(channel, R5, up->curregs[R5]);
773 	}
774 
775 	spin_unlock_irqrestore(&port->lock, flags);
776 }
777 
778 static void __sunzilog_startup(struct uart_sunzilog_port *up)
779 {
780 	struct zilog_channel __iomem *channel;
781 
782 	channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
783 	up->prev_status = readb(&channel->control);
784 
785 	/* Enable receiver and transmitter.  */
786 	up->curregs[R3] |= RxENAB;
787 	up->curregs[R5] |= TxENAB;
788 
789 	up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
790 	sunzilog_maybe_update_regs(up, channel);
791 }
792 
793 static int sunzilog_startup(struct uart_port *port)
794 {
795 	struct uart_sunzilog_port *up = UART_ZILOG(port);
796 	unsigned long flags;
797 
798 	if (ZS_IS_CONS(up))
799 		return 0;
800 
801 	spin_lock_irqsave(&port->lock, flags);
802 	__sunzilog_startup(up);
803 	spin_unlock_irqrestore(&port->lock, flags);
804 	return 0;
805 }
806 
807 /*
808  * The test for ZS_IS_CONS is explained by the following e-mail:
809  *****
810  * From: Russell King <rmk@arm.linux.org.uk>
811  * Date: Sun, 8 Dec 2002 10:18:38 +0000
812  *
813  * On Sun, Dec 08, 2002 at 02:43:36AM -0500, Pete Zaitcev wrote:
814  * > I boot my 2.5 boxes using "console=ttyS0,9600" argument,
815  * > and I noticed that something is not right with reference
816  * > counting in this case. It seems that when the console
817  * > is open by kernel initially, this is not accounted
818  * > as an open, and uart_startup is not called.
819  *
820  * That is correct.  We are unable to call uart_startup when the serial
821  * console is initialised because it may need to allocate memory (as
822  * request_irq does) and the memory allocators may not have been
823  * initialised.
824  *
825  * 1. initialise the port into a state where it can send characters in the
826  *    console write method.
827  *
828  * 2. don't do the actual hardware shutdown in your shutdown() method (but
829  *    do the normal software shutdown - ie, free irqs etc)
830  *****
831  */
832 static void sunzilog_shutdown(struct uart_port *port)
833 {
834 	struct uart_sunzilog_port *up = UART_ZILOG(port);
835 	struct zilog_channel __iomem *channel;
836 	unsigned long flags;
837 
838 	if (ZS_IS_CONS(up))
839 		return;
840 
841 	spin_lock_irqsave(&port->lock, flags);
842 
843 	channel = ZILOG_CHANNEL_FROM_PORT(port);
844 
845 	/* Disable receiver and transmitter.  */
846 	up->curregs[R3] &= ~RxENAB;
847 	up->curregs[R5] &= ~TxENAB;
848 
849 	/* Disable all interrupts and BRK assertion.  */
850 	up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
851 	up->curregs[R5] &= ~SND_BRK;
852 	sunzilog_maybe_update_regs(up, channel);
853 
854 	spin_unlock_irqrestore(&port->lock, flags);
855 }
856 
857 /* Shared by TTY driver and serial console setup.  The port lock is held
858  * and local interrupts are disabled.
859  */
860 static void
861 sunzilog_convert_to_zs(struct uart_sunzilog_port *up, unsigned int cflag,
862 		       unsigned int iflag, int brg)
863 {
864 
865 	up->curregs[R10] = NRZ;
866 	up->curregs[R11] = TCBR | RCBR;
867 
868 	/* Program BAUD and clock source. */
869 	up->curregs[R4] &= ~XCLK_MASK;
870 	up->curregs[R4] |= X16CLK;
871 	up->curregs[R12] = brg & 0xff;
872 	up->curregs[R13] = (brg >> 8) & 0xff;
873 	up->curregs[R14] = BRSRC | BRENAB;
874 
875 	/* Character size, stop bits, and parity. */
876 	up->curregs[R3] &= ~RxN_MASK;
877 	up->curregs[R5] &= ~TxN_MASK;
878 	switch (cflag & CSIZE) {
879 	case CS5:
880 		up->curregs[R3] |= Rx5;
881 		up->curregs[R5] |= Tx5;
882 		up->parity_mask = 0x1f;
883 		break;
884 	case CS6:
885 		up->curregs[R3] |= Rx6;
886 		up->curregs[R5] |= Tx6;
887 		up->parity_mask = 0x3f;
888 		break;
889 	case CS7:
890 		up->curregs[R3] |= Rx7;
891 		up->curregs[R5] |= Tx7;
892 		up->parity_mask = 0x7f;
893 		break;
894 	case CS8:
895 	default:
896 		up->curregs[R3] |= Rx8;
897 		up->curregs[R5] |= Tx8;
898 		up->parity_mask = 0xff;
899 		break;
900 	}
901 	up->curregs[R4] &= ~0x0c;
902 	if (cflag & CSTOPB)
903 		up->curregs[R4] |= SB2;
904 	else
905 		up->curregs[R4] |= SB1;
906 	if (cflag & PARENB)
907 		up->curregs[R4] |= PAR_ENAB;
908 	else
909 		up->curregs[R4] &= ~PAR_ENAB;
910 	if (!(cflag & PARODD))
911 		up->curregs[R4] |= PAR_EVEN;
912 	else
913 		up->curregs[R4] &= ~PAR_EVEN;
914 
915 	up->port.read_status_mask = Rx_OVR;
916 	if (iflag & INPCK)
917 		up->port.read_status_mask |= CRC_ERR | PAR_ERR;
918 	if (iflag & (IGNBRK | BRKINT | PARMRK))
919 		up->port.read_status_mask |= BRK_ABRT;
920 
921 	up->port.ignore_status_mask = 0;
922 	if (iflag & IGNPAR)
923 		up->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
924 	if (iflag & IGNBRK) {
925 		up->port.ignore_status_mask |= BRK_ABRT;
926 		if (iflag & IGNPAR)
927 			up->port.ignore_status_mask |= Rx_OVR;
928 	}
929 
930 	if ((cflag & CREAD) == 0)
931 		up->port.ignore_status_mask = 0xff;
932 }
933 
934 /* The port lock is not held.  */
935 static void
936 sunzilog_set_termios(struct uart_port *port, struct ktermios *termios,
937 		     struct ktermios *old)
938 {
939 	struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
940 	unsigned long flags;
941 	int baud, brg;
942 
943 	baud = uart_get_baud_rate(port, termios, old, 1200, 76800);
944 
945 	spin_lock_irqsave(&up->port.lock, flags);
946 
947 	brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
948 
949 	sunzilog_convert_to_zs(up, termios->c_cflag, termios->c_iflag, brg);
950 
951 	if (UART_ENABLE_MS(&up->port, termios->c_cflag))
952 		up->flags |= SUNZILOG_FLAG_MODEM_STATUS;
953 	else
954 		up->flags &= ~SUNZILOG_FLAG_MODEM_STATUS;
955 
956 	up->cflag = termios->c_cflag;
957 
958 	sunzilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(port));
959 
960 	uart_update_timeout(port, termios->c_cflag, baud);
961 
962 	spin_unlock_irqrestore(&up->port.lock, flags);
963 }
964 
965 static const char *sunzilog_type(struct uart_port *port)
966 {
967 	struct uart_sunzilog_port *up = UART_ZILOG(port);
968 
969 	return (up->flags & SUNZILOG_FLAG_ESCC) ? "zs (ESCC)" : "zs";
970 }
971 
972 /* We do not request/release mappings of the registers here, this
973  * happens at early serial probe time.
974  */
975 static void sunzilog_release_port(struct uart_port *port)
976 {
977 }
978 
979 static int sunzilog_request_port(struct uart_port *port)
980 {
981 	return 0;
982 }
983 
984 /* These do not need to do anything interesting either.  */
985 static void sunzilog_config_port(struct uart_port *port, int flags)
986 {
987 }
988 
989 /* We do not support letting the user mess with the divisor, IRQ, etc. */
990 static int sunzilog_verify_port(struct uart_port *port, struct serial_struct *ser)
991 {
992 	return -EINVAL;
993 }
994 
995 #ifdef CONFIG_CONSOLE_POLL
996 static int sunzilog_get_poll_char(struct uart_port *port)
997 {
998 	unsigned char ch, r1;
999 	struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
1000 	struct zilog_channel __iomem *channel
1001 		= ZILOG_CHANNEL_FROM_PORT(&up->port);
1002 
1003 
1004 	r1 = read_zsreg(channel, R1);
1005 	if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
1006 		writeb(ERR_RES, &channel->control);
1007 		ZSDELAY();
1008 		ZS_WSYNC(channel);
1009 	}
1010 
1011 	ch = readb(&channel->control);
1012 	ZSDELAY();
1013 
1014 	/* This funny hack depends upon BRK_ABRT not interfering
1015 	 * with the other bits we care about in R1.
1016 	 */
1017 	if (ch & BRK_ABRT)
1018 		r1 |= BRK_ABRT;
1019 
1020 	if (!(ch & Rx_CH_AV))
1021 		return NO_POLL_CHAR;
1022 
1023 	ch = readb(&channel->data);
1024 	ZSDELAY();
1025 
1026 	ch &= up->parity_mask;
1027 	return ch;
1028 }
1029 
1030 static void sunzilog_put_poll_char(struct uart_port *port,
1031 			unsigned char ch)
1032 {
1033 	struct uart_sunzilog_port *up = (struct uart_sunzilog_port *)port;
1034 
1035 	sunzilog_putchar(&up->port, ch);
1036 }
1037 #endif /* CONFIG_CONSOLE_POLL */
1038 
1039 static struct uart_ops sunzilog_pops = {
1040 	.tx_empty	=	sunzilog_tx_empty,
1041 	.set_mctrl	=	sunzilog_set_mctrl,
1042 	.get_mctrl	=	sunzilog_get_mctrl,
1043 	.stop_tx	=	sunzilog_stop_tx,
1044 	.start_tx	=	sunzilog_start_tx,
1045 	.stop_rx	=	sunzilog_stop_rx,
1046 	.enable_ms	=	sunzilog_enable_ms,
1047 	.break_ctl	=	sunzilog_break_ctl,
1048 	.startup	=	sunzilog_startup,
1049 	.shutdown	=	sunzilog_shutdown,
1050 	.set_termios	=	sunzilog_set_termios,
1051 	.type		=	sunzilog_type,
1052 	.release_port	=	sunzilog_release_port,
1053 	.request_port	=	sunzilog_request_port,
1054 	.config_port	=	sunzilog_config_port,
1055 	.verify_port	=	sunzilog_verify_port,
1056 #ifdef CONFIG_CONSOLE_POLL
1057 	.poll_get_char	=	sunzilog_get_poll_char,
1058 	.poll_put_char	=	sunzilog_put_poll_char,
1059 #endif
1060 };
1061 
1062 static int uart_chip_count;
1063 static struct uart_sunzilog_port *sunzilog_port_table;
1064 static struct zilog_layout __iomem **sunzilog_chip_regs;
1065 
1066 static struct uart_sunzilog_port *sunzilog_irq_chain;
1067 
1068 static struct uart_driver sunzilog_reg = {
1069 	.owner		=	THIS_MODULE,
1070 	.driver_name	=	"sunzilog",
1071 	.dev_name	=	"ttyS",
1072 	.major		=	TTY_MAJOR,
1073 };
1074 
1075 static int __init sunzilog_alloc_tables(int num_sunzilog)
1076 {
1077 	struct uart_sunzilog_port *up;
1078 	unsigned long size;
1079 	int num_channels = num_sunzilog * 2;
1080 	int i;
1081 
1082 	size = num_channels * sizeof(struct uart_sunzilog_port);
1083 	sunzilog_port_table = kzalloc(size, GFP_KERNEL);
1084 	if (!sunzilog_port_table)
1085 		return -ENOMEM;
1086 
1087 	for (i = 0; i < num_channels; i++) {
1088 		up = &sunzilog_port_table[i];
1089 
1090 		spin_lock_init(&up->port.lock);
1091 
1092 		if (i == 0)
1093 			sunzilog_irq_chain = up;
1094 
1095 		if (i < num_channels - 1)
1096 			up->next = up + 1;
1097 		else
1098 			up->next = NULL;
1099 	}
1100 
1101 	size = num_sunzilog * sizeof(struct zilog_layout __iomem *);
1102 	sunzilog_chip_regs = kzalloc(size, GFP_KERNEL);
1103 	if (!sunzilog_chip_regs) {
1104 		kfree(sunzilog_port_table);
1105 		sunzilog_irq_chain = NULL;
1106 		return -ENOMEM;
1107 	}
1108 
1109 	return 0;
1110 }
1111 
1112 static void sunzilog_free_tables(void)
1113 {
1114 	kfree(sunzilog_port_table);
1115 	sunzilog_irq_chain = NULL;
1116 	kfree(sunzilog_chip_regs);
1117 }
1118 
1119 #define ZS_PUT_CHAR_MAX_DELAY	2000	/* 10 ms */
1120 
1121 static void sunzilog_putchar(struct uart_port *port, int ch)
1122 {
1123 	struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
1124 	int loops = ZS_PUT_CHAR_MAX_DELAY;
1125 
1126 	/* This is a timed polling loop so do not switch the explicit
1127 	 * udelay with ZSDELAY as that is a NOP on some platforms.  -DaveM
1128 	 */
1129 	do {
1130 		unsigned char val = readb(&channel->control);
1131 		if (val & Tx_BUF_EMP) {
1132 			ZSDELAY();
1133 			break;
1134 		}
1135 		udelay(5);
1136 	} while (--loops);
1137 
1138 	writeb(ch, &channel->data);
1139 	ZSDELAY();
1140 	ZS_WSYNC(channel);
1141 }
1142 
1143 #ifdef CONFIG_SERIO
1144 
1145 static DEFINE_SPINLOCK(sunzilog_serio_lock);
1146 
1147 static int sunzilog_serio_write(struct serio *serio, unsigned char ch)
1148 {
1149 	struct uart_sunzilog_port *up = serio->port_data;
1150 	unsigned long flags;
1151 
1152 	spin_lock_irqsave(&sunzilog_serio_lock, flags);
1153 
1154 	sunzilog_putchar(&up->port, ch);
1155 
1156 	spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
1157 
1158 	return 0;
1159 }
1160 
1161 static int sunzilog_serio_open(struct serio *serio)
1162 {
1163 	struct uart_sunzilog_port *up = serio->port_data;
1164 	unsigned long flags;
1165 	int ret;
1166 
1167 	spin_lock_irqsave(&sunzilog_serio_lock, flags);
1168 	if (!up->serio_open) {
1169 		up->serio_open = 1;
1170 		ret = 0;
1171 	} else
1172 		ret = -EBUSY;
1173 	spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
1174 
1175 	return ret;
1176 }
1177 
1178 static void sunzilog_serio_close(struct serio *serio)
1179 {
1180 	struct uart_sunzilog_port *up = serio->port_data;
1181 	unsigned long flags;
1182 
1183 	spin_lock_irqsave(&sunzilog_serio_lock, flags);
1184 	up->serio_open = 0;
1185 	spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
1186 }
1187 
1188 #endif /* CONFIG_SERIO */
1189 
1190 #ifdef CONFIG_SERIAL_SUNZILOG_CONSOLE
1191 static void
1192 sunzilog_console_write(struct console *con, const char *s, unsigned int count)
1193 {
1194 	struct uart_sunzilog_port *up = &sunzilog_port_table[con->index];
1195 	unsigned long flags;
1196 	int locked = 1;
1197 
1198 	if (up->port.sysrq || oops_in_progress)
1199 		locked = spin_trylock_irqsave(&up->port.lock, flags);
1200 	else
1201 		spin_lock_irqsave(&up->port.lock, flags);
1202 
1203 	uart_console_write(&up->port, s, count, sunzilog_putchar);
1204 	udelay(2);
1205 
1206 	if (locked)
1207 		spin_unlock_irqrestore(&up->port.lock, flags);
1208 }
1209 
1210 static int __init sunzilog_console_setup(struct console *con, char *options)
1211 {
1212 	struct uart_sunzilog_port *up = &sunzilog_port_table[con->index];
1213 	unsigned long flags;
1214 	int baud, brg;
1215 
1216 	if (up->port.type != PORT_SUNZILOG)
1217 		return -1;
1218 
1219 	printk(KERN_INFO "Console: ttyS%d (SunZilog zs%d)\n",
1220 	       (sunzilog_reg.minor - 64) + con->index, con->index);
1221 
1222 	/* Get firmware console settings.  */
1223 	sunserial_console_termios(con, up->port.dev->of_node);
1224 
1225 	/* Firmware console speed is limited to 150-->38400 baud so
1226 	 * this hackish cflag thing is OK.
1227 	 */
1228 	switch (con->cflag & CBAUD) {
1229 	case B150: baud = 150; break;
1230 	case B300: baud = 300; break;
1231 	case B600: baud = 600; break;
1232 	case B1200: baud = 1200; break;
1233 	case B2400: baud = 2400; break;
1234 	case B4800: baud = 4800; break;
1235 	default: case B9600: baud = 9600; break;
1236 	case B19200: baud = 19200; break;
1237 	case B38400: baud = 38400; break;
1238 	}
1239 
1240 	brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1241 
1242 	spin_lock_irqsave(&up->port.lock, flags);
1243 
1244 	up->curregs[R15] |= BRKIE;
1245 	sunzilog_convert_to_zs(up, con->cflag, 0, brg);
1246 
1247 	sunzilog_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
1248 	__sunzilog_startup(up);
1249 
1250 	spin_unlock_irqrestore(&up->port.lock, flags);
1251 
1252 	return 0;
1253 }
1254 
1255 static struct console sunzilog_console_ops = {
1256 	.name	=	"ttyS",
1257 	.write	=	sunzilog_console_write,
1258 	.device	=	uart_console_device,
1259 	.setup	=	sunzilog_console_setup,
1260 	.flags	=	CON_PRINTBUFFER,
1261 	.index	=	-1,
1262 	.data   =	&sunzilog_reg,
1263 };
1264 
1265 static inline struct console *SUNZILOG_CONSOLE(void)
1266 {
1267 	return &sunzilog_console_ops;
1268 }
1269 
1270 #else
1271 #define SUNZILOG_CONSOLE()	(NULL)
1272 #endif
1273 
1274 static void sunzilog_init_kbdms(struct uart_sunzilog_port *up)
1275 {
1276 	int baud, brg;
1277 
1278 	if (up->flags & SUNZILOG_FLAG_CONS_KEYB) {
1279 		up->cflag = B1200 | CS8 | CLOCAL | CREAD;
1280 		baud = 1200;
1281 	} else {
1282 		up->cflag = B4800 | CS8 | CLOCAL | CREAD;
1283 		baud = 4800;
1284 	}
1285 
1286 	up->curregs[R15] |= BRKIE;
1287 	brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1288 	sunzilog_convert_to_zs(up, up->cflag, 0, brg);
1289 	sunzilog_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
1290 	__sunzilog_startup(up);
1291 }
1292 
1293 #ifdef CONFIG_SERIO
1294 static void sunzilog_register_serio(struct uart_sunzilog_port *up)
1295 {
1296 	struct serio *serio = &up->serio;
1297 
1298 	serio->port_data = up;
1299 
1300 	serio->id.type = SERIO_RS232;
1301 	if (up->flags & SUNZILOG_FLAG_CONS_KEYB) {
1302 		serio->id.proto = SERIO_SUNKBD;
1303 		strlcpy(serio->name, "zskbd", sizeof(serio->name));
1304 	} else {
1305 		serio->id.proto = SERIO_SUN;
1306 		serio->id.extra = 1;
1307 		strlcpy(serio->name, "zsms", sizeof(serio->name));
1308 	}
1309 	strlcpy(serio->phys,
1310 		((up->flags & SUNZILOG_FLAG_CONS_KEYB) ?
1311 		 "zs/serio0" : "zs/serio1"),
1312 		sizeof(serio->phys));
1313 
1314 	serio->write = sunzilog_serio_write;
1315 	serio->open = sunzilog_serio_open;
1316 	serio->close = sunzilog_serio_close;
1317 	serio->dev.parent = up->port.dev;
1318 
1319 	serio_register_port(serio);
1320 }
1321 #endif
1322 
1323 static void sunzilog_init_hw(struct uart_sunzilog_port *up)
1324 {
1325 	struct zilog_channel __iomem *channel;
1326 	unsigned long flags;
1327 	int baud, brg;
1328 
1329 	channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
1330 
1331 	spin_lock_irqsave(&up->port.lock, flags);
1332 	if (ZS_IS_CHANNEL_A(up)) {
1333 		write_zsreg(channel, R9, FHWRES);
1334 		ZSDELAY_LONG();
1335 		(void) read_zsreg(channel, R0);
1336 	}
1337 
1338 	if (up->flags & (SUNZILOG_FLAG_CONS_KEYB |
1339 			 SUNZILOG_FLAG_CONS_MOUSE)) {
1340 		up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
1341 		up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
1342 		up->curregs[R3] = RxENAB | Rx8;
1343 		up->curregs[R5] = TxENAB | Tx8;
1344 		up->curregs[R6] = 0x00; /* SDLC Address */
1345 		up->curregs[R7] = 0x7E; /* SDLC Flag    */
1346 		up->curregs[R9] = NV;
1347 		up->curregs[R7p] = 0x00;
1348 		sunzilog_init_kbdms(up);
1349 		/* Only enable interrupts if an ISR handler available */
1350 		if (up->flags & SUNZILOG_FLAG_ISR_HANDLER)
1351 			up->curregs[R9] |= MIE;
1352 		write_zsreg(channel, R9, up->curregs[R9]);
1353 	} else {
1354 		/* Normal serial TTY. */
1355 		up->parity_mask = 0xff;
1356 		up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
1357 		up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
1358 		up->curregs[R3] = RxENAB | Rx8;
1359 		up->curregs[R5] = TxENAB | Tx8;
1360 		up->curregs[R6] = 0x00; /* SDLC Address */
1361 		up->curregs[R7] = 0x7E; /* SDLC Flag    */
1362 		up->curregs[R9] = NV;
1363 		up->curregs[R10] = NRZ;
1364 		up->curregs[R11] = TCBR | RCBR;
1365 		baud = 9600;
1366 		brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1367 		up->curregs[R12] = (brg & 0xff);
1368 		up->curregs[R13] = (brg >> 8) & 0xff;
1369 		up->curregs[R14] = BRSRC | BRENAB;
1370 		up->curregs[R15] = FIFOEN; /* Use FIFO if on ESCC */
1371 		up->curregs[R7p] = TxFIFO_LVL | RxFIFO_LVL;
1372 		if (__load_zsregs(channel, up->curregs)) {
1373 			up->flags |= SUNZILOG_FLAG_ESCC;
1374 		}
1375 		/* Only enable interrupts if an ISR handler available */
1376 		if (up->flags & SUNZILOG_FLAG_ISR_HANDLER)
1377 			up->curregs[R9] |= MIE;
1378 		write_zsreg(channel, R9, up->curregs[R9]);
1379 	}
1380 
1381 	spin_unlock_irqrestore(&up->port.lock, flags);
1382 
1383 #ifdef CONFIG_SERIO
1384 	if (up->flags & (SUNZILOG_FLAG_CONS_KEYB |
1385 			 SUNZILOG_FLAG_CONS_MOUSE))
1386 		sunzilog_register_serio(up);
1387 #endif
1388 }
1389 
1390 static int zilog_irq;
1391 
1392 static int zs_probe(struct platform_device *op)
1393 {
1394 	static int kbm_inst, uart_inst;
1395 	int inst;
1396 	struct uart_sunzilog_port *up;
1397 	struct zilog_layout __iomem *rp;
1398 	int keyboard_mouse = 0;
1399 	int err;
1400 
1401 	if (of_find_property(op->dev.of_node, "keyboard", NULL))
1402 		keyboard_mouse = 1;
1403 
1404 	/* uarts must come before keyboards/mice */
1405 	if (keyboard_mouse)
1406 		inst = uart_chip_count + kbm_inst;
1407 	else
1408 		inst = uart_inst;
1409 
1410 	sunzilog_chip_regs[inst] = of_ioremap(&op->resource[0], 0,
1411 					      sizeof(struct zilog_layout),
1412 					      "zs");
1413 	if (!sunzilog_chip_regs[inst])
1414 		return -ENOMEM;
1415 
1416 	rp = sunzilog_chip_regs[inst];
1417 
1418 	if (!zilog_irq)
1419 		zilog_irq = op->archdata.irqs[0];
1420 
1421 	up = &sunzilog_port_table[inst * 2];
1422 
1423 	/* Channel A */
1424 	up[0].port.mapbase = op->resource[0].start + 0x00;
1425 	up[0].port.membase = (void __iomem *) &rp->channelA;
1426 	up[0].port.iotype = UPIO_MEM;
1427 	up[0].port.irq = op->archdata.irqs[0];
1428 	up[0].port.uartclk = ZS_CLOCK;
1429 	up[0].port.fifosize = 1;
1430 	up[0].port.ops = &sunzilog_pops;
1431 	up[0].port.type = PORT_SUNZILOG;
1432 	up[0].port.flags = 0;
1433 	up[0].port.line = (inst * 2) + 0;
1434 	up[0].port.dev = &op->dev;
1435 	up[0].flags |= SUNZILOG_FLAG_IS_CHANNEL_A;
1436 	if (keyboard_mouse)
1437 		up[0].flags |= SUNZILOG_FLAG_CONS_KEYB;
1438 	sunzilog_init_hw(&up[0]);
1439 
1440 	/* Channel B */
1441 	up[1].port.mapbase = op->resource[0].start + 0x04;
1442 	up[1].port.membase = (void __iomem *) &rp->channelB;
1443 	up[1].port.iotype = UPIO_MEM;
1444 	up[1].port.irq = op->archdata.irqs[0];
1445 	up[1].port.uartclk = ZS_CLOCK;
1446 	up[1].port.fifosize = 1;
1447 	up[1].port.ops = &sunzilog_pops;
1448 	up[1].port.type = PORT_SUNZILOG;
1449 	up[1].port.flags = 0;
1450 	up[1].port.line = (inst * 2) + 1;
1451 	up[1].port.dev = &op->dev;
1452 	up[1].flags |= 0;
1453 	if (keyboard_mouse)
1454 		up[1].flags |= SUNZILOG_FLAG_CONS_MOUSE;
1455 	sunzilog_init_hw(&up[1]);
1456 
1457 	if (!keyboard_mouse) {
1458 		if (sunserial_console_match(SUNZILOG_CONSOLE(), op->dev.of_node,
1459 					    &sunzilog_reg, up[0].port.line,
1460 					    false))
1461 			up->flags |= SUNZILOG_FLAG_IS_CONS;
1462 		err = uart_add_one_port(&sunzilog_reg, &up[0].port);
1463 		if (err) {
1464 			of_iounmap(&op->resource[0],
1465 				   rp, sizeof(struct zilog_layout));
1466 			return err;
1467 		}
1468 		if (sunserial_console_match(SUNZILOG_CONSOLE(), op->dev.of_node,
1469 					    &sunzilog_reg, up[1].port.line,
1470 					    false))
1471 			up->flags |= SUNZILOG_FLAG_IS_CONS;
1472 		err = uart_add_one_port(&sunzilog_reg, &up[1].port);
1473 		if (err) {
1474 			uart_remove_one_port(&sunzilog_reg, &up[0].port);
1475 			of_iounmap(&op->resource[0],
1476 				   rp, sizeof(struct zilog_layout));
1477 			return err;
1478 		}
1479 		uart_inst++;
1480 	} else {
1481 		printk(KERN_INFO "%s: Keyboard at MMIO 0x%llx (irq = %d) "
1482 		       "is a %s\n",
1483 		       dev_name(&op->dev),
1484 		       (unsigned long long) up[0].port.mapbase,
1485 		       op->archdata.irqs[0], sunzilog_type(&up[0].port));
1486 		printk(KERN_INFO "%s: Mouse at MMIO 0x%llx (irq = %d) "
1487 		       "is a %s\n",
1488 		       dev_name(&op->dev),
1489 		       (unsigned long long) up[1].port.mapbase,
1490 		       op->archdata.irqs[0], sunzilog_type(&up[1].port));
1491 		kbm_inst++;
1492 	}
1493 
1494 	platform_set_drvdata(op, &up[0]);
1495 
1496 	return 0;
1497 }
1498 
1499 static void zs_remove_one(struct uart_sunzilog_port *up)
1500 {
1501 	if (ZS_IS_KEYB(up) || ZS_IS_MOUSE(up)) {
1502 #ifdef CONFIG_SERIO
1503 		serio_unregister_port(&up->serio);
1504 #endif
1505 	} else
1506 		uart_remove_one_port(&sunzilog_reg, &up->port);
1507 }
1508 
1509 static int zs_remove(struct platform_device *op)
1510 {
1511 	struct uart_sunzilog_port *up = platform_get_drvdata(op);
1512 	struct zilog_layout __iomem *regs;
1513 
1514 	zs_remove_one(&up[0]);
1515 	zs_remove_one(&up[1]);
1516 
1517 	regs = sunzilog_chip_regs[up[0].port.line / 2];
1518 	of_iounmap(&op->resource[0], regs, sizeof(struct zilog_layout));
1519 
1520 	return 0;
1521 }
1522 
1523 static const struct of_device_id zs_match[] = {
1524 	{
1525 		.name = "zs",
1526 	},
1527 	{},
1528 };
1529 MODULE_DEVICE_TABLE(of, zs_match);
1530 
1531 static struct platform_driver zs_driver = {
1532 	.driver = {
1533 		.name = "zs",
1534 		.owner = THIS_MODULE,
1535 		.of_match_table = zs_match,
1536 	},
1537 	.probe		= zs_probe,
1538 	.remove		= zs_remove,
1539 };
1540 
1541 static int __init sunzilog_init(void)
1542 {
1543 	struct device_node *dp;
1544 	int err;
1545 	int num_keybms = 0;
1546 	int num_sunzilog = 0;
1547 
1548 	for_each_node_by_name(dp, "zs") {
1549 		num_sunzilog++;
1550 		if (of_find_property(dp, "keyboard", NULL))
1551 			num_keybms++;
1552 	}
1553 
1554 	if (num_sunzilog) {
1555 		err = sunzilog_alloc_tables(num_sunzilog);
1556 		if (err)
1557 			goto out;
1558 
1559 		uart_chip_count = num_sunzilog - num_keybms;
1560 
1561 		err = sunserial_register_minors(&sunzilog_reg,
1562 						uart_chip_count * 2);
1563 		if (err)
1564 			goto out_free_tables;
1565 	}
1566 
1567 	err = platform_driver_register(&zs_driver);
1568 	if (err)
1569 		goto out_unregister_uart;
1570 
1571 	if (zilog_irq) {
1572 		struct uart_sunzilog_port *up = sunzilog_irq_chain;
1573 		err = request_irq(zilog_irq, sunzilog_interrupt, IRQF_SHARED,
1574 				  "zs", sunzilog_irq_chain);
1575 		if (err)
1576 			goto out_unregister_driver;
1577 
1578 		/* Enable Interrupts */
1579 		while (up) {
1580 			struct zilog_channel __iomem *channel;
1581 
1582 			/* printk (KERN_INFO "Enable IRQ for ZILOG Hardware %p\n", up); */
1583 			channel          = ZILOG_CHANNEL_FROM_PORT(&up->port);
1584 			up->flags       |= SUNZILOG_FLAG_ISR_HANDLER;
1585 			up->curregs[R9] |= MIE;
1586 			write_zsreg(channel, R9, up->curregs[R9]);
1587 			up = up->next;
1588 		}
1589 	}
1590 
1591 out:
1592 	return err;
1593 
1594 out_unregister_driver:
1595 	platform_driver_unregister(&zs_driver);
1596 
1597 out_unregister_uart:
1598 	if (num_sunzilog) {
1599 		sunserial_unregister_minors(&sunzilog_reg, num_sunzilog);
1600 		sunzilog_reg.cons = NULL;
1601 	}
1602 
1603 out_free_tables:
1604 	sunzilog_free_tables();
1605 	goto out;
1606 }
1607 
1608 static void __exit sunzilog_exit(void)
1609 {
1610 	platform_driver_unregister(&zs_driver);
1611 
1612 	if (zilog_irq) {
1613 		struct uart_sunzilog_port *up = sunzilog_irq_chain;
1614 
1615 		/* Disable Interrupts */
1616 		while (up) {
1617 			struct zilog_channel __iomem *channel;
1618 
1619 			/* printk (KERN_INFO "Disable IRQ for ZILOG Hardware %p\n", up); */
1620 			channel          = ZILOG_CHANNEL_FROM_PORT(&up->port);
1621 			up->flags       &= ~SUNZILOG_FLAG_ISR_HANDLER;
1622 			up->curregs[R9] &= ~MIE;
1623 			write_zsreg(channel, R9, up->curregs[R9]);
1624 			up = up->next;
1625 		}
1626 
1627 		free_irq(zilog_irq, sunzilog_irq_chain);
1628 		zilog_irq = 0;
1629 	}
1630 
1631 	if (sunzilog_reg.nr) {
1632 		sunserial_unregister_minors(&sunzilog_reg, sunzilog_reg.nr);
1633 		sunzilog_free_tables();
1634 	}
1635 }
1636 
1637 module_init(sunzilog_init);
1638 module_exit(sunzilog_exit);
1639 
1640 MODULE_AUTHOR("David S. Miller");
1641 MODULE_DESCRIPTION("Sun Zilog serial port driver");
1642 MODULE_VERSION("2.0");
1643 MODULE_LICENSE("GPL");
1644