1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * su.c: Small serial driver for keyboard/mouse interface on sparc32/PCI 4 * 5 * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be) 6 * Copyright (C) 1998-1999 Pete Zaitcev (zaitcev@yahoo.com) 7 * 8 * This is mainly a variation of 8250.c, credits go to authors mentioned 9 * therein. In fact this driver should be merged into the generic 8250.c 10 * infrastructure perhaps using a 8250_sparc.c module. 11 * 12 * Fixed to use tty_get_baud_rate(). 13 * Theodore Ts'o <tytso@mit.edu>, 2001-Oct-12 14 * 15 * Converted to new 2.5.x UART layer. 16 * David S. Miller (davem@davemloft.net), 2002-Jul-29 17 */ 18 19 #include <linux/module.h> 20 #include <linux/kernel.h> 21 #include <linux/spinlock.h> 22 #include <linux/errno.h> 23 #include <linux/tty.h> 24 #include <linux/tty_flip.h> 25 #include <linux/major.h> 26 #include <linux/string.h> 27 #include <linux/ptrace.h> 28 #include <linux/ioport.h> 29 #include <linux/circ_buf.h> 30 #include <linux/serial.h> 31 #include <linux/sysrq.h> 32 #include <linux/console.h> 33 #include <linux/slab.h> 34 #ifdef CONFIG_SERIO 35 #include <linux/serio.h> 36 #endif 37 #include <linux/serial_reg.h> 38 #include <linux/init.h> 39 #include <linux/delay.h> 40 #include <linux/of_device.h> 41 42 #include <linux/io.h> 43 #include <asm/irq.h> 44 #include <asm/prom.h> 45 #include <asm/setup.h> 46 47 #include <linux/serial_core.h> 48 #include <linux/sunserialcore.h> 49 50 /* We are on a NS PC87303 clocked with 24.0 MHz, which results 51 * in a UART clock of 1.8462 MHz. 52 */ 53 #define SU_BASE_BAUD (1846200 / 16) 54 55 enum su_type { SU_PORT_NONE, SU_PORT_MS, SU_PORT_KBD, SU_PORT_PORT }; 56 static char *su_typev[] = { "su(???)", "su(mouse)", "su(kbd)", "su(serial)" }; 57 58 struct serial_uart_config { 59 char *name; 60 int dfl_xmit_fifo_size; 61 int flags; 62 }; 63 64 /* 65 * Here we define the default xmit fifo size used for each type of UART. 66 */ 67 static const struct serial_uart_config uart_config[] = { 68 { "unknown", 1, 0 }, 69 { "8250", 1, 0 }, 70 { "16450", 1, 0 }, 71 { "16550", 1, 0 }, 72 { "16550A", 16, UART_CLEAR_FIFO | UART_USE_FIFO }, 73 { "Cirrus", 1, 0 }, 74 { "ST16650", 1, UART_CLEAR_FIFO | UART_STARTECH }, 75 { "ST16650V2", 32, UART_CLEAR_FIFO | UART_USE_FIFO | UART_STARTECH }, 76 { "TI16750", 64, UART_CLEAR_FIFO | UART_USE_FIFO }, 77 { "Startech", 1, 0 }, 78 { "16C950/954", 128, UART_CLEAR_FIFO | UART_USE_FIFO }, 79 { "ST16654", 64, UART_CLEAR_FIFO | UART_USE_FIFO | UART_STARTECH }, 80 { "XR16850", 128, UART_CLEAR_FIFO | UART_USE_FIFO | UART_STARTECH }, 81 { "RSA", 2048, UART_CLEAR_FIFO | UART_USE_FIFO } 82 }; 83 84 struct uart_sunsu_port { 85 struct uart_port port; 86 unsigned char acr; 87 unsigned char ier; 88 unsigned short rev; 89 unsigned char lcr; 90 unsigned int lsr_break_flag; 91 unsigned int cflag; 92 93 /* Probing information. */ 94 enum su_type su_type; 95 unsigned int type_probed; /* XXX Stupid */ 96 unsigned long reg_size; 97 98 #ifdef CONFIG_SERIO 99 struct serio serio; 100 int serio_open; 101 #endif 102 }; 103 104 static unsigned int serial_in(struct uart_sunsu_port *up, int offset) 105 { 106 offset <<= up->port.regshift; 107 108 switch (up->port.iotype) { 109 case UPIO_HUB6: 110 outb(up->port.hub6 - 1 + offset, up->port.iobase); 111 return inb(up->port.iobase + 1); 112 113 case UPIO_MEM: 114 return readb(up->port.membase + offset); 115 116 default: 117 return inb(up->port.iobase + offset); 118 } 119 } 120 121 static void serial_out(struct uart_sunsu_port *up, int offset, int value) 122 { 123 #ifndef CONFIG_SPARC64 124 /* 125 * MrCoffee has weird schematics: IRQ4 & P10(?) pins of SuperIO are 126 * connected with a gate then go to SlavIO. When IRQ4 goes tristated 127 * gate outputs a logical one. Since we use level triggered interrupts 128 * we have lockup and watchdog reset. We cannot mask IRQ because 129 * keyboard shares IRQ with us (Word has it as Bob Smelik's design). 130 * This problem is similar to what Alpha people suffer, see serial.c. 131 */ 132 if (offset == UART_MCR) 133 value |= UART_MCR_OUT2; 134 #endif 135 offset <<= up->port.regshift; 136 137 switch (up->port.iotype) { 138 case UPIO_HUB6: 139 outb(up->port.hub6 - 1 + offset, up->port.iobase); 140 outb(value, up->port.iobase + 1); 141 break; 142 143 case UPIO_MEM: 144 writeb(value, up->port.membase + offset); 145 break; 146 147 default: 148 outb(value, up->port.iobase + offset); 149 } 150 } 151 152 /* 153 * We used to support using pause I/O for certain machines. We 154 * haven't supported this for a while, but just in case it's badly 155 * needed for certain old 386 machines, I've left these #define's 156 * in.... 157 */ 158 #define serial_inp(up, offset) serial_in(up, offset) 159 #define serial_outp(up, offset, value) serial_out(up, offset, value) 160 161 162 /* 163 * For the 16C950 164 */ 165 static void serial_icr_write(struct uart_sunsu_port *up, int offset, int value) 166 { 167 serial_out(up, UART_SCR, offset); 168 serial_out(up, UART_ICR, value); 169 } 170 171 #if 0 /* Unused currently */ 172 static unsigned int serial_icr_read(struct uart_sunsu_port *up, int offset) 173 { 174 unsigned int value; 175 176 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD); 177 serial_out(up, UART_SCR, offset); 178 value = serial_in(up, UART_ICR); 179 serial_icr_write(up, UART_ACR, up->acr); 180 181 return value; 182 } 183 #endif 184 185 #ifdef CONFIG_SERIAL_8250_RSA 186 /* 187 * Attempts to turn on the RSA FIFO. Returns zero on failure. 188 * We set the port uart clock rate if we succeed. 189 */ 190 static int __enable_rsa(struct uart_sunsu_port *up) 191 { 192 unsigned char mode; 193 int result; 194 195 mode = serial_inp(up, UART_RSA_MSR); 196 result = mode & UART_RSA_MSR_FIFO; 197 198 if (!result) { 199 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO); 200 mode = serial_inp(up, UART_RSA_MSR); 201 result = mode & UART_RSA_MSR_FIFO; 202 } 203 204 if (result) 205 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16; 206 207 return result; 208 } 209 210 static void enable_rsa(struct uart_sunsu_port *up) 211 { 212 if (up->port.type == PORT_RSA) { 213 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) { 214 spin_lock_irq(&up->port.lock); 215 __enable_rsa(up); 216 spin_unlock_irq(&up->port.lock); 217 } 218 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) 219 serial_outp(up, UART_RSA_FRR, 0); 220 } 221 } 222 223 /* 224 * Attempts to turn off the RSA FIFO. Returns zero on failure. 225 * It is unknown why interrupts were disabled in here. However, 226 * the caller is expected to preserve this behaviour by grabbing 227 * the spinlock before calling this function. 228 */ 229 static void disable_rsa(struct uart_sunsu_port *up) 230 { 231 unsigned char mode; 232 int result; 233 234 if (up->port.type == PORT_RSA && 235 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) { 236 spin_lock_irq(&up->port.lock); 237 238 mode = serial_inp(up, UART_RSA_MSR); 239 result = !(mode & UART_RSA_MSR_FIFO); 240 241 if (!result) { 242 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO); 243 mode = serial_inp(up, UART_RSA_MSR); 244 result = !(mode & UART_RSA_MSR_FIFO); 245 } 246 247 if (result) 248 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16; 249 spin_unlock_irq(&up->port.lock); 250 } 251 } 252 #endif /* CONFIG_SERIAL_8250_RSA */ 253 254 static inline void __stop_tx(struct uart_sunsu_port *p) 255 { 256 if (p->ier & UART_IER_THRI) { 257 p->ier &= ~UART_IER_THRI; 258 serial_out(p, UART_IER, p->ier); 259 } 260 } 261 262 static void sunsu_stop_tx(struct uart_port *port) 263 { 264 struct uart_sunsu_port *up = 265 container_of(port, struct uart_sunsu_port, port); 266 267 __stop_tx(up); 268 269 /* 270 * We really want to stop the transmitter from sending. 271 */ 272 if (up->port.type == PORT_16C950) { 273 up->acr |= UART_ACR_TXDIS; 274 serial_icr_write(up, UART_ACR, up->acr); 275 } 276 } 277 278 static void sunsu_start_tx(struct uart_port *port) 279 { 280 struct uart_sunsu_port *up = 281 container_of(port, struct uart_sunsu_port, port); 282 283 if (!(up->ier & UART_IER_THRI)) { 284 up->ier |= UART_IER_THRI; 285 serial_out(up, UART_IER, up->ier); 286 } 287 288 /* 289 * Re-enable the transmitter if we disabled it. 290 */ 291 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) { 292 up->acr &= ~UART_ACR_TXDIS; 293 serial_icr_write(up, UART_ACR, up->acr); 294 } 295 } 296 297 static void sunsu_stop_rx(struct uart_port *port) 298 { 299 struct uart_sunsu_port *up = 300 container_of(port, struct uart_sunsu_port, port); 301 302 up->ier &= ~UART_IER_RLSI; 303 up->port.read_status_mask &= ~UART_LSR_DR; 304 serial_out(up, UART_IER, up->ier); 305 } 306 307 static void sunsu_enable_ms(struct uart_port *port) 308 { 309 struct uart_sunsu_port *up = 310 container_of(port, struct uart_sunsu_port, port); 311 unsigned long flags; 312 313 spin_lock_irqsave(&up->port.lock, flags); 314 up->ier |= UART_IER_MSI; 315 serial_out(up, UART_IER, up->ier); 316 spin_unlock_irqrestore(&up->port.lock, flags); 317 } 318 319 static void 320 receive_chars(struct uart_sunsu_port *up, unsigned char *status) 321 { 322 struct tty_port *port = &up->port.state->port; 323 unsigned char ch, flag; 324 int max_count = 256; 325 int saw_console_brk = 0; 326 327 do { 328 ch = serial_inp(up, UART_RX); 329 flag = TTY_NORMAL; 330 up->port.icount.rx++; 331 332 if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE | 333 UART_LSR_FE | UART_LSR_OE))) { 334 /* 335 * For statistics only 336 */ 337 if (*status & UART_LSR_BI) { 338 *status &= ~(UART_LSR_FE | UART_LSR_PE); 339 up->port.icount.brk++; 340 if (up->port.cons != NULL && 341 up->port.line == up->port.cons->index) 342 saw_console_brk = 1; 343 /* 344 * We do the SysRQ and SAK checking 345 * here because otherwise the break 346 * may get masked by ignore_status_mask 347 * or read_status_mask. 348 */ 349 if (uart_handle_break(&up->port)) 350 goto ignore_char; 351 } else if (*status & UART_LSR_PE) 352 up->port.icount.parity++; 353 else if (*status & UART_LSR_FE) 354 up->port.icount.frame++; 355 if (*status & UART_LSR_OE) 356 up->port.icount.overrun++; 357 358 /* 359 * Mask off conditions which should be ingored. 360 */ 361 *status &= up->port.read_status_mask; 362 363 if (up->port.cons != NULL && 364 up->port.line == up->port.cons->index) { 365 /* Recover the break flag from console xmit */ 366 *status |= up->lsr_break_flag; 367 up->lsr_break_flag = 0; 368 } 369 370 if (*status & UART_LSR_BI) { 371 flag = TTY_BREAK; 372 } else if (*status & UART_LSR_PE) 373 flag = TTY_PARITY; 374 else if (*status & UART_LSR_FE) 375 flag = TTY_FRAME; 376 } 377 if (uart_handle_sysrq_char(&up->port, ch)) 378 goto ignore_char; 379 if ((*status & up->port.ignore_status_mask) == 0) 380 tty_insert_flip_char(port, ch, flag); 381 if (*status & UART_LSR_OE) 382 /* 383 * Overrun is special, since it's reported 384 * immediately, and doesn't affect the current 385 * character. 386 */ 387 tty_insert_flip_char(port, 0, TTY_OVERRUN); 388 ignore_char: 389 *status = serial_inp(up, UART_LSR); 390 } while ((*status & UART_LSR_DR) && (max_count-- > 0)); 391 392 if (saw_console_brk) 393 sun_do_break(); 394 } 395 396 static void transmit_chars(struct uart_sunsu_port *up) 397 { 398 struct circ_buf *xmit = &up->port.state->xmit; 399 int count; 400 401 if (up->port.x_char) { 402 serial_outp(up, UART_TX, up->port.x_char); 403 up->port.icount.tx++; 404 up->port.x_char = 0; 405 return; 406 } 407 if (uart_tx_stopped(&up->port)) { 408 sunsu_stop_tx(&up->port); 409 return; 410 } 411 if (uart_circ_empty(xmit)) { 412 __stop_tx(up); 413 return; 414 } 415 416 count = up->port.fifosize; 417 do { 418 serial_out(up, UART_TX, xmit->buf[xmit->tail]); 419 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 420 up->port.icount.tx++; 421 if (uart_circ_empty(xmit)) 422 break; 423 } while (--count > 0); 424 425 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 426 uart_write_wakeup(&up->port); 427 428 if (uart_circ_empty(xmit)) 429 __stop_tx(up); 430 } 431 432 static void check_modem_status(struct uart_sunsu_port *up) 433 { 434 int status; 435 436 status = serial_in(up, UART_MSR); 437 438 if ((status & UART_MSR_ANY_DELTA) == 0) 439 return; 440 441 if (status & UART_MSR_TERI) 442 up->port.icount.rng++; 443 if (status & UART_MSR_DDSR) 444 up->port.icount.dsr++; 445 if (status & UART_MSR_DDCD) 446 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD); 447 if (status & UART_MSR_DCTS) 448 uart_handle_cts_change(&up->port, status & UART_MSR_CTS); 449 450 wake_up_interruptible(&up->port.state->port.delta_msr_wait); 451 } 452 453 static irqreturn_t sunsu_serial_interrupt(int irq, void *dev_id) 454 { 455 struct uart_sunsu_port *up = dev_id; 456 unsigned long flags; 457 unsigned char status; 458 459 spin_lock_irqsave(&up->port.lock, flags); 460 461 do { 462 status = serial_inp(up, UART_LSR); 463 if (status & UART_LSR_DR) 464 receive_chars(up, &status); 465 check_modem_status(up); 466 if (status & UART_LSR_THRE) 467 transmit_chars(up); 468 469 tty_flip_buffer_push(&up->port.state->port); 470 471 } while (!(serial_in(up, UART_IIR) & UART_IIR_NO_INT)); 472 473 spin_unlock_irqrestore(&up->port.lock, flags); 474 475 return IRQ_HANDLED; 476 } 477 478 /* Separate interrupt handling path for keyboard/mouse ports. */ 479 480 static void 481 sunsu_change_speed(struct uart_port *port, unsigned int cflag, 482 unsigned int iflag, unsigned int quot); 483 484 static void sunsu_change_mouse_baud(struct uart_sunsu_port *up) 485 { 486 unsigned int cur_cflag = up->cflag; 487 int quot, new_baud; 488 489 up->cflag &= ~CBAUD; 490 up->cflag |= suncore_mouse_baud_cflag_next(cur_cflag, &new_baud); 491 492 quot = up->port.uartclk / (16 * new_baud); 493 494 sunsu_change_speed(&up->port, up->cflag, 0, quot); 495 } 496 497 static void receive_kbd_ms_chars(struct uart_sunsu_port *up, int is_break) 498 { 499 do { 500 unsigned char ch = serial_inp(up, UART_RX); 501 502 /* Stop-A is handled by drivers/char/keyboard.c now. */ 503 if (up->su_type == SU_PORT_KBD) { 504 #ifdef CONFIG_SERIO 505 serio_interrupt(&up->serio, ch, 0); 506 #endif 507 } else if (up->su_type == SU_PORT_MS) { 508 int ret = suncore_mouse_baud_detection(ch, is_break); 509 510 switch (ret) { 511 case 2: 512 sunsu_change_mouse_baud(up); 513 fallthrough; 514 case 1: 515 break; 516 517 case 0: 518 #ifdef CONFIG_SERIO 519 serio_interrupt(&up->serio, ch, 0); 520 #endif 521 break; 522 } 523 } 524 } while (serial_in(up, UART_LSR) & UART_LSR_DR); 525 } 526 527 static irqreturn_t sunsu_kbd_ms_interrupt(int irq, void *dev_id) 528 { 529 struct uart_sunsu_port *up = dev_id; 530 531 if (!(serial_in(up, UART_IIR) & UART_IIR_NO_INT)) { 532 unsigned char status = serial_inp(up, UART_LSR); 533 534 if ((status & UART_LSR_DR) || (status & UART_LSR_BI)) 535 receive_kbd_ms_chars(up, (status & UART_LSR_BI) != 0); 536 } 537 538 return IRQ_HANDLED; 539 } 540 541 static unsigned int sunsu_tx_empty(struct uart_port *port) 542 { 543 struct uart_sunsu_port *up = 544 container_of(port, struct uart_sunsu_port, port); 545 unsigned long flags; 546 unsigned int ret; 547 548 spin_lock_irqsave(&up->port.lock, flags); 549 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0; 550 spin_unlock_irqrestore(&up->port.lock, flags); 551 552 return ret; 553 } 554 555 static unsigned int sunsu_get_mctrl(struct uart_port *port) 556 { 557 struct uart_sunsu_port *up = 558 container_of(port, struct uart_sunsu_port, port); 559 unsigned char status; 560 unsigned int ret; 561 562 status = serial_in(up, UART_MSR); 563 564 ret = 0; 565 if (status & UART_MSR_DCD) 566 ret |= TIOCM_CAR; 567 if (status & UART_MSR_RI) 568 ret |= TIOCM_RNG; 569 if (status & UART_MSR_DSR) 570 ret |= TIOCM_DSR; 571 if (status & UART_MSR_CTS) 572 ret |= TIOCM_CTS; 573 return ret; 574 } 575 576 static void sunsu_set_mctrl(struct uart_port *port, unsigned int mctrl) 577 { 578 struct uart_sunsu_port *up = 579 container_of(port, struct uart_sunsu_port, port); 580 unsigned char mcr = 0; 581 582 if (mctrl & TIOCM_RTS) 583 mcr |= UART_MCR_RTS; 584 if (mctrl & TIOCM_DTR) 585 mcr |= UART_MCR_DTR; 586 if (mctrl & TIOCM_OUT1) 587 mcr |= UART_MCR_OUT1; 588 if (mctrl & TIOCM_OUT2) 589 mcr |= UART_MCR_OUT2; 590 if (mctrl & TIOCM_LOOP) 591 mcr |= UART_MCR_LOOP; 592 593 serial_out(up, UART_MCR, mcr); 594 } 595 596 static void sunsu_break_ctl(struct uart_port *port, int break_state) 597 { 598 struct uart_sunsu_port *up = 599 container_of(port, struct uart_sunsu_port, port); 600 unsigned long flags; 601 602 spin_lock_irqsave(&up->port.lock, flags); 603 if (break_state == -1) 604 up->lcr |= UART_LCR_SBC; 605 else 606 up->lcr &= ~UART_LCR_SBC; 607 serial_out(up, UART_LCR, up->lcr); 608 spin_unlock_irqrestore(&up->port.lock, flags); 609 } 610 611 static int sunsu_startup(struct uart_port *port) 612 { 613 struct uart_sunsu_port *up = 614 container_of(port, struct uart_sunsu_port, port); 615 unsigned long flags; 616 int retval; 617 618 if (up->port.type == PORT_16C950) { 619 /* Wake up and initialize UART */ 620 up->acr = 0; 621 serial_outp(up, UART_LCR, 0xBF); 622 serial_outp(up, UART_EFR, UART_EFR_ECB); 623 serial_outp(up, UART_IER, 0); 624 serial_outp(up, UART_LCR, 0); 625 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */ 626 serial_outp(up, UART_LCR, 0xBF); 627 serial_outp(up, UART_EFR, UART_EFR_ECB); 628 serial_outp(up, UART_LCR, 0); 629 } 630 631 #ifdef CONFIG_SERIAL_8250_RSA 632 /* 633 * If this is an RSA port, see if we can kick it up to the 634 * higher speed clock. 635 */ 636 enable_rsa(up); 637 #endif 638 639 /* 640 * Clear the FIFO buffers and disable them. 641 * (they will be reenabled in set_termios()) 642 */ 643 if (uart_config[up->port.type].flags & UART_CLEAR_FIFO) { 644 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO); 645 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | 646 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 647 serial_outp(up, UART_FCR, 0); 648 } 649 650 /* 651 * Clear the interrupt registers. 652 */ 653 (void) serial_inp(up, UART_LSR); 654 (void) serial_inp(up, UART_RX); 655 (void) serial_inp(up, UART_IIR); 656 (void) serial_inp(up, UART_MSR); 657 658 /* 659 * At this point, there's no way the LSR could still be 0xff; 660 * if it is, then bail out, because there's likely no UART 661 * here. 662 */ 663 if (!(up->port.flags & UPF_BUGGY_UART) && 664 (serial_inp(up, UART_LSR) == 0xff)) { 665 printk("ttyS%d: LSR safety check engaged!\n", up->port.line); 666 return -ENODEV; 667 } 668 669 if (up->su_type != SU_PORT_PORT) { 670 retval = request_irq(up->port.irq, sunsu_kbd_ms_interrupt, 671 IRQF_SHARED, su_typev[up->su_type], up); 672 } else { 673 retval = request_irq(up->port.irq, sunsu_serial_interrupt, 674 IRQF_SHARED, su_typev[up->su_type], up); 675 } 676 if (retval) { 677 printk("su: Cannot register IRQ %d\n", up->port.irq); 678 return retval; 679 } 680 681 /* 682 * Now, initialize the UART 683 */ 684 serial_outp(up, UART_LCR, UART_LCR_WLEN8); 685 686 spin_lock_irqsave(&up->port.lock, flags); 687 688 up->port.mctrl |= TIOCM_OUT2; 689 690 sunsu_set_mctrl(&up->port, up->port.mctrl); 691 spin_unlock_irqrestore(&up->port.lock, flags); 692 693 /* 694 * Finally, enable interrupts. Note: Modem status interrupts 695 * are set via set_termios(), which will be occurring imminently 696 * anyway, so we don't enable them here. 697 */ 698 up->ier = UART_IER_RLSI | UART_IER_RDI; 699 serial_outp(up, UART_IER, up->ier); 700 701 if (up->port.flags & UPF_FOURPORT) { 702 unsigned int icp; 703 /* 704 * Enable interrupts on the AST Fourport board 705 */ 706 icp = (up->port.iobase & 0xfe0) | 0x01f; 707 outb_p(0x80, icp); 708 (void) inb_p(icp); 709 } 710 711 /* 712 * And clear the interrupt registers again for luck. 713 */ 714 (void) serial_inp(up, UART_LSR); 715 (void) serial_inp(up, UART_RX); 716 (void) serial_inp(up, UART_IIR); 717 (void) serial_inp(up, UART_MSR); 718 719 return 0; 720 } 721 722 static void sunsu_shutdown(struct uart_port *port) 723 { 724 struct uart_sunsu_port *up = 725 container_of(port, struct uart_sunsu_port, port); 726 unsigned long flags; 727 728 /* 729 * Disable interrupts from this port 730 */ 731 up->ier = 0; 732 serial_outp(up, UART_IER, 0); 733 734 spin_lock_irqsave(&up->port.lock, flags); 735 if (up->port.flags & UPF_FOURPORT) { 736 /* reset interrupts on the AST Fourport board */ 737 inb((up->port.iobase & 0xfe0) | 0x1f); 738 up->port.mctrl |= TIOCM_OUT1; 739 } else 740 up->port.mctrl &= ~TIOCM_OUT2; 741 742 sunsu_set_mctrl(&up->port, up->port.mctrl); 743 spin_unlock_irqrestore(&up->port.lock, flags); 744 745 /* 746 * Disable break condition and FIFOs 747 */ 748 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC); 749 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | 750 UART_FCR_CLEAR_RCVR | 751 UART_FCR_CLEAR_XMIT); 752 serial_outp(up, UART_FCR, 0); 753 754 #ifdef CONFIG_SERIAL_8250_RSA 755 /* 756 * Reset the RSA board back to 115kbps compat mode. 757 */ 758 disable_rsa(up); 759 #endif 760 761 /* 762 * Read data port to reset things. 763 */ 764 (void) serial_in(up, UART_RX); 765 766 free_irq(up->port.irq, up); 767 } 768 769 static void 770 sunsu_change_speed(struct uart_port *port, unsigned int cflag, 771 unsigned int iflag, unsigned int quot) 772 { 773 struct uart_sunsu_port *up = 774 container_of(port, struct uart_sunsu_port, port); 775 unsigned char cval, fcr = 0; 776 unsigned long flags; 777 778 switch (cflag & CSIZE) { 779 case CS5: 780 cval = 0x00; 781 break; 782 case CS6: 783 cval = 0x01; 784 break; 785 case CS7: 786 cval = 0x02; 787 break; 788 default: 789 case CS8: 790 cval = 0x03; 791 break; 792 } 793 794 if (cflag & CSTOPB) 795 cval |= 0x04; 796 if (cflag & PARENB) 797 cval |= UART_LCR_PARITY; 798 if (!(cflag & PARODD)) 799 cval |= UART_LCR_EPAR; 800 #ifdef CMSPAR 801 if (cflag & CMSPAR) 802 cval |= UART_LCR_SPAR; 803 #endif 804 805 /* 806 * Work around a bug in the Oxford Semiconductor 952 rev B 807 * chip which causes it to seriously miscalculate baud rates 808 * when DLL is 0. 809 */ 810 if ((quot & 0xff) == 0 && up->port.type == PORT_16C950 && 811 up->rev == 0x5201) 812 quot ++; 813 814 if (uart_config[up->port.type].flags & UART_USE_FIFO) { 815 if ((up->port.uartclk / quot) < (2400 * 16)) 816 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1; 817 #ifdef CONFIG_SERIAL_8250_RSA 818 else if (up->port.type == PORT_RSA) 819 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_14; 820 #endif 821 else 822 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_8; 823 } 824 if (up->port.type == PORT_16750) 825 fcr |= UART_FCR7_64BYTE; 826 827 /* 828 * Ok, we're now changing the port state. Do it with 829 * interrupts disabled. 830 */ 831 spin_lock_irqsave(&up->port.lock, flags); 832 833 /* 834 * Update the per-port timeout. 835 */ 836 uart_update_timeout(port, cflag, (port->uartclk / (16 * quot))); 837 838 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; 839 if (iflag & INPCK) 840 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; 841 if (iflag & (IGNBRK | BRKINT | PARMRK)) 842 up->port.read_status_mask |= UART_LSR_BI; 843 844 /* 845 * Characteres to ignore 846 */ 847 up->port.ignore_status_mask = 0; 848 if (iflag & IGNPAR) 849 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; 850 if (iflag & IGNBRK) { 851 up->port.ignore_status_mask |= UART_LSR_BI; 852 /* 853 * If we're ignoring parity and break indicators, 854 * ignore overruns too (for real raw support). 855 */ 856 if (iflag & IGNPAR) 857 up->port.ignore_status_mask |= UART_LSR_OE; 858 } 859 860 /* 861 * ignore all characters if CREAD is not set 862 */ 863 if ((cflag & CREAD) == 0) 864 up->port.ignore_status_mask |= UART_LSR_DR; 865 866 /* 867 * CTS flow control flag and modem status interrupts 868 */ 869 up->ier &= ~UART_IER_MSI; 870 if (UART_ENABLE_MS(&up->port, cflag)) 871 up->ier |= UART_IER_MSI; 872 873 serial_out(up, UART_IER, up->ier); 874 875 if (uart_config[up->port.type].flags & UART_STARTECH) { 876 serial_outp(up, UART_LCR, 0xBF); 877 serial_outp(up, UART_EFR, cflag & CRTSCTS ? UART_EFR_CTS :0); 878 } 879 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */ 880 serial_outp(up, UART_DLL, quot & 0xff); /* LS of divisor */ 881 serial_outp(up, UART_DLM, quot >> 8); /* MS of divisor */ 882 if (up->port.type == PORT_16750) 883 serial_outp(up, UART_FCR, fcr); /* set fcr */ 884 serial_outp(up, UART_LCR, cval); /* reset DLAB */ 885 up->lcr = cval; /* Save LCR */ 886 if (up->port.type != PORT_16750) { 887 if (fcr & UART_FCR_ENABLE_FIFO) { 888 /* emulated UARTs (Lucent Venus 167x) need two steps */ 889 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO); 890 } 891 serial_outp(up, UART_FCR, fcr); /* set fcr */ 892 } 893 894 up->cflag = cflag; 895 896 spin_unlock_irqrestore(&up->port.lock, flags); 897 } 898 899 static void 900 sunsu_set_termios(struct uart_port *port, struct ktermios *termios, 901 struct ktermios *old) 902 { 903 unsigned int baud, quot; 904 905 /* 906 * Ask the core to calculate the divisor for us. 907 */ 908 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); 909 quot = uart_get_divisor(port, baud); 910 911 sunsu_change_speed(port, termios->c_cflag, termios->c_iflag, quot); 912 } 913 914 static void sunsu_release_port(struct uart_port *port) 915 { 916 } 917 918 static int sunsu_request_port(struct uart_port *port) 919 { 920 return 0; 921 } 922 923 static void sunsu_config_port(struct uart_port *port, int flags) 924 { 925 struct uart_sunsu_port *up = 926 container_of(port, struct uart_sunsu_port, port); 927 928 if (flags & UART_CONFIG_TYPE) { 929 /* 930 * We are supposed to call autoconfig here, but this requires 931 * splitting all the OBP probing crap from the UART probing. 932 * We'll do it when we kill sunsu.c altogether. 933 */ 934 port->type = up->type_probed; /* XXX */ 935 } 936 } 937 938 static int 939 sunsu_verify_port(struct uart_port *port, struct serial_struct *ser) 940 { 941 return -EINVAL; 942 } 943 944 static const char * 945 sunsu_type(struct uart_port *port) 946 { 947 int type = port->type; 948 949 if (type >= ARRAY_SIZE(uart_config)) 950 type = 0; 951 return uart_config[type].name; 952 } 953 954 static const struct uart_ops sunsu_pops = { 955 .tx_empty = sunsu_tx_empty, 956 .set_mctrl = sunsu_set_mctrl, 957 .get_mctrl = sunsu_get_mctrl, 958 .stop_tx = sunsu_stop_tx, 959 .start_tx = sunsu_start_tx, 960 .stop_rx = sunsu_stop_rx, 961 .enable_ms = sunsu_enable_ms, 962 .break_ctl = sunsu_break_ctl, 963 .startup = sunsu_startup, 964 .shutdown = sunsu_shutdown, 965 .set_termios = sunsu_set_termios, 966 .type = sunsu_type, 967 .release_port = sunsu_release_port, 968 .request_port = sunsu_request_port, 969 .config_port = sunsu_config_port, 970 .verify_port = sunsu_verify_port, 971 }; 972 973 #define UART_NR 4 974 975 static struct uart_sunsu_port sunsu_ports[UART_NR]; 976 static int nr_inst; /* Number of already registered ports */ 977 978 #ifdef CONFIG_SERIO 979 980 static DEFINE_SPINLOCK(sunsu_serio_lock); 981 982 static int sunsu_serio_write(struct serio *serio, unsigned char ch) 983 { 984 struct uart_sunsu_port *up = serio->port_data; 985 unsigned long flags; 986 int lsr; 987 988 spin_lock_irqsave(&sunsu_serio_lock, flags); 989 990 do { 991 lsr = serial_in(up, UART_LSR); 992 } while (!(lsr & UART_LSR_THRE)); 993 994 /* Send the character out. */ 995 serial_out(up, UART_TX, ch); 996 997 spin_unlock_irqrestore(&sunsu_serio_lock, flags); 998 999 return 0; 1000 } 1001 1002 static int sunsu_serio_open(struct serio *serio) 1003 { 1004 struct uart_sunsu_port *up = serio->port_data; 1005 unsigned long flags; 1006 int ret; 1007 1008 spin_lock_irqsave(&sunsu_serio_lock, flags); 1009 if (!up->serio_open) { 1010 up->serio_open = 1; 1011 ret = 0; 1012 } else 1013 ret = -EBUSY; 1014 spin_unlock_irqrestore(&sunsu_serio_lock, flags); 1015 1016 return ret; 1017 } 1018 1019 static void sunsu_serio_close(struct serio *serio) 1020 { 1021 struct uart_sunsu_port *up = serio->port_data; 1022 unsigned long flags; 1023 1024 spin_lock_irqsave(&sunsu_serio_lock, flags); 1025 up->serio_open = 0; 1026 spin_unlock_irqrestore(&sunsu_serio_lock, flags); 1027 } 1028 1029 #endif /* CONFIG_SERIO */ 1030 1031 static void sunsu_autoconfig(struct uart_sunsu_port *up) 1032 { 1033 unsigned char status1, status2, scratch, scratch2, scratch3; 1034 unsigned char save_lcr, save_mcr; 1035 unsigned long flags; 1036 1037 if (up->su_type == SU_PORT_NONE) 1038 return; 1039 1040 up->type_probed = PORT_UNKNOWN; 1041 up->port.iotype = UPIO_MEM; 1042 1043 spin_lock_irqsave(&up->port.lock, flags); 1044 1045 if (!(up->port.flags & UPF_BUGGY_UART)) { 1046 /* 1047 * Do a simple existence test first; if we fail this, there's 1048 * no point trying anything else. 1049 * 1050 * 0x80 is used as a nonsense port to prevent against false 1051 * positives due to ISA bus float. The assumption is that 1052 * 0x80 is a non-existent port; which should be safe since 1053 * include/asm/io.h also makes this assumption. 1054 */ 1055 scratch = serial_inp(up, UART_IER); 1056 serial_outp(up, UART_IER, 0); 1057 #ifdef __i386__ 1058 outb(0xff, 0x080); 1059 #endif 1060 scratch2 = serial_inp(up, UART_IER); 1061 serial_outp(up, UART_IER, 0x0f); 1062 #ifdef __i386__ 1063 outb(0, 0x080); 1064 #endif 1065 scratch3 = serial_inp(up, UART_IER); 1066 serial_outp(up, UART_IER, scratch); 1067 if (scratch2 != 0 || scratch3 != 0x0F) 1068 goto out; /* We failed; there's nothing here */ 1069 } 1070 1071 save_mcr = serial_in(up, UART_MCR); 1072 save_lcr = serial_in(up, UART_LCR); 1073 1074 /* 1075 * Check to see if a UART is really there. Certain broken 1076 * internal modems based on the Rockwell chipset fail this 1077 * test, because they apparently don't implement the loopback 1078 * test mode. So this test is skipped on the COM 1 through 1079 * COM 4 ports. This *should* be safe, since no board 1080 * manufacturer would be stupid enough to design a board 1081 * that conflicts with COM 1-4 --- we hope! 1082 */ 1083 if (!(up->port.flags & UPF_SKIP_TEST)) { 1084 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A); 1085 status1 = serial_inp(up, UART_MSR) & 0xF0; 1086 serial_outp(up, UART_MCR, save_mcr); 1087 if (status1 != 0x90) 1088 goto out; /* We failed loopback test */ 1089 } 1090 serial_outp(up, UART_LCR, 0xBF); /* set up for StarTech test */ 1091 serial_outp(up, UART_EFR, 0); /* EFR is the same as FCR */ 1092 serial_outp(up, UART_LCR, 0); 1093 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO); 1094 scratch = serial_in(up, UART_IIR) >> 6; 1095 switch (scratch) { 1096 case 0: 1097 up->port.type = PORT_16450; 1098 break; 1099 case 1: 1100 up->port.type = PORT_UNKNOWN; 1101 break; 1102 case 2: 1103 up->port.type = PORT_16550; 1104 break; 1105 case 3: 1106 up->port.type = PORT_16550A; 1107 break; 1108 } 1109 if (up->port.type == PORT_16550A) { 1110 /* Check for Startech UART's */ 1111 serial_outp(up, UART_LCR, UART_LCR_DLAB); 1112 if (serial_in(up, UART_EFR) == 0) { 1113 up->port.type = PORT_16650; 1114 } else { 1115 serial_outp(up, UART_LCR, 0xBF); 1116 if (serial_in(up, UART_EFR) == 0) 1117 up->port.type = PORT_16650V2; 1118 } 1119 } 1120 if (up->port.type == PORT_16550A) { 1121 /* Check for TI 16750 */ 1122 serial_outp(up, UART_LCR, save_lcr | UART_LCR_DLAB); 1123 serial_outp(up, UART_FCR, 1124 UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE); 1125 scratch = serial_in(up, UART_IIR) >> 5; 1126 if (scratch == 7) { 1127 /* 1128 * If this is a 16750, and not a cheap UART 1129 * clone, then it should only go into 64 byte 1130 * mode if the UART_FCR7_64BYTE bit was set 1131 * while UART_LCR_DLAB was latched. 1132 */ 1133 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO); 1134 serial_outp(up, UART_LCR, 0); 1135 serial_outp(up, UART_FCR, 1136 UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE); 1137 scratch = serial_in(up, UART_IIR) >> 5; 1138 if (scratch == 6) 1139 up->port.type = PORT_16750; 1140 } 1141 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO); 1142 } 1143 serial_outp(up, UART_LCR, save_lcr); 1144 if (up->port.type == PORT_16450) { 1145 scratch = serial_in(up, UART_SCR); 1146 serial_outp(up, UART_SCR, 0xa5); 1147 status1 = serial_in(up, UART_SCR); 1148 serial_outp(up, UART_SCR, 0x5a); 1149 status2 = serial_in(up, UART_SCR); 1150 serial_outp(up, UART_SCR, scratch); 1151 1152 if ((status1 != 0xa5) || (status2 != 0x5a)) 1153 up->port.type = PORT_8250; 1154 } 1155 1156 up->port.fifosize = uart_config[up->port.type].dfl_xmit_fifo_size; 1157 1158 if (up->port.type == PORT_UNKNOWN) 1159 goto out; 1160 up->type_probed = up->port.type; /* XXX */ 1161 1162 /* 1163 * Reset the UART. 1164 */ 1165 #ifdef CONFIG_SERIAL_8250_RSA 1166 if (up->port.type == PORT_RSA) 1167 serial_outp(up, UART_RSA_FRR, 0); 1168 #endif 1169 serial_outp(up, UART_MCR, save_mcr); 1170 serial_outp(up, UART_FCR, (UART_FCR_ENABLE_FIFO | 1171 UART_FCR_CLEAR_RCVR | 1172 UART_FCR_CLEAR_XMIT)); 1173 serial_outp(up, UART_FCR, 0); 1174 (void)serial_in(up, UART_RX); 1175 serial_outp(up, UART_IER, 0); 1176 1177 out: 1178 spin_unlock_irqrestore(&up->port.lock, flags); 1179 } 1180 1181 static struct uart_driver sunsu_reg = { 1182 .owner = THIS_MODULE, 1183 .driver_name = "sunsu", 1184 .dev_name = "ttyS", 1185 .major = TTY_MAJOR, 1186 }; 1187 1188 static int sunsu_kbd_ms_init(struct uart_sunsu_port *up) 1189 { 1190 int quot, baud; 1191 #ifdef CONFIG_SERIO 1192 struct serio *serio; 1193 #endif 1194 1195 if (up->su_type == SU_PORT_KBD) { 1196 up->cflag = B1200 | CS8 | CLOCAL | CREAD; 1197 baud = 1200; 1198 } else { 1199 up->cflag = B4800 | CS8 | CLOCAL | CREAD; 1200 baud = 4800; 1201 } 1202 quot = up->port.uartclk / (16 * baud); 1203 1204 sunsu_autoconfig(up); 1205 if (up->port.type == PORT_UNKNOWN) 1206 return -ENODEV; 1207 1208 printk("%pOF: %s port at %llx, irq %u\n", 1209 up->port.dev->of_node, 1210 (up->su_type == SU_PORT_KBD) ? "Keyboard" : "Mouse", 1211 (unsigned long long) up->port.mapbase, 1212 up->port.irq); 1213 1214 #ifdef CONFIG_SERIO 1215 serio = &up->serio; 1216 serio->port_data = up; 1217 1218 serio->id.type = SERIO_RS232; 1219 if (up->su_type == SU_PORT_KBD) { 1220 serio->id.proto = SERIO_SUNKBD; 1221 strlcpy(serio->name, "sukbd", sizeof(serio->name)); 1222 } else { 1223 serio->id.proto = SERIO_SUN; 1224 serio->id.extra = 1; 1225 strlcpy(serio->name, "sums", sizeof(serio->name)); 1226 } 1227 strlcpy(serio->phys, 1228 (!(up->port.line & 1) ? "su/serio0" : "su/serio1"), 1229 sizeof(serio->phys)); 1230 1231 serio->write = sunsu_serio_write; 1232 serio->open = sunsu_serio_open; 1233 serio->close = sunsu_serio_close; 1234 serio->dev.parent = up->port.dev; 1235 1236 serio_register_port(serio); 1237 #endif 1238 1239 sunsu_change_speed(&up->port, up->cflag, 0, quot); 1240 1241 sunsu_startup(&up->port); 1242 return 0; 1243 } 1244 1245 /* 1246 * ------------------------------------------------------------ 1247 * Serial console driver 1248 * ------------------------------------------------------------ 1249 */ 1250 1251 #ifdef CONFIG_SERIAL_SUNSU_CONSOLE 1252 1253 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) 1254 1255 /* 1256 * Wait for transmitter & holding register to empty 1257 */ 1258 static void wait_for_xmitr(struct uart_sunsu_port *up) 1259 { 1260 unsigned int status, tmout = 10000; 1261 1262 /* Wait up to 10ms for the character(s) to be sent. */ 1263 do { 1264 status = serial_in(up, UART_LSR); 1265 1266 if (status & UART_LSR_BI) 1267 up->lsr_break_flag = UART_LSR_BI; 1268 1269 if (--tmout == 0) 1270 break; 1271 udelay(1); 1272 } while ((status & BOTH_EMPTY) != BOTH_EMPTY); 1273 1274 /* Wait up to 1s for flow control if necessary */ 1275 if (up->port.flags & UPF_CONS_FLOW) { 1276 tmout = 1000000; 1277 while (--tmout && 1278 ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0)) 1279 udelay(1); 1280 } 1281 } 1282 1283 static void sunsu_console_putchar(struct uart_port *port, int ch) 1284 { 1285 struct uart_sunsu_port *up = 1286 container_of(port, struct uart_sunsu_port, port); 1287 1288 wait_for_xmitr(up); 1289 serial_out(up, UART_TX, ch); 1290 } 1291 1292 /* 1293 * Print a string to the serial port trying not to disturb 1294 * any possible real use of the port... 1295 */ 1296 static void sunsu_console_write(struct console *co, const char *s, 1297 unsigned int count) 1298 { 1299 struct uart_sunsu_port *up = &sunsu_ports[co->index]; 1300 unsigned long flags; 1301 unsigned int ier; 1302 int locked = 1; 1303 1304 if (up->port.sysrq || oops_in_progress) 1305 locked = spin_trylock_irqsave(&up->port.lock, flags); 1306 else 1307 spin_lock_irqsave(&up->port.lock, flags); 1308 1309 /* 1310 * First save the UER then disable the interrupts 1311 */ 1312 ier = serial_in(up, UART_IER); 1313 serial_out(up, UART_IER, 0); 1314 1315 uart_console_write(&up->port, s, count, sunsu_console_putchar); 1316 1317 /* 1318 * Finally, wait for transmitter to become empty 1319 * and restore the IER 1320 */ 1321 wait_for_xmitr(up); 1322 serial_out(up, UART_IER, ier); 1323 1324 if (locked) 1325 spin_unlock_irqrestore(&up->port.lock, flags); 1326 } 1327 1328 /* 1329 * Setup initial baud/bits/parity. We do two things here: 1330 * - construct a cflag setting for the first su_open() 1331 * - initialize the serial port 1332 * Return non-zero if we didn't find a serial port. 1333 */ 1334 static int __init sunsu_console_setup(struct console *co, char *options) 1335 { 1336 static struct ktermios dummy; 1337 struct ktermios termios; 1338 struct uart_port *port; 1339 1340 printk("Console: ttyS%d (SU)\n", 1341 (sunsu_reg.minor - 64) + co->index); 1342 1343 if (co->index > nr_inst) 1344 return -ENODEV; 1345 port = &sunsu_ports[co->index].port; 1346 1347 /* 1348 * Temporary fix. 1349 */ 1350 spin_lock_init(&port->lock); 1351 1352 /* Get firmware console settings. */ 1353 sunserial_console_termios(co, port->dev->of_node); 1354 1355 memset(&termios, 0, sizeof(struct ktermios)); 1356 termios.c_cflag = co->cflag; 1357 port->mctrl |= TIOCM_DTR; 1358 port->ops->set_termios(port, &termios, &dummy); 1359 1360 return 0; 1361 } 1362 1363 static struct console sunsu_console = { 1364 .name = "ttyS", 1365 .write = sunsu_console_write, 1366 .device = uart_console_device, 1367 .setup = sunsu_console_setup, 1368 .flags = CON_PRINTBUFFER, 1369 .index = -1, 1370 .data = &sunsu_reg, 1371 }; 1372 1373 /* 1374 * Register console. 1375 */ 1376 1377 static inline struct console *SUNSU_CONSOLE(void) 1378 { 1379 return &sunsu_console; 1380 } 1381 #else 1382 #define SUNSU_CONSOLE() (NULL) 1383 #define sunsu_serial_console_init() do { } while (0) 1384 #endif 1385 1386 static enum su_type su_get_type(struct device_node *dp) 1387 { 1388 struct device_node *ap = of_find_node_by_path("/aliases"); 1389 enum su_type rc = SU_PORT_PORT; 1390 1391 if (ap) { 1392 const char *keyb = of_get_property(ap, "keyboard", NULL); 1393 const char *ms = of_get_property(ap, "mouse", NULL); 1394 struct device_node *match; 1395 1396 if (keyb) { 1397 match = of_find_node_by_path(keyb); 1398 1399 /* 1400 * The pointer is used as an identifier not 1401 * as a pointer, we can drop the refcount on 1402 * the of__node immediately after getting it. 1403 */ 1404 of_node_put(match); 1405 1406 if (dp == match) { 1407 rc = SU_PORT_KBD; 1408 goto out; 1409 } 1410 } 1411 if (ms) { 1412 match = of_find_node_by_path(ms); 1413 1414 of_node_put(match); 1415 1416 if (dp == match) { 1417 rc = SU_PORT_MS; 1418 goto out; 1419 } 1420 } 1421 } 1422 1423 out: 1424 of_node_put(ap); 1425 return rc; 1426 } 1427 1428 static int su_probe(struct platform_device *op) 1429 { 1430 struct device_node *dp = op->dev.of_node; 1431 struct uart_sunsu_port *up; 1432 struct resource *rp; 1433 enum su_type type; 1434 bool ignore_line; 1435 int err; 1436 1437 type = su_get_type(dp); 1438 if (type == SU_PORT_PORT) { 1439 if (nr_inst >= UART_NR) 1440 return -EINVAL; 1441 up = &sunsu_ports[nr_inst]; 1442 } else { 1443 up = kzalloc(sizeof(*up), GFP_KERNEL); 1444 if (!up) 1445 return -ENOMEM; 1446 } 1447 1448 up->port.line = nr_inst; 1449 1450 spin_lock_init(&up->port.lock); 1451 1452 up->su_type = type; 1453 1454 rp = &op->resource[0]; 1455 up->port.mapbase = rp->start; 1456 up->reg_size = resource_size(rp); 1457 up->port.membase = of_ioremap(rp, 0, up->reg_size, "su"); 1458 if (!up->port.membase) { 1459 if (type != SU_PORT_PORT) 1460 kfree(up); 1461 return -ENOMEM; 1462 } 1463 1464 up->port.irq = op->archdata.irqs[0]; 1465 1466 up->port.dev = &op->dev; 1467 1468 up->port.type = PORT_UNKNOWN; 1469 up->port.uartclk = (SU_BASE_BAUD * 16); 1470 up->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SUNSU_CONSOLE); 1471 1472 err = 0; 1473 if (up->su_type == SU_PORT_KBD || up->su_type == SU_PORT_MS) { 1474 err = sunsu_kbd_ms_init(up); 1475 if (err) { 1476 of_iounmap(&op->resource[0], 1477 up->port.membase, up->reg_size); 1478 kfree(up); 1479 return err; 1480 } 1481 platform_set_drvdata(op, up); 1482 1483 nr_inst++; 1484 1485 return 0; 1486 } 1487 1488 up->port.flags |= UPF_BOOT_AUTOCONF; 1489 1490 sunsu_autoconfig(up); 1491 1492 err = -ENODEV; 1493 if (up->port.type == PORT_UNKNOWN) 1494 goto out_unmap; 1495 1496 up->port.ops = &sunsu_pops; 1497 1498 ignore_line = false; 1499 if (of_node_name_eq(dp, "rsc-console") || 1500 of_node_name_eq(dp, "lom-console")) 1501 ignore_line = true; 1502 1503 sunserial_console_match(SUNSU_CONSOLE(), dp, 1504 &sunsu_reg, up->port.line, 1505 ignore_line); 1506 err = uart_add_one_port(&sunsu_reg, &up->port); 1507 if (err) 1508 goto out_unmap; 1509 1510 platform_set_drvdata(op, up); 1511 1512 nr_inst++; 1513 1514 return 0; 1515 1516 out_unmap: 1517 of_iounmap(&op->resource[0], up->port.membase, up->reg_size); 1518 kfree(up); 1519 return err; 1520 } 1521 1522 static int su_remove(struct platform_device *op) 1523 { 1524 struct uart_sunsu_port *up = platform_get_drvdata(op); 1525 bool kbdms = false; 1526 1527 if (up->su_type == SU_PORT_MS || 1528 up->su_type == SU_PORT_KBD) 1529 kbdms = true; 1530 1531 if (kbdms) { 1532 #ifdef CONFIG_SERIO 1533 serio_unregister_port(&up->serio); 1534 #endif 1535 } else if (up->port.type != PORT_UNKNOWN) 1536 uart_remove_one_port(&sunsu_reg, &up->port); 1537 1538 if (up->port.membase) 1539 of_iounmap(&op->resource[0], up->port.membase, up->reg_size); 1540 1541 if (kbdms) 1542 kfree(up); 1543 1544 return 0; 1545 } 1546 1547 static const struct of_device_id su_match[] = { 1548 { 1549 .name = "su", 1550 }, 1551 { 1552 .name = "su_pnp", 1553 }, 1554 { 1555 .name = "serial", 1556 .compatible = "su", 1557 }, 1558 { 1559 .type = "serial", 1560 .compatible = "su", 1561 }, 1562 {}, 1563 }; 1564 MODULE_DEVICE_TABLE(of, su_match); 1565 1566 static struct platform_driver su_driver = { 1567 .driver = { 1568 .name = "su", 1569 .of_match_table = su_match, 1570 }, 1571 .probe = su_probe, 1572 .remove = su_remove, 1573 }; 1574 1575 static int __init sunsu_init(void) 1576 { 1577 struct device_node *dp; 1578 int err; 1579 int num_uart = 0; 1580 1581 for_each_node_by_name(dp, "su") { 1582 if (su_get_type(dp) == SU_PORT_PORT) 1583 num_uart++; 1584 } 1585 for_each_node_by_name(dp, "su_pnp") { 1586 if (su_get_type(dp) == SU_PORT_PORT) 1587 num_uart++; 1588 } 1589 for_each_node_by_name(dp, "serial") { 1590 if (of_device_is_compatible(dp, "su")) { 1591 if (su_get_type(dp) == SU_PORT_PORT) 1592 num_uart++; 1593 } 1594 } 1595 for_each_node_by_type(dp, "serial") { 1596 if (of_device_is_compatible(dp, "su")) { 1597 if (su_get_type(dp) == SU_PORT_PORT) 1598 num_uart++; 1599 } 1600 } 1601 1602 if (num_uart) { 1603 err = sunserial_register_minors(&sunsu_reg, num_uart); 1604 if (err) 1605 return err; 1606 } 1607 1608 err = platform_driver_register(&su_driver); 1609 if (err && num_uart) 1610 sunserial_unregister_minors(&sunsu_reg, num_uart); 1611 1612 return err; 1613 } 1614 1615 static void __exit sunsu_exit(void) 1616 { 1617 platform_driver_unregister(&su_driver); 1618 if (sunsu_reg.nr) 1619 sunserial_unregister_minors(&sunsu_reg, sunsu_reg.nr); 1620 } 1621 1622 module_init(sunsu_init); 1623 module_exit(sunsu_exit); 1624 1625 MODULE_AUTHOR("Eddie C. Dost, Peter Zaitcev, and David S. Miller"); 1626 MODULE_DESCRIPTION("Sun SU serial port driver"); 1627 MODULE_VERSION("2.0"); 1628 MODULE_LICENSE("GPL"); 1629