1 // SPDX-License-Identifier: GPL-2.0 2 /* sunsab.c: ASYNC Driver for the SIEMENS SAB82532 DUSCC. 3 * 4 * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be) 5 * Copyright (C) 2002, 2006 David S. Miller (davem@davemloft.net) 6 * 7 * Rewrote buffer handling to use CIRC(Circular Buffer) macros. 8 * Maxim Krasnyanskiy <maxk@qualcomm.com> 9 * 10 * Fixed to use tty_get_baud_rate, and to allow for arbitrary baud 11 * rates to be programmed into the UART. Also eliminated a lot of 12 * duplicated code in the console setup. 13 * Theodore Ts'o <tytso@mit.edu>, 2001-Oct-12 14 * 15 * Ported to new 2.5.x UART layer. 16 * David S. Miller <davem@davemloft.net> 17 */ 18 19 #include <linux/module.h> 20 #include <linux/kernel.h> 21 #include <linux/errno.h> 22 #include <linux/tty.h> 23 #include <linux/tty_flip.h> 24 #include <linux/major.h> 25 #include <linux/string.h> 26 #include <linux/ptrace.h> 27 #include <linux/ioport.h> 28 #include <linux/circ_buf.h> 29 #include <linux/serial.h> 30 #include <linux/sysrq.h> 31 #include <linux/console.h> 32 #include <linux/spinlock.h> 33 #include <linux/slab.h> 34 #include <linux/delay.h> 35 #include <linux/init.h> 36 #include <linux/of_device.h> 37 38 #include <asm/io.h> 39 #include <asm/irq.h> 40 #include <asm/prom.h> 41 #include <asm/setup.h> 42 43 #include <linux/serial_core.h> 44 #include <linux/sunserialcore.h> 45 46 #include "sunsab.h" 47 48 struct uart_sunsab_port { 49 struct uart_port port; /* Generic UART port */ 50 union sab82532_async_regs __iomem *regs; /* Chip registers */ 51 unsigned long irqflags; /* IRQ state flags */ 52 int dsr; /* Current DSR state */ 53 unsigned int cec_timeout; /* Chip poll timeout... */ 54 unsigned int tec_timeout; /* likewise */ 55 unsigned char interrupt_mask0;/* ISR0 masking */ 56 unsigned char interrupt_mask1;/* ISR1 masking */ 57 unsigned char pvr_dtr_bit; /* Which PVR bit is DTR */ 58 unsigned char pvr_dsr_bit; /* Which PVR bit is DSR */ 59 unsigned int gis_shift; 60 int type; /* SAB82532 version */ 61 62 /* Setting configuration bits while the transmitter is active 63 * can cause garbage characters to get emitted by the chip. 64 * Therefore, we cache such writes here and do the real register 65 * write the next time the transmitter becomes idle. 66 */ 67 unsigned int cached_ebrg; 68 unsigned char cached_mode; 69 unsigned char cached_pvr; 70 unsigned char cached_dafo; 71 }; 72 73 /* 74 * This assumes you have a 29.4912 MHz clock for your UART. 75 */ 76 #define SAB_BASE_BAUD ( 29491200 / 16 ) 77 78 static char *sab82532_version[16] = { 79 "V1.0", "V2.0", "V3.2", "V(0x03)", 80 "V(0x04)", "V(0x05)", "V(0x06)", "V(0x07)", 81 "V(0x08)", "V(0x09)", "V(0x0a)", "V(0x0b)", 82 "V(0x0c)", "V(0x0d)", "V(0x0e)", "V(0x0f)" 83 }; 84 85 #define SAB82532_MAX_TEC_TIMEOUT 200000 /* 1 character time (at 50 baud) */ 86 #define SAB82532_MAX_CEC_TIMEOUT 50000 /* 2.5 TX CLKs (at 50 baud) */ 87 88 #define SAB82532_RECV_FIFO_SIZE 32 /* Standard async fifo sizes */ 89 #define SAB82532_XMIT_FIFO_SIZE 32 90 91 static __inline__ void sunsab_tec_wait(struct uart_sunsab_port *up) 92 { 93 int timeout = up->tec_timeout; 94 95 while ((readb(&up->regs->r.star) & SAB82532_STAR_TEC) && --timeout) 96 udelay(1); 97 } 98 99 static __inline__ void sunsab_cec_wait(struct uart_sunsab_port *up) 100 { 101 int timeout = up->cec_timeout; 102 103 while ((readb(&up->regs->r.star) & SAB82532_STAR_CEC) && --timeout) 104 udelay(1); 105 } 106 107 static struct tty_port * 108 receive_chars(struct uart_sunsab_port *up, 109 union sab82532_irq_status *stat) 110 { 111 struct tty_port *port = NULL; 112 unsigned char buf[32]; 113 int saw_console_brk = 0; 114 int free_fifo = 0; 115 int count = 0; 116 int i; 117 118 if (up->port.state != NULL) /* Unopened serial console */ 119 port = &up->port.state->port; 120 121 /* Read number of BYTES (Character + Status) available. */ 122 if (stat->sreg.isr0 & SAB82532_ISR0_RPF) { 123 count = SAB82532_RECV_FIFO_SIZE; 124 free_fifo++; 125 } 126 127 if (stat->sreg.isr0 & SAB82532_ISR0_TCD) { 128 count = readb(&up->regs->r.rbcl) & (SAB82532_RECV_FIFO_SIZE - 1); 129 free_fifo++; 130 } 131 132 /* Issue a FIFO read command in case we where idle. */ 133 if (stat->sreg.isr0 & SAB82532_ISR0_TIME) { 134 sunsab_cec_wait(up); 135 writeb(SAB82532_CMDR_RFRD, &up->regs->w.cmdr); 136 return port; 137 } 138 139 if (stat->sreg.isr0 & SAB82532_ISR0_RFO) 140 free_fifo++; 141 142 /* Read the FIFO. */ 143 for (i = 0; i < count; i++) 144 buf[i] = readb(&up->regs->r.rfifo[i]); 145 146 /* Issue Receive Message Complete command. */ 147 if (free_fifo) { 148 sunsab_cec_wait(up); 149 writeb(SAB82532_CMDR_RMC, &up->regs->w.cmdr); 150 } 151 152 /* Count may be zero for BRK, so we check for it here */ 153 if ((stat->sreg.isr1 & SAB82532_ISR1_BRK) && 154 (up->port.line == up->port.cons->index)) 155 saw_console_brk = 1; 156 157 if (count == 0) { 158 if (unlikely(stat->sreg.isr1 & SAB82532_ISR1_BRK)) { 159 stat->sreg.isr0 &= ~(SAB82532_ISR0_PERR | 160 SAB82532_ISR0_FERR); 161 up->port.icount.brk++; 162 uart_handle_break(&up->port); 163 } 164 } 165 166 for (i = 0; i < count; i++) { 167 unsigned char ch = buf[i], flag; 168 169 flag = TTY_NORMAL; 170 up->port.icount.rx++; 171 172 if (unlikely(stat->sreg.isr0 & (SAB82532_ISR0_PERR | 173 SAB82532_ISR0_FERR | 174 SAB82532_ISR0_RFO)) || 175 unlikely(stat->sreg.isr1 & SAB82532_ISR1_BRK)) { 176 /* 177 * For statistics only 178 */ 179 if (stat->sreg.isr1 & SAB82532_ISR1_BRK) { 180 stat->sreg.isr0 &= ~(SAB82532_ISR0_PERR | 181 SAB82532_ISR0_FERR); 182 up->port.icount.brk++; 183 /* 184 * We do the SysRQ and SAK checking 185 * here because otherwise the break 186 * may get masked by ignore_status_mask 187 * or read_status_mask. 188 */ 189 if (uart_handle_break(&up->port)) 190 continue; 191 } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR) 192 up->port.icount.parity++; 193 else if (stat->sreg.isr0 & SAB82532_ISR0_FERR) 194 up->port.icount.frame++; 195 if (stat->sreg.isr0 & SAB82532_ISR0_RFO) 196 up->port.icount.overrun++; 197 198 /* 199 * Mask off conditions which should be ingored. 200 */ 201 stat->sreg.isr0 &= (up->port.read_status_mask & 0xff); 202 stat->sreg.isr1 &= ((up->port.read_status_mask >> 8) & 0xff); 203 204 if (stat->sreg.isr1 & SAB82532_ISR1_BRK) { 205 flag = TTY_BREAK; 206 } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR) 207 flag = TTY_PARITY; 208 else if (stat->sreg.isr0 & SAB82532_ISR0_FERR) 209 flag = TTY_FRAME; 210 } 211 212 if (uart_handle_sysrq_char(&up->port, ch) || !port) 213 continue; 214 215 if ((stat->sreg.isr0 & (up->port.ignore_status_mask & 0xff)) == 0 && 216 (stat->sreg.isr1 & ((up->port.ignore_status_mask >> 8) & 0xff)) == 0) 217 tty_insert_flip_char(port, ch, flag); 218 if (stat->sreg.isr0 & SAB82532_ISR0_RFO) 219 tty_insert_flip_char(port, 0, TTY_OVERRUN); 220 } 221 222 if (saw_console_brk) 223 sun_do_break(); 224 225 return port; 226 } 227 228 static void sunsab_stop_tx(struct uart_port *); 229 static void sunsab_tx_idle(struct uart_sunsab_port *); 230 231 static void transmit_chars(struct uart_sunsab_port *up, 232 union sab82532_irq_status *stat) 233 { 234 struct circ_buf *xmit = &up->port.state->xmit; 235 int i; 236 237 if (stat->sreg.isr1 & SAB82532_ISR1_ALLS) { 238 up->interrupt_mask1 |= SAB82532_IMR1_ALLS; 239 writeb(up->interrupt_mask1, &up->regs->w.imr1); 240 set_bit(SAB82532_ALLS, &up->irqflags); 241 } 242 243 #if 0 /* bde@nwlink.com says this check causes problems */ 244 if (!(stat->sreg.isr1 & SAB82532_ISR1_XPR)) 245 return; 246 #endif 247 248 if (!(readb(&up->regs->r.star) & SAB82532_STAR_XFW)) 249 return; 250 251 set_bit(SAB82532_XPR, &up->irqflags); 252 sunsab_tx_idle(up); 253 254 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) { 255 up->interrupt_mask1 |= SAB82532_IMR1_XPR; 256 writeb(up->interrupt_mask1, &up->regs->w.imr1); 257 return; 258 } 259 260 up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR); 261 writeb(up->interrupt_mask1, &up->regs->w.imr1); 262 clear_bit(SAB82532_ALLS, &up->irqflags); 263 264 /* Stuff 32 bytes into Transmit FIFO. */ 265 clear_bit(SAB82532_XPR, &up->irqflags); 266 for (i = 0; i < up->port.fifosize; i++) { 267 writeb(xmit->buf[xmit->tail], 268 &up->regs->w.xfifo[i]); 269 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 270 up->port.icount.tx++; 271 if (uart_circ_empty(xmit)) 272 break; 273 } 274 275 /* Issue a Transmit Frame command. */ 276 sunsab_cec_wait(up); 277 writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr); 278 279 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 280 uart_write_wakeup(&up->port); 281 282 if (uart_circ_empty(xmit)) 283 sunsab_stop_tx(&up->port); 284 } 285 286 static void check_status(struct uart_sunsab_port *up, 287 union sab82532_irq_status *stat) 288 { 289 if (stat->sreg.isr0 & SAB82532_ISR0_CDSC) 290 uart_handle_dcd_change(&up->port, 291 !(readb(&up->regs->r.vstr) & SAB82532_VSTR_CD)); 292 293 if (stat->sreg.isr1 & SAB82532_ISR1_CSC) 294 uart_handle_cts_change(&up->port, 295 (readb(&up->regs->r.star) & SAB82532_STAR_CTS)); 296 297 if ((readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ^ up->dsr) { 298 up->dsr = (readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ? 0 : 1; 299 up->port.icount.dsr++; 300 } 301 302 wake_up_interruptible(&up->port.state->port.delta_msr_wait); 303 } 304 305 static irqreturn_t sunsab_interrupt(int irq, void *dev_id) 306 { 307 struct uart_sunsab_port *up = dev_id; 308 struct tty_port *port = NULL; 309 union sab82532_irq_status status; 310 unsigned long flags; 311 unsigned char gis; 312 313 spin_lock_irqsave(&up->port.lock, flags); 314 315 status.stat = 0; 316 gis = readb(&up->regs->r.gis) >> up->gis_shift; 317 if (gis & 1) 318 status.sreg.isr0 = readb(&up->regs->r.isr0); 319 if (gis & 2) 320 status.sreg.isr1 = readb(&up->regs->r.isr1); 321 322 if (status.stat) { 323 if ((status.sreg.isr0 & (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME | 324 SAB82532_ISR0_RFO | SAB82532_ISR0_RPF)) || 325 (status.sreg.isr1 & SAB82532_ISR1_BRK)) 326 port = receive_chars(up, &status); 327 if ((status.sreg.isr0 & SAB82532_ISR0_CDSC) || 328 (status.sreg.isr1 & SAB82532_ISR1_CSC)) 329 check_status(up, &status); 330 if (status.sreg.isr1 & (SAB82532_ISR1_ALLS | SAB82532_ISR1_XPR)) 331 transmit_chars(up, &status); 332 } 333 334 spin_unlock_irqrestore(&up->port.lock, flags); 335 336 if (port) 337 tty_flip_buffer_push(port); 338 339 return IRQ_HANDLED; 340 } 341 342 /* port->lock is not held. */ 343 static unsigned int sunsab_tx_empty(struct uart_port *port) 344 { 345 struct uart_sunsab_port *up = 346 container_of(port, struct uart_sunsab_port, port); 347 int ret; 348 349 /* Do not need a lock for a state test like this. */ 350 if (test_bit(SAB82532_ALLS, &up->irqflags)) 351 ret = TIOCSER_TEMT; 352 else 353 ret = 0; 354 355 return ret; 356 } 357 358 /* port->lock held by caller. */ 359 static void sunsab_set_mctrl(struct uart_port *port, unsigned int mctrl) 360 { 361 struct uart_sunsab_port *up = 362 container_of(port, struct uart_sunsab_port, port); 363 364 if (mctrl & TIOCM_RTS) { 365 up->cached_mode &= ~SAB82532_MODE_FRTS; 366 up->cached_mode |= SAB82532_MODE_RTS; 367 } else { 368 up->cached_mode |= (SAB82532_MODE_FRTS | 369 SAB82532_MODE_RTS); 370 } 371 if (mctrl & TIOCM_DTR) { 372 up->cached_pvr &= ~(up->pvr_dtr_bit); 373 } else { 374 up->cached_pvr |= up->pvr_dtr_bit; 375 } 376 377 set_bit(SAB82532_REGS_PENDING, &up->irqflags); 378 if (test_bit(SAB82532_XPR, &up->irqflags)) 379 sunsab_tx_idle(up); 380 } 381 382 /* port->lock is held by caller and interrupts are disabled. */ 383 static unsigned int sunsab_get_mctrl(struct uart_port *port) 384 { 385 struct uart_sunsab_port *up = 386 container_of(port, struct uart_sunsab_port, port); 387 unsigned char val; 388 unsigned int result; 389 390 result = 0; 391 392 val = readb(&up->regs->r.pvr); 393 result |= (val & up->pvr_dsr_bit) ? 0 : TIOCM_DSR; 394 395 val = readb(&up->regs->r.vstr); 396 result |= (val & SAB82532_VSTR_CD) ? 0 : TIOCM_CAR; 397 398 val = readb(&up->regs->r.star); 399 result |= (val & SAB82532_STAR_CTS) ? TIOCM_CTS : 0; 400 401 return result; 402 } 403 404 /* port->lock held by caller. */ 405 static void sunsab_stop_tx(struct uart_port *port) 406 { 407 struct uart_sunsab_port *up = 408 container_of(port, struct uart_sunsab_port, port); 409 410 up->interrupt_mask1 |= SAB82532_IMR1_XPR; 411 writeb(up->interrupt_mask1, &up->regs->w.imr1); 412 } 413 414 /* port->lock held by caller. */ 415 static void sunsab_tx_idle(struct uart_sunsab_port *up) 416 { 417 if (test_bit(SAB82532_REGS_PENDING, &up->irqflags)) { 418 u8 tmp; 419 420 clear_bit(SAB82532_REGS_PENDING, &up->irqflags); 421 writeb(up->cached_mode, &up->regs->rw.mode); 422 writeb(up->cached_pvr, &up->regs->rw.pvr); 423 writeb(up->cached_dafo, &up->regs->w.dafo); 424 425 writeb(up->cached_ebrg & 0xff, &up->regs->w.bgr); 426 tmp = readb(&up->regs->rw.ccr2); 427 tmp &= ~0xc0; 428 tmp |= (up->cached_ebrg >> 2) & 0xc0; 429 writeb(tmp, &up->regs->rw.ccr2); 430 } 431 } 432 433 /* port->lock held by caller. */ 434 static void sunsab_start_tx(struct uart_port *port) 435 { 436 struct uart_sunsab_port *up = 437 container_of(port, struct uart_sunsab_port, port); 438 struct circ_buf *xmit = &up->port.state->xmit; 439 int i; 440 441 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) 442 return; 443 444 up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR); 445 writeb(up->interrupt_mask1, &up->regs->w.imr1); 446 447 if (!test_bit(SAB82532_XPR, &up->irqflags)) 448 return; 449 450 clear_bit(SAB82532_ALLS, &up->irqflags); 451 clear_bit(SAB82532_XPR, &up->irqflags); 452 453 for (i = 0; i < up->port.fifosize; i++) { 454 writeb(xmit->buf[xmit->tail], 455 &up->regs->w.xfifo[i]); 456 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 457 up->port.icount.tx++; 458 if (uart_circ_empty(xmit)) 459 break; 460 } 461 462 /* Issue a Transmit Frame command. */ 463 sunsab_cec_wait(up); 464 writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr); 465 } 466 467 /* port->lock is not held. */ 468 static void sunsab_send_xchar(struct uart_port *port, char ch) 469 { 470 struct uart_sunsab_port *up = 471 container_of(port, struct uart_sunsab_port, port); 472 unsigned long flags; 473 474 if (ch == __DISABLED_CHAR) 475 return; 476 477 spin_lock_irqsave(&up->port.lock, flags); 478 479 sunsab_tec_wait(up); 480 writeb(ch, &up->regs->w.tic); 481 482 spin_unlock_irqrestore(&up->port.lock, flags); 483 } 484 485 /* port->lock held by caller. */ 486 static void sunsab_stop_rx(struct uart_port *port) 487 { 488 struct uart_sunsab_port *up = 489 container_of(port, struct uart_sunsab_port, port); 490 491 up->interrupt_mask0 |= SAB82532_IMR0_TCD; 492 writeb(up->interrupt_mask1, &up->regs->w.imr0); 493 } 494 495 /* port->lock is not held. */ 496 static void sunsab_break_ctl(struct uart_port *port, int break_state) 497 { 498 struct uart_sunsab_port *up = 499 container_of(port, struct uart_sunsab_port, port); 500 unsigned long flags; 501 unsigned char val; 502 503 spin_lock_irqsave(&up->port.lock, flags); 504 505 val = up->cached_dafo; 506 if (break_state) 507 val |= SAB82532_DAFO_XBRK; 508 else 509 val &= ~SAB82532_DAFO_XBRK; 510 up->cached_dafo = val; 511 512 set_bit(SAB82532_REGS_PENDING, &up->irqflags); 513 if (test_bit(SAB82532_XPR, &up->irqflags)) 514 sunsab_tx_idle(up); 515 516 spin_unlock_irqrestore(&up->port.lock, flags); 517 } 518 519 /* port->lock is not held. */ 520 static int sunsab_startup(struct uart_port *port) 521 { 522 struct uart_sunsab_port *up = 523 container_of(port, struct uart_sunsab_port, port); 524 unsigned long flags; 525 unsigned char tmp; 526 int err = request_irq(up->port.irq, sunsab_interrupt, 527 IRQF_SHARED, "sab", up); 528 if (err) 529 return err; 530 531 spin_lock_irqsave(&up->port.lock, flags); 532 533 /* 534 * Wait for any commands or immediate characters 535 */ 536 sunsab_cec_wait(up); 537 sunsab_tec_wait(up); 538 539 /* 540 * Clear the FIFO buffers. 541 */ 542 writeb(SAB82532_CMDR_RRES, &up->regs->w.cmdr); 543 sunsab_cec_wait(up); 544 writeb(SAB82532_CMDR_XRES, &up->regs->w.cmdr); 545 546 /* 547 * Clear the interrupt registers. 548 */ 549 (void) readb(&up->regs->r.isr0); 550 (void) readb(&up->regs->r.isr1); 551 552 /* 553 * Now, initialize the UART 554 */ 555 writeb(0, &up->regs->w.ccr0); /* power-down */ 556 writeb(SAB82532_CCR0_MCE | SAB82532_CCR0_SC_NRZ | 557 SAB82532_CCR0_SM_ASYNC, &up->regs->w.ccr0); 558 writeb(SAB82532_CCR1_ODS | SAB82532_CCR1_BCR | 7, &up->regs->w.ccr1); 559 writeb(SAB82532_CCR2_BDF | SAB82532_CCR2_SSEL | 560 SAB82532_CCR2_TOE, &up->regs->w.ccr2); 561 writeb(0, &up->regs->w.ccr3); 562 writeb(SAB82532_CCR4_MCK4 | SAB82532_CCR4_EBRG, &up->regs->w.ccr4); 563 up->cached_mode = (SAB82532_MODE_RTS | SAB82532_MODE_FCTS | 564 SAB82532_MODE_RAC); 565 writeb(up->cached_mode, &up->regs->w.mode); 566 writeb(SAB82532_RFC_DPS|SAB82532_RFC_RFTH_32, &up->regs->w.rfc); 567 568 tmp = readb(&up->regs->rw.ccr0); 569 tmp |= SAB82532_CCR0_PU; /* power-up */ 570 writeb(tmp, &up->regs->rw.ccr0); 571 572 /* 573 * Finally, enable interrupts 574 */ 575 up->interrupt_mask0 = (SAB82532_IMR0_PERR | SAB82532_IMR0_FERR | 576 SAB82532_IMR0_PLLA); 577 writeb(up->interrupt_mask0, &up->regs->w.imr0); 578 up->interrupt_mask1 = (SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS | 579 SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN | 580 SAB82532_IMR1_CSC | SAB82532_IMR1_XON | 581 SAB82532_IMR1_XPR); 582 writeb(up->interrupt_mask1, &up->regs->w.imr1); 583 set_bit(SAB82532_ALLS, &up->irqflags); 584 set_bit(SAB82532_XPR, &up->irqflags); 585 586 spin_unlock_irqrestore(&up->port.lock, flags); 587 588 return 0; 589 } 590 591 /* port->lock is not held. */ 592 static void sunsab_shutdown(struct uart_port *port) 593 { 594 struct uart_sunsab_port *up = 595 container_of(port, struct uart_sunsab_port, port); 596 unsigned long flags; 597 598 spin_lock_irqsave(&up->port.lock, flags); 599 600 /* Disable Interrupts */ 601 up->interrupt_mask0 = 0xff; 602 writeb(up->interrupt_mask0, &up->regs->w.imr0); 603 up->interrupt_mask1 = 0xff; 604 writeb(up->interrupt_mask1, &up->regs->w.imr1); 605 606 /* Disable break condition */ 607 up->cached_dafo = readb(&up->regs->rw.dafo); 608 up->cached_dafo &= ~SAB82532_DAFO_XBRK; 609 writeb(up->cached_dafo, &up->regs->rw.dafo); 610 611 /* Disable Receiver */ 612 up->cached_mode &= ~SAB82532_MODE_RAC; 613 writeb(up->cached_mode, &up->regs->rw.mode); 614 615 /* 616 * XXX FIXME 617 * 618 * If the chip is powered down here the system hangs/crashes during 619 * reboot or shutdown. This needs to be investigated further, 620 * similar behaviour occurs in 2.4 when the driver is configured 621 * as a module only. One hint may be that data is sometimes 622 * transmitted at 9600 baud during shutdown (regardless of the 623 * speed the chip was configured for when the port was open). 624 */ 625 #if 0 626 /* Power Down */ 627 tmp = readb(&up->regs->rw.ccr0); 628 tmp &= ~SAB82532_CCR0_PU; 629 writeb(tmp, &up->regs->rw.ccr0); 630 #endif 631 632 spin_unlock_irqrestore(&up->port.lock, flags); 633 free_irq(up->port.irq, up); 634 } 635 636 /* 637 * This is used to figure out the divisor speeds. 638 * 639 * The formula is: Baud = SAB_BASE_BAUD / ((N + 1) * (1 << M)), 640 * 641 * with 0 <= N < 64 and 0 <= M < 16 642 */ 643 644 static void calc_ebrg(int baud, int *n_ret, int *m_ret) 645 { 646 int n, m; 647 648 if (baud == 0) { 649 *n_ret = 0; 650 *m_ret = 0; 651 return; 652 } 653 654 /* 655 * We scale numbers by 10 so that we get better accuracy 656 * without having to use floating point. Here we increment m 657 * until n is within the valid range. 658 */ 659 n = (SAB_BASE_BAUD * 10) / baud; 660 m = 0; 661 while (n >= 640) { 662 n = n / 2; 663 m++; 664 } 665 n = (n+5) / 10; 666 /* 667 * We try very hard to avoid speeds with M == 0 since they may 668 * not work correctly for XTAL frequences above 10 MHz. 669 */ 670 if ((m == 0) && ((n & 1) == 0)) { 671 n = n / 2; 672 m++; 673 } 674 *n_ret = n - 1; 675 *m_ret = m; 676 } 677 678 /* Internal routine, port->lock is held and local interrupts are disabled. */ 679 static void sunsab_convert_to_sab(struct uart_sunsab_port *up, unsigned int cflag, 680 unsigned int iflag, unsigned int baud, 681 unsigned int quot) 682 { 683 unsigned char dafo; 684 int bits, n, m; 685 686 /* Byte size and parity */ 687 switch (cflag & CSIZE) { 688 case CS5: dafo = SAB82532_DAFO_CHL5; bits = 7; break; 689 case CS6: dafo = SAB82532_DAFO_CHL6; bits = 8; break; 690 case CS7: dafo = SAB82532_DAFO_CHL7; bits = 9; break; 691 case CS8: dafo = SAB82532_DAFO_CHL8; bits = 10; break; 692 /* Never happens, but GCC is too dumb to figure it out */ 693 default: dafo = SAB82532_DAFO_CHL5; bits = 7; break; 694 } 695 696 if (cflag & CSTOPB) { 697 dafo |= SAB82532_DAFO_STOP; 698 bits++; 699 } 700 701 if (cflag & PARENB) { 702 dafo |= SAB82532_DAFO_PARE; 703 bits++; 704 } 705 706 if (cflag & PARODD) { 707 dafo |= SAB82532_DAFO_PAR_ODD; 708 } else { 709 dafo |= SAB82532_DAFO_PAR_EVEN; 710 } 711 up->cached_dafo = dafo; 712 713 calc_ebrg(baud, &n, &m); 714 715 up->cached_ebrg = n | (m << 6); 716 717 up->tec_timeout = (10 * 1000000) / baud; 718 up->cec_timeout = up->tec_timeout >> 2; 719 720 /* CTS flow control flags */ 721 /* We encode read_status_mask and ignore_status_mask like so: 722 * 723 * --------------------- 724 * | ... | ISR1 | ISR0 | 725 * --------------------- 726 * .. 15 8 7 0 727 */ 728 729 up->port.read_status_mask = (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME | 730 SAB82532_ISR0_RFO | SAB82532_ISR0_RPF | 731 SAB82532_ISR0_CDSC); 732 up->port.read_status_mask |= (SAB82532_ISR1_CSC | 733 SAB82532_ISR1_ALLS | 734 SAB82532_ISR1_XPR) << 8; 735 if (iflag & INPCK) 736 up->port.read_status_mask |= (SAB82532_ISR0_PERR | 737 SAB82532_ISR0_FERR); 738 if (iflag & (IGNBRK | BRKINT | PARMRK)) 739 up->port.read_status_mask |= (SAB82532_ISR1_BRK << 8); 740 741 /* 742 * Characteres to ignore 743 */ 744 up->port.ignore_status_mask = 0; 745 if (iflag & IGNPAR) 746 up->port.ignore_status_mask |= (SAB82532_ISR0_PERR | 747 SAB82532_ISR0_FERR); 748 if (iflag & IGNBRK) { 749 up->port.ignore_status_mask |= (SAB82532_ISR1_BRK << 8); 750 /* 751 * If we're ignoring parity and break indicators, 752 * ignore overruns too (for real raw support). 753 */ 754 if (iflag & IGNPAR) 755 up->port.ignore_status_mask |= SAB82532_ISR0_RFO; 756 } 757 758 /* 759 * ignore all characters if CREAD is not set 760 */ 761 if ((cflag & CREAD) == 0) 762 up->port.ignore_status_mask |= (SAB82532_ISR0_RPF | 763 SAB82532_ISR0_TCD); 764 765 uart_update_timeout(&up->port, cflag, 766 (up->port.uartclk / (16 * quot))); 767 768 /* Now schedule a register update when the chip's 769 * transmitter is idle. 770 */ 771 up->cached_mode |= SAB82532_MODE_RAC; 772 set_bit(SAB82532_REGS_PENDING, &up->irqflags); 773 if (test_bit(SAB82532_XPR, &up->irqflags)) 774 sunsab_tx_idle(up); 775 } 776 777 /* port->lock is not held. */ 778 static void sunsab_set_termios(struct uart_port *port, struct ktermios *termios, 779 struct ktermios *old) 780 { 781 struct uart_sunsab_port *up = 782 container_of(port, struct uart_sunsab_port, port); 783 unsigned long flags; 784 unsigned int baud = uart_get_baud_rate(port, termios, old, 0, 4000000); 785 unsigned int quot = uart_get_divisor(port, baud); 786 787 spin_lock_irqsave(&up->port.lock, flags); 788 sunsab_convert_to_sab(up, termios->c_cflag, termios->c_iflag, baud, quot); 789 spin_unlock_irqrestore(&up->port.lock, flags); 790 } 791 792 static const char *sunsab_type(struct uart_port *port) 793 { 794 struct uart_sunsab_port *up = (void *)port; 795 static char buf[36]; 796 797 sprintf(buf, "SAB82532 %s", sab82532_version[up->type]); 798 return buf; 799 } 800 801 static void sunsab_release_port(struct uart_port *port) 802 { 803 } 804 805 static int sunsab_request_port(struct uart_port *port) 806 { 807 return 0; 808 } 809 810 static void sunsab_config_port(struct uart_port *port, int flags) 811 { 812 } 813 814 static int sunsab_verify_port(struct uart_port *port, struct serial_struct *ser) 815 { 816 return -EINVAL; 817 } 818 819 static const struct uart_ops sunsab_pops = { 820 .tx_empty = sunsab_tx_empty, 821 .set_mctrl = sunsab_set_mctrl, 822 .get_mctrl = sunsab_get_mctrl, 823 .stop_tx = sunsab_stop_tx, 824 .start_tx = sunsab_start_tx, 825 .send_xchar = sunsab_send_xchar, 826 .stop_rx = sunsab_stop_rx, 827 .break_ctl = sunsab_break_ctl, 828 .startup = sunsab_startup, 829 .shutdown = sunsab_shutdown, 830 .set_termios = sunsab_set_termios, 831 .type = sunsab_type, 832 .release_port = sunsab_release_port, 833 .request_port = sunsab_request_port, 834 .config_port = sunsab_config_port, 835 .verify_port = sunsab_verify_port, 836 }; 837 838 static struct uart_driver sunsab_reg = { 839 .owner = THIS_MODULE, 840 .driver_name = "sunsab", 841 .dev_name = "ttyS", 842 .major = TTY_MAJOR, 843 }; 844 845 static struct uart_sunsab_port *sunsab_ports; 846 847 #ifdef CONFIG_SERIAL_SUNSAB_CONSOLE 848 849 static void sunsab_console_putchar(struct uart_port *port, int c) 850 { 851 struct uart_sunsab_port *up = 852 container_of(port, struct uart_sunsab_port, port); 853 854 sunsab_tec_wait(up); 855 writeb(c, &up->regs->w.tic); 856 } 857 858 static void sunsab_console_write(struct console *con, const char *s, unsigned n) 859 { 860 struct uart_sunsab_port *up = &sunsab_ports[con->index]; 861 unsigned long flags; 862 int locked = 1; 863 864 if (up->port.sysrq || oops_in_progress) 865 locked = spin_trylock_irqsave(&up->port.lock, flags); 866 else 867 spin_lock_irqsave(&up->port.lock, flags); 868 869 uart_console_write(&up->port, s, n, sunsab_console_putchar); 870 sunsab_tec_wait(up); 871 872 if (locked) 873 spin_unlock_irqrestore(&up->port.lock, flags); 874 } 875 876 static int sunsab_console_setup(struct console *con, char *options) 877 { 878 struct uart_sunsab_port *up = &sunsab_ports[con->index]; 879 unsigned long flags; 880 unsigned int baud, quot; 881 882 /* 883 * The console framework calls us for each and every port 884 * registered. Defer the console setup until the requested 885 * port has been properly discovered. A bit of a hack, 886 * though... 887 */ 888 if (up->port.type != PORT_SUNSAB) 889 return -1; 890 891 printk("Console: ttyS%d (SAB82532)\n", 892 (sunsab_reg.minor - 64) + con->index); 893 894 sunserial_console_termios(con, up->port.dev->of_node); 895 896 switch (con->cflag & CBAUD) { 897 case B150: baud = 150; break; 898 case B300: baud = 300; break; 899 case B600: baud = 600; break; 900 case B1200: baud = 1200; break; 901 case B2400: baud = 2400; break; 902 case B4800: baud = 4800; break; 903 default: case B9600: baud = 9600; break; 904 case B19200: baud = 19200; break; 905 case B38400: baud = 38400; break; 906 case B57600: baud = 57600; break; 907 case B115200: baud = 115200; break; 908 case B230400: baud = 230400; break; 909 case B460800: baud = 460800; break; 910 } 911 912 /* 913 * Temporary fix. 914 */ 915 spin_lock_init(&up->port.lock); 916 917 /* 918 * Initialize the hardware 919 */ 920 sunsab_startup(&up->port); 921 922 spin_lock_irqsave(&up->port.lock, flags); 923 924 /* 925 * Finally, enable interrupts 926 */ 927 up->interrupt_mask0 = SAB82532_IMR0_PERR | SAB82532_IMR0_FERR | 928 SAB82532_IMR0_PLLA | SAB82532_IMR0_CDSC; 929 writeb(up->interrupt_mask0, &up->regs->w.imr0); 930 up->interrupt_mask1 = SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS | 931 SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN | 932 SAB82532_IMR1_CSC | SAB82532_IMR1_XON | 933 SAB82532_IMR1_XPR; 934 writeb(up->interrupt_mask1, &up->regs->w.imr1); 935 936 quot = uart_get_divisor(&up->port, baud); 937 sunsab_convert_to_sab(up, con->cflag, 0, baud, quot); 938 sunsab_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS); 939 940 spin_unlock_irqrestore(&up->port.lock, flags); 941 942 return 0; 943 } 944 945 static struct console sunsab_console = { 946 .name = "ttyS", 947 .write = sunsab_console_write, 948 .device = uart_console_device, 949 .setup = sunsab_console_setup, 950 .flags = CON_PRINTBUFFER, 951 .index = -1, 952 .data = &sunsab_reg, 953 }; 954 955 static inline struct console *SUNSAB_CONSOLE(void) 956 { 957 return &sunsab_console; 958 } 959 #else 960 #define SUNSAB_CONSOLE() (NULL) 961 #define sunsab_console_init() do { } while (0) 962 #endif 963 964 static int sunsab_init_one(struct uart_sunsab_port *up, 965 struct platform_device *op, 966 unsigned long offset, 967 int line) 968 { 969 up->port.line = line; 970 up->port.dev = &op->dev; 971 972 up->port.mapbase = op->resource[0].start + offset; 973 up->port.membase = of_ioremap(&op->resource[0], offset, 974 sizeof(union sab82532_async_regs), 975 "sab"); 976 if (!up->port.membase) 977 return -ENOMEM; 978 up->regs = (union sab82532_async_regs __iomem *) up->port.membase; 979 980 up->port.irq = op->archdata.irqs[0]; 981 982 up->port.fifosize = SAB82532_XMIT_FIFO_SIZE; 983 up->port.iotype = UPIO_MEM; 984 up->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SUNSAB_CONSOLE); 985 986 writeb(SAB82532_IPC_IC_ACT_LOW, &up->regs->w.ipc); 987 988 up->port.ops = &sunsab_pops; 989 up->port.type = PORT_SUNSAB; 990 up->port.uartclk = SAB_BASE_BAUD; 991 992 up->type = readb(&up->regs->r.vstr) & 0x0f; 993 writeb(~((1 << 1) | (1 << 2) | (1 << 4)), &up->regs->w.pcr); 994 writeb(0xff, &up->regs->w.pim); 995 if ((up->port.line & 0x1) == 0) { 996 up->pvr_dsr_bit = (1 << 0); 997 up->pvr_dtr_bit = (1 << 1); 998 up->gis_shift = 2; 999 } else { 1000 up->pvr_dsr_bit = (1 << 3); 1001 up->pvr_dtr_bit = (1 << 2); 1002 up->gis_shift = 0; 1003 } 1004 up->cached_pvr = (1 << 1) | (1 << 2) | (1 << 4); 1005 writeb(up->cached_pvr, &up->regs->w.pvr); 1006 up->cached_mode = readb(&up->regs->rw.mode); 1007 up->cached_mode |= SAB82532_MODE_FRTS; 1008 writeb(up->cached_mode, &up->regs->rw.mode); 1009 up->cached_mode |= SAB82532_MODE_RTS; 1010 writeb(up->cached_mode, &up->regs->rw.mode); 1011 1012 up->tec_timeout = SAB82532_MAX_TEC_TIMEOUT; 1013 up->cec_timeout = SAB82532_MAX_CEC_TIMEOUT; 1014 1015 return 0; 1016 } 1017 1018 static int sab_probe(struct platform_device *op) 1019 { 1020 static int inst; 1021 struct uart_sunsab_port *up; 1022 int err; 1023 1024 up = &sunsab_ports[inst * 2]; 1025 1026 err = sunsab_init_one(&up[0], op, 1027 0, 1028 (inst * 2) + 0); 1029 if (err) 1030 goto out; 1031 1032 err = sunsab_init_one(&up[1], op, 1033 sizeof(union sab82532_async_regs), 1034 (inst * 2) + 1); 1035 if (err) 1036 goto out1; 1037 1038 sunserial_console_match(SUNSAB_CONSOLE(), op->dev.of_node, 1039 &sunsab_reg, up[0].port.line, 1040 false); 1041 1042 sunserial_console_match(SUNSAB_CONSOLE(), op->dev.of_node, 1043 &sunsab_reg, up[1].port.line, 1044 false); 1045 1046 err = uart_add_one_port(&sunsab_reg, &up[0].port); 1047 if (err) 1048 goto out2; 1049 1050 err = uart_add_one_port(&sunsab_reg, &up[1].port); 1051 if (err) 1052 goto out3; 1053 1054 platform_set_drvdata(op, &up[0]); 1055 1056 inst++; 1057 1058 return 0; 1059 1060 out3: 1061 uart_remove_one_port(&sunsab_reg, &up[0].port); 1062 out2: 1063 of_iounmap(&op->resource[0], 1064 up[1].port.membase, 1065 sizeof(union sab82532_async_regs)); 1066 out1: 1067 of_iounmap(&op->resource[0], 1068 up[0].port.membase, 1069 sizeof(union sab82532_async_regs)); 1070 out: 1071 return err; 1072 } 1073 1074 static int sab_remove(struct platform_device *op) 1075 { 1076 struct uart_sunsab_port *up = platform_get_drvdata(op); 1077 1078 uart_remove_one_port(&sunsab_reg, &up[1].port); 1079 uart_remove_one_port(&sunsab_reg, &up[0].port); 1080 of_iounmap(&op->resource[0], 1081 up[1].port.membase, 1082 sizeof(union sab82532_async_regs)); 1083 of_iounmap(&op->resource[0], 1084 up[0].port.membase, 1085 sizeof(union sab82532_async_regs)); 1086 1087 return 0; 1088 } 1089 1090 static const struct of_device_id sab_match[] = { 1091 { 1092 .name = "se", 1093 }, 1094 { 1095 .name = "serial", 1096 .compatible = "sab82532", 1097 }, 1098 {}, 1099 }; 1100 MODULE_DEVICE_TABLE(of, sab_match); 1101 1102 static struct platform_driver sab_driver = { 1103 .driver = { 1104 .name = "sab", 1105 .of_match_table = sab_match, 1106 }, 1107 .probe = sab_probe, 1108 .remove = sab_remove, 1109 }; 1110 1111 static int __init sunsab_init(void) 1112 { 1113 struct device_node *dp; 1114 int err; 1115 int num_channels = 0; 1116 1117 for_each_node_by_name(dp, "se") 1118 num_channels += 2; 1119 for_each_node_by_name(dp, "serial") { 1120 if (of_device_is_compatible(dp, "sab82532")) 1121 num_channels += 2; 1122 } 1123 1124 if (num_channels) { 1125 sunsab_ports = kcalloc(num_channels, 1126 sizeof(struct uart_sunsab_port), 1127 GFP_KERNEL); 1128 if (!sunsab_ports) 1129 return -ENOMEM; 1130 1131 err = sunserial_register_minors(&sunsab_reg, num_channels); 1132 if (err) { 1133 kfree(sunsab_ports); 1134 sunsab_ports = NULL; 1135 1136 return err; 1137 } 1138 } 1139 1140 return platform_driver_register(&sab_driver); 1141 } 1142 1143 static void __exit sunsab_exit(void) 1144 { 1145 platform_driver_unregister(&sab_driver); 1146 if (sunsab_reg.nr) { 1147 sunserial_unregister_minors(&sunsab_reg, sunsab_reg.nr); 1148 } 1149 1150 kfree(sunsab_ports); 1151 sunsab_ports = NULL; 1152 } 1153 1154 module_init(sunsab_init); 1155 module_exit(sunsab_exit); 1156 1157 MODULE_AUTHOR("Eddie C. Dost and David S. Miller"); 1158 MODULE_DESCRIPTION("Sun SAB82532 serial port driver"); 1159 MODULE_LICENSE("GPL"); 1160