1 /* sunsab.c: ASYNC Driver for the SIEMENS SAB82532 DUSCC. 2 * 3 * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be) 4 * Copyright (C) 2002, 2006 David S. Miller (davem@davemloft.net) 5 * 6 * Rewrote buffer handling to use CIRC(Circular Buffer) macros. 7 * Maxim Krasnyanskiy <maxk@qualcomm.com> 8 * 9 * Fixed to use tty_get_baud_rate, and to allow for arbitrary baud 10 * rates to be programmed into the UART. Also eliminated a lot of 11 * duplicated code in the console setup. 12 * Theodore Ts'o <tytso@mit.edu>, 2001-Oct-12 13 * 14 * Ported to new 2.5.x UART layer. 15 * David S. Miller <davem@davemloft.net> 16 */ 17 18 #include <linux/module.h> 19 #include <linux/kernel.h> 20 #include <linux/errno.h> 21 #include <linux/tty.h> 22 #include <linux/tty_flip.h> 23 #include <linux/major.h> 24 #include <linux/string.h> 25 #include <linux/ptrace.h> 26 #include <linux/ioport.h> 27 #include <linux/circ_buf.h> 28 #include <linux/serial.h> 29 #include <linux/sysrq.h> 30 #include <linux/console.h> 31 #include <linux/spinlock.h> 32 #include <linux/slab.h> 33 #include <linux/delay.h> 34 #include <linux/init.h> 35 #include <linux/of_device.h> 36 37 #include <asm/io.h> 38 #include <asm/irq.h> 39 #include <asm/prom.h> 40 #include <asm/setup.h> 41 42 #if defined(CONFIG_SERIAL_SUNSAB_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 43 #define SUPPORT_SYSRQ 44 #endif 45 46 #include <linux/serial_core.h> 47 #include <linux/sunserialcore.h> 48 49 #include "sunsab.h" 50 51 struct uart_sunsab_port { 52 struct uart_port port; /* Generic UART port */ 53 union sab82532_async_regs __iomem *regs; /* Chip registers */ 54 unsigned long irqflags; /* IRQ state flags */ 55 int dsr; /* Current DSR state */ 56 unsigned int cec_timeout; /* Chip poll timeout... */ 57 unsigned int tec_timeout; /* likewise */ 58 unsigned char interrupt_mask0;/* ISR0 masking */ 59 unsigned char interrupt_mask1;/* ISR1 masking */ 60 unsigned char pvr_dtr_bit; /* Which PVR bit is DTR */ 61 unsigned char pvr_dsr_bit; /* Which PVR bit is DSR */ 62 unsigned int gis_shift; 63 int type; /* SAB82532 version */ 64 65 /* Setting configuration bits while the transmitter is active 66 * can cause garbage characters to get emitted by the chip. 67 * Therefore, we cache such writes here and do the real register 68 * write the next time the transmitter becomes idle. 69 */ 70 unsigned int cached_ebrg; 71 unsigned char cached_mode; 72 unsigned char cached_pvr; 73 unsigned char cached_dafo; 74 }; 75 76 /* 77 * This assumes you have a 29.4912 MHz clock for your UART. 78 */ 79 #define SAB_BASE_BAUD ( 29491200 / 16 ) 80 81 static char *sab82532_version[16] = { 82 "V1.0", "V2.0", "V3.2", "V(0x03)", 83 "V(0x04)", "V(0x05)", "V(0x06)", "V(0x07)", 84 "V(0x08)", "V(0x09)", "V(0x0a)", "V(0x0b)", 85 "V(0x0c)", "V(0x0d)", "V(0x0e)", "V(0x0f)" 86 }; 87 88 #define SAB82532_MAX_TEC_TIMEOUT 200000 /* 1 character time (at 50 baud) */ 89 #define SAB82532_MAX_CEC_TIMEOUT 50000 /* 2.5 TX CLKs (at 50 baud) */ 90 91 #define SAB82532_RECV_FIFO_SIZE 32 /* Standard async fifo sizes */ 92 #define SAB82532_XMIT_FIFO_SIZE 32 93 94 static __inline__ void sunsab_tec_wait(struct uart_sunsab_port *up) 95 { 96 int timeout = up->tec_timeout; 97 98 while ((readb(&up->regs->r.star) & SAB82532_STAR_TEC) && --timeout) 99 udelay(1); 100 } 101 102 static __inline__ void sunsab_cec_wait(struct uart_sunsab_port *up) 103 { 104 int timeout = up->cec_timeout; 105 106 while ((readb(&up->regs->r.star) & SAB82532_STAR_CEC) && --timeout) 107 udelay(1); 108 } 109 110 static struct tty_struct * 111 receive_chars(struct uart_sunsab_port *up, 112 union sab82532_irq_status *stat) 113 { 114 struct tty_struct *tty = NULL; 115 unsigned char buf[32]; 116 int saw_console_brk = 0; 117 int free_fifo = 0; 118 int count = 0; 119 int i; 120 121 if (up->port.state != NULL) /* Unopened serial console */ 122 tty = up->port.state->port.tty; 123 124 /* Read number of BYTES (Character + Status) available. */ 125 if (stat->sreg.isr0 & SAB82532_ISR0_RPF) { 126 count = SAB82532_RECV_FIFO_SIZE; 127 free_fifo++; 128 } 129 130 if (stat->sreg.isr0 & SAB82532_ISR0_TCD) { 131 count = readb(&up->regs->r.rbcl) & (SAB82532_RECV_FIFO_SIZE - 1); 132 free_fifo++; 133 } 134 135 /* Issue a FIFO read command in case we where idle. */ 136 if (stat->sreg.isr0 & SAB82532_ISR0_TIME) { 137 sunsab_cec_wait(up); 138 writeb(SAB82532_CMDR_RFRD, &up->regs->w.cmdr); 139 return tty; 140 } 141 142 if (stat->sreg.isr0 & SAB82532_ISR0_RFO) 143 free_fifo++; 144 145 /* Read the FIFO. */ 146 for (i = 0; i < count; i++) 147 buf[i] = readb(&up->regs->r.rfifo[i]); 148 149 /* Issue Receive Message Complete command. */ 150 if (free_fifo) { 151 sunsab_cec_wait(up); 152 writeb(SAB82532_CMDR_RMC, &up->regs->w.cmdr); 153 } 154 155 /* Count may be zero for BRK, so we check for it here */ 156 if ((stat->sreg.isr1 & SAB82532_ISR1_BRK) && 157 (up->port.line == up->port.cons->index)) 158 saw_console_brk = 1; 159 160 for (i = 0; i < count; i++) { 161 unsigned char ch = buf[i], flag; 162 163 if (tty == NULL) { 164 uart_handle_sysrq_char(&up->port, ch); 165 continue; 166 } 167 168 flag = TTY_NORMAL; 169 up->port.icount.rx++; 170 171 if (unlikely(stat->sreg.isr0 & (SAB82532_ISR0_PERR | 172 SAB82532_ISR0_FERR | 173 SAB82532_ISR0_RFO)) || 174 unlikely(stat->sreg.isr1 & SAB82532_ISR1_BRK)) { 175 /* 176 * For statistics only 177 */ 178 if (stat->sreg.isr1 & SAB82532_ISR1_BRK) { 179 stat->sreg.isr0 &= ~(SAB82532_ISR0_PERR | 180 SAB82532_ISR0_FERR); 181 up->port.icount.brk++; 182 /* 183 * We do the SysRQ and SAK checking 184 * here because otherwise the break 185 * may get masked by ignore_status_mask 186 * or read_status_mask. 187 */ 188 if (uart_handle_break(&up->port)) 189 continue; 190 } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR) 191 up->port.icount.parity++; 192 else if (stat->sreg.isr0 & SAB82532_ISR0_FERR) 193 up->port.icount.frame++; 194 if (stat->sreg.isr0 & SAB82532_ISR0_RFO) 195 up->port.icount.overrun++; 196 197 /* 198 * Mask off conditions which should be ingored. 199 */ 200 stat->sreg.isr0 &= (up->port.read_status_mask & 0xff); 201 stat->sreg.isr1 &= ((up->port.read_status_mask >> 8) & 0xff); 202 203 if (stat->sreg.isr1 & SAB82532_ISR1_BRK) { 204 flag = TTY_BREAK; 205 } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR) 206 flag = TTY_PARITY; 207 else if (stat->sreg.isr0 & SAB82532_ISR0_FERR) 208 flag = TTY_FRAME; 209 } 210 211 if (uart_handle_sysrq_char(&up->port, ch)) 212 continue; 213 214 if ((stat->sreg.isr0 & (up->port.ignore_status_mask & 0xff)) == 0 && 215 (stat->sreg.isr1 & ((up->port.ignore_status_mask >> 8) & 0xff)) == 0) 216 tty_insert_flip_char(tty, ch, flag); 217 if (stat->sreg.isr0 & SAB82532_ISR0_RFO) 218 tty_insert_flip_char(tty, 0, TTY_OVERRUN); 219 } 220 221 if (saw_console_brk) 222 sun_do_break(); 223 224 return tty; 225 } 226 227 static void sunsab_stop_tx(struct uart_port *); 228 static void sunsab_tx_idle(struct uart_sunsab_port *); 229 230 static void transmit_chars(struct uart_sunsab_port *up, 231 union sab82532_irq_status *stat) 232 { 233 struct circ_buf *xmit = &up->port.state->xmit; 234 int i; 235 236 if (stat->sreg.isr1 & SAB82532_ISR1_ALLS) { 237 up->interrupt_mask1 |= SAB82532_IMR1_ALLS; 238 writeb(up->interrupt_mask1, &up->regs->w.imr1); 239 set_bit(SAB82532_ALLS, &up->irqflags); 240 } 241 242 #if 0 /* bde@nwlink.com says this check causes problems */ 243 if (!(stat->sreg.isr1 & SAB82532_ISR1_XPR)) 244 return; 245 #endif 246 247 if (!(readb(&up->regs->r.star) & SAB82532_STAR_XFW)) 248 return; 249 250 set_bit(SAB82532_XPR, &up->irqflags); 251 sunsab_tx_idle(up); 252 253 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) { 254 up->interrupt_mask1 |= SAB82532_IMR1_XPR; 255 writeb(up->interrupt_mask1, &up->regs->w.imr1); 256 return; 257 } 258 259 up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR); 260 writeb(up->interrupt_mask1, &up->regs->w.imr1); 261 clear_bit(SAB82532_ALLS, &up->irqflags); 262 263 /* Stuff 32 bytes into Transmit FIFO. */ 264 clear_bit(SAB82532_XPR, &up->irqflags); 265 for (i = 0; i < up->port.fifosize; i++) { 266 writeb(xmit->buf[xmit->tail], 267 &up->regs->w.xfifo[i]); 268 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 269 up->port.icount.tx++; 270 if (uart_circ_empty(xmit)) 271 break; 272 } 273 274 /* Issue a Transmit Frame command. */ 275 sunsab_cec_wait(up); 276 writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr); 277 278 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 279 uart_write_wakeup(&up->port); 280 281 if (uart_circ_empty(xmit)) 282 sunsab_stop_tx(&up->port); 283 } 284 285 static void check_status(struct uart_sunsab_port *up, 286 union sab82532_irq_status *stat) 287 { 288 if (stat->sreg.isr0 & SAB82532_ISR0_CDSC) 289 uart_handle_dcd_change(&up->port, 290 !(readb(&up->regs->r.vstr) & SAB82532_VSTR_CD)); 291 292 if (stat->sreg.isr1 & SAB82532_ISR1_CSC) 293 uart_handle_cts_change(&up->port, 294 (readb(&up->regs->r.star) & SAB82532_STAR_CTS)); 295 296 if ((readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ^ up->dsr) { 297 up->dsr = (readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ? 0 : 1; 298 up->port.icount.dsr++; 299 } 300 301 wake_up_interruptible(&up->port.state->port.delta_msr_wait); 302 } 303 304 static irqreturn_t sunsab_interrupt(int irq, void *dev_id) 305 { 306 struct uart_sunsab_port *up = dev_id; 307 struct tty_struct *tty; 308 union sab82532_irq_status status; 309 unsigned long flags; 310 unsigned char gis; 311 312 spin_lock_irqsave(&up->port.lock, flags); 313 314 status.stat = 0; 315 gis = readb(&up->regs->r.gis) >> up->gis_shift; 316 if (gis & 1) 317 status.sreg.isr0 = readb(&up->regs->r.isr0); 318 if (gis & 2) 319 status.sreg.isr1 = readb(&up->regs->r.isr1); 320 321 tty = NULL; 322 if (status.stat) { 323 if ((status.sreg.isr0 & (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME | 324 SAB82532_ISR0_RFO | SAB82532_ISR0_RPF)) || 325 (status.sreg.isr1 & SAB82532_ISR1_BRK)) 326 tty = receive_chars(up, &status); 327 if ((status.sreg.isr0 & SAB82532_ISR0_CDSC) || 328 (status.sreg.isr1 & SAB82532_ISR1_CSC)) 329 check_status(up, &status); 330 if (status.sreg.isr1 & (SAB82532_ISR1_ALLS | SAB82532_ISR1_XPR)) 331 transmit_chars(up, &status); 332 } 333 334 spin_unlock_irqrestore(&up->port.lock, flags); 335 336 if (tty) 337 tty_flip_buffer_push(tty); 338 339 return IRQ_HANDLED; 340 } 341 342 /* port->lock is not held. */ 343 static unsigned int sunsab_tx_empty(struct uart_port *port) 344 { 345 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port; 346 int ret; 347 348 /* Do not need a lock for a state test like this. */ 349 if (test_bit(SAB82532_ALLS, &up->irqflags)) 350 ret = TIOCSER_TEMT; 351 else 352 ret = 0; 353 354 return ret; 355 } 356 357 /* port->lock held by caller. */ 358 static void sunsab_set_mctrl(struct uart_port *port, unsigned int mctrl) 359 { 360 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port; 361 362 if (mctrl & TIOCM_RTS) { 363 up->cached_mode &= ~SAB82532_MODE_FRTS; 364 up->cached_mode |= SAB82532_MODE_RTS; 365 } else { 366 up->cached_mode |= (SAB82532_MODE_FRTS | 367 SAB82532_MODE_RTS); 368 } 369 if (mctrl & TIOCM_DTR) { 370 up->cached_pvr &= ~(up->pvr_dtr_bit); 371 } else { 372 up->cached_pvr |= up->pvr_dtr_bit; 373 } 374 375 set_bit(SAB82532_REGS_PENDING, &up->irqflags); 376 if (test_bit(SAB82532_XPR, &up->irqflags)) 377 sunsab_tx_idle(up); 378 } 379 380 /* port->lock is held by caller and interrupts are disabled. */ 381 static unsigned int sunsab_get_mctrl(struct uart_port *port) 382 { 383 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port; 384 unsigned char val; 385 unsigned int result; 386 387 result = 0; 388 389 val = readb(&up->regs->r.pvr); 390 result |= (val & up->pvr_dsr_bit) ? 0 : TIOCM_DSR; 391 392 val = readb(&up->regs->r.vstr); 393 result |= (val & SAB82532_VSTR_CD) ? 0 : TIOCM_CAR; 394 395 val = readb(&up->regs->r.star); 396 result |= (val & SAB82532_STAR_CTS) ? TIOCM_CTS : 0; 397 398 return result; 399 } 400 401 /* port->lock held by caller. */ 402 static void sunsab_stop_tx(struct uart_port *port) 403 { 404 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port; 405 406 up->interrupt_mask1 |= SAB82532_IMR1_XPR; 407 writeb(up->interrupt_mask1, &up->regs->w.imr1); 408 } 409 410 /* port->lock held by caller. */ 411 static void sunsab_tx_idle(struct uart_sunsab_port *up) 412 { 413 if (test_bit(SAB82532_REGS_PENDING, &up->irqflags)) { 414 u8 tmp; 415 416 clear_bit(SAB82532_REGS_PENDING, &up->irqflags); 417 writeb(up->cached_mode, &up->regs->rw.mode); 418 writeb(up->cached_pvr, &up->regs->rw.pvr); 419 writeb(up->cached_dafo, &up->regs->w.dafo); 420 421 writeb(up->cached_ebrg & 0xff, &up->regs->w.bgr); 422 tmp = readb(&up->regs->rw.ccr2); 423 tmp &= ~0xc0; 424 tmp |= (up->cached_ebrg >> 2) & 0xc0; 425 writeb(tmp, &up->regs->rw.ccr2); 426 } 427 } 428 429 /* port->lock held by caller. */ 430 static void sunsab_start_tx(struct uart_port *port) 431 { 432 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port; 433 struct circ_buf *xmit = &up->port.state->xmit; 434 int i; 435 436 up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR); 437 writeb(up->interrupt_mask1, &up->regs->w.imr1); 438 439 if (!test_bit(SAB82532_XPR, &up->irqflags)) 440 return; 441 442 clear_bit(SAB82532_ALLS, &up->irqflags); 443 clear_bit(SAB82532_XPR, &up->irqflags); 444 445 for (i = 0; i < up->port.fifosize; i++) { 446 writeb(xmit->buf[xmit->tail], 447 &up->regs->w.xfifo[i]); 448 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 449 up->port.icount.tx++; 450 if (uart_circ_empty(xmit)) 451 break; 452 } 453 454 /* Issue a Transmit Frame command. */ 455 sunsab_cec_wait(up); 456 writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr); 457 } 458 459 /* port->lock is not held. */ 460 static void sunsab_send_xchar(struct uart_port *port, char ch) 461 { 462 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port; 463 unsigned long flags; 464 465 spin_lock_irqsave(&up->port.lock, flags); 466 467 sunsab_tec_wait(up); 468 writeb(ch, &up->regs->w.tic); 469 470 spin_unlock_irqrestore(&up->port.lock, flags); 471 } 472 473 /* port->lock held by caller. */ 474 static void sunsab_stop_rx(struct uart_port *port) 475 { 476 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port; 477 478 up->interrupt_mask0 |= SAB82532_IMR0_TCD; 479 writeb(up->interrupt_mask1, &up->regs->w.imr0); 480 } 481 482 /* port->lock held by caller. */ 483 static void sunsab_enable_ms(struct uart_port *port) 484 { 485 /* For now we always receive these interrupts. */ 486 } 487 488 /* port->lock is not held. */ 489 static void sunsab_break_ctl(struct uart_port *port, int break_state) 490 { 491 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port; 492 unsigned long flags; 493 unsigned char val; 494 495 spin_lock_irqsave(&up->port.lock, flags); 496 497 val = up->cached_dafo; 498 if (break_state) 499 val |= SAB82532_DAFO_XBRK; 500 else 501 val &= ~SAB82532_DAFO_XBRK; 502 up->cached_dafo = val; 503 504 set_bit(SAB82532_REGS_PENDING, &up->irqflags); 505 if (test_bit(SAB82532_XPR, &up->irqflags)) 506 sunsab_tx_idle(up); 507 508 spin_unlock_irqrestore(&up->port.lock, flags); 509 } 510 511 /* port->lock is not held. */ 512 static int sunsab_startup(struct uart_port *port) 513 { 514 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port; 515 unsigned long flags; 516 unsigned char tmp; 517 int err = request_irq(up->port.irq, sunsab_interrupt, 518 IRQF_SHARED, "sab", up); 519 if (err) 520 return err; 521 522 spin_lock_irqsave(&up->port.lock, flags); 523 524 /* 525 * Wait for any commands or immediate characters 526 */ 527 sunsab_cec_wait(up); 528 sunsab_tec_wait(up); 529 530 /* 531 * Clear the FIFO buffers. 532 */ 533 writeb(SAB82532_CMDR_RRES, &up->regs->w.cmdr); 534 sunsab_cec_wait(up); 535 writeb(SAB82532_CMDR_XRES, &up->regs->w.cmdr); 536 537 /* 538 * Clear the interrupt registers. 539 */ 540 (void) readb(&up->regs->r.isr0); 541 (void) readb(&up->regs->r.isr1); 542 543 /* 544 * Now, initialize the UART 545 */ 546 writeb(0, &up->regs->w.ccr0); /* power-down */ 547 writeb(SAB82532_CCR0_MCE | SAB82532_CCR0_SC_NRZ | 548 SAB82532_CCR0_SM_ASYNC, &up->regs->w.ccr0); 549 writeb(SAB82532_CCR1_ODS | SAB82532_CCR1_BCR | 7, &up->regs->w.ccr1); 550 writeb(SAB82532_CCR2_BDF | SAB82532_CCR2_SSEL | 551 SAB82532_CCR2_TOE, &up->regs->w.ccr2); 552 writeb(0, &up->regs->w.ccr3); 553 writeb(SAB82532_CCR4_MCK4 | SAB82532_CCR4_EBRG, &up->regs->w.ccr4); 554 up->cached_mode = (SAB82532_MODE_RTS | SAB82532_MODE_FCTS | 555 SAB82532_MODE_RAC); 556 writeb(up->cached_mode, &up->regs->w.mode); 557 writeb(SAB82532_RFC_DPS|SAB82532_RFC_RFTH_32, &up->regs->w.rfc); 558 559 tmp = readb(&up->regs->rw.ccr0); 560 tmp |= SAB82532_CCR0_PU; /* power-up */ 561 writeb(tmp, &up->regs->rw.ccr0); 562 563 /* 564 * Finally, enable interrupts 565 */ 566 up->interrupt_mask0 = (SAB82532_IMR0_PERR | SAB82532_IMR0_FERR | 567 SAB82532_IMR0_PLLA); 568 writeb(up->interrupt_mask0, &up->regs->w.imr0); 569 up->interrupt_mask1 = (SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS | 570 SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN | 571 SAB82532_IMR1_CSC | SAB82532_IMR1_XON | 572 SAB82532_IMR1_XPR); 573 writeb(up->interrupt_mask1, &up->regs->w.imr1); 574 set_bit(SAB82532_ALLS, &up->irqflags); 575 set_bit(SAB82532_XPR, &up->irqflags); 576 577 spin_unlock_irqrestore(&up->port.lock, flags); 578 579 return 0; 580 } 581 582 /* port->lock is not held. */ 583 static void sunsab_shutdown(struct uart_port *port) 584 { 585 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port; 586 unsigned long flags; 587 588 spin_lock_irqsave(&up->port.lock, flags); 589 590 /* Disable Interrupts */ 591 up->interrupt_mask0 = 0xff; 592 writeb(up->interrupt_mask0, &up->regs->w.imr0); 593 up->interrupt_mask1 = 0xff; 594 writeb(up->interrupt_mask1, &up->regs->w.imr1); 595 596 /* Disable break condition */ 597 up->cached_dafo = readb(&up->regs->rw.dafo); 598 up->cached_dafo &= ~SAB82532_DAFO_XBRK; 599 writeb(up->cached_dafo, &up->regs->rw.dafo); 600 601 /* Disable Receiver */ 602 up->cached_mode &= ~SAB82532_MODE_RAC; 603 writeb(up->cached_mode, &up->regs->rw.mode); 604 605 /* 606 * XXX FIXME 607 * 608 * If the chip is powered down here the system hangs/crashes during 609 * reboot or shutdown. This needs to be investigated further, 610 * similar behaviour occurs in 2.4 when the driver is configured 611 * as a module only. One hint may be that data is sometimes 612 * transmitted at 9600 baud during shutdown (regardless of the 613 * speed the chip was configured for when the port was open). 614 */ 615 #if 0 616 /* Power Down */ 617 tmp = readb(&up->regs->rw.ccr0); 618 tmp &= ~SAB82532_CCR0_PU; 619 writeb(tmp, &up->regs->rw.ccr0); 620 #endif 621 622 spin_unlock_irqrestore(&up->port.lock, flags); 623 free_irq(up->port.irq, up); 624 } 625 626 /* 627 * This is used to figure out the divisor speeds. 628 * 629 * The formula is: Baud = SAB_BASE_BAUD / ((N + 1) * (1 << M)), 630 * 631 * with 0 <= N < 64 and 0 <= M < 16 632 */ 633 634 static void calc_ebrg(int baud, int *n_ret, int *m_ret) 635 { 636 int n, m; 637 638 if (baud == 0) { 639 *n_ret = 0; 640 *m_ret = 0; 641 return; 642 } 643 644 /* 645 * We scale numbers by 10 so that we get better accuracy 646 * without having to use floating point. Here we increment m 647 * until n is within the valid range. 648 */ 649 n = (SAB_BASE_BAUD * 10) / baud; 650 m = 0; 651 while (n >= 640) { 652 n = n / 2; 653 m++; 654 } 655 n = (n+5) / 10; 656 /* 657 * We try very hard to avoid speeds with M == 0 since they may 658 * not work correctly for XTAL frequences above 10 MHz. 659 */ 660 if ((m == 0) && ((n & 1) == 0)) { 661 n = n / 2; 662 m++; 663 } 664 *n_ret = n - 1; 665 *m_ret = m; 666 } 667 668 /* Internal routine, port->lock is held and local interrupts are disabled. */ 669 static void sunsab_convert_to_sab(struct uart_sunsab_port *up, unsigned int cflag, 670 unsigned int iflag, unsigned int baud, 671 unsigned int quot) 672 { 673 unsigned char dafo; 674 int bits, n, m; 675 676 /* Byte size and parity */ 677 switch (cflag & CSIZE) { 678 case CS5: dafo = SAB82532_DAFO_CHL5; bits = 7; break; 679 case CS6: dafo = SAB82532_DAFO_CHL6; bits = 8; break; 680 case CS7: dafo = SAB82532_DAFO_CHL7; bits = 9; break; 681 case CS8: dafo = SAB82532_DAFO_CHL8; bits = 10; break; 682 /* Never happens, but GCC is too dumb to figure it out */ 683 default: dafo = SAB82532_DAFO_CHL5; bits = 7; break; 684 } 685 686 if (cflag & CSTOPB) { 687 dafo |= SAB82532_DAFO_STOP; 688 bits++; 689 } 690 691 if (cflag & PARENB) { 692 dafo |= SAB82532_DAFO_PARE; 693 bits++; 694 } 695 696 if (cflag & PARODD) { 697 dafo |= SAB82532_DAFO_PAR_ODD; 698 } else { 699 dafo |= SAB82532_DAFO_PAR_EVEN; 700 } 701 up->cached_dafo = dafo; 702 703 calc_ebrg(baud, &n, &m); 704 705 up->cached_ebrg = n | (m << 6); 706 707 up->tec_timeout = (10 * 1000000) / baud; 708 up->cec_timeout = up->tec_timeout >> 2; 709 710 /* CTS flow control flags */ 711 /* We encode read_status_mask and ignore_status_mask like so: 712 * 713 * --------------------- 714 * | ... | ISR1 | ISR0 | 715 * --------------------- 716 * .. 15 8 7 0 717 */ 718 719 up->port.read_status_mask = (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME | 720 SAB82532_ISR0_RFO | SAB82532_ISR0_RPF | 721 SAB82532_ISR0_CDSC); 722 up->port.read_status_mask |= (SAB82532_ISR1_CSC | 723 SAB82532_ISR1_ALLS | 724 SAB82532_ISR1_XPR) << 8; 725 if (iflag & INPCK) 726 up->port.read_status_mask |= (SAB82532_ISR0_PERR | 727 SAB82532_ISR0_FERR); 728 if (iflag & (BRKINT | PARMRK)) 729 up->port.read_status_mask |= (SAB82532_ISR1_BRK << 8); 730 731 /* 732 * Characteres to ignore 733 */ 734 up->port.ignore_status_mask = 0; 735 if (iflag & IGNPAR) 736 up->port.ignore_status_mask |= (SAB82532_ISR0_PERR | 737 SAB82532_ISR0_FERR); 738 if (iflag & IGNBRK) { 739 up->port.ignore_status_mask |= (SAB82532_ISR1_BRK << 8); 740 /* 741 * If we're ignoring parity and break indicators, 742 * ignore overruns too (for real raw support). 743 */ 744 if (iflag & IGNPAR) 745 up->port.ignore_status_mask |= SAB82532_ISR0_RFO; 746 } 747 748 /* 749 * ignore all characters if CREAD is not set 750 */ 751 if ((cflag & CREAD) == 0) 752 up->port.ignore_status_mask |= (SAB82532_ISR0_RPF | 753 SAB82532_ISR0_TCD); 754 755 uart_update_timeout(&up->port, cflag, 756 (up->port.uartclk / (16 * quot))); 757 758 /* Now schedule a register update when the chip's 759 * transmitter is idle. 760 */ 761 up->cached_mode |= SAB82532_MODE_RAC; 762 set_bit(SAB82532_REGS_PENDING, &up->irqflags); 763 if (test_bit(SAB82532_XPR, &up->irqflags)) 764 sunsab_tx_idle(up); 765 } 766 767 /* port->lock is not held. */ 768 static void sunsab_set_termios(struct uart_port *port, struct ktermios *termios, 769 struct ktermios *old) 770 { 771 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port; 772 unsigned long flags; 773 unsigned int baud = uart_get_baud_rate(port, termios, old, 0, 4000000); 774 unsigned int quot = uart_get_divisor(port, baud); 775 776 spin_lock_irqsave(&up->port.lock, flags); 777 sunsab_convert_to_sab(up, termios->c_cflag, termios->c_iflag, baud, quot); 778 spin_unlock_irqrestore(&up->port.lock, flags); 779 } 780 781 static const char *sunsab_type(struct uart_port *port) 782 { 783 struct uart_sunsab_port *up = (void *)port; 784 static char buf[36]; 785 786 sprintf(buf, "SAB82532 %s", sab82532_version[up->type]); 787 return buf; 788 } 789 790 static void sunsab_release_port(struct uart_port *port) 791 { 792 } 793 794 static int sunsab_request_port(struct uart_port *port) 795 { 796 return 0; 797 } 798 799 static void sunsab_config_port(struct uart_port *port, int flags) 800 { 801 } 802 803 static int sunsab_verify_port(struct uart_port *port, struct serial_struct *ser) 804 { 805 return -EINVAL; 806 } 807 808 static struct uart_ops sunsab_pops = { 809 .tx_empty = sunsab_tx_empty, 810 .set_mctrl = sunsab_set_mctrl, 811 .get_mctrl = sunsab_get_mctrl, 812 .stop_tx = sunsab_stop_tx, 813 .start_tx = sunsab_start_tx, 814 .send_xchar = sunsab_send_xchar, 815 .stop_rx = sunsab_stop_rx, 816 .enable_ms = sunsab_enable_ms, 817 .break_ctl = sunsab_break_ctl, 818 .startup = sunsab_startup, 819 .shutdown = sunsab_shutdown, 820 .set_termios = sunsab_set_termios, 821 .type = sunsab_type, 822 .release_port = sunsab_release_port, 823 .request_port = sunsab_request_port, 824 .config_port = sunsab_config_port, 825 .verify_port = sunsab_verify_port, 826 }; 827 828 static struct uart_driver sunsab_reg = { 829 .owner = THIS_MODULE, 830 .driver_name = "sunsab", 831 .dev_name = "ttyS", 832 .major = TTY_MAJOR, 833 }; 834 835 static struct uart_sunsab_port *sunsab_ports; 836 837 #ifdef CONFIG_SERIAL_SUNSAB_CONSOLE 838 839 static void sunsab_console_putchar(struct uart_port *port, int c) 840 { 841 struct uart_sunsab_port *up = (struct uart_sunsab_port *)port; 842 843 sunsab_tec_wait(up); 844 writeb(c, &up->regs->w.tic); 845 } 846 847 static void sunsab_console_write(struct console *con, const char *s, unsigned n) 848 { 849 struct uart_sunsab_port *up = &sunsab_ports[con->index]; 850 unsigned long flags; 851 int locked = 1; 852 853 local_irq_save(flags); 854 if (up->port.sysrq) { 855 locked = 0; 856 } else if (oops_in_progress) { 857 locked = spin_trylock(&up->port.lock); 858 } else 859 spin_lock(&up->port.lock); 860 861 uart_console_write(&up->port, s, n, sunsab_console_putchar); 862 sunsab_tec_wait(up); 863 864 if (locked) 865 spin_unlock(&up->port.lock); 866 local_irq_restore(flags); 867 } 868 869 static int sunsab_console_setup(struct console *con, char *options) 870 { 871 struct uart_sunsab_port *up = &sunsab_ports[con->index]; 872 unsigned long flags; 873 unsigned int baud, quot; 874 875 /* 876 * The console framework calls us for each and every port 877 * registered. Defer the console setup until the requested 878 * port has been properly discovered. A bit of a hack, 879 * though... 880 */ 881 if (up->port.type != PORT_SUNSAB) 882 return -1; 883 884 printk("Console: ttyS%d (SAB82532)\n", 885 (sunsab_reg.minor - 64) + con->index); 886 887 sunserial_console_termios(con, up->port.dev->of_node); 888 889 switch (con->cflag & CBAUD) { 890 case B150: baud = 150; break; 891 case B300: baud = 300; break; 892 case B600: baud = 600; break; 893 case B1200: baud = 1200; break; 894 case B2400: baud = 2400; break; 895 case B4800: baud = 4800; break; 896 default: case B9600: baud = 9600; break; 897 case B19200: baud = 19200; break; 898 case B38400: baud = 38400; break; 899 case B57600: baud = 57600; break; 900 case B115200: baud = 115200; break; 901 case B230400: baud = 230400; break; 902 case B460800: baud = 460800; break; 903 }; 904 905 /* 906 * Temporary fix. 907 */ 908 spin_lock_init(&up->port.lock); 909 910 /* 911 * Initialize the hardware 912 */ 913 sunsab_startup(&up->port); 914 915 spin_lock_irqsave(&up->port.lock, flags); 916 917 /* 918 * Finally, enable interrupts 919 */ 920 up->interrupt_mask0 = SAB82532_IMR0_PERR | SAB82532_IMR0_FERR | 921 SAB82532_IMR0_PLLA | SAB82532_IMR0_CDSC; 922 writeb(up->interrupt_mask0, &up->regs->w.imr0); 923 up->interrupt_mask1 = SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS | 924 SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN | 925 SAB82532_IMR1_CSC | SAB82532_IMR1_XON | 926 SAB82532_IMR1_XPR; 927 writeb(up->interrupt_mask1, &up->regs->w.imr1); 928 929 quot = uart_get_divisor(&up->port, baud); 930 sunsab_convert_to_sab(up, con->cflag, 0, baud, quot); 931 sunsab_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS); 932 933 spin_unlock_irqrestore(&up->port.lock, flags); 934 935 return 0; 936 } 937 938 static struct console sunsab_console = { 939 .name = "ttyS", 940 .write = sunsab_console_write, 941 .device = uart_console_device, 942 .setup = sunsab_console_setup, 943 .flags = CON_PRINTBUFFER, 944 .index = -1, 945 .data = &sunsab_reg, 946 }; 947 948 static inline struct console *SUNSAB_CONSOLE(void) 949 { 950 return &sunsab_console; 951 } 952 #else 953 #define SUNSAB_CONSOLE() (NULL) 954 #define sunsab_console_init() do { } while (0) 955 #endif 956 957 static int sunsab_init_one(struct uart_sunsab_port *up, 958 struct platform_device *op, 959 unsigned long offset, 960 int line) 961 { 962 up->port.line = line; 963 up->port.dev = &op->dev; 964 965 up->port.mapbase = op->resource[0].start + offset; 966 up->port.membase = of_ioremap(&op->resource[0], offset, 967 sizeof(union sab82532_async_regs), 968 "sab"); 969 if (!up->port.membase) 970 return -ENOMEM; 971 up->regs = (union sab82532_async_regs __iomem *) up->port.membase; 972 973 up->port.irq = op->archdata.irqs[0]; 974 975 up->port.fifosize = SAB82532_XMIT_FIFO_SIZE; 976 up->port.iotype = UPIO_MEM; 977 978 writeb(SAB82532_IPC_IC_ACT_LOW, &up->regs->w.ipc); 979 980 up->port.ops = &sunsab_pops; 981 up->port.type = PORT_SUNSAB; 982 up->port.uartclk = SAB_BASE_BAUD; 983 984 up->type = readb(&up->regs->r.vstr) & 0x0f; 985 writeb(~((1 << 1) | (1 << 2) | (1 << 4)), &up->regs->w.pcr); 986 writeb(0xff, &up->regs->w.pim); 987 if ((up->port.line & 0x1) == 0) { 988 up->pvr_dsr_bit = (1 << 0); 989 up->pvr_dtr_bit = (1 << 1); 990 up->gis_shift = 2; 991 } else { 992 up->pvr_dsr_bit = (1 << 3); 993 up->pvr_dtr_bit = (1 << 2); 994 up->gis_shift = 0; 995 } 996 up->cached_pvr = (1 << 1) | (1 << 2) | (1 << 4); 997 writeb(up->cached_pvr, &up->regs->w.pvr); 998 up->cached_mode = readb(&up->regs->rw.mode); 999 up->cached_mode |= SAB82532_MODE_FRTS; 1000 writeb(up->cached_mode, &up->regs->rw.mode); 1001 up->cached_mode |= SAB82532_MODE_RTS; 1002 writeb(up->cached_mode, &up->regs->rw.mode); 1003 1004 up->tec_timeout = SAB82532_MAX_TEC_TIMEOUT; 1005 up->cec_timeout = SAB82532_MAX_CEC_TIMEOUT; 1006 1007 return 0; 1008 } 1009 1010 static int sab_probe(struct platform_device *op) 1011 { 1012 static int inst; 1013 struct uart_sunsab_port *up; 1014 int err; 1015 1016 up = &sunsab_ports[inst * 2]; 1017 1018 err = sunsab_init_one(&up[0], op, 1019 0, 1020 (inst * 2) + 0); 1021 if (err) 1022 goto out; 1023 1024 err = sunsab_init_one(&up[1], op, 1025 sizeof(union sab82532_async_regs), 1026 (inst * 2) + 1); 1027 if (err) 1028 goto out1; 1029 1030 sunserial_console_match(SUNSAB_CONSOLE(), op->dev.of_node, 1031 &sunsab_reg, up[0].port.line, 1032 false); 1033 1034 sunserial_console_match(SUNSAB_CONSOLE(), op->dev.of_node, 1035 &sunsab_reg, up[1].port.line, 1036 false); 1037 1038 err = uart_add_one_port(&sunsab_reg, &up[0].port); 1039 if (err) 1040 goto out2; 1041 1042 err = uart_add_one_port(&sunsab_reg, &up[1].port); 1043 if (err) 1044 goto out3; 1045 1046 dev_set_drvdata(&op->dev, &up[0]); 1047 1048 inst++; 1049 1050 return 0; 1051 1052 out3: 1053 uart_remove_one_port(&sunsab_reg, &up[0].port); 1054 out2: 1055 of_iounmap(&op->resource[0], 1056 up[1].port.membase, 1057 sizeof(union sab82532_async_regs)); 1058 out1: 1059 of_iounmap(&op->resource[0], 1060 up[0].port.membase, 1061 sizeof(union sab82532_async_regs)); 1062 out: 1063 return err; 1064 } 1065 1066 static int sab_remove(struct platform_device *op) 1067 { 1068 struct uart_sunsab_port *up = dev_get_drvdata(&op->dev); 1069 1070 uart_remove_one_port(&sunsab_reg, &up[1].port); 1071 uart_remove_one_port(&sunsab_reg, &up[0].port); 1072 of_iounmap(&op->resource[0], 1073 up[1].port.membase, 1074 sizeof(union sab82532_async_regs)); 1075 of_iounmap(&op->resource[0], 1076 up[0].port.membase, 1077 sizeof(union sab82532_async_regs)); 1078 1079 dev_set_drvdata(&op->dev, NULL); 1080 1081 return 0; 1082 } 1083 1084 static const struct of_device_id sab_match[] = { 1085 { 1086 .name = "se", 1087 }, 1088 { 1089 .name = "serial", 1090 .compatible = "sab82532", 1091 }, 1092 {}, 1093 }; 1094 MODULE_DEVICE_TABLE(of, sab_match); 1095 1096 static struct platform_driver sab_driver = { 1097 .driver = { 1098 .name = "sab", 1099 .owner = THIS_MODULE, 1100 .of_match_table = sab_match, 1101 }, 1102 .probe = sab_probe, 1103 .remove = sab_remove, 1104 }; 1105 1106 static int __init sunsab_init(void) 1107 { 1108 struct device_node *dp; 1109 int err; 1110 int num_channels = 0; 1111 1112 for_each_node_by_name(dp, "se") 1113 num_channels += 2; 1114 for_each_node_by_name(dp, "serial") { 1115 if (of_device_is_compatible(dp, "sab82532")) 1116 num_channels += 2; 1117 } 1118 1119 if (num_channels) { 1120 sunsab_ports = kzalloc(sizeof(struct uart_sunsab_port) * 1121 num_channels, GFP_KERNEL); 1122 if (!sunsab_ports) 1123 return -ENOMEM; 1124 1125 err = sunserial_register_minors(&sunsab_reg, num_channels); 1126 if (err) { 1127 kfree(sunsab_ports); 1128 sunsab_ports = NULL; 1129 1130 return err; 1131 } 1132 } 1133 1134 return platform_driver_register(&sab_driver); 1135 } 1136 1137 static void __exit sunsab_exit(void) 1138 { 1139 platform_driver_unregister(&sab_driver); 1140 if (sunsab_reg.nr) { 1141 sunserial_unregister_minors(&sunsab_reg, sunsab_reg.nr); 1142 } 1143 1144 kfree(sunsab_ports); 1145 sunsab_ports = NULL; 1146 } 1147 1148 module_init(sunsab_init); 1149 module_exit(sunsab_exit); 1150 1151 MODULE_AUTHOR("Eddie C. Dost and David S. Miller"); 1152 MODULE_DESCRIPTION("Sun SAB82532 serial port driver"); 1153 MODULE_LICENSE("GPL"); 1154