1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) Maxime Coquelin 2015 4 * Copyright (C) STMicroelectronics SA 2017 5 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com> 6 * Gerald Baeza <gerald.baeza@foss.st.com> 7 * Erwan Le Ray <erwan.leray@foss.st.com> 8 * 9 * Inspired by st-asc.c from STMicroelectronics (c) 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/console.h> 14 #include <linux/delay.h> 15 #include <linux/dma-direction.h> 16 #include <linux/dmaengine.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/io.h> 19 #include <linux/iopoll.h> 20 #include <linux/irq.h> 21 #include <linux/module.h> 22 #include <linux/of.h> 23 #include <linux/of_platform.h> 24 #include <linux/pinctrl/consumer.h> 25 #include <linux/platform_device.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/pm_wakeirq.h> 28 #include <linux/serial_core.h> 29 #include <linux/serial.h> 30 #include <linux/spinlock.h> 31 #include <linux/sysrq.h> 32 #include <linux/tty_flip.h> 33 #include <linux/tty.h> 34 35 #include "serial_mctrl_gpio.h" 36 #include "stm32-usart.h" 37 38 39 /* Register offsets */ 40 static struct stm32_usart_info __maybe_unused stm32f4_info = { 41 .ofs = { 42 .isr = 0x00, 43 .rdr = 0x04, 44 .tdr = 0x04, 45 .brr = 0x08, 46 .cr1 = 0x0c, 47 .cr2 = 0x10, 48 .cr3 = 0x14, 49 .gtpr = 0x18, 50 .rtor = UNDEF_REG, 51 .rqr = UNDEF_REG, 52 .icr = UNDEF_REG, 53 }, 54 .cfg = { 55 .uart_enable_bit = 13, 56 .has_7bits_data = false, 57 .fifosize = 1, 58 } 59 }; 60 61 static struct stm32_usart_info __maybe_unused stm32f7_info = { 62 .ofs = { 63 .cr1 = 0x00, 64 .cr2 = 0x04, 65 .cr3 = 0x08, 66 .brr = 0x0c, 67 .gtpr = 0x10, 68 .rtor = 0x14, 69 .rqr = 0x18, 70 .isr = 0x1c, 71 .icr = 0x20, 72 .rdr = 0x24, 73 .tdr = 0x28, 74 }, 75 .cfg = { 76 .uart_enable_bit = 0, 77 .has_7bits_data = true, 78 .has_swap = true, 79 .fifosize = 1, 80 } 81 }; 82 83 static struct stm32_usart_info __maybe_unused stm32h7_info = { 84 .ofs = { 85 .cr1 = 0x00, 86 .cr2 = 0x04, 87 .cr3 = 0x08, 88 .brr = 0x0c, 89 .gtpr = 0x10, 90 .rtor = 0x14, 91 .rqr = 0x18, 92 .isr = 0x1c, 93 .icr = 0x20, 94 .rdr = 0x24, 95 .tdr = 0x28, 96 }, 97 .cfg = { 98 .uart_enable_bit = 0, 99 .has_7bits_data = true, 100 .has_swap = true, 101 .has_wakeup = true, 102 .has_fifo = true, 103 .fifosize = 16, 104 } 105 }; 106 107 static void stm32_usart_stop_tx(struct uart_port *port); 108 static void stm32_usart_transmit_chars(struct uart_port *port); 109 static void __maybe_unused stm32_usart_console_putchar(struct uart_port *port, unsigned char ch); 110 111 static inline struct stm32_port *to_stm32_port(struct uart_port *port) 112 { 113 return container_of(port, struct stm32_port, port); 114 } 115 116 static void stm32_usart_set_bits(struct uart_port *port, u32 reg, u32 bits) 117 { 118 u32 val; 119 120 val = readl_relaxed(port->membase + reg); 121 val |= bits; 122 writel_relaxed(val, port->membase + reg); 123 } 124 125 static void stm32_usart_clr_bits(struct uart_port *port, u32 reg, u32 bits) 126 { 127 u32 val; 128 129 val = readl_relaxed(port->membase + reg); 130 val &= ~bits; 131 writel_relaxed(val, port->membase + reg); 132 } 133 134 static unsigned int stm32_usart_tx_empty(struct uart_port *port) 135 { 136 struct stm32_port *stm32_port = to_stm32_port(port); 137 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 138 139 if (readl_relaxed(port->membase + ofs->isr) & USART_SR_TC) 140 return TIOCSER_TEMT; 141 142 return 0; 143 } 144 145 static void stm32_usart_rs485_rts_enable(struct uart_port *port) 146 { 147 struct stm32_port *stm32_port = to_stm32_port(port); 148 struct serial_rs485 *rs485conf = &port->rs485; 149 150 if (stm32_port->hw_flow_control || 151 !(rs485conf->flags & SER_RS485_ENABLED)) 152 return; 153 154 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 155 mctrl_gpio_set(stm32_port->gpios, 156 stm32_port->port.mctrl | TIOCM_RTS); 157 } else { 158 mctrl_gpio_set(stm32_port->gpios, 159 stm32_port->port.mctrl & ~TIOCM_RTS); 160 } 161 } 162 163 static void stm32_usart_rs485_rts_disable(struct uart_port *port) 164 { 165 struct stm32_port *stm32_port = to_stm32_port(port); 166 struct serial_rs485 *rs485conf = &port->rs485; 167 168 if (stm32_port->hw_flow_control || 169 !(rs485conf->flags & SER_RS485_ENABLED)) 170 return; 171 172 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 173 mctrl_gpio_set(stm32_port->gpios, 174 stm32_port->port.mctrl & ~TIOCM_RTS); 175 } else { 176 mctrl_gpio_set(stm32_port->gpios, 177 stm32_port->port.mctrl | TIOCM_RTS); 178 } 179 } 180 181 static void stm32_usart_config_reg_rs485(u32 *cr1, u32 *cr3, u32 delay_ADE, 182 u32 delay_DDE, u32 baud) 183 { 184 u32 rs485_deat_dedt; 185 u32 rs485_deat_dedt_max = (USART_CR1_DEAT_MASK >> USART_CR1_DEAT_SHIFT); 186 bool over8; 187 188 *cr3 |= USART_CR3_DEM; 189 over8 = *cr1 & USART_CR1_OVER8; 190 191 *cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK); 192 193 if (over8) 194 rs485_deat_dedt = delay_ADE * baud * 8; 195 else 196 rs485_deat_dedt = delay_ADE * baud * 16; 197 198 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000); 199 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ? 200 rs485_deat_dedt_max : rs485_deat_dedt; 201 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEAT_SHIFT) & 202 USART_CR1_DEAT_MASK; 203 *cr1 |= rs485_deat_dedt; 204 205 if (over8) 206 rs485_deat_dedt = delay_DDE * baud * 8; 207 else 208 rs485_deat_dedt = delay_DDE * baud * 16; 209 210 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000); 211 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ? 212 rs485_deat_dedt_max : rs485_deat_dedt; 213 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEDT_SHIFT) & 214 USART_CR1_DEDT_MASK; 215 *cr1 |= rs485_deat_dedt; 216 } 217 218 static int stm32_usart_config_rs485(struct uart_port *port, struct ktermios *termios, 219 struct serial_rs485 *rs485conf) 220 { 221 struct stm32_port *stm32_port = to_stm32_port(port); 222 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 223 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 224 u32 usartdiv, baud, cr1, cr3; 225 bool over8; 226 227 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 228 229 rs485conf->flags |= SER_RS485_RX_DURING_TX; 230 231 if (rs485conf->flags & SER_RS485_ENABLED) { 232 cr1 = readl_relaxed(port->membase + ofs->cr1); 233 cr3 = readl_relaxed(port->membase + ofs->cr3); 234 usartdiv = readl_relaxed(port->membase + ofs->brr); 235 usartdiv = usartdiv & GENMASK(15, 0); 236 over8 = cr1 & USART_CR1_OVER8; 237 238 if (over8) 239 usartdiv = usartdiv | (usartdiv & GENMASK(4, 0)) 240 << USART_BRR_04_R_SHIFT; 241 242 baud = DIV_ROUND_CLOSEST(port->uartclk, usartdiv); 243 stm32_usart_config_reg_rs485(&cr1, &cr3, 244 rs485conf->delay_rts_before_send, 245 rs485conf->delay_rts_after_send, 246 baud); 247 248 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) 249 cr3 &= ~USART_CR3_DEP; 250 else 251 cr3 |= USART_CR3_DEP; 252 253 writel_relaxed(cr3, port->membase + ofs->cr3); 254 writel_relaxed(cr1, port->membase + ofs->cr1); 255 } else { 256 stm32_usart_clr_bits(port, ofs->cr3, 257 USART_CR3_DEM | USART_CR3_DEP); 258 stm32_usart_clr_bits(port, ofs->cr1, 259 USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK); 260 } 261 262 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 263 264 /* Adjust RTS polarity in case it's driven in software */ 265 if (stm32_usart_tx_empty(port)) 266 stm32_usart_rs485_rts_disable(port); 267 else 268 stm32_usart_rs485_rts_enable(port); 269 270 return 0; 271 } 272 273 static int stm32_usart_init_rs485(struct uart_port *port, 274 struct platform_device *pdev) 275 { 276 struct serial_rs485 *rs485conf = &port->rs485; 277 278 rs485conf->flags = 0; 279 rs485conf->delay_rts_before_send = 0; 280 rs485conf->delay_rts_after_send = 0; 281 282 if (!pdev->dev.of_node) 283 return -ENODEV; 284 285 return uart_get_rs485_mode(port); 286 } 287 288 static bool stm32_usart_rx_dma_enabled(struct uart_port *port) 289 { 290 struct stm32_port *stm32_port = to_stm32_port(port); 291 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 292 293 if (!stm32_port->rx_ch) 294 return false; 295 296 return !!(readl_relaxed(port->membase + ofs->cr3) & USART_CR3_DMAR); 297 } 298 299 /* Return true when data is pending (in pio mode), and false when no data is pending. */ 300 static bool stm32_usart_pending_rx_pio(struct uart_port *port, u32 *sr) 301 { 302 struct stm32_port *stm32_port = to_stm32_port(port); 303 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 304 305 *sr = readl_relaxed(port->membase + ofs->isr); 306 /* Get pending characters in RDR or FIFO */ 307 if (*sr & USART_SR_RXNE) { 308 /* Get all pending characters from the RDR or the FIFO when using interrupts */ 309 if (!stm32_usart_rx_dma_enabled(port)) 310 return true; 311 312 /* Handle only RX data errors when using DMA */ 313 if (*sr & USART_SR_ERR_MASK) 314 return true; 315 } 316 317 return false; 318 } 319 320 static unsigned long stm32_usart_get_char_pio(struct uart_port *port) 321 { 322 struct stm32_port *stm32_port = to_stm32_port(port); 323 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 324 unsigned long c; 325 326 c = readl_relaxed(port->membase + ofs->rdr); 327 /* Apply RDR data mask */ 328 c &= stm32_port->rdr_mask; 329 330 return c; 331 } 332 333 static unsigned int stm32_usart_receive_chars_pio(struct uart_port *port) 334 { 335 struct stm32_port *stm32_port = to_stm32_port(port); 336 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 337 unsigned long c; 338 unsigned int size = 0; 339 u32 sr; 340 char flag; 341 342 while (stm32_usart_pending_rx_pio(port, &sr)) { 343 sr |= USART_SR_DUMMY_RX; 344 flag = TTY_NORMAL; 345 346 /* 347 * Status bits has to be cleared before reading the RDR: 348 * In FIFO mode, reading the RDR will pop the next data 349 * (if any) along with its status bits into the SR. 350 * Not doing so leads to misalignement between RDR and SR, 351 * and clear status bits of the next rx data. 352 * 353 * Clear errors flags for stm32f7 and stm32h7 compatible 354 * devices. On stm32f4 compatible devices, the error bit is 355 * cleared by the sequence [read SR - read DR]. 356 */ 357 if ((sr & USART_SR_ERR_MASK) && ofs->icr != UNDEF_REG) 358 writel_relaxed(sr & USART_SR_ERR_MASK, 359 port->membase + ofs->icr); 360 361 c = stm32_usart_get_char_pio(port); 362 port->icount.rx++; 363 size++; 364 if (sr & USART_SR_ERR_MASK) { 365 if (sr & USART_SR_ORE) { 366 port->icount.overrun++; 367 } else if (sr & USART_SR_PE) { 368 port->icount.parity++; 369 } else if (sr & USART_SR_FE) { 370 /* Break detection if character is null */ 371 if (!c) { 372 port->icount.brk++; 373 if (uart_handle_break(port)) 374 continue; 375 } else { 376 port->icount.frame++; 377 } 378 } 379 380 sr &= port->read_status_mask; 381 382 if (sr & USART_SR_PE) { 383 flag = TTY_PARITY; 384 } else if (sr & USART_SR_FE) { 385 if (!c) 386 flag = TTY_BREAK; 387 else 388 flag = TTY_FRAME; 389 } 390 } 391 392 if (uart_prepare_sysrq_char(port, c)) 393 continue; 394 uart_insert_char(port, sr, USART_SR_ORE, c, flag); 395 } 396 397 return size; 398 } 399 400 static void stm32_usart_push_buffer_dma(struct uart_port *port, unsigned int dma_size) 401 { 402 struct stm32_port *stm32_port = to_stm32_port(port); 403 struct tty_port *ttyport = &stm32_port->port.state->port; 404 unsigned char *dma_start; 405 int dma_count, i; 406 407 dma_start = stm32_port->rx_buf + (RX_BUF_L - stm32_port->last_res); 408 409 /* 410 * Apply rdr_mask on buffer in order to mask parity bit. 411 * This loop is useless in cs8 mode because DMA copies only 412 * 8 bits and already ignores parity bit. 413 */ 414 if (!(stm32_port->rdr_mask == (BIT(8) - 1))) 415 for (i = 0; i < dma_size; i++) 416 *(dma_start + i) &= stm32_port->rdr_mask; 417 418 dma_count = tty_insert_flip_string(ttyport, dma_start, dma_size); 419 port->icount.rx += dma_count; 420 if (dma_count != dma_size) 421 port->icount.buf_overrun++; 422 stm32_port->last_res -= dma_count; 423 if (stm32_port->last_res == 0) 424 stm32_port->last_res = RX_BUF_L; 425 } 426 427 static unsigned int stm32_usart_receive_chars_dma(struct uart_port *port) 428 { 429 struct stm32_port *stm32_port = to_stm32_port(port); 430 unsigned int dma_size, size = 0; 431 432 /* DMA buffer is configured in cyclic mode and handles the rollback of the buffer. */ 433 if (stm32_port->rx_dma_state.residue > stm32_port->last_res) { 434 /* Conditional first part: from last_res to end of DMA buffer */ 435 dma_size = stm32_port->last_res; 436 stm32_usart_push_buffer_dma(port, dma_size); 437 size = dma_size; 438 } 439 440 dma_size = stm32_port->last_res - stm32_port->rx_dma_state.residue; 441 stm32_usart_push_buffer_dma(port, dma_size); 442 size += dma_size; 443 444 return size; 445 } 446 447 static unsigned int stm32_usart_receive_chars(struct uart_port *port, bool force_dma_flush) 448 { 449 struct stm32_port *stm32_port = to_stm32_port(port); 450 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 451 enum dma_status rx_dma_status; 452 u32 sr; 453 unsigned int size = 0; 454 455 if (stm32_usart_rx_dma_enabled(port) || force_dma_flush) { 456 rx_dma_status = dmaengine_tx_status(stm32_port->rx_ch, 457 stm32_port->rx_ch->cookie, 458 &stm32_port->rx_dma_state); 459 if (rx_dma_status == DMA_IN_PROGRESS) { 460 /* Empty DMA buffer */ 461 size = stm32_usart_receive_chars_dma(port); 462 sr = readl_relaxed(port->membase + ofs->isr); 463 if (sr & USART_SR_ERR_MASK) { 464 /* Disable DMA request line */ 465 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR); 466 467 /* Switch to PIO mode to handle the errors */ 468 size += stm32_usart_receive_chars_pio(port); 469 470 /* Switch back to DMA mode */ 471 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAR); 472 } 473 } else { 474 /* Disable RX DMA */ 475 dmaengine_terminate_async(stm32_port->rx_ch); 476 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR); 477 /* Fall back to interrupt mode */ 478 dev_dbg(port->dev, "DMA error, fallback to irq mode\n"); 479 size = stm32_usart_receive_chars_pio(port); 480 } 481 } else { 482 size = stm32_usart_receive_chars_pio(port); 483 } 484 485 return size; 486 } 487 488 static void stm32_usart_tx_dma_terminate(struct stm32_port *stm32_port) 489 { 490 dmaengine_terminate_async(stm32_port->tx_ch); 491 stm32_port->tx_dma_busy = false; 492 } 493 494 static bool stm32_usart_tx_dma_started(struct stm32_port *stm32_port) 495 { 496 /* 497 * We cannot use the function "dmaengine_tx_status" to know the 498 * status of DMA. This function does not show if the "dma complete" 499 * callback of the DMA transaction has been called. So we prefer 500 * to use "tx_dma_busy" flag to prevent dual DMA transaction at the 501 * same time. 502 */ 503 return stm32_port->tx_dma_busy; 504 } 505 506 static bool stm32_usart_tx_dma_enabled(struct stm32_port *stm32_port) 507 { 508 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 509 510 return !!(readl_relaxed(stm32_port->port.membase + ofs->cr3) & USART_CR3_DMAT); 511 } 512 513 static void stm32_usart_tx_dma_complete(void *arg) 514 { 515 struct uart_port *port = arg; 516 struct stm32_port *stm32port = to_stm32_port(port); 517 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 518 unsigned long flags; 519 520 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 521 stm32_usart_tx_dma_terminate(stm32port); 522 523 /* Let's see if we have pending data to send */ 524 spin_lock_irqsave(&port->lock, flags); 525 stm32_usart_transmit_chars(port); 526 spin_unlock_irqrestore(&port->lock, flags); 527 } 528 529 static void stm32_usart_tx_interrupt_enable(struct uart_port *port) 530 { 531 struct stm32_port *stm32_port = to_stm32_port(port); 532 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 533 534 /* 535 * Enables TX FIFO threashold irq when FIFO is enabled, 536 * or TX empty irq when FIFO is disabled 537 */ 538 if (stm32_port->fifoen && stm32_port->txftcfg >= 0) 539 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_TXFTIE); 540 else 541 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TXEIE); 542 } 543 544 static void stm32_usart_tc_interrupt_enable(struct uart_port *port) 545 { 546 struct stm32_port *stm32_port = to_stm32_port(port); 547 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 548 549 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TCIE); 550 } 551 552 static void stm32_usart_rx_dma_complete(void *arg) 553 { 554 struct uart_port *port = arg; 555 struct tty_port *tport = &port->state->port; 556 unsigned int size; 557 unsigned long flags; 558 559 spin_lock_irqsave(&port->lock, flags); 560 size = stm32_usart_receive_chars(port, false); 561 uart_unlock_and_check_sysrq_irqrestore(port, flags); 562 if (size) 563 tty_flip_buffer_push(tport); 564 } 565 566 static void stm32_usart_tx_interrupt_disable(struct uart_port *port) 567 { 568 struct stm32_port *stm32_port = to_stm32_port(port); 569 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 570 571 if (stm32_port->fifoen && stm32_port->txftcfg >= 0) 572 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_TXFTIE); 573 else 574 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_TXEIE); 575 } 576 577 static void stm32_usart_tc_interrupt_disable(struct uart_port *port) 578 { 579 struct stm32_port *stm32_port = to_stm32_port(port); 580 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 581 582 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_TCIE); 583 } 584 585 static void stm32_usart_transmit_chars_pio(struct uart_port *port) 586 { 587 struct stm32_port *stm32_port = to_stm32_port(port); 588 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 589 struct circ_buf *xmit = &port->state->xmit; 590 591 if (stm32_usart_tx_dma_enabled(stm32_port)) 592 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 593 594 while (!uart_circ_empty(xmit)) { 595 /* Check that TDR is empty before filling FIFO */ 596 if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE)) 597 break; 598 writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr); 599 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 600 port->icount.tx++; 601 } 602 603 /* rely on TXE irq (mask or unmask) for sending remaining data */ 604 if (uart_circ_empty(xmit)) 605 stm32_usart_tx_interrupt_disable(port); 606 else 607 stm32_usart_tx_interrupt_enable(port); 608 } 609 610 static void stm32_usart_transmit_chars_dma(struct uart_port *port) 611 { 612 struct stm32_port *stm32port = to_stm32_port(port); 613 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 614 struct circ_buf *xmit = &port->state->xmit; 615 struct dma_async_tx_descriptor *desc = NULL; 616 unsigned int count; 617 618 if (stm32_usart_tx_dma_started(stm32port)) { 619 if (!stm32_usart_tx_dma_enabled(stm32port)) 620 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT); 621 return; 622 } 623 624 count = uart_circ_chars_pending(xmit); 625 626 if (count > TX_BUF_L) 627 count = TX_BUF_L; 628 629 if (xmit->tail < xmit->head) { 630 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count); 631 } else { 632 size_t one = UART_XMIT_SIZE - xmit->tail; 633 size_t two; 634 635 if (one > count) 636 one = count; 637 two = count - one; 638 639 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one); 640 if (two) 641 memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two); 642 } 643 644 desc = dmaengine_prep_slave_single(stm32port->tx_ch, 645 stm32port->tx_dma_buf, 646 count, 647 DMA_MEM_TO_DEV, 648 DMA_PREP_INTERRUPT); 649 650 if (!desc) 651 goto fallback_err; 652 653 /* 654 * Set "tx_dma_busy" flag. This flag will be released when 655 * dmaengine_terminate_async will be called. This flag helps 656 * transmit_chars_dma not to start another DMA transaction 657 * if the callback of the previous is not yet called. 658 */ 659 stm32port->tx_dma_busy = true; 660 661 desc->callback = stm32_usart_tx_dma_complete; 662 desc->callback_param = port; 663 664 /* Push current DMA TX transaction in the pending queue */ 665 if (dma_submit_error(dmaengine_submit(desc))) { 666 /* dma no yet started, safe to free resources */ 667 stm32_usart_tx_dma_terminate(stm32port); 668 goto fallback_err; 669 } 670 671 /* Issue pending DMA TX requests */ 672 dma_async_issue_pending(stm32port->tx_ch); 673 674 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT); 675 676 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); 677 port->icount.tx += count; 678 return; 679 680 fallback_err: 681 stm32_usart_transmit_chars_pio(port); 682 } 683 684 static void stm32_usart_transmit_chars(struct uart_port *port) 685 { 686 struct stm32_port *stm32_port = to_stm32_port(port); 687 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 688 struct circ_buf *xmit = &port->state->xmit; 689 u32 isr; 690 int ret; 691 692 if (!stm32_port->hw_flow_control && 693 port->rs485.flags & SER_RS485_ENABLED) { 694 stm32_port->txdone = false; 695 stm32_usart_tc_interrupt_disable(port); 696 stm32_usart_rs485_rts_enable(port); 697 } 698 699 if (port->x_char) { 700 if (stm32_usart_tx_dma_started(stm32_port) && 701 stm32_usart_tx_dma_enabled(stm32_port)) 702 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 703 704 /* Check that TDR is empty before filling FIFO */ 705 ret = 706 readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, 707 isr, 708 (isr & USART_SR_TXE), 709 10, 1000); 710 if (ret) 711 dev_warn(port->dev, "1 character may be erased\n"); 712 713 writel_relaxed(port->x_char, port->membase + ofs->tdr); 714 port->x_char = 0; 715 port->icount.tx++; 716 if (stm32_usart_tx_dma_started(stm32_port)) 717 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT); 718 return; 719 } 720 721 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 722 stm32_usart_tx_interrupt_disable(port); 723 return; 724 } 725 726 if (ofs->icr == UNDEF_REG) 727 stm32_usart_clr_bits(port, ofs->isr, USART_SR_TC); 728 else 729 writel_relaxed(USART_ICR_TCCF, port->membase + ofs->icr); 730 731 if (stm32_port->tx_ch) 732 stm32_usart_transmit_chars_dma(port); 733 else 734 stm32_usart_transmit_chars_pio(port); 735 736 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 737 uart_write_wakeup(port); 738 739 if (uart_circ_empty(xmit)) { 740 stm32_usart_tx_interrupt_disable(port); 741 if (!stm32_port->hw_flow_control && 742 port->rs485.flags & SER_RS485_ENABLED) { 743 stm32_port->txdone = true; 744 stm32_usart_tc_interrupt_enable(port); 745 } 746 } 747 } 748 749 static irqreturn_t stm32_usart_interrupt(int irq, void *ptr) 750 { 751 struct uart_port *port = ptr; 752 struct tty_port *tport = &port->state->port; 753 struct stm32_port *stm32_port = to_stm32_port(port); 754 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 755 u32 sr; 756 unsigned int size; 757 758 sr = readl_relaxed(port->membase + ofs->isr); 759 760 if (!stm32_port->hw_flow_control && 761 port->rs485.flags & SER_RS485_ENABLED && 762 (sr & USART_SR_TC)) { 763 stm32_usart_tc_interrupt_disable(port); 764 stm32_usart_rs485_rts_disable(port); 765 } 766 767 if ((sr & USART_SR_RTOF) && ofs->icr != UNDEF_REG) 768 writel_relaxed(USART_ICR_RTOCF, 769 port->membase + ofs->icr); 770 771 if ((sr & USART_SR_WUF) && ofs->icr != UNDEF_REG) { 772 /* Clear wake up flag and disable wake up interrupt */ 773 writel_relaxed(USART_ICR_WUCF, 774 port->membase + ofs->icr); 775 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE); 776 if (irqd_is_wakeup_set(irq_get_irq_data(port->irq))) 777 pm_wakeup_event(tport->tty->dev, 0); 778 } 779 780 /* 781 * rx errors in dma mode has to be handled ASAP to avoid overrun as the DMA request 782 * line has been masked by HW and rx data are stacking in FIFO. 783 */ 784 if (!stm32_port->throttled) { 785 if (((sr & USART_SR_RXNE) && !stm32_usart_rx_dma_enabled(port)) || 786 ((sr & USART_SR_ERR_MASK) && stm32_usart_rx_dma_enabled(port))) { 787 spin_lock(&port->lock); 788 size = stm32_usart_receive_chars(port, false); 789 uart_unlock_and_check_sysrq(port); 790 if (size) 791 tty_flip_buffer_push(tport); 792 } 793 } 794 795 if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch)) { 796 spin_lock(&port->lock); 797 stm32_usart_transmit_chars(port); 798 spin_unlock(&port->lock); 799 } 800 801 if (stm32_usart_rx_dma_enabled(port)) 802 return IRQ_WAKE_THREAD; 803 else 804 return IRQ_HANDLED; 805 } 806 807 static irqreturn_t stm32_usart_threaded_interrupt(int irq, void *ptr) 808 { 809 struct uart_port *port = ptr; 810 struct tty_port *tport = &port->state->port; 811 struct stm32_port *stm32_port = to_stm32_port(port); 812 unsigned int size; 813 unsigned long flags; 814 815 /* Receiver timeout irq for DMA RX */ 816 if (!stm32_port->throttled) { 817 spin_lock_irqsave(&port->lock, flags); 818 size = stm32_usart_receive_chars(port, false); 819 uart_unlock_and_check_sysrq_irqrestore(port, flags); 820 if (size) 821 tty_flip_buffer_push(tport); 822 } 823 824 return IRQ_HANDLED; 825 } 826 827 static void stm32_usart_set_mctrl(struct uart_port *port, unsigned int mctrl) 828 { 829 struct stm32_port *stm32_port = to_stm32_port(port); 830 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 831 832 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) 833 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_RTSE); 834 else 835 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_RTSE); 836 837 mctrl_gpio_set(stm32_port->gpios, mctrl); 838 } 839 840 static unsigned int stm32_usart_get_mctrl(struct uart_port *port) 841 { 842 struct stm32_port *stm32_port = to_stm32_port(port); 843 unsigned int ret; 844 845 /* This routine is used to get signals of: DCD, DSR, RI, and CTS */ 846 ret = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; 847 848 return mctrl_gpio_get(stm32_port->gpios, &ret); 849 } 850 851 static void stm32_usart_enable_ms(struct uart_port *port) 852 { 853 mctrl_gpio_enable_ms(to_stm32_port(port)->gpios); 854 } 855 856 static void stm32_usart_disable_ms(struct uart_port *port) 857 { 858 mctrl_gpio_disable_ms(to_stm32_port(port)->gpios); 859 } 860 861 /* Transmit stop */ 862 static void stm32_usart_stop_tx(struct uart_port *port) 863 { 864 struct stm32_port *stm32_port = to_stm32_port(port); 865 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 866 867 stm32_usart_tx_interrupt_disable(port); 868 if (stm32_usart_tx_dma_started(stm32_port) && stm32_usart_tx_dma_enabled(stm32_port)) 869 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 870 871 stm32_usart_rs485_rts_disable(port); 872 } 873 874 /* There are probably characters waiting to be transmitted. */ 875 static void stm32_usart_start_tx(struct uart_port *port) 876 { 877 struct circ_buf *xmit = &port->state->xmit; 878 879 if (uart_circ_empty(xmit) && !port->x_char) { 880 stm32_usart_rs485_rts_disable(port); 881 return; 882 } 883 884 stm32_usart_rs485_rts_enable(port); 885 886 stm32_usart_transmit_chars(port); 887 } 888 889 /* Flush the transmit buffer. */ 890 static void stm32_usart_flush_buffer(struct uart_port *port) 891 { 892 struct stm32_port *stm32_port = to_stm32_port(port); 893 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 894 895 if (stm32_port->tx_ch) { 896 stm32_usart_tx_dma_terminate(stm32_port); 897 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 898 } 899 } 900 901 /* Throttle the remote when input buffer is about to overflow. */ 902 static void stm32_usart_throttle(struct uart_port *port) 903 { 904 struct stm32_port *stm32_port = to_stm32_port(port); 905 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 906 unsigned long flags; 907 908 spin_lock_irqsave(&port->lock, flags); 909 910 /* 911 * Disable DMA request line if enabled, so the RX data gets queued into the FIFO. 912 * Hardware flow control is triggered when RX FIFO is full. 913 */ 914 if (stm32_usart_rx_dma_enabled(port)) 915 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR); 916 917 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq); 918 if (stm32_port->cr3_irq) 919 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); 920 921 stm32_port->throttled = true; 922 spin_unlock_irqrestore(&port->lock, flags); 923 } 924 925 /* Unthrottle the remote, the input buffer can now accept data. */ 926 static void stm32_usart_unthrottle(struct uart_port *port) 927 { 928 struct stm32_port *stm32_port = to_stm32_port(port); 929 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 930 unsigned long flags; 931 932 spin_lock_irqsave(&port->lock, flags); 933 stm32_usart_set_bits(port, ofs->cr1, stm32_port->cr1_irq); 934 if (stm32_port->cr3_irq) 935 stm32_usart_set_bits(port, ofs->cr3, stm32_port->cr3_irq); 936 937 /* 938 * Switch back to DMA mode (re-enable DMA request line). 939 * Hardware flow control is stopped when FIFO is not full any more. 940 */ 941 if (stm32_port->rx_ch) 942 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAR); 943 944 stm32_port->throttled = false; 945 spin_unlock_irqrestore(&port->lock, flags); 946 } 947 948 /* Receive stop */ 949 static void stm32_usart_stop_rx(struct uart_port *port) 950 { 951 struct stm32_port *stm32_port = to_stm32_port(port); 952 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 953 954 /* Disable DMA request line. */ 955 if (stm32_port->rx_ch) 956 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR); 957 958 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq); 959 if (stm32_port->cr3_irq) 960 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); 961 } 962 963 /* Handle breaks - ignored by us */ 964 static void stm32_usart_break_ctl(struct uart_port *port, int break_state) 965 { 966 } 967 968 static int stm32_usart_start_rx_dma_cyclic(struct uart_port *port) 969 { 970 struct stm32_port *stm32_port = to_stm32_port(port); 971 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 972 struct dma_async_tx_descriptor *desc; 973 int ret; 974 975 stm32_port->last_res = RX_BUF_L; 976 /* Prepare a DMA cyclic transaction */ 977 desc = dmaengine_prep_dma_cyclic(stm32_port->rx_ch, 978 stm32_port->rx_dma_buf, 979 RX_BUF_L, RX_BUF_P, 980 DMA_DEV_TO_MEM, 981 DMA_PREP_INTERRUPT); 982 if (!desc) { 983 dev_err(port->dev, "rx dma prep cyclic failed\n"); 984 return -ENODEV; 985 } 986 987 desc->callback = stm32_usart_rx_dma_complete; 988 desc->callback_param = port; 989 990 /* Push current DMA transaction in the pending queue */ 991 ret = dma_submit_error(dmaengine_submit(desc)); 992 if (ret) { 993 dmaengine_terminate_sync(stm32_port->rx_ch); 994 return ret; 995 } 996 997 /* Issue pending DMA requests */ 998 dma_async_issue_pending(stm32_port->rx_ch); 999 1000 /* 1001 * DMA request line not re-enabled at resume when port is throttled. 1002 * It will be re-enabled by unthrottle ops. 1003 */ 1004 if (!stm32_port->throttled) 1005 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAR); 1006 1007 return 0; 1008 } 1009 1010 static int stm32_usart_startup(struct uart_port *port) 1011 { 1012 struct stm32_port *stm32_port = to_stm32_port(port); 1013 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1014 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 1015 const char *name = to_platform_device(port->dev)->name; 1016 u32 val; 1017 int ret; 1018 1019 ret = request_threaded_irq(port->irq, stm32_usart_interrupt, 1020 stm32_usart_threaded_interrupt, 1021 IRQF_ONESHOT | IRQF_NO_SUSPEND, 1022 name, port); 1023 if (ret) 1024 return ret; 1025 1026 if (stm32_port->swap) { 1027 val = readl_relaxed(port->membase + ofs->cr2); 1028 val |= USART_CR2_SWAP; 1029 writel_relaxed(val, port->membase + ofs->cr2); 1030 } 1031 1032 /* RX FIFO Flush */ 1033 if (ofs->rqr != UNDEF_REG) 1034 writel_relaxed(USART_RQR_RXFRQ, port->membase + ofs->rqr); 1035 1036 if (stm32_port->rx_ch) { 1037 ret = stm32_usart_start_rx_dma_cyclic(port); 1038 if (ret) { 1039 free_irq(port->irq, port); 1040 return ret; 1041 } 1042 } 1043 1044 /* RX enabling */ 1045 val = stm32_port->cr1_irq | USART_CR1_RE | BIT(cfg->uart_enable_bit); 1046 stm32_usart_set_bits(port, ofs->cr1, val); 1047 1048 return 0; 1049 } 1050 1051 static void stm32_usart_shutdown(struct uart_port *port) 1052 { 1053 struct stm32_port *stm32_port = to_stm32_port(port); 1054 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1055 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 1056 u32 val, isr; 1057 int ret; 1058 1059 if (stm32_usart_tx_dma_enabled(stm32_port)) 1060 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 1061 1062 if (stm32_usart_tx_dma_started(stm32_port)) 1063 stm32_usart_tx_dma_terminate(stm32_port); 1064 1065 /* Disable modem control interrupts */ 1066 stm32_usart_disable_ms(port); 1067 1068 val = USART_CR1_TXEIE | USART_CR1_TE; 1069 val |= stm32_port->cr1_irq | USART_CR1_RE; 1070 val |= BIT(cfg->uart_enable_bit); 1071 if (stm32_port->fifoen) 1072 val |= USART_CR1_FIFOEN; 1073 1074 ret = readl_relaxed_poll_timeout(port->membase + ofs->isr, 1075 isr, (isr & USART_SR_TC), 1076 10, 100000); 1077 1078 /* Send the TC error message only when ISR_TC is not set */ 1079 if (ret) 1080 dev_err(port->dev, "Transmission is not complete\n"); 1081 1082 /* Disable RX DMA. */ 1083 if (stm32_port->rx_ch) 1084 dmaengine_terminate_async(stm32_port->rx_ch); 1085 1086 /* flush RX & TX FIFO */ 1087 if (ofs->rqr != UNDEF_REG) 1088 writel_relaxed(USART_RQR_TXFRQ | USART_RQR_RXFRQ, 1089 port->membase + ofs->rqr); 1090 1091 stm32_usart_clr_bits(port, ofs->cr1, val); 1092 1093 free_irq(port->irq, port); 1094 } 1095 1096 static void stm32_usart_set_termios(struct uart_port *port, 1097 struct ktermios *termios, 1098 const struct ktermios *old) 1099 { 1100 struct stm32_port *stm32_port = to_stm32_port(port); 1101 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1102 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 1103 struct serial_rs485 *rs485conf = &port->rs485; 1104 unsigned int baud, bits; 1105 u32 usartdiv, mantissa, fraction, oversampling; 1106 tcflag_t cflag = termios->c_cflag; 1107 u32 cr1, cr2, cr3, isr; 1108 unsigned long flags; 1109 int ret; 1110 1111 if (!stm32_port->hw_flow_control) 1112 cflag &= ~CRTSCTS; 1113 1114 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8); 1115 1116 spin_lock_irqsave(&port->lock, flags); 1117 1118 ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, 1119 isr, 1120 (isr & USART_SR_TC), 1121 10, 100000); 1122 1123 /* Send the TC error message only when ISR_TC is not set. */ 1124 if (ret) 1125 dev_err(port->dev, "Transmission is not complete\n"); 1126 1127 /* Stop serial port and reset value */ 1128 writel_relaxed(0, port->membase + ofs->cr1); 1129 1130 /* flush RX & TX FIFO */ 1131 if (ofs->rqr != UNDEF_REG) 1132 writel_relaxed(USART_RQR_TXFRQ | USART_RQR_RXFRQ, 1133 port->membase + ofs->rqr); 1134 1135 cr1 = USART_CR1_TE | USART_CR1_RE; 1136 if (stm32_port->fifoen) 1137 cr1 |= USART_CR1_FIFOEN; 1138 cr2 = stm32_port->swap ? USART_CR2_SWAP : 0; 1139 1140 /* Tx and RX FIFO configuration */ 1141 cr3 = readl_relaxed(port->membase + ofs->cr3); 1142 cr3 &= USART_CR3_TXFTIE | USART_CR3_RXFTIE; 1143 if (stm32_port->fifoen) { 1144 if (stm32_port->txftcfg >= 0) 1145 cr3 |= stm32_port->txftcfg << USART_CR3_TXFTCFG_SHIFT; 1146 if (stm32_port->rxftcfg >= 0) 1147 cr3 |= stm32_port->rxftcfg << USART_CR3_RXFTCFG_SHIFT; 1148 } 1149 1150 if (cflag & CSTOPB) 1151 cr2 |= USART_CR2_STOP_2B; 1152 1153 bits = tty_get_char_size(cflag); 1154 stm32_port->rdr_mask = (BIT(bits) - 1); 1155 1156 if (cflag & PARENB) { 1157 bits++; 1158 cr1 |= USART_CR1_PCE; 1159 } 1160 1161 /* 1162 * Word length configuration: 1163 * CS8 + parity, 9 bits word aka [M1:M0] = 0b01 1164 * CS7 or (CS6 + parity), 7 bits word aka [M1:M0] = 0b10 1165 * CS8 or (CS7 + parity), 8 bits word aka [M1:M0] = 0b00 1166 * M0 and M1 already cleared by cr1 initialization. 1167 */ 1168 if (bits == 9) { 1169 cr1 |= USART_CR1_M0; 1170 } else if ((bits == 7) && cfg->has_7bits_data) { 1171 cr1 |= USART_CR1_M1; 1172 } else if (bits != 8) { 1173 dev_dbg(port->dev, "Unsupported data bits config: %u bits\n" 1174 , bits); 1175 cflag &= ~CSIZE; 1176 cflag |= CS8; 1177 termios->c_cflag = cflag; 1178 bits = 8; 1179 if (cflag & PARENB) { 1180 bits++; 1181 cr1 |= USART_CR1_M0; 1182 } 1183 } 1184 1185 if (ofs->rtor != UNDEF_REG && (stm32_port->rx_ch || 1186 (stm32_port->fifoen && 1187 stm32_port->rxftcfg >= 0))) { 1188 if (cflag & CSTOPB) 1189 bits = bits + 3; /* 1 start bit + 2 stop bits */ 1190 else 1191 bits = bits + 2; /* 1 start bit + 1 stop bit */ 1192 1193 /* RX timeout irq to occur after last stop bit + bits */ 1194 stm32_port->cr1_irq = USART_CR1_RTOIE; 1195 writel_relaxed(bits, port->membase + ofs->rtor); 1196 cr2 |= USART_CR2_RTOEN; 1197 /* 1198 * Enable fifo threshold irq in two cases, either when there is no DMA, or when 1199 * wake up over usart, from low power until the DMA gets re-enabled by resume. 1200 */ 1201 stm32_port->cr3_irq = USART_CR3_RXFTIE; 1202 } 1203 1204 cr1 |= stm32_port->cr1_irq; 1205 cr3 |= stm32_port->cr3_irq; 1206 1207 if (cflag & PARODD) 1208 cr1 |= USART_CR1_PS; 1209 1210 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); 1211 if (cflag & CRTSCTS) { 1212 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 1213 cr3 |= USART_CR3_CTSE | USART_CR3_RTSE; 1214 } 1215 1216 usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud); 1217 1218 /* 1219 * The USART supports 16 or 8 times oversampling. 1220 * By default we prefer 16 times oversampling, so that the receiver 1221 * has a better tolerance to clock deviations. 1222 * 8 times oversampling is only used to achieve higher speeds. 1223 */ 1224 if (usartdiv < 16) { 1225 oversampling = 8; 1226 cr1 |= USART_CR1_OVER8; 1227 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_OVER8); 1228 } else { 1229 oversampling = 16; 1230 cr1 &= ~USART_CR1_OVER8; 1231 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_OVER8); 1232 } 1233 1234 mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT; 1235 fraction = usartdiv % oversampling; 1236 writel_relaxed(mantissa | fraction, port->membase + ofs->brr); 1237 1238 uart_update_timeout(port, cflag, baud); 1239 1240 port->read_status_mask = USART_SR_ORE; 1241 if (termios->c_iflag & INPCK) 1242 port->read_status_mask |= USART_SR_PE | USART_SR_FE; 1243 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 1244 port->read_status_mask |= USART_SR_FE; 1245 1246 /* Characters to ignore */ 1247 port->ignore_status_mask = 0; 1248 if (termios->c_iflag & IGNPAR) 1249 port->ignore_status_mask = USART_SR_PE | USART_SR_FE; 1250 if (termios->c_iflag & IGNBRK) { 1251 port->ignore_status_mask |= USART_SR_FE; 1252 /* 1253 * If we're ignoring parity and break indicators, 1254 * ignore overruns too (for real raw support). 1255 */ 1256 if (termios->c_iflag & IGNPAR) 1257 port->ignore_status_mask |= USART_SR_ORE; 1258 } 1259 1260 /* Ignore all characters if CREAD is not set */ 1261 if ((termios->c_cflag & CREAD) == 0) 1262 port->ignore_status_mask |= USART_SR_DUMMY_RX; 1263 1264 if (stm32_port->rx_ch) { 1265 /* 1266 * Setup DMA to collect only valid data and enable error irqs. 1267 * This also enables break reception when using DMA. 1268 */ 1269 cr1 |= USART_CR1_PEIE; 1270 cr3 |= USART_CR3_EIE; 1271 cr3 |= USART_CR3_DMAR; 1272 cr3 |= USART_CR3_DDRE; 1273 } 1274 1275 if (rs485conf->flags & SER_RS485_ENABLED) { 1276 stm32_usart_config_reg_rs485(&cr1, &cr3, 1277 rs485conf->delay_rts_before_send, 1278 rs485conf->delay_rts_after_send, 1279 baud); 1280 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 1281 cr3 &= ~USART_CR3_DEP; 1282 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND; 1283 } else { 1284 cr3 |= USART_CR3_DEP; 1285 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; 1286 } 1287 1288 } else { 1289 cr3 &= ~(USART_CR3_DEM | USART_CR3_DEP); 1290 cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK); 1291 } 1292 1293 /* Configure wake up from low power on start bit detection */ 1294 if (stm32_port->wakeup_src) { 1295 cr3 &= ~USART_CR3_WUS_MASK; 1296 cr3 |= USART_CR3_WUS_START_BIT; 1297 } 1298 1299 writel_relaxed(cr3, port->membase + ofs->cr3); 1300 writel_relaxed(cr2, port->membase + ofs->cr2); 1301 writel_relaxed(cr1, port->membase + ofs->cr1); 1302 1303 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 1304 spin_unlock_irqrestore(&port->lock, flags); 1305 1306 /* Handle modem control interrupts */ 1307 if (UART_ENABLE_MS(port, termios->c_cflag)) 1308 stm32_usart_enable_ms(port); 1309 else 1310 stm32_usart_disable_ms(port); 1311 } 1312 1313 static const char *stm32_usart_type(struct uart_port *port) 1314 { 1315 return (port->type == PORT_STM32) ? DRIVER_NAME : NULL; 1316 } 1317 1318 static void stm32_usart_release_port(struct uart_port *port) 1319 { 1320 } 1321 1322 static int stm32_usart_request_port(struct uart_port *port) 1323 { 1324 return 0; 1325 } 1326 1327 static void stm32_usart_config_port(struct uart_port *port, int flags) 1328 { 1329 if (flags & UART_CONFIG_TYPE) 1330 port->type = PORT_STM32; 1331 } 1332 1333 static int 1334 stm32_usart_verify_port(struct uart_port *port, struct serial_struct *ser) 1335 { 1336 /* No user changeable parameters */ 1337 return -EINVAL; 1338 } 1339 1340 static void stm32_usart_pm(struct uart_port *port, unsigned int state, 1341 unsigned int oldstate) 1342 { 1343 struct stm32_port *stm32port = container_of(port, 1344 struct stm32_port, port); 1345 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 1346 const struct stm32_usart_config *cfg = &stm32port->info->cfg; 1347 unsigned long flags; 1348 1349 switch (state) { 1350 case UART_PM_STATE_ON: 1351 pm_runtime_get_sync(port->dev); 1352 break; 1353 case UART_PM_STATE_OFF: 1354 spin_lock_irqsave(&port->lock, flags); 1355 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 1356 spin_unlock_irqrestore(&port->lock, flags); 1357 pm_runtime_put_sync(port->dev); 1358 break; 1359 } 1360 } 1361 1362 #if defined(CONFIG_CONSOLE_POLL) 1363 1364 /* Callbacks for characters polling in debug context (i.e. KGDB). */ 1365 static int stm32_usart_poll_init(struct uart_port *port) 1366 { 1367 struct stm32_port *stm32_port = to_stm32_port(port); 1368 1369 return clk_prepare_enable(stm32_port->clk); 1370 } 1371 1372 static int stm32_usart_poll_get_char(struct uart_port *port) 1373 { 1374 struct stm32_port *stm32_port = to_stm32_port(port); 1375 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1376 1377 if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_RXNE)) 1378 return NO_POLL_CHAR; 1379 1380 return readl_relaxed(port->membase + ofs->rdr) & stm32_port->rdr_mask; 1381 } 1382 1383 static void stm32_usart_poll_put_char(struct uart_port *port, unsigned char ch) 1384 { 1385 stm32_usart_console_putchar(port, ch); 1386 } 1387 #endif /* CONFIG_CONSOLE_POLL */ 1388 1389 static const struct uart_ops stm32_uart_ops = { 1390 .tx_empty = stm32_usart_tx_empty, 1391 .set_mctrl = stm32_usart_set_mctrl, 1392 .get_mctrl = stm32_usart_get_mctrl, 1393 .stop_tx = stm32_usart_stop_tx, 1394 .start_tx = stm32_usart_start_tx, 1395 .throttle = stm32_usart_throttle, 1396 .unthrottle = stm32_usart_unthrottle, 1397 .stop_rx = stm32_usart_stop_rx, 1398 .enable_ms = stm32_usart_enable_ms, 1399 .break_ctl = stm32_usart_break_ctl, 1400 .startup = stm32_usart_startup, 1401 .shutdown = stm32_usart_shutdown, 1402 .flush_buffer = stm32_usart_flush_buffer, 1403 .set_termios = stm32_usart_set_termios, 1404 .pm = stm32_usart_pm, 1405 .type = stm32_usart_type, 1406 .release_port = stm32_usart_release_port, 1407 .request_port = stm32_usart_request_port, 1408 .config_port = stm32_usart_config_port, 1409 .verify_port = stm32_usart_verify_port, 1410 #if defined(CONFIG_CONSOLE_POLL) 1411 .poll_init = stm32_usart_poll_init, 1412 .poll_get_char = stm32_usart_poll_get_char, 1413 .poll_put_char = stm32_usart_poll_put_char, 1414 #endif /* CONFIG_CONSOLE_POLL */ 1415 }; 1416 1417 /* 1418 * STM32H7 RX & TX FIFO threshold configuration (CR3 RXFTCFG / TXFTCFG) 1419 * Note: 1 isn't a valid value in RXFTCFG / TXFTCFG. In this case, 1420 * RXNEIE / TXEIE can be used instead of threshold irqs: RXFTIE / TXFTIE. 1421 * So, RXFTCFG / TXFTCFG bitfields values are encoded as array index + 1. 1422 */ 1423 static const u32 stm32h7_usart_fifo_thresh_cfg[] = { 1, 2, 4, 8, 12, 14, 16 }; 1424 1425 static void stm32_usart_get_ftcfg(struct platform_device *pdev, const char *p, 1426 int *ftcfg) 1427 { 1428 u32 bytes, i; 1429 1430 /* DT option to get RX & TX FIFO threshold (default to 8 bytes) */ 1431 if (of_property_read_u32(pdev->dev.of_node, p, &bytes)) 1432 bytes = 8; 1433 1434 for (i = 0; i < ARRAY_SIZE(stm32h7_usart_fifo_thresh_cfg); i++) 1435 if (stm32h7_usart_fifo_thresh_cfg[i] >= bytes) 1436 break; 1437 if (i >= ARRAY_SIZE(stm32h7_usart_fifo_thresh_cfg)) 1438 i = ARRAY_SIZE(stm32h7_usart_fifo_thresh_cfg) - 1; 1439 1440 dev_dbg(&pdev->dev, "%s set to %d bytes\n", p, 1441 stm32h7_usart_fifo_thresh_cfg[i]); 1442 1443 /* Provide FIFO threshold ftcfg (1 is invalid: threshold irq unused) */ 1444 if (i) 1445 *ftcfg = i - 1; 1446 else 1447 *ftcfg = -EINVAL; 1448 } 1449 1450 static void stm32_usart_deinit_port(struct stm32_port *stm32port) 1451 { 1452 clk_disable_unprepare(stm32port->clk); 1453 } 1454 1455 static const struct serial_rs485 stm32_rs485_supported = { 1456 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND | 1457 SER_RS485_RX_DURING_TX, 1458 .delay_rts_before_send = 1, 1459 .delay_rts_after_send = 1, 1460 }; 1461 1462 static int stm32_usart_init_port(struct stm32_port *stm32port, 1463 struct platform_device *pdev) 1464 { 1465 struct uart_port *port = &stm32port->port; 1466 struct resource *res; 1467 int ret, irq; 1468 1469 irq = platform_get_irq(pdev, 0); 1470 if (irq < 0) 1471 return irq; 1472 1473 port->iotype = UPIO_MEM; 1474 port->flags = UPF_BOOT_AUTOCONF; 1475 port->ops = &stm32_uart_ops; 1476 port->dev = &pdev->dev; 1477 port->fifosize = stm32port->info->cfg.fifosize; 1478 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_STM32_CONSOLE); 1479 port->irq = irq; 1480 port->rs485_config = stm32_usart_config_rs485; 1481 port->rs485_supported = stm32_rs485_supported; 1482 1483 ret = stm32_usart_init_rs485(port, pdev); 1484 if (ret) 1485 return ret; 1486 1487 stm32port->wakeup_src = stm32port->info->cfg.has_wakeup && 1488 of_property_read_bool(pdev->dev.of_node, "wakeup-source"); 1489 1490 stm32port->swap = stm32port->info->cfg.has_swap && 1491 of_property_read_bool(pdev->dev.of_node, "rx-tx-swap"); 1492 1493 stm32port->fifoen = stm32port->info->cfg.has_fifo; 1494 if (stm32port->fifoen) { 1495 stm32_usart_get_ftcfg(pdev, "rx-threshold", 1496 &stm32port->rxftcfg); 1497 stm32_usart_get_ftcfg(pdev, "tx-threshold", 1498 &stm32port->txftcfg); 1499 } 1500 1501 port->membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1502 if (IS_ERR(port->membase)) 1503 return PTR_ERR(port->membase); 1504 port->mapbase = res->start; 1505 1506 spin_lock_init(&port->lock); 1507 1508 stm32port->clk = devm_clk_get(&pdev->dev, NULL); 1509 if (IS_ERR(stm32port->clk)) 1510 return PTR_ERR(stm32port->clk); 1511 1512 /* Ensure that clk rate is correct by enabling the clk */ 1513 ret = clk_prepare_enable(stm32port->clk); 1514 if (ret) 1515 return ret; 1516 1517 stm32port->port.uartclk = clk_get_rate(stm32port->clk); 1518 if (!stm32port->port.uartclk) { 1519 ret = -EINVAL; 1520 goto err_clk; 1521 } 1522 1523 stm32port->gpios = mctrl_gpio_init(&stm32port->port, 0); 1524 if (IS_ERR(stm32port->gpios)) { 1525 ret = PTR_ERR(stm32port->gpios); 1526 goto err_clk; 1527 } 1528 1529 /* 1530 * Both CTS/RTS gpios and "st,hw-flow-ctrl" (deprecated) or "uart-has-rtscts" 1531 * properties should not be specified. 1532 */ 1533 if (stm32port->hw_flow_control) { 1534 if (mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_CTS) || 1535 mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_RTS)) { 1536 dev_err(&pdev->dev, "Conflicting RTS/CTS config\n"); 1537 ret = -EINVAL; 1538 goto err_clk; 1539 } 1540 } 1541 1542 return ret; 1543 1544 err_clk: 1545 clk_disable_unprepare(stm32port->clk); 1546 1547 return ret; 1548 } 1549 1550 static struct stm32_port *stm32_usart_of_get_port(struct platform_device *pdev) 1551 { 1552 struct device_node *np = pdev->dev.of_node; 1553 int id; 1554 1555 if (!np) 1556 return NULL; 1557 1558 id = of_alias_get_id(np, "serial"); 1559 if (id < 0) { 1560 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", id); 1561 return NULL; 1562 } 1563 1564 if (WARN_ON(id >= STM32_MAX_PORTS)) 1565 return NULL; 1566 1567 stm32_ports[id].hw_flow_control = 1568 of_property_read_bool (np, "st,hw-flow-ctrl") /*deprecated*/ || 1569 of_property_read_bool (np, "uart-has-rtscts"); 1570 stm32_ports[id].port.line = id; 1571 stm32_ports[id].cr1_irq = USART_CR1_RXNEIE; 1572 stm32_ports[id].cr3_irq = 0; 1573 stm32_ports[id].last_res = RX_BUF_L; 1574 return &stm32_ports[id]; 1575 } 1576 1577 #ifdef CONFIG_OF 1578 static const struct of_device_id stm32_match[] = { 1579 { .compatible = "st,stm32-uart", .data = &stm32f4_info}, 1580 { .compatible = "st,stm32f7-uart", .data = &stm32f7_info}, 1581 { .compatible = "st,stm32h7-uart", .data = &stm32h7_info}, 1582 {}, 1583 }; 1584 1585 MODULE_DEVICE_TABLE(of, stm32_match); 1586 #endif 1587 1588 static void stm32_usart_of_dma_rx_remove(struct stm32_port *stm32port, 1589 struct platform_device *pdev) 1590 { 1591 if (stm32port->rx_buf) 1592 dma_free_coherent(&pdev->dev, RX_BUF_L, stm32port->rx_buf, 1593 stm32port->rx_dma_buf); 1594 } 1595 1596 static int stm32_usart_of_dma_rx_probe(struct stm32_port *stm32port, 1597 struct platform_device *pdev) 1598 { 1599 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 1600 struct uart_port *port = &stm32port->port; 1601 struct device *dev = &pdev->dev; 1602 struct dma_slave_config config; 1603 int ret; 1604 1605 /* 1606 * Using DMA and threaded handler for the console could lead to 1607 * deadlocks. 1608 */ 1609 if (uart_console(port)) 1610 return -ENODEV; 1611 1612 stm32port->rx_buf = dma_alloc_coherent(dev, RX_BUF_L, 1613 &stm32port->rx_dma_buf, 1614 GFP_KERNEL); 1615 if (!stm32port->rx_buf) 1616 return -ENOMEM; 1617 1618 /* Configure DMA channel */ 1619 memset(&config, 0, sizeof(config)); 1620 config.src_addr = port->mapbase + ofs->rdr; 1621 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1622 1623 ret = dmaengine_slave_config(stm32port->rx_ch, &config); 1624 if (ret < 0) { 1625 dev_err(dev, "rx dma channel config failed\n"); 1626 stm32_usart_of_dma_rx_remove(stm32port, pdev); 1627 return ret; 1628 } 1629 1630 return 0; 1631 } 1632 1633 static void stm32_usart_of_dma_tx_remove(struct stm32_port *stm32port, 1634 struct platform_device *pdev) 1635 { 1636 if (stm32port->tx_buf) 1637 dma_free_coherent(&pdev->dev, TX_BUF_L, stm32port->tx_buf, 1638 stm32port->tx_dma_buf); 1639 } 1640 1641 static int stm32_usart_of_dma_tx_probe(struct stm32_port *stm32port, 1642 struct platform_device *pdev) 1643 { 1644 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 1645 struct uart_port *port = &stm32port->port; 1646 struct device *dev = &pdev->dev; 1647 struct dma_slave_config config; 1648 int ret; 1649 1650 stm32port->tx_buf = dma_alloc_coherent(dev, TX_BUF_L, 1651 &stm32port->tx_dma_buf, 1652 GFP_KERNEL); 1653 if (!stm32port->tx_buf) 1654 return -ENOMEM; 1655 1656 /* Configure DMA channel */ 1657 memset(&config, 0, sizeof(config)); 1658 config.dst_addr = port->mapbase + ofs->tdr; 1659 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1660 1661 ret = dmaengine_slave_config(stm32port->tx_ch, &config); 1662 if (ret < 0) { 1663 dev_err(dev, "tx dma channel config failed\n"); 1664 stm32_usart_of_dma_tx_remove(stm32port, pdev); 1665 return ret; 1666 } 1667 1668 return 0; 1669 } 1670 1671 static int stm32_usart_serial_probe(struct platform_device *pdev) 1672 { 1673 struct stm32_port *stm32port; 1674 int ret; 1675 1676 stm32port = stm32_usart_of_get_port(pdev); 1677 if (!stm32port) 1678 return -ENODEV; 1679 1680 stm32port->info = of_device_get_match_data(&pdev->dev); 1681 if (!stm32port->info) 1682 return -EINVAL; 1683 1684 ret = stm32_usart_init_port(stm32port, pdev); 1685 if (ret) 1686 return ret; 1687 1688 if (stm32port->wakeup_src) { 1689 device_set_wakeup_capable(&pdev->dev, true); 1690 ret = dev_pm_set_wake_irq(&pdev->dev, stm32port->port.irq); 1691 if (ret) 1692 goto err_deinit_port; 1693 } 1694 1695 stm32port->rx_ch = dma_request_chan(&pdev->dev, "rx"); 1696 if (PTR_ERR(stm32port->rx_ch) == -EPROBE_DEFER) { 1697 ret = -EPROBE_DEFER; 1698 goto err_wakeirq; 1699 } 1700 /* Fall back in interrupt mode for any non-deferral error */ 1701 if (IS_ERR(stm32port->rx_ch)) 1702 stm32port->rx_ch = NULL; 1703 1704 stm32port->tx_ch = dma_request_chan(&pdev->dev, "tx"); 1705 if (PTR_ERR(stm32port->tx_ch) == -EPROBE_DEFER) { 1706 ret = -EPROBE_DEFER; 1707 goto err_dma_rx; 1708 } 1709 /* Fall back in interrupt mode for any non-deferral error */ 1710 if (IS_ERR(stm32port->tx_ch)) 1711 stm32port->tx_ch = NULL; 1712 1713 if (stm32port->rx_ch && stm32_usart_of_dma_rx_probe(stm32port, pdev)) { 1714 /* Fall back in interrupt mode */ 1715 dma_release_channel(stm32port->rx_ch); 1716 stm32port->rx_ch = NULL; 1717 } 1718 1719 if (stm32port->tx_ch && stm32_usart_of_dma_tx_probe(stm32port, pdev)) { 1720 /* Fall back in interrupt mode */ 1721 dma_release_channel(stm32port->tx_ch); 1722 stm32port->tx_ch = NULL; 1723 } 1724 1725 if (!stm32port->rx_ch) 1726 dev_info(&pdev->dev, "interrupt mode for rx (no dma)\n"); 1727 if (!stm32port->tx_ch) 1728 dev_info(&pdev->dev, "interrupt mode for tx (no dma)\n"); 1729 1730 platform_set_drvdata(pdev, &stm32port->port); 1731 1732 pm_runtime_get_noresume(&pdev->dev); 1733 pm_runtime_set_active(&pdev->dev); 1734 pm_runtime_enable(&pdev->dev); 1735 1736 ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port); 1737 if (ret) 1738 goto err_port; 1739 1740 pm_runtime_put_sync(&pdev->dev); 1741 1742 return 0; 1743 1744 err_port: 1745 pm_runtime_disable(&pdev->dev); 1746 pm_runtime_set_suspended(&pdev->dev); 1747 pm_runtime_put_noidle(&pdev->dev); 1748 1749 if (stm32port->tx_ch) { 1750 stm32_usart_of_dma_tx_remove(stm32port, pdev); 1751 dma_release_channel(stm32port->tx_ch); 1752 } 1753 1754 if (stm32port->rx_ch) 1755 stm32_usart_of_dma_rx_remove(stm32port, pdev); 1756 1757 err_dma_rx: 1758 if (stm32port->rx_ch) 1759 dma_release_channel(stm32port->rx_ch); 1760 1761 err_wakeirq: 1762 if (stm32port->wakeup_src) 1763 dev_pm_clear_wake_irq(&pdev->dev); 1764 1765 err_deinit_port: 1766 if (stm32port->wakeup_src) 1767 device_set_wakeup_capable(&pdev->dev, false); 1768 1769 stm32_usart_deinit_port(stm32port); 1770 1771 return ret; 1772 } 1773 1774 static int stm32_usart_serial_remove(struct platform_device *pdev) 1775 { 1776 struct uart_port *port = platform_get_drvdata(pdev); 1777 struct stm32_port *stm32_port = to_stm32_port(port); 1778 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1779 int err; 1780 u32 cr3; 1781 1782 pm_runtime_get_sync(&pdev->dev); 1783 err = uart_remove_one_port(&stm32_usart_driver, port); 1784 if (err) 1785 return(err); 1786 1787 pm_runtime_disable(&pdev->dev); 1788 pm_runtime_set_suspended(&pdev->dev); 1789 pm_runtime_put_noidle(&pdev->dev); 1790 1791 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_PEIE); 1792 cr3 = readl_relaxed(port->membase + ofs->cr3); 1793 cr3 &= ~USART_CR3_EIE; 1794 cr3 &= ~USART_CR3_DMAR; 1795 cr3 &= ~USART_CR3_DDRE; 1796 writel_relaxed(cr3, port->membase + ofs->cr3); 1797 1798 if (stm32_port->tx_ch) { 1799 stm32_usart_of_dma_tx_remove(stm32_port, pdev); 1800 dma_release_channel(stm32_port->tx_ch); 1801 } 1802 1803 if (stm32_port->rx_ch) { 1804 stm32_usart_of_dma_rx_remove(stm32_port, pdev); 1805 dma_release_channel(stm32_port->rx_ch); 1806 } 1807 1808 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 1809 1810 if (stm32_port->wakeup_src) { 1811 dev_pm_clear_wake_irq(&pdev->dev); 1812 device_init_wakeup(&pdev->dev, false); 1813 } 1814 1815 stm32_usart_deinit_port(stm32_port); 1816 1817 return 0; 1818 } 1819 1820 static void __maybe_unused stm32_usart_console_putchar(struct uart_port *port, unsigned char ch) 1821 { 1822 struct stm32_port *stm32_port = to_stm32_port(port); 1823 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1824 u32 isr; 1825 int ret; 1826 1827 ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, isr, 1828 (isr & USART_SR_TXE), 100, 1829 STM32_USART_TIMEOUT_USEC); 1830 if (ret != 0) { 1831 dev_err(port->dev, "Error while sending data in UART TX : %d\n", ret); 1832 return; 1833 } 1834 writel_relaxed(ch, port->membase + ofs->tdr); 1835 } 1836 1837 #ifdef CONFIG_SERIAL_STM32_CONSOLE 1838 static void stm32_usart_console_write(struct console *co, const char *s, 1839 unsigned int cnt) 1840 { 1841 struct uart_port *port = &stm32_ports[co->index].port; 1842 struct stm32_port *stm32_port = to_stm32_port(port); 1843 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1844 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 1845 unsigned long flags; 1846 u32 old_cr1, new_cr1; 1847 int locked = 1; 1848 1849 if (oops_in_progress) 1850 locked = spin_trylock_irqsave(&port->lock, flags); 1851 else 1852 spin_lock_irqsave(&port->lock, flags); 1853 1854 /* Save and disable interrupts, enable the transmitter */ 1855 old_cr1 = readl_relaxed(port->membase + ofs->cr1); 1856 new_cr1 = old_cr1 & ~USART_CR1_IE_MASK; 1857 new_cr1 |= USART_CR1_TE | BIT(cfg->uart_enable_bit); 1858 writel_relaxed(new_cr1, port->membase + ofs->cr1); 1859 1860 uart_console_write(port, s, cnt, stm32_usart_console_putchar); 1861 1862 /* Restore interrupt state */ 1863 writel_relaxed(old_cr1, port->membase + ofs->cr1); 1864 1865 if (locked) 1866 spin_unlock_irqrestore(&port->lock, flags); 1867 } 1868 1869 static int stm32_usart_console_setup(struct console *co, char *options) 1870 { 1871 struct stm32_port *stm32port; 1872 int baud = 9600; 1873 int bits = 8; 1874 int parity = 'n'; 1875 int flow = 'n'; 1876 1877 if (co->index >= STM32_MAX_PORTS) 1878 return -ENODEV; 1879 1880 stm32port = &stm32_ports[co->index]; 1881 1882 /* 1883 * This driver does not support early console initialization 1884 * (use ARM early printk support instead), so we only expect 1885 * this to be called during the uart port registration when the 1886 * driver gets probed and the port should be mapped at that point. 1887 */ 1888 if (stm32port->port.mapbase == 0 || !stm32port->port.membase) 1889 return -ENXIO; 1890 1891 if (options) 1892 uart_parse_options(options, &baud, &parity, &bits, &flow); 1893 1894 return uart_set_options(&stm32port->port, co, baud, parity, bits, flow); 1895 } 1896 1897 static struct console stm32_console = { 1898 .name = STM32_SERIAL_NAME, 1899 .device = uart_console_device, 1900 .write = stm32_usart_console_write, 1901 .setup = stm32_usart_console_setup, 1902 .flags = CON_PRINTBUFFER, 1903 .index = -1, 1904 .data = &stm32_usart_driver, 1905 }; 1906 1907 #define STM32_SERIAL_CONSOLE (&stm32_console) 1908 1909 #else 1910 #define STM32_SERIAL_CONSOLE NULL 1911 #endif /* CONFIG_SERIAL_STM32_CONSOLE */ 1912 1913 #ifdef CONFIG_SERIAL_EARLYCON 1914 static void early_stm32_usart_console_putchar(struct uart_port *port, unsigned char ch) 1915 { 1916 struct stm32_usart_info *info = port->private_data; 1917 1918 while (!(readl_relaxed(port->membase + info->ofs.isr) & USART_SR_TXE)) 1919 cpu_relax(); 1920 1921 writel_relaxed(ch, port->membase + info->ofs.tdr); 1922 } 1923 1924 static void early_stm32_serial_write(struct console *console, const char *s, unsigned int count) 1925 { 1926 struct earlycon_device *device = console->data; 1927 struct uart_port *port = &device->port; 1928 1929 uart_console_write(port, s, count, early_stm32_usart_console_putchar); 1930 } 1931 1932 static int __init early_stm32_h7_serial_setup(struct earlycon_device *device, const char *options) 1933 { 1934 if (!(device->port.membase || device->port.iobase)) 1935 return -ENODEV; 1936 device->port.private_data = &stm32h7_info; 1937 device->con->write = early_stm32_serial_write; 1938 return 0; 1939 } 1940 1941 static int __init early_stm32_f7_serial_setup(struct earlycon_device *device, const char *options) 1942 { 1943 if (!(device->port.membase || device->port.iobase)) 1944 return -ENODEV; 1945 device->port.private_data = &stm32f7_info; 1946 device->con->write = early_stm32_serial_write; 1947 return 0; 1948 } 1949 1950 static int __init early_stm32_f4_serial_setup(struct earlycon_device *device, const char *options) 1951 { 1952 if (!(device->port.membase || device->port.iobase)) 1953 return -ENODEV; 1954 device->port.private_data = &stm32f4_info; 1955 device->con->write = early_stm32_serial_write; 1956 return 0; 1957 } 1958 1959 OF_EARLYCON_DECLARE(stm32, "st,stm32h7-uart", early_stm32_h7_serial_setup); 1960 OF_EARLYCON_DECLARE(stm32, "st,stm32f7-uart", early_stm32_f7_serial_setup); 1961 OF_EARLYCON_DECLARE(stm32, "st,stm32-uart", early_stm32_f4_serial_setup); 1962 #endif /* CONFIG_SERIAL_EARLYCON */ 1963 1964 static struct uart_driver stm32_usart_driver = { 1965 .driver_name = DRIVER_NAME, 1966 .dev_name = STM32_SERIAL_NAME, 1967 .major = 0, 1968 .minor = 0, 1969 .nr = STM32_MAX_PORTS, 1970 .cons = STM32_SERIAL_CONSOLE, 1971 }; 1972 1973 static int __maybe_unused stm32_usart_serial_en_wakeup(struct uart_port *port, 1974 bool enable) 1975 { 1976 struct stm32_port *stm32_port = to_stm32_port(port); 1977 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1978 struct tty_port *tport = &port->state->port; 1979 int ret; 1980 unsigned int size; 1981 unsigned long flags; 1982 1983 if (!stm32_port->wakeup_src || !tty_port_initialized(tport)) 1984 return 0; 1985 1986 /* 1987 * Enable low-power wake-up and wake-up irq if argument is set to 1988 * "enable", disable low-power wake-up and wake-up irq otherwise 1989 */ 1990 if (enable) { 1991 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_UESM); 1992 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_WUFIE); 1993 mctrl_gpio_enable_irq_wake(stm32_port->gpios); 1994 1995 /* 1996 * When DMA is used for reception, it must be disabled before 1997 * entering low-power mode and re-enabled when exiting from 1998 * low-power mode. 1999 */ 2000 if (stm32_port->rx_ch) { 2001 spin_lock_irqsave(&port->lock, flags); 2002 /* Avoid race with RX IRQ when DMAR is cleared */ 2003 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR); 2004 /* Poll data from DMA RX buffer if any */ 2005 size = stm32_usart_receive_chars(port, true); 2006 dmaengine_terminate_async(stm32_port->rx_ch); 2007 uart_unlock_and_check_sysrq_irqrestore(port, flags); 2008 if (size) 2009 tty_flip_buffer_push(tport); 2010 } 2011 2012 /* Poll data from RX FIFO if any */ 2013 stm32_usart_receive_chars(port, false); 2014 } else { 2015 if (stm32_port->rx_ch) { 2016 ret = stm32_usart_start_rx_dma_cyclic(port); 2017 if (ret) 2018 return ret; 2019 } 2020 mctrl_gpio_disable_irq_wake(stm32_port->gpios); 2021 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_UESM); 2022 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE); 2023 } 2024 2025 return 0; 2026 } 2027 2028 static int __maybe_unused stm32_usart_serial_suspend(struct device *dev) 2029 { 2030 struct uart_port *port = dev_get_drvdata(dev); 2031 int ret; 2032 2033 uart_suspend_port(&stm32_usart_driver, port); 2034 2035 if (device_may_wakeup(dev) || device_wakeup_path(dev)) { 2036 ret = stm32_usart_serial_en_wakeup(port, true); 2037 if (ret) 2038 return ret; 2039 } 2040 2041 /* 2042 * When "no_console_suspend" is enabled, keep the pinctrl default state 2043 * and rely on bootloader stage to restore this state upon resume. 2044 * Otherwise, apply the idle or sleep states depending on wakeup 2045 * capabilities. 2046 */ 2047 if (console_suspend_enabled || !uart_console(port)) { 2048 if (device_may_wakeup(dev) || device_wakeup_path(dev)) 2049 pinctrl_pm_select_idle_state(dev); 2050 else 2051 pinctrl_pm_select_sleep_state(dev); 2052 } 2053 2054 return 0; 2055 } 2056 2057 static int __maybe_unused stm32_usart_serial_resume(struct device *dev) 2058 { 2059 struct uart_port *port = dev_get_drvdata(dev); 2060 int ret; 2061 2062 pinctrl_pm_select_default_state(dev); 2063 2064 if (device_may_wakeup(dev) || device_wakeup_path(dev)) { 2065 ret = stm32_usart_serial_en_wakeup(port, false); 2066 if (ret) 2067 return ret; 2068 } 2069 2070 return uart_resume_port(&stm32_usart_driver, port); 2071 } 2072 2073 static int __maybe_unused stm32_usart_runtime_suspend(struct device *dev) 2074 { 2075 struct uart_port *port = dev_get_drvdata(dev); 2076 struct stm32_port *stm32port = container_of(port, 2077 struct stm32_port, port); 2078 2079 clk_disable_unprepare(stm32port->clk); 2080 2081 return 0; 2082 } 2083 2084 static int __maybe_unused stm32_usart_runtime_resume(struct device *dev) 2085 { 2086 struct uart_port *port = dev_get_drvdata(dev); 2087 struct stm32_port *stm32port = container_of(port, 2088 struct stm32_port, port); 2089 2090 return clk_prepare_enable(stm32port->clk); 2091 } 2092 2093 static const struct dev_pm_ops stm32_serial_pm_ops = { 2094 SET_RUNTIME_PM_OPS(stm32_usart_runtime_suspend, 2095 stm32_usart_runtime_resume, NULL) 2096 SET_SYSTEM_SLEEP_PM_OPS(stm32_usart_serial_suspend, 2097 stm32_usart_serial_resume) 2098 }; 2099 2100 static struct platform_driver stm32_serial_driver = { 2101 .probe = stm32_usart_serial_probe, 2102 .remove = stm32_usart_serial_remove, 2103 .driver = { 2104 .name = DRIVER_NAME, 2105 .pm = &stm32_serial_pm_ops, 2106 .of_match_table = of_match_ptr(stm32_match), 2107 }, 2108 }; 2109 2110 static int __init stm32_usart_init(void) 2111 { 2112 static char banner[] __initdata = "STM32 USART driver initialized"; 2113 int ret; 2114 2115 pr_info("%s\n", banner); 2116 2117 ret = uart_register_driver(&stm32_usart_driver); 2118 if (ret) 2119 return ret; 2120 2121 ret = platform_driver_register(&stm32_serial_driver); 2122 if (ret) 2123 uart_unregister_driver(&stm32_usart_driver); 2124 2125 return ret; 2126 } 2127 2128 static void __exit stm32_usart_exit(void) 2129 { 2130 platform_driver_unregister(&stm32_serial_driver); 2131 uart_unregister_driver(&stm32_usart_driver); 2132 } 2133 2134 module_init(stm32_usart_init); 2135 module_exit(stm32_usart_exit); 2136 2137 MODULE_ALIAS("platform:" DRIVER_NAME); 2138 MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver"); 2139 MODULE_LICENSE("GPL v2"); 2140