1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) Maxime Coquelin 2015 4 * Copyright (C) STMicroelectronics SA 2017 5 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com> 6 * Gerald Baeza <gerald.baeza@foss.st.com> 7 * Erwan Le Ray <erwan.leray@foss.st.com> 8 * 9 * Inspired by st-asc.c from STMicroelectronics (c) 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/console.h> 14 #include <linux/delay.h> 15 #include <linux/dma-direction.h> 16 #include <linux/dmaengine.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/io.h> 19 #include <linux/iopoll.h> 20 #include <linux/irq.h> 21 #include <linux/module.h> 22 #include <linux/of.h> 23 #include <linux/of_platform.h> 24 #include <linux/pinctrl/consumer.h> 25 #include <linux/platform_device.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/pm_wakeirq.h> 28 #include <linux/serial_core.h> 29 #include <linux/serial.h> 30 #include <linux/spinlock.h> 31 #include <linux/sysrq.h> 32 #include <linux/tty_flip.h> 33 #include <linux/tty.h> 34 35 #include "serial_mctrl_gpio.h" 36 #include "stm32-usart.h" 37 38 39 /* Register offsets */ 40 static struct stm32_usart_info stm32f4_info = { 41 .ofs = { 42 .isr = 0x00, 43 .rdr = 0x04, 44 .tdr = 0x04, 45 .brr = 0x08, 46 .cr1 = 0x0c, 47 .cr2 = 0x10, 48 .cr3 = 0x14, 49 .gtpr = 0x18, 50 .rtor = UNDEF_REG, 51 .rqr = UNDEF_REG, 52 .icr = UNDEF_REG, 53 }, 54 .cfg = { 55 .uart_enable_bit = 13, 56 .has_7bits_data = false, 57 .fifosize = 1, 58 } 59 }; 60 61 static struct stm32_usart_info stm32f7_info = { 62 .ofs = { 63 .cr1 = 0x00, 64 .cr2 = 0x04, 65 .cr3 = 0x08, 66 .brr = 0x0c, 67 .gtpr = 0x10, 68 .rtor = 0x14, 69 .rqr = 0x18, 70 .isr = 0x1c, 71 .icr = 0x20, 72 .rdr = 0x24, 73 .tdr = 0x28, 74 }, 75 .cfg = { 76 .uart_enable_bit = 0, 77 .has_7bits_data = true, 78 .has_swap = true, 79 .fifosize = 1, 80 } 81 }; 82 83 static struct stm32_usart_info stm32h7_info = { 84 .ofs = { 85 .cr1 = 0x00, 86 .cr2 = 0x04, 87 .cr3 = 0x08, 88 .brr = 0x0c, 89 .gtpr = 0x10, 90 .rtor = 0x14, 91 .rqr = 0x18, 92 .isr = 0x1c, 93 .icr = 0x20, 94 .rdr = 0x24, 95 .tdr = 0x28, 96 }, 97 .cfg = { 98 .uart_enable_bit = 0, 99 .has_7bits_data = true, 100 .has_swap = true, 101 .has_wakeup = true, 102 .has_fifo = true, 103 .fifosize = 16, 104 } 105 }; 106 107 static void stm32_usart_stop_tx(struct uart_port *port); 108 static void stm32_usart_transmit_chars(struct uart_port *port); 109 static void __maybe_unused stm32_usart_console_putchar(struct uart_port *port, unsigned char ch); 110 111 static inline struct stm32_port *to_stm32_port(struct uart_port *port) 112 { 113 return container_of(port, struct stm32_port, port); 114 } 115 116 static void stm32_usart_set_bits(struct uart_port *port, u32 reg, u32 bits) 117 { 118 u32 val; 119 120 val = readl_relaxed(port->membase + reg); 121 val |= bits; 122 writel_relaxed(val, port->membase + reg); 123 } 124 125 static void stm32_usart_clr_bits(struct uart_port *port, u32 reg, u32 bits) 126 { 127 u32 val; 128 129 val = readl_relaxed(port->membase + reg); 130 val &= ~bits; 131 writel_relaxed(val, port->membase + reg); 132 } 133 134 static void stm32_usart_config_reg_rs485(u32 *cr1, u32 *cr3, u32 delay_ADE, 135 u32 delay_DDE, u32 baud) 136 { 137 u32 rs485_deat_dedt; 138 u32 rs485_deat_dedt_max = (USART_CR1_DEAT_MASK >> USART_CR1_DEAT_SHIFT); 139 bool over8; 140 141 *cr3 |= USART_CR3_DEM; 142 over8 = *cr1 & USART_CR1_OVER8; 143 144 *cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK); 145 146 if (over8) 147 rs485_deat_dedt = delay_ADE * baud * 8; 148 else 149 rs485_deat_dedt = delay_ADE * baud * 16; 150 151 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000); 152 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ? 153 rs485_deat_dedt_max : rs485_deat_dedt; 154 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEAT_SHIFT) & 155 USART_CR1_DEAT_MASK; 156 *cr1 |= rs485_deat_dedt; 157 158 if (over8) 159 rs485_deat_dedt = delay_DDE * baud * 8; 160 else 161 rs485_deat_dedt = delay_DDE * baud * 16; 162 163 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000); 164 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ? 165 rs485_deat_dedt_max : rs485_deat_dedt; 166 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEDT_SHIFT) & 167 USART_CR1_DEDT_MASK; 168 *cr1 |= rs485_deat_dedt; 169 } 170 171 static int stm32_usart_config_rs485(struct uart_port *port, struct ktermios *termios, 172 struct serial_rs485 *rs485conf) 173 { 174 struct stm32_port *stm32_port = to_stm32_port(port); 175 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 176 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 177 u32 usartdiv, baud, cr1, cr3; 178 bool over8; 179 180 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 181 182 rs485conf->flags |= SER_RS485_RX_DURING_TX; 183 184 if (rs485conf->flags & SER_RS485_ENABLED) { 185 cr1 = readl_relaxed(port->membase + ofs->cr1); 186 cr3 = readl_relaxed(port->membase + ofs->cr3); 187 usartdiv = readl_relaxed(port->membase + ofs->brr); 188 usartdiv = usartdiv & GENMASK(15, 0); 189 over8 = cr1 & USART_CR1_OVER8; 190 191 if (over8) 192 usartdiv = usartdiv | (usartdiv & GENMASK(4, 0)) 193 << USART_BRR_04_R_SHIFT; 194 195 baud = DIV_ROUND_CLOSEST(port->uartclk, usartdiv); 196 stm32_usart_config_reg_rs485(&cr1, &cr3, 197 rs485conf->delay_rts_before_send, 198 rs485conf->delay_rts_after_send, 199 baud); 200 201 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) 202 cr3 &= ~USART_CR3_DEP; 203 else 204 cr3 |= USART_CR3_DEP; 205 206 writel_relaxed(cr3, port->membase + ofs->cr3); 207 writel_relaxed(cr1, port->membase + ofs->cr1); 208 } else { 209 stm32_usart_clr_bits(port, ofs->cr3, 210 USART_CR3_DEM | USART_CR3_DEP); 211 stm32_usart_clr_bits(port, ofs->cr1, 212 USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK); 213 } 214 215 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 216 217 return 0; 218 } 219 220 static int stm32_usart_init_rs485(struct uart_port *port, 221 struct platform_device *pdev) 222 { 223 struct serial_rs485 *rs485conf = &port->rs485; 224 225 rs485conf->flags = 0; 226 rs485conf->delay_rts_before_send = 0; 227 rs485conf->delay_rts_after_send = 0; 228 229 if (!pdev->dev.of_node) 230 return -ENODEV; 231 232 return uart_get_rs485_mode(port); 233 } 234 235 static bool stm32_usart_rx_dma_enabled(struct uart_port *port) 236 { 237 struct stm32_port *stm32_port = to_stm32_port(port); 238 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 239 240 if (!stm32_port->rx_ch) 241 return false; 242 243 return !!(readl_relaxed(port->membase + ofs->cr3) & USART_CR3_DMAR); 244 } 245 246 /* Return true when data is pending (in pio mode), and false when no data is pending. */ 247 static bool stm32_usart_pending_rx_pio(struct uart_port *port, u32 *sr) 248 { 249 struct stm32_port *stm32_port = to_stm32_port(port); 250 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 251 252 *sr = readl_relaxed(port->membase + ofs->isr); 253 /* Get pending characters in RDR or FIFO */ 254 if (*sr & USART_SR_RXNE) { 255 /* Get all pending characters from the RDR or the FIFO when using interrupts */ 256 if (!stm32_usart_rx_dma_enabled(port)) 257 return true; 258 259 /* Handle only RX data errors when using DMA */ 260 if (*sr & USART_SR_ERR_MASK) 261 return true; 262 } 263 264 return false; 265 } 266 267 static unsigned long stm32_usart_get_char_pio(struct uart_port *port) 268 { 269 struct stm32_port *stm32_port = to_stm32_port(port); 270 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 271 unsigned long c; 272 273 c = readl_relaxed(port->membase + ofs->rdr); 274 /* Apply RDR data mask */ 275 c &= stm32_port->rdr_mask; 276 277 return c; 278 } 279 280 static unsigned int stm32_usart_receive_chars_pio(struct uart_port *port) 281 { 282 struct stm32_port *stm32_port = to_stm32_port(port); 283 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 284 unsigned long c; 285 unsigned int size = 0; 286 u32 sr; 287 char flag; 288 289 while (stm32_usart_pending_rx_pio(port, &sr)) { 290 sr |= USART_SR_DUMMY_RX; 291 flag = TTY_NORMAL; 292 293 /* 294 * Status bits has to be cleared before reading the RDR: 295 * In FIFO mode, reading the RDR will pop the next data 296 * (if any) along with its status bits into the SR. 297 * Not doing so leads to misalignement between RDR and SR, 298 * and clear status bits of the next rx data. 299 * 300 * Clear errors flags for stm32f7 and stm32h7 compatible 301 * devices. On stm32f4 compatible devices, the error bit is 302 * cleared by the sequence [read SR - read DR]. 303 */ 304 if ((sr & USART_SR_ERR_MASK) && ofs->icr != UNDEF_REG) 305 writel_relaxed(sr & USART_SR_ERR_MASK, 306 port->membase + ofs->icr); 307 308 c = stm32_usart_get_char_pio(port); 309 port->icount.rx++; 310 size++; 311 if (sr & USART_SR_ERR_MASK) { 312 if (sr & USART_SR_ORE) { 313 port->icount.overrun++; 314 } else if (sr & USART_SR_PE) { 315 port->icount.parity++; 316 } else if (sr & USART_SR_FE) { 317 /* Break detection if character is null */ 318 if (!c) { 319 port->icount.brk++; 320 if (uart_handle_break(port)) 321 continue; 322 } else { 323 port->icount.frame++; 324 } 325 } 326 327 sr &= port->read_status_mask; 328 329 if (sr & USART_SR_PE) { 330 flag = TTY_PARITY; 331 } else if (sr & USART_SR_FE) { 332 if (!c) 333 flag = TTY_BREAK; 334 else 335 flag = TTY_FRAME; 336 } 337 } 338 339 if (uart_prepare_sysrq_char(port, c)) 340 continue; 341 uart_insert_char(port, sr, USART_SR_ORE, c, flag); 342 } 343 344 return size; 345 } 346 347 static void stm32_usart_push_buffer_dma(struct uart_port *port, unsigned int dma_size) 348 { 349 struct stm32_port *stm32_port = to_stm32_port(port); 350 struct tty_port *ttyport = &stm32_port->port.state->port; 351 unsigned char *dma_start; 352 int dma_count, i; 353 354 dma_start = stm32_port->rx_buf + (RX_BUF_L - stm32_port->last_res); 355 356 /* 357 * Apply rdr_mask on buffer in order to mask parity bit. 358 * This loop is useless in cs8 mode because DMA copies only 359 * 8 bits and already ignores parity bit. 360 */ 361 if (!(stm32_port->rdr_mask == (BIT(8) - 1))) 362 for (i = 0; i < dma_size; i++) 363 *(dma_start + i) &= stm32_port->rdr_mask; 364 365 dma_count = tty_insert_flip_string(ttyport, dma_start, dma_size); 366 port->icount.rx += dma_count; 367 if (dma_count != dma_size) 368 port->icount.buf_overrun++; 369 stm32_port->last_res -= dma_count; 370 if (stm32_port->last_res == 0) 371 stm32_port->last_res = RX_BUF_L; 372 } 373 374 static unsigned int stm32_usart_receive_chars_dma(struct uart_port *port) 375 { 376 struct stm32_port *stm32_port = to_stm32_port(port); 377 unsigned int dma_size, size = 0; 378 379 /* DMA buffer is configured in cyclic mode and handles the rollback of the buffer. */ 380 if (stm32_port->rx_dma_state.residue > stm32_port->last_res) { 381 /* Conditional first part: from last_res to end of DMA buffer */ 382 dma_size = stm32_port->last_res; 383 stm32_usart_push_buffer_dma(port, dma_size); 384 size = dma_size; 385 } 386 387 dma_size = stm32_port->last_res - stm32_port->rx_dma_state.residue; 388 stm32_usart_push_buffer_dma(port, dma_size); 389 size += dma_size; 390 391 return size; 392 } 393 394 static unsigned int stm32_usart_receive_chars(struct uart_port *port, bool force_dma_flush) 395 { 396 struct stm32_port *stm32_port = to_stm32_port(port); 397 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 398 enum dma_status rx_dma_status; 399 u32 sr; 400 unsigned int size = 0; 401 402 if (stm32_usart_rx_dma_enabled(port) || force_dma_flush) { 403 rx_dma_status = dmaengine_tx_status(stm32_port->rx_ch, 404 stm32_port->rx_ch->cookie, 405 &stm32_port->rx_dma_state); 406 if (rx_dma_status == DMA_IN_PROGRESS) { 407 /* Empty DMA buffer */ 408 size = stm32_usart_receive_chars_dma(port); 409 sr = readl_relaxed(port->membase + ofs->isr); 410 if (sr & USART_SR_ERR_MASK) { 411 /* Disable DMA request line */ 412 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR); 413 414 /* Switch to PIO mode to handle the errors */ 415 size += stm32_usart_receive_chars_pio(port); 416 417 /* Switch back to DMA mode */ 418 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAR); 419 } 420 } else { 421 /* Disable RX DMA */ 422 dmaengine_terminate_async(stm32_port->rx_ch); 423 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR); 424 /* Fall back to interrupt mode */ 425 dev_dbg(port->dev, "DMA error, fallback to irq mode\n"); 426 size = stm32_usart_receive_chars_pio(port); 427 } 428 } else { 429 size = stm32_usart_receive_chars_pio(port); 430 } 431 432 return size; 433 } 434 435 static void stm32_usart_tx_dma_terminate(struct stm32_port *stm32_port) 436 { 437 dmaengine_terminate_async(stm32_port->tx_ch); 438 stm32_port->tx_dma_busy = false; 439 } 440 441 static bool stm32_usart_tx_dma_started(struct stm32_port *stm32_port) 442 { 443 /* 444 * We cannot use the function "dmaengine_tx_status" to know the 445 * status of DMA. This function does not show if the "dma complete" 446 * callback of the DMA transaction has been called. So we prefer 447 * to use "tx_dma_busy" flag to prevent dual DMA transaction at the 448 * same time. 449 */ 450 return stm32_port->tx_dma_busy; 451 } 452 453 static bool stm32_usart_tx_dma_enabled(struct stm32_port *stm32_port) 454 { 455 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 456 457 return !!(readl_relaxed(stm32_port->port.membase + ofs->cr3) & USART_CR3_DMAT); 458 } 459 460 static void stm32_usart_tx_dma_complete(void *arg) 461 { 462 struct uart_port *port = arg; 463 struct stm32_port *stm32port = to_stm32_port(port); 464 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 465 unsigned long flags; 466 467 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 468 stm32_usart_tx_dma_terminate(stm32port); 469 470 /* Let's see if we have pending data to send */ 471 spin_lock_irqsave(&port->lock, flags); 472 stm32_usart_transmit_chars(port); 473 spin_unlock_irqrestore(&port->lock, flags); 474 } 475 476 static void stm32_usart_tx_interrupt_enable(struct uart_port *port) 477 { 478 struct stm32_port *stm32_port = to_stm32_port(port); 479 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 480 481 /* 482 * Enables TX FIFO threashold irq when FIFO is enabled, 483 * or TX empty irq when FIFO is disabled 484 */ 485 if (stm32_port->fifoen && stm32_port->txftcfg >= 0) 486 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_TXFTIE); 487 else 488 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TXEIE); 489 } 490 491 static void stm32_usart_tc_interrupt_enable(struct uart_port *port) 492 { 493 struct stm32_port *stm32_port = to_stm32_port(port); 494 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 495 496 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TCIE); 497 } 498 499 static void stm32_usart_rx_dma_complete(void *arg) 500 { 501 struct uart_port *port = arg; 502 struct tty_port *tport = &port->state->port; 503 unsigned int size; 504 unsigned long flags; 505 506 spin_lock_irqsave(&port->lock, flags); 507 size = stm32_usart_receive_chars(port, false); 508 uart_unlock_and_check_sysrq_irqrestore(port, flags); 509 if (size) 510 tty_flip_buffer_push(tport); 511 } 512 513 static void stm32_usart_tx_interrupt_disable(struct uart_port *port) 514 { 515 struct stm32_port *stm32_port = to_stm32_port(port); 516 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 517 518 if (stm32_port->fifoen && stm32_port->txftcfg >= 0) 519 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_TXFTIE); 520 else 521 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_TXEIE); 522 } 523 524 static void stm32_usart_tc_interrupt_disable(struct uart_port *port) 525 { 526 struct stm32_port *stm32_port = to_stm32_port(port); 527 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 528 529 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_TCIE); 530 } 531 532 static void stm32_usart_rs485_rts_enable(struct uart_port *port) 533 { 534 struct stm32_port *stm32_port = to_stm32_port(port); 535 struct serial_rs485 *rs485conf = &port->rs485; 536 537 if (stm32_port->hw_flow_control || 538 !(rs485conf->flags & SER_RS485_ENABLED)) 539 return; 540 541 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 542 mctrl_gpio_set(stm32_port->gpios, 543 stm32_port->port.mctrl | TIOCM_RTS); 544 } else { 545 mctrl_gpio_set(stm32_port->gpios, 546 stm32_port->port.mctrl & ~TIOCM_RTS); 547 } 548 } 549 550 static void stm32_usart_rs485_rts_disable(struct uart_port *port) 551 { 552 struct stm32_port *stm32_port = to_stm32_port(port); 553 struct serial_rs485 *rs485conf = &port->rs485; 554 555 if (stm32_port->hw_flow_control || 556 !(rs485conf->flags & SER_RS485_ENABLED)) 557 return; 558 559 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 560 mctrl_gpio_set(stm32_port->gpios, 561 stm32_port->port.mctrl & ~TIOCM_RTS); 562 } else { 563 mctrl_gpio_set(stm32_port->gpios, 564 stm32_port->port.mctrl | TIOCM_RTS); 565 } 566 } 567 568 static void stm32_usart_transmit_chars_pio(struct uart_port *port) 569 { 570 struct stm32_port *stm32_port = to_stm32_port(port); 571 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 572 struct circ_buf *xmit = &port->state->xmit; 573 574 if (stm32_usart_tx_dma_enabled(stm32_port)) 575 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 576 577 while (!uart_circ_empty(xmit)) { 578 /* Check that TDR is empty before filling FIFO */ 579 if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE)) 580 break; 581 writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr); 582 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 583 port->icount.tx++; 584 } 585 586 /* rely on TXE irq (mask or unmask) for sending remaining data */ 587 if (uart_circ_empty(xmit)) 588 stm32_usart_tx_interrupt_disable(port); 589 else 590 stm32_usart_tx_interrupt_enable(port); 591 } 592 593 static void stm32_usart_transmit_chars_dma(struct uart_port *port) 594 { 595 struct stm32_port *stm32port = to_stm32_port(port); 596 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 597 struct circ_buf *xmit = &port->state->xmit; 598 struct dma_async_tx_descriptor *desc = NULL; 599 unsigned int count; 600 601 if (stm32_usart_tx_dma_started(stm32port)) { 602 if (!stm32_usart_tx_dma_enabled(stm32port)) 603 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT); 604 return; 605 } 606 607 count = uart_circ_chars_pending(xmit); 608 609 if (count > TX_BUF_L) 610 count = TX_BUF_L; 611 612 if (xmit->tail < xmit->head) { 613 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count); 614 } else { 615 size_t one = UART_XMIT_SIZE - xmit->tail; 616 size_t two; 617 618 if (one > count) 619 one = count; 620 two = count - one; 621 622 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one); 623 if (two) 624 memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two); 625 } 626 627 desc = dmaengine_prep_slave_single(stm32port->tx_ch, 628 stm32port->tx_dma_buf, 629 count, 630 DMA_MEM_TO_DEV, 631 DMA_PREP_INTERRUPT); 632 633 if (!desc) 634 goto fallback_err; 635 636 /* 637 * Set "tx_dma_busy" flag. This flag will be released when 638 * dmaengine_terminate_async will be called. This flag helps 639 * transmit_chars_dma not to start another DMA transaction 640 * if the callback of the previous is not yet called. 641 */ 642 stm32port->tx_dma_busy = true; 643 644 desc->callback = stm32_usart_tx_dma_complete; 645 desc->callback_param = port; 646 647 /* Push current DMA TX transaction in the pending queue */ 648 if (dma_submit_error(dmaengine_submit(desc))) { 649 /* dma no yet started, safe to free resources */ 650 stm32_usart_tx_dma_terminate(stm32port); 651 goto fallback_err; 652 } 653 654 /* Issue pending DMA TX requests */ 655 dma_async_issue_pending(stm32port->tx_ch); 656 657 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT); 658 659 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); 660 port->icount.tx += count; 661 return; 662 663 fallback_err: 664 stm32_usart_transmit_chars_pio(port); 665 } 666 667 static void stm32_usart_transmit_chars(struct uart_port *port) 668 { 669 struct stm32_port *stm32_port = to_stm32_port(port); 670 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 671 struct circ_buf *xmit = &port->state->xmit; 672 u32 isr; 673 int ret; 674 675 if (!stm32_port->hw_flow_control && 676 port->rs485.flags & SER_RS485_ENABLED) { 677 stm32_port->txdone = false; 678 stm32_usart_tc_interrupt_disable(port); 679 stm32_usart_rs485_rts_enable(port); 680 } 681 682 if (port->x_char) { 683 if (stm32_usart_tx_dma_started(stm32_port) && 684 stm32_usart_tx_dma_enabled(stm32_port)) 685 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 686 687 /* Check that TDR is empty before filling FIFO */ 688 ret = 689 readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, 690 isr, 691 (isr & USART_SR_TXE), 692 10, 1000); 693 if (ret) 694 dev_warn(port->dev, "1 character may be erased\n"); 695 696 writel_relaxed(port->x_char, port->membase + ofs->tdr); 697 port->x_char = 0; 698 port->icount.tx++; 699 if (stm32_usart_tx_dma_started(stm32_port)) 700 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT); 701 return; 702 } 703 704 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 705 stm32_usart_tx_interrupt_disable(port); 706 return; 707 } 708 709 if (ofs->icr == UNDEF_REG) 710 stm32_usart_clr_bits(port, ofs->isr, USART_SR_TC); 711 else 712 writel_relaxed(USART_ICR_TCCF, port->membase + ofs->icr); 713 714 if (stm32_port->tx_ch) 715 stm32_usart_transmit_chars_dma(port); 716 else 717 stm32_usart_transmit_chars_pio(port); 718 719 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 720 uart_write_wakeup(port); 721 722 if (uart_circ_empty(xmit)) { 723 stm32_usart_tx_interrupt_disable(port); 724 if (!stm32_port->hw_flow_control && 725 port->rs485.flags & SER_RS485_ENABLED) { 726 stm32_port->txdone = true; 727 stm32_usart_tc_interrupt_enable(port); 728 } 729 } 730 } 731 732 static irqreturn_t stm32_usart_interrupt(int irq, void *ptr) 733 { 734 struct uart_port *port = ptr; 735 struct tty_port *tport = &port->state->port; 736 struct stm32_port *stm32_port = to_stm32_port(port); 737 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 738 u32 sr; 739 unsigned int size; 740 741 sr = readl_relaxed(port->membase + ofs->isr); 742 743 if (!stm32_port->hw_flow_control && 744 port->rs485.flags & SER_RS485_ENABLED && 745 (sr & USART_SR_TC)) { 746 stm32_usart_tc_interrupt_disable(port); 747 stm32_usart_rs485_rts_disable(port); 748 } 749 750 if ((sr & USART_SR_RTOF) && ofs->icr != UNDEF_REG) 751 writel_relaxed(USART_ICR_RTOCF, 752 port->membase + ofs->icr); 753 754 if ((sr & USART_SR_WUF) && ofs->icr != UNDEF_REG) { 755 /* Clear wake up flag and disable wake up interrupt */ 756 writel_relaxed(USART_ICR_WUCF, 757 port->membase + ofs->icr); 758 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE); 759 if (irqd_is_wakeup_set(irq_get_irq_data(port->irq))) 760 pm_wakeup_event(tport->tty->dev, 0); 761 } 762 763 /* 764 * rx errors in dma mode has to be handled ASAP to avoid overrun as the DMA request 765 * line has been masked by HW and rx data are stacking in FIFO. 766 */ 767 if (!stm32_port->throttled) { 768 if (((sr & USART_SR_RXNE) && !stm32_usart_rx_dma_enabled(port)) || 769 ((sr & USART_SR_ERR_MASK) && stm32_usart_rx_dma_enabled(port))) { 770 spin_lock(&port->lock); 771 size = stm32_usart_receive_chars(port, false); 772 uart_unlock_and_check_sysrq(port); 773 if (size) 774 tty_flip_buffer_push(tport); 775 } 776 } 777 778 if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch)) { 779 spin_lock(&port->lock); 780 stm32_usart_transmit_chars(port); 781 spin_unlock(&port->lock); 782 } 783 784 if (stm32_usart_rx_dma_enabled(port)) 785 return IRQ_WAKE_THREAD; 786 else 787 return IRQ_HANDLED; 788 } 789 790 static irqreturn_t stm32_usart_threaded_interrupt(int irq, void *ptr) 791 { 792 struct uart_port *port = ptr; 793 struct tty_port *tport = &port->state->port; 794 struct stm32_port *stm32_port = to_stm32_port(port); 795 unsigned int size; 796 unsigned long flags; 797 798 /* Receiver timeout irq for DMA RX */ 799 if (!stm32_port->throttled) { 800 spin_lock_irqsave(&port->lock, flags); 801 size = stm32_usart_receive_chars(port, false); 802 uart_unlock_and_check_sysrq_irqrestore(port, flags); 803 if (size) 804 tty_flip_buffer_push(tport); 805 } 806 807 return IRQ_HANDLED; 808 } 809 810 static unsigned int stm32_usart_tx_empty(struct uart_port *port) 811 { 812 struct stm32_port *stm32_port = to_stm32_port(port); 813 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 814 815 if (readl_relaxed(port->membase + ofs->isr) & USART_SR_TC) 816 return TIOCSER_TEMT; 817 818 return 0; 819 } 820 821 static void stm32_usart_set_mctrl(struct uart_port *port, unsigned int mctrl) 822 { 823 struct stm32_port *stm32_port = to_stm32_port(port); 824 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 825 826 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) 827 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_RTSE); 828 else 829 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_RTSE); 830 831 mctrl_gpio_set(stm32_port->gpios, mctrl); 832 } 833 834 static unsigned int stm32_usart_get_mctrl(struct uart_port *port) 835 { 836 struct stm32_port *stm32_port = to_stm32_port(port); 837 unsigned int ret; 838 839 /* This routine is used to get signals of: DCD, DSR, RI, and CTS */ 840 ret = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; 841 842 return mctrl_gpio_get(stm32_port->gpios, &ret); 843 } 844 845 static void stm32_usart_enable_ms(struct uart_port *port) 846 { 847 mctrl_gpio_enable_ms(to_stm32_port(port)->gpios); 848 } 849 850 static void stm32_usart_disable_ms(struct uart_port *port) 851 { 852 mctrl_gpio_disable_ms(to_stm32_port(port)->gpios); 853 } 854 855 /* Transmit stop */ 856 static void stm32_usart_stop_tx(struct uart_port *port) 857 { 858 struct stm32_port *stm32_port = to_stm32_port(port); 859 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 860 861 stm32_usart_tx_interrupt_disable(port); 862 if (stm32_usart_tx_dma_started(stm32_port) && stm32_usart_tx_dma_enabled(stm32_port)) 863 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 864 865 stm32_usart_rs485_rts_disable(port); 866 } 867 868 /* There are probably characters waiting to be transmitted. */ 869 static void stm32_usart_start_tx(struct uart_port *port) 870 { 871 struct circ_buf *xmit = &port->state->xmit; 872 873 if (uart_circ_empty(xmit) && !port->x_char) { 874 stm32_usart_rs485_rts_disable(port); 875 return; 876 } 877 878 stm32_usart_rs485_rts_enable(port); 879 880 stm32_usart_transmit_chars(port); 881 } 882 883 /* Flush the transmit buffer. */ 884 static void stm32_usart_flush_buffer(struct uart_port *port) 885 { 886 struct stm32_port *stm32_port = to_stm32_port(port); 887 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 888 889 if (stm32_port->tx_ch) { 890 stm32_usart_tx_dma_terminate(stm32_port); 891 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 892 } 893 } 894 895 /* Throttle the remote when input buffer is about to overflow. */ 896 static void stm32_usart_throttle(struct uart_port *port) 897 { 898 struct stm32_port *stm32_port = to_stm32_port(port); 899 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 900 unsigned long flags; 901 902 spin_lock_irqsave(&port->lock, flags); 903 904 /* 905 * Disable DMA request line if enabled, so the RX data gets queued into the FIFO. 906 * Hardware flow control is triggered when RX FIFO is full. 907 */ 908 if (stm32_usart_rx_dma_enabled(port)) 909 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR); 910 911 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq); 912 if (stm32_port->cr3_irq) 913 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); 914 915 stm32_port->throttled = true; 916 spin_unlock_irqrestore(&port->lock, flags); 917 } 918 919 /* Unthrottle the remote, the input buffer can now accept data. */ 920 static void stm32_usart_unthrottle(struct uart_port *port) 921 { 922 struct stm32_port *stm32_port = to_stm32_port(port); 923 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 924 unsigned long flags; 925 926 spin_lock_irqsave(&port->lock, flags); 927 stm32_usart_set_bits(port, ofs->cr1, stm32_port->cr1_irq); 928 if (stm32_port->cr3_irq) 929 stm32_usart_set_bits(port, ofs->cr3, stm32_port->cr3_irq); 930 931 /* 932 * Switch back to DMA mode (re-enable DMA request line). 933 * Hardware flow control is stopped when FIFO is not full any more. 934 */ 935 if (stm32_port->rx_ch) 936 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAR); 937 938 stm32_port->throttled = false; 939 spin_unlock_irqrestore(&port->lock, flags); 940 } 941 942 /* Receive stop */ 943 static void stm32_usart_stop_rx(struct uart_port *port) 944 { 945 struct stm32_port *stm32_port = to_stm32_port(port); 946 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 947 948 /* Disable DMA request line. */ 949 if (stm32_port->rx_ch) 950 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR); 951 952 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq); 953 if (stm32_port->cr3_irq) 954 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); 955 } 956 957 /* Handle breaks - ignored by us */ 958 static void stm32_usart_break_ctl(struct uart_port *port, int break_state) 959 { 960 } 961 962 static int stm32_usart_start_rx_dma_cyclic(struct uart_port *port) 963 { 964 struct stm32_port *stm32_port = to_stm32_port(port); 965 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 966 struct dma_async_tx_descriptor *desc; 967 int ret; 968 969 stm32_port->last_res = RX_BUF_L; 970 /* Prepare a DMA cyclic transaction */ 971 desc = dmaengine_prep_dma_cyclic(stm32_port->rx_ch, 972 stm32_port->rx_dma_buf, 973 RX_BUF_L, RX_BUF_P, 974 DMA_DEV_TO_MEM, 975 DMA_PREP_INTERRUPT); 976 if (!desc) { 977 dev_err(port->dev, "rx dma prep cyclic failed\n"); 978 return -ENODEV; 979 } 980 981 desc->callback = stm32_usart_rx_dma_complete; 982 desc->callback_param = port; 983 984 /* Push current DMA transaction in the pending queue */ 985 ret = dma_submit_error(dmaengine_submit(desc)); 986 if (ret) { 987 dmaengine_terminate_sync(stm32_port->rx_ch); 988 return ret; 989 } 990 991 /* Issue pending DMA requests */ 992 dma_async_issue_pending(stm32_port->rx_ch); 993 994 /* 995 * DMA request line not re-enabled at resume when port is throttled. 996 * It will be re-enabled by unthrottle ops. 997 */ 998 if (!stm32_port->throttled) 999 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAR); 1000 1001 return 0; 1002 } 1003 1004 static int stm32_usart_startup(struct uart_port *port) 1005 { 1006 struct stm32_port *stm32_port = to_stm32_port(port); 1007 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1008 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 1009 const char *name = to_platform_device(port->dev)->name; 1010 u32 val; 1011 int ret; 1012 1013 ret = request_threaded_irq(port->irq, stm32_usart_interrupt, 1014 stm32_usart_threaded_interrupt, 1015 IRQF_ONESHOT | IRQF_NO_SUSPEND, 1016 name, port); 1017 if (ret) 1018 return ret; 1019 1020 if (stm32_port->swap) { 1021 val = readl_relaxed(port->membase + ofs->cr2); 1022 val |= USART_CR2_SWAP; 1023 writel_relaxed(val, port->membase + ofs->cr2); 1024 } 1025 1026 /* RX FIFO Flush */ 1027 if (ofs->rqr != UNDEF_REG) 1028 writel_relaxed(USART_RQR_RXFRQ, port->membase + ofs->rqr); 1029 1030 if (stm32_port->rx_ch) { 1031 ret = stm32_usart_start_rx_dma_cyclic(port); 1032 if (ret) { 1033 free_irq(port->irq, port); 1034 return ret; 1035 } 1036 } 1037 1038 /* RX enabling */ 1039 val = stm32_port->cr1_irq | USART_CR1_RE | BIT(cfg->uart_enable_bit); 1040 stm32_usart_set_bits(port, ofs->cr1, val); 1041 1042 return 0; 1043 } 1044 1045 static void stm32_usart_shutdown(struct uart_port *port) 1046 { 1047 struct stm32_port *stm32_port = to_stm32_port(port); 1048 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1049 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 1050 u32 val, isr; 1051 int ret; 1052 1053 if (stm32_usart_tx_dma_enabled(stm32_port)) 1054 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 1055 1056 if (stm32_usart_tx_dma_started(stm32_port)) 1057 stm32_usart_tx_dma_terminate(stm32_port); 1058 1059 /* Disable modem control interrupts */ 1060 stm32_usart_disable_ms(port); 1061 1062 val = USART_CR1_TXEIE | USART_CR1_TE; 1063 val |= stm32_port->cr1_irq | USART_CR1_RE; 1064 val |= BIT(cfg->uart_enable_bit); 1065 if (stm32_port->fifoen) 1066 val |= USART_CR1_FIFOEN; 1067 1068 ret = readl_relaxed_poll_timeout(port->membase + ofs->isr, 1069 isr, (isr & USART_SR_TC), 1070 10, 100000); 1071 1072 /* Send the TC error message only when ISR_TC is not set */ 1073 if (ret) 1074 dev_err(port->dev, "Transmission is not complete\n"); 1075 1076 /* Disable RX DMA. */ 1077 if (stm32_port->rx_ch) 1078 dmaengine_terminate_async(stm32_port->rx_ch); 1079 1080 /* flush RX & TX FIFO */ 1081 if (ofs->rqr != UNDEF_REG) 1082 writel_relaxed(USART_RQR_TXFRQ | USART_RQR_RXFRQ, 1083 port->membase + ofs->rqr); 1084 1085 stm32_usart_clr_bits(port, ofs->cr1, val); 1086 1087 free_irq(port->irq, port); 1088 } 1089 1090 static void stm32_usart_set_termios(struct uart_port *port, 1091 struct ktermios *termios, 1092 struct ktermios *old) 1093 { 1094 struct stm32_port *stm32_port = to_stm32_port(port); 1095 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1096 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 1097 struct serial_rs485 *rs485conf = &port->rs485; 1098 unsigned int baud, bits; 1099 u32 usartdiv, mantissa, fraction, oversampling; 1100 tcflag_t cflag = termios->c_cflag; 1101 u32 cr1, cr2, cr3, isr; 1102 unsigned long flags; 1103 int ret; 1104 1105 if (!stm32_port->hw_flow_control) 1106 cflag &= ~CRTSCTS; 1107 1108 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8); 1109 1110 spin_lock_irqsave(&port->lock, flags); 1111 1112 ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, 1113 isr, 1114 (isr & USART_SR_TC), 1115 10, 100000); 1116 1117 /* Send the TC error message only when ISR_TC is not set. */ 1118 if (ret) 1119 dev_err(port->dev, "Transmission is not complete\n"); 1120 1121 /* Stop serial port and reset value */ 1122 writel_relaxed(0, port->membase + ofs->cr1); 1123 1124 /* flush RX & TX FIFO */ 1125 if (ofs->rqr != UNDEF_REG) 1126 writel_relaxed(USART_RQR_TXFRQ | USART_RQR_RXFRQ, 1127 port->membase + ofs->rqr); 1128 1129 cr1 = USART_CR1_TE | USART_CR1_RE; 1130 if (stm32_port->fifoen) 1131 cr1 |= USART_CR1_FIFOEN; 1132 cr2 = stm32_port->swap ? USART_CR2_SWAP : 0; 1133 1134 /* Tx and RX FIFO configuration */ 1135 cr3 = readl_relaxed(port->membase + ofs->cr3); 1136 cr3 &= USART_CR3_TXFTIE | USART_CR3_RXFTIE; 1137 if (stm32_port->fifoen) { 1138 if (stm32_port->txftcfg >= 0) 1139 cr3 |= stm32_port->txftcfg << USART_CR3_TXFTCFG_SHIFT; 1140 if (stm32_port->rxftcfg >= 0) 1141 cr3 |= stm32_port->rxftcfg << USART_CR3_RXFTCFG_SHIFT; 1142 } 1143 1144 if (cflag & CSTOPB) 1145 cr2 |= USART_CR2_STOP_2B; 1146 1147 bits = tty_get_char_size(cflag); 1148 stm32_port->rdr_mask = (BIT(bits) - 1); 1149 1150 if (cflag & PARENB) { 1151 bits++; 1152 cr1 |= USART_CR1_PCE; 1153 } 1154 1155 /* 1156 * Word length configuration: 1157 * CS8 + parity, 9 bits word aka [M1:M0] = 0b01 1158 * CS7 or (CS6 + parity), 7 bits word aka [M1:M0] = 0b10 1159 * CS8 or (CS7 + parity), 8 bits word aka [M1:M0] = 0b00 1160 * M0 and M1 already cleared by cr1 initialization. 1161 */ 1162 if (bits == 9) { 1163 cr1 |= USART_CR1_M0; 1164 } else if ((bits == 7) && cfg->has_7bits_data) { 1165 cr1 |= USART_CR1_M1; 1166 } else if (bits != 8) { 1167 dev_dbg(port->dev, "Unsupported data bits config: %u bits\n" 1168 , bits); 1169 cflag &= ~CSIZE; 1170 cflag |= CS8; 1171 termios->c_cflag = cflag; 1172 bits = 8; 1173 if (cflag & PARENB) { 1174 bits++; 1175 cr1 |= USART_CR1_M0; 1176 } 1177 } 1178 1179 if (ofs->rtor != UNDEF_REG && (stm32_port->rx_ch || 1180 (stm32_port->fifoen && 1181 stm32_port->rxftcfg >= 0))) { 1182 if (cflag & CSTOPB) 1183 bits = bits + 3; /* 1 start bit + 2 stop bits */ 1184 else 1185 bits = bits + 2; /* 1 start bit + 1 stop bit */ 1186 1187 /* RX timeout irq to occur after last stop bit + bits */ 1188 stm32_port->cr1_irq = USART_CR1_RTOIE; 1189 writel_relaxed(bits, port->membase + ofs->rtor); 1190 cr2 |= USART_CR2_RTOEN; 1191 /* 1192 * Enable fifo threshold irq in two cases, either when there is no DMA, or when 1193 * wake up over usart, from low power until the DMA gets re-enabled by resume. 1194 */ 1195 stm32_port->cr3_irq = USART_CR3_RXFTIE; 1196 } 1197 1198 cr1 |= stm32_port->cr1_irq; 1199 cr3 |= stm32_port->cr3_irq; 1200 1201 if (cflag & PARODD) 1202 cr1 |= USART_CR1_PS; 1203 1204 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); 1205 if (cflag & CRTSCTS) { 1206 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 1207 cr3 |= USART_CR3_CTSE | USART_CR3_RTSE; 1208 } 1209 1210 usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud); 1211 1212 /* 1213 * The USART supports 16 or 8 times oversampling. 1214 * By default we prefer 16 times oversampling, so that the receiver 1215 * has a better tolerance to clock deviations. 1216 * 8 times oversampling is only used to achieve higher speeds. 1217 */ 1218 if (usartdiv < 16) { 1219 oversampling = 8; 1220 cr1 |= USART_CR1_OVER8; 1221 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_OVER8); 1222 } else { 1223 oversampling = 16; 1224 cr1 &= ~USART_CR1_OVER8; 1225 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_OVER8); 1226 } 1227 1228 mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT; 1229 fraction = usartdiv % oversampling; 1230 writel_relaxed(mantissa | fraction, port->membase + ofs->brr); 1231 1232 uart_update_timeout(port, cflag, baud); 1233 1234 port->read_status_mask = USART_SR_ORE; 1235 if (termios->c_iflag & INPCK) 1236 port->read_status_mask |= USART_SR_PE | USART_SR_FE; 1237 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 1238 port->read_status_mask |= USART_SR_FE; 1239 1240 /* Characters to ignore */ 1241 port->ignore_status_mask = 0; 1242 if (termios->c_iflag & IGNPAR) 1243 port->ignore_status_mask = USART_SR_PE | USART_SR_FE; 1244 if (termios->c_iflag & IGNBRK) { 1245 port->ignore_status_mask |= USART_SR_FE; 1246 /* 1247 * If we're ignoring parity and break indicators, 1248 * ignore overruns too (for real raw support). 1249 */ 1250 if (termios->c_iflag & IGNPAR) 1251 port->ignore_status_mask |= USART_SR_ORE; 1252 } 1253 1254 /* Ignore all characters if CREAD is not set */ 1255 if ((termios->c_cflag & CREAD) == 0) 1256 port->ignore_status_mask |= USART_SR_DUMMY_RX; 1257 1258 if (stm32_port->rx_ch) { 1259 /* 1260 * Setup DMA to collect only valid data and enable error irqs. 1261 * This also enables break reception when using DMA. 1262 */ 1263 cr1 |= USART_CR1_PEIE; 1264 cr3 |= USART_CR3_EIE; 1265 cr3 |= USART_CR3_DMAR; 1266 cr3 |= USART_CR3_DDRE; 1267 } 1268 1269 if (rs485conf->flags & SER_RS485_ENABLED) { 1270 stm32_usart_config_reg_rs485(&cr1, &cr3, 1271 rs485conf->delay_rts_before_send, 1272 rs485conf->delay_rts_after_send, 1273 baud); 1274 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 1275 cr3 &= ~USART_CR3_DEP; 1276 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND; 1277 } else { 1278 cr3 |= USART_CR3_DEP; 1279 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; 1280 } 1281 1282 } else { 1283 cr3 &= ~(USART_CR3_DEM | USART_CR3_DEP); 1284 cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK); 1285 } 1286 1287 /* Configure wake up from low power on start bit detection */ 1288 if (stm32_port->wakeup_src) { 1289 cr3 &= ~USART_CR3_WUS_MASK; 1290 cr3 |= USART_CR3_WUS_START_BIT; 1291 } 1292 1293 writel_relaxed(cr3, port->membase + ofs->cr3); 1294 writel_relaxed(cr2, port->membase + ofs->cr2); 1295 writel_relaxed(cr1, port->membase + ofs->cr1); 1296 1297 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 1298 spin_unlock_irqrestore(&port->lock, flags); 1299 1300 /* Handle modem control interrupts */ 1301 if (UART_ENABLE_MS(port, termios->c_cflag)) 1302 stm32_usart_enable_ms(port); 1303 else 1304 stm32_usart_disable_ms(port); 1305 } 1306 1307 static const char *stm32_usart_type(struct uart_port *port) 1308 { 1309 return (port->type == PORT_STM32) ? DRIVER_NAME : NULL; 1310 } 1311 1312 static void stm32_usart_release_port(struct uart_port *port) 1313 { 1314 } 1315 1316 static int stm32_usart_request_port(struct uart_port *port) 1317 { 1318 return 0; 1319 } 1320 1321 static void stm32_usart_config_port(struct uart_port *port, int flags) 1322 { 1323 if (flags & UART_CONFIG_TYPE) 1324 port->type = PORT_STM32; 1325 } 1326 1327 static int 1328 stm32_usart_verify_port(struct uart_port *port, struct serial_struct *ser) 1329 { 1330 /* No user changeable parameters */ 1331 return -EINVAL; 1332 } 1333 1334 static void stm32_usart_pm(struct uart_port *port, unsigned int state, 1335 unsigned int oldstate) 1336 { 1337 struct stm32_port *stm32port = container_of(port, 1338 struct stm32_port, port); 1339 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 1340 const struct stm32_usart_config *cfg = &stm32port->info->cfg; 1341 unsigned long flags; 1342 1343 switch (state) { 1344 case UART_PM_STATE_ON: 1345 pm_runtime_get_sync(port->dev); 1346 break; 1347 case UART_PM_STATE_OFF: 1348 spin_lock_irqsave(&port->lock, flags); 1349 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 1350 spin_unlock_irqrestore(&port->lock, flags); 1351 pm_runtime_put_sync(port->dev); 1352 break; 1353 } 1354 } 1355 1356 #if defined(CONFIG_CONSOLE_POLL) 1357 1358 /* Callbacks for characters polling in debug context (i.e. KGDB). */ 1359 static int stm32_usart_poll_init(struct uart_port *port) 1360 { 1361 struct stm32_port *stm32_port = to_stm32_port(port); 1362 1363 return clk_prepare_enable(stm32_port->clk); 1364 } 1365 1366 static int stm32_usart_poll_get_char(struct uart_port *port) 1367 { 1368 struct stm32_port *stm32_port = to_stm32_port(port); 1369 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1370 1371 if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_RXNE)) 1372 return NO_POLL_CHAR; 1373 1374 return readl_relaxed(port->membase + ofs->rdr) & stm32_port->rdr_mask; 1375 } 1376 1377 static void stm32_usart_poll_put_char(struct uart_port *port, unsigned char ch) 1378 { 1379 stm32_usart_console_putchar(port, ch); 1380 } 1381 #endif /* CONFIG_CONSOLE_POLL */ 1382 1383 static const struct uart_ops stm32_uart_ops = { 1384 .tx_empty = stm32_usart_tx_empty, 1385 .set_mctrl = stm32_usart_set_mctrl, 1386 .get_mctrl = stm32_usart_get_mctrl, 1387 .stop_tx = stm32_usart_stop_tx, 1388 .start_tx = stm32_usart_start_tx, 1389 .throttle = stm32_usart_throttle, 1390 .unthrottle = stm32_usart_unthrottle, 1391 .stop_rx = stm32_usart_stop_rx, 1392 .enable_ms = stm32_usart_enable_ms, 1393 .break_ctl = stm32_usart_break_ctl, 1394 .startup = stm32_usart_startup, 1395 .shutdown = stm32_usart_shutdown, 1396 .flush_buffer = stm32_usart_flush_buffer, 1397 .set_termios = stm32_usart_set_termios, 1398 .pm = stm32_usart_pm, 1399 .type = stm32_usart_type, 1400 .release_port = stm32_usart_release_port, 1401 .request_port = stm32_usart_request_port, 1402 .config_port = stm32_usart_config_port, 1403 .verify_port = stm32_usart_verify_port, 1404 #if defined(CONFIG_CONSOLE_POLL) 1405 .poll_init = stm32_usart_poll_init, 1406 .poll_get_char = stm32_usart_poll_get_char, 1407 .poll_put_char = stm32_usart_poll_put_char, 1408 #endif /* CONFIG_CONSOLE_POLL */ 1409 }; 1410 1411 /* 1412 * STM32H7 RX & TX FIFO threshold configuration (CR3 RXFTCFG / TXFTCFG) 1413 * Note: 1 isn't a valid value in RXFTCFG / TXFTCFG. In this case, 1414 * RXNEIE / TXEIE can be used instead of threshold irqs: RXFTIE / TXFTIE. 1415 * So, RXFTCFG / TXFTCFG bitfields values are encoded as array index + 1. 1416 */ 1417 static const u32 stm32h7_usart_fifo_thresh_cfg[] = { 1, 2, 4, 8, 12, 14, 16 }; 1418 1419 static void stm32_usart_get_ftcfg(struct platform_device *pdev, const char *p, 1420 int *ftcfg) 1421 { 1422 u32 bytes, i; 1423 1424 /* DT option to get RX & TX FIFO threshold (default to 8 bytes) */ 1425 if (of_property_read_u32(pdev->dev.of_node, p, &bytes)) 1426 bytes = 8; 1427 1428 for (i = 0; i < ARRAY_SIZE(stm32h7_usart_fifo_thresh_cfg); i++) 1429 if (stm32h7_usart_fifo_thresh_cfg[i] >= bytes) 1430 break; 1431 if (i >= ARRAY_SIZE(stm32h7_usart_fifo_thresh_cfg)) 1432 i = ARRAY_SIZE(stm32h7_usart_fifo_thresh_cfg) - 1; 1433 1434 dev_dbg(&pdev->dev, "%s set to %d bytes\n", p, 1435 stm32h7_usart_fifo_thresh_cfg[i]); 1436 1437 /* Provide FIFO threshold ftcfg (1 is invalid: threshold irq unused) */ 1438 if (i) 1439 *ftcfg = i - 1; 1440 else 1441 *ftcfg = -EINVAL; 1442 } 1443 1444 static void stm32_usart_deinit_port(struct stm32_port *stm32port) 1445 { 1446 clk_disable_unprepare(stm32port->clk); 1447 } 1448 1449 static const struct serial_rs485 stm32_rs485_supported = { 1450 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND | 1451 SER_RS485_RX_DURING_TX, 1452 .delay_rts_before_send = 1, 1453 .delay_rts_after_send = 1, 1454 }; 1455 1456 static int stm32_usart_init_port(struct stm32_port *stm32port, 1457 struct platform_device *pdev) 1458 { 1459 struct uart_port *port = &stm32port->port; 1460 struct resource *res; 1461 int ret, irq; 1462 1463 irq = platform_get_irq(pdev, 0); 1464 if (irq < 0) 1465 return irq; 1466 1467 port->iotype = UPIO_MEM; 1468 port->flags = UPF_BOOT_AUTOCONF; 1469 port->ops = &stm32_uart_ops; 1470 port->dev = &pdev->dev; 1471 port->fifosize = stm32port->info->cfg.fifosize; 1472 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_STM32_CONSOLE); 1473 port->irq = irq; 1474 port->rs485_config = stm32_usart_config_rs485; 1475 port->rs485_supported = stm32_rs485_supported; 1476 1477 ret = stm32_usart_init_rs485(port, pdev); 1478 if (ret) 1479 return ret; 1480 1481 stm32port->wakeup_src = stm32port->info->cfg.has_wakeup && 1482 of_property_read_bool(pdev->dev.of_node, "wakeup-source"); 1483 1484 stm32port->swap = stm32port->info->cfg.has_swap && 1485 of_property_read_bool(pdev->dev.of_node, "rx-tx-swap"); 1486 1487 stm32port->fifoen = stm32port->info->cfg.has_fifo; 1488 if (stm32port->fifoen) { 1489 stm32_usart_get_ftcfg(pdev, "rx-threshold", 1490 &stm32port->rxftcfg); 1491 stm32_usart_get_ftcfg(pdev, "tx-threshold", 1492 &stm32port->txftcfg); 1493 } 1494 1495 port->membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1496 if (IS_ERR(port->membase)) 1497 return PTR_ERR(port->membase); 1498 port->mapbase = res->start; 1499 1500 spin_lock_init(&port->lock); 1501 1502 stm32port->clk = devm_clk_get(&pdev->dev, NULL); 1503 if (IS_ERR(stm32port->clk)) 1504 return PTR_ERR(stm32port->clk); 1505 1506 /* Ensure that clk rate is correct by enabling the clk */ 1507 ret = clk_prepare_enable(stm32port->clk); 1508 if (ret) 1509 return ret; 1510 1511 stm32port->port.uartclk = clk_get_rate(stm32port->clk); 1512 if (!stm32port->port.uartclk) { 1513 ret = -EINVAL; 1514 goto err_clk; 1515 } 1516 1517 stm32port->gpios = mctrl_gpio_init(&stm32port->port, 0); 1518 if (IS_ERR(stm32port->gpios)) { 1519 ret = PTR_ERR(stm32port->gpios); 1520 goto err_clk; 1521 } 1522 1523 /* 1524 * Both CTS/RTS gpios and "st,hw-flow-ctrl" (deprecated) or "uart-has-rtscts" 1525 * properties should not be specified. 1526 */ 1527 if (stm32port->hw_flow_control) { 1528 if (mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_CTS) || 1529 mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_RTS)) { 1530 dev_err(&pdev->dev, "Conflicting RTS/CTS config\n"); 1531 ret = -EINVAL; 1532 goto err_clk; 1533 } 1534 } 1535 1536 return ret; 1537 1538 err_clk: 1539 clk_disable_unprepare(stm32port->clk); 1540 1541 return ret; 1542 } 1543 1544 static struct stm32_port *stm32_usart_of_get_port(struct platform_device *pdev) 1545 { 1546 struct device_node *np = pdev->dev.of_node; 1547 int id; 1548 1549 if (!np) 1550 return NULL; 1551 1552 id = of_alias_get_id(np, "serial"); 1553 if (id < 0) { 1554 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", id); 1555 return NULL; 1556 } 1557 1558 if (WARN_ON(id >= STM32_MAX_PORTS)) 1559 return NULL; 1560 1561 stm32_ports[id].hw_flow_control = 1562 of_property_read_bool (np, "st,hw-flow-ctrl") /*deprecated*/ || 1563 of_property_read_bool (np, "uart-has-rtscts"); 1564 stm32_ports[id].port.line = id; 1565 stm32_ports[id].cr1_irq = USART_CR1_RXNEIE; 1566 stm32_ports[id].cr3_irq = 0; 1567 stm32_ports[id].last_res = RX_BUF_L; 1568 return &stm32_ports[id]; 1569 } 1570 1571 #ifdef CONFIG_OF 1572 static const struct of_device_id stm32_match[] = { 1573 { .compatible = "st,stm32-uart", .data = &stm32f4_info}, 1574 { .compatible = "st,stm32f7-uart", .data = &stm32f7_info}, 1575 { .compatible = "st,stm32h7-uart", .data = &stm32h7_info}, 1576 {}, 1577 }; 1578 1579 MODULE_DEVICE_TABLE(of, stm32_match); 1580 #endif 1581 1582 static void stm32_usart_of_dma_rx_remove(struct stm32_port *stm32port, 1583 struct platform_device *pdev) 1584 { 1585 if (stm32port->rx_buf) 1586 dma_free_coherent(&pdev->dev, RX_BUF_L, stm32port->rx_buf, 1587 stm32port->rx_dma_buf); 1588 } 1589 1590 static int stm32_usart_of_dma_rx_probe(struct stm32_port *stm32port, 1591 struct platform_device *pdev) 1592 { 1593 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 1594 struct uart_port *port = &stm32port->port; 1595 struct device *dev = &pdev->dev; 1596 struct dma_slave_config config; 1597 int ret; 1598 1599 /* 1600 * Using DMA and threaded handler for the console could lead to 1601 * deadlocks. 1602 */ 1603 if (uart_console(port)) 1604 return -ENODEV; 1605 1606 stm32port->rx_buf = dma_alloc_coherent(dev, RX_BUF_L, 1607 &stm32port->rx_dma_buf, 1608 GFP_KERNEL); 1609 if (!stm32port->rx_buf) 1610 return -ENOMEM; 1611 1612 /* Configure DMA channel */ 1613 memset(&config, 0, sizeof(config)); 1614 config.src_addr = port->mapbase + ofs->rdr; 1615 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1616 1617 ret = dmaengine_slave_config(stm32port->rx_ch, &config); 1618 if (ret < 0) { 1619 dev_err(dev, "rx dma channel config failed\n"); 1620 stm32_usart_of_dma_rx_remove(stm32port, pdev); 1621 return ret; 1622 } 1623 1624 return 0; 1625 } 1626 1627 static void stm32_usart_of_dma_tx_remove(struct stm32_port *stm32port, 1628 struct platform_device *pdev) 1629 { 1630 if (stm32port->tx_buf) 1631 dma_free_coherent(&pdev->dev, TX_BUF_L, stm32port->tx_buf, 1632 stm32port->tx_dma_buf); 1633 } 1634 1635 static int stm32_usart_of_dma_tx_probe(struct stm32_port *stm32port, 1636 struct platform_device *pdev) 1637 { 1638 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 1639 struct uart_port *port = &stm32port->port; 1640 struct device *dev = &pdev->dev; 1641 struct dma_slave_config config; 1642 int ret; 1643 1644 stm32port->tx_buf = dma_alloc_coherent(dev, TX_BUF_L, 1645 &stm32port->tx_dma_buf, 1646 GFP_KERNEL); 1647 if (!stm32port->tx_buf) 1648 return -ENOMEM; 1649 1650 /* Configure DMA channel */ 1651 memset(&config, 0, sizeof(config)); 1652 config.dst_addr = port->mapbase + ofs->tdr; 1653 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1654 1655 ret = dmaengine_slave_config(stm32port->tx_ch, &config); 1656 if (ret < 0) { 1657 dev_err(dev, "tx dma channel config failed\n"); 1658 stm32_usart_of_dma_tx_remove(stm32port, pdev); 1659 return ret; 1660 } 1661 1662 return 0; 1663 } 1664 1665 static int stm32_usart_serial_probe(struct platform_device *pdev) 1666 { 1667 struct stm32_port *stm32port; 1668 int ret; 1669 1670 stm32port = stm32_usart_of_get_port(pdev); 1671 if (!stm32port) 1672 return -ENODEV; 1673 1674 stm32port->info = of_device_get_match_data(&pdev->dev); 1675 if (!stm32port->info) 1676 return -EINVAL; 1677 1678 ret = stm32_usart_init_port(stm32port, pdev); 1679 if (ret) 1680 return ret; 1681 1682 if (stm32port->wakeup_src) { 1683 device_set_wakeup_capable(&pdev->dev, true); 1684 ret = dev_pm_set_wake_irq(&pdev->dev, stm32port->port.irq); 1685 if (ret) 1686 goto err_deinit_port; 1687 } 1688 1689 stm32port->rx_ch = dma_request_chan(&pdev->dev, "rx"); 1690 if (PTR_ERR(stm32port->rx_ch) == -EPROBE_DEFER) { 1691 ret = -EPROBE_DEFER; 1692 goto err_wakeirq; 1693 } 1694 /* Fall back in interrupt mode for any non-deferral error */ 1695 if (IS_ERR(stm32port->rx_ch)) 1696 stm32port->rx_ch = NULL; 1697 1698 stm32port->tx_ch = dma_request_chan(&pdev->dev, "tx"); 1699 if (PTR_ERR(stm32port->tx_ch) == -EPROBE_DEFER) { 1700 ret = -EPROBE_DEFER; 1701 goto err_dma_rx; 1702 } 1703 /* Fall back in interrupt mode for any non-deferral error */ 1704 if (IS_ERR(stm32port->tx_ch)) 1705 stm32port->tx_ch = NULL; 1706 1707 if (stm32port->rx_ch && stm32_usart_of_dma_rx_probe(stm32port, pdev)) { 1708 /* Fall back in interrupt mode */ 1709 dma_release_channel(stm32port->rx_ch); 1710 stm32port->rx_ch = NULL; 1711 } 1712 1713 if (stm32port->tx_ch && stm32_usart_of_dma_tx_probe(stm32port, pdev)) { 1714 /* Fall back in interrupt mode */ 1715 dma_release_channel(stm32port->tx_ch); 1716 stm32port->tx_ch = NULL; 1717 } 1718 1719 if (!stm32port->rx_ch) 1720 dev_info(&pdev->dev, "interrupt mode for rx (no dma)\n"); 1721 if (!stm32port->tx_ch) 1722 dev_info(&pdev->dev, "interrupt mode for tx (no dma)\n"); 1723 1724 platform_set_drvdata(pdev, &stm32port->port); 1725 1726 pm_runtime_get_noresume(&pdev->dev); 1727 pm_runtime_set_active(&pdev->dev); 1728 pm_runtime_enable(&pdev->dev); 1729 1730 ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port); 1731 if (ret) 1732 goto err_port; 1733 1734 pm_runtime_put_sync(&pdev->dev); 1735 1736 return 0; 1737 1738 err_port: 1739 pm_runtime_disable(&pdev->dev); 1740 pm_runtime_set_suspended(&pdev->dev); 1741 pm_runtime_put_noidle(&pdev->dev); 1742 1743 if (stm32port->tx_ch) { 1744 stm32_usart_of_dma_tx_remove(stm32port, pdev); 1745 dma_release_channel(stm32port->tx_ch); 1746 } 1747 1748 if (stm32port->rx_ch) 1749 stm32_usart_of_dma_rx_remove(stm32port, pdev); 1750 1751 err_dma_rx: 1752 if (stm32port->rx_ch) 1753 dma_release_channel(stm32port->rx_ch); 1754 1755 err_wakeirq: 1756 if (stm32port->wakeup_src) 1757 dev_pm_clear_wake_irq(&pdev->dev); 1758 1759 err_deinit_port: 1760 if (stm32port->wakeup_src) 1761 device_set_wakeup_capable(&pdev->dev, false); 1762 1763 stm32_usart_deinit_port(stm32port); 1764 1765 return ret; 1766 } 1767 1768 static int stm32_usart_serial_remove(struct platform_device *pdev) 1769 { 1770 struct uart_port *port = platform_get_drvdata(pdev); 1771 struct stm32_port *stm32_port = to_stm32_port(port); 1772 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1773 int err; 1774 u32 cr3; 1775 1776 pm_runtime_get_sync(&pdev->dev); 1777 err = uart_remove_one_port(&stm32_usart_driver, port); 1778 if (err) 1779 return(err); 1780 1781 pm_runtime_disable(&pdev->dev); 1782 pm_runtime_set_suspended(&pdev->dev); 1783 pm_runtime_put_noidle(&pdev->dev); 1784 1785 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_PEIE); 1786 cr3 = readl_relaxed(port->membase + ofs->cr3); 1787 cr3 &= ~USART_CR3_EIE; 1788 cr3 &= ~USART_CR3_DMAR; 1789 cr3 &= ~USART_CR3_DDRE; 1790 writel_relaxed(cr3, port->membase + ofs->cr3); 1791 1792 if (stm32_port->tx_ch) { 1793 stm32_usart_of_dma_tx_remove(stm32_port, pdev); 1794 dma_release_channel(stm32_port->tx_ch); 1795 } 1796 1797 if (stm32_port->rx_ch) { 1798 stm32_usart_of_dma_rx_remove(stm32_port, pdev); 1799 dma_release_channel(stm32_port->rx_ch); 1800 } 1801 1802 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 1803 1804 if (stm32_port->wakeup_src) { 1805 dev_pm_clear_wake_irq(&pdev->dev); 1806 device_init_wakeup(&pdev->dev, false); 1807 } 1808 1809 stm32_usart_deinit_port(stm32_port); 1810 1811 return 0; 1812 } 1813 1814 static void __maybe_unused stm32_usart_console_putchar(struct uart_port *port, unsigned char ch) 1815 { 1816 struct stm32_port *stm32_port = to_stm32_port(port); 1817 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1818 u32 isr; 1819 int ret; 1820 1821 ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, isr, 1822 (isr & USART_SR_TXE), 100, 1823 STM32_USART_TIMEOUT_USEC); 1824 if (ret != 0) { 1825 dev_err(port->dev, "Error while sending data in UART TX : %d\n", ret); 1826 return; 1827 } 1828 writel_relaxed(ch, port->membase + ofs->tdr); 1829 } 1830 1831 #ifdef CONFIG_SERIAL_STM32_CONSOLE 1832 static void stm32_usart_console_write(struct console *co, const char *s, 1833 unsigned int cnt) 1834 { 1835 struct uart_port *port = &stm32_ports[co->index].port; 1836 struct stm32_port *stm32_port = to_stm32_port(port); 1837 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1838 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 1839 unsigned long flags; 1840 u32 old_cr1, new_cr1; 1841 int locked = 1; 1842 1843 if (oops_in_progress) 1844 locked = spin_trylock_irqsave(&port->lock, flags); 1845 else 1846 spin_lock_irqsave(&port->lock, flags); 1847 1848 /* Save and disable interrupts, enable the transmitter */ 1849 old_cr1 = readl_relaxed(port->membase + ofs->cr1); 1850 new_cr1 = old_cr1 & ~USART_CR1_IE_MASK; 1851 new_cr1 |= USART_CR1_TE | BIT(cfg->uart_enable_bit); 1852 writel_relaxed(new_cr1, port->membase + ofs->cr1); 1853 1854 uart_console_write(port, s, cnt, stm32_usart_console_putchar); 1855 1856 /* Restore interrupt state */ 1857 writel_relaxed(old_cr1, port->membase + ofs->cr1); 1858 1859 if (locked) 1860 spin_unlock_irqrestore(&port->lock, flags); 1861 } 1862 1863 static int stm32_usart_console_setup(struct console *co, char *options) 1864 { 1865 struct stm32_port *stm32port; 1866 int baud = 9600; 1867 int bits = 8; 1868 int parity = 'n'; 1869 int flow = 'n'; 1870 1871 if (co->index >= STM32_MAX_PORTS) 1872 return -ENODEV; 1873 1874 stm32port = &stm32_ports[co->index]; 1875 1876 /* 1877 * This driver does not support early console initialization 1878 * (use ARM early printk support instead), so we only expect 1879 * this to be called during the uart port registration when the 1880 * driver gets probed and the port should be mapped at that point. 1881 */ 1882 if (stm32port->port.mapbase == 0 || !stm32port->port.membase) 1883 return -ENXIO; 1884 1885 if (options) 1886 uart_parse_options(options, &baud, &parity, &bits, &flow); 1887 1888 return uart_set_options(&stm32port->port, co, baud, parity, bits, flow); 1889 } 1890 1891 static struct console stm32_console = { 1892 .name = STM32_SERIAL_NAME, 1893 .device = uart_console_device, 1894 .write = stm32_usart_console_write, 1895 .setup = stm32_usart_console_setup, 1896 .flags = CON_PRINTBUFFER, 1897 .index = -1, 1898 .data = &stm32_usart_driver, 1899 }; 1900 1901 #define STM32_SERIAL_CONSOLE (&stm32_console) 1902 1903 #else 1904 #define STM32_SERIAL_CONSOLE NULL 1905 #endif /* CONFIG_SERIAL_STM32_CONSOLE */ 1906 1907 #ifdef CONFIG_SERIAL_EARLYCON 1908 static void early_stm32_usart_console_putchar(struct uart_port *port, unsigned char ch) 1909 { 1910 struct stm32_usart_info *info = port->private_data; 1911 1912 while (!(readl_relaxed(port->membase + info->ofs.isr) & USART_SR_TXE)) 1913 cpu_relax(); 1914 1915 writel_relaxed(ch, port->membase + info->ofs.tdr); 1916 } 1917 1918 static void early_stm32_serial_write(struct console *console, const char *s, unsigned int count) 1919 { 1920 struct earlycon_device *device = console->data; 1921 struct uart_port *port = &device->port; 1922 1923 uart_console_write(port, s, count, early_stm32_usart_console_putchar); 1924 } 1925 1926 static int __init early_stm32_h7_serial_setup(struct earlycon_device *device, const char *options) 1927 { 1928 if (!(device->port.membase || device->port.iobase)) 1929 return -ENODEV; 1930 device->port.private_data = &stm32h7_info; 1931 device->con->write = early_stm32_serial_write; 1932 return 0; 1933 } 1934 1935 static int __init early_stm32_f7_serial_setup(struct earlycon_device *device, const char *options) 1936 { 1937 if (!(device->port.membase || device->port.iobase)) 1938 return -ENODEV; 1939 device->port.private_data = &stm32f7_info; 1940 device->con->write = early_stm32_serial_write; 1941 return 0; 1942 } 1943 1944 static int __init early_stm32_f4_serial_setup(struct earlycon_device *device, const char *options) 1945 { 1946 if (!(device->port.membase || device->port.iobase)) 1947 return -ENODEV; 1948 device->port.private_data = &stm32f4_info; 1949 device->con->write = early_stm32_serial_write; 1950 return 0; 1951 } 1952 1953 OF_EARLYCON_DECLARE(stm32, "st,stm32h7-uart", early_stm32_h7_serial_setup); 1954 OF_EARLYCON_DECLARE(stm32, "st,stm32f7-uart", early_stm32_f7_serial_setup); 1955 OF_EARLYCON_DECLARE(stm32, "st,stm32-uart", early_stm32_f4_serial_setup); 1956 #endif /* CONFIG_SERIAL_EARLYCON */ 1957 1958 static struct uart_driver stm32_usart_driver = { 1959 .driver_name = DRIVER_NAME, 1960 .dev_name = STM32_SERIAL_NAME, 1961 .major = 0, 1962 .minor = 0, 1963 .nr = STM32_MAX_PORTS, 1964 .cons = STM32_SERIAL_CONSOLE, 1965 }; 1966 1967 static int __maybe_unused stm32_usart_serial_en_wakeup(struct uart_port *port, 1968 bool enable) 1969 { 1970 struct stm32_port *stm32_port = to_stm32_port(port); 1971 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1972 struct tty_port *tport = &port->state->port; 1973 int ret; 1974 unsigned int size; 1975 unsigned long flags; 1976 1977 if (!stm32_port->wakeup_src || !tty_port_initialized(tport)) 1978 return 0; 1979 1980 /* 1981 * Enable low-power wake-up and wake-up irq if argument is set to 1982 * "enable", disable low-power wake-up and wake-up irq otherwise 1983 */ 1984 if (enable) { 1985 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_UESM); 1986 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_WUFIE); 1987 mctrl_gpio_enable_irq_wake(stm32_port->gpios); 1988 1989 /* 1990 * When DMA is used for reception, it must be disabled before 1991 * entering low-power mode and re-enabled when exiting from 1992 * low-power mode. 1993 */ 1994 if (stm32_port->rx_ch) { 1995 spin_lock_irqsave(&port->lock, flags); 1996 /* Avoid race with RX IRQ when DMAR is cleared */ 1997 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR); 1998 /* Poll data from DMA RX buffer if any */ 1999 size = stm32_usart_receive_chars(port, true); 2000 dmaengine_terminate_async(stm32_port->rx_ch); 2001 uart_unlock_and_check_sysrq_irqrestore(port, flags); 2002 if (size) 2003 tty_flip_buffer_push(tport); 2004 } 2005 2006 /* Poll data from RX FIFO if any */ 2007 stm32_usart_receive_chars(port, false); 2008 } else { 2009 if (stm32_port->rx_ch) { 2010 ret = stm32_usart_start_rx_dma_cyclic(port); 2011 if (ret) 2012 return ret; 2013 } 2014 mctrl_gpio_disable_irq_wake(stm32_port->gpios); 2015 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_UESM); 2016 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE); 2017 } 2018 2019 return 0; 2020 } 2021 2022 static int __maybe_unused stm32_usart_serial_suspend(struct device *dev) 2023 { 2024 struct uart_port *port = dev_get_drvdata(dev); 2025 int ret; 2026 2027 uart_suspend_port(&stm32_usart_driver, port); 2028 2029 if (device_may_wakeup(dev) || device_wakeup_path(dev)) { 2030 ret = stm32_usart_serial_en_wakeup(port, true); 2031 if (ret) 2032 return ret; 2033 } 2034 2035 /* 2036 * When "no_console_suspend" is enabled, keep the pinctrl default state 2037 * and rely on bootloader stage to restore this state upon resume. 2038 * Otherwise, apply the idle or sleep states depending on wakeup 2039 * capabilities. 2040 */ 2041 if (console_suspend_enabled || !uart_console(port)) { 2042 if (device_may_wakeup(dev) || device_wakeup_path(dev)) 2043 pinctrl_pm_select_idle_state(dev); 2044 else 2045 pinctrl_pm_select_sleep_state(dev); 2046 } 2047 2048 return 0; 2049 } 2050 2051 static int __maybe_unused stm32_usart_serial_resume(struct device *dev) 2052 { 2053 struct uart_port *port = dev_get_drvdata(dev); 2054 int ret; 2055 2056 pinctrl_pm_select_default_state(dev); 2057 2058 if (device_may_wakeup(dev) || device_wakeup_path(dev)) { 2059 ret = stm32_usart_serial_en_wakeup(port, false); 2060 if (ret) 2061 return ret; 2062 } 2063 2064 return uart_resume_port(&stm32_usart_driver, port); 2065 } 2066 2067 static int __maybe_unused stm32_usart_runtime_suspend(struct device *dev) 2068 { 2069 struct uart_port *port = dev_get_drvdata(dev); 2070 struct stm32_port *stm32port = container_of(port, 2071 struct stm32_port, port); 2072 2073 clk_disable_unprepare(stm32port->clk); 2074 2075 return 0; 2076 } 2077 2078 static int __maybe_unused stm32_usart_runtime_resume(struct device *dev) 2079 { 2080 struct uart_port *port = dev_get_drvdata(dev); 2081 struct stm32_port *stm32port = container_of(port, 2082 struct stm32_port, port); 2083 2084 return clk_prepare_enable(stm32port->clk); 2085 } 2086 2087 static const struct dev_pm_ops stm32_serial_pm_ops = { 2088 SET_RUNTIME_PM_OPS(stm32_usart_runtime_suspend, 2089 stm32_usart_runtime_resume, NULL) 2090 SET_SYSTEM_SLEEP_PM_OPS(stm32_usart_serial_suspend, 2091 stm32_usart_serial_resume) 2092 }; 2093 2094 static struct platform_driver stm32_serial_driver = { 2095 .probe = stm32_usart_serial_probe, 2096 .remove = stm32_usart_serial_remove, 2097 .driver = { 2098 .name = DRIVER_NAME, 2099 .pm = &stm32_serial_pm_ops, 2100 .of_match_table = of_match_ptr(stm32_match), 2101 }, 2102 }; 2103 2104 static int __init stm32_usart_init(void) 2105 { 2106 static char banner[] __initdata = "STM32 USART driver initialized"; 2107 int ret; 2108 2109 pr_info("%s\n", banner); 2110 2111 ret = uart_register_driver(&stm32_usart_driver); 2112 if (ret) 2113 return ret; 2114 2115 ret = platform_driver_register(&stm32_serial_driver); 2116 if (ret) 2117 uart_unregister_driver(&stm32_usart_driver); 2118 2119 return ret; 2120 } 2121 2122 static void __exit stm32_usart_exit(void) 2123 { 2124 platform_driver_unregister(&stm32_serial_driver); 2125 uart_unregister_driver(&stm32_usart_driver); 2126 } 2127 2128 module_init(stm32_usart_init); 2129 module_exit(stm32_usart_exit); 2130 2131 MODULE_ALIAS("platform:" DRIVER_NAME); 2132 MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver"); 2133 MODULE_LICENSE("GPL v2"); 2134