xref: /openbmc/linux/drivers/tty/serial/stm32-usart.c (revision b8d312aa)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) Maxime Coquelin 2015
4  * Copyright (C) STMicroelectronics SA 2017
5  * Authors:  Maxime Coquelin <mcoquelin.stm32@gmail.com>
6  *	     Gerald Baeza <gerald.baeza@st.com>
7  *
8  * Inspired by st-asc.c from STMicroelectronics (c)
9  */
10 
11 #if defined(CONFIG_SERIAL_STM32_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
12 #define SUPPORT_SYSRQ
13 #endif
14 
15 #include <linux/clk.h>
16 #include <linux/console.h>
17 #include <linux/delay.h>
18 #include <linux/dma-direction.h>
19 #include <linux/dmaengine.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/io.h>
22 #include <linux/iopoll.h>
23 #include <linux/irq.h>
24 #include <linux/module.h>
25 #include <linux/of.h>
26 #include <linux/of_platform.h>
27 #include <linux/platform_device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/pm_wakeirq.h>
30 #include <linux/serial_core.h>
31 #include <linux/serial.h>
32 #include <linux/spinlock.h>
33 #include <linux/sysrq.h>
34 #include <linux/tty_flip.h>
35 #include <linux/tty.h>
36 
37 #include "stm32-usart.h"
38 
39 static void stm32_stop_tx(struct uart_port *port);
40 static void stm32_transmit_chars(struct uart_port *port);
41 
42 static inline struct stm32_port *to_stm32_port(struct uart_port *port)
43 {
44 	return container_of(port, struct stm32_port, port);
45 }
46 
47 static void stm32_set_bits(struct uart_port *port, u32 reg, u32 bits)
48 {
49 	u32 val;
50 
51 	val = readl_relaxed(port->membase + reg);
52 	val |= bits;
53 	writel_relaxed(val, port->membase + reg);
54 }
55 
56 static void stm32_clr_bits(struct uart_port *port, u32 reg, u32 bits)
57 {
58 	u32 val;
59 
60 	val = readl_relaxed(port->membase + reg);
61 	val &= ~bits;
62 	writel_relaxed(val, port->membase + reg);
63 }
64 
65 static void stm32_config_reg_rs485(u32 *cr1, u32 *cr3, u32 delay_ADE,
66 				   u32 delay_DDE, u32 baud)
67 {
68 	u32 rs485_deat_dedt;
69 	u32 rs485_deat_dedt_max = (USART_CR1_DEAT_MASK >> USART_CR1_DEAT_SHIFT);
70 	bool over8;
71 
72 	*cr3 |= USART_CR3_DEM;
73 	over8 = *cr1 & USART_CR1_OVER8;
74 
75 	if (over8)
76 		rs485_deat_dedt = delay_ADE * baud * 8;
77 	else
78 		rs485_deat_dedt = delay_ADE * baud * 16;
79 
80 	rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000);
81 	rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ?
82 			  rs485_deat_dedt_max : rs485_deat_dedt;
83 	rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEAT_SHIFT) &
84 			   USART_CR1_DEAT_MASK;
85 	*cr1 |= rs485_deat_dedt;
86 
87 	if (over8)
88 		rs485_deat_dedt = delay_DDE * baud * 8;
89 	else
90 		rs485_deat_dedt = delay_DDE * baud * 16;
91 
92 	rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000);
93 	rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ?
94 			  rs485_deat_dedt_max : rs485_deat_dedt;
95 	rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEDT_SHIFT) &
96 			   USART_CR1_DEDT_MASK;
97 	*cr1 |= rs485_deat_dedt;
98 }
99 
100 static int stm32_config_rs485(struct uart_port *port,
101 			      struct serial_rs485 *rs485conf)
102 {
103 	struct stm32_port *stm32_port = to_stm32_port(port);
104 	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
105 	struct stm32_usart_config *cfg = &stm32_port->info->cfg;
106 	u32 usartdiv, baud, cr1, cr3;
107 	bool over8;
108 
109 	stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
110 
111 	port->rs485 = *rs485conf;
112 
113 	rs485conf->flags |= SER_RS485_RX_DURING_TX;
114 
115 	if (rs485conf->flags & SER_RS485_ENABLED) {
116 		cr1 = readl_relaxed(port->membase + ofs->cr1);
117 		cr3 = readl_relaxed(port->membase + ofs->cr3);
118 		usartdiv = readl_relaxed(port->membase + ofs->brr);
119 		usartdiv = usartdiv & GENMASK(15, 0);
120 		over8 = cr1 & USART_CR1_OVER8;
121 
122 		if (over8)
123 			usartdiv = usartdiv | (usartdiv & GENMASK(4, 0))
124 				   << USART_BRR_04_R_SHIFT;
125 
126 		baud = DIV_ROUND_CLOSEST(port->uartclk, usartdiv);
127 		stm32_config_reg_rs485(&cr1, &cr3,
128 				       rs485conf->delay_rts_before_send,
129 				       rs485conf->delay_rts_after_send, baud);
130 
131 		if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
132 			cr3 &= ~USART_CR3_DEP;
133 			rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
134 		} else {
135 			cr3 |= USART_CR3_DEP;
136 			rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
137 		}
138 
139 		writel_relaxed(cr3, port->membase + ofs->cr3);
140 		writel_relaxed(cr1, port->membase + ofs->cr1);
141 	} else {
142 		stm32_clr_bits(port, ofs->cr3, USART_CR3_DEM | USART_CR3_DEP);
143 		stm32_clr_bits(port, ofs->cr1,
144 			       USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
145 	}
146 
147 	stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
148 
149 	return 0;
150 }
151 
152 static int stm32_init_rs485(struct uart_port *port,
153 			    struct platform_device *pdev)
154 {
155 	struct serial_rs485 *rs485conf = &port->rs485;
156 
157 	rs485conf->flags = 0;
158 	rs485conf->delay_rts_before_send = 0;
159 	rs485conf->delay_rts_after_send = 0;
160 
161 	if (!pdev->dev.of_node)
162 		return -ENODEV;
163 
164 	uart_get_rs485_mode(&pdev->dev, rs485conf);
165 
166 	return 0;
167 }
168 
169 static int stm32_pending_rx(struct uart_port *port, u32 *sr, int *last_res,
170 			    bool threaded)
171 {
172 	struct stm32_port *stm32_port = to_stm32_port(port);
173 	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
174 	enum dma_status status;
175 	struct dma_tx_state state;
176 
177 	*sr = readl_relaxed(port->membase + ofs->isr);
178 
179 	if (threaded && stm32_port->rx_ch) {
180 		status = dmaengine_tx_status(stm32_port->rx_ch,
181 					     stm32_port->rx_ch->cookie,
182 					     &state);
183 		if ((status == DMA_IN_PROGRESS) &&
184 		    (*last_res != state.residue))
185 			return 1;
186 		else
187 			return 0;
188 	} else if (*sr & USART_SR_RXNE) {
189 		return 1;
190 	}
191 	return 0;
192 }
193 
194 static unsigned long stm32_get_char(struct uart_port *port, u32 *sr,
195 				    int *last_res)
196 {
197 	struct stm32_port *stm32_port = to_stm32_port(port);
198 	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
199 	unsigned long c;
200 
201 	if (stm32_port->rx_ch) {
202 		c = stm32_port->rx_buf[RX_BUF_L - (*last_res)--];
203 		if ((*last_res) == 0)
204 			*last_res = RX_BUF_L;
205 	} else {
206 		c = readl_relaxed(port->membase + ofs->rdr);
207 		/* apply RDR data mask */
208 		c &= stm32_port->rdr_mask;
209 	}
210 
211 	return c;
212 }
213 
214 static void stm32_receive_chars(struct uart_port *port, bool threaded)
215 {
216 	struct tty_port *tport = &port->state->port;
217 	struct stm32_port *stm32_port = to_stm32_port(port);
218 	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
219 	unsigned long c;
220 	u32 sr;
221 	char flag;
222 
223 	if (irqd_is_wakeup_set(irq_get_irq_data(port->irq)))
224 		pm_wakeup_event(tport->tty->dev, 0);
225 
226 	while (stm32_pending_rx(port, &sr, &stm32_port->last_res, threaded)) {
227 		sr |= USART_SR_DUMMY_RX;
228 		flag = TTY_NORMAL;
229 
230 		/*
231 		 * Status bits has to be cleared before reading the RDR:
232 		 * In FIFO mode, reading the RDR will pop the next data
233 		 * (if any) along with its status bits into the SR.
234 		 * Not doing so leads to misalignement between RDR and SR,
235 		 * and clear status bits of the next rx data.
236 		 *
237 		 * Clear errors flags for stm32f7 and stm32h7 compatible
238 		 * devices. On stm32f4 compatible devices, the error bit is
239 		 * cleared by the sequence [read SR - read DR].
240 		 */
241 		if ((sr & USART_SR_ERR_MASK) && ofs->icr != UNDEF_REG)
242 			stm32_clr_bits(port, ofs->icr, USART_ICR_ORECF |
243 				       USART_ICR_PECF | USART_ICR_FECF);
244 
245 		c = stm32_get_char(port, &sr, &stm32_port->last_res);
246 		port->icount.rx++;
247 		if (sr & USART_SR_ERR_MASK) {
248 			if (sr & USART_SR_ORE) {
249 				port->icount.overrun++;
250 			} else if (sr & USART_SR_PE) {
251 				port->icount.parity++;
252 			} else if (sr & USART_SR_FE) {
253 				/* Break detection if character is null */
254 				if (!c) {
255 					port->icount.brk++;
256 					if (uart_handle_break(port))
257 						continue;
258 				} else {
259 					port->icount.frame++;
260 				}
261 			}
262 
263 			sr &= port->read_status_mask;
264 
265 			if (sr & USART_SR_PE) {
266 				flag = TTY_PARITY;
267 			} else if (sr & USART_SR_FE) {
268 				if (!c)
269 					flag = TTY_BREAK;
270 				else
271 					flag = TTY_FRAME;
272 			}
273 		}
274 
275 		if (uart_handle_sysrq_char(port, c))
276 			continue;
277 		uart_insert_char(port, sr, USART_SR_ORE, c, flag);
278 	}
279 
280 	spin_unlock(&port->lock);
281 	tty_flip_buffer_push(tport);
282 	spin_lock(&port->lock);
283 }
284 
285 static void stm32_tx_dma_complete(void *arg)
286 {
287 	struct uart_port *port = arg;
288 	struct stm32_port *stm32port = to_stm32_port(port);
289 	struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
290 
291 	stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
292 	stm32port->tx_dma_busy = false;
293 
294 	/* Let's see if we have pending data to send */
295 	stm32_transmit_chars(port);
296 }
297 
298 static void stm32_tx_interrupt_enable(struct uart_port *port)
299 {
300 	struct stm32_port *stm32_port = to_stm32_port(port);
301 	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
302 
303 	/*
304 	 * Enables TX FIFO threashold irq when FIFO is enabled,
305 	 * or TX empty irq when FIFO is disabled
306 	 */
307 	if (stm32_port->fifoen)
308 		stm32_set_bits(port, ofs->cr3, USART_CR3_TXFTIE);
309 	else
310 		stm32_set_bits(port, ofs->cr1, USART_CR1_TXEIE);
311 }
312 
313 static void stm32_tx_interrupt_disable(struct uart_port *port)
314 {
315 	struct stm32_port *stm32_port = to_stm32_port(port);
316 	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
317 
318 	if (stm32_port->fifoen)
319 		stm32_clr_bits(port, ofs->cr3, USART_CR3_TXFTIE);
320 	else
321 		stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
322 }
323 
324 static void stm32_transmit_chars_pio(struct uart_port *port)
325 {
326 	struct stm32_port *stm32_port = to_stm32_port(port);
327 	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
328 	struct circ_buf *xmit = &port->state->xmit;
329 
330 	if (stm32_port->tx_dma_busy) {
331 		stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
332 		stm32_port->tx_dma_busy = false;
333 	}
334 
335 	while (!uart_circ_empty(xmit)) {
336 		/* Check that TDR is empty before filling FIFO */
337 		if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE))
338 			break;
339 		writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr);
340 		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
341 		port->icount.tx++;
342 	}
343 
344 	/* rely on TXE irq (mask or unmask) for sending remaining data */
345 	if (uart_circ_empty(xmit))
346 		stm32_tx_interrupt_disable(port);
347 	else
348 		stm32_tx_interrupt_enable(port);
349 }
350 
351 static void stm32_transmit_chars_dma(struct uart_port *port)
352 {
353 	struct stm32_port *stm32port = to_stm32_port(port);
354 	struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
355 	struct circ_buf *xmit = &port->state->xmit;
356 	struct dma_async_tx_descriptor *desc = NULL;
357 	dma_cookie_t cookie;
358 	unsigned int count, i;
359 
360 	if (stm32port->tx_dma_busy)
361 		return;
362 
363 	stm32port->tx_dma_busy = true;
364 
365 	count = uart_circ_chars_pending(xmit);
366 
367 	if (count > TX_BUF_L)
368 		count = TX_BUF_L;
369 
370 	if (xmit->tail < xmit->head) {
371 		memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count);
372 	} else {
373 		size_t one = UART_XMIT_SIZE - xmit->tail;
374 		size_t two;
375 
376 		if (one > count)
377 			one = count;
378 		two = count - one;
379 
380 		memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one);
381 		if (two)
382 			memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two);
383 	}
384 
385 	desc = dmaengine_prep_slave_single(stm32port->tx_ch,
386 					   stm32port->tx_dma_buf,
387 					   count,
388 					   DMA_MEM_TO_DEV,
389 					   DMA_PREP_INTERRUPT);
390 
391 	if (!desc) {
392 		for (i = count; i > 0; i--)
393 			stm32_transmit_chars_pio(port);
394 		return;
395 	}
396 
397 	desc->callback = stm32_tx_dma_complete;
398 	desc->callback_param = port;
399 
400 	/* Push current DMA TX transaction in the pending queue */
401 	cookie = dmaengine_submit(desc);
402 
403 	/* Issue pending DMA TX requests */
404 	dma_async_issue_pending(stm32port->tx_ch);
405 
406 	stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT);
407 
408 	xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
409 	port->icount.tx += count;
410 }
411 
412 static void stm32_transmit_chars(struct uart_port *port)
413 {
414 	struct stm32_port *stm32_port = to_stm32_port(port);
415 	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
416 	struct circ_buf *xmit = &port->state->xmit;
417 
418 	if (port->x_char) {
419 		if (stm32_port->tx_dma_busy)
420 			stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
421 		writel_relaxed(port->x_char, port->membase + ofs->tdr);
422 		port->x_char = 0;
423 		port->icount.tx++;
424 		if (stm32_port->tx_dma_busy)
425 			stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT);
426 		return;
427 	}
428 
429 	if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
430 		stm32_tx_interrupt_disable(port);
431 		return;
432 	}
433 
434 	if (ofs->icr == UNDEF_REG)
435 		stm32_clr_bits(port, ofs->isr, USART_SR_TC);
436 	else
437 		stm32_set_bits(port, ofs->icr, USART_ICR_TCCF);
438 
439 	if (stm32_port->tx_ch)
440 		stm32_transmit_chars_dma(port);
441 	else
442 		stm32_transmit_chars_pio(port);
443 
444 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
445 		uart_write_wakeup(port);
446 
447 	if (uart_circ_empty(xmit))
448 		stm32_tx_interrupt_disable(port);
449 }
450 
451 static irqreturn_t stm32_interrupt(int irq, void *ptr)
452 {
453 	struct uart_port *port = ptr;
454 	struct stm32_port *stm32_port = to_stm32_port(port);
455 	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
456 	u32 sr;
457 
458 	spin_lock(&port->lock);
459 
460 	sr = readl_relaxed(port->membase + ofs->isr);
461 
462 	if ((sr & USART_SR_RTOF) && ofs->icr != UNDEF_REG)
463 		writel_relaxed(USART_ICR_RTOCF,
464 			       port->membase + ofs->icr);
465 
466 	if ((sr & USART_SR_WUF) && (ofs->icr != UNDEF_REG))
467 		writel_relaxed(USART_ICR_WUCF,
468 			       port->membase + ofs->icr);
469 
470 	if ((sr & USART_SR_RXNE) && !(stm32_port->rx_ch))
471 		stm32_receive_chars(port, false);
472 
473 	if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch))
474 		stm32_transmit_chars(port);
475 
476 	spin_unlock(&port->lock);
477 
478 	if (stm32_port->rx_ch)
479 		return IRQ_WAKE_THREAD;
480 	else
481 		return IRQ_HANDLED;
482 }
483 
484 static irqreturn_t stm32_threaded_interrupt(int irq, void *ptr)
485 {
486 	struct uart_port *port = ptr;
487 	struct stm32_port *stm32_port = to_stm32_port(port);
488 
489 	spin_lock(&port->lock);
490 
491 	if (stm32_port->rx_ch)
492 		stm32_receive_chars(port, true);
493 
494 	spin_unlock(&port->lock);
495 
496 	return IRQ_HANDLED;
497 }
498 
499 static unsigned int stm32_tx_empty(struct uart_port *port)
500 {
501 	struct stm32_port *stm32_port = to_stm32_port(port);
502 	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
503 
504 	return readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE;
505 }
506 
507 static void stm32_set_mctrl(struct uart_port *port, unsigned int mctrl)
508 {
509 	struct stm32_port *stm32_port = to_stm32_port(port);
510 	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
511 
512 	if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
513 		stm32_set_bits(port, ofs->cr3, USART_CR3_RTSE);
514 	else
515 		stm32_clr_bits(port, ofs->cr3, USART_CR3_RTSE);
516 }
517 
518 static unsigned int stm32_get_mctrl(struct uart_port *port)
519 {
520 	/* This routine is used to get signals of: DCD, DSR, RI, and CTS */
521 	return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
522 }
523 
524 /* Transmit stop */
525 static void stm32_stop_tx(struct uart_port *port)
526 {
527 	stm32_tx_interrupt_disable(port);
528 }
529 
530 /* There are probably characters waiting to be transmitted. */
531 static void stm32_start_tx(struct uart_port *port)
532 {
533 	struct circ_buf *xmit = &port->state->xmit;
534 
535 	if (uart_circ_empty(xmit))
536 		return;
537 
538 	stm32_transmit_chars(port);
539 }
540 
541 /* Throttle the remote when input buffer is about to overflow. */
542 static void stm32_throttle(struct uart_port *port)
543 {
544 	struct stm32_port *stm32_port = to_stm32_port(port);
545 	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
546 	unsigned long flags;
547 
548 	spin_lock_irqsave(&port->lock, flags);
549 	stm32_clr_bits(port, ofs->cr1, stm32_port->cr1_irq);
550 	if (stm32_port->cr3_irq)
551 		stm32_clr_bits(port, ofs->cr3, stm32_port->cr3_irq);
552 
553 	spin_unlock_irqrestore(&port->lock, flags);
554 }
555 
556 /* Unthrottle the remote, the input buffer can now accept data. */
557 static void stm32_unthrottle(struct uart_port *port)
558 {
559 	struct stm32_port *stm32_port = to_stm32_port(port);
560 	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
561 	unsigned long flags;
562 
563 	spin_lock_irqsave(&port->lock, flags);
564 	stm32_set_bits(port, ofs->cr1, stm32_port->cr1_irq);
565 	if (stm32_port->cr3_irq)
566 		stm32_set_bits(port, ofs->cr3, stm32_port->cr3_irq);
567 
568 	spin_unlock_irqrestore(&port->lock, flags);
569 }
570 
571 /* Receive stop */
572 static void stm32_stop_rx(struct uart_port *port)
573 {
574 	struct stm32_port *stm32_port = to_stm32_port(port);
575 	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
576 
577 	stm32_clr_bits(port, ofs->cr1, stm32_port->cr1_irq);
578 	if (stm32_port->cr3_irq)
579 		stm32_clr_bits(port, ofs->cr3, stm32_port->cr3_irq);
580 
581 }
582 
583 /* Handle breaks - ignored by us */
584 static void stm32_break_ctl(struct uart_port *port, int break_state)
585 {
586 }
587 
588 static int stm32_startup(struct uart_port *port)
589 {
590 	struct stm32_port *stm32_port = to_stm32_port(port);
591 	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
592 	const char *name = to_platform_device(port->dev)->name;
593 	u32 val;
594 	int ret;
595 
596 	ret = request_threaded_irq(port->irq, stm32_interrupt,
597 				   stm32_threaded_interrupt,
598 				   IRQF_NO_SUSPEND, name, port);
599 	if (ret)
600 		return ret;
601 
602 	/* RX FIFO Flush */
603 	if (ofs->rqr != UNDEF_REG)
604 		stm32_set_bits(port, ofs->rqr, USART_RQR_RXFRQ);
605 
606 	/* Tx and RX FIFO configuration */
607 	if (stm32_port->fifoen) {
608 		val = readl_relaxed(port->membase + ofs->cr3);
609 		val &= ~(USART_CR3_TXFTCFG_MASK | USART_CR3_RXFTCFG_MASK);
610 		val |= USART_CR3_TXFTCFG_HALF << USART_CR3_TXFTCFG_SHIFT;
611 		val |= USART_CR3_RXFTCFG_HALF << USART_CR3_RXFTCFG_SHIFT;
612 		writel_relaxed(val, port->membase + ofs->cr3);
613 	}
614 
615 	/* RX FIFO enabling */
616 	val = stm32_port->cr1_irq | USART_CR1_RE;
617 	if (stm32_port->fifoen)
618 		val |= USART_CR1_FIFOEN;
619 	stm32_set_bits(port, ofs->cr1, val);
620 
621 	return 0;
622 }
623 
624 static void stm32_shutdown(struct uart_port *port)
625 {
626 	struct stm32_port *stm32_port = to_stm32_port(port);
627 	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
628 	struct stm32_usart_config *cfg = &stm32_port->info->cfg;
629 	u32 val, isr;
630 	int ret;
631 
632 	val = USART_CR1_TXEIE | USART_CR1_TE;
633 	val |= stm32_port->cr1_irq | USART_CR1_RE;
634 	val |= BIT(cfg->uart_enable_bit);
635 	if (stm32_port->fifoen)
636 		val |= USART_CR1_FIFOEN;
637 
638 	ret = readl_relaxed_poll_timeout(port->membase + ofs->isr,
639 					 isr, (isr & USART_SR_TC),
640 					 10, 100000);
641 
642 	if (ret)
643 		dev_err(port->dev, "transmission complete not set\n");
644 
645 	stm32_clr_bits(port, ofs->cr1, val);
646 
647 	free_irq(port->irq, port);
648 }
649 
650 static unsigned int stm32_get_databits(struct ktermios *termios)
651 {
652 	unsigned int bits;
653 
654 	tcflag_t cflag = termios->c_cflag;
655 
656 	switch (cflag & CSIZE) {
657 	/*
658 	 * CSIZE settings are not necessarily supported in hardware.
659 	 * CSIZE unsupported configurations are handled here to set word length
660 	 * to 8 bits word as default configuration and to print debug message.
661 	 */
662 	case CS5:
663 		bits = 5;
664 		break;
665 	case CS6:
666 		bits = 6;
667 		break;
668 	case CS7:
669 		bits = 7;
670 		break;
671 	/* default including CS8 */
672 	default:
673 		bits = 8;
674 		break;
675 	}
676 
677 	return bits;
678 }
679 
680 static void stm32_set_termios(struct uart_port *port, struct ktermios *termios,
681 			    struct ktermios *old)
682 {
683 	struct stm32_port *stm32_port = to_stm32_port(port);
684 	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
685 	struct stm32_usart_config *cfg = &stm32_port->info->cfg;
686 	struct serial_rs485 *rs485conf = &port->rs485;
687 	unsigned int baud, bits;
688 	u32 usartdiv, mantissa, fraction, oversampling;
689 	tcflag_t cflag = termios->c_cflag;
690 	u32 cr1, cr2, cr3;
691 	unsigned long flags;
692 
693 	if (!stm32_port->hw_flow_control)
694 		cflag &= ~CRTSCTS;
695 
696 	baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8);
697 
698 	spin_lock_irqsave(&port->lock, flags);
699 
700 	/* Stop serial port and reset value */
701 	writel_relaxed(0, port->membase + ofs->cr1);
702 
703 	/* flush RX & TX FIFO */
704 	if (ofs->rqr != UNDEF_REG)
705 		stm32_set_bits(port, ofs->rqr,
706 			       USART_RQR_TXFRQ | USART_RQR_RXFRQ);
707 
708 	cr1 = USART_CR1_TE | USART_CR1_RE;
709 	if (stm32_port->fifoen)
710 		cr1 |= USART_CR1_FIFOEN;
711 	cr2 = 0;
712 	cr3 = readl_relaxed(port->membase + ofs->cr3);
713 	cr3 &= USART_CR3_TXFTIE | USART_CR3_RXFTCFG_MASK | USART_CR3_RXFTIE
714 		| USART_CR3_TXFTCFG_MASK;
715 
716 	if (cflag & CSTOPB)
717 		cr2 |= USART_CR2_STOP_2B;
718 
719 	bits = stm32_get_databits(termios);
720 	stm32_port->rdr_mask = (BIT(bits) - 1);
721 
722 	if (cflag & PARENB) {
723 		bits++;
724 		cr1 |= USART_CR1_PCE;
725 	}
726 
727 	/*
728 	 * Word length configuration:
729 	 * CS8 + parity, 9 bits word aka [M1:M0] = 0b01
730 	 * CS7 or (CS6 + parity), 7 bits word aka [M1:M0] = 0b10
731 	 * CS8 or (CS7 + parity), 8 bits word aka [M1:M0] = 0b00
732 	 * M0 and M1 already cleared by cr1 initialization.
733 	 */
734 	if (bits == 9)
735 		cr1 |= USART_CR1_M0;
736 	else if ((bits == 7) && cfg->has_7bits_data)
737 		cr1 |= USART_CR1_M1;
738 	else if (bits != 8)
739 		dev_dbg(port->dev, "Unsupported data bits config: %u bits\n"
740 			, bits);
741 
742 	if (ofs->rtor != UNDEF_REG && (stm32_port->rx_ch ||
743 				       stm32_port->fifoen)) {
744 		if (cflag & CSTOPB)
745 			bits = bits + 3; /* 1 start bit + 2 stop bits */
746 		else
747 			bits = bits + 2; /* 1 start bit + 1 stop bit */
748 
749 		/* RX timeout irq to occur after last stop bit + bits */
750 		stm32_port->cr1_irq = USART_CR1_RTOIE;
751 		writel_relaxed(bits, port->membase + ofs->rtor);
752 		cr2 |= USART_CR2_RTOEN;
753 		/* Not using dma, enable fifo threshold irq */
754 		if (!stm32_port->rx_ch)
755 			stm32_port->cr3_irq =  USART_CR3_RXFTIE;
756 	}
757 
758 	cr1 |= stm32_port->cr1_irq;
759 	cr3 |= stm32_port->cr3_irq;
760 
761 	if (cflag & PARODD)
762 		cr1 |= USART_CR1_PS;
763 
764 	port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
765 	if (cflag & CRTSCTS) {
766 		port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
767 		cr3 |= USART_CR3_CTSE | USART_CR3_RTSE;
768 	}
769 
770 	usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud);
771 
772 	/*
773 	 * The USART supports 16 or 8 times oversampling.
774 	 * By default we prefer 16 times oversampling, so that the receiver
775 	 * has a better tolerance to clock deviations.
776 	 * 8 times oversampling is only used to achieve higher speeds.
777 	 */
778 	if (usartdiv < 16) {
779 		oversampling = 8;
780 		cr1 |= USART_CR1_OVER8;
781 		stm32_set_bits(port, ofs->cr1, USART_CR1_OVER8);
782 	} else {
783 		oversampling = 16;
784 		cr1 &= ~USART_CR1_OVER8;
785 		stm32_clr_bits(port, ofs->cr1, USART_CR1_OVER8);
786 	}
787 
788 	mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT;
789 	fraction = usartdiv % oversampling;
790 	writel_relaxed(mantissa | fraction, port->membase + ofs->brr);
791 
792 	uart_update_timeout(port, cflag, baud);
793 
794 	port->read_status_mask = USART_SR_ORE;
795 	if (termios->c_iflag & INPCK)
796 		port->read_status_mask |= USART_SR_PE | USART_SR_FE;
797 	if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
798 		port->read_status_mask |= USART_SR_FE;
799 
800 	/* Characters to ignore */
801 	port->ignore_status_mask = 0;
802 	if (termios->c_iflag & IGNPAR)
803 		port->ignore_status_mask = USART_SR_PE | USART_SR_FE;
804 	if (termios->c_iflag & IGNBRK) {
805 		port->ignore_status_mask |= USART_SR_FE;
806 		/*
807 		 * If we're ignoring parity and break indicators,
808 		 * ignore overruns too (for real raw support).
809 		 */
810 		if (termios->c_iflag & IGNPAR)
811 			port->ignore_status_mask |= USART_SR_ORE;
812 	}
813 
814 	/* Ignore all characters if CREAD is not set */
815 	if ((termios->c_cflag & CREAD) == 0)
816 		port->ignore_status_mask |= USART_SR_DUMMY_RX;
817 
818 	if (stm32_port->rx_ch)
819 		cr3 |= USART_CR3_DMAR;
820 
821 	if (rs485conf->flags & SER_RS485_ENABLED) {
822 		stm32_config_reg_rs485(&cr1, &cr3,
823 				       rs485conf->delay_rts_before_send,
824 				       rs485conf->delay_rts_after_send, baud);
825 		if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
826 			cr3 &= ~USART_CR3_DEP;
827 			rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
828 		} else {
829 			cr3 |= USART_CR3_DEP;
830 			rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
831 		}
832 
833 	} else {
834 		cr3 &= ~(USART_CR3_DEM | USART_CR3_DEP);
835 		cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
836 	}
837 
838 	writel_relaxed(cr3, port->membase + ofs->cr3);
839 	writel_relaxed(cr2, port->membase + ofs->cr2);
840 	writel_relaxed(cr1, port->membase + ofs->cr1);
841 
842 	stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
843 	spin_unlock_irqrestore(&port->lock, flags);
844 }
845 
846 static const char *stm32_type(struct uart_port *port)
847 {
848 	return (port->type == PORT_STM32) ? DRIVER_NAME : NULL;
849 }
850 
851 static void stm32_release_port(struct uart_port *port)
852 {
853 }
854 
855 static int stm32_request_port(struct uart_port *port)
856 {
857 	return 0;
858 }
859 
860 static void stm32_config_port(struct uart_port *port, int flags)
861 {
862 	if (flags & UART_CONFIG_TYPE)
863 		port->type = PORT_STM32;
864 }
865 
866 static int
867 stm32_verify_port(struct uart_port *port, struct serial_struct *ser)
868 {
869 	/* No user changeable parameters */
870 	return -EINVAL;
871 }
872 
873 static void stm32_pm(struct uart_port *port, unsigned int state,
874 		unsigned int oldstate)
875 {
876 	struct stm32_port *stm32port = container_of(port,
877 			struct stm32_port, port);
878 	struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
879 	struct stm32_usart_config *cfg = &stm32port->info->cfg;
880 	unsigned long flags = 0;
881 
882 	switch (state) {
883 	case UART_PM_STATE_ON:
884 		clk_prepare_enable(stm32port->clk);
885 		break;
886 	case UART_PM_STATE_OFF:
887 		spin_lock_irqsave(&port->lock, flags);
888 		stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
889 		spin_unlock_irqrestore(&port->lock, flags);
890 		clk_disable_unprepare(stm32port->clk);
891 		break;
892 	}
893 }
894 
895 static const struct uart_ops stm32_uart_ops = {
896 	.tx_empty	= stm32_tx_empty,
897 	.set_mctrl	= stm32_set_mctrl,
898 	.get_mctrl	= stm32_get_mctrl,
899 	.stop_tx	= stm32_stop_tx,
900 	.start_tx	= stm32_start_tx,
901 	.throttle	= stm32_throttle,
902 	.unthrottle	= stm32_unthrottle,
903 	.stop_rx	= stm32_stop_rx,
904 	.break_ctl	= stm32_break_ctl,
905 	.startup	= stm32_startup,
906 	.shutdown	= stm32_shutdown,
907 	.set_termios	= stm32_set_termios,
908 	.pm		= stm32_pm,
909 	.type		= stm32_type,
910 	.release_port	= stm32_release_port,
911 	.request_port	= stm32_request_port,
912 	.config_port	= stm32_config_port,
913 	.verify_port	= stm32_verify_port,
914 };
915 
916 static int stm32_init_port(struct stm32_port *stm32port,
917 			  struct platform_device *pdev)
918 {
919 	struct uart_port *port = &stm32port->port;
920 	struct resource *res;
921 	int ret;
922 
923 	port->iotype	= UPIO_MEM;
924 	port->flags	= UPF_BOOT_AUTOCONF;
925 	port->ops	= &stm32_uart_ops;
926 	port->dev	= &pdev->dev;
927 	port->fifosize	= stm32port->info->cfg.fifosize;
928 
929 	ret = platform_get_irq(pdev, 0);
930 	if (ret <= 0) {
931 		if (ret != -EPROBE_DEFER)
932 			dev_err(&pdev->dev, "Can't get event IRQ: %d\n", ret);
933 		return ret ? ret : -ENODEV;
934 	}
935 	port->irq = ret;
936 
937 	port->rs485_config = stm32_config_rs485;
938 
939 	stm32_init_rs485(port, pdev);
940 
941 	if (stm32port->info->cfg.has_wakeup) {
942 		stm32port->wakeirq = platform_get_irq(pdev, 1);
943 		if (stm32port->wakeirq <= 0 && stm32port->wakeirq != -ENXIO) {
944 			if (stm32port->wakeirq != -EPROBE_DEFER)
945 				dev_err(&pdev->dev,
946 					"Can't get event wake IRQ: %d\n",
947 					stm32port->wakeirq);
948 			return stm32port->wakeirq ? stm32port->wakeirq :
949 				-ENODEV;
950 		}
951 	}
952 
953 	stm32port->fifoen = stm32port->info->cfg.has_fifo;
954 
955 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
956 	port->membase = devm_ioremap_resource(&pdev->dev, res);
957 	if (IS_ERR(port->membase))
958 		return PTR_ERR(port->membase);
959 	port->mapbase = res->start;
960 
961 	spin_lock_init(&port->lock);
962 
963 	stm32port->clk = devm_clk_get(&pdev->dev, NULL);
964 	if (IS_ERR(stm32port->clk))
965 		return PTR_ERR(stm32port->clk);
966 
967 	/* Ensure that clk rate is correct by enabling the clk */
968 	ret = clk_prepare_enable(stm32port->clk);
969 	if (ret)
970 		return ret;
971 
972 	stm32port->port.uartclk = clk_get_rate(stm32port->clk);
973 	if (!stm32port->port.uartclk) {
974 		clk_disable_unprepare(stm32port->clk);
975 		ret = -EINVAL;
976 	}
977 
978 	return ret;
979 }
980 
981 static struct stm32_port *stm32_of_get_stm32_port(struct platform_device *pdev)
982 {
983 	struct device_node *np = pdev->dev.of_node;
984 	int id;
985 
986 	if (!np)
987 		return NULL;
988 
989 	id = of_alias_get_id(np, "serial");
990 	if (id < 0) {
991 		dev_err(&pdev->dev, "failed to get alias id, errno %d\n", id);
992 		return NULL;
993 	}
994 
995 	if (WARN_ON(id >= STM32_MAX_PORTS))
996 		return NULL;
997 
998 	stm32_ports[id].hw_flow_control = of_property_read_bool(np,
999 							"st,hw-flow-ctrl");
1000 	stm32_ports[id].port.line = id;
1001 	stm32_ports[id].cr1_irq = USART_CR1_RXNEIE;
1002 	stm32_ports[id].cr3_irq = 0;
1003 	stm32_ports[id].last_res = RX_BUF_L;
1004 	return &stm32_ports[id];
1005 }
1006 
1007 #ifdef CONFIG_OF
1008 static const struct of_device_id stm32_match[] = {
1009 	{ .compatible = "st,stm32-uart", .data = &stm32f4_info},
1010 	{ .compatible = "st,stm32f7-uart", .data = &stm32f7_info},
1011 	{ .compatible = "st,stm32h7-uart", .data = &stm32h7_info},
1012 	{},
1013 };
1014 
1015 MODULE_DEVICE_TABLE(of, stm32_match);
1016 #endif
1017 
1018 static int stm32_of_dma_rx_probe(struct stm32_port *stm32port,
1019 				 struct platform_device *pdev)
1020 {
1021 	struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
1022 	struct uart_port *port = &stm32port->port;
1023 	struct device *dev = &pdev->dev;
1024 	struct dma_slave_config config;
1025 	struct dma_async_tx_descriptor *desc = NULL;
1026 	dma_cookie_t cookie;
1027 	int ret;
1028 
1029 	/* Request DMA RX channel */
1030 	stm32port->rx_ch = dma_request_slave_channel(dev, "rx");
1031 	if (!stm32port->rx_ch) {
1032 		dev_info(dev, "rx dma alloc failed\n");
1033 		return -ENODEV;
1034 	}
1035 	stm32port->rx_buf = dma_alloc_coherent(&pdev->dev, RX_BUF_L,
1036 						 &stm32port->rx_dma_buf,
1037 						 GFP_KERNEL);
1038 	if (!stm32port->rx_buf) {
1039 		ret = -ENOMEM;
1040 		goto alloc_err;
1041 	}
1042 
1043 	/* Configure DMA channel */
1044 	memset(&config, 0, sizeof(config));
1045 	config.src_addr = port->mapbase + ofs->rdr;
1046 	config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1047 
1048 	ret = dmaengine_slave_config(stm32port->rx_ch, &config);
1049 	if (ret < 0) {
1050 		dev_err(dev, "rx dma channel config failed\n");
1051 		ret = -ENODEV;
1052 		goto config_err;
1053 	}
1054 
1055 	/* Prepare a DMA cyclic transaction */
1056 	desc = dmaengine_prep_dma_cyclic(stm32port->rx_ch,
1057 					 stm32port->rx_dma_buf,
1058 					 RX_BUF_L, RX_BUF_P, DMA_DEV_TO_MEM,
1059 					 DMA_PREP_INTERRUPT);
1060 	if (!desc) {
1061 		dev_err(dev, "rx dma prep cyclic failed\n");
1062 		ret = -ENODEV;
1063 		goto config_err;
1064 	}
1065 
1066 	/* No callback as dma buffer is drained on usart interrupt */
1067 	desc->callback = NULL;
1068 	desc->callback_param = NULL;
1069 
1070 	/* Push current DMA transaction in the pending queue */
1071 	cookie = dmaengine_submit(desc);
1072 
1073 	/* Issue pending DMA requests */
1074 	dma_async_issue_pending(stm32port->rx_ch);
1075 
1076 	return 0;
1077 
1078 config_err:
1079 	dma_free_coherent(&pdev->dev,
1080 			  RX_BUF_L, stm32port->rx_buf,
1081 			  stm32port->rx_dma_buf);
1082 
1083 alloc_err:
1084 	dma_release_channel(stm32port->rx_ch);
1085 	stm32port->rx_ch = NULL;
1086 
1087 	return ret;
1088 }
1089 
1090 static int stm32_of_dma_tx_probe(struct stm32_port *stm32port,
1091 				 struct platform_device *pdev)
1092 {
1093 	struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
1094 	struct uart_port *port = &stm32port->port;
1095 	struct device *dev = &pdev->dev;
1096 	struct dma_slave_config config;
1097 	int ret;
1098 
1099 	stm32port->tx_dma_busy = false;
1100 
1101 	/* Request DMA TX channel */
1102 	stm32port->tx_ch = dma_request_slave_channel(dev, "tx");
1103 	if (!stm32port->tx_ch) {
1104 		dev_info(dev, "tx dma alloc failed\n");
1105 		return -ENODEV;
1106 	}
1107 	stm32port->tx_buf = dma_alloc_coherent(&pdev->dev, TX_BUF_L,
1108 						 &stm32port->tx_dma_buf,
1109 						 GFP_KERNEL);
1110 	if (!stm32port->tx_buf) {
1111 		ret = -ENOMEM;
1112 		goto alloc_err;
1113 	}
1114 
1115 	/* Configure DMA channel */
1116 	memset(&config, 0, sizeof(config));
1117 	config.dst_addr = port->mapbase + ofs->tdr;
1118 	config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1119 
1120 	ret = dmaengine_slave_config(stm32port->tx_ch, &config);
1121 	if (ret < 0) {
1122 		dev_err(dev, "tx dma channel config failed\n");
1123 		ret = -ENODEV;
1124 		goto config_err;
1125 	}
1126 
1127 	return 0;
1128 
1129 config_err:
1130 	dma_free_coherent(&pdev->dev,
1131 			  TX_BUF_L, stm32port->tx_buf,
1132 			  stm32port->tx_dma_buf);
1133 
1134 alloc_err:
1135 	dma_release_channel(stm32port->tx_ch);
1136 	stm32port->tx_ch = NULL;
1137 
1138 	return ret;
1139 }
1140 
1141 static int stm32_serial_probe(struct platform_device *pdev)
1142 {
1143 	const struct of_device_id *match;
1144 	struct stm32_port *stm32port;
1145 	int ret;
1146 
1147 	stm32port = stm32_of_get_stm32_port(pdev);
1148 	if (!stm32port)
1149 		return -ENODEV;
1150 
1151 	match = of_match_device(stm32_match, &pdev->dev);
1152 	if (match && match->data)
1153 		stm32port->info = (struct stm32_usart_info *)match->data;
1154 	else
1155 		return -EINVAL;
1156 
1157 	ret = stm32_init_port(stm32port, pdev);
1158 	if (ret)
1159 		return ret;
1160 
1161 	if (stm32port->wakeirq > 0) {
1162 		ret = device_init_wakeup(&pdev->dev, true);
1163 		if (ret)
1164 			goto err_uninit;
1165 
1166 		ret = dev_pm_set_dedicated_wake_irq(&pdev->dev,
1167 						    stm32port->wakeirq);
1168 		if (ret)
1169 			goto err_nowup;
1170 
1171 		device_set_wakeup_enable(&pdev->dev, false);
1172 	}
1173 
1174 	ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port);
1175 	if (ret)
1176 		goto err_wirq;
1177 
1178 	ret = stm32_of_dma_rx_probe(stm32port, pdev);
1179 	if (ret)
1180 		dev_info(&pdev->dev, "interrupt mode used for rx (no dma)\n");
1181 
1182 	ret = stm32_of_dma_tx_probe(stm32port, pdev);
1183 	if (ret)
1184 		dev_info(&pdev->dev, "interrupt mode used for tx (no dma)\n");
1185 
1186 	platform_set_drvdata(pdev, &stm32port->port);
1187 
1188 	return 0;
1189 
1190 err_wirq:
1191 	if (stm32port->wakeirq > 0)
1192 		dev_pm_clear_wake_irq(&pdev->dev);
1193 
1194 err_nowup:
1195 	if (stm32port->wakeirq > 0)
1196 		device_init_wakeup(&pdev->dev, false);
1197 
1198 err_uninit:
1199 	clk_disable_unprepare(stm32port->clk);
1200 
1201 	return ret;
1202 }
1203 
1204 static int stm32_serial_remove(struct platform_device *pdev)
1205 {
1206 	struct uart_port *port = platform_get_drvdata(pdev);
1207 	struct stm32_port *stm32_port = to_stm32_port(port);
1208 	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1209 
1210 	stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAR);
1211 
1212 	if (stm32_port->rx_ch)
1213 		dma_release_channel(stm32_port->rx_ch);
1214 
1215 	if (stm32_port->rx_dma_buf)
1216 		dma_free_coherent(&pdev->dev,
1217 				  RX_BUF_L, stm32_port->rx_buf,
1218 				  stm32_port->rx_dma_buf);
1219 
1220 	stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
1221 
1222 	if (stm32_port->tx_ch)
1223 		dma_release_channel(stm32_port->tx_ch);
1224 
1225 	if (stm32_port->tx_dma_buf)
1226 		dma_free_coherent(&pdev->dev,
1227 				  TX_BUF_L, stm32_port->tx_buf,
1228 				  stm32_port->tx_dma_buf);
1229 
1230 	if (stm32_port->wakeirq > 0) {
1231 		dev_pm_clear_wake_irq(&pdev->dev);
1232 		device_init_wakeup(&pdev->dev, false);
1233 	}
1234 
1235 	clk_disable_unprepare(stm32_port->clk);
1236 
1237 	return uart_remove_one_port(&stm32_usart_driver, port);
1238 }
1239 
1240 
1241 #ifdef CONFIG_SERIAL_STM32_CONSOLE
1242 static void stm32_console_putchar(struct uart_port *port, int ch)
1243 {
1244 	struct stm32_port *stm32_port = to_stm32_port(port);
1245 	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1246 
1247 	while (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE))
1248 		cpu_relax();
1249 
1250 	writel_relaxed(ch, port->membase + ofs->tdr);
1251 }
1252 
1253 static void stm32_console_write(struct console *co, const char *s, unsigned cnt)
1254 {
1255 	struct uart_port *port = &stm32_ports[co->index].port;
1256 	struct stm32_port *stm32_port = to_stm32_port(port);
1257 	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1258 	struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1259 	unsigned long flags;
1260 	u32 old_cr1, new_cr1;
1261 	int locked = 1;
1262 
1263 	local_irq_save(flags);
1264 	if (port->sysrq)
1265 		locked = 0;
1266 	else if (oops_in_progress)
1267 		locked = spin_trylock(&port->lock);
1268 	else
1269 		spin_lock(&port->lock);
1270 
1271 	/* Save and disable interrupts, enable the transmitter */
1272 	old_cr1 = readl_relaxed(port->membase + ofs->cr1);
1273 	new_cr1 = old_cr1 & ~USART_CR1_IE_MASK;
1274 	new_cr1 |=  USART_CR1_TE | BIT(cfg->uart_enable_bit);
1275 	writel_relaxed(new_cr1, port->membase + ofs->cr1);
1276 
1277 	uart_console_write(port, s, cnt, stm32_console_putchar);
1278 
1279 	/* Restore interrupt state */
1280 	writel_relaxed(old_cr1, port->membase + ofs->cr1);
1281 
1282 	if (locked)
1283 		spin_unlock(&port->lock);
1284 	local_irq_restore(flags);
1285 }
1286 
1287 static int stm32_console_setup(struct console *co, char *options)
1288 {
1289 	struct stm32_port *stm32port;
1290 	int baud = 9600;
1291 	int bits = 8;
1292 	int parity = 'n';
1293 	int flow = 'n';
1294 
1295 	if (co->index >= STM32_MAX_PORTS)
1296 		return -ENODEV;
1297 
1298 	stm32port = &stm32_ports[co->index];
1299 
1300 	/*
1301 	 * This driver does not support early console initialization
1302 	 * (use ARM early printk support instead), so we only expect
1303 	 * this to be called during the uart port registration when the
1304 	 * driver gets probed and the port should be mapped at that point.
1305 	 */
1306 	if (stm32port->port.mapbase == 0 || stm32port->port.membase == NULL)
1307 		return -ENXIO;
1308 
1309 	if (options)
1310 		uart_parse_options(options, &baud, &parity, &bits, &flow);
1311 
1312 	return uart_set_options(&stm32port->port, co, baud, parity, bits, flow);
1313 }
1314 
1315 static struct console stm32_console = {
1316 	.name		= STM32_SERIAL_NAME,
1317 	.device		= uart_console_device,
1318 	.write		= stm32_console_write,
1319 	.setup		= stm32_console_setup,
1320 	.flags		= CON_PRINTBUFFER,
1321 	.index		= -1,
1322 	.data		= &stm32_usart_driver,
1323 };
1324 
1325 #define STM32_SERIAL_CONSOLE (&stm32_console)
1326 
1327 #else
1328 #define STM32_SERIAL_CONSOLE NULL
1329 #endif /* CONFIG_SERIAL_STM32_CONSOLE */
1330 
1331 static struct uart_driver stm32_usart_driver = {
1332 	.driver_name	= DRIVER_NAME,
1333 	.dev_name	= STM32_SERIAL_NAME,
1334 	.major		= 0,
1335 	.minor		= 0,
1336 	.nr		= STM32_MAX_PORTS,
1337 	.cons		= STM32_SERIAL_CONSOLE,
1338 };
1339 
1340 #ifdef CONFIG_PM_SLEEP
1341 static void stm32_serial_enable_wakeup(struct uart_port *port, bool enable)
1342 {
1343 	struct stm32_port *stm32_port = to_stm32_port(port);
1344 	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1345 	struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1346 	u32 val;
1347 
1348 	if (stm32_port->wakeirq <= 0)
1349 		return;
1350 
1351 	if (enable) {
1352 		stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
1353 		stm32_set_bits(port, ofs->cr1, USART_CR1_UESM);
1354 		val = readl_relaxed(port->membase + ofs->cr3);
1355 		val &= ~USART_CR3_WUS_MASK;
1356 		/* Enable Wake up interrupt from low power on start bit */
1357 		val |= USART_CR3_WUS_START_BIT | USART_CR3_WUFIE;
1358 		writel_relaxed(val, port->membase + ofs->cr3);
1359 		stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
1360 	} else {
1361 		stm32_clr_bits(port, ofs->cr1, USART_CR1_UESM);
1362 	}
1363 }
1364 
1365 static int stm32_serial_suspend(struct device *dev)
1366 {
1367 	struct uart_port *port = dev_get_drvdata(dev);
1368 
1369 	uart_suspend_port(&stm32_usart_driver, port);
1370 
1371 	if (device_may_wakeup(dev))
1372 		stm32_serial_enable_wakeup(port, true);
1373 	else
1374 		stm32_serial_enable_wakeup(port, false);
1375 
1376 	return 0;
1377 }
1378 
1379 static int stm32_serial_resume(struct device *dev)
1380 {
1381 	struct uart_port *port = dev_get_drvdata(dev);
1382 
1383 	if (device_may_wakeup(dev))
1384 		stm32_serial_enable_wakeup(port, false);
1385 
1386 	return uart_resume_port(&stm32_usart_driver, port);
1387 }
1388 #endif /* CONFIG_PM_SLEEP */
1389 
1390 static const struct dev_pm_ops stm32_serial_pm_ops = {
1391 	SET_SYSTEM_SLEEP_PM_OPS(stm32_serial_suspend, stm32_serial_resume)
1392 };
1393 
1394 static struct platform_driver stm32_serial_driver = {
1395 	.probe		= stm32_serial_probe,
1396 	.remove		= stm32_serial_remove,
1397 	.driver	= {
1398 		.name	= DRIVER_NAME,
1399 		.pm	= &stm32_serial_pm_ops,
1400 		.of_match_table = of_match_ptr(stm32_match),
1401 	},
1402 };
1403 
1404 static int __init usart_init(void)
1405 {
1406 	static char banner[] __initdata = "STM32 USART driver initialized";
1407 	int ret;
1408 
1409 	pr_info("%s\n", banner);
1410 
1411 	ret = uart_register_driver(&stm32_usart_driver);
1412 	if (ret)
1413 		return ret;
1414 
1415 	ret = platform_driver_register(&stm32_serial_driver);
1416 	if (ret)
1417 		uart_unregister_driver(&stm32_usart_driver);
1418 
1419 	return ret;
1420 }
1421 
1422 static void __exit usart_exit(void)
1423 {
1424 	platform_driver_unregister(&stm32_serial_driver);
1425 	uart_unregister_driver(&stm32_usart_driver);
1426 }
1427 
1428 module_init(usart_init);
1429 module_exit(usart_exit);
1430 
1431 MODULE_ALIAS("platform:" DRIVER_NAME);
1432 MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver");
1433 MODULE_LICENSE("GPL v2");
1434