1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) Maxime Coquelin 2015 4 * Copyright (C) STMicroelectronics SA 2017 5 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com> 6 * Gerald Baeza <gerald.baeza@st.com> 7 * 8 * Inspired by st-asc.c from STMicroelectronics (c) 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/console.h> 13 #include <linux/delay.h> 14 #include <linux/dma-direction.h> 15 #include <linux/dmaengine.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/io.h> 18 #include <linux/iopoll.h> 19 #include <linux/irq.h> 20 #include <linux/module.h> 21 #include <linux/of.h> 22 #include <linux/of_platform.h> 23 #include <linux/pinctrl/consumer.h> 24 #include <linux/platform_device.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/pm_wakeirq.h> 27 #include <linux/serial_core.h> 28 #include <linux/serial.h> 29 #include <linux/spinlock.h> 30 #include <linux/sysrq.h> 31 #include <linux/tty_flip.h> 32 #include <linux/tty.h> 33 34 #include "stm32-usart.h" 35 36 static void stm32_stop_tx(struct uart_port *port); 37 static void stm32_transmit_chars(struct uart_port *port); 38 39 static inline struct stm32_port *to_stm32_port(struct uart_port *port) 40 { 41 return container_of(port, struct stm32_port, port); 42 } 43 44 static void stm32_set_bits(struct uart_port *port, u32 reg, u32 bits) 45 { 46 u32 val; 47 48 val = readl_relaxed(port->membase + reg); 49 val |= bits; 50 writel_relaxed(val, port->membase + reg); 51 } 52 53 static void stm32_clr_bits(struct uart_port *port, u32 reg, u32 bits) 54 { 55 u32 val; 56 57 val = readl_relaxed(port->membase + reg); 58 val &= ~bits; 59 writel_relaxed(val, port->membase + reg); 60 } 61 62 static void stm32_config_reg_rs485(u32 *cr1, u32 *cr3, u32 delay_ADE, 63 u32 delay_DDE, u32 baud) 64 { 65 u32 rs485_deat_dedt; 66 u32 rs485_deat_dedt_max = (USART_CR1_DEAT_MASK >> USART_CR1_DEAT_SHIFT); 67 bool over8; 68 69 *cr3 |= USART_CR3_DEM; 70 over8 = *cr1 & USART_CR1_OVER8; 71 72 if (over8) 73 rs485_deat_dedt = delay_ADE * baud * 8; 74 else 75 rs485_deat_dedt = delay_ADE * baud * 16; 76 77 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000); 78 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ? 79 rs485_deat_dedt_max : rs485_deat_dedt; 80 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEAT_SHIFT) & 81 USART_CR1_DEAT_MASK; 82 *cr1 |= rs485_deat_dedt; 83 84 if (over8) 85 rs485_deat_dedt = delay_DDE * baud * 8; 86 else 87 rs485_deat_dedt = delay_DDE * baud * 16; 88 89 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000); 90 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ? 91 rs485_deat_dedt_max : rs485_deat_dedt; 92 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEDT_SHIFT) & 93 USART_CR1_DEDT_MASK; 94 *cr1 |= rs485_deat_dedt; 95 } 96 97 static int stm32_config_rs485(struct uart_port *port, 98 struct serial_rs485 *rs485conf) 99 { 100 struct stm32_port *stm32_port = to_stm32_port(port); 101 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 102 struct stm32_usart_config *cfg = &stm32_port->info->cfg; 103 u32 usartdiv, baud, cr1, cr3; 104 bool over8; 105 106 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 107 108 port->rs485 = *rs485conf; 109 110 rs485conf->flags |= SER_RS485_RX_DURING_TX; 111 112 if (rs485conf->flags & SER_RS485_ENABLED) { 113 cr1 = readl_relaxed(port->membase + ofs->cr1); 114 cr3 = readl_relaxed(port->membase + ofs->cr3); 115 usartdiv = readl_relaxed(port->membase + ofs->brr); 116 usartdiv = usartdiv & GENMASK(15, 0); 117 over8 = cr1 & USART_CR1_OVER8; 118 119 if (over8) 120 usartdiv = usartdiv | (usartdiv & GENMASK(4, 0)) 121 << USART_BRR_04_R_SHIFT; 122 123 baud = DIV_ROUND_CLOSEST(port->uartclk, usartdiv); 124 stm32_config_reg_rs485(&cr1, &cr3, 125 rs485conf->delay_rts_before_send, 126 rs485conf->delay_rts_after_send, baud); 127 128 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 129 cr3 &= ~USART_CR3_DEP; 130 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND; 131 } else { 132 cr3 |= USART_CR3_DEP; 133 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; 134 } 135 136 writel_relaxed(cr3, port->membase + ofs->cr3); 137 writel_relaxed(cr1, port->membase + ofs->cr1); 138 } else { 139 stm32_clr_bits(port, ofs->cr3, USART_CR3_DEM | USART_CR3_DEP); 140 stm32_clr_bits(port, ofs->cr1, 141 USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK); 142 } 143 144 stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 145 146 return 0; 147 } 148 149 static int stm32_init_rs485(struct uart_port *port, 150 struct platform_device *pdev) 151 { 152 struct serial_rs485 *rs485conf = &port->rs485; 153 154 rs485conf->flags = 0; 155 rs485conf->delay_rts_before_send = 0; 156 rs485conf->delay_rts_after_send = 0; 157 158 if (!pdev->dev.of_node) 159 return -ENODEV; 160 161 uart_get_rs485_mode(&pdev->dev, rs485conf); 162 163 return 0; 164 } 165 166 static int stm32_pending_rx(struct uart_port *port, u32 *sr, int *last_res, 167 bool threaded) 168 { 169 struct stm32_port *stm32_port = to_stm32_port(port); 170 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 171 enum dma_status status; 172 struct dma_tx_state state; 173 174 *sr = readl_relaxed(port->membase + ofs->isr); 175 176 if (threaded && stm32_port->rx_ch) { 177 status = dmaengine_tx_status(stm32_port->rx_ch, 178 stm32_port->rx_ch->cookie, 179 &state); 180 if ((status == DMA_IN_PROGRESS) && 181 (*last_res != state.residue)) 182 return 1; 183 else 184 return 0; 185 } else if (*sr & USART_SR_RXNE) { 186 return 1; 187 } 188 return 0; 189 } 190 191 static unsigned long stm32_get_char(struct uart_port *port, u32 *sr, 192 int *last_res) 193 { 194 struct stm32_port *stm32_port = to_stm32_port(port); 195 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 196 unsigned long c; 197 198 if (stm32_port->rx_ch) { 199 c = stm32_port->rx_buf[RX_BUF_L - (*last_res)--]; 200 if ((*last_res) == 0) 201 *last_res = RX_BUF_L; 202 } else { 203 c = readl_relaxed(port->membase + ofs->rdr); 204 /* apply RDR data mask */ 205 c &= stm32_port->rdr_mask; 206 } 207 208 return c; 209 } 210 211 static void stm32_receive_chars(struct uart_port *port, bool threaded) 212 { 213 struct tty_port *tport = &port->state->port; 214 struct stm32_port *stm32_port = to_stm32_port(port); 215 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 216 unsigned long c; 217 u32 sr; 218 char flag; 219 220 if (irqd_is_wakeup_set(irq_get_irq_data(port->irq))) 221 pm_wakeup_event(tport->tty->dev, 0); 222 223 while (stm32_pending_rx(port, &sr, &stm32_port->last_res, threaded)) { 224 sr |= USART_SR_DUMMY_RX; 225 flag = TTY_NORMAL; 226 227 /* 228 * Status bits has to be cleared before reading the RDR: 229 * In FIFO mode, reading the RDR will pop the next data 230 * (if any) along with its status bits into the SR. 231 * Not doing so leads to misalignement between RDR and SR, 232 * and clear status bits of the next rx data. 233 * 234 * Clear errors flags for stm32f7 and stm32h7 compatible 235 * devices. On stm32f4 compatible devices, the error bit is 236 * cleared by the sequence [read SR - read DR]. 237 */ 238 if ((sr & USART_SR_ERR_MASK) && ofs->icr != UNDEF_REG) 239 writel_relaxed(sr & USART_SR_ERR_MASK, 240 port->membase + ofs->icr); 241 242 c = stm32_get_char(port, &sr, &stm32_port->last_res); 243 port->icount.rx++; 244 if (sr & USART_SR_ERR_MASK) { 245 if (sr & USART_SR_ORE) { 246 port->icount.overrun++; 247 } else if (sr & USART_SR_PE) { 248 port->icount.parity++; 249 } else if (sr & USART_SR_FE) { 250 /* Break detection if character is null */ 251 if (!c) { 252 port->icount.brk++; 253 if (uart_handle_break(port)) 254 continue; 255 } else { 256 port->icount.frame++; 257 } 258 } 259 260 sr &= port->read_status_mask; 261 262 if (sr & USART_SR_PE) { 263 flag = TTY_PARITY; 264 } else if (sr & USART_SR_FE) { 265 if (!c) 266 flag = TTY_BREAK; 267 else 268 flag = TTY_FRAME; 269 } 270 } 271 272 if (uart_handle_sysrq_char(port, c)) 273 continue; 274 uart_insert_char(port, sr, USART_SR_ORE, c, flag); 275 } 276 277 spin_unlock(&port->lock); 278 tty_flip_buffer_push(tport); 279 spin_lock(&port->lock); 280 } 281 282 static void stm32_tx_dma_complete(void *arg) 283 { 284 struct uart_port *port = arg; 285 struct stm32_port *stm32port = to_stm32_port(port); 286 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 287 288 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 289 stm32port->tx_dma_busy = false; 290 291 /* Let's see if we have pending data to send */ 292 stm32_transmit_chars(port); 293 } 294 295 static void stm32_tx_interrupt_enable(struct uart_port *port) 296 { 297 struct stm32_port *stm32_port = to_stm32_port(port); 298 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 299 300 /* 301 * Enables TX FIFO threashold irq when FIFO is enabled, 302 * or TX empty irq when FIFO is disabled 303 */ 304 if (stm32_port->fifoen) 305 stm32_set_bits(port, ofs->cr3, USART_CR3_TXFTIE); 306 else 307 stm32_set_bits(port, ofs->cr1, USART_CR1_TXEIE); 308 } 309 310 static void stm32_tx_interrupt_disable(struct uart_port *port) 311 { 312 struct stm32_port *stm32_port = to_stm32_port(port); 313 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 314 315 if (stm32_port->fifoen) 316 stm32_clr_bits(port, ofs->cr3, USART_CR3_TXFTIE); 317 else 318 stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE); 319 } 320 321 static void stm32_transmit_chars_pio(struct uart_port *port) 322 { 323 struct stm32_port *stm32_port = to_stm32_port(port); 324 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 325 struct circ_buf *xmit = &port->state->xmit; 326 327 if (stm32_port->tx_dma_busy) { 328 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 329 stm32_port->tx_dma_busy = false; 330 } 331 332 while (!uart_circ_empty(xmit)) { 333 /* Check that TDR is empty before filling FIFO */ 334 if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE)) 335 break; 336 writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr); 337 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 338 port->icount.tx++; 339 } 340 341 /* rely on TXE irq (mask or unmask) for sending remaining data */ 342 if (uart_circ_empty(xmit)) 343 stm32_tx_interrupt_disable(port); 344 else 345 stm32_tx_interrupt_enable(port); 346 } 347 348 static void stm32_transmit_chars_dma(struct uart_port *port) 349 { 350 struct stm32_port *stm32port = to_stm32_port(port); 351 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 352 struct circ_buf *xmit = &port->state->xmit; 353 struct dma_async_tx_descriptor *desc = NULL; 354 dma_cookie_t cookie; 355 unsigned int count, i; 356 357 if (stm32port->tx_dma_busy) 358 return; 359 360 stm32port->tx_dma_busy = true; 361 362 count = uart_circ_chars_pending(xmit); 363 364 if (count > TX_BUF_L) 365 count = TX_BUF_L; 366 367 if (xmit->tail < xmit->head) { 368 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count); 369 } else { 370 size_t one = UART_XMIT_SIZE - xmit->tail; 371 size_t two; 372 373 if (one > count) 374 one = count; 375 two = count - one; 376 377 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one); 378 if (two) 379 memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two); 380 } 381 382 desc = dmaengine_prep_slave_single(stm32port->tx_ch, 383 stm32port->tx_dma_buf, 384 count, 385 DMA_MEM_TO_DEV, 386 DMA_PREP_INTERRUPT); 387 388 if (!desc) { 389 for (i = count; i > 0; i--) 390 stm32_transmit_chars_pio(port); 391 return; 392 } 393 394 desc->callback = stm32_tx_dma_complete; 395 desc->callback_param = port; 396 397 /* Push current DMA TX transaction in the pending queue */ 398 cookie = dmaengine_submit(desc); 399 400 /* Issue pending DMA TX requests */ 401 dma_async_issue_pending(stm32port->tx_ch); 402 403 stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT); 404 405 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); 406 port->icount.tx += count; 407 } 408 409 static void stm32_transmit_chars(struct uart_port *port) 410 { 411 struct stm32_port *stm32_port = to_stm32_port(port); 412 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 413 struct circ_buf *xmit = &port->state->xmit; 414 415 if (port->x_char) { 416 if (stm32_port->tx_dma_busy) 417 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 418 writel_relaxed(port->x_char, port->membase + ofs->tdr); 419 port->x_char = 0; 420 port->icount.tx++; 421 if (stm32_port->tx_dma_busy) 422 stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT); 423 return; 424 } 425 426 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 427 stm32_tx_interrupt_disable(port); 428 return; 429 } 430 431 if (ofs->icr == UNDEF_REG) 432 stm32_clr_bits(port, ofs->isr, USART_SR_TC); 433 else 434 writel_relaxed(USART_ICR_TCCF, port->membase + ofs->icr); 435 436 if (stm32_port->tx_ch) 437 stm32_transmit_chars_dma(port); 438 else 439 stm32_transmit_chars_pio(port); 440 441 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 442 uart_write_wakeup(port); 443 444 if (uart_circ_empty(xmit)) 445 stm32_tx_interrupt_disable(port); 446 } 447 448 static irqreturn_t stm32_interrupt(int irq, void *ptr) 449 { 450 struct uart_port *port = ptr; 451 struct stm32_port *stm32_port = to_stm32_port(port); 452 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 453 u32 sr; 454 455 spin_lock(&port->lock); 456 457 sr = readl_relaxed(port->membase + ofs->isr); 458 459 if ((sr & USART_SR_RTOF) && ofs->icr != UNDEF_REG) 460 writel_relaxed(USART_ICR_RTOCF, 461 port->membase + ofs->icr); 462 463 if ((sr & USART_SR_WUF) && (ofs->icr != UNDEF_REG)) 464 writel_relaxed(USART_ICR_WUCF, 465 port->membase + ofs->icr); 466 467 if ((sr & USART_SR_RXNE) && !(stm32_port->rx_ch)) 468 stm32_receive_chars(port, false); 469 470 if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch)) 471 stm32_transmit_chars(port); 472 473 spin_unlock(&port->lock); 474 475 if (stm32_port->rx_ch) 476 return IRQ_WAKE_THREAD; 477 else 478 return IRQ_HANDLED; 479 } 480 481 static irqreturn_t stm32_threaded_interrupt(int irq, void *ptr) 482 { 483 struct uart_port *port = ptr; 484 struct stm32_port *stm32_port = to_stm32_port(port); 485 486 spin_lock(&port->lock); 487 488 if (stm32_port->rx_ch) 489 stm32_receive_chars(port, true); 490 491 spin_unlock(&port->lock); 492 493 return IRQ_HANDLED; 494 } 495 496 static unsigned int stm32_tx_empty(struct uart_port *port) 497 { 498 struct stm32_port *stm32_port = to_stm32_port(port); 499 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 500 501 return readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE; 502 } 503 504 static void stm32_set_mctrl(struct uart_port *port, unsigned int mctrl) 505 { 506 struct stm32_port *stm32_port = to_stm32_port(port); 507 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 508 509 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) 510 stm32_set_bits(port, ofs->cr3, USART_CR3_RTSE); 511 else 512 stm32_clr_bits(port, ofs->cr3, USART_CR3_RTSE); 513 } 514 515 static unsigned int stm32_get_mctrl(struct uart_port *port) 516 { 517 /* This routine is used to get signals of: DCD, DSR, RI, and CTS */ 518 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; 519 } 520 521 /* Transmit stop */ 522 static void stm32_stop_tx(struct uart_port *port) 523 { 524 stm32_tx_interrupt_disable(port); 525 } 526 527 /* There are probably characters waiting to be transmitted. */ 528 static void stm32_start_tx(struct uart_port *port) 529 { 530 struct circ_buf *xmit = &port->state->xmit; 531 532 if (uart_circ_empty(xmit)) 533 return; 534 535 stm32_transmit_chars(port); 536 } 537 538 /* Throttle the remote when input buffer is about to overflow. */ 539 static void stm32_throttle(struct uart_port *port) 540 { 541 struct stm32_port *stm32_port = to_stm32_port(port); 542 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 543 unsigned long flags; 544 545 spin_lock_irqsave(&port->lock, flags); 546 stm32_clr_bits(port, ofs->cr1, stm32_port->cr1_irq); 547 if (stm32_port->cr3_irq) 548 stm32_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); 549 550 spin_unlock_irqrestore(&port->lock, flags); 551 } 552 553 /* Unthrottle the remote, the input buffer can now accept data. */ 554 static void stm32_unthrottle(struct uart_port *port) 555 { 556 struct stm32_port *stm32_port = to_stm32_port(port); 557 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 558 unsigned long flags; 559 560 spin_lock_irqsave(&port->lock, flags); 561 stm32_set_bits(port, ofs->cr1, stm32_port->cr1_irq); 562 if (stm32_port->cr3_irq) 563 stm32_set_bits(port, ofs->cr3, stm32_port->cr3_irq); 564 565 spin_unlock_irqrestore(&port->lock, flags); 566 } 567 568 /* Receive stop */ 569 static void stm32_stop_rx(struct uart_port *port) 570 { 571 struct stm32_port *stm32_port = to_stm32_port(port); 572 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 573 574 stm32_clr_bits(port, ofs->cr1, stm32_port->cr1_irq); 575 if (stm32_port->cr3_irq) 576 stm32_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); 577 578 } 579 580 /* Handle breaks - ignored by us */ 581 static void stm32_break_ctl(struct uart_port *port, int break_state) 582 { 583 } 584 585 static int stm32_startup(struct uart_port *port) 586 { 587 struct stm32_port *stm32_port = to_stm32_port(port); 588 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 589 const char *name = to_platform_device(port->dev)->name; 590 u32 val; 591 int ret; 592 593 ret = request_threaded_irq(port->irq, stm32_interrupt, 594 stm32_threaded_interrupt, 595 IRQF_NO_SUSPEND, name, port); 596 if (ret) 597 return ret; 598 599 /* RX FIFO Flush */ 600 if (ofs->rqr != UNDEF_REG) 601 stm32_set_bits(port, ofs->rqr, USART_RQR_RXFRQ); 602 603 /* Tx and RX FIFO configuration */ 604 if (stm32_port->fifoen) { 605 val = readl_relaxed(port->membase + ofs->cr3); 606 val &= ~(USART_CR3_TXFTCFG_MASK | USART_CR3_RXFTCFG_MASK); 607 val |= USART_CR3_TXFTCFG_HALF << USART_CR3_TXFTCFG_SHIFT; 608 val |= USART_CR3_RXFTCFG_HALF << USART_CR3_RXFTCFG_SHIFT; 609 writel_relaxed(val, port->membase + ofs->cr3); 610 } 611 612 /* RX FIFO enabling */ 613 val = stm32_port->cr1_irq | USART_CR1_RE; 614 if (stm32_port->fifoen) 615 val |= USART_CR1_FIFOEN; 616 stm32_set_bits(port, ofs->cr1, val); 617 618 return 0; 619 } 620 621 static void stm32_shutdown(struct uart_port *port) 622 { 623 struct stm32_port *stm32_port = to_stm32_port(port); 624 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 625 struct stm32_usart_config *cfg = &stm32_port->info->cfg; 626 u32 val, isr; 627 int ret; 628 629 val = USART_CR1_TXEIE | USART_CR1_TE; 630 val |= stm32_port->cr1_irq | USART_CR1_RE; 631 val |= BIT(cfg->uart_enable_bit); 632 if (stm32_port->fifoen) 633 val |= USART_CR1_FIFOEN; 634 635 ret = readl_relaxed_poll_timeout(port->membase + ofs->isr, 636 isr, (isr & USART_SR_TC), 637 10, 100000); 638 639 if (ret) 640 dev_err(port->dev, "transmission complete not set\n"); 641 642 stm32_clr_bits(port, ofs->cr1, val); 643 644 free_irq(port->irq, port); 645 } 646 647 static unsigned int stm32_get_databits(struct ktermios *termios) 648 { 649 unsigned int bits; 650 651 tcflag_t cflag = termios->c_cflag; 652 653 switch (cflag & CSIZE) { 654 /* 655 * CSIZE settings are not necessarily supported in hardware. 656 * CSIZE unsupported configurations are handled here to set word length 657 * to 8 bits word as default configuration and to print debug message. 658 */ 659 case CS5: 660 bits = 5; 661 break; 662 case CS6: 663 bits = 6; 664 break; 665 case CS7: 666 bits = 7; 667 break; 668 /* default including CS8 */ 669 default: 670 bits = 8; 671 break; 672 } 673 674 return bits; 675 } 676 677 static void stm32_set_termios(struct uart_port *port, struct ktermios *termios, 678 struct ktermios *old) 679 { 680 struct stm32_port *stm32_port = to_stm32_port(port); 681 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 682 struct stm32_usart_config *cfg = &stm32_port->info->cfg; 683 struct serial_rs485 *rs485conf = &port->rs485; 684 unsigned int baud, bits; 685 u32 usartdiv, mantissa, fraction, oversampling; 686 tcflag_t cflag = termios->c_cflag; 687 u32 cr1, cr2, cr3; 688 unsigned long flags; 689 690 if (!stm32_port->hw_flow_control) 691 cflag &= ~CRTSCTS; 692 693 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8); 694 695 spin_lock_irqsave(&port->lock, flags); 696 697 /* Stop serial port and reset value */ 698 writel_relaxed(0, port->membase + ofs->cr1); 699 700 /* flush RX & TX FIFO */ 701 if (ofs->rqr != UNDEF_REG) 702 stm32_set_bits(port, ofs->rqr, 703 USART_RQR_TXFRQ | USART_RQR_RXFRQ); 704 705 cr1 = USART_CR1_TE | USART_CR1_RE; 706 if (stm32_port->fifoen) 707 cr1 |= USART_CR1_FIFOEN; 708 cr2 = 0; 709 cr3 = readl_relaxed(port->membase + ofs->cr3); 710 cr3 &= USART_CR3_TXFTIE | USART_CR3_RXFTCFG_MASK | USART_CR3_RXFTIE 711 | USART_CR3_TXFTCFG_MASK; 712 713 if (cflag & CSTOPB) 714 cr2 |= USART_CR2_STOP_2B; 715 716 bits = stm32_get_databits(termios); 717 stm32_port->rdr_mask = (BIT(bits) - 1); 718 719 if (cflag & PARENB) { 720 bits++; 721 cr1 |= USART_CR1_PCE; 722 } 723 724 /* 725 * Word length configuration: 726 * CS8 + parity, 9 bits word aka [M1:M0] = 0b01 727 * CS7 or (CS6 + parity), 7 bits word aka [M1:M0] = 0b10 728 * CS8 or (CS7 + parity), 8 bits word aka [M1:M0] = 0b00 729 * M0 and M1 already cleared by cr1 initialization. 730 */ 731 if (bits == 9) 732 cr1 |= USART_CR1_M0; 733 else if ((bits == 7) && cfg->has_7bits_data) 734 cr1 |= USART_CR1_M1; 735 else if (bits != 8) 736 dev_dbg(port->dev, "Unsupported data bits config: %u bits\n" 737 , bits); 738 739 if (ofs->rtor != UNDEF_REG && (stm32_port->rx_ch || 740 stm32_port->fifoen)) { 741 if (cflag & CSTOPB) 742 bits = bits + 3; /* 1 start bit + 2 stop bits */ 743 else 744 bits = bits + 2; /* 1 start bit + 1 stop bit */ 745 746 /* RX timeout irq to occur after last stop bit + bits */ 747 stm32_port->cr1_irq = USART_CR1_RTOIE; 748 writel_relaxed(bits, port->membase + ofs->rtor); 749 cr2 |= USART_CR2_RTOEN; 750 /* Not using dma, enable fifo threshold irq */ 751 if (!stm32_port->rx_ch) 752 stm32_port->cr3_irq = USART_CR3_RXFTIE; 753 } 754 755 cr1 |= stm32_port->cr1_irq; 756 cr3 |= stm32_port->cr3_irq; 757 758 if (cflag & PARODD) 759 cr1 |= USART_CR1_PS; 760 761 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); 762 if (cflag & CRTSCTS) { 763 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 764 cr3 |= USART_CR3_CTSE | USART_CR3_RTSE; 765 } 766 767 usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud); 768 769 /* 770 * The USART supports 16 or 8 times oversampling. 771 * By default we prefer 16 times oversampling, so that the receiver 772 * has a better tolerance to clock deviations. 773 * 8 times oversampling is only used to achieve higher speeds. 774 */ 775 if (usartdiv < 16) { 776 oversampling = 8; 777 cr1 |= USART_CR1_OVER8; 778 stm32_set_bits(port, ofs->cr1, USART_CR1_OVER8); 779 } else { 780 oversampling = 16; 781 cr1 &= ~USART_CR1_OVER8; 782 stm32_clr_bits(port, ofs->cr1, USART_CR1_OVER8); 783 } 784 785 mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT; 786 fraction = usartdiv % oversampling; 787 writel_relaxed(mantissa | fraction, port->membase + ofs->brr); 788 789 uart_update_timeout(port, cflag, baud); 790 791 port->read_status_mask = USART_SR_ORE; 792 if (termios->c_iflag & INPCK) 793 port->read_status_mask |= USART_SR_PE | USART_SR_FE; 794 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 795 port->read_status_mask |= USART_SR_FE; 796 797 /* Characters to ignore */ 798 port->ignore_status_mask = 0; 799 if (termios->c_iflag & IGNPAR) 800 port->ignore_status_mask = USART_SR_PE | USART_SR_FE; 801 if (termios->c_iflag & IGNBRK) { 802 port->ignore_status_mask |= USART_SR_FE; 803 /* 804 * If we're ignoring parity and break indicators, 805 * ignore overruns too (for real raw support). 806 */ 807 if (termios->c_iflag & IGNPAR) 808 port->ignore_status_mask |= USART_SR_ORE; 809 } 810 811 /* Ignore all characters if CREAD is not set */ 812 if ((termios->c_cflag & CREAD) == 0) 813 port->ignore_status_mask |= USART_SR_DUMMY_RX; 814 815 if (stm32_port->rx_ch) 816 cr3 |= USART_CR3_DMAR; 817 818 if (rs485conf->flags & SER_RS485_ENABLED) { 819 stm32_config_reg_rs485(&cr1, &cr3, 820 rs485conf->delay_rts_before_send, 821 rs485conf->delay_rts_after_send, baud); 822 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 823 cr3 &= ~USART_CR3_DEP; 824 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND; 825 } else { 826 cr3 |= USART_CR3_DEP; 827 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; 828 } 829 830 } else { 831 cr3 &= ~(USART_CR3_DEM | USART_CR3_DEP); 832 cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK); 833 } 834 835 writel_relaxed(cr3, port->membase + ofs->cr3); 836 writel_relaxed(cr2, port->membase + ofs->cr2); 837 writel_relaxed(cr1, port->membase + ofs->cr1); 838 839 stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 840 spin_unlock_irqrestore(&port->lock, flags); 841 } 842 843 static const char *stm32_type(struct uart_port *port) 844 { 845 return (port->type == PORT_STM32) ? DRIVER_NAME : NULL; 846 } 847 848 static void stm32_release_port(struct uart_port *port) 849 { 850 } 851 852 static int stm32_request_port(struct uart_port *port) 853 { 854 return 0; 855 } 856 857 static void stm32_config_port(struct uart_port *port, int flags) 858 { 859 if (flags & UART_CONFIG_TYPE) 860 port->type = PORT_STM32; 861 } 862 863 static int 864 stm32_verify_port(struct uart_port *port, struct serial_struct *ser) 865 { 866 /* No user changeable parameters */ 867 return -EINVAL; 868 } 869 870 static void stm32_pm(struct uart_port *port, unsigned int state, 871 unsigned int oldstate) 872 { 873 struct stm32_port *stm32port = container_of(port, 874 struct stm32_port, port); 875 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 876 struct stm32_usart_config *cfg = &stm32port->info->cfg; 877 unsigned long flags = 0; 878 879 switch (state) { 880 case UART_PM_STATE_ON: 881 pm_runtime_get_sync(port->dev); 882 break; 883 case UART_PM_STATE_OFF: 884 spin_lock_irqsave(&port->lock, flags); 885 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 886 spin_unlock_irqrestore(&port->lock, flags); 887 pm_runtime_put_sync(port->dev); 888 break; 889 } 890 } 891 892 static const struct uart_ops stm32_uart_ops = { 893 .tx_empty = stm32_tx_empty, 894 .set_mctrl = stm32_set_mctrl, 895 .get_mctrl = stm32_get_mctrl, 896 .stop_tx = stm32_stop_tx, 897 .start_tx = stm32_start_tx, 898 .throttle = stm32_throttle, 899 .unthrottle = stm32_unthrottle, 900 .stop_rx = stm32_stop_rx, 901 .break_ctl = stm32_break_ctl, 902 .startup = stm32_startup, 903 .shutdown = stm32_shutdown, 904 .set_termios = stm32_set_termios, 905 .pm = stm32_pm, 906 .type = stm32_type, 907 .release_port = stm32_release_port, 908 .request_port = stm32_request_port, 909 .config_port = stm32_config_port, 910 .verify_port = stm32_verify_port, 911 }; 912 913 static int stm32_init_port(struct stm32_port *stm32port, 914 struct platform_device *pdev) 915 { 916 struct uart_port *port = &stm32port->port; 917 struct resource *res; 918 int ret; 919 920 port->iotype = UPIO_MEM; 921 port->flags = UPF_BOOT_AUTOCONF; 922 port->ops = &stm32_uart_ops; 923 port->dev = &pdev->dev; 924 port->fifosize = stm32port->info->cfg.fifosize; 925 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_STM32_CONSOLE); 926 927 ret = platform_get_irq(pdev, 0); 928 if (ret <= 0) 929 return ret ? : -ENODEV; 930 port->irq = ret; 931 932 port->rs485_config = stm32_config_rs485; 933 934 stm32_init_rs485(port, pdev); 935 936 if (stm32port->info->cfg.has_wakeup) { 937 stm32port->wakeirq = platform_get_irq(pdev, 1); 938 if (stm32port->wakeirq <= 0 && stm32port->wakeirq != -ENXIO) 939 return stm32port->wakeirq ? : -ENODEV; 940 } 941 942 stm32port->fifoen = stm32port->info->cfg.has_fifo; 943 944 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 945 port->membase = devm_ioremap_resource(&pdev->dev, res); 946 if (IS_ERR(port->membase)) 947 return PTR_ERR(port->membase); 948 port->mapbase = res->start; 949 950 spin_lock_init(&port->lock); 951 952 stm32port->clk = devm_clk_get(&pdev->dev, NULL); 953 if (IS_ERR(stm32port->clk)) 954 return PTR_ERR(stm32port->clk); 955 956 /* Ensure that clk rate is correct by enabling the clk */ 957 ret = clk_prepare_enable(stm32port->clk); 958 if (ret) 959 return ret; 960 961 stm32port->port.uartclk = clk_get_rate(stm32port->clk); 962 if (!stm32port->port.uartclk) { 963 clk_disable_unprepare(stm32port->clk); 964 ret = -EINVAL; 965 } 966 967 return ret; 968 } 969 970 static struct stm32_port *stm32_of_get_stm32_port(struct platform_device *pdev) 971 { 972 struct device_node *np = pdev->dev.of_node; 973 int id; 974 975 if (!np) 976 return NULL; 977 978 id = of_alias_get_id(np, "serial"); 979 if (id < 0) { 980 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", id); 981 return NULL; 982 } 983 984 if (WARN_ON(id >= STM32_MAX_PORTS)) 985 return NULL; 986 987 stm32_ports[id].hw_flow_control = of_property_read_bool(np, 988 "st,hw-flow-ctrl"); 989 stm32_ports[id].port.line = id; 990 stm32_ports[id].cr1_irq = USART_CR1_RXNEIE; 991 stm32_ports[id].cr3_irq = 0; 992 stm32_ports[id].last_res = RX_BUF_L; 993 return &stm32_ports[id]; 994 } 995 996 #ifdef CONFIG_OF 997 static const struct of_device_id stm32_match[] = { 998 { .compatible = "st,stm32-uart", .data = &stm32f4_info}, 999 { .compatible = "st,stm32f7-uart", .data = &stm32f7_info}, 1000 { .compatible = "st,stm32h7-uart", .data = &stm32h7_info}, 1001 {}, 1002 }; 1003 1004 MODULE_DEVICE_TABLE(of, stm32_match); 1005 #endif 1006 1007 static int stm32_of_dma_rx_probe(struct stm32_port *stm32port, 1008 struct platform_device *pdev) 1009 { 1010 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 1011 struct uart_port *port = &stm32port->port; 1012 struct device *dev = &pdev->dev; 1013 struct dma_slave_config config; 1014 struct dma_async_tx_descriptor *desc = NULL; 1015 dma_cookie_t cookie; 1016 int ret; 1017 1018 /* Request DMA RX channel */ 1019 stm32port->rx_ch = dma_request_slave_channel(dev, "rx"); 1020 if (!stm32port->rx_ch) { 1021 dev_info(dev, "rx dma alloc failed\n"); 1022 return -ENODEV; 1023 } 1024 stm32port->rx_buf = dma_alloc_coherent(&pdev->dev, RX_BUF_L, 1025 &stm32port->rx_dma_buf, 1026 GFP_KERNEL); 1027 if (!stm32port->rx_buf) { 1028 ret = -ENOMEM; 1029 goto alloc_err; 1030 } 1031 1032 /* Configure DMA channel */ 1033 memset(&config, 0, sizeof(config)); 1034 config.src_addr = port->mapbase + ofs->rdr; 1035 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1036 1037 ret = dmaengine_slave_config(stm32port->rx_ch, &config); 1038 if (ret < 0) { 1039 dev_err(dev, "rx dma channel config failed\n"); 1040 ret = -ENODEV; 1041 goto config_err; 1042 } 1043 1044 /* Prepare a DMA cyclic transaction */ 1045 desc = dmaengine_prep_dma_cyclic(stm32port->rx_ch, 1046 stm32port->rx_dma_buf, 1047 RX_BUF_L, RX_BUF_P, DMA_DEV_TO_MEM, 1048 DMA_PREP_INTERRUPT); 1049 if (!desc) { 1050 dev_err(dev, "rx dma prep cyclic failed\n"); 1051 ret = -ENODEV; 1052 goto config_err; 1053 } 1054 1055 /* No callback as dma buffer is drained on usart interrupt */ 1056 desc->callback = NULL; 1057 desc->callback_param = NULL; 1058 1059 /* Push current DMA transaction in the pending queue */ 1060 cookie = dmaengine_submit(desc); 1061 1062 /* Issue pending DMA requests */ 1063 dma_async_issue_pending(stm32port->rx_ch); 1064 1065 return 0; 1066 1067 config_err: 1068 dma_free_coherent(&pdev->dev, 1069 RX_BUF_L, stm32port->rx_buf, 1070 stm32port->rx_dma_buf); 1071 1072 alloc_err: 1073 dma_release_channel(stm32port->rx_ch); 1074 stm32port->rx_ch = NULL; 1075 1076 return ret; 1077 } 1078 1079 static int stm32_of_dma_tx_probe(struct stm32_port *stm32port, 1080 struct platform_device *pdev) 1081 { 1082 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 1083 struct uart_port *port = &stm32port->port; 1084 struct device *dev = &pdev->dev; 1085 struct dma_slave_config config; 1086 int ret; 1087 1088 stm32port->tx_dma_busy = false; 1089 1090 /* Request DMA TX channel */ 1091 stm32port->tx_ch = dma_request_slave_channel(dev, "tx"); 1092 if (!stm32port->tx_ch) { 1093 dev_info(dev, "tx dma alloc failed\n"); 1094 return -ENODEV; 1095 } 1096 stm32port->tx_buf = dma_alloc_coherent(&pdev->dev, TX_BUF_L, 1097 &stm32port->tx_dma_buf, 1098 GFP_KERNEL); 1099 if (!stm32port->tx_buf) { 1100 ret = -ENOMEM; 1101 goto alloc_err; 1102 } 1103 1104 /* Configure DMA channel */ 1105 memset(&config, 0, sizeof(config)); 1106 config.dst_addr = port->mapbase + ofs->tdr; 1107 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1108 1109 ret = dmaengine_slave_config(stm32port->tx_ch, &config); 1110 if (ret < 0) { 1111 dev_err(dev, "tx dma channel config failed\n"); 1112 ret = -ENODEV; 1113 goto config_err; 1114 } 1115 1116 return 0; 1117 1118 config_err: 1119 dma_free_coherent(&pdev->dev, 1120 TX_BUF_L, stm32port->tx_buf, 1121 stm32port->tx_dma_buf); 1122 1123 alloc_err: 1124 dma_release_channel(stm32port->tx_ch); 1125 stm32port->tx_ch = NULL; 1126 1127 return ret; 1128 } 1129 1130 static int stm32_serial_probe(struct platform_device *pdev) 1131 { 1132 const struct of_device_id *match; 1133 struct stm32_port *stm32port; 1134 int ret; 1135 1136 stm32port = stm32_of_get_stm32_port(pdev); 1137 if (!stm32port) 1138 return -ENODEV; 1139 1140 match = of_match_device(stm32_match, &pdev->dev); 1141 if (match && match->data) 1142 stm32port->info = (struct stm32_usart_info *)match->data; 1143 else 1144 return -EINVAL; 1145 1146 ret = stm32_init_port(stm32port, pdev); 1147 if (ret) 1148 return ret; 1149 1150 if (stm32port->wakeirq > 0) { 1151 ret = device_init_wakeup(&pdev->dev, true); 1152 if (ret) 1153 goto err_uninit; 1154 1155 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev, 1156 stm32port->wakeirq); 1157 if (ret) 1158 goto err_nowup; 1159 1160 device_set_wakeup_enable(&pdev->dev, false); 1161 } 1162 1163 ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port); 1164 if (ret) 1165 goto err_wirq; 1166 1167 ret = stm32_of_dma_rx_probe(stm32port, pdev); 1168 if (ret) 1169 dev_info(&pdev->dev, "interrupt mode used for rx (no dma)\n"); 1170 1171 ret = stm32_of_dma_tx_probe(stm32port, pdev); 1172 if (ret) 1173 dev_info(&pdev->dev, "interrupt mode used for tx (no dma)\n"); 1174 1175 platform_set_drvdata(pdev, &stm32port->port); 1176 1177 pm_runtime_get_noresume(&pdev->dev); 1178 pm_runtime_set_active(&pdev->dev); 1179 pm_runtime_enable(&pdev->dev); 1180 pm_runtime_put_sync(&pdev->dev); 1181 1182 return 0; 1183 1184 err_wirq: 1185 if (stm32port->wakeirq > 0) 1186 dev_pm_clear_wake_irq(&pdev->dev); 1187 1188 err_nowup: 1189 if (stm32port->wakeirq > 0) 1190 device_init_wakeup(&pdev->dev, false); 1191 1192 err_uninit: 1193 clk_disable_unprepare(stm32port->clk); 1194 1195 return ret; 1196 } 1197 1198 static int stm32_serial_remove(struct platform_device *pdev) 1199 { 1200 struct uart_port *port = platform_get_drvdata(pdev); 1201 struct stm32_port *stm32_port = to_stm32_port(port); 1202 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1203 int err; 1204 1205 pm_runtime_get_sync(&pdev->dev); 1206 1207 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAR); 1208 1209 if (stm32_port->rx_ch) 1210 dma_release_channel(stm32_port->rx_ch); 1211 1212 if (stm32_port->rx_dma_buf) 1213 dma_free_coherent(&pdev->dev, 1214 RX_BUF_L, stm32_port->rx_buf, 1215 stm32_port->rx_dma_buf); 1216 1217 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 1218 1219 if (stm32_port->tx_ch) 1220 dma_release_channel(stm32_port->tx_ch); 1221 1222 if (stm32_port->tx_dma_buf) 1223 dma_free_coherent(&pdev->dev, 1224 TX_BUF_L, stm32_port->tx_buf, 1225 stm32_port->tx_dma_buf); 1226 1227 if (stm32_port->wakeirq > 0) { 1228 dev_pm_clear_wake_irq(&pdev->dev); 1229 device_init_wakeup(&pdev->dev, false); 1230 } 1231 1232 clk_disable_unprepare(stm32_port->clk); 1233 1234 err = uart_remove_one_port(&stm32_usart_driver, port); 1235 1236 pm_runtime_disable(&pdev->dev); 1237 pm_runtime_put_noidle(&pdev->dev); 1238 1239 return err; 1240 } 1241 1242 1243 #ifdef CONFIG_SERIAL_STM32_CONSOLE 1244 static void stm32_console_putchar(struct uart_port *port, int ch) 1245 { 1246 struct stm32_port *stm32_port = to_stm32_port(port); 1247 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1248 1249 while (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE)) 1250 cpu_relax(); 1251 1252 writel_relaxed(ch, port->membase + ofs->tdr); 1253 } 1254 1255 static void stm32_console_write(struct console *co, const char *s, unsigned cnt) 1256 { 1257 struct uart_port *port = &stm32_ports[co->index].port; 1258 struct stm32_port *stm32_port = to_stm32_port(port); 1259 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1260 struct stm32_usart_config *cfg = &stm32_port->info->cfg; 1261 unsigned long flags; 1262 u32 old_cr1, new_cr1; 1263 int locked = 1; 1264 1265 local_irq_save(flags); 1266 if (port->sysrq) 1267 locked = 0; 1268 else if (oops_in_progress) 1269 locked = spin_trylock(&port->lock); 1270 else 1271 spin_lock(&port->lock); 1272 1273 /* Save and disable interrupts, enable the transmitter */ 1274 old_cr1 = readl_relaxed(port->membase + ofs->cr1); 1275 new_cr1 = old_cr1 & ~USART_CR1_IE_MASK; 1276 new_cr1 |= USART_CR1_TE | BIT(cfg->uart_enable_bit); 1277 writel_relaxed(new_cr1, port->membase + ofs->cr1); 1278 1279 uart_console_write(port, s, cnt, stm32_console_putchar); 1280 1281 /* Restore interrupt state */ 1282 writel_relaxed(old_cr1, port->membase + ofs->cr1); 1283 1284 if (locked) 1285 spin_unlock(&port->lock); 1286 local_irq_restore(flags); 1287 } 1288 1289 static int stm32_console_setup(struct console *co, char *options) 1290 { 1291 struct stm32_port *stm32port; 1292 int baud = 9600; 1293 int bits = 8; 1294 int parity = 'n'; 1295 int flow = 'n'; 1296 1297 if (co->index >= STM32_MAX_PORTS) 1298 return -ENODEV; 1299 1300 stm32port = &stm32_ports[co->index]; 1301 1302 /* 1303 * This driver does not support early console initialization 1304 * (use ARM early printk support instead), so we only expect 1305 * this to be called during the uart port registration when the 1306 * driver gets probed and the port should be mapped at that point. 1307 */ 1308 if (stm32port->port.mapbase == 0 || stm32port->port.membase == NULL) 1309 return -ENXIO; 1310 1311 if (options) 1312 uart_parse_options(options, &baud, &parity, &bits, &flow); 1313 1314 return uart_set_options(&stm32port->port, co, baud, parity, bits, flow); 1315 } 1316 1317 static struct console stm32_console = { 1318 .name = STM32_SERIAL_NAME, 1319 .device = uart_console_device, 1320 .write = stm32_console_write, 1321 .setup = stm32_console_setup, 1322 .flags = CON_PRINTBUFFER, 1323 .index = -1, 1324 .data = &stm32_usart_driver, 1325 }; 1326 1327 #define STM32_SERIAL_CONSOLE (&stm32_console) 1328 1329 #else 1330 #define STM32_SERIAL_CONSOLE NULL 1331 #endif /* CONFIG_SERIAL_STM32_CONSOLE */ 1332 1333 static struct uart_driver stm32_usart_driver = { 1334 .driver_name = DRIVER_NAME, 1335 .dev_name = STM32_SERIAL_NAME, 1336 .major = 0, 1337 .minor = 0, 1338 .nr = STM32_MAX_PORTS, 1339 .cons = STM32_SERIAL_CONSOLE, 1340 }; 1341 1342 static void __maybe_unused stm32_serial_enable_wakeup(struct uart_port *port, 1343 bool enable) 1344 { 1345 struct stm32_port *stm32_port = to_stm32_port(port); 1346 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1347 struct stm32_usart_config *cfg = &stm32_port->info->cfg; 1348 u32 val; 1349 1350 if (stm32_port->wakeirq <= 0) 1351 return; 1352 1353 if (enable) { 1354 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 1355 stm32_set_bits(port, ofs->cr1, USART_CR1_UESM); 1356 val = readl_relaxed(port->membase + ofs->cr3); 1357 val &= ~USART_CR3_WUS_MASK; 1358 /* Enable Wake up interrupt from low power on start bit */ 1359 val |= USART_CR3_WUS_START_BIT | USART_CR3_WUFIE; 1360 writel_relaxed(val, port->membase + ofs->cr3); 1361 stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 1362 } else { 1363 stm32_clr_bits(port, ofs->cr1, USART_CR1_UESM); 1364 } 1365 } 1366 1367 static int __maybe_unused stm32_serial_suspend(struct device *dev) 1368 { 1369 struct uart_port *port = dev_get_drvdata(dev); 1370 1371 uart_suspend_port(&stm32_usart_driver, port); 1372 1373 if (device_may_wakeup(dev)) 1374 stm32_serial_enable_wakeup(port, true); 1375 else 1376 stm32_serial_enable_wakeup(port, false); 1377 1378 pinctrl_pm_select_sleep_state(dev); 1379 1380 return 0; 1381 } 1382 1383 static int __maybe_unused stm32_serial_resume(struct device *dev) 1384 { 1385 struct uart_port *port = dev_get_drvdata(dev); 1386 1387 pinctrl_pm_select_default_state(dev); 1388 1389 if (device_may_wakeup(dev)) 1390 stm32_serial_enable_wakeup(port, false); 1391 1392 return uart_resume_port(&stm32_usart_driver, port); 1393 } 1394 1395 static int __maybe_unused stm32_serial_runtime_suspend(struct device *dev) 1396 { 1397 struct uart_port *port = dev_get_drvdata(dev); 1398 struct stm32_port *stm32port = container_of(port, 1399 struct stm32_port, port); 1400 1401 clk_disable_unprepare(stm32port->clk); 1402 1403 return 0; 1404 } 1405 1406 static int __maybe_unused stm32_serial_runtime_resume(struct device *dev) 1407 { 1408 struct uart_port *port = dev_get_drvdata(dev); 1409 struct stm32_port *stm32port = container_of(port, 1410 struct stm32_port, port); 1411 1412 return clk_prepare_enable(stm32port->clk); 1413 } 1414 1415 static const struct dev_pm_ops stm32_serial_pm_ops = { 1416 SET_RUNTIME_PM_OPS(stm32_serial_runtime_suspend, 1417 stm32_serial_runtime_resume, NULL) 1418 SET_SYSTEM_SLEEP_PM_OPS(stm32_serial_suspend, stm32_serial_resume) 1419 }; 1420 1421 static struct platform_driver stm32_serial_driver = { 1422 .probe = stm32_serial_probe, 1423 .remove = stm32_serial_remove, 1424 .driver = { 1425 .name = DRIVER_NAME, 1426 .pm = &stm32_serial_pm_ops, 1427 .of_match_table = of_match_ptr(stm32_match), 1428 }, 1429 }; 1430 1431 static int __init usart_init(void) 1432 { 1433 static char banner[] __initdata = "STM32 USART driver initialized"; 1434 int ret; 1435 1436 pr_info("%s\n", banner); 1437 1438 ret = uart_register_driver(&stm32_usart_driver); 1439 if (ret) 1440 return ret; 1441 1442 ret = platform_driver_register(&stm32_serial_driver); 1443 if (ret) 1444 uart_unregister_driver(&stm32_usart_driver); 1445 1446 return ret; 1447 } 1448 1449 static void __exit usart_exit(void) 1450 { 1451 platform_driver_unregister(&stm32_serial_driver); 1452 uart_unregister_driver(&stm32_usart_driver); 1453 } 1454 1455 module_init(usart_init); 1456 module_exit(usart_exit); 1457 1458 MODULE_ALIAS("platform:" DRIVER_NAME); 1459 MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver"); 1460 MODULE_LICENSE("GPL v2"); 1461