1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) Maxime Coquelin 2015 4 * Copyright (C) STMicroelectronics SA 2017 5 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com> 6 * Gerald Baeza <gerald.baeza@foss.st.com> 7 * Erwan Le Ray <erwan.leray@foss.st.com> 8 * 9 * Inspired by st-asc.c from STMicroelectronics (c) 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/console.h> 14 #include <linux/delay.h> 15 #include <linux/dma-direction.h> 16 #include <linux/dmaengine.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/io.h> 19 #include <linux/iopoll.h> 20 #include <linux/irq.h> 21 #include <linux/module.h> 22 #include <linux/of.h> 23 #include <linux/of_platform.h> 24 #include <linux/pinctrl/consumer.h> 25 #include <linux/platform_device.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/pm_wakeirq.h> 28 #include <linux/serial_core.h> 29 #include <linux/serial.h> 30 #include <linux/spinlock.h> 31 #include <linux/sysrq.h> 32 #include <linux/tty_flip.h> 33 #include <linux/tty.h> 34 35 #include "serial_mctrl_gpio.h" 36 #include "stm32-usart.h" 37 38 static void stm32_usart_stop_tx(struct uart_port *port); 39 static void stm32_usart_transmit_chars(struct uart_port *port); 40 41 static inline struct stm32_port *to_stm32_port(struct uart_port *port) 42 { 43 return container_of(port, struct stm32_port, port); 44 } 45 46 static void stm32_usart_set_bits(struct uart_port *port, u32 reg, u32 bits) 47 { 48 u32 val; 49 50 val = readl_relaxed(port->membase + reg); 51 val |= bits; 52 writel_relaxed(val, port->membase + reg); 53 } 54 55 static void stm32_usart_clr_bits(struct uart_port *port, u32 reg, u32 bits) 56 { 57 u32 val; 58 59 val = readl_relaxed(port->membase + reg); 60 val &= ~bits; 61 writel_relaxed(val, port->membase + reg); 62 } 63 64 static void stm32_usart_config_reg_rs485(u32 *cr1, u32 *cr3, u32 delay_ADE, 65 u32 delay_DDE, u32 baud) 66 { 67 u32 rs485_deat_dedt; 68 u32 rs485_deat_dedt_max = (USART_CR1_DEAT_MASK >> USART_CR1_DEAT_SHIFT); 69 bool over8; 70 71 *cr3 |= USART_CR3_DEM; 72 over8 = *cr1 & USART_CR1_OVER8; 73 74 if (over8) 75 rs485_deat_dedt = delay_ADE * baud * 8; 76 else 77 rs485_deat_dedt = delay_ADE * baud * 16; 78 79 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000); 80 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ? 81 rs485_deat_dedt_max : rs485_deat_dedt; 82 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEAT_SHIFT) & 83 USART_CR1_DEAT_MASK; 84 *cr1 |= rs485_deat_dedt; 85 86 if (over8) 87 rs485_deat_dedt = delay_DDE * baud * 8; 88 else 89 rs485_deat_dedt = delay_DDE * baud * 16; 90 91 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000); 92 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ? 93 rs485_deat_dedt_max : rs485_deat_dedt; 94 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEDT_SHIFT) & 95 USART_CR1_DEDT_MASK; 96 *cr1 |= rs485_deat_dedt; 97 } 98 99 static int stm32_usart_config_rs485(struct uart_port *port, 100 struct serial_rs485 *rs485conf) 101 { 102 struct stm32_port *stm32_port = to_stm32_port(port); 103 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 104 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 105 u32 usartdiv, baud, cr1, cr3; 106 bool over8; 107 108 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 109 110 port->rs485 = *rs485conf; 111 112 rs485conf->flags |= SER_RS485_RX_DURING_TX; 113 114 if (rs485conf->flags & SER_RS485_ENABLED) { 115 cr1 = readl_relaxed(port->membase + ofs->cr1); 116 cr3 = readl_relaxed(port->membase + ofs->cr3); 117 usartdiv = readl_relaxed(port->membase + ofs->brr); 118 usartdiv = usartdiv & GENMASK(15, 0); 119 over8 = cr1 & USART_CR1_OVER8; 120 121 if (over8) 122 usartdiv = usartdiv | (usartdiv & GENMASK(4, 0)) 123 << USART_BRR_04_R_SHIFT; 124 125 baud = DIV_ROUND_CLOSEST(port->uartclk, usartdiv); 126 stm32_usart_config_reg_rs485(&cr1, &cr3, 127 rs485conf->delay_rts_before_send, 128 rs485conf->delay_rts_after_send, 129 baud); 130 131 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 132 cr3 &= ~USART_CR3_DEP; 133 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND; 134 } else { 135 cr3 |= USART_CR3_DEP; 136 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; 137 } 138 139 writel_relaxed(cr3, port->membase + ofs->cr3); 140 writel_relaxed(cr1, port->membase + ofs->cr1); 141 } else { 142 stm32_usart_clr_bits(port, ofs->cr3, 143 USART_CR3_DEM | USART_CR3_DEP); 144 stm32_usart_clr_bits(port, ofs->cr1, 145 USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK); 146 } 147 148 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 149 150 return 0; 151 } 152 153 static int stm32_usart_init_rs485(struct uart_port *port, 154 struct platform_device *pdev) 155 { 156 struct serial_rs485 *rs485conf = &port->rs485; 157 158 rs485conf->flags = 0; 159 rs485conf->delay_rts_before_send = 0; 160 rs485conf->delay_rts_after_send = 0; 161 162 if (!pdev->dev.of_node) 163 return -ENODEV; 164 165 return uart_get_rs485_mode(port); 166 } 167 168 static int stm32_usart_pending_rx(struct uart_port *port, u32 *sr, 169 int *last_res, bool threaded) 170 { 171 struct stm32_port *stm32_port = to_stm32_port(port); 172 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 173 enum dma_status status; 174 struct dma_tx_state state; 175 176 *sr = readl_relaxed(port->membase + ofs->isr); 177 178 if (threaded && stm32_port->rx_ch) { 179 status = dmaengine_tx_status(stm32_port->rx_ch, 180 stm32_port->rx_ch->cookie, 181 &state); 182 if (status == DMA_IN_PROGRESS && (*last_res != state.residue)) 183 return 1; 184 else 185 return 0; 186 } else if (*sr & USART_SR_RXNE) { 187 return 1; 188 } 189 return 0; 190 } 191 192 static unsigned long stm32_usart_get_char(struct uart_port *port, u32 *sr, 193 int *last_res) 194 { 195 struct stm32_port *stm32_port = to_stm32_port(port); 196 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 197 unsigned long c; 198 199 if (stm32_port->rx_ch) { 200 c = stm32_port->rx_buf[RX_BUF_L - (*last_res)--]; 201 if ((*last_res) == 0) 202 *last_res = RX_BUF_L; 203 } else { 204 c = readl_relaxed(port->membase + ofs->rdr); 205 /* apply RDR data mask */ 206 c &= stm32_port->rdr_mask; 207 } 208 209 return c; 210 } 211 212 static void stm32_usart_receive_chars(struct uart_port *port, bool threaded) 213 { 214 struct tty_port *tport = &port->state->port; 215 struct stm32_port *stm32_port = to_stm32_port(port); 216 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 217 unsigned long c; 218 u32 sr; 219 char flag; 220 221 spin_lock(&port->lock); 222 223 while (stm32_usart_pending_rx(port, &sr, &stm32_port->last_res, 224 threaded)) { 225 sr |= USART_SR_DUMMY_RX; 226 flag = TTY_NORMAL; 227 228 /* 229 * Status bits has to be cleared before reading the RDR: 230 * In FIFO mode, reading the RDR will pop the next data 231 * (if any) along with its status bits into the SR. 232 * Not doing so leads to misalignement between RDR and SR, 233 * and clear status bits of the next rx data. 234 * 235 * Clear errors flags for stm32f7 and stm32h7 compatible 236 * devices. On stm32f4 compatible devices, the error bit is 237 * cleared by the sequence [read SR - read DR]. 238 */ 239 if ((sr & USART_SR_ERR_MASK) && ofs->icr != UNDEF_REG) 240 writel_relaxed(sr & USART_SR_ERR_MASK, 241 port->membase + ofs->icr); 242 243 c = stm32_usart_get_char(port, &sr, &stm32_port->last_res); 244 port->icount.rx++; 245 if (sr & USART_SR_ERR_MASK) { 246 if (sr & USART_SR_ORE) { 247 port->icount.overrun++; 248 } else if (sr & USART_SR_PE) { 249 port->icount.parity++; 250 } else if (sr & USART_SR_FE) { 251 /* Break detection if character is null */ 252 if (!c) { 253 port->icount.brk++; 254 if (uart_handle_break(port)) 255 continue; 256 } else { 257 port->icount.frame++; 258 } 259 } 260 261 sr &= port->read_status_mask; 262 263 if (sr & USART_SR_PE) { 264 flag = TTY_PARITY; 265 } else if (sr & USART_SR_FE) { 266 if (!c) 267 flag = TTY_BREAK; 268 else 269 flag = TTY_FRAME; 270 } 271 } 272 273 if (uart_prepare_sysrq_char(port, c)) 274 continue; 275 uart_insert_char(port, sr, USART_SR_ORE, c, flag); 276 } 277 278 uart_unlock_and_check_sysrq(port); 279 280 tty_flip_buffer_push(tport); 281 } 282 283 static void stm32_usart_tx_dma_complete(void *arg) 284 { 285 struct uart_port *port = arg; 286 struct stm32_port *stm32port = to_stm32_port(port); 287 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 288 unsigned long flags; 289 290 dmaengine_terminate_async(stm32port->tx_ch); 291 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 292 stm32port->tx_dma_busy = false; 293 294 /* Let's see if we have pending data to send */ 295 spin_lock_irqsave(&port->lock, flags); 296 stm32_usart_transmit_chars(port); 297 spin_unlock_irqrestore(&port->lock, flags); 298 } 299 300 static void stm32_usart_tx_interrupt_enable(struct uart_port *port) 301 { 302 struct stm32_port *stm32_port = to_stm32_port(port); 303 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 304 305 /* 306 * Enables TX FIFO threashold irq when FIFO is enabled, 307 * or TX empty irq when FIFO is disabled 308 */ 309 if (stm32_port->fifoen && stm32_port->txftcfg >= 0) 310 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_TXFTIE); 311 else 312 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TXEIE); 313 } 314 315 static void stm32_usart_tx_interrupt_disable(struct uart_port *port) 316 { 317 struct stm32_port *stm32_port = to_stm32_port(port); 318 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 319 320 if (stm32_port->fifoen && stm32_port->txftcfg >= 0) 321 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_TXFTIE); 322 else 323 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_TXEIE); 324 } 325 326 static void stm32_usart_transmit_chars_pio(struct uart_port *port) 327 { 328 struct stm32_port *stm32_port = to_stm32_port(port); 329 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 330 struct circ_buf *xmit = &port->state->xmit; 331 332 if (stm32_port->tx_dma_busy) { 333 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 334 stm32_port->tx_dma_busy = false; 335 } 336 337 while (!uart_circ_empty(xmit)) { 338 /* Check that TDR is empty before filling FIFO */ 339 if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE)) 340 break; 341 writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr); 342 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 343 port->icount.tx++; 344 } 345 346 /* rely on TXE irq (mask or unmask) for sending remaining data */ 347 if (uart_circ_empty(xmit)) 348 stm32_usart_tx_interrupt_disable(port); 349 else 350 stm32_usart_tx_interrupt_enable(port); 351 } 352 353 static void stm32_usart_transmit_chars_dma(struct uart_port *port) 354 { 355 struct stm32_port *stm32port = to_stm32_port(port); 356 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 357 struct circ_buf *xmit = &port->state->xmit; 358 struct dma_async_tx_descriptor *desc = NULL; 359 unsigned int count, i; 360 361 if (stm32port->tx_dma_busy) 362 return; 363 364 stm32port->tx_dma_busy = true; 365 366 count = uart_circ_chars_pending(xmit); 367 368 if (count > TX_BUF_L) 369 count = TX_BUF_L; 370 371 if (xmit->tail < xmit->head) { 372 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count); 373 } else { 374 size_t one = UART_XMIT_SIZE - xmit->tail; 375 size_t two; 376 377 if (one > count) 378 one = count; 379 two = count - one; 380 381 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one); 382 if (two) 383 memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two); 384 } 385 386 desc = dmaengine_prep_slave_single(stm32port->tx_ch, 387 stm32port->tx_dma_buf, 388 count, 389 DMA_MEM_TO_DEV, 390 DMA_PREP_INTERRUPT); 391 392 if (!desc) 393 goto fallback_err; 394 395 desc->callback = stm32_usart_tx_dma_complete; 396 desc->callback_param = port; 397 398 /* Push current DMA TX transaction in the pending queue */ 399 if (dma_submit_error(dmaengine_submit(desc))) { 400 /* dma no yet started, safe to free resources */ 401 dmaengine_terminate_async(stm32port->tx_ch); 402 goto fallback_err; 403 } 404 405 /* Issue pending DMA TX requests */ 406 dma_async_issue_pending(stm32port->tx_ch); 407 408 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT); 409 410 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); 411 port->icount.tx += count; 412 return; 413 414 fallback_err: 415 for (i = count; i > 0; i--) 416 stm32_usart_transmit_chars_pio(port); 417 } 418 419 static void stm32_usart_transmit_chars(struct uart_port *port) 420 { 421 struct stm32_port *stm32_port = to_stm32_port(port); 422 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 423 struct circ_buf *xmit = &port->state->xmit; 424 425 if (port->x_char) { 426 if (stm32_port->tx_dma_busy) 427 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 428 writel_relaxed(port->x_char, port->membase + ofs->tdr); 429 port->x_char = 0; 430 port->icount.tx++; 431 if (stm32_port->tx_dma_busy) 432 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT); 433 return; 434 } 435 436 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 437 stm32_usart_tx_interrupt_disable(port); 438 return; 439 } 440 441 if (ofs->icr == UNDEF_REG) 442 stm32_usart_clr_bits(port, ofs->isr, USART_SR_TC); 443 else 444 writel_relaxed(USART_ICR_TCCF, port->membase + ofs->icr); 445 446 if (stm32_port->tx_ch) 447 stm32_usart_transmit_chars_dma(port); 448 else 449 stm32_usart_transmit_chars_pio(port); 450 451 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 452 uart_write_wakeup(port); 453 454 if (uart_circ_empty(xmit)) 455 stm32_usart_tx_interrupt_disable(port); 456 } 457 458 static irqreturn_t stm32_usart_interrupt(int irq, void *ptr) 459 { 460 struct uart_port *port = ptr; 461 struct tty_port *tport = &port->state->port; 462 struct stm32_port *stm32_port = to_stm32_port(port); 463 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 464 u32 sr; 465 466 sr = readl_relaxed(port->membase + ofs->isr); 467 468 if ((sr & USART_SR_RTOF) && ofs->icr != UNDEF_REG) 469 writel_relaxed(USART_ICR_RTOCF, 470 port->membase + ofs->icr); 471 472 if ((sr & USART_SR_WUF) && ofs->icr != UNDEF_REG) { 473 /* Clear wake up flag and disable wake up interrupt */ 474 writel_relaxed(USART_ICR_WUCF, 475 port->membase + ofs->icr); 476 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE); 477 if (irqd_is_wakeup_set(irq_get_irq_data(port->irq))) 478 pm_wakeup_event(tport->tty->dev, 0); 479 } 480 481 if ((sr & USART_SR_RXNE) && !(stm32_port->rx_ch)) 482 stm32_usart_receive_chars(port, false); 483 484 if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch)) { 485 spin_lock(&port->lock); 486 stm32_usart_transmit_chars(port); 487 spin_unlock(&port->lock); 488 } 489 490 if (stm32_port->rx_ch) 491 return IRQ_WAKE_THREAD; 492 else 493 return IRQ_HANDLED; 494 } 495 496 static irqreturn_t stm32_usart_threaded_interrupt(int irq, void *ptr) 497 { 498 struct uart_port *port = ptr; 499 struct stm32_port *stm32_port = to_stm32_port(port); 500 501 if (stm32_port->rx_ch) 502 stm32_usart_receive_chars(port, true); 503 504 return IRQ_HANDLED; 505 } 506 507 static unsigned int stm32_usart_tx_empty(struct uart_port *port) 508 { 509 struct stm32_port *stm32_port = to_stm32_port(port); 510 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 511 512 if (readl_relaxed(port->membase + ofs->isr) & USART_SR_TC) 513 return TIOCSER_TEMT; 514 515 return 0; 516 } 517 518 static void stm32_usart_set_mctrl(struct uart_port *port, unsigned int mctrl) 519 { 520 struct stm32_port *stm32_port = to_stm32_port(port); 521 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 522 523 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) 524 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_RTSE); 525 else 526 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_RTSE); 527 528 mctrl_gpio_set(stm32_port->gpios, mctrl); 529 } 530 531 static unsigned int stm32_usart_get_mctrl(struct uart_port *port) 532 { 533 struct stm32_port *stm32_port = to_stm32_port(port); 534 unsigned int ret; 535 536 /* This routine is used to get signals of: DCD, DSR, RI, and CTS */ 537 ret = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; 538 539 return mctrl_gpio_get(stm32_port->gpios, &ret); 540 } 541 542 static void stm32_usart_enable_ms(struct uart_port *port) 543 { 544 mctrl_gpio_enable_ms(to_stm32_port(port)->gpios); 545 } 546 547 static void stm32_usart_disable_ms(struct uart_port *port) 548 { 549 mctrl_gpio_disable_ms(to_stm32_port(port)->gpios); 550 } 551 552 /* Transmit stop */ 553 static void stm32_usart_stop_tx(struct uart_port *port) 554 { 555 struct stm32_port *stm32_port = to_stm32_port(port); 556 struct serial_rs485 *rs485conf = &port->rs485; 557 558 stm32_usart_tx_interrupt_disable(port); 559 560 if (rs485conf->flags & SER_RS485_ENABLED) { 561 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 562 mctrl_gpio_set(stm32_port->gpios, 563 stm32_port->port.mctrl & ~TIOCM_RTS); 564 } else { 565 mctrl_gpio_set(stm32_port->gpios, 566 stm32_port->port.mctrl | TIOCM_RTS); 567 } 568 } 569 } 570 571 /* There are probably characters waiting to be transmitted. */ 572 static void stm32_usart_start_tx(struct uart_port *port) 573 { 574 struct stm32_port *stm32_port = to_stm32_port(port); 575 struct serial_rs485 *rs485conf = &port->rs485; 576 struct circ_buf *xmit = &port->state->xmit; 577 578 if (uart_circ_empty(xmit)) 579 return; 580 581 if (rs485conf->flags & SER_RS485_ENABLED) { 582 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 583 mctrl_gpio_set(stm32_port->gpios, 584 stm32_port->port.mctrl | TIOCM_RTS); 585 } else { 586 mctrl_gpio_set(stm32_port->gpios, 587 stm32_port->port.mctrl & ~TIOCM_RTS); 588 } 589 } 590 591 stm32_usart_transmit_chars(port); 592 } 593 594 /* Flush the transmit buffer. */ 595 static void stm32_usart_flush_buffer(struct uart_port *port) 596 { 597 struct stm32_port *stm32_port = to_stm32_port(port); 598 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 599 600 if (stm32_port->tx_ch) { 601 dmaengine_terminate_async(stm32_port->tx_ch); 602 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 603 stm32_port->tx_dma_busy = false; 604 } 605 } 606 607 /* Throttle the remote when input buffer is about to overflow. */ 608 static void stm32_usart_throttle(struct uart_port *port) 609 { 610 struct stm32_port *stm32_port = to_stm32_port(port); 611 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 612 unsigned long flags; 613 614 spin_lock_irqsave(&port->lock, flags); 615 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq); 616 if (stm32_port->cr3_irq) 617 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); 618 619 spin_unlock_irqrestore(&port->lock, flags); 620 } 621 622 /* Unthrottle the remote, the input buffer can now accept data. */ 623 static void stm32_usart_unthrottle(struct uart_port *port) 624 { 625 struct stm32_port *stm32_port = to_stm32_port(port); 626 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 627 unsigned long flags; 628 629 spin_lock_irqsave(&port->lock, flags); 630 stm32_usart_set_bits(port, ofs->cr1, stm32_port->cr1_irq); 631 if (stm32_port->cr3_irq) 632 stm32_usart_set_bits(port, ofs->cr3, stm32_port->cr3_irq); 633 634 spin_unlock_irqrestore(&port->lock, flags); 635 } 636 637 /* Receive stop */ 638 static void stm32_usart_stop_rx(struct uart_port *port) 639 { 640 struct stm32_port *stm32_port = to_stm32_port(port); 641 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 642 643 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq); 644 if (stm32_port->cr3_irq) 645 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); 646 } 647 648 /* Handle breaks - ignored by us */ 649 static void stm32_usart_break_ctl(struct uart_port *port, int break_state) 650 { 651 } 652 653 static int stm32_usart_startup(struct uart_port *port) 654 { 655 struct stm32_port *stm32_port = to_stm32_port(port); 656 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 657 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 658 const char *name = to_platform_device(port->dev)->name; 659 u32 val; 660 int ret; 661 662 ret = request_threaded_irq(port->irq, stm32_usart_interrupt, 663 stm32_usart_threaded_interrupt, 664 IRQF_ONESHOT | IRQF_NO_SUSPEND, 665 name, port); 666 if (ret) 667 return ret; 668 669 if (stm32_port->swap) { 670 val = readl_relaxed(port->membase + ofs->cr2); 671 val |= USART_CR2_SWAP; 672 writel_relaxed(val, port->membase + ofs->cr2); 673 } 674 675 /* RX FIFO Flush */ 676 if (ofs->rqr != UNDEF_REG) 677 writel_relaxed(USART_RQR_RXFRQ, port->membase + ofs->rqr); 678 679 /* RX enabling */ 680 val = stm32_port->cr1_irq | USART_CR1_RE | BIT(cfg->uart_enable_bit); 681 stm32_usart_set_bits(port, ofs->cr1, val); 682 683 return 0; 684 } 685 686 static void stm32_usart_shutdown(struct uart_port *port) 687 { 688 struct stm32_port *stm32_port = to_stm32_port(port); 689 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 690 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 691 u32 val, isr; 692 int ret; 693 694 /* Disable modem control interrupts */ 695 stm32_usart_disable_ms(port); 696 697 val = USART_CR1_TXEIE | USART_CR1_TE; 698 val |= stm32_port->cr1_irq | USART_CR1_RE; 699 val |= BIT(cfg->uart_enable_bit); 700 if (stm32_port->fifoen) 701 val |= USART_CR1_FIFOEN; 702 703 ret = readl_relaxed_poll_timeout(port->membase + ofs->isr, 704 isr, (isr & USART_SR_TC), 705 10, 100000); 706 707 /* Send the TC error message only when ISR_TC is not set */ 708 if (ret) 709 dev_err(port->dev, "Transmission is not complete\n"); 710 711 /* flush RX & TX FIFO */ 712 if (ofs->rqr != UNDEF_REG) 713 writel_relaxed(USART_RQR_TXFRQ | USART_RQR_RXFRQ, 714 port->membase + ofs->rqr); 715 716 stm32_usart_clr_bits(port, ofs->cr1, val); 717 718 free_irq(port->irq, port); 719 } 720 721 static unsigned int stm32_usart_get_databits(struct ktermios *termios) 722 { 723 unsigned int bits; 724 725 tcflag_t cflag = termios->c_cflag; 726 727 switch (cflag & CSIZE) { 728 /* 729 * CSIZE settings are not necessarily supported in hardware. 730 * CSIZE unsupported configurations are handled here to set word length 731 * to 8 bits word as default configuration and to print debug message. 732 */ 733 case CS5: 734 bits = 5; 735 break; 736 case CS6: 737 bits = 6; 738 break; 739 case CS7: 740 bits = 7; 741 break; 742 /* default including CS8 */ 743 default: 744 bits = 8; 745 break; 746 } 747 748 return bits; 749 } 750 751 static void stm32_usart_set_termios(struct uart_port *port, 752 struct ktermios *termios, 753 struct ktermios *old) 754 { 755 struct stm32_port *stm32_port = to_stm32_port(port); 756 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 757 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 758 struct serial_rs485 *rs485conf = &port->rs485; 759 unsigned int baud, bits; 760 u32 usartdiv, mantissa, fraction, oversampling; 761 tcflag_t cflag = termios->c_cflag; 762 u32 cr1, cr2, cr3, isr; 763 unsigned long flags; 764 int ret; 765 766 if (!stm32_port->hw_flow_control) 767 cflag &= ~CRTSCTS; 768 769 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8); 770 771 spin_lock_irqsave(&port->lock, flags); 772 773 ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, 774 isr, 775 (isr & USART_SR_TC), 776 10, 100000); 777 778 /* Send the TC error message only when ISR_TC is not set. */ 779 if (ret) 780 dev_err(port->dev, "Transmission is not complete\n"); 781 782 /* Stop serial port and reset value */ 783 writel_relaxed(0, port->membase + ofs->cr1); 784 785 /* flush RX & TX FIFO */ 786 if (ofs->rqr != UNDEF_REG) 787 writel_relaxed(USART_RQR_TXFRQ | USART_RQR_RXFRQ, 788 port->membase + ofs->rqr); 789 790 cr1 = USART_CR1_TE | USART_CR1_RE; 791 if (stm32_port->fifoen) 792 cr1 |= USART_CR1_FIFOEN; 793 cr2 = stm32_port->swap ? USART_CR2_SWAP : 0; 794 795 /* Tx and RX FIFO configuration */ 796 cr3 = readl_relaxed(port->membase + ofs->cr3); 797 cr3 &= USART_CR3_TXFTIE | USART_CR3_RXFTIE; 798 if (stm32_port->fifoen) { 799 if (stm32_port->txftcfg >= 0) 800 cr3 |= stm32_port->txftcfg << USART_CR3_TXFTCFG_SHIFT; 801 if (stm32_port->rxftcfg >= 0) 802 cr3 |= stm32_port->rxftcfg << USART_CR3_RXFTCFG_SHIFT; 803 } 804 805 if (cflag & CSTOPB) 806 cr2 |= USART_CR2_STOP_2B; 807 808 bits = stm32_usart_get_databits(termios); 809 stm32_port->rdr_mask = (BIT(bits) - 1); 810 811 if (cflag & PARENB) { 812 bits++; 813 cr1 |= USART_CR1_PCE; 814 } 815 816 /* 817 * Word length configuration: 818 * CS8 + parity, 9 bits word aka [M1:M0] = 0b01 819 * CS7 or (CS6 + parity), 7 bits word aka [M1:M0] = 0b10 820 * CS8 or (CS7 + parity), 8 bits word aka [M1:M0] = 0b00 821 * M0 and M1 already cleared by cr1 initialization. 822 */ 823 if (bits == 9) 824 cr1 |= USART_CR1_M0; 825 else if ((bits == 7) && cfg->has_7bits_data) 826 cr1 |= USART_CR1_M1; 827 else if (bits != 8) 828 dev_dbg(port->dev, "Unsupported data bits config: %u bits\n" 829 , bits); 830 831 if (ofs->rtor != UNDEF_REG && (stm32_port->rx_ch || 832 (stm32_port->fifoen && 833 stm32_port->rxftcfg >= 0))) { 834 if (cflag & CSTOPB) 835 bits = bits + 3; /* 1 start bit + 2 stop bits */ 836 else 837 bits = bits + 2; /* 1 start bit + 1 stop bit */ 838 839 /* RX timeout irq to occur after last stop bit + bits */ 840 stm32_port->cr1_irq = USART_CR1_RTOIE; 841 writel_relaxed(bits, port->membase + ofs->rtor); 842 cr2 |= USART_CR2_RTOEN; 843 /* Not using dma, enable fifo threshold irq */ 844 if (!stm32_port->rx_ch) 845 stm32_port->cr3_irq = USART_CR3_RXFTIE; 846 } 847 848 cr1 |= stm32_port->cr1_irq; 849 cr3 |= stm32_port->cr3_irq; 850 851 if (cflag & PARODD) 852 cr1 |= USART_CR1_PS; 853 854 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); 855 if (cflag & CRTSCTS) { 856 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 857 cr3 |= USART_CR3_CTSE | USART_CR3_RTSE; 858 } 859 860 usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud); 861 862 /* 863 * The USART supports 16 or 8 times oversampling. 864 * By default we prefer 16 times oversampling, so that the receiver 865 * has a better tolerance to clock deviations. 866 * 8 times oversampling is only used to achieve higher speeds. 867 */ 868 if (usartdiv < 16) { 869 oversampling = 8; 870 cr1 |= USART_CR1_OVER8; 871 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_OVER8); 872 } else { 873 oversampling = 16; 874 cr1 &= ~USART_CR1_OVER8; 875 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_OVER8); 876 } 877 878 mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT; 879 fraction = usartdiv % oversampling; 880 writel_relaxed(mantissa | fraction, port->membase + ofs->brr); 881 882 uart_update_timeout(port, cflag, baud); 883 884 port->read_status_mask = USART_SR_ORE; 885 if (termios->c_iflag & INPCK) 886 port->read_status_mask |= USART_SR_PE | USART_SR_FE; 887 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 888 port->read_status_mask |= USART_SR_FE; 889 890 /* Characters to ignore */ 891 port->ignore_status_mask = 0; 892 if (termios->c_iflag & IGNPAR) 893 port->ignore_status_mask = USART_SR_PE | USART_SR_FE; 894 if (termios->c_iflag & IGNBRK) { 895 port->ignore_status_mask |= USART_SR_FE; 896 /* 897 * If we're ignoring parity and break indicators, 898 * ignore overruns too (for real raw support). 899 */ 900 if (termios->c_iflag & IGNPAR) 901 port->ignore_status_mask |= USART_SR_ORE; 902 } 903 904 /* Ignore all characters if CREAD is not set */ 905 if ((termios->c_cflag & CREAD) == 0) 906 port->ignore_status_mask |= USART_SR_DUMMY_RX; 907 908 if (stm32_port->rx_ch) 909 cr3 |= USART_CR3_DMAR; 910 911 if (rs485conf->flags & SER_RS485_ENABLED) { 912 stm32_usart_config_reg_rs485(&cr1, &cr3, 913 rs485conf->delay_rts_before_send, 914 rs485conf->delay_rts_after_send, 915 baud); 916 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 917 cr3 &= ~USART_CR3_DEP; 918 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND; 919 } else { 920 cr3 |= USART_CR3_DEP; 921 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; 922 } 923 924 } else { 925 cr3 &= ~(USART_CR3_DEM | USART_CR3_DEP); 926 cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK); 927 } 928 929 /* Configure wake up from low power on start bit detection */ 930 if (stm32_port->wakeup_src) { 931 cr3 &= ~USART_CR3_WUS_MASK; 932 cr3 |= USART_CR3_WUS_START_BIT; 933 } 934 935 writel_relaxed(cr3, port->membase + ofs->cr3); 936 writel_relaxed(cr2, port->membase + ofs->cr2); 937 writel_relaxed(cr1, port->membase + ofs->cr1); 938 939 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 940 spin_unlock_irqrestore(&port->lock, flags); 941 942 /* Handle modem control interrupts */ 943 if (UART_ENABLE_MS(port, termios->c_cflag)) 944 stm32_usart_enable_ms(port); 945 else 946 stm32_usart_disable_ms(port); 947 } 948 949 static const char *stm32_usart_type(struct uart_port *port) 950 { 951 return (port->type == PORT_STM32) ? DRIVER_NAME : NULL; 952 } 953 954 static void stm32_usart_release_port(struct uart_port *port) 955 { 956 } 957 958 static int stm32_usart_request_port(struct uart_port *port) 959 { 960 return 0; 961 } 962 963 static void stm32_usart_config_port(struct uart_port *port, int flags) 964 { 965 if (flags & UART_CONFIG_TYPE) 966 port->type = PORT_STM32; 967 } 968 969 static int 970 stm32_usart_verify_port(struct uart_port *port, struct serial_struct *ser) 971 { 972 /* No user changeable parameters */ 973 return -EINVAL; 974 } 975 976 static void stm32_usart_pm(struct uart_port *port, unsigned int state, 977 unsigned int oldstate) 978 { 979 struct stm32_port *stm32port = container_of(port, 980 struct stm32_port, port); 981 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 982 const struct stm32_usart_config *cfg = &stm32port->info->cfg; 983 unsigned long flags = 0; 984 985 switch (state) { 986 case UART_PM_STATE_ON: 987 pm_runtime_get_sync(port->dev); 988 break; 989 case UART_PM_STATE_OFF: 990 spin_lock_irqsave(&port->lock, flags); 991 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 992 spin_unlock_irqrestore(&port->lock, flags); 993 pm_runtime_put_sync(port->dev); 994 break; 995 } 996 } 997 998 static const struct uart_ops stm32_uart_ops = { 999 .tx_empty = stm32_usart_tx_empty, 1000 .set_mctrl = stm32_usart_set_mctrl, 1001 .get_mctrl = stm32_usart_get_mctrl, 1002 .stop_tx = stm32_usart_stop_tx, 1003 .start_tx = stm32_usart_start_tx, 1004 .throttle = stm32_usart_throttle, 1005 .unthrottle = stm32_usart_unthrottle, 1006 .stop_rx = stm32_usart_stop_rx, 1007 .enable_ms = stm32_usart_enable_ms, 1008 .break_ctl = stm32_usart_break_ctl, 1009 .startup = stm32_usart_startup, 1010 .shutdown = stm32_usart_shutdown, 1011 .flush_buffer = stm32_usart_flush_buffer, 1012 .set_termios = stm32_usart_set_termios, 1013 .pm = stm32_usart_pm, 1014 .type = stm32_usart_type, 1015 .release_port = stm32_usart_release_port, 1016 .request_port = stm32_usart_request_port, 1017 .config_port = stm32_usart_config_port, 1018 .verify_port = stm32_usart_verify_port, 1019 }; 1020 1021 /* 1022 * STM32H7 RX & TX FIFO threshold configuration (CR3 RXFTCFG / TXFTCFG) 1023 * Note: 1 isn't a valid value in RXFTCFG / TXFTCFG. In this case, 1024 * RXNEIE / TXEIE can be used instead of threshold irqs: RXFTIE / TXFTIE. 1025 * So, RXFTCFG / TXFTCFG bitfields values are encoded as array index + 1. 1026 */ 1027 static const u32 stm32h7_usart_fifo_thresh_cfg[] = { 1, 2, 4, 8, 12, 14, 16 }; 1028 1029 static void stm32_usart_get_ftcfg(struct platform_device *pdev, const char *p, 1030 int *ftcfg) 1031 { 1032 u32 bytes, i; 1033 1034 /* DT option to get RX & TX FIFO threshold (default to 8 bytes) */ 1035 if (of_property_read_u32(pdev->dev.of_node, p, &bytes)) 1036 bytes = 8; 1037 1038 for (i = 0; i < ARRAY_SIZE(stm32h7_usart_fifo_thresh_cfg); i++) 1039 if (stm32h7_usart_fifo_thresh_cfg[i] >= bytes) 1040 break; 1041 if (i >= ARRAY_SIZE(stm32h7_usart_fifo_thresh_cfg)) 1042 i = ARRAY_SIZE(stm32h7_usart_fifo_thresh_cfg) - 1; 1043 1044 dev_dbg(&pdev->dev, "%s set to %d bytes\n", p, 1045 stm32h7_usart_fifo_thresh_cfg[i]); 1046 1047 /* Provide FIFO threshold ftcfg (1 is invalid: threshold irq unused) */ 1048 if (i) 1049 *ftcfg = i - 1; 1050 else 1051 *ftcfg = -EINVAL; 1052 } 1053 1054 static void stm32_usart_deinit_port(struct stm32_port *stm32port) 1055 { 1056 clk_disable_unprepare(stm32port->clk); 1057 } 1058 1059 static int stm32_usart_init_port(struct stm32_port *stm32port, 1060 struct platform_device *pdev) 1061 { 1062 struct uart_port *port = &stm32port->port; 1063 struct resource *res; 1064 int ret, irq; 1065 1066 irq = platform_get_irq(pdev, 0); 1067 if (irq <= 0) 1068 return irq ? : -ENODEV; 1069 1070 port->iotype = UPIO_MEM; 1071 port->flags = UPF_BOOT_AUTOCONF; 1072 port->ops = &stm32_uart_ops; 1073 port->dev = &pdev->dev; 1074 port->fifosize = stm32port->info->cfg.fifosize; 1075 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_STM32_CONSOLE); 1076 port->irq = irq; 1077 port->rs485_config = stm32_usart_config_rs485; 1078 1079 ret = stm32_usart_init_rs485(port, pdev); 1080 if (ret) 1081 return ret; 1082 1083 stm32port->wakeup_src = stm32port->info->cfg.has_wakeup && 1084 of_property_read_bool(pdev->dev.of_node, "wakeup-source"); 1085 1086 stm32port->swap = stm32port->info->cfg.has_swap && 1087 of_property_read_bool(pdev->dev.of_node, "rx-tx-swap"); 1088 1089 stm32port->fifoen = stm32port->info->cfg.has_fifo; 1090 if (stm32port->fifoen) { 1091 stm32_usart_get_ftcfg(pdev, "rx-threshold", 1092 &stm32port->rxftcfg); 1093 stm32_usart_get_ftcfg(pdev, "tx-threshold", 1094 &stm32port->txftcfg); 1095 } 1096 1097 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1098 port->membase = devm_ioremap_resource(&pdev->dev, res); 1099 if (IS_ERR(port->membase)) 1100 return PTR_ERR(port->membase); 1101 port->mapbase = res->start; 1102 1103 spin_lock_init(&port->lock); 1104 1105 stm32port->clk = devm_clk_get(&pdev->dev, NULL); 1106 if (IS_ERR(stm32port->clk)) 1107 return PTR_ERR(stm32port->clk); 1108 1109 /* Ensure that clk rate is correct by enabling the clk */ 1110 ret = clk_prepare_enable(stm32port->clk); 1111 if (ret) 1112 return ret; 1113 1114 stm32port->port.uartclk = clk_get_rate(stm32port->clk); 1115 if (!stm32port->port.uartclk) { 1116 ret = -EINVAL; 1117 goto err_clk; 1118 } 1119 1120 stm32port->gpios = mctrl_gpio_init(&stm32port->port, 0); 1121 if (IS_ERR(stm32port->gpios)) { 1122 ret = PTR_ERR(stm32port->gpios); 1123 goto err_clk; 1124 } 1125 1126 /* 1127 * Both CTS/RTS gpios and "st,hw-flow-ctrl" (deprecated) or "uart-has-rtscts" 1128 * properties should not be specified. 1129 */ 1130 if (stm32port->hw_flow_control) { 1131 if (mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_CTS) || 1132 mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_RTS)) { 1133 dev_err(&pdev->dev, "Conflicting RTS/CTS config\n"); 1134 ret = -EINVAL; 1135 goto err_clk; 1136 } 1137 } 1138 1139 return ret; 1140 1141 err_clk: 1142 clk_disable_unprepare(stm32port->clk); 1143 1144 return ret; 1145 } 1146 1147 static struct stm32_port *stm32_usart_of_get_port(struct platform_device *pdev) 1148 { 1149 struct device_node *np = pdev->dev.of_node; 1150 int id; 1151 1152 if (!np) 1153 return NULL; 1154 1155 id = of_alias_get_id(np, "serial"); 1156 if (id < 0) { 1157 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", id); 1158 return NULL; 1159 } 1160 1161 if (WARN_ON(id >= STM32_MAX_PORTS)) 1162 return NULL; 1163 1164 stm32_ports[id].hw_flow_control = 1165 of_property_read_bool (np, "st,hw-flow-ctrl") /*deprecated*/ || 1166 of_property_read_bool (np, "uart-has-rtscts"); 1167 stm32_ports[id].port.line = id; 1168 stm32_ports[id].cr1_irq = USART_CR1_RXNEIE; 1169 stm32_ports[id].cr3_irq = 0; 1170 stm32_ports[id].last_res = RX_BUF_L; 1171 return &stm32_ports[id]; 1172 } 1173 1174 #ifdef CONFIG_OF 1175 static const struct of_device_id stm32_match[] = { 1176 { .compatible = "st,stm32-uart", .data = &stm32f4_info}, 1177 { .compatible = "st,stm32f7-uart", .data = &stm32f7_info}, 1178 { .compatible = "st,stm32h7-uart", .data = &stm32h7_info}, 1179 {}, 1180 }; 1181 1182 MODULE_DEVICE_TABLE(of, stm32_match); 1183 #endif 1184 1185 static int stm32_usart_of_dma_rx_probe(struct stm32_port *stm32port, 1186 struct platform_device *pdev) 1187 { 1188 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 1189 struct uart_port *port = &stm32port->port; 1190 struct device *dev = &pdev->dev; 1191 struct dma_slave_config config; 1192 struct dma_async_tx_descriptor *desc = NULL; 1193 int ret; 1194 1195 /* 1196 * Using DMA and threaded handler for the console could lead to 1197 * deadlocks. 1198 */ 1199 if (uart_console(port)) 1200 return -ENODEV; 1201 1202 /* Request DMA RX channel */ 1203 stm32port->rx_ch = dma_request_slave_channel(dev, "rx"); 1204 if (!stm32port->rx_ch) { 1205 dev_info(dev, "rx dma alloc failed\n"); 1206 return -ENODEV; 1207 } 1208 stm32port->rx_buf = dma_alloc_coherent(&pdev->dev, RX_BUF_L, 1209 &stm32port->rx_dma_buf, 1210 GFP_KERNEL); 1211 if (!stm32port->rx_buf) { 1212 ret = -ENOMEM; 1213 goto alloc_err; 1214 } 1215 1216 /* Configure DMA channel */ 1217 memset(&config, 0, sizeof(config)); 1218 config.src_addr = port->mapbase + ofs->rdr; 1219 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1220 1221 ret = dmaengine_slave_config(stm32port->rx_ch, &config); 1222 if (ret < 0) { 1223 dev_err(dev, "rx dma channel config failed\n"); 1224 ret = -ENODEV; 1225 goto config_err; 1226 } 1227 1228 /* Prepare a DMA cyclic transaction */ 1229 desc = dmaengine_prep_dma_cyclic(stm32port->rx_ch, 1230 stm32port->rx_dma_buf, 1231 RX_BUF_L, RX_BUF_P, DMA_DEV_TO_MEM, 1232 DMA_PREP_INTERRUPT); 1233 if (!desc) { 1234 dev_err(dev, "rx dma prep cyclic failed\n"); 1235 ret = -ENODEV; 1236 goto config_err; 1237 } 1238 1239 /* No callback as dma buffer is drained on usart interrupt */ 1240 desc->callback = NULL; 1241 desc->callback_param = NULL; 1242 1243 /* Push current DMA transaction in the pending queue */ 1244 ret = dma_submit_error(dmaengine_submit(desc)); 1245 if (ret) { 1246 dmaengine_terminate_sync(stm32port->rx_ch); 1247 goto config_err; 1248 } 1249 1250 /* Issue pending DMA requests */ 1251 dma_async_issue_pending(stm32port->rx_ch); 1252 1253 return 0; 1254 1255 config_err: 1256 dma_free_coherent(&pdev->dev, 1257 RX_BUF_L, stm32port->rx_buf, 1258 stm32port->rx_dma_buf); 1259 1260 alloc_err: 1261 dma_release_channel(stm32port->rx_ch); 1262 stm32port->rx_ch = NULL; 1263 1264 return ret; 1265 } 1266 1267 static int stm32_usart_of_dma_tx_probe(struct stm32_port *stm32port, 1268 struct platform_device *pdev) 1269 { 1270 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 1271 struct uart_port *port = &stm32port->port; 1272 struct device *dev = &pdev->dev; 1273 struct dma_slave_config config; 1274 int ret; 1275 1276 stm32port->tx_dma_busy = false; 1277 1278 /* Request DMA TX channel */ 1279 stm32port->tx_ch = dma_request_slave_channel(dev, "tx"); 1280 if (!stm32port->tx_ch) { 1281 dev_info(dev, "tx dma alloc failed\n"); 1282 return -ENODEV; 1283 } 1284 stm32port->tx_buf = dma_alloc_coherent(&pdev->dev, TX_BUF_L, 1285 &stm32port->tx_dma_buf, 1286 GFP_KERNEL); 1287 if (!stm32port->tx_buf) { 1288 ret = -ENOMEM; 1289 goto alloc_err; 1290 } 1291 1292 /* Configure DMA channel */ 1293 memset(&config, 0, sizeof(config)); 1294 config.dst_addr = port->mapbase + ofs->tdr; 1295 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1296 1297 ret = dmaengine_slave_config(stm32port->tx_ch, &config); 1298 if (ret < 0) { 1299 dev_err(dev, "tx dma channel config failed\n"); 1300 ret = -ENODEV; 1301 goto config_err; 1302 } 1303 1304 return 0; 1305 1306 config_err: 1307 dma_free_coherent(&pdev->dev, 1308 TX_BUF_L, stm32port->tx_buf, 1309 stm32port->tx_dma_buf); 1310 1311 alloc_err: 1312 dma_release_channel(stm32port->tx_ch); 1313 stm32port->tx_ch = NULL; 1314 1315 return ret; 1316 } 1317 1318 static int stm32_usart_serial_probe(struct platform_device *pdev) 1319 { 1320 struct stm32_port *stm32port; 1321 int ret; 1322 1323 stm32port = stm32_usart_of_get_port(pdev); 1324 if (!stm32port) 1325 return -ENODEV; 1326 1327 stm32port->info = of_device_get_match_data(&pdev->dev); 1328 if (!stm32port->info) 1329 return -EINVAL; 1330 1331 ret = stm32_usart_init_port(stm32port, pdev); 1332 if (ret) 1333 return ret; 1334 1335 if (stm32port->wakeup_src) { 1336 device_set_wakeup_capable(&pdev->dev, true); 1337 ret = dev_pm_set_wake_irq(&pdev->dev, stm32port->port.irq); 1338 if (ret) 1339 goto err_nowup; 1340 } 1341 1342 ret = stm32_usart_of_dma_rx_probe(stm32port, pdev); 1343 if (ret) 1344 dev_info(&pdev->dev, "interrupt mode used for rx (no dma)\n"); 1345 1346 ret = stm32_usart_of_dma_tx_probe(stm32port, pdev); 1347 if (ret) 1348 dev_info(&pdev->dev, "interrupt mode used for tx (no dma)\n"); 1349 1350 platform_set_drvdata(pdev, &stm32port->port); 1351 1352 pm_runtime_get_noresume(&pdev->dev); 1353 pm_runtime_set_active(&pdev->dev); 1354 pm_runtime_enable(&pdev->dev); 1355 1356 ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port); 1357 if (ret) 1358 goto err_port; 1359 1360 pm_runtime_put_sync(&pdev->dev); 1361 1362 return 0; 1363 1364 err_port: 1365 pm_runtime_disable(&pdev->dev); 1366 pm_runtime_set_suspended(&pdev->dev); 1367 pm_runtime_put_noidle(&pdev->dev); 1368 1369 if (stm32port->rx_ch) { 1370 dmaengine_terminate_async(stm32port->rx_ch); 1371 dma_release_channel(stm32port->rx_ch); 1372 } 1373 1374 if (stm32port->rx_dma_buf) 1375 dma_free_coherent(&pdev->dev, 1376 RX_BUF_L, stm32port->rx_buf, 1377 stm32port->rx_dma_buf); 1378 1379 if (stm32port->tx_ch) { 1380 dmaengine_terminate_async(stm32port->tx_ch); 1381 dma_release_channel(stm32port->tx_ch); 1382 } 1383 1384 if (stm32port->tx_dma_buf) 1385 dma_free_coherent(&pdev->dev, 1386 TX_BUF_L, stm32port->tx_buf, 1387 stm32port->tx_dma_buf); 1388 1389 if (stm32port->wakeup_src) 1390 dev_pm_clear_wake_irq(&pdev->dev); 1391 1392 err_nowup: 1393 if (stm32port->wakeup_src) 1394 device_set_wakeup_capable(&pdev->dev, false); 1395 1396 stm32_usart_deinit_port(stm32port); 1397 1398 return ret; 1399 } 1400 1401 static int stm32_usart_serial_remove(struct platform_device *pdev) 1402 { 1403 struct uart_port *port = platform_get_drvdata(pdev); 1404 struct stm32_port *stm32_port = to_stm32_port(port); 1405 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1406 int err; 1407 1408 pm_runtime_get_sync(&pdev->dev); 1409 err = uart_remove_one_port(&stm32_usart_driver, port); 1410 if (err) 1411 return(err); 1412 1413 pm_runtime_disable(&pdev->dev); 1414 pm_runtime_set_suspended(&pdev->dev); 1415 pm_runtime_put_noidle(&pdev->dev); 1416 1417 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR); 1418 1419 if (stm32_port->rx_ch) { 1420 dmaengine_terminate_async(stm32_port->rx_ch); 1421 dma_release_channel(stm32_port->rx_ch); 1422 } 1423 1424 if (stm32_port->rx_dma_buf) 1425 dma_free_coherent(&pdev->dev, 1426 RX_BUF_L, stm32_port->rx_buf, 1427 stm32_port->rx_dma_buf); 1428 1429 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 1430 1431 if (stm32_port->tx_ch) { 1432 dmaengine_terminate_async(stm32_port->tx_ch); 1433 dma_release_channel(stm32_port->tx_ch); 1434 } 1435 1436 if (stm32_port->tx_dma_buf) 1437 dma_free_coherent(&pdev->dev, 1438 TX_BUF_L, stm32_port->tx_buf, 1439 stm32_port->tx_dma_buf); 1440 1441 if (stm32_port->wakeup_src) { 1442 dev_pm_clear_wake_irq(&pdev->dev); 1443 device_init_wakeup(&pdev->dev, false); 1444 } 1445 1446 stm32_usart_deinit_port(stm32_port); 1447 1448 return 0; 1449 } 1450 1451 #ifdef CONFIG_SERIAL_STM32_CONSOLE 1452 static void stm32_usart_console_putchar(struct uart_port *port, int ch) 1453 { 1454 struct stm32_port *stm32_port = to_stm32_port(port); 1455 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1456 1457 while (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE)) 1458 cpu_relax(); 1459 1460 writel_relaxed(ch, port->membase + ofs->tdr); 1461 } 1462 1463 static void stm32_usart_console_write(struct console *co, const char *s, 1464 unsigned int cnt) 1465 { 1466 struct uart_port *port = &stm32_ports[co->index].port; 1467 struct stm32_port *stm32_port = to_stm32_port(port); 1468 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1469 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 1470 unsigned long flags; 1471 u32 old_cr1, new_cr1; 1472 int locked = 1; 1473 1474 if (oops_in_progress) 1475 locked = spin_trylock_irqsave(&port->lock, flags); 1476 else 1477 spin_lock_irqsave(&port->lock, flags); 1478 1479 /* Save and disable interrupts, enable the transmitter */ 1480 old_cr1 = readl_relaxed(port->membase + ofs->cr1); 1481 new_cr1 = old_cr1 & ~USART_CR1_IE_MASK; 1482 new_cr1 |= USART_CR1_TE | BIT(cfg->uart_enable_bit); 1483 writel_relaxed(new_cr1, port->membase + ofs->cr1); 1484 1485 uart_console_write(port, s, cnt, stm32_usart_console_putchar); 1486 1487 /* Restore interrupt state */ 1488 writel_relaxed(old_cr1, port->membase + ofs->cr1); 1489 1490 if (locked) 1491 spin_unlock_irqrestore(&port->lock, flags); 1492 } 1493 1494 static int stm32_usart_console_setup(struct console *co, char *options) 1495 { 1496 struct stm32_port *stm32port; 1497 int baud = 9600; 1498 int bits = 8; 1499 int parity = 'n'; 1500 int flow = 'n'; 1501 1502 if (co->index >= STM32_MAX_PORTS) 1503 return -ENODEV; 1504 1505 stm32port = &stm32_ports[co->index]; 1506 1507 /* 1508 * This driver does not support early console initialization 1509 * (use ARM early printk support instead), so we only expect 1510 * this to be called during the uart port registration when the 1511 * driver gets probed and the port should be mapped at that point. 1512 */ 1513 if (stm32port->port.mapbase == 0 || !stm32port->port.membase) 1514 return -ENXIO; 1515 1516 if (options) 1517 uart_parse_options(options, &baud, &parity, &bits, &flow); 1518 1519 return uart_set_options(&stm32port->port, co, baud, parity, bits, flow); 1520 } 1521 1522 static struct console stm32_console = { 1523 .name = STM32_SERIAL_NAME, 1524 .device = uart_console_device, 1525 .write = stm32_usart_console_write, 1526 .setup = stm32_usart_console_setup, 1527 .flags = CON_PRINTBUFFER, 1528 .index = -1, 1529 .data = &stm32_usart_driver, 1530 }; 1531 1532 #define STM32_SERIAL_CONSOLE (&stm32_console) 1533 1534 #else 1535 #define STM32_SERIAL_CONSOLE NULL 1536 #endif /* CONFIG_SERIAL_STM32_CONSOLE */ 1537 1538 static struct uart_driver stm32_usart_driver = { 1539 .driver_name = DRIVER_NAME, 1540 .dev_name = STM32_SERIAL_NAME, 1541 .major = 0, 1542 .minor = 0, 1543 .nr = STM32_MAX_PORTS, 1544 .cons = STM32_SERIAL_CONSOLE, 1545 }; 1546 1547 static void __maybe_unused stm32_usart_serial_en_wakeup(struct uart_port *port, 1548 bool enable) 1549 { 1550 struct stm32_port *stm32_port = to_stm32_port(port); 1551 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1552 1553 if (!stm32_port->wakeup_src) 1554 return; 1555 1556 /* 1557 * Enable low-power wake-up and wake-up irq if argument is set to 1558 * "enable", disable low-power wake-up and wake-up irq otherwise 1559 */ 1560 if (enable) { 1561 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_UESM); 1562 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_WUFIE); 1563 } else { 1564 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_UESM); 1565 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE); 1566 } 1567 } 1568 1569 static int __maybe_unused stm32_usart_serial_suspend(struct device *dev) 1570 { 1571 struct uart_port *port = dev_get_drvdata(dev); 1572 1573 uart_suspend_port(&stm32_usart_driver, port); 1574 1575 if (device_may_wakeup(dev) || device_wakeup_path(dev)) 1576 stm32_usart_serial_en_wakeup(port, true); 1577 1578 /* 1579 * When "no_console_suspend" is enabled, keep the pinctrl default state 1580 * and rely on bootloader stage to restore this state upon resume. 1581 * Otherwise, apply the idle or sleep states depending on wakeup 1582 * capabilities. 1583 */ 1584 if (console_suspend_enabled || !uart_console(port)) { 1585 if (device_may_wakeup(dev) || device_wakeup_path(dev)) 1586 pinctrl_pm_select_idle_state(dev); 1587 else 1588 pinctrl_pm_select_sleep_state(dev); 1589 } 1590 1591 return 0; 1592 } 1593 1594 static int __maybe_unused stm32_usart_serial_resume(struct device *dev) 1595 { 1596 struct uart_port *port = dev_get_drvdata(dev); 1597 1598 pinctrl_pm_select_default_state(dev); 1599 1600 if (device_may_wakeup(dev) || device_wakeup_path(dev)) 1601 stm32_usart_serial_en_wakeup(port, false); 1602 1603 return uart_resume_port(&stm32_usart_driver, port); 1604 } 1605 1606 static int __maybe_unused stm32_usart_runtime_suspend(struct device *dev) 1607 { 1608 struct uart_port *port = dev_get_drvdata(dev); 1609 struct stm32_port *stm32port = container_of(port, 1610 struct stm32_port, port); 1611 1612 clk_disable_unprepare(stm32port->clk); 1613 1614 return 0; 1615 } 1616 1617 static int __maybe_unused stm32_usart_runtime_resume(struct device *dev) 1618 { 1619 struct uart_port *port = dev_get_drvdata(dev); 1620 struct stm32_port *stm32port = container_of(port, 1621 struct stm32_port, port); 1622 1623 return clk_prepare_enable(stm32port->clk); 1624 } 1625 1626 static const struct dev_pm_ops stm32_serial_pm_ops = { 1627 SET_RUNTIME_PM_OPS(stm32_usart_runtime_suspend, 1628 stm32_usart_runtime_resume, NULL) 1629 SET_SYSTEM_SLEEP_PM_OPS(stm32_usart_serial_suspend, 1630 stm32_usart_serial_resume) 1631 }; 1632 1633 static struct platform_driver stm32_serial_driver = { 1634 .probe = stm32_usart_serial_probe, 1635 .remove = stm32_usart_serial_remove, 1636 .driver = { 1637 .name = DRIVER_NAME, 1638 .pm = &stm32_serial_pm_ops, 1639 .of_match_table = of_match_ptr(stm32_match), 1640 }, 1641 }; 1642 1643 static int __init stm32_usart_init(void) 1644 { 1645 static char banner[] __initdata = "STM32 USART driver initialized"; 1646 int ret; 1647 1648 pr_info("%s\n", banner); 1649 1650 ret = uart_register_driver(&stm32_usart_driver); 1651 if (ret) 1652 return ret; 1653 1654 ret = platform_driver_register(&stm32_serial_driver); 1655 if (ret) 1656 uart_unregister_driver(&stm32_usart_driver); 1657 1658 return ret; 1659 } 1660 1661 static void __exit stm32_usart_exit(void) 1662 { 1663 platform_driver_unregister(&stm32_serial_driver); 1664 uart_unregister_driver(&stm32_usart_driver); 1665 } 1666 1667 module_init(stm32_usart_init); 1668 module_exit(stm32_usart_exit); 1669 1670 MODULE_ALIAS("platform:" DRIVER_NAME); 1671 MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver"); 1672 MODULE_LICENSE("GPL v2"); 1673