1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) Maxime Coquelin 2015 4 * Copyright (C) STMicroelectronics SA 2017 5 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com> 6 * Gerald Baeza <gerald.baeza@st.com> 7 * 8 * Inspired by st-asc.c from STMicroelectronics (c) 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/console.h> 13 #include <linux/delay.h> 14 #include <linux/dma-direction.h> 15 #include <linux/dmaengine.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/io.h> 18 #include <linux/iopoll.h> 19 #include <linux/irq.h> 20 #include <linux/module.h> 21 #include <linux/of.h> 22 #include <linux/of_platform.h> 23 #include <linux/pinctrl/consumer.h> 24 #include <linux/platform_device.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/pm_wakeirq.h> 27 #include <linux/serial_core.h> 28 #include <linux/serial.h> 29 #include <linux/spinlock.h> 30 #include <linux/sysrq.h> 31 #include <linux/tty_flip.h> 32 #include <linux/tty.h> 33 34 #include "serial_mctrl_gpio.h" 35 #include "stm32-usart.h" 36 37 static void stm32_stop_tx(struct uart_port *port); 38 static void stm32_transmit_chars(struct uart_port *port); 39 40 static inline struct stm32_port *to_stm32_port(struct uart_port *port) 41 { 42 return container_of(port, struct stm32_port, port); 43 } 44 45 static void stm32_set_bits(struct uart_port *port, u32 reg, u32 bits) 46 { 47 u32 val; 48 49 val = readl_relaxed(port->membase + reg); 50 val |= bits; 51 writel_relaxed(val, port->membase + reg); 52 } 53 54 static void stm32_clr_bits(struct uart_port *port, u32 reg, u32 bits) 55 { 56 u32 val; 57 58 val = readl_relaxed(port->membase + reg); 59 val &= ~bits; 60 writel_relaxed(val, port->membase + reg); 61 } 62 63 static void stm32_config_reg_rs485(u32 *cr1, u32 *cr3, u32 delay_ADE, 64 u32 delay_DDE, u32 baud) 65 { 66 u32 rs485_deat_dedt; 67 u32 rs485_deat_dedt_max = (USART_CR1_DEAT_MASK >> USART_CR1_DEAT_SHIFT); 68 bool over8; 69 70 *cr3 |= USART_CR3_DEM; 71 over8 = *cr1 & USART_CR1_OVER8; 72 73 if (over8) 74 rs485_deat_dedt = delay_ADE * baud * 8; 75 else 76 rs485_deat_dedt = delay_ADE * baud * 16; 77 78 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000); 79 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ? 80 rs485_deat_dedt_max : rs485_deat_dedt; 81 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEAT_SHIFT) & 82 USART_CR1_DEAT_MASK; 83 *cr1 |= rs485_deat_dedt; 84 85 if (over8) 86 rs485_deat_dedt = delay_DDE * baud * 8; 87 else 88 rs485_deat_dedt = delay_DDE * baud * 16; 89 90 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000); 91 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ? 92 rs485_deat_dedt_max : rs485_deat_dedt; 93 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEDT_SHIFT) & 94 USART_CR1_DEDT_MASK; 95 *cr1 |= rs485_deat_dedt; 96 } 97 98 static int stm32_config_rs485(struct uart_port *port, 99 struct serial_rs485 *rs485conf) 100 { 101 struct stm32_port *stm32_port = to_stm32_port(port); 102 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 103 struct stm32_usart_config *cfg = &stm32_port->info->cfg; 104 u32 usartdiv, baud, cr1, cr3; 105 bool over8; 106 107 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 108 109 port->rs485 = *rs485conf; 110 111 rs485conf->flags |= SER_RS485_RX_DURING_TX; 112 113 if (rs485conf->flags & SER_RS485_ENABLED) { 114 cr1 = readl_relaxed(port->membase + ofs->cr1); 115 cr3 = readl_relaxed(port->membase + ofs->cr3); 116 usartdiv = readl_relaxed(port->membase + ofs->brr); 117 usartdiv = usartdiv & GENMASK(15, 0); 118 over8 = cr1 & USART_CR1_OVER8; 119 120 if (over8) 121 usartdiv = usartdiv | (usartdiv & GENMASK(4, 0)) 122 << USART_BRR_04_R_SHIFT; 123 124 baud = DIV_ROUND_CLOSEST(port->uartclk, usartdiv); 125 stm32_config_reg_rs485(&cr1, &cr3, 126 rs485conf->delay_rts_before_send, 127 rs485conf->delay_rts_after_send, baud); 128 129 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 130 cr3 &= ~USART_CR3_DEP; 131 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND; 132 } else { 133 cr3 |= USART_CR3_DEP; 134 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; 135 } 136 137 writel_relaxed(cr3, port->membase + ofs->cr3); 138 writel_relaxed(cr1, port->membase + ofs->cr1); 139 } else { 140 stm32_clr_bits(port, ofs->cr3, USART_CR3_DEM | USART_CR3_DEP); 141 stm32_clr_bits(port, ofs->cr1, 142 USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK); 143 } 144 145 stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 146 147 return 0; 148 } 149 150 static int stm32_init_rs485(struct uart_port *port, 151 struct platform_device *pdev) 152 { 153 struct serial_rs485 *rs485conf = &port->rs485; 154 155 rs485conf->flags = 0; 156 rs485conf->delay_rts_before_send = 0; 157 rs485conf->delay_rts_after_send = 0; 158 159 if (!pdev->dev.of_node) 160 return -ENODEV; 161 162 return uart_get_rs485_mode(port); 163 } 164 165 static int stm32_pending_rx(struct uart_port *port, u32 *sr, int *last_res, 166 bool threaded) 167 { 168 struct stm32_port *stm32_port = to_stm32_port(port); 169 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 170 enum dma_status status; 171 struct dma_tx_state state; 172 173 *sr = readl_relaxed(port->membase + ofs->isr); 174 175 if (threaded && stm32_port->rx_ch) { 176 status = dmaengine_tx_status(stm32_port->rx_ch, 177 stm32_port->rx_ch->cookie, 178 &state); 179 if ((status == DMA_IN_PROGRESS) && 180 (*last_res != state.residue)) 181 return 1; 182 else 183 return 0; 184 } else if (*sr & USART_SR_RXNE) { 185 return 1; 186 } 187 return 0; 188 } 189 190 static unsigned long stm32_get_char(struct uart_port *port, u32 *sr, 191 int *last_res) 192 { 193 struct stm32_port *stm32_port = to_stm32_port(port); 194 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 195 unsigned long c; 196 197 if (stm32_port->rx_ch) { 198 c = stm32_port->rx_buf[RX_BUF_L - (*last_res)--]; 199 if ((*last_res) == 0) 200 *last_res = RX_BUF_L; 201 } else { 202 c = readl_relaxed(port->membase + ofs->rdr); 203 /* apply RDR data mask */ 204 c &= stm32_port->rdr_mask; 205 } 206 207 return c; 208 } 209 210 static void stm32_receive_chars(struct uart_port *port, bool threaded) 211 { 212 struct tty_port *tport = &port->state->port; 213 struct stm32_port *stm32_port = to_stm32_port(port); 214 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 215 unsigned long c; 216 u32 sr; 217 char flag; 218 219 if (irqd_is_wakeup_set(irq_get_irq_data(port->irq))) 220 pm_wakeup_event(tport->tty->dev, 0); 221 222 while (stm32_pending_rx(port, &sr, &stm32_port->last_res, threaded)) { 223 sr |= USART_SR_DUMMY_RX; 224 flag = TTY_NORMAL; 225 226 /* 227 * Status bits has to be cleared before reading the RDR: 228 * In FIFO mode, reading the RDR will pop the next data 229 * (if any) along with its status bits into the SR. 230 * Not doing so leads to misalignement between RDR and SR, 231 * and clear status bits of the next rx data. 232 * 233 * Clear errors flags for stm32f7 and stm32h7 compatible 234 * devices. On stm32f4 compatible devices, the error bit is 235 * cleared by the sequence [read SR - read DR]. 236 */ 237 if ((sr & USART_SR_ERR_MASK) && ofs->icr != UNDEF_REG) 238 writel_relaxed(sr & USART_SR_ERR_MASK, 239 port->membase + ofs->icr); 240 241 c = stm32_get_char(port, &sr, &stm32_port->last_res); 242 port->icount.rx++; 243 if (sr & USART_SR_ERR_MASK) { 244 if (sr & USART_SR_ORE) { 245 port->icount.overrun++; 246 } else if (sr & USART_SR_PE) { 247 port->icount.parity++; 248 } else if (sr & USART_SR_FE) { 249 /* Break detection if character is null */ 250 if (!c) { 251 port->icount.brk++; 252 if (uart_handle_break(port)) 253 continue; 254 } else { 255 port->icount.frame++; 256 } 257 } 258 259 sr &= port->read_status_mask; 260 261 if (sr & USART_SR_PE) { 262 flag = TTY_PARITY; 263 } else if (sr & USART_SR_FE) { 264 if (!c) 265 flag = TTY_BREAK; 266 else 267 flag = TTY_FRAME; 268 } 269 } 270 271 if (uart_handle_sysrq_char(port, c)) 272 continue; 273 uart_insert_char(port, sr, USART_SR_ORE, c, flag); 274 } 275 276 spin_unlock(&port->lock); 277 tty_flip_buffer_push(tport); 278 spin_lock(&port->lock); 279 } 280 281 static void stm32_tx_dma_complete(void *arg) 282 { 283 struct uart_port *port = arg; 284 struct stm32_port *stm32port = to_stm32_port(port); 285 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 286 287 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 288 stm32port->tx_dma_busy = false; 289 290 /* Let's see if we have pending data to send */ 291 stm32_transmit_chars(port); 292 } 293 294 static void stm32_tx_interrupt_enable(struct uart_port *port) 295 { 296 struct stm32_port *stm32_port = to_stm32_port(port); 297 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 298 299 /* 300 * Enables TX FIFO threashold irq when FIFO is enabled, 301 * or TX empty irq when FIFO is disabled 302 */ 303 if (stm32_port->fifoen) 304 stm32_set_bits(port, ofs->cr3, USART_CR3_TXFTIE); 305 else 306 stm32_set_bits(port, ofs->cr1, USART_CR1_TXEIE); 307 } 308 309 static void stm32_tx_interrupt_disable(struct uart_port *port) 310 { 311 struct stm32_port *stm32_port = to_stm32_port(port); 312 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 313 314 if (stm32_port->fifoen) 315 stm32_clr_bits(port, ofs->cr3, USART_CR3_TXFTIE); 316 else 317 stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE); 318 } 319 320 static void stm32_transmit_chars_pio(struct uart_port *port) 321 { 322 struct stm32_port *stm32_port = to_stm32_port(port); 323 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 324 struct circ_buf *xmit = &port->state->xmit; 325 326 if (stm32_port->tx_dma_busy) { 327 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 328 stm32_port->tx_dma_busy = false; 329 } 330 331 while (!uart_circ_empty(xmit)) { 332 /* Check that TDR is empty before filling FIFO */ 333 if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE)) 334 break; 335 writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr); 336 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 337 port->icount.tx++; 338 } 339 340 /* rely on TXE irq (mask or unmask) for sending remaining data */ 341 if (uart_circ_empty(xmit)) 342 stm32_tx_interrupt_disable(port); 343 else 344 stm32_tx_interrupt_enable(port); 345 } 346 347 static void stm32_transmit_chars_dma(struct uart_port *port) 348 { 349 struct stm32_port *stm32port = to_stm32_port(port); 350 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 351 struct circ_buf *xmit = &port->state->xmit; 352 struct dma_async_tx_descriptor *desc = NULL; 353 dma_cookie_t cookie; 354 unsigned int count, i; 355 356 if (stm32port->tx_dma_busy) 357 return; 358 359 stm32port->tx_dma_busy = true; 360 361 count = uart_circ_chars_pending(xmit); 362 363 if (count > TX_BUF_L) 364 count = TX_BUF_L; 365 366 if (xmit->tail < xmit->head) { 367 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count); 368 } else { 369 size_t one = UART_XMIT_SIZE - xmit->tail; 370 size_t two; 371 372 if (one > count) 373 one = count; 374 two = count - one; 375 376 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one); 377 if (two) 378 memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two); 379 } 380 381 desc = dmaengine_prep_slave_single(stm32port->tx_ch, 382 stm32port->tx_dma_buf, 383 count, 384 DMA_MEM_TO_DEV, 385 DMA_PREP_INTERRUPT); 386 387 if (!desc) { 388 for (i = count; i > 0; i--) 389 stm32_transmit_chars_pio(port); 390 return; 391 } 392 393 desc->callback = stm32_tx_dma_complete; 394 desc->callback_param = port; 395 396 /* Push current DMA TX transaction in the pending queue */ 397 cookie = dmaengine_submit(desc); 398 399 /* Issue pending DMA TX requests */ 400 dma_async_issue_pending(stm32port->tx_ch); 401 402 stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT); 403 404 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); 405 port->icount.tx += count; 406 } 407 408 static void stm32_transmit_chars(struct uart_port *port) 409 { 410 struct stm32_port *stm32_port = to_stm32_port(port); 411 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 412 struct circ_buf *xmit = &port->state->xmit; 413 414 if (port->x_char) { 415 if (stm32_port->tx_dma_busy) 416 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 417 writel_relaxed(port->x_char, port->membase + ofs->tdr); 418 port->x_char = 0; 419 port->icount.tx++; 420 if (stm32_port->tx_dma_busy) 421 stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT); 422 return; 423 } 424 425 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 426 stm32_tx_interrupt_disable(port); 427 return; 428 } 429 430 if (ofs->icr == UNDEF_REG) 431 stm32_clr_bits(port, ofs->isr, USART_SR_TC); 432 else 433 writel_relaxed(USART_ICR_TCCF, port->membase + ofs->icr); 434 435 if (stm32_port->tx_ch) 436 stm32_transmit_chars_dma(port); 437 else 438 stm32_transmit_chars_pio(port); 439 440 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 441 uart_write_wakeup(port); 442 443 if (uart_circ_empty(xmit)) 444 stm32_tx_interrupt_disable(port); 445 } 446 447 static irqreturn_t stm32_interrupt(int irq, void *ptr) 448 { 449 struct uart_port *port = ptr; 450 struct stm32_port *stm32_port = to_stm32_port(port); 451 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 452 u32 sr; 453 454 spin_lock(&port->lock); 455 456 sr = readl_relaxed(port->membase + ofs->isr); 457 458 if ((sr & USART_SR_RTOF) && ofs->icr != UNDEF_REG) 459 writel_relaxed(USART_ICR_RTOCF, 460 port->membase + ofs->icr); 461 462 if ((sr & USART_SR_WUF) && (ofs->icr != UNDEF_REG)) 463 writel_relaxed(USART_ICR_WUCF, 464 port->membase + ofs->icr); 465 466 if ((sr & USART_SR_RXNE) && !(stm32_port->rx_ch)) 467 stm32_receive_chars(port, false); 468 469 if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch)) 470 stm32_transmit_chars(port); 471 472 spin_unlock(&port->lock); 473 474 if (stm32_port->rx_ch) 475 return IRQ_WAKE_THREAD; 476 else 477 return IRQ_HANDLED; 478 } 479 480 static irqreturn_t stm32_threaded_interrupt(int irq, void *ptr) 481 { 482 struct uart_port *port = ptr; 483 struct stm32_port *stm32_port = to_stm32_port(port); 484 485 spin_lock(&port->lock); 486 487 if (stm32_port->rx_ch) 488 stm32_receive_chars(port, true); 489 490 spin_unlock(&port->lock); 491 492 return IRQ_HANDLED; 493 } 494 495 static unsigned int stm32_tx_empty(struct uart_port *port) 496 { 497 struct stm32_port *stm32_port = to_stm32_port(port); 498 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 499 500 return readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE; 501 } 502 503 static void stm32_set_mctrl(struct uart_port *port, unsigned int mctrl) 504 { 505 struct stm32_port *stm32_port = to_stm32_port(port); 506 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 507 508 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) 509 stm32_set_bits(port, ofs->cr3, USART_CR3_RTSE); 510 else 511 stm32_clr_bits(port, ofs->cr3, USART_CR3_RTSE); 512 513 mctrl_gpio_set(stm32_port->gpios, mctrl); 514 } 515 516 static unsigned int stm32_get_mctrl(struct uart_port *port) 517 { 518 struct stm32_port *stm32_port = to_stm32_port(port); 519 unsigned int ret; 520 521 /* This routine is used to get signals of: DCD, DSR, RI, and CTS */ 522 ret = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; 523 524 return mctrl_gpio_get(stm32_port->gpios, &ret); 525 } 526 527 static void stm32_enable_ms(struct uart_port *port) 528 { 529 mctrl_gpio_enable_ms(to_stm32_port(port)->gpios); 530 } 531 532 static void stm32_disable_ms(struct uart_port *port) 533 { 534 mctrl_gpio_disable_ms(to_stm32_port(port)->gpios); 535 } 536 537 /* Transmit stop */ 538 static void stm32_stop_tx(struct uart_port *port) 539 { 540 stm32_tx_interrupt_disable(port); 541 } 542 543 /* There are probably characters waiting to be transmitted. */ 544 static void stm32_start_tx(struct uart_port *port) 545 { 546 struct circ_buf *xmit = &port->state->xmit; 547 548 if (uart_circ_empty(xmit)) 549 return; 550 551 stm32_transmit_chars(port); 552 } 553 554 /* Throttle the remote when input buffer is about to overflow. */ 555 static void stm32_throttle(struct uart_port *port) 556 { 557 struct stm32_port *stm32_port = to_stm32_port(port); 558 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 559 unsigned long flags; 560 561 spin_lock_irqsave(&port->lock, flags); 562 stm32_clr_bits(port, ofs->cr1, stm32_port->cr1_irq); 563 if (stm32_port->cr3_irq) 564 stm32_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); 565 566 spin_unlock_irqrestore(&port->lock, flags); 567 } 568 569 /* Unthrottle the remote, the input buffer can now accept data. */ 570 static void stm32_unthrottle(struct uart_port *port) 571 { 572 struct stm32_port *stm32_port = to_stm32_port(port); 573 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 574 unsigned long flags; 575 576 spin_lock_irqsave(&port->lock, flags); 577 stm32_set_bits(port, ofs->cr1, stm32_port->cr1_irq); 578 if (stm32_port->cr3_irq) 579 stm32_set_bits(port, ofs->cr3, stm32_port->cr3_irq); 580 581 spin_unlock_irqrestore(&port->lock, flags); 582 } 583 584 /* Receive stop */ 585 static void stm32_stop_rx(struct uart_port *port) 586 { 587 struct stm32_port *stm32_port = to_stm32_port(port); 588 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 589 590 stm32_clr_bits(port, ofs->cr1, stm32_port->cr1_irq); 591 if (stm32_port->cr3_irq) 592 stm32_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); 593 594 } 595 596 /* Handle breaks - ignored by us */ 597 static void stm32_break_ctl(struct uart_port *port, int break_state) 598 { 599 } 600 601 static int stm32_startup(struct uart_port *port) 602 { 603 struct stm32_port *stm32_port = to_stm32_port(port); 604 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 605 const char *name = to_platform_device(port->dev)->name; 606 u32 val; 607 int ret; 608 609 ret = request_threaded_irq(port->irq, stm32_interrupt, 610 stm32_threaded_interrupt, 611 IRQF_NO_SUSPEND, name, port); 612 if (ret) 613 return ret; 614 615 /* RX FIFO Flush */ 616 if (ofs->rqr != UNDEF_REG) 617 stm32_set_bits(port, ofs->rqr, USART_RQR_RXFRQ); 618 619 /* Tx and RX FIFO configuration */ 620 if (stm32_port->fifoen) { 621 val = readl_relaxed(port->membase + ofs->cr3); 622 val &= ~(USART_CR3_TXFTCFG_MASK | USART_CR3_RXFTCFG_MASK); 623 val |= USART_CR3_TXFTCFG_HALF << USART_CR3_TXFTCFG_SHIFT; 624 val |= USART_CR3_RXFTCFG_HALF << USART_CR3_RXFTCFG_SHIFT; 625 writel_relaxed(val, port->membase + ofs->cr3); 626 } 627 628 /* RX FIFO enabling */ 629 val = stm32_port->cr1_irq | USART_CR1_RE; 630 if (stm32_port->fifoen) 631 val |= USART_CR1_FIFOEN; 632 stm32_set_bits(port, ofs->cr1, val); 633 634 return 0; 635 } 636 637 static void stm32_shutdown(struct uart_port *port) 638 { 639 struct stm32_port *stm32_port = to_stm32_port(port); 640 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 641 struct stm32_usart_config *cfg = &stm32_port->info->cfg; 642 u32 val, isr; 643 int ret; 644 645 /* Disable modem control interrupts */ 646 stm32_disable_ms(port); 647 648 val = USART_CR1_TXEIE | USART_CR1_TE; 649 val |= stm32_port->cr1_irq | USART_CR1_RE; 650 val |= BIT(cfg->uart_enable_bit); 651 if (stm32_port->fifoen) 652 val |= USART_CR1_FIFOEN; 653 654 ret = readl_relaxed_poll_timeout(port->membase + ofs->isr, 655 isr, (isr & USART_SR_TC), 656 10, 100000); 657 658 if (ret) 659 dev_err(port->dev, "transmission complete not set\n"); 660 661 stm32_clr_bits(port, ofs->cr1, val); 662 663 free_irq(port->irq, port); 664 } 665 666 static unsigned int stm32_get_databits(struct ktermios *termios) 667 { 668 unsigned int bits; 669 670 tcflag_t cflag = termios->c_cflag; 671 672 switch (cflag & CSIZE) { 673 /* 674 * CSIZE settings are not necessarily supported in hardware. 675 * CSIZE unsupported configurations are handled here to set word length 676 * to 8 bits word as default configuration and to print debug message. 677 */ 678 case CS5: 679 bits = 5; 680 break; 681 case CS6: 682 bits = 6; 683 break; 684 case CS7: 685 bits = 7; 686 break; 687 /* default including CS8 */ 688 default: 689 bits = 8; 690 break; 691 } 692 693 return bits; 694 } 695 696 static void stm32_set_termios(struct uart_port *port, struct ktermios *termios, 697 struct ktermios *old) 698 { 699 struct stm32_port *stm32_port = to_stm32_port(port); 700 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 701 struct stm32_usart_config *cfg = &stm32_port->info->cfg; 702 struct serial_rs485 *rs485conf = &port->rs485; 703 unsigned int baud, bits; 704 u32 usartdiv, mantissa, fraction, oversampling; 705 tcflag_t cflag = termios->c_cflag; 706 u32 cr1, cr2, cr3; 707 unsigned long flags; 708 709 if (!stm32_port->hw_flow_control) 710 cflag &= ~CRTSCTS; 711 712 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8); 713 714 spin_lock_irqsave(&port->lock, flags); 715 716 /* Stop serial port and reset value */ 717 writel_relaxed(0, port->membase + ofs->cr1); 718 719 /* flush RX & TX FIFO */ 720 if (ofs->rqr != UNDEF_REG) 721 stm32_set_bits(port, ofs->rqr, 722 USART_RQR_TXFRQ | USART_RQR_RXFRQ); 723 724 cr1 = USART_CR1_TE | USART_CR1_RE; 725 if (stm32_port->fifoen) 726 cr1 |= USART_CR1_FIFOEN; 727 cr2 = 0; 728 cr3 = readl_relaxed(port->membase + ofs->cr3); 729 cr3 &= USART_CR3_TXFTIE | USART_CR3_RXFTCFG_MASK | USART_CR3_RXFTIE 730 | USART_CR3_TXFTCFG_MASK; 731 732 if (cflag & CSTOPB) 733 cr2 |= USART_CR2_STOP_2B; 734 735 bits = stm32_get_databits(termios); 736 stm32_port->rdr_mask = (BIT(bits) - 1); 737 738 if (cflag & PARENB) { 739 bits++; 740 cr1 |= USART_CR1_PCE; 741 } 742 743 /* 744 * Word length configuration: 745 * CS8 + parity, 9 bits word aka [M1:M0] = 0b01 746 * CS7 or (CS6 + parity), 7 bits word aka [M1:M0] = 0b10 747 * CS8 or (CS7 + parity), 8 bits word aka [M1:M0] = 0b00 748 * M0 and M1 already cleared by cr1 initialization. 749 */ 750 if (bits == 9) 751 cr1 |= USART_CR1_M0; 752 else if ((bits == 7) && cfg->has_7bits_data) 753 cr1 |= USART_CR1_M1; 754 else if (bits != 8) 755 dev_dbg(port->dev, "Unsupported data bits config: %u bits\n" 756 , bits); 757 758 if (ofs->rtor != UNDEF_REG && (stm32_port->rx_ch || 759 stm32_port->fifoen)) { 760 if (cflag & CSTOPB) 761 bits = bits + 3; /* 1 start bit + 2 stop bits */ 762 else 763 bits = bits + 2; /* 1 start bit + 1 stop bit */ 764 765 /* RX timeout irq to occur after last stop bit + bits */ 766 stm32_port->cr1_irq = USART_CR1_RTOIE; 767 writel_relaxed(bits, port->membase + ofs->rtor); 768 cr2 |= USART_CR2_RTOEN; 769 /* Not using dma, enable fifo threshold irq */ 770 if (!stm32_port->rx_ch) 771 stm32_port->cr3_irq = USART_CR3_RXFTIE; 772 } 773 774 cr1 |= stm32_port->cr1_irq; 775 cr3 |= stm32_port->cr3_irq; 776 777 if (cflag & PARODD) 778 cr1 |= USART_CR1_PS; 779 780 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); 781 if (cflag & CRTSCTS) { 782 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 783 cr3 |= USART_CR3_CTSE | USART_CR3_RTSE; 784 } 785 786 /* Handle modem control interrupts */ 787 if (UART_ENABLE_MS(port, termios->c_cflag)) 788 stm32_enable_ms(port); 789 else 790 stm32_disable_ms(port); 791 792 usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud); 793 794 /* 795 * The USART supports 16 or 8 times oversampling. 796 * By default we prefer 16 times oversampling, so that the receiver 797 * has a better tolerance to clock deviations. 798 * 8 times oversampling is only used to achieve higher speeds. 799 */ 800 if (usartdiv < 16) { 801 oversampling = 8; 802 cr1 |= USART_CR1_OVER8; 803 stm32_set_bits(port, ofs->cr1, USART_CR1_OVER8); 804 } else { 805 oversampling = 16; 806 cr1 &= ~USART_CR1_OVER8; 807 stm32_clr_bits(port, ofs->cr1, USART_CR1_OVER8); 808 } 809 810 mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT; 811 fraction = usartdiv % oversampling; 812 writel_relaxed(mantissa | fraction, port->membase + ofs->brr); 813 814 uart_update_timeout(port, cflag, baud); 815 816 port->read_status_mask = USART_SR_ORE; 817 if (termios->c_iflag & INPCK) 818 port->read_status_mask |= USART_SR_PE | USART_SR_FE; 819 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 820 port->read_status_mask |= USART_SR_FE; 821 822 /* Characters to ignore */ 823 port->ignore_status_mask = 0; 824 if (termios->c_iflag & IGNPAR) 825 port->ignore_status_mask = USART_SR_PE | USART_SR_FE; 826 if (termios->c_iflag & IGNBRK) { 827 port->ignore_status_mask |= USART_SR_FE; 828 /* 829 * If we're ignoring parity and break indicators, 830 * ignore overruns too (for real raw support). 831 */ 832 if (termios->c_iflag & IGNPAR) 833 port->ignore_status_mask |= USART_SR_ORE; 834 } 835 836 /* Ignore all characters if CREAD is not set */ 837 if ((termios->c_cflag & CREAD) == 0) 838 port->ignore_status_mask |= USART_SR_DUMMY_RX; 839 840 if (stm32_port->rx_ch) 841 cr3 |= USART_CR3_DMAR; 842 843 if (rs485conf->flags & SER_RS485_ENABLED) { 844 stm32_config_reg_rs485(&cr1, &cr3, 845 rs485conf->delay_rts_before_send, 846 rs485conf->delay_rts_after_send, baud); 847 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 848 cr3 &= ~USART_CR3_DEP; 849 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND; 850 } else { 851 cr3 |= USART_CR3_DEP; 852 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; 853 } 854 855 } else { 856 cr3 &= ~(USART_CR3_DEM | USART_CR3_DEP); 857 cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK); 858 } 859 860 writel_relaxed(cr3, port->membase + ofs->cr3); 861 writel_relaxed(cr2, port->membase + ofs->cr2); 862 writel_relaxed(cr1, port->membase + ofs->cr1); 863 864 stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 865 spin_unlock_irqrestore(&port->lock, flags); 866 } 867 868 static const char *stm32_type(struct uart_port *port) 869 { 870 return (port->type == PORT_STM32) ? DRIVER_NAME : NULL; 871 } 872 873 static void stm32_release_port(struct uart_port *port) 874 { 875 } 876 877 static int stm32_request_port(struct uart_port *port) 878 { 879 return 0; 880 } 881 882 static void stm32_config_port(struct uart_port *port, int flags) 883 { 884 if (flags & UART_CONFIG_TYPE) 885 port->type = PORT_STM32; 886 } 887 888 static int 889 stm32_verify_port(struct uart_port *port, struct serial_struct *ser) 890 { 891 /* No user changeable parameters */ 892 return -EINVAL; 893 } 894 895 static void stm32_pm(struct uart_port *port, unsigned int state, 896 unsigned int oldstate) 897 { 898 struct stm32_port *stm32port = container_of(port, 899 struct stm32_port, port); 900 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 901 struct stm32_usart_config *cfg = &stm32port->info->cfg; 902 unsigned long flags = 0; 903 904 switch (state) { 905 case UART_PM_STATE_ON: 906 pm_runtime_get_sync(port->dev); 907 break; 908 case UART_PM_STATE_OFF: 909 spin_lock_irqsave(&port->lock, flags); 910 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 911 spin_unlock_irqrestore(&port->lock, flags); 912 pm_runtime_put_sync(port->dev); 913 break; 914 } 915 } 916 917 static const struct uart_ops stm32_uart_ops = { 918 .tx_empty = stm32_tx_empty, 919 .set_mctrl = stm32_set_mctrl, 920 .get_mctrl = stm32_get_mctrl, 921 .stop_tx = stm32_stop_tx, 922 .start_tx = stm32_start_tx, 923 .throttle = stm32_throttle, 924 .unthrottle = stm32_unthrottle, 925 .stop_rx = stm32_stop_rx, 926 .enable_ms = stm32_enable_ms, 927 .break_ctl = stm32_break_ctl, 928 .startup = stm32_startup, 929 .shutdown = stm32_shutdown, 930 .set_termios = stm32_set_termios, 931 .pm = stm32_pm, 932 .type = stm32_type, 933 .release_port = stm32_release_port, 934 .request_port = stm32_request_port, 935 .config_port = stm32_config_port, 936 .verify_port = stm32_verify_port, 937 }; 938 939 static int stm32_init_port(struct stm32_port *stm32port, 940 struct platform_device *pdev) 941 { 942 struct uart_port *port = &stm32port->port; 943 struct resource *res; 944 int ret; 945 946 port->iotype = UPIO_MEM; 947 port->flags = UPF_BOOT_AUTOCONF; 948 port->ops = &stm32_uart_ops; 949 port->dev = &pdev->dev; 950 port->fifosize = stm32port->info->cfg.fifosize; 951 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_STM32_CONSOLE); 952 953 ret = platform_get_irq(pdev, 0); 954 if (ret <= 0) 955 return ret ? : -ENODEV; 956 port->irq = ret; 957 958 port->rs485_config = stm32_config_rs485; 959 960 ret = stm32_init_rs485(port, pdev); 961 if (ret) 962 return ret; 963 964 if (stm32port->info->cfg.has_wakeup) { 965 stm32port->wakeirq = platform_get_irq(pdev, 1); 966 if (stm32port->wakeirq <= 0 && stm32port->wakeirq != -ENXIO) 967 return stm32port->wakeirq ? : -ENODEV; 968 } 969 970 stm32port->fifoen = stm32port->info->cfg.has_fifo; 971 972 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 973 port->membase = devm_ioremap_resource(&pdev->dev, res); 974 if (IS_ERR(port->membase)) 975 return PTR_ERR(port->membase); 976 port->mapbase = res->start; 977 978 spin_lock_init(&port->lock); 979 980 stm32port->clk = devm_clk_get(&pdev->dev, NULL); 981 if (IS_ERR(stm32port->clk)) 982 return PTR_ERR(stm32port->clk); 983 984 /* Ensure that clk rate is correct by enabling the clk */ 985 ret = clk_prepare_enable(stm32port->clk); 986 if (ret) 987 return ret; 988 989 stm32port->port.uartclk = clk_get_rate(stm32port->clk); 990 if (!stm32port->port.uartclk) { 991 ret = -EINVAL; 992 goto err_clk; 993 } 994 995 stm32port->gpios = mctrl_gpio_init(&stm32port->port, 0); 996 if (IS_ERR(stm32port->gpios)) { 997 ret = PTR_ERR(stm32port->gpios); 998 goto err_clk; 999 } 1000 1001 /* Both CTS/RTS gpios and "st,hw-flow-ctrl" should not be specified */ 1002 if (stm32port->hw_flow_control) { 1003 if (mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_CTS) || 1004 mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_RTS)) { 1005 dev_err(&pdev->dev, "Conflicting RTS/CTS config\n"); 1006 ret = -EINVAL; 1007 goto err_clk; 1008 } 1009 } 1010 1011 return ret; 1012 1013 err_clk: 1014 clk_disable_unprepare(stm32port->clk); 1015 1016 return ret; 1017 } 1018 1019 static struct stm32_port *stm32_of_get_stm32_port(struct platform_device *pdev) 1020 { 1021 struct device_node *np = pdev->dev.of_node; 1022 int id; 1023 1024 if (!np) 1025 return NULL; 1026 1027 id = of_alias_get_id(np, "serial"); 1028 if (id < 0) { 1029 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", id); 1030 return NULL; 1031 } 1032 1033 if (WARN_ON(id >= STM32_MAX_PORTS)) 1034 return NULL; 1035 1036 stm32_ports[id].hw_flow_control = of_property_read_bool(np, 1037 "st,hw-flow-ctrl"); 1038 stm32_ports[id].port.line = id; 1039 stm32_ports[id].cr1_irq = USART_CR1_RXNEIE; 1040 stm32_ports[id].cr3_irq = 0; 1041 stm32_ports[id].last_res = RX_BUF_L; 1042 return &stm32_ports[id]; 1043 } 1044 1045 #ifdef CONFIG_OF 1046 static const struct of_device_id stm32_match[] = { 1047 { .compatible = "st,stm32-uart", .data = &stm32f4_info}, 1048 { .compatible = "st,stm32f7-uart", .data = &stm32f7_info}, 1049 { .compatible = "st,stm32h7-uart", .data = &stm32h7_info}, 1050 {}, 1051 }; 1052 1053 MODULE_DEVICE_TABLE(of, stm32_match); 1054 #endif 1055 1056 static int stm32_of_dma_rx_probe(struct stm32_port *stm32port, 1057 struct platform_device *pdev) 1058 { 1059 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 1060 struct uart_port *port = &stm32port->port; 1061 struct device *dev = &pdev->dev; 1062 struct dma_slave_config config; 1063 struct dma_async_tx_descriptor *desc = NULL; 1064 dma_cookie_t cookie; 1065 int ret; 1066 1067 /* Request DMA RX channel */ 1068 stm32port->rx_ch = dma_request_slave_channel(dev, "rx"); 1069 if (!stm32port->rx_ch) { 1070 dev_info(dev, "rx dma alloc failed\n"); 1071 return -ENODEV; 1072 } 1073 stm32port->rx_buf = dma_alloc_coherent(&pdev->dev, RX_BUF_L, 1074 &stm32port->rx_dma_buf, 1075 GFP_KERNEL); 1076 if (!stm32port->rx_buf) { 1077 ret = -ENOMEM; 1078 goto alloc_err; 1079 } 1080 1081 /* Configure DMA channel */ 1082 memset(&config, 0, sizeof(config)); 1083 config.src_addr = port->mapbase + ofs->rdr; 1084 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1085 1086 ret = dmaengine_slave_config(stm32port->rx_ch, &config); 1087 if (ret < 0) { 1088 dev_err(dev, "rx dma channel config failed\n"); 1089 ret = -ENODEV; 1090 goto config_err; 1091 } 1092 1093 /* Prepare a DMA cyclic transaction */ 1094 desc = dmaengine_prep_dma_cyclic(stm32port->rx_ch, 1095 stm32port->rx_dma_buf, 1096 RX_BUF_L, RX_BUF_P, DMA_DEV_TO_MEM, 1097 DMA_PREP_INTERRUPT); 1098 if (!desc) { 1099 dev_err(dev, "rx dma prep cyclic failed\n"); 1100 ret = -ENODEV; 1101 goto config_err; 1102 } 1103 1104 /* No callback as dma buffer is drained on usart interrupt */ 1105 desc->callback = NULL; 1106 desc->callback_param = NULL; 1107 1108 /* Push current DMA transaction in the pending queue */ 1109 cookie = dmaengine_submit(desc); 1110 1111 /* Issue pending DMA requests */ 1112 dma_async_issue_pending(stm32port->rx_ch); 1113 1114 return 0; 1115 1116 config_err: 1117 dma_free_coherent(&pdev->dev, 1118 RX_BUF_L, stm32port->rx_buf, 1119 stm32port->rx_dma_buf); 1120 1121 alloc_err: 1122 dma_release_channel(stm32port->rx_ch); 1123 stm32port->rx_ch = NULL; 1124 1125 return ret; 1126 } 1127 1128 static int stm32_of_dma_tx_probe(struct stm32_port *stm32port, 1129 struct platform_device *pdev) 1130 { 1131 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 1132 struct uart_port *port = &stm32port->port; 1133 struct device *dev = &pdev->dev; 1134 struct dma_slave_config config; 1135 int ret; 1136 1137 stm32port->tx_dma_busy = false; 1138 1139 /* Request DMA TX channel */ 1140 stm32port->tx_ch = dma_request_slave_channel(dev, "tx"); 1141 if (!stm32port->tx_ch) { 1142 dev_info(dev, "tx dma alloc failed\n"); 1143 return -ENODEV; 1144 } 1145 stm32port->tx_buf = dma_alloc_coherent(&pdev->dev, TX_BUF_L, 1146 &stm32port->tx_dma_buf, 1147 GFP_KERNEL); 1148 if (!stm32port->tx_buf) { 1149 ret = -ENOMEM; 1150 goto alloc_err; 1151 } 1152 1153 /* Configure DMA channel */ 1154 memset(&config, 0, sizeof(config)); 1155 config.dst_addr = port->mapbase + ofs->tdr; 1156 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1157 1158 ret = dmaengine_slave_config(stm32port->tx_ch, &config); 1159 if (ret < 0) { 1160 dev_err(dev, "tx dma channel config failed\n"); 1161 ret = -ENODEV; 1162 goto config_err; 1163 } 1164 1165 return 0; 1166 1167 config_err: 1168 dma_free_coherent(&pdev->dev, 1169 TX_BUF_L, stm32port->tx_buf, 1170 stm32port->tx_dma_buf); 1171 1172 alloc_err: 1173 dma_release_channel(stm32port->tx_ch); 1174 stm32port->tx_ch = NULL; 1175 1176 return ret; 1177 } 1178 1179 static int stm32_serial_probe(struct platform_device *pdev) 1180 { 1181 const struct of_device_id *match; 1182 struct stm32_port *stm32port; 1183 int ret; 1184 1185 stm32port = stm32_of_get_stm32_port(pdev); 1186 if (!stm32port) 1187 return -ENODEV; 1188 1189 match = of_match_device(stm32_match, &pdev->dev); 1190 if (match && match->data) 1191 stm32port->info = (struct stm32_usart_info *)match->data; 1192 else 1193 return -EINVAL; 1194 1195 ret = stm32_init_port(stm32port, pdev); 1196 if (ret) 1197 return ret; 1198 1199 if (stm32port->wakeirq > 0) { 1200 ret = device_init_wakeup(&pdev->dev, true); 1201 if (ret) 1202 goto err_uninit; 1203 1204 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev, 1205 stm32port->wakeirq); 1206 if (ret) 1207 goto err_nowup; 1208 1209 device_set_wakeup_enable(&pdev->dev, false); 1210 } 1211 1212 ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port); 1213 if (ret) 1214 goto err_wirq; 1215 1216 ret = stm32_of_dma_rx_probe(stm32port, pdev); 1217 if (ret) 1218 dev_info(&pdev->dev, "interrupt mode used for rx (no dma)\n"); 1219 1220 ret = stm32_of_dma_tx_probe(stm32port, pdev); 1221 if (ret) 1222 dev_info(&pdev->dev, "interrupt mode used for tx (no dma)\n"); 1223 1224 platform_set_drvdata(pdev, &stm32port->port); 1225 1226 pm_runtime_get_noresume(&pdev->dev); 1227 pm_runtime_set_active(&pdev->dev); 1228 pm_runtime_enable(&pdev->dev); 1229 pm_runtime_put_sync(&pdev->dev); 1230 1231 return 0; 1232 1233 err_wirq: 1234 if (stm32port->wakeirq > 0) 1235 dev_pm_clear_wake_irq(&pdev->dev); 1236 1237 err_nowup: 1238 if (stm32port->wakeirq > 0) 1239 device_init_wakeup(&pdev->dev, false); 1240 1241 err_uninit: 1242 clk_disable_unprepare(stm32port->clk); 1243 1244 return ret; 1245 } 1246 1247 static int stm32_serial_remove(struct platform_device *pdev) 1248 { 1249 struct uart_port *port = platform_get_drvdata(pdev); 1250 struct stm32_port *stm32_port = to_stm32_port(port); 1251 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1252 int err; 1253 1254 pm_runtime_get_sync(&pdev->dev); 1255 1256 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAR); 1257 1258 if (stm32_port->rx_ch) 1259 dma_release_channel(stm32_port->rx_ch); 1260 1261 if (stm32_port->rx_dma_buf) 1262 dma_free_coherent(&pdev->dev, 1263 RX_BUF_L, stm32_port->rx_buf, 1264 stm32_port->rx_dma_buf); 1265 1266 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 1267 1268 if (stm32_port->tx_ch) 1269 dma_release_channel(stm32_port->tx_ch); 1270 1271 if (stm32_port->tx_dma_buf) 1272 dma_free_coherent(&pdev->dev, 1273 TX_BUF_L, stm32_port->tx_buf, 1274 stm32_port->tx_dma_buf); 1275 1276 if (stm32_port->wakeirq > 0) { 1277 dev_pm_clear_wake_irq(&pdev->dev); 1278 device_init_wakeup(&pdev->dev, false); 1279 } 1280 1281 clk_disable_unprepare(stm32_port->clk); 1282 1283 err = uart_remove_one_port(&stm32_usart_driver, port); 1284 1285 pm_runtime_disable(&pdev->dev); 1286 pm_runtime_put_noidle(&pdev->dev); 1287 1288 return err; 1289 } 1290 1291 1292 #ifdef CONFIG_SERIAL_STM32_CONSOLE 1293 static void stm32_console_putchar(struct uart_port *port, int ch) 1294 { 1295 struct stm32_port *stm32_port = to_stm32_port(port); 1296 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1297 1298 while (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE)) 1299 cpu_relax(); 1300 1301 writel_relaxed(ch, port->membase + ofs->tdr); 1302 } 1303 1304 static void stm32_console_write(struct console *co, const char *s, unsigned cnt) 1305 { 1306 struct uart_port *port = &stm32_ports[co->index].port; 1307 struct stm32_port *stm32_port = to_stm32_port(port); 1308 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1309 struct stm32_usart_config *cfg = &stm32_port->info->cfg; 1310 unsigned long flags; 1311 u32 old_cr1, new_cr1; 1312 int locked = 1; 1313 1314 local_irq_save(flags); 1315 if (port->sysrq) 1316 locked = 0; 1317 else if (oops_in_progress) 1318 locked = spin_trylock(&port->lock); 1319 else 1320 spin_lock(&port->lock); 1321 1322 /* Save and disable interrupts, enable the transmitter */ 1323 old_cr1 = readl_relaxed(port->membase + ofs->cr1); 1324 new_cr1 = old_cr1 & ~USART_CR1_IE_MASK; 1325 new_cr1 |= USART_CR1_TE | BIT(cfg->uart_enable_bit); 1326 writel_relaxed(new_cr1, port->membase + ofs->cr1); 1327 1328 uart_console_write(port, s, cnt, stm32_console_putchar); 1329 1330 /* Restore interrupt state */ 1331 writel_relaxed(old_cr1, port->membase + ofs->cr1); 1332 1333 if (locked) 1334 spin_unlock(&port->lock); 1335 local_irq_restore(flags); 1336 } 1337 1338 static int stm32_console_setup(struct console *co, char *options) 1339 { 1340 struct stm32_port *stm32port; 1341 int baud = 9600; 1342 int bits = 8; 1343 int parity = 'n'; 1344 int flow = 'n'; 1345 1346 if (co->index >= STM32_MAX_PORTS) 1347 return -ENODEV; 1348 1349 stm32port = &stm32_ports[co->index]; 1350 1351 /* 1352 * This driver does not support early console initialization 1353 * (use ARM early printk support instead), so we only expect 1354 * this to be called during the uart port registration when the 1355 * driver gets probed and the port should be mapped at that point. 1356 */ 1357 if (stm32port->port.mapbase == 0 || stm32port->port.membase == NULL) 1358 return -ENXIO; 1359 1360 if (options) 1361 uart_parse_options(options, &baud, &parity, &bits, &flow); 1362 1363 return uart_set_options(&stm32port->port, co, baud, parity, bits, flow); 1364 } 1365 1366 static struct console stm32_console = { 1367 .name = STM32_SERIAL_NAME, 1368 .device = uart_console_device, 1369 .write = stm32_console_write, 1370 .setup = stm32_console_setup, 1371 .flags = CON_PRINTBUFFER, 1372 .index = -1, 1373 .data = &stm32_usart_driver, 1374 }; 1375 1376 #define STM32_SERIAL_CONSOLE (&stm32_console) 1377 1378 #else 1379 #define STM32_SERIAL_CONSOLE NULL 1380 #endif /* CONFIG_SERIAL_STM32_CONSOLE */ 1381 1382 static struct uart_driver stm32_usart_driver = { 1383 .driver_name = DRIVER_NAME, 1384 .dev_name = STM32_SERIAL_NAME, 1385 .major = 0, 1386 .minor = 0, 1387 .nr = STM32_MAX_PORTS, 1388 .cons = STM32_SERIAL_CONSOLE, 1389 }; 1390 1391 static void __maybe_unused stm32_serial_enable_wakeup(struct uart_port *port, 1392 bool enable) 1393 { 1394 struct stm32_port *stm32_port = to_stm32_port(port); 1395 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1396 struct stm32_usart_config *cfg = &stm32_port->info->cfg; 1397 u32 val; 1398 1399 if (stm32_port->wakeirq <= 0) 1400 return; 1401 1402 if (enable) { 1403 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 1404 stm32_set_bits(port, ofs->cr1, USART_CR1_UESM); 1405 val = readl_relaxed(port->membase + ofs->cr3); 1406 val &= ~USART_CR3_WUS_MASK; 1407 /* Enable Wake up interrupt from low power on start bit */ 1408 val |= USART_CR3_WUS_START_BIT | USART_CR3_WUFIE; 1409 writel_relaxed(val, port->membase + ofs->cr3); 1410 stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 1411 } else { 1412 stm32_clr_bits(port, ofs->cr1, USART_CR1_UESM); 1413 } 1414 } 1415 1416 static int __maybe_unused stm32_serial_suspend(struct device *dev) 1417 { 1418 struct uart_port *port = dev_get_drvdata(dev); 1419 1420 uart_suspend_port(&stm32_usart_driver, port); 1421 1422 if (device_may_wakeup(dev)) 1423 stm32_serial_enable_wakeup(port, true); 1424 else 1425 stm32_serial_enable_wakeup(port, false); 1426 1427 /* 1428 * When "no_console_suspend" is enabled, keep the pinctrl default state 1429 * and rely on bootloader stage to restore this state upon resume. 1430 * Otherwise, apply the idle or sleep states depending on wakeup 1431 * capabilities. 1432 */ 1433 if (console_suspend_enabled || !uart_console(port)) { 1434 if (device_may_wakeup(dev)) 1435 pinctrl_pm_select_idle_state(dev); 1436 else 1437 pinctrl_pm_select_sleep_state(dev); 1438 } 1439 1440 return 0; 1441 } 1442 1443 static int __maybe_unused stm32_serial_resume(struct device *dev) 1444 { 1445 struct uart_port *port = dev_get_drvdata(dev); 1446 1447 pinctrl_pm_select_default_state(dev); 1448 1449 if (device_may_wakeup(dev)) 1450 stm32_serial_enable_wakeup(port, false); 1451 1452 return uart_resume_port(&stm32_usart_driver, port); 1453 } 1454 1455 static int __maybe_unused stm32_serial_runtime_suspend(struct device *dev) 1456 { 1457 struct uart_port *port = dev_get_drvdata(dev); 1458 struct stm32_port *stm32port = container_of(port, 1459 struct stm32_port, port); 1460 1461 clk_disable_unprepare(stm32port->clk); 1462 1463 return 0; 1464 } 1465 1466 static int __maybe_unused stm32_serial_runtime_resume(struct device *dev) 1467 { 1468 struct uart_port *port = dev_get_drvdata(dev); 1469 struct stm32_port *stm32port = container_of(port, 1470 struct stm32_port, port); 1471 1472 return clk_prepare_enable(stm32port->clk); 1473 } 1474 1475 static const struct dev_pm_ops stm32_serial_pm_ops = { 1476 SET_RUNTIME_PM_OPS(stm32_serial_runtime_suspend, 1477 stm32_serial_runtime_resume, NULL) 1478 SET_SYSTEM_SLEEP_PM_OPS(stm32_serial_suspend, stm32_serial_resume) 1479 }; 1480 1481 static struct platform_driver stm32_serial_driver = { 1482 .probe = stm32_serial_probe, 1483 .remove = stm32_serial_remove, 1484 .driver = { 1485 .name = DRIVER_NAME, 1486 .pm = &stm32_serial_pm_ops, 1487 .of_match_table = of_match_ptr(stm32_match), 1488 }, 1489 }; 1490 1491 static int __init usart_init(void) 1492 { 1493 static char banner[] __initdata = "STM32 USART driver initialized"; 1494 int ret; 1495 1496 pr_info("%s\n", banner); 1497 1498 ret = uart_register_driver(&stm32_usart_driver); 1499 if (ret) 1500 return ret; 1501 1502 ret = platform_driver_register(&stm32_serial_driver); 1503 if (ret) 1504 uart_unregister_driver(&stm32_usart_driver); 1505 1506 return ret; 1507 } 1508 1509 static void __exit usart_exit(void) 1510 { 1511 platform_driver_unregister(&stm32_serial_driver); 1512 uart_unregister_driver(&stm32_usart_driver); 1513 } 1514 1515 module_init(usart_init); 1516 module_exit(usart_exit); 1517 1518 MODULE_ALIAS("platform:" DRIVER_NAME); 1519 MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver"); 1520 MODULE_LICENSE("GPL v2"); 1521