xref: /openbmc/linux/drivers/tty/serial/sh-sci.h (revision 82003e04)
1 #include <linux/bitops.h>
2 #include <linux/serial_core.h>
3 #include <linux/io.h>
4 #include <linux/gpio.h>
5 
6 #define SCI_MAJOR		204
7 #define SCI_MINOR_START		8
8 
9 
10 /*
11  * SCI register subset common for all port types.
12  * Not all registers will exist on all parts.
13  */
14 enum {
15 	SCSMR,				/* Serial Mode Register */
16 	SCBRR,				/* Bit Rate Register */
17 	SCSCR,				/* Serial Control Register */
18 	SCxSR,				/* Serial Status Register */
19 	SCFCR,				/* FIFO Control Register */
20 	SCFDR,				/* FIFO Data Count Register */
21 	SCxTDR,				/* Transmit (FIFO) Data Register */
22 	SCxRDR,				/* Receive (FIFO) Data Register */
23 	SCLSR,				/* Line Status Register */
24 	SCTFDR,				/* Transmit FIFO Data Count Register */
25 	SCRFDR,				/* Receive FIFO Data Count Register */
26 	SCSPTR,				/* Serial Port Register */
27 	HSSRR,				/* Sampling Rate Register */
28 	SCPCR,				/* Serial Port Control Register */
29 	SCPDR,				/* Serial Port Data Register */
30 	SCDL,				/* BRG Frequency Division Register */
31 	SCCKS,				/* BRG Clock Select Register */
32 
33 	SCIx_NR_REGS,
34 };
35 
36 
37 /* SCSMR (Serial Mode Register) */
38 #define SCSMR_C_A	BIT(7)	/* Communication Mode */
39 #define SCSMR_CSYNC	BIT(7)	/*   - Clocked synchronous mode */
40 #define SCSMR_ASYNC	0	/*   - Asynchronous mode */
41 #define SCSMR_CHR	BIT(6)	/* 7-bit Character Length */
42 #define SCSMR_PE	BIT(5)	/* Parity Enable */
43 #define SCSMR_ODD	BIT(4)	/* Odd Parity */
44 #define SCSMR_STOP	BIT(3)	/* Stop Bit Length */
45 #define SCSMR_CKS	0x0003	/* Clock Select */
46 
47 /* Serial Mode Register, SCIFA/SCIFB only bits */
48 #define SCSMR_CKEDG	BIT(12)	/* Transmit/Receive Clock Edge Select */
49 #define SCSMR_SRC_MASK	0x0700	/* Sampling Control */
50 #define SCSMR_SRC_16	0x0000	/* Sampling rate 1/16 */
51 #define SCSMR_SRC_5	0x0100	/* Sampling rate 1/5 */
52 #define SCSMR_SRC_7	0x0200	/* Sampling rate 1/7 */
53 #define SCSMR_SRC_11	0x0300	/* Sampling rate 1/11 */
54 #define SCSMR_SRC_13	0x0400	/* Sampling rate 1/13 */
55 #define SCSMR_SRC_17	0x0500	/* Sampling rate 1/17 */
56 #define SCSMR_SRC_19	0x0600	/* Sampling rate 1/19 */
57 #define SCSMR_SRC_27	0x0700	/* Sampling rate 1/27 */
58 
59 /* Serial Control Register, SCIFA/SCIFB only bits */
60 #define SCSCR_TDRQE	BIT(15)	/* Tx Data Transfer Request Enable */
61 #define SCSCR_RDRQE	BIT(14)	/* Rx Data Transfer Request Enable */
62 
63 /* SCxSR (Serial Status Register) on SCI */
64 #define SCI_TDRE	BIT(7)	/* Transmit Data Register Empty */
65 #define SCI_RDRF	BIT(6)	/* Receive Data Register Full */
66 #define SCI_ORER	BIT(5)	/* Overrun Error */
67 #define SCI_FER		BIT(4)	/* Framing Error */
68 #define SCI_PER		BIT(3)	/* Parity Error */
69 #define SCI_TEND	BIT(2)	/* Transmit End */
70 #define SCI_RESERVED	0x03	/* All reserved bits */
71 
72 #define SCI_DEFAULT_ERROR_MASK (SCI_PER | SCI_FER)
73 
74 #define SCI_RDxF_CLEAR	(u32)(~(SCI_RESERVED | SCI_RDRF))
75 #define SCI_ERROR_CLEAR	(u32)(~(SCI_RESERVED | SCI_PER | SCI_FER | SCI_ORER))
76 #define SCI_TDxE_CLEAR	(u32)(~(SCI_RESERVED | SCI_TEND | SCI_TDRE))
77 #define SCI_BREAK_CLEAR	(u32)(~(SCI_RESERVED | SCI_PER | SCI_FER | SCI_ORER))
78 
79 /* SCxSR (Serial Status Register) on SCIF, SCIFA, SCIFB, HSCIF */
80 #define SCIF_ER		BIT(7)	/* Receive Error */
81 #define SCIF_TEND	BIT(6)	/* Transmission End */
82 #define SCIF_TDFE	BIT(5)	/* Transmit FIFO Data Empty */
83 #define SCIF_BRK	BIT(4)	/* Break Detect */
84 #define SCIF_FER	BIT(3)	/* Framing Error */
85 #define SCIF_PER	BIT(2)	/* Parity Error */
86 #define SCIF_RDF	BIT(1)	/* Receive FIFO Data Full */
87 #define SCIF_DR		BIT(0)	/* Receive Data Ready */
88 /* SCIF only (optional) */
89 #define SCIF_PERC	0xf000	/* Number of Parity Errors */
90 #define SCIF_FERC	0x0f00	/* Number of Framing Errors */
91 /*SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 only */
92 #define SCIFA_ORER	BIT(9)	/* Overrun Error */
93 
94 #define SCIF_DEFAULT_ERROR_MASK (SCIF_PER | SCIF_FER | SCIF_BRK | SCIF_ER)
95 
96 #define SCIF_RDxF_CLEAR		(u32)(~(SCIF_DR | SCIF_RDF))
97 #define SCIF_ERROR_CLEAR	(u32)(~(SCIF_PER | SCIF_FER | SCIF_ER))
98 #define SCIF_TDxE_CLEAR		(u32)(~(SCIF_TDFE))
99 #define SCIF_BREAK_CLEAR	(u32)(~(SCIF_PER | SCIF_FER | SCIF_BRK))
100 
101 /* SCFCR (FIFO Control Register) */
102 #define SCFCR_MCE	BIT(3)	/* Modem Control Enable */
103 #define SCFCR_TFRST	BIT(2)	/* Transmit FIFO Data Register Reset */
104 #define SCFCR_RFRST	BIT(1)	/* Receive FIFO Data Register Reset */
105 #define SCFCR_LOOP	BIT(0)	/* Loopback Test */
106 
107 /* SCLSR (Line Status Register) on (H)SCIF */
108 #define SCLSR_TO	BIT(2)	/* Timeout */
109 #define SCLSR_ORER	BIT(0)	/* Overrun Error */
110 
111 /* SCSPTR (Serial Port Register), optional */
112 #define SCSPTR_RTSIO	BIT(7)	/* Serial Port RTS# Pin Input/Output */
113 #define SCSPTR_RTSDT	BIT(6)	/* Serial Port RTS# Pin Data */
114 #define SCSPTR_CTSIO	BIT(5)	/* Serial Port CTS# Pin Input/Output */
115 #define SCSPTR_CTSDT	BIT(4)	/* Serial Port CTS# Pin Data */
116 #define SCSPTR_SCKIO	BIT(3)	/* Serial Port Clock Pin Input/Output */
117 #define SCSPTR_SCKDT	BIT(2)	/* Serial Port Clock Pin Data */
118 #define SCSPTR_SPB2IO	BIT(1)	/* Serial Port Break Input/Output */
119 #define SCSPTR_SPB2DT	BIT(0)	/* Serial Port Break Data */
120 
121 /* HSSRR HSCIF */
122 #define HSCIF_SRE	BIT(15)	/* Sampling Rate Register Enable */
123 
124 /* SCPCR (Serial Port Control Register), SCIFA/SCIFB only */
125 #define SCPCR_RTSC	BIT(4)	/* Serial Port RTS# Pin / Output Pin */
126 #define SCPCR_CTSC	BIT(3)	/* Serial Port CTS# Pin / Input Pin */
127 #define SCPCR_SCKC	BIT(2)	/* Serial Port SCK Pin / Output Pin */
128 #define SCPCR_RXDC	BIT(1)	/* Serial Port RXD Pin / Input Pin */
129 #define SCPCR_TXDC	BIT(0)	/* Serial Port TXD Pin / Output Pin */
130 
131 /* SCPDR (Serial Port Data Register), SCIFA/SCIFB only */
132 #define SCPDR_RTSD	BIT(4)	/* Serial Port RTS# Output Pin Data */
133 #define SCPDR_CTSD	BIT(3)	/* Serial Port CTS# Input Pin Data */
134 #define SCPDR_SCKD	BIT(2)	/* Serial Port SCK Output Pin Data */
135 #define SCPDR_RXDD	BIT(1)	/* Serial Port RXD Input Pin Data */
136 #define SCPDR_TXDD	BIT(0)	/* Serial Port TXD Output Pin Data */
137 
138 /*
139  * BRG Clock Select Register (Some SCIF and HSCIF)
140  * The Baud Rate Generator for external clock can provide a clock source for
141  * the sampling clock. It outputs either its frequency divided clock, or the
142  * (undivided) (H)SCK external clock.
143  */
144 #define SCCKS_CKS	BIT(15)	/* Select (H)SCK (1) or divided SC_CLK (0) */
145 #define SCCKS_XIN	BIT(14)	/* SC_CLK uses bus clock (1) or SCIF_CLK (0) */
146 
147 #define SCxSR_TEND(port)	(((port)->type == PORT_SCI) ? SCI_TEND   : SCIF_TEND)
148 #define SCxSR_RDxF(port)	(((port)->type == PORT_SCI) ? SCI_RDRF   : SCIF_RDF)
149 #define SCxSR_TDxE(port)	(((port)->type == PORT_SCI) ? SCI_TDRE   : SCIF_TDFE)
150 #define SCxSR_FER(port)		(((port)->type == PORT_SCI) ? SCI_FER    : SCIF_FER)
151 #define SCxSR_PER(port)		(((port)->type == PORT_SCI) ? SCI_PER    : SCIF_PER)
152 #define SCxSR_BRK(port)		(((port)->type == PORT_SCI) ? 0x00       : SCIF_BRK)
153 
154 #define SCxSR_ERRORS(port)	(to_sci_port(port)->error_mask)
155 
156 #define SCxSR_RDxF_CLEAR(port) \
157 	(((port)->type == PORT_SCI) ? SCI_RDxF_CLEAR : SCIF_RDxF_CLEAR)
158 #define SCxSR_ERROR_CLEAR(port) \
159 	(to_sci_port(port)->error_clear)
160 #define SCxSR_TDxE_CLEAR(port) \
161 	(((port)->type == PORT_SCI) ? SCI_TDxE_CLEAR : SCIF_TDxE_CLEAR)
162 #define SCxSR_BREAK_CLEAR(port) \
163 	(((port)->type == PORT_SCI) ? SCI_BREAK_CLEAR : SCIF_BREAK_CLEAR)
164