1 #include <linux/serial_core.h> 2 #include <linux/io.h> 3 #include <linux/gpio.h> 4 5 #if defined(CONFIG_H83007) || defined(CONFIG_H83068) 6 #include <asm/regs306x.h> 7 #endif 8 #if defined(CONFIG_H8S2678) 9 #include <asm/regs267x.h> 10 #endif 11 12 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ 13 defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 14 defined(CONFIG_CPU_SUBTYPE_SH7708) || \ 15 defined(CONFIG_CPU_SUBTYPE_SH7709) 16 # define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */ 17 # define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */ 18 #elif defined(CONFIG_CPU_SUBTYPE_SH7705) 19 # define SCIF0 0xA4400000 20 # define SCIF2 0xA4410000 21 # define SCPCR 0xA4000116 22 # define SCPDR 0xA4000136 23 #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 24 defined(CONFIG_CPU_SUBTYPE_SH7721) || \ 25 defined(CONFIG_ARCH_SH73A0) || \ 26 defined(CONFIG_ARCH_SH7367) || \ 27 defined(CONFIG_ARCH_SH7377) || \ 28 defined(CONFIG_ARCH_SH7372) 29 # define PORT_PTCR 0xA405011EUL 30 # define PORT_PVCR 0xA4050122UL 31 # define SCIF_ORER 0x0200 /* overrun error bit */ 32 #elif defined(CONFIG_SH_RTS7751R2D) 33 # define SCSPTR1 0xFFE0001C /* 8 bit SCIF */ 34 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ 35 # define SCIF_ORER 0x0001 /* overrun error bit */ 36 #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \ 37 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ 38 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ 39 defined(CONFIG_CPU_SUBTYPE_SH7091) || \ 40 defined(CONFIG_CPU_SUBTYPE_SH7751) || \ 41 defined(CONFIG_CPU_SUBTYPE_SH7751R) 42 # define SCSPTR1 0xffe0001c /* 8 bit SCI */ 43 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ 44 # define SCIF_ORER 0x0001 /* overrun error bit */ 45 #elif defined(CONFIG_CPU_SUBTYPE_SH7760) 46 # define SCSPTR0 0xfe600024 /* 16 bit SCIF */ 47 # define SCSPTR1 0xfe610024 /* 16 bit SCIF */ 48 # define SCSPTR2 0xfe620024 /* 16 bit SCIF */ 49 # define SCIF_ORER 0x0001 /* overrun error bit */ 50 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) 51 # define SCSPTR0 0xA4400000 /* 16 bit SCIF */ 52 # define SCIF_ORER 0x0001 /* overrun error bit */ 53 # define PACR 0xa4050100 54 # define PBCR 0xa4050102 55 #elif defined(CONFIG_CPU_SUBTYPE_SH7343) 56 # define SCSPTR0 0xffe00010 /* 16 bit SCIF */ 57 # define SCSPTR1 0xffe10010 /* 16 bit SCIF */ 58 # define SCSPTR2 0xffe20010 /* 16 bit SCIF */ 59 # define SCSPTR3 0xffe30010 /* 16 bit SCIF */ 60 #elif defined(CONFIG_CPU_SUBTYPE_SH7722) 61 # define PADR 0xA4050120 62 # define PSDR 0xA405013e 63 # define PWDR 0xA4050166 64 # define PSCR 0xA405011E 65 # define SCIF_ORER 0x0001 /* overrun error bit */ 66 #elif defined(CONFIG_CPU_SUBTYPE_SH7366) 67 # define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */ 68 # define SCSPTR0 SCPDR0 69 # define SCIF_ORER 0x0001 /* overrun error bit */ 70 #elif defined(CONFIG_CPU_SUBTYPE_SH7723) 71 # define SCSPTR0 0xa4050160 72 # define SCSPTR1 0xa405013e 73 # define SCSPTR2 0xa4050160 74 # define SCSPTR3 0xa405013e 75 # define SCSPTR4 0xa4050128 76 # define SCSPTR5 0xa4050128 77 # define SCIF_ORER 0x0001 /* overrun error bit */ 78 #elif defined(CONFIG_CPU_SUBTYPE_SH7724) 79 # define SCIF_ORER 0x0001 /* overrun error bit */ 80 #elif defined(CONFIG_CPU_SUBTYPE_SH4_202) 81 # define SCSPTR2 0xffe80020 /* 16 bit SCIF */ 82 # define SCIF_ORER 0x0001 /* overrun error bit */ 83 #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) 84 # define SCIF_PTR2_OFFS 0x0000020 85 # define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */ 86 #elif defined(CONFIG_H83007) || defined(CONFIG_H83068) 87 # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port) 88 #elif defined(CONFIG_H8S2678) 89 # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port) 90 #elif defined(CONFIG_CPU_SUBTYPE_SH7757) 91 # define SCSPTR0 0xfe4b0020 92 # define SCSPTR1 0xfe4b0020 93 # define SCSPTR2 0xfe4b0020 94 # define SCIF_ORER 0x0001 95 # define SCIF_ONLY 96 #elif defined(CONFIG_CPU_SUBTYPE_SH7763) 97 # define SCSPTR0 0xffe00024 /* 16 bit SCIF */ 98 # define SCSPTR1 0xffe08024 /* 16 bit SCIF */ 99 # define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */ 100 # define SCIF_ORER 0x0001 /* overrun error bit */ 101 #elif defined(CONFIG_CPU_SUBTYPE_SH7770) 102 # define SCSPTR0 0xff923020 /* 16 bit SCIF */ 103 # define SCSPTR1 0xff924020 /* 16 bit SCIF */ 104 # define SCSPTR2 0xff925020 /* 16 bit SCIF */ 105 # define SCIF_ORER 0x0001 /* overrun error bit */ 106 #elif defined(CONFIG_CPU_SUBTYPE_SH7780) 107 # define SCSPTR0 0xffe00024 /* 16 bit SCIF */ 108 # define SCSPTR1 0xffe10024 /* 16 bit SCIF */ 109 # define SCIF_ORER 0x0001 /* Overrun error bit */ 110 #elif defined(CONFIG_CPU_SUBTYPE_SH7785) || \ 111 defined(CONFIG_CPU_SUBTYPE_SH7786) 112 # define SCSPTR0 0xffea0024 /* 16 bit SCIF */ 113 # define SCSPTR1 0xffeb0024 /* 16 bit SCIF */ 114 # define SCSPTR2 0xffec0024 /* 16 bit SCIF */ 115 # define SCSPTR3 0xffed0024 /* 16 bit SCIF */ 116 # define SCSPTR4 0xffee0024 /* 16 bit SCIF */ 117 # define SCSPTR5 0xffef0024 /* 16 bit SCIF */ 118 # define SCIF_ORER 0x0001 /* Overrun error bit */ 119 #elif defined(CONFIG_CPU_SUBTYPE_SH7201) || \ 120 defined(CONFIG_CPU_SUBTYPE_SH7203) || \ 121 defined(CONFIG_CPU_SUBTYPE_SH7206) || \ 122 defined(CONFIG_CPU_SUBTYPE_SH7263) 123 # define SCSPTR0 0xfffe8020 /* 16 bit SCIF */ 124 # define SCSPTR1 0xfffe8820 /* 16 bit SCIF */ 125 # define SCSPTR2 0xfffe9020 /* 16 bit SCIF */ 126 # define SCSPTR3 0xfffe9820 /* 16 bit SCIF */ 127 # if defined(CONFIG_CPU_SUBTYPE_SH7201) 128 # define SCSPTR4 0xfffeA020 /* 16 bit SCIF */ 129 # define SCSPTR5 0xfffeA820 /* 16 bit SCIF */ 130 # define SCSPTR6 0xfffeB020 /* 16 bit SCIF */ 131 # define SCSPTR7 0xfffeB820 /* 16 bit SCIF */ 132 # endif 133 #elif defined(CONFIG_CPU_SUBTYPE_SH7619) 134 # define SCSPTR0 0xf8400020 /* 16 bit SCIF */ 135 # define SCSPTR1 0xf8410020 /* 16 bit SCIF */ 136 # define SCSPTR2 0xf8420020 /* 16 bit SCIF */ 137 # define SCIF_ORER 0x0001 /* overrun error bit */ 138 #elif defined(CONFIG_CPU_SUBTYPE_SHX3) 139 # define SCSPTR0 0xffc30020 /* 16 bit SCIF */ 140 # define SCSPTR1 0xffc40020 /* 16 bit SCIF */ 141 # define SCSPTR2 0xffc50020 /* 16 bit SCIF */ 142 # define SCSPTR3 0xffc60020 /* 16 bit SCIF */ 143 # define SCIF_ORER 0x0001 /* Overrun error bit */ 144 #else 145 # error CPU subtype not defined 146 #endif 147 148 /* SCxSR SCI */ 149 #define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 150 #define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 151 #define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 152 #define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 153 #define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 154 #define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 155 /* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 156 /* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 157 158 #define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER) 159 160 /* SCxSR SCIF */ 161 #define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 162 #define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 163 #define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 164 #define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 165 #define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 166 #define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 167 #define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 168 #define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 169 170 #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ 171 defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 172 defined(CONFIG_CPU_SUBTYPE_SH7721) || \ 173 defined(CONFIG_ARCH_SH73A0) || \ 174 defined(CONFIG_ARCH_SH7367) || \ 175 defined(CONFIG_ARCH_SH7377) || \ 176 defined(CONFIG_ARCH_SH7372) 177 # define SCIF_ORER 0x0200 178 # define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER) 179 # define SCIF_RFDC_MASK 0x007f 180 # define SCIF_TXROOM_MAX 64 181 #elif defined(CONFIG_CPU_SUBTYPE_SH7763) 182 # define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK ) 183 # define SCIF_RFDC_MASK 0x007f 184 # define SCIF_TXROOM_MAX 64 185 /* SH7763 SCIF2 support */ 186 # define SCIF2_RFDC_MASK 0x001f 187 # define SCIF2_TXROOM_MAX 16 188 #else 189 # define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK) 190 # define SCIF_RFDC_MASK 0x001f 191 # define SCIF_TXROOM_MAX 16 192 #endif 193 194 #ifndef SCIF_ORER 195 #define SCIF_ORER 0x0000 196 #endif 197 198 #define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND) 199 #define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS) 200 #define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF) 201 #define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE) 202 #define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER) 203 #define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER) 204 #define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK) 205 #define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER) 206 207 #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ 208 defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 209 defined(CONFIG_CPU_SUBTYPE_SH7721) || \ 210 defined(CONFIG_ARCH_SH73A0) || \ 211 defined(CONFIG_ARCH_SH7367) || \ 212 defined(CONFIG_ARCH_SH7377) || \ 213 defined(CONFIG_ARCH_SH7372) 214 # define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc) 215 # define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73) 216 # define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf) 217 # define SCxSR_BREAK_CLEAR(port) (sci_in(port, SCxSR) & 0xffe3) 218 #else 219 # define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc) 220 # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073) 221 # define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df) 222 # define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3) 223 #endif 224 225 /* SCFCR */ 226 #define SCFCR_RFRST 0x0002 227 #define SCFCR_TFRST 0x0004 228 #define SCFCR_MCE 0x0008 229 230 #define SCI_MAJOR 204 231 #define SCI_MINOR_START 8 232 233 #define SCI_IN(size, offset) \ 234 if ((size) == 8) { \ 235 return ioread8(port->membase + (offset)); \ 236 } else { \ 237 return ioread16(port->membase + (offset)); \ 238 } 239 #define SCI_OUT(size, offset, value) \ 240 if ((size) == 8) { \ 241 iowrite8(value, port->membase + (offset)); \ 242 } else if ((size) == 16) { \ 243 iowrite16(value, port->membase + (offset)); \ 244 } 245 246 #define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\ 247 static inline unsigned int sci_##name##_in(struct uart_port *port) \ 248 { \ 249 if (port->type == PORT_SCIF || port->type == PORT_SCIFB) { \ 250 SCI_IN(scif_size, scif_offset) \ 251 } else { /* PORT_SCI or PORT_SCIFA */ \ 252 SCI_IN(sci_size, sci_offset); \ 253 } \ 254 } \ 255 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \ 256 { \ 257 if (port->type == PORT_SCIF || port->type == PORT_SCIFB) { \ 258 SCI_OUT(scif_size, scif_offset, value) \ 259 } else { /* PORT_SCI or PORT_SCIFA */ \ 260 SCI_OUT(sci_size, sci_offset, value); \ 261 } \ 262 } 263 264 #ifdef CONFIG_H8300 265 /* h8300 don't have SCIF */ 266 #define CPU_SCIF_FNS(name) \ 267 static inline unsigned int sci_##name##_in(struct uart_port *port) \ 268 { \ 269 return 0; \ 270 } \ 271 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \ 272 { \ 273 } 274 #else 275 #define CPU_SCIF_FNS(name, scif_offset, scif_size) \ 276 static inline unsigned int sci_##name##_in(struct uart_port *port) \ 277 { \ 278 SCI_IN(scif_size, scif_offset); \ 279 } \ 280 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \ 281 { \ 282 SCI_OUT(scif_size, scif_offset, value); \ 283 } 284 #endif 285 286 #define CPU_SCI_FNS(name, sci_offset, sci_size) \ 287 static inline unsigned int sci_##name##_in(struct uart_port* port) \ 288 { \ 289 SCI_IN(sci_size, sci_offset); \ 290 } \ 291 static inline void sci_##name##_out(struct uart_port* port, unsigned int value) \ 292 { \ 293 SCI_OUT(sci_size, sci_offset, value); \ 294 } 295 296 #if defined(CONFIG_CPU_SH3) || \ 297 defined(CONFIG_ARCH_SH73A0) || \ 298 defined(CONFIG_ARCH_SH7367) || \ 299 defined(CONFIG_ARCH_SH7377) || \ 300 defined(CONFIG_ARCH_SH7372) 301 #if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) 302 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \ 303 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \ 304 h8_sci_offset, h8_sci_size) \ 305 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size) 306 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \ 307 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) 308 #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \ 309 defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 310 defined(CONFIG_CPU_SUBTYPE_SH7721) || \ 311 defined(CONFIG_ARCH_SH73A0) || \ 312 defined(CONFIG_ARCH_SH7367) || \ 313 defined(CONFIG_ARCH_SH7377) 314 #define SCIF_FNS(name, scif_offset, scif_size) \ 315 CPU_SCIF_FNS(name, scif_offset, scif_size) 316 #elif defined(CONFIG_ARCH_SH7372) 317 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scifb_offset, sh4_scifb_size) \ 318 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scifb_offset, sh4_scifb_size) 319 #define SCIF_FNS(name, scif_offset, scif_size) \ 320 CPU_SCIF_FNS(name, scif_offset, scif_size) 321 #else 322 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \ 323 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \ 324 h8_sci_offset, h8_sci_size) \ 325 CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size) 326 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \ 327 CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size) 328 #endif 329 #elif defined(__H8300H__) || defined(__H8300S__) 330 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \ 331 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \ 332 h8_sci_offset, h8_sci_size) \ 333 CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size) 334 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \ 335 CPU_SCIF_FNS(name) 336 #elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\ 337 defined(CONFIG_CPU_SUBTYPE_SH7724) 338 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size) \ 339 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size) 340 #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \ 341 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) 342 #else 343 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \ 344 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \ 345 h8_sci_offset, h8_sci_size) \ 346 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size) 347 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \ 348 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) 349 #endif 350 351 #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ 352 defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 353 defined(CONFIG_CPU_SUBTYPE_SH7721) || \ 354 defined(CONFIG_ARCH_SH73A0) || \ 355 defined(CONFIG_ARCH_SH7367) || \ 356 defined(CONFIG_ARCH_SH7377) 357 358 SCIF_FNS(SCSMR, 0x00, 16) 359 SCIF_FNS(SCBRR, 0x04, 8) 360 SCIF_FNS(SCSCR, 0x08, 16) 361 SCIF_FNS(SCxSR, 0x14, 16) 362 SCIF_FNS(SCFCR, 0x18, 16) 363 SCIF_FNS(SCFDR, 0x1c, 16) 364 SCIF_FNS(SCxTDR, 0x20, 8) 365 SCIF_FNS(SCxRDR, 0x24, 8) 366 SCIF_FNS(SCLSR, 0x00, 0) 367 #elif defined(CONFIG_ARCH_SH7372) 368 SCIF_FNS(SCSMR, 0x00, 16) 369 SCIF_FNS(SCBRR, 0x04, 8) 370 SCIF_FNS(SCSCR, 0x08, 16) 371 SCIF_FNS(SCTDSR, 0x0c, 16) 372 SCIF_FNS(SCFER, 0x10, 16) 373 SCIF_FNS(SCxSR, 0x14, 16) 374 SCIF_FNS(SCFCR, 0x18, 16) 375 SCIF_FNS(SCFDR, 0x1c, 16) 376 SCIF_FNS(SCTFDR, 0x38, 16) 377 SCIF_FNS(SCRFDR, 0x3c, 16) 378 SCIx_FNS(SCxTDR, 0x20, 8, 0x40, 8) 379 SCIx_FNS(SCxRDR, 0x24, 8, 0x60, 8) 380 SCIF_FNS(SCLSR, 0x00, 0) 381 #elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\ 382 defined(CONFIG_CPU_SUBTYPE_SH7724) 383 SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16) 384 SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8) 385 SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16) 386 SCIx_FNS(SCxTDR, 0x20, 8, 0x0c, 8) 387 SCIx_FNS(SCxSR, 0x14, 16, 0x10, 16) 388 SCIx_FNS(SCxRDR, 0x24, 8, 0x14, 8) 389 SCIx_FNS(SCSPTR, 0, 0, 0, 0) 390 SCIF_FNS(SCFCR, 0x18, 16) 391 SCIF_FNS(SCFDR, 0x1c, 16) 392 SCIF_FNS(SCLSR, 0x24, 16) 393 #else 394 /* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/ 395 /* name off sz off sz off sz off sz off sz*/ 396 SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8) 397 SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8) 398 SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8) 399 SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8) 400 SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8) 401 SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8) 402 SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16) 403 #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \ 404 defined(CONFIG_CPU_SUBTYPE_SH7780) || \ 405 defined(CONFIG_CPU_SUBTYPE_SH7785) || \ 406 defined(CONFIG_CPU_SUBTYPE_SH7786) 407 SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) 408 SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16) 409 SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16) 410 SCIF_FNS(SCSPTR, 0, 0, 0x24, 16) 411 SCIF_FNS(SCLSR, 0, 0, 0x28, 16) 412 #elif defined(CONFIG_CPU_SUBTYPE_SH7763) 413 SCIF_FNS(SCFDR, 0, 0, 0x1C, 16) 414 SCIF_FNS(SCSPTR2, 0, 0, 0x20, 16) 415 SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16) 416 SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16) 417 SCIF_FNS(SCSPTR, 0, 0, 0x24, 16) 418 SCIF_FNS(SCLSR, 0, 0, 0x28, 16) 419 #else 420 SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) 421 #if defined(CONFIG_CPU_SUBTYPE_SH7722) 422 SCIF_FNS(SCSPTR, 0, 0, 0, 0) 423 #else 424 SCIF_FNS(SCSPTR, 0, 0, 0x20, 16) 425 #endif 426 SCIF_FNS(SCLSR, 0, 0, 0x24, 16) 427 #endif 428 #endif 429 #define sci_in(port, reg) sci_##reg##_in(port) 430 #define sci_out(port, reg, value) sci_##reg##_out(port, value) 431 432 /* H8/300 series SCI pins assignment */ 433 #if defined(__H8300H__) || defined(__H8300S__) 434 static const struct __attribute__((packed)) { 435 int port; /* GPIO port no */ 436 unsigned short rx,tx; /* GPIO bit no */ 437 } h8300_sci_pins[] = { 438 #if defined(CONFIG_H83007) || defined(CONFIG_H83068) 439 { /* SCI0 */ 440 .port = H8300_GPIO_P9, 441 .rx = H8300_GPIO_B2, 442 .tx = H8300_GPIO_B0, 443 }, 444 { /* SCI1 */ 445 .port = H8300_GPIO_P9, 446 .rx = H8300_GPIO_B3, 447 .tx = H8300_GPIO_B1, 448 }, 449 { /* SCI2 */ 450 .port = H8300_GPIO_PB, 451 .rx = H8300_GPIO_B7, 452 .tx = H8300_GPIO_B6, 453 } 454 #elif defined(CONFIG_H8S2678) 455 { /* SCI0 */ 456 .port = H8300_GPIO_P3, 457 .rx = H8300_GPIO_B2, 458 .tx = H8300_GPIO_B0, 459 }, 460 { /* SCI1 */ 461 .port = H8300_GPIO_P3, 462 .rx = H8300_GPIO_B3, 463 .tx = H8300_GPIO_B1, 464 }, 465 { /* SCI2 */ 466 .port = H8300_GPIO_P5, 467 .rx = H8300_GPIO_B1, 468 .tx = H8300_GPIO_B0, 469 } 470 #endif 471 }; 472 #endif 473 474 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ 475 defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 476 defined(CONFIG_CPU_SUBTYPE_SH7708) || \ 477 defined(CONFIG_CPU_SUBTYPE_SH7709) 478 static inline int sci_rxd_in(struct uart_port *port) 479 { 480 if (port->mapbase == 0xfffffe80) 481 return __raw_readb(SCPDR)&0x01 ? 1 : 0; /* SCI */ 482 return 1; 483 } 484 #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \ 485 defined(CONFIG_CPU_SUBTYPE_SH7751) || \ 486 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \ 487 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ 488 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ 489 defined(CONFIG_CPU_SUBTYPE_SH7091) 490 static inline int sci_rxd_in(struct uart_port *port) 491 { 492 if (port->mapbase == 0xffe00000) 493 return __raw_readb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */ 494 return 1; 495 } 496 #elif defined(__H8300H__) || defined(__H8300S__) 497 static inline int sci_rxd_in(struct uart_port *port) 498 { 499 int ch = (port->mapbase - SMR0) >> 3; 500 return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0; 501 } 502 #else /* default case for non-SCI processors */ 503 static inline int sci_rxd_in(struct uart_port *port) 504 { 505 return 1; 506 } 507 #endif 508