1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) 4 * 5 * Copyright (C) 2002 - 2011 Paul Mundt 6 * Copyright (C) 2015 Glider bvba 7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007). 8 * 9 * based off of the old drivers/char/sh-sci.c by: 10 * 11 * Copyright (C) 1999, 2000 Niibe Yutaka 12 * Copyright (C) 2000 Sugioka Toshinobu 13 * Modified to support multiple serial ports. Stuart Menefy (May 2000). 14 * Modified to support SecureEdge. David McCullough (2002) 15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003). 16 * Removed SH7300 support (Jul 2007). 17 */ 18 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 19 #define SUPPORT_SYSRQ 20 #endif 21 22 #undef DEBUG 23 24 #include <linux/clk.h> 25 #include <linux/console.h> 26 #include <linux/ctype.h> 27 #include <linux/cpufreq.h> 28 #include <linux/delay.h> 29 #include <linux/dmaengine.h> 30 #include <linux/dma-mapping.h> 31 #include <linux/err.h> 32 #include <linux/errno.h> 33 #include <linux/init.h> 34 #include <linux/interrupt.h> 35 #include <linux/ioport.h> 36 #include <linux/ktime.h> 37 #include <linux/major.h> 38 #include <linux/module.h> 39 #include <linux/mm.h> 40 #include <linux/of.h> 41 #include <linux/of_device.h> 42 #include <linux/platform_device.h> 43 #include <linux/pm_runtime.h> 44 #include <linux/scatterlist.h> 45 #include <linux/serial.h> 46 #include <linux/serial_sci.h> 47 #include <linux/sh_dma.h> 48 #include <linux/slab.h> 49 #include <linux/string.h> 50 #include <linux/sysrq.h> 51 #include <linux/timer.h> 52 #include <linux/tty.h> 53 #include <linux/tty_flip.h> 54 55 #ifdef CONFIG_SUPERH 56 #include <asm/sh_bios.h> 57 #include <asm/platform_early.h> 58 #endif 59 60 #include "serial_mctrl_gpio.h" 61 #include "sh-sci.h" 62 63 /* Offsets into the sci_port->irqs array */ 64 enum { 65 SCIx_ERI_IRQ, 66 SCIx_RXI_IRQ, 67 SCIx_TXI_IRQ, 68 SCIx_BRI_IRQ, 69 SCIx_DRI_IRQ, 70 SCIx_TEI_IRQ, 71 SCIx_NR_IRQS, 72 73 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */ 74 }; 75 76 #define SCIx_IRQ_IS_MUXED(port) \ 77 ((port)->irqs[SCIx_ERI_IRQ] == \ 78 (port)->irqs[SCIx_RXI_IRQ]) || \ 79 ((port)->irqs[SCIx_ERI_IRQ] && \ 80 ((port)->irqs[SCIx_RXI_IRQ] < 0)) 81 82 enum SCI_CLKS { 83 SCI_FCK, /* Functional Clock */ 84 SCI_SCK, /* Optional External Clock */ 85 SCI_BRG_INT, /* Optional BRG Internal Clock Source */ 86 SCI_SCIF_CLK, /* Optional BRG External Clock Source */ 87 SCI_NUM_CLKS 88 }; 89 90 /* Bit x set means sampling rate x + 1 is supported */ 91 #define SCI_SR(x) BIT((x) - 1) 92 #define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1) 93 94 #define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \ 95 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \ 96 SCI_SR(19) | SCI_SR(27) 97 98 #define min_sr(_port) ffs((_port)->sampling_rate_mask) 99 #define max_sr(_port) fls((_port)->sampling_rate_mask) 100 101 /* Iterate over all supported sampling rates, from high to low */ 102 #define for_each_sr(_sr, _port) \ 103 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \ 104 if ((_port)->sampling_rate_mask & SCI_SR((_sr))) 105 106 struct plat_sci_reg { 107 u8 offset, size; 108 }; 109 110 struct sci_port_params { 111 const struct plat_sci_reg regs[SCIx_NR_REGS]; 112 unsigned int fifosize; 113 unsigned int overrun_reg; 114 unsigned int overrun_mask; 115 unsigned int sampling_rate_mask; 116 unsigned int error_mask; 117 unsigned int error_clear; 118 }; 119 120 struct sci_port { 121 struct uart_port port; 122 123 /* Platform configuration */ 124 const struct sci_port_params *params; 125 const struct plat_sci_port *cfg; 126 unsigned int sampling_rate_mask; 127 resource_size_t reg_size; 128 struct mctrl_gpios *gpios; 129 130 /* Clocks */ 131 struct clk *clks[SCI_NUM_CLKS]; 132 unsigned long clk_rates[SCI_NUM_CLKS]; 133 134 int irqs[SCIx_NR_IRQS]; 135 char *irqstr[SCIx_NR_IRQS]; 136 137 struct dma_chan *chan_tx; 138 struct dma_chan *chan_rx; 139 140 #ifdef CONFIG_SERIAL_SH_SCI_DMA 141 struct dma_chan *chan_tx_saved; 142 struct dma_chan *chan_rx_saved; 143 dma_cookie_t cookie_tx; 144 dma_cookie_t cookie_rx[2]; 145 dma_cookie_t active_rx; 146 dma_addr_t tx_dma_addr; 147 unsigned int tx_dma_len; 148 struct scatterlist sg_rx[2]; 149 void *rx_buf[2]; 150 size_t buf_len_rx; 151 struct work_struct work_tx; 152 struct hrtimer rx_timer; 153 unsigned int rx_timeout; /* microseconds */ 154 #endif 155 unsigned int rx_frame; 156 int rx_trigger; 157 struct timer_list rx_fifo_timer; 158 int rx_fifo_timeout; 159 u16 hscif_tot; 160 161 bool has_rtscts; 162 bool autorts; 163 }; 164 165 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS 166 167 static struct sci_port sci_ports[SCI_NPORTS]; 168 static unsigned long sci_ports_in_use; 169 static struct uart_driver sci_uart_driver; 170 171 static inline struct sci_port * 172 to_sci_port(struct uart_port *uart) 173 { 174 return container_of(uart, struct sci_port, port); 175 } 176 177 static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { 178 /* 179 * Common SCI definitions, dependent on the port's regshift 180 * value. 181 */ 182 [SCIx_SCI_REGTYPE] = { 183 .regs = { 184 [SCSMR] = { 0x00, 8 }, 185 [SCBRR] = { 0x01, 8 }, 186 [SCSCR] = { 0x02, 8 }, 187 [SCxTDR] = { 0x03, 8 }, 188 [SCxSR] = { 0x04, 8 }, 189 [SCxRDR] = { 0x05, 8 }, 190 }, 191 .fifosize = 1, 192 .overrun_reg = SCxSR, 193 .overrun_mask = SCI_ORER, 194 .sampling_rate_mask = SCI_SR(32), 195 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, 196 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, 197 }, 198 199 /* 200 * Common definitions for legacy IrDA ports. 201 */ 202 [SCIx_IRDA_REGTYPE] = { 203 .regs = { 204 [SCSMR] = { 0x00, 8 }, 205 [SCBRR] = { 0x02, 8 }, 206 [SCSCR] = { 0x04, 8 }, 207 [SCxTDR] = { 0x06, 8 }, 208 [SCxSR] = { 0x08, 16 }, 209 [SCxRDR] = { 0x0a, 8 }, 210 [SCFCR] = { 0x0c, 8 }, 211 [SCFDR] = { 0x0e, 16 }, 212 }, 213 .fifosize = 1, 214 .overrun_reg = SCxSR, 215 .overrun_mask = SCI_ORER, 216 .sampling_rate_mask = SCI_SR(32), 217 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, 218 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, 219 }, 220 221 /* 222 * Common SCIFA definitions. 223 */ 224 [SCIx_SCIFA_REGTYPE] = { 225 .regs = { 226 [SCSMR] = { 0x00, 16 }, 227 [SCBRR] = { 0x04, 8 }, 228 [SCSCR] = { 0x08, 16 }, 229 [SCxTDR] = { 0x20, 8 }, 230 [SCxSR] = { 0x14, 16 }, 231 [SCxRDR] = { 0x24, 8 }, 232 [SCFCR] = { 0x18, 16 }, 233 [SCFDR] = { 0x1c, 16 }, 234 [SCPCR] = { 0x30, 16 }, 235 [SCPDR] = { 0x34, 16 }, 236 }, 237 .fifosize = 64, 238 .overrun_reg = SCxSR, 239 .overrun_mask = SCIFA_ORER, 240 .sampling_rate_mask = SCI_SR_SCIFAB, 241 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 242 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 243 }, 244 245 /* 246 * Common SCIFB definitions. 247 */ 248 [SCIx_SCIFB_REGTYPE] = { 249 .regs = { 250 [SCSMR] = { 0x00, 16 }, 251 [SCBRR] = { 0x04, 8 }, 252 [SCSCR] = { 0x08, 16 }, 253 [SCxTDR] = { 0x40, 8 }, 254 [SCxSR] = { 0x14, 16 }, 255 [SCxRDR] = { 0x60, 8 }, 256 [SCFCR] = { 0x18, 16 }, 257 [SCTFDR] = { 0x38, 16 }, 258 [SCRFDR] = { 0x3c, 16 }, 259 [SCPCR] = { 0x30, 16 }, 260 [SCPDR] = { 0x34, 16 }, 261 }, 262 .fifosize = 256, 263 .overrun_reg = SCxSR, 264 .overrun_mask = SCIFA_ORER, 265 .sampling_rate_mask = SCI_SR_SCIFAB, 266 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 267 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 268 }, 269 270 /* 271 * Common SH-2(A) SCIF definitions for ports with FIFO data 272 * count registers. 273 */ 274 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = { 275 .regs = { 276 [SCSMR] = { 0x00, 16 }, 277 [SCBRR] = { 0x04, 8 }, 278 [SCSCR] = { 0x08, 16 }, 279 [SCxTDR] = { 0x0c, 8 }, 280 [SCxSR] = { 0x10, 16 }, 281 [SCxRDR] = { 0x14, 8 }, 282 [SCFCR] = { 0x18, 16 }, 283 [SCFDR] = { 0x1c, 16 }, 284 [SCSPTR] = { 0x20, 16 }, 285 [SCLSR] = { 0x24, 16 }, 286 }, 287 .fifosize = 16, 288 .overrun_reg = SCLSR, 289 .overrun_mask = SCLSR_ORER, 290 .sampling_rate_mask = SCI_SR(32), 291 .error_mask = SCIF_DEFAULT_ERROR_MASK, 292 .error_clear = SCIF_ERROR_CLEAR, 293 }, 294 295 /* 296 * The "SCIFA" that is in RZ/T and RZ/A2. 297 * It looks like a normal SCIF with FIFO data, but with a 298 * compressed address space. Also, the break out of interrupts 299 * are different: ERI/BRI, RXI, TXI, TEI, DRI. 300 */ 301 [SCIx_RZ_SCIFA_REGTYPE] = { 302 .regs = { 303 [SCSMR] = { 0x00, 16 }, 304 [SCBRR] = { 0x02, 8 }, 305 [SCSCR] = { 0x04, 16 }, 306 [SCxTDR] = { 0x06, 8 }, 307 [SCxSR] = { 0x08, 16 }, 308 [SCxRDR] = { 0x0A, 8 }, 309 [SCFCR] = { 0x0C, 16 }, 310 [SCFDR] = { 0x0E, 16 }, 311 [SCSPTR] = { 0x10, 16 }, 312 [SCLSR] = { 0x12, 16 }, 313 }, 314 .fifosize = 16, 315 .overrun_reg = SCLSR, 316 .overrun_mask = SCLSR_ORER, 317 .sampling_rate_mask = SCI_SR(32), 318 .error_mask = SCIF_DEFAULT_ERROR_MASK, 319 .error_clear = SCIF_ERROR_CLEAR, 320 }, 321 322 /* 323 * Common SH-3 SCIF definitions. 324 */ 325 [SCIx_SH3_SCIF_REGTYPE] = { 326 .regs = { 327 [SCSMR] = { 0x00, 8 }, 328 [SCBRR] = { 0x02, 8 }, 329 [SCSCR] = { 0x04, 8 }, 330 [SCxTDR] = { 0x06, 8 }, 331 [SCxSR] = { 0x08, 16 }, 332 [SCxRDR] = { 0x0a, 8 }, 333 [SCFCR] = { 0x0c, 8 }, 334 [SCFDR] = { 0x0e, 16 }, 335 }, 336 .fifosize = 16, 337 .overrun_reg = SCLSR, 338 .overrun_mask = SCLSR_ORER, 339 .sampling_rate_mask = SCI_SR(32), 340 .error_mask = SCIF_DEFAULT_ERROR_MASK, 341 .error_clear = SCIF_ERROR_CLEAR, 342 }, 343 344 /* 345 * Common SH-4(A) SCIF(B) definitions. 346 */ 347 [SCIx_SH4_SCIF_REGTYPE] = { 348 .regs = { 349 [SCSMR] = { 0x00, 16 }, 350 [SCBRR] = { 0x04, 8 }, 351 [SCSCR] = { 0x08, 16 }, 352 [SCxTDR] = { 0x0c, 8 }, 353 [SCxSR] = { 0x10, 16 }, 354 [SCxRDR] = { 0x14, 8 }, 355 [SCFCR] = { 0x18, 16 }, 356 [SCFDR] = { 0x1c, 16 }, 357 [SCSPTR] = { 0x20, 16 }, 358 [SCLSR] = { 0x24, 16 }, 359 }, 360 .fifosize = 16, 361 .overrun_reg = SCLSR, 362 .overrun_mask = SCLSR_ORER, 363 .sampling_rate_mask = SCI_SR(32), 364 .error_mask = SCIF_DEFAULT_ERROR_MASK, 365 .error_clear = SCIF_ERROR_CLEAR, 366 }, 367 368 /* 369 * Common SCIF definitions for ports with a Baud Rate Generator for 370 * External Clock (BRG). 371 */ 372 [SCIx_SH4_SCIF_BRG_REGTYPE] = { 373 .regs = { 374 [SCSMR] = { 0x00, 16 }, 375 [SCBRR] = { 0x04, 8 }, 376 [SCSCR] = { 0x08, 16 }, 377 [SCxTDR] = { 0x0c, 8 }, 378 [SCxSR] = { 0x10, 16 }, 379 [SCxRDR] = { 0x14, 8 }, 380 [SCFCR] = { 0x18, 16 }, 381 [SCFDR] = { 0x1c, 16 }, 382 [SCSPTR] = { 0x20, 16 }, 383 [SCLSR] = { 0x24, 16 }, 384 [SCDL] = { 0x30, 16 }, 385 [SCCKS] = { 0x34, 16 }, 386 }, 387 .fifosize = 16, 388 .overrun_reg = SCLSR, 389 .overrun_mask = SCLSR_ORER, 390 .sampling_rate_mask = SCI_SR(32), 391 .error_mask = SCIF_DEFAULT_ERROR_MASK, 392 .error_clear = SCIF_ERROR_CLEAR, 393 }, 394 395 /* 396 * Common HSCIF definitions. 397 */ 398 [SCIx_HSCIF_REGTYPE] = { 399 .regs = { 400 [SCSMR] = { 0x00, 16 }, 401 [SCBRR] = { 0x04, 8 }, 402 [SCSCR] = { 0x08, 16 }, 403 [SCxTDR] = { 0x0c, 8 }, 404 [SCxSR] = { 0x10, 16 }, 405 [SCxRDR] = { 0x14, 8 }, 406 [SCFCR] = { 0x18, 16 }, 407 [SCFDR] = { 0x1c, 16 }, 408 [SCSPTR] = { 0x20, 16 }, 409 [SCLSR] = { 0x24, 16 }, 410 [HSSRR] = { 0x40, 16 }, 411 [SCDL] = { 0x30, 16 }, 412 [SCCKS] = { 0x34, 16 }, 413 [HSRTRGR] = { 0x54, 16 }, 414 [HSTTRGR] = { 0x58, 16 }, 415 }, 416 .fifosize = 128, 417 .overrun_reg = SCLSR, 418 .overrun_mask = SCLSR_ORER, 419 .sampling_rate_mask = SCI_SR_RANGE(8, 32), 420 .error_mask = SCIF_DEFAULT_ERROR_MASK, 421 .error_clear = SCIF_ERROR_CLEAR, 422 }, 423 424 /* 425 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR 426 * register. 427 */ 428 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = { 429 .regs = { 430 [SCSMR] = { 0x00, 16 }, 431 [SCBRR] = { 0x04, 8 }, 432 [SCSCR] = { 0x08, 16 }, 433 [SCxTDR] = { 0x0c, 8 }, 434 [SCxSR] = { 0x10, 16 }, 435 [SCxRDR] = { 0x14, 8 }, 436 [SCFCR] = { 0x18, 16 }, 437 [SCFDR] = { 0x1c, 16 }, 438 [SCLSR] = { 0x24, 16 }, 439 }, 440 .fifosize = 16, 441 .overrun_reg = SCLSR, 442 .overrun_mask = SCLSR_ORER, 443 .sampling_rate_mask = SCI_SR(32), 444 .error_mask = SCIF_DEFAULT_ERROR_MASK, 445 .error_clear = SCIF_ERROR_CLEAR, 446 }, 447 448 /* 449 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data 450 * count registers. 451 */ 452 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = { 453 .regs = { 454 [SCSMR] = { 0x00, 16 }, 455 [SCBRR] = { 0x04, 8 }, 456 [SCSCR] = { 0x08, 16 }, 457 [SCxTDR] = { 0x0c, 8 }, 458 [SCxSR] = { 0x10, 16 }, 459 [SCxRDR] = { 0x14, 8 }, 460 [SCFCR] = { 0x18, 16 }, 461 [SCFDR] = { 0x1c, 16 }, 462 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */ 463 [SCRFDR] = { 0x20, 16 }, 464 [SCSPTR] = { 0x24, 16 }, 465 [SCLSR] = { 0x28, 16 }, 466 }, 467 .fifosize = 16, 468 .overrun_reg = SCLSR, 469 .overrun_mask = SCLSR_ORER, 470 .sampling_rate_mask = SCI_SR(32), 471 .error_mask = SCIF_DEFAULT_ERROR_MASK, 472 .error_clear = SCIF_ERROR_CLEAR, 473 }, 474 475 /* 476 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR 477 * registers. 478 */ 479 [SCIx_SH7705_SCIF_REGTYPE] = { 480 .regs = { 481 [SCSMR] = { 0x00, 16 }, 482 [SCBRR] = { 0x04, 8 }, 483 [SCSCR] = { 0x08, 16 }, 484 [SCxTDR] = { 0x20, 8 }, 485 [SCxSR] = { 0x14, 16 }, 486 [SCxRDR] = { 0x24, 8 }, 487 [SCFCR] = { 0x18, 16 }, 488 [SCFDR] = { 0x1c, 16 }, 489 }, 490 .fifosize = 64, 491 .overrun_reg = SCxSR, 492 .overrun_mask = SCIFA_ORER, 493 .sampling_rate_mask = SCI_SR(16), 494 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 495 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 496 }, 497 }; 498 499 #define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset]) 500 501 /* 502 * The "offset" here is rather misleading, in that it refers to an enum 503 * value relative to the port mapping rather than the fixed offset 504 * itself, which needs to be manually retrieved from the platform's 505 * register map for the given port. 506 */ 507 static unsigned int sci_serial_in(struct uart_port *p, int offset) 508 { 509 const struct plat_sci_reg *reg = sci_getreg(p, offset); 510 511 if (reg->size == 8) 512 return ioread8(p->membase + (reg->offset << p->regshift)); 513 else if (reg->size == 16) 514 return ioread16(p->membase + (reg->offset << p->regshift)); 515 else 516 WARN(1, "Invalid register access\n"); 517 518 return 0; 519 } 520 521 static void sci_serial_out(struct uart_port *p, int offset, int value) 522 { 523 const struct plat_sci_reg *reg = sci_getreg(p, offset); 524 525 if (reg->size == 8) 526 iowrite8(value, p->membase + (reg->offset << p->regshift)); 527 else if (reg->size == 16) 528 iowrite16(value, p->membase + (reg->offset << p->regshift)); 529 else 530 WARN(1, "Invalid register access\n"); 531 } 532 533 static void sci_port_enable(struct sci_port *sci_port) 534 { 535 unsigned int i; 536 537 if (!sci_port->port.dev) 538 return; 539 540 pm_runtime_get_sync(sci_port->port.dev); 541 542 for (i = 0; i < SCI_NUM_CLKS; i++) { 543 clk_prepare_enable(sci_port->clks[i]); 544 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]); 545 } 546 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK]; 547 } 548 549 static void sci_port_disable(struct sci_port *sci_port) 550 { 551 unsigned int i; 552 553 if (!sci_port->port.dev) 554 return; 555 556 for (i = SCI_NUM_CLKS; i-- > 0; ) 557 clk_disable_unprepare(sci_port->clks[i]); 558 559 pm_runtime_put_sync(sci_port->port.dev); 560 } 561 562 static inline unsigned long port_rx_irq_mask(struct uart_port *port) 563 { 564 /* 565 * Not all ports (such as SCIFA) will support REIE. Rather than 566 * special-casing the port type, we check the port initialization 567 * IRQ enable mask to see whether the IRQ is desired at all. If 568 * it's unset, it's logically inferred that there's no point in 569 * testing for it. 570 */ 571 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE); 572 } 573 574 static void sci_start_tx(struct uart_port *port) 575 { 576 struct sci_port *s = to_sci_port(port); 577 unsigned short ctrl; 578 579 #ifdef CONFIG_SERIAL_SH_SCI_DMA 580 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 581 u16 new, scr = serial_port_in(port, SCSCR); 582 if (s->chan_tx) 583 new = scr | SCSCR_TDRQE; 584 else 585 new = scr & ~SCSCR_TDRQE; 586 if (new != scr) 587 serial_port_out(port, SCSCR, new); 588 } 589 590 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) && 591 dma_submit_error(s->cookie_tx)) { 592 s->cookie_tx = 0; 593 schedule_work(&s->work_tx); 594 } 595 #endif 596 597 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 598 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ 599 ctrl = serial_port_in(port, SCSCR); 600 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE); 601 } 602 } 603 604 static void sci_stop_tx(struct uart_port *port) 605 { 606 unsigned short ctrl; 607 608 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ 609 ctrl = serial_port_in(port, SCSCR); 610 611 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 612 ctrl &= ~SCSCR_TDRQE; 613 614 ctrl &= ~SCSCR_TIE; 615 616 serial_port_out(port, SCSCR, ctrl); 617 } 618 619 static void sci_start_rx(struct uart_port *port) 620 { 621 unsigned short ctrl; 622 623 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port); 624 625 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 626 ctrl &= ~SCSCR_RDRQE; 627 628 serial_port_out(port, SCSCR, ctrl); 629 } 630 631 static void sci_stop_rx(struct uart_port *port) 632 { 633 unsigned short ctrl; 634 635 ctrl = serial_port_in(port, SCSCR); 636 637 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 638 ctrl &= ~SCSCR_RDRQE; 639 640 ctrl &= ~port_rx_irq_mask(port); 641 642 serial_port_out(port, SCSCR, ctrl); 643 } 644 645 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask) 646 { 647 if (port->type == PORT_SCI) { 648 /* Just store the mask */ 649 serial_port_out(port, SCxSR, mask); 650 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) { 651 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */ 652 /* Only clear the status bits we want to clear */ 653 serial_port_out(port, SCxSR, 654 serial_port_in(port, SCxSR) & mask); 655 } else { 656 /* Store the mask, clear parity/framing errors */ 657 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC)); 658 } 659 } 660 661 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ 662 defined(CONFIG_SERIAL_SH_SCI_EARLYCON) 663 664 #ifdef CONFIG_CONSOLE_POLL 665 static int sci_poll_get_char(struct uart_port *port) 666 { 667 unsigned short status; 668 int c; 669 670 do { 671 status = serial_port_in(port, SCxSR); 672 if (status & SCxSR_ERRORS(port)) { 673 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); 674 continue; 675 } 676 break; 677 } while (1); 678 679 if (!(status & SCxSR_RDxF(port))) 680 return NO_POLL_CHAR; 681 682 c = serial_port_in(port, SCxRDR); 683 684 /* Dummy read */ 685 serial_port_in(port, SCxSR); 686 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 687 688 return c; 689 } 690 #endif 691 692 static void sci_poll_put_char(struct uart_port *port, unsigned char c) 693 { 694 unsigned short status; 695 696 do { 697 status = serial_port_in(port, SCxSR); 698 } while (!(status & SCxSR_TDxE(port))); 699 700 serial_port_out(port, SCxTDR, c); 701 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port)); 702 } 703 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE || 704 CONFIG_SERIAL_SH_SCI_EARLYCON */ 705 706 static void sci_init_pins(struct uart_port *port, unsigned int cflag) 707 { 708 struct sci_port *s = to_sci_port(port); 709 710 /* 711 * Use port-specific handler if provided. 712 */ 713 if (s->cfg->ops && s->cfg->ops->init_pins) { 714 s->cfg->ops->init_pins(port, cflag); 715 return; 716 } 717 718 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 719 u16 data = serial_port_in(port, SCPDR); 720 u16 ctrl = serial_port_in(port, SCPCR); 721 722 /* Enable RXD and TXD pin functions */ 723 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC); 724 if (to_sci_port(port)->has_rtscts) { 725 /* RTS# is output, active low, unless autorts */ 726 if (!(port->mctrl & TIOCM_RTS)) { 727 ctrl |= SCPCR_RTSC; 728 data |= SCPDR_RTSD; 729 } else if (!s->autorts) { 730 ctrl |= SCPCR_RTSC; 731 data &= ~SCPDR_RTSD; 732 } else { 733 /* Enable RTS# pin function */ 734 ctrl &= ~SCPCR_RTSC; 735 } 736 /* Enable CTS# pin function */ 737 ctrl &= ~SCPCR_CTSC; 738 } 739 serial_port_out(port, SCPDR, data); 740 serial_port_out(port, SCPCR, ctrl); 741 } else if (sci_getreg(port, SCSPTR)->size) { 742 u16 status = serial_port_in(port, SCSPTR); 743 744 /* RTS# is always output; and active low, unless autorts */ 745 status |= SCSPTR_RTSIO; 746 if (!(port->mctrl & TIOCM_RTS)) 747 status |= SCSPTR_RTSDT; 748 else if (!s->autorts) 749 status &= ~SCSPTR_RTSDT; 750 /* CTS# and SCK are inputs */ 751 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO); 752 serial_port_out(port, SCSPTR, status); 753 } 754 } 755 756 static int sci_txfill(struct uart_port *port) 757 { 758 struct sci_port *s = to_sci_port(port); 759 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; 760 const struct plat_sci_reg *reg; 761 762 reg = sci_getreg(port, SCTFDR); 763 if (reg->size) 764 return serial_port_in(port, SCTFDR) & fifo_mask; 765 766 reg = sci_getreg(port, SCFDR); 767 if (reg->size) 768 return serial_port_in(port, SCFDR) >> 8; 769 770 return !(serial_port_in(port, SCxSR) & SCI_TDRE); 771 } 772 773 static int sci_txroom(struct uart_port *port) 774 { 775 return port->fifosize - sci_txfill(port); 776 } 777 778 static int sci_rxfill(struct uart_port *port) 779 { 780 struct sci_port *s = to_sci_port(port); 781 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; 782 const struct plat_sci_reg *reg; 783 784 reg = sci_getreg(port, SCRFDR); 785 if (reg->size) 786 return serial_port_in(port, SCRFDR) & fifo_mask; 787 788 reg = sci_getreg(port, SCFDR); 789 if (reg->size) 790 return serial_port_in(port, SCFDR) & fifo_mask; 791 792 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0; 793 } 794 795 /* ********************************************************************** * 796 * the interrupt related routines * 797 * ********************************************************************** */ 798 799 static void sci_transmit_chars(struct uart_port *port) 800 { 801 struct circ_buf *xmit = &port->state->xmit; 802 unsigned int stopped = uart_tx_stopped(port); 803 unsigned short status; 804 unsigned short ctrl; 805 int count; 806 807 status = serial_port_in(port, SCxSR); 808 if (!(status & SCxSR_TDxE(port))) { 809 ctrl = serial_port_in(port, SCSCR); 810 if (uart_circ_empty(xmit)) 811 ctrl &= ~SCSCR_TIE; 812 else 813 ctrl |= SCSCR_TIE; 814 serial_port_out(port, SCSCR, ctrl); 815 return; 816 } 817 818 count = sci_txroom(port); 819 820 do { 821 unsigned char c; 822 823 if (port->x_char) { 824 c = port->x_char; 825 port->x_char = 0; 826 } else if (!uart_circ_empty(xmit) && !stopped) { 827 c = xmit->buf[xmit->tail]; 828 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 829 } else { 830 break; 831 } 832 833 serial_port_out(port, SCxTDR, c); 834 835 port->icount.tx++; 836 } while (--count > 0); 837 838 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port)); 839 840 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 841 uart_write_wakeup(port); 842 if (uart_circ_empty(xmit)) 843 sci_stop_tx(port); 844 845 } 846 847 /* On SH3, SCIF may read end-of-break as a space->mark char */ 848 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); }) 849 850 static void sci_receive_chars(struct uart_port *port) 851 { 852 struct tty_port *tport = &port->state->port; 853 int i, count, copied = 0; 854 unsigned short status; 855 unsigned char flag; 856 857 status = serial_port_in(port, SCxSR); 858 if (!(status & SCxSR_RDxF(port))) 859 return; 860 861 while (1) { 862 /* Don't copy more bytes than there is room for in the buffer */ 863 count = tty_buffer_request_room(tport, sci_rxfill(port)); 864 865 /* If for any reason we can't copy more data, we're done! */ 866 if (count == 0) 867 break; 868 869 if (port->type == PORT_SCI) { 870 char c = serial_port_in(port, SCxRDR); 871 if (uart_handle_sysrq_char(port, c)) 872 count = 0; 873 else 874 tty_insert_flip_char(tport, c, TTY_NORMAL); 875 } else { 876 for (i = 0; i < count; i++) { 877 char c = serial_port_in(port, SCxRDR); 878 879 status = serial_port_in(port, SCxSR); 880 if (uart_handle_sysrq_char(port, c)) { 881 count--; i--; 882 continue; 883 } 884 885 /* Store data and status */ 886 if (status & SCxSR_FER(port)) { 887 flag = TTY_FRAME; 888 port->icount.frame++; 889 dev_notice(port->dev, "frame error\n"); 890 } else if (status & SCxSR_PER(port)) { 891 flag = TTY_PARITY; 892 port->icount.parity++; 893 dev_notice(port->dev, "parity error\n"); 894 } else 895 flag = TTY_NORMAL; 896 897 tty_insert_flip_char(tport, c, flag); 898 } 899 } 900 901 serial_port_in(port, SCxSR); /* dummy read */ 902 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 903 904 copied += count; 905 port->icount.rx += count; 906 } 907 908 if (copied) { 909 /* Tell the rest of the system the news. New characters! */ 910 tty_flip_buffer_push(tport); 911 } else { 912 /* TTY buffers full; read from RX reg to prevent lockup */ 913 serial_port_in(port, SCxRDR); 914 serial_port_in(port, SCxSR); /* dummy read */ 915 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 916 } 917 } 918 919 static int sci_handle_errors(struct uart_port *port) 920 { 921 int copied = 0; 922 unsigned short status = serial_port_in(port, SCxSR); 923 struct tty_port *tport = &port->state->port; 924 struct sci_port *s = to_sci_port(port); 925 926 /* Handle overruns */ 927 if (status & s->params->overrun_mask) { 928 port->icount.overrun++; 929 930 /* overrun error */ 931 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN)) 932 copied++; 933 934 dev_notice(port->dev, "overrun error\n"); 935 } 936 937 if (status & SCxSR_FER(port)) { 938 /* frame error */ 939 port->icount.frame++; 940 941 if (tty_insert_flip_char(tport, 0, TTY_FRAME)) 942 copied++; 943 944 dev_notice(port->dev, "frame error\n"); 945 } 946 947 if (status & SCxSR_PER(port)) { 948 /* parity error */ 949 port->icount.parity++; 950 951 if (tty_insert_flip_char(tport, 0, TTY_PARITY)) 952 copied++; 953 954 dev_notice(port->dev, "parity error\n"); 955 } 956 957 if (copied) 958 tty_flip_buffer_push(tport); 959 960 return copied; 961 } 962 963 static int sci_handle_fifo_overrun(struct uart_port *port) 964 { 965 struct tty_port *tport = &port->state->port; 966 struct sci_port *s = to_sci_port(port); 967 const struct plat_sci_reg *reg; 968 int copied = 0; 969 u16 status; 970 971 reg = sci_getreg(port, s->params->overrun_reg); 972 if (!reg->size) 973 return 0; 974 975 status = serial_port_in(port, s->params->overrun_reg); 976 if (status & s->params->overrun_mask) { 977 status &= ~s->params->overrun_mask; 978 serial_port_out(port, s->params->overrun_reg, status); 979 980 port->icount.overrun++; 981 982 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 983 tty_flip_buffer_push(tport); 984 985 dev_dbg(port->dev, "overrun error\n"); 986 copied++; 987 } 988 989 return copied; 990 } 991 992 static int sci_handle_breaks(struct uart_port *port) 993 { 994 int copied = 0; 995 unsigned short status = serial_port_in(port, SCxSR); 996 struct tty_port *tport = &port->state->port; 997 998 if (uart_handle_break(port)) 999 return 0; 1000 1001 if (status & SCxSR_BRK(port)) { 1002 port->icount.brk++; 1003 1004 /* Notify of BREAK */ 1005 if (tty_insert_flip_char(tport, 0, TTY_BREAK)) 1006 copied++; 1007 1008 dev_dbg(port->dev, "BREAK detected\n"); 1009 } 1010 1011 if (copied) 1012 tty_flip_buffer_push(tport); 1013 1014 copied += sci_handle_fifo_overrun(port); 1015 1016 return copied; 1017 } 1018 1019 static int scif_set_rtrg(struct uart_port *port, int rx_trig) 1020 { 1021 unsigned int bits; 1022 1023 if (rx_trig < 1) 1024 rx_trig = 1; 1025 if (rx_trig >= port->fifosize) 1026 rx_trig = port->fifosize; 1027 1028 /* HSCIF can be set to an arbitrary level. */ 1029 if (sci_getreg(port, HSRTRGR)->size) { 1030 serial_port_out(port, HSRTRGR, rx_trig); 1031 return rx_trig; 1032 } 1033 1034 switch (port->type) { 1035 case PORT_SCIF: 1036 if (rx_trig < 4) { 1037 bits = 0; 1038 rx_trig = 1; 1039 } else if (rx_trig < 8) { 1040 bits = SCFCR_RTRG0; 1041 rx_trig = 4; 1042 } else if (rx_trig < 14) { 1043 bits = SCFCR_RTRG1; 1044 rx_trig = 8; 1045 } else { 1046 bits = SCFCR_RTRG0 | SCFCR_RTRG1; 1047 rx_trig = 14; 1048 } 1049 break; 1050 case PORT_SCIFA: 1051 case PORT_SCIFB: 1052 if (rx_trig < 16) { 1053 bits = 0; 1054 rx_trig = 1; 1055 } else if (rx_trig < 32) { 1056 bits = SCFCR_RTRG0; 1057 rx_trig = 16; 1058 } else if (rx_trig < 48) { 1059 bits = SCFCR_RTRG1; 1060 rx_trig = 32; 1061 } else { 1062 bits = SCFCR_RTRG0 | SCFCR_RTRG1; 1063 rx_trig = 48; 1064 } 1065 break; 1066 default: 1067 WARN(1, "unknown FIFO configuration"); 1068 return 1; 1069 } 1070 1071 serial_port_out(port, SCFCR, 1072 (serial_port_in(port, SCFCR) & 1073 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits); 1074 1075 return rx_trig; 1076 } 1077 1078 static int scif_rtrg_enabled(struct uart_port *port) 1079 { 1080 if (sci_getreg(port, HSRTRGR)->size) 1081 return serial_port_in(port, HSRTRGR) != 0; 1082 else 1083 return (serial_port_in(port, SCFCR) & 1084 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0; 1085 } 1086 1087 static void rx_fifo_timer_fn(struct timer_list *t) 1088 { 1089 struct sci_port *s = from_timer(s, t, rx_fifo_timer); 1090 struct uart_port *port = &s->port; 1091 1092 dev_dbg(port->dev, "Rx timed out\n"); 1093 scif_set_rtrg(port, 1); 1094 } 1095 1096 static ssize_t rx_fifo_trigger_show(struct device *dev, 1097 struct device_attribute *attr, char *buf) 1098 { 1099 struct uart_port *port = dev_get_drvdata(dev); 1100 struct sci_port *sci = to_sci_port(port); 1101 1102 return sprintf(buf, "%d\n", sci->rx_trigger); 1103 } 1104 1105 static ssize_t rx_fifo_trigger_store(struct device *dev, 1106 struct device_attribute *attr, 1107 const char *buf, size_t count) 1108 { 1109 struct uart_port *port = dev_get_drvdata(dev); 1110 struct sci_port *sci = to_sci_port(port); 1111 int ret; 1112 long r; 1113 1114 ret = kstrtol(buf, 0, &r); 1115 if (ret) 1116 return ret; 1117 1118 sci->rx_trigger = scif_set_rtrg(port, r); 1119 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1120 scif_set_rtrg(port, 1); 1121 1122 return count; 1123 } 1124 1125 static DEVICE_ATTR_RW(rx_fifo_trigger); 1126 1127 static ssize_t rx_fifo_timeout_show(struct device *dev, 1128 struct device_attribute *attr, 1129 char *buf) 1130 { 1131 struct uart_port *port = dev_get_drvdata(dev); 1132 struct sci_port *sci = to_sci_port(port); 1133 int v; 1134 1135 if (port->type == PORT_HSCIF) 1136 v = sci->hscif_tot >> HSSCR_TOT_SHIFT; 1137 else 1138 v = sci->rx_fifo_timeout; 1139 1140 return sprintf(buf, "%d\n", v); 1141 } 1142 1143 static ssize_t rx_fifo_timeout_store(struct device *dev, 1144 struct device_attribute *attr, 1145 const char *buf, 1146 size_t count) 1147 { 1148 struct uart_port *port = dev_get_drvdata(dev); 1149 struct sci_port *sci = to_sci_port(port); 1150 int ret; 1151 long r; 1152 1153 ret = kstrtol(buf, 0, &r); 1154 if (ret) 1155 return ret; 1156 1157 if (port->type == PORT_HSCIF) { 1158 if (r < 0 || r > 3) 1159 return -EINVAL; 1160 sci->hscif_tot = r << HSSCR_TOT_SHIFT; 1161 } else { 1162 sci->rx_fifo_timeout = r; 1163 scif_set_rtrg(port, 1); 1164 if (r > 0) 1165 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0); 1166 } 1167 1168 return count; 1169 } 1170 1171 static DEVICE_ATTR_RW(rx_fifo_timeout); 1172 1173 1174 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1175 static void sci_dma_tx_complete(void *arg) 1176 { 1177 struct sci_port *s = arg; 1178 struct uart_port *port = &s->port; 1179 struct circ_buf *xmit = &port->state->xmit; 1180 unsigned long flags; 1181 1182 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1183 1184 spin_lock_irqsave(&port->lock, flags); 1185 1186 xmit->tail += s->tx_dma_len; 1187 xmit->tail &= UART_XMIT_SIZE - 1; 1188 1189 port->icount.tx += s->tx_dma_len; 1190 1191 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1192 uart_write_wakeup(port); 1193 1194 if (!uart_circ_empty(xmit)) { 1195 s->cookie_tx = 0; 1196 schedule_work(&s->work_tx); 1197 } else { 1198 s->cookie_tx = -EINVAL; 1199 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1200 u16 ctrl = serial_port_in(port, SCSCR); 1201 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE); 1202 } 1203 } 1204 1205 spin_unlock_irqrestore(&port->lock, flags); 1206 } 1207 1208 /* Locking: called with port lock held */ 1209 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count) 1210 { 1211 struct uart_port *port = &s->port; 1212 struct tty_port *tport = &port->state->port; 1213 int copied; 1214 1215 copied = tty_insert_flip_string(tport, buf, count); 1216 if (copied < count) 1217 port->icount.buf_overrun++; 1218 1219 port->icount.rx += copied; 1220 1221 return copied; 1222 } 1223 1224 static int sci_dma_rx_find_active(struct sci_port *s) 1225 { 1226 unsigned int i; 1227 1228 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) 1229 if (s->active_rx == s->cookie_rx[i]) 1230 return i; 1231 1232 return -1; 1233 } 1234 1235 static void sci_dma_rx_chan_invalidate(struct sci_port *s) 1236 { 1237 unsigned int i; 1238 1239 s->chan_rx = NULL; 1240 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) 1241 s->cookie_rx[i] = -EINVAL; 1242 s->active_rx = 0; 1243 } 1244 1245 static void sci_dma_rx_release(struct sci_port *s) 1246 { 1247 struct dma_chan *chan = s->chan_rx_saved; 1248 1249 s->chan_rx_saved = NULL; 1250 sci_dma_rx_chan_invalidate(s); 1251 dmaengine_terminate_sync(chan); 1252 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0], 1253 sg_dma_address(&s->sg_rx[0])); 1254 dma_release_channel(chan); 1255 } 1256 1257 static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec) 1258 { 1259 long sec = usec / 1000000; 1260 long nsec = (usec % 1000000) * 1000; 1261 ktime_t t = ktime_set(sec, nsec); 1262 1263 hrtimer_start(hrt, t, HRTIMER_MODE_REL); 1264 } 1265 1266 static void sci_dma_rx_reenable_irq(struct sci_port *s) 1267 { 1268 struct uart_port *port = &s->port; 1269 u16 scr; 1270 1271 /* Direct new serial port interrupts back to CPU */ 1272 scr = serial_port_in(port, SCSCR); 1273 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1274 scr &= ~SCSCR_RDRQE; 1275 enable_irq(s->irqs[SCIx_RXI_IRQ]); 1276 } 1277 serial_port_out(port, SCSCR, scr | SCSCR_RIE); 1278 } 1279 1280 static void sci_dma_rx_complete(void *arg) 1281 { 1282 struct sci_port *s = arg; 1283 struct dma_chan *chan = s->chan_rx; 1284 struct uart_port *port = &s->port; 1285 struct dma_async_tx_descriptor *desc; 1286 unsigned long flags; 1287 int active, count = 0; 1288 1289 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line, 1290 s->active_rx); 1291 1292 spin_lock_irqsave(&port->lock, flags); 1293 1294 active = sci_dma_rx_find_active(s); 1295 if (active >= 0) 1296 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx); 1297 1298 start_hrtimer_us(&s->rx_timer, s->rx_timeout); 1299 1300 if (count) 1301 tty_flip_buffer_push(&port->state->port); 1302 1303 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1, 1304 DMA_DEV_TO_MEM, 1305 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1306 if (!desc) 1307 goto fail; 1308 1309 desc->callback = sci_dma_rx_complete; 1310 desc->callback_param = s; 1311 s->cookie_rx[active] = dmaengine_submit(desc); 1312 if (dma_submit_error(s->cookie_rx[active])) 1313 goto fail; 1314 1315 s->active_rx = s->cookie_rx[!active]; 1316 1317 dma_async_issue_pending(chan); 1318 1319 spin_unlock_irqrestore(&port->lock, flags); 1320 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n", 1321 __func__, s->cookie_rx[active], active, s->active_rx); 1322 return; 1323 1324 fail: 1325 spin_unlock_irqrestore(&port->lock, flags); 1326 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n"); 1327 /* Switch to PIO */ 1328 spin_lock_irqsave(&port->lock, flags); 1329 dmaengine_terminate_async(chan); 1330 sci_dma_rx_chan_invalidate(s); 1331 sci_dma_rx_reenable_irq(s); 1332 spin_unlock_irqrestore(&port->lock, flags); 1333 } 1334 1335 static void sci_dma_tx_release(struct sci_port *s) 1336 { 1337 struct dma_chan *chan = s->chan_tx_saved; 1338 1339 cancel_work_sync(&s->work_tx); 1340 s->chan_tx_saved = s->chan_tx = NULL; 1341 s->cookie_tx = -EINVAL; 1342 dmaengine_terminate_sync(chan); 1343 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE, 1344 DMA_TO_DEVICE); 1345 dma_release_channel(chan); 1346 } 1347 1348 static int sci_dma_rx_submit(struct sci_port *s, bool port_lock_held) 1349 { 1350 struct dma_chan *chan = s->chan_rx; 1351 struct uart_port *port = &s->port; 1352 unsigned long flags; 1353 int i; 1354 1355 for (i = 0; i < 2; i++) { 1356 struct scatterlist *sg = &s->sg_rx[i]; 1357 struct dma_async_tx_descriptor *desc; 1358 1359 desc = dmaengine_prep_slave_sg(chan, 1360 sg, 1, DMA_DEV_TO_MEM, 1361 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1362 if (!desc) 1363 goto fail; 1364 1365 desc->callback = sci_dma_rx_complete; 1366 desc->callback_param = s; 1367 s->cookie_rx[i] = dmaengine_submit(desc); 1368 if (dma_submit_error(s->cookie_rx[i])) 1369 goto fail; 1370 1371 } 1372 1373 s->active_rx = s->cookie_rx[0]; 1374 1375 dma_async_issue_pending(chan); 1376 return 0; 1377 1378 fail: 1379 /* Switch to PIO */ 1380 if (!port_lock_held) 1381 spin_lock_irqsave(&port->lock, flags); 1382 if (i) 1383 dmaengine_terminate_async(chan); 1384 sci_dma_rx_chan_invalidate(s); 1385 sci_start_rx(port); 1386 if (!port_lock_held) 1387 spin_unlock_irqrestore(&port->lock, flags); 1388 return -EAGAIN; 1389 } 1390 1391 static void sci_dma_tx_work_fn(struct work_struct *work) 1392 { 1393 struct sci_port *s = container_of(work, struct sci_port, work_tx); 1394 struct dma_async_tx_descriptor *desc; 1395 struct dma_chan *chan = s->chan_tx; 1396 struct uart_port *port = &s->port; 1397 struct circ_buf *xmit = &port->state->xmit; 1398 unsigned long flags; 1399 dma_addr_t buf; 1400 int head, tail; 1401 1402 /* 1403 * DMA is idle now. 1404 * Port xmit buffer is already mapped, and it is one page... Just adjust 1405 * offsets and lengths. Since it is a circular buffer, we have to 1406 * transmit till the end, and then the rest. Take the port lock to get a 1407 * consistent xmit buffer state. 1408 */ 1409 spin_lock_irq(&port->lock); 1410 head = xmit->head; 1411 tail = xmit->tail; 1412 buf = s->tx_dma_addr + (tail & (UART_XMIT_SIZE - 1)); 1413 s->tx_dma_len = min_t(unsigned int, 1414 CIRC_CNT(head, tail, UART_XMIT_SIZE), 1415 CIRC_CNT_TO_END(head, tail, UART_XMIT_SIZE)); 1416 if (!s->tx_dma_len) { 1417 /* Transmit buffer has been flushed */ 1418 spin_unlock_irq(&port->lock); 1419 return; 1420 } 1421 1422 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len, 1423 DMA_MEM_TO_DEV, 1424 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1425 if (!desc) { 1426 spin_unlock_irq(&port->lock); 1427 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n"); 1428 goto switch_to_pio; 1429 } 1430 1431 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len, 1432 DMA_TO_DEVICE); 1433 1434 desc->callback = sci_dma_tx_complete; 1435 desc->callback_param = s; 1436 s->cookie_tx = dmaengine_submit(desc); 1437 if (dma_submit_error(s->cookie_tx)) { 1438 spin_unlock_irq(&port->lock); 1439 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n"); 1440 goto switch_to_pio; 1441 } 1442 1443 spin_unlock_irq(&port->lock); 1444 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", 1445 __func__, xmit->buf, tail, head, s->cookie_tx); 1446 1447 dma_async_issue_pending(chan); 1448 return; 1449 1450 switch_to_pio: 1451 spin_lock_irqsave(&port->lock, flags); 1452 s->chan_tx = NULL; 1453 sci_start_tx(port); 1454 spin_unlock_irqrestore(&port->lock, flags); 1455 return; 1456 } 1457 1458 static enum hrtimer_restart sci_dma_rx_timer_fn(struct hrtimer *t) 1459 { 1460 struct sci_port *s = container_of(t, struct sci_port, rx_timer); 1461 struct dma_chan *chan = s->chan_rx; 1462 struct uart_port *port = &s->port; 1463 struct dma_tx_state state; 1464 enum dma_status status; 1465 unsigned long flags; 1466 unsigned int read; 1467 int active, count; 1468 1469 dev_dbg(port->dev, "DMA Rx timed out\n"); 1470 1471 spin_lock_irqsave(&port->lock, flags); 1472 1473 active = sci_dma_rx_find_active(s); 1474 if (active < 0) { 1475 spin_unlock_irqrestore(&port->lock, flags); 1476 return HRTIMER_NORESTART; 1477 } 1478 1479 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); 1480 if (status == DMA_COMPLETE) { 1481 spin_unlock_irqrestore(&port->lock, flags); 1482 dev_dbg(port->dev, "Cookie %d #%d has already completed\n", 1483 s->active_rx, active); 1484 1485 /* Let packet complete handler take care of the packet */ 1486 return HRTIMER_NORESTART; 1487 } 1488 1489 dmaengine_pause(chan); 1490 1491 /* 1492 * sometimes DMA transfer doesn't stop even if it is stopped and 1493 * data keeps on coming until transaction is complete so check 1494 * for DMA_COMPLETE again 1495 * Let packet complete handler take care of the packet 1496 */ 1497 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); 1498 if (status == DMA_COMPLETE) { 1499 spin_unlock_irqrestore(&port->lock, flags); 1500 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped"); 1501 return HRTIMER_NORESTART; 1502 } 1503 1504 /* Handle incomplete DMA receive */ 1505 dmaengine_terminate_async(s->chan_rx); 1506 read = sg_dma_len(&s->sg_rx[active]) - state.residue; 1507 1508 if (read) { 1509 count = sci_dma_rx_push(s, s->rx_buf[active], read); 1510 if (count) 1511 tty_flip_buffer_push(&port->state->port); 1512 } 1513 1514 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1515 sci_dma_rx_submit(s, true); 1516 1517 sci_dma_rx_reenable_irq(s); 1518 1519 spin_unlock_irqrestore(&port->lock, flags); 1520 1521 return HRTIMER_NORESTART; 1522 } 1523 1524 static struct dma_chan *sci_request_dma_chan(struct uart_port *port, 1525 enum dma_transfer_direction dir) 1526 { 1527 struct dma_chan *chan; 1528 struct dma_slave_config cfg; 1529 int ret; 1530 1531 chan = dma_request_slave_channel(port->dev, 1532 dir == DMA_MEM_TO_DEV ? "tx" : "rx"); 1533 if (!chan) { 1534 dev_dbg(port->dev, "dma_request_slave_channel failed\n"); 1535 return NULL; 1536 } 1537 1538 memset(&cfg, 0, sizeof(cfg)); 1539 cfg.direction = dir; 1540 if (dir == DMA_MEM_TO_DEV) { 1541 cfg.dst_addr = port->mapbase + 1542 (sci_getreg(port, SCxTDR)->offset << port->regshift); 1543 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1544 } else { 1545 cfg.src_addr = port->mapbase + 1546 (sci_getreg(port, SCxRDR)->offset << port->regshift); 1547 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1548 } 1549 1550 ret = dmaengine_slave_config(chan, &cfg); 1551 if (ret) { 1552 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret); 1553 dma_release_channel(chan); 1554 return NULL; 1555 } 1556 1557 return chan; 1558 } 1559 1560 static void sci_request_dma(struct uart_port *port) 1561 { 1562 struct sci_port *s = to_sci_port(port); 1563 struct dma_chan *chan; 1564 1565 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line); 1566 1567 /* 1568 * DMA on console may interfere with Kernel log messages which use 1569 * plain putchar(). So, simply don't use it with a console. 1570 */ 1571 if (uart_console(port)) 1572 return; 1573 1574 if (!port->dev->of_node) 1575 return; 1576 1577 s->cookie_tx = -EINVAL; 1578 1579 /* 1580 * Don't request a dma channel if no channel was specified 1581 * in the device tree. 1582 */ 1583 if (!of_find_property(port->dev->of_node, "dmas", NULL)) 1584 return; 1585 1586 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV); 1587 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan); 1588 if (chan) { 1589 /* UART circular tx buffer is an aligned page. */ 1590 s->tx_dma_addr = dma_map_single(chan->device->dev, 1591 port->state->xmit.buf, 1592 UART_XMIT_SIZE, 1593 DMA_TO_DEVICE); 1594 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) { 1595 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n"); 1596 dma_release_channel(chan); 1597 } else { 1598 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n", 1599 __func__, UART_XMIT_SIZE, 1600 port->state->xmit.buf, &s->tx_dma_addr); 1601 1602 INIT_WORK(&s->work_tx, sci_dma_tx_work_fn); 1603 s->chan_tx_saved = s->chan_tx = chan; 1604 } 1605 } 1606 1607 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM); 1608 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan); 1609 if (chan) { 1610 unsigned int i; 1611 dma_addr_t dma; 1612 void *buf; 1613 1614 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize); 1615 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2, 1616 &dma, GFP_KERNEL); 1617 if (!buf) { 1618 dev_warn(port->dev, 1619 "Failed to allocate Rx dma buffer, using PIO\n"); 1620 dma_release_channel(chan); 1621 return; 1622 } 1623 1624 for (i = 0; i < 2; i++) { 1625 struct scatterlist *sg = &s->sg_rx[i]; 1626 1627 sg_init_table(sg, 1); 1628 s->rx_buf[i] = buf; 1629 sg_dma_address(sg) = dma; 1630 sg_dma_len(sg) = s->buf_len_rx; 1631 1632 buf += s->buf_len_rx; 1633 dma += s->buf_len_rx; 1634 } 1635 1636 hrtimer_init(&s->rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 1637 s->rx_timer.function = sci_dma_rx_timer_fn; 1638 1639 s->chan_rx_saved = s->chan_rx = chan; 1640 1641 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1642 sci_dma_rx_submit(s, false); 1643 } 1644 } 1645 1646 static void sci_free_dma(struct uart_port *port) 1647 { 1648 struct sci_port *s = to_sci_port(port); 1649 1650 if (s->chan_tx_saved) 1651 sci_dma_tx_release(s); 1652 if (s->chan_rx_saved) 1653 sci_dma_rx_release(s); 1654 } 1655 1656 static void sci_flush_buffer(struct uart_port *port) 1657 { 1658 struct sci_port *s = to_sci_port(port); 1659 1660 /* 1661 * In uart_flush_buffer(), the xmit circular buffer has just been 1662 * cleared, so we have to reset tx_dma_len accordingly, and stop any 1663 * pending transfers 1664 */ 1665 s->tx_dma_len = 0; 1666 if (s->chan_tx) { 1667 dmaengine_terminate_async(s->chan_tx); 1668 s->cookie_tx = -EINVAL; 1669 } 1670 } 1671 #else /* !CONFIG_SERIAL_SH_SCI_DMA */ 1672 static inline void sci_request_dma(struct uart_port *port) 1673 { 1674 } 1675 1676 static inline void sci_free_dma(struct uart_port *port) 1677 { 1678 } 1679 1680 #define sci_flush_buffer NULL 1681 #endif /* !CONFIG_SERIAL_SH_SCI_DMA */ 1682 1683 static irqreturn_t sci_rx_interrupt(int irq, void *ptr) 1684 { 1685 struct uart_port *port = ptr; 1686 struct sci_port *s = to_sci_port(port); 1687 1688 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1689 if (s->chan_rx) { 1690 u16 scr = serial_port_in(port, SCSCR); 1691 u16 ssr = serial_port_in(port, SCxSR); 1692 1693 /* Disable future Rx interrupts */ 1694 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1695 disable_irq_nosync(irq); 1696 scr |= SCSCR_RDRQE; 1697 } else { 1698 if (sci_dma_rx_submit(s, false) < 0) 1699 goto handle_pio; 1700 1701 scr &= ~SCSCR_RIE; 1702 } 1703 serial_port_out(port, SCSCR, scr); 1704 /* Clear current interrupt */ 1705 serial_port_out(port, SCxSR, 1706 ssr & ~(SCIF_DR | SCxSR_RDxF(port))); 1707 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n", 1708 jiffies, s->rx_timeout); 1709 start_hrtimer_us(&s->rx_timer, s->rx_timeout); 1710 1711 return IRQ_HANDLED; 1712 } 1713 1714 handle_pio: 1715 #endif 1716 1717 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) { 1718 if (!scif_rtrg_enabled(port)) 1719 scif_set_rtrg(port, s->rx_trigger); 1720 1721 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP( 1722 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000)); 1723 } 1724 1725 /* I think sci_receive_chars has to be called irrespective 1726 * of whether the I_IXOFF is set, otherwise, how is the interrupt 1727 * to be disabled? 1728 */ 1729 sci_receive_chars(port); 1730 1731 return IRQ_HANDLED; 1732 } 1733 1734 static irqreturn_t sci_tx_interrupt(int irq, void *ptr) 1735 { 1736 struct uart_port *port = ptr; 1737 unsigned long flags; 1738 1739 spin_lock_irqsave(&port->lock, flags); 1740 sci_transmit_chars(port); 1741 spin_unlock_irqrestore(&port->lock, flags); 1742 1743 return IRQ_HANDLED; 1744 } 1745 1746 static irqreturn_t sci_br_interrupt(int irq, void *ptr) 1747 { 1748 struct uart_port *port = ptr; 1749 1750 /* Handle BREAKs */ 1751 sci_handle_breaks(port); 1752 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port)); 1753 1754 return IRQ_HANDLED; 1755 } 1756 1757 static irqreturn_t sci_er_interrupt(int irq, void *ptr) 1758 { 1759 struct uart_port *port = ptr; 1760 struct sci_port *s = to_sci_port(port); 1761 1762 if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) { 1763 /* Break and Error interrupts are muxed */ 1764 unsigned short ssr_status = serial_port_in(port, SCxSR); 1765 1766 /* Break Interrupt */ 1767 if (ssr_status & SCxSR_BRK(port)) 1768 sci_br_interrupt(irq, ptr); 1769 1770 /* Break only? */ 1771 if (!(ssr_status & SCxSR_ERRORS(port))) 1772 return IRQ_HANDLED; 1773 } 1774 1775 /* Handle errors */ 1776 if (port->type == PORT_SCI) { 1777 if (sci_handle_errors(port)) { 1778 /* discard character in rx buffer */ 1779 serial_port_in(port, SCxSR); 1780 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 1781 } 1782 } else { 1783 sci_handle_fifo_overrun(port); 1784 if (!s->chan_rx) 1785 sci_receive_chars(port); 1786 } 1787 1788 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); 1789 1790 /* Kick the transmission */ 1791 if (!s->chan_tx) 1792 sci_tx_interrupt(irq, ptr); 1793 1794 return IRQ_HANDLED; 1795 } 1796 1797 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) 1798 { 1799 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0; 1800 struct uart_port *port = ptr; 1801 struct sci_port *s = to_sci_port(port); 1802 irqreturn_t ret = IRQ_NONE; 1803 1804 ssr_status = serial_port_in(port, SCxSR); 1805 scr_status = serial_port_in(port, SCSCR); 1806 if (s->params->overrun_reg == SCxSR) 1807 orer_status = ssr_status; 1808 else if (sci_getreg(port, s->params->overrun_reg)->size) 1809 orer_status = serial_port_in(port, s->params->overrun_reg); 1810 1811 err_enabled = scr_status & port_rx_irq_mask(port); 1812 1813 /* Tx Interrupt */ 1814 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) && 1815 !s->chan_tx) 1816 ret = sci_tx_interrupt(irq, ptr); 1817 1818 /* 1819 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF / 1820 * DR flags 1821 */ 1822 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) && 1823 (scr_status & SCSCR_RIE)) 1824 ret = sci_rx_interrupt(irq, ptr); 1825 1826 /* Error Interrupt */ 1827 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled) 1828 ret = sci_er_interrupt(irq, ptr); 1829 1830 /* Break Interrupt */ 1831 if ((ssr_status & SCxSR_BRK(port)) && err_enabled) 1832 ret = sci_br_interrupt(irq, ptr); 1833 1834 /* Overrun Interrupt */ 1835 if (orer_status & s->params->overrun_mask) { 1836 sci_handle_fifo_overrun(port); 1837 ret = IRQ_HANDLED; 1838 } 1839 1840 return ret; 1841 } 1842 1843 static const struct sci_irq_desc { 1844 const char *desc; 1845 irq_handler_t handler; 1846 } sci_irq_desc[] = { 1847 /* 1848 * Split out handlers, the default case. 1849 */ 1850 [SCIx_ERI_IRQ] = { 1851 .desc = "rx err", 1852 .handler = sci_er_interrupt, 1853 }, 1854 1855 [SCIx_RXI_IRQ] = { 1856 .desc = "rx full", 1857 .handler = sci_rx_interrupt, 1858 }, 1859 1860 [SCIx_TXI_IRQ] = { 1861 .desc = "tx empty", 1862 .handler = sci_tx_interrupt, 1863 }, 1864 1865 [SCIx_BRI_IRQ] = { 1866 .desc = "break", 1867 .handler = sci_br_interrupt, 1868 }, 1869 1870 [SCIx_DRI_IRQ] = { 1871 .desc = "rx ready", 1872 .handler = sci_rx_interrupt, 1873 }, 1874 1875 [SCIx_TEI_IRQ] = { 1876 .desc = "tx end", 1877 .handler = sci_tx_interrupt, 1878 }, 1879 1880 /* 1881 * Special muxed handler. 1882 */ 1883 [SCIx_MUX_IRQ] = { 1884 .desc = "mux", 1885 .handler = sci_mpxed_interrupt, 1886 }, 1887 }; 1888 1889 static int sci_request_irq(struct sci_port *port) 1890 { 1891 struct uart_port *up = &port->port; 1892 int i, j, w, ret = 0; 1893 1894 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) { 1895 const struct sci_irq_desc *desc; 1896 int irq; 1897 1898 /* Check if already registered (muxed) */ 1899 for (w = 0; w < i; w++) 1900 if (port->irqs[w] == port->irqs[i]) 1901 w = i + 1; 1902 if (w > i) 1903 continue; 1904 1905 if (SCIx_IRQ_IS_MUXED(port)) { 1906 i = SCIx_MUX_IRQ; 1907 irq = up->irq; 1908 } else { 1909 irq = port->irqs[i]; 1910 1911 /* 1912 * Certain port types won't support all of the 1913 * available interrupt sources. 1914 */ 1915 if (unlikely(irq < 0)) 1916 continue; 1917 } 1918 1919 desc = sci_irq_desc + i; 1920 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s", 1921 dev_name(up->dev), desc->desc); 1922 if (!port->irqstr[j]) { 1923 ret = -ENOMEM; 1924 goto out_nomem; 1925 } 1926 1927 ret = request_irq(irq, desc->handler, up->irqflags, 1928 port->irqstr[j], port); 1929 if (unlikely(ret)) { 1930 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc); 1931 goto out_noirq; 1932 } 1933 } 1934 1935 return 0; 1936 1937 out_noirq: 1938 while (--i >= 0) 1939 free_irq(port->irqs[i], port); 1940 1941 out_nomem: 1942 while (--j >= 0) 1943 kfree(port->irqstr[j]); 1944 1945 return ret; 1946 } 1947 1948 static void sci_free_irq(struct sci_port *port) 1949 { 1950 int i, j; 1951 1952 /* 1953 * Intentionally in reverse order so we iterate over the muxed 1954 * IRQ first. 1955 */ 1956 for (i = 0; i < SCIx_NR_IRQS; i++) { 1957 int irq = port->irqs[i]; 1958 1959 /* 1960 * Certain port types won't support all of the available 1961 * interrupt sources. 1962 */ 1963 if (unlikely(irq < 0)) 1964 continue; 1965 1966 /* Check if already freed (irq was muxed) */ 1967 for (j = 0; j < i; j++) 1968 if (port->irqs[j] == irq) 1969 j = i + 1; 1970 if (j > i) 1971 continue; 1972 1973 free_irq(port->irqs[i], port); 1974 kfree(port->irqstr[i]); 1975 1976 if (SCIx_IRQ_IS_MUXED(port)) { 1977 /* If there's only one IRQ, we're done. */ 1978 return; 1979 } 1980 } 1981 } 1982 1983 static unsigned int sci_tx_empty(struct uart_port *port) 1984 { 1985 unsigned short status = serial_port_in(port, SCxSR); 1986 unsigned short in_tx_fifo = sci_txfill(port); 1987 1988 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0; 1989 } 1990 1991 static void sci_set_rts(struct uart_port *port, bool state) 1992 { 1993 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1994 u16 data = serial_port_in(port, SCPDR); 1995 1996 /* Active low */ 1997 if (state) 1998 data &= ~SCPDR_RTSD; 1999 else 2000 data |= SCPDR_RTSD; 2001 serial_port_out(port, SCPDR, data); 2002 2003 /* RTS# is output */ 2004 serial_port_out(port, SCPCR, 2005 serial_port_in(port, SCPCR) | SCPCR_RTSC); 2006 } else if (sci_getreg(port, SCSPTR)->size) { 2007 u16 ctrl = serial_port_in(port, SCSPTR); 2008 2009 /* Active low */ 2010 if (state) 2011 ctrl &= ~SCSPTR_RTSDT; 2012 else 2013 ctrl |= SCSPTR_RTSDT; 2014 serial_port_out(port, SCSPTR, ctrl); 2015 } 2016 } 2017 2018 static bool sci_get_cts(struct uart_port *port) 2019 { 2020 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 2021 /* Active low */ 2022 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD); 2023 } else if (sci_getreg(port, SCSPTR)->size) { 2024 /* Active low */ 2025 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT); 2026 } 2027 2028 return true; 2029 } 2030 2031 /* 2032 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally 2033 * CTS/RTS is supported in hardware by at least one port and controlled 2034 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently 2035 * handled via the ->init_pins() op, which is a bit of a one-way street, 2036 * lacking any ability to defer pin control -- this will later be 2037 * converted over to the GPIO framework). 2038 * 2039 * Other modes (such as loopback) are supported generically on certain 2040 * port types, but not others. For these it's sufficient to test for the 2041 * existence of the support register and simply ignore the port type. 2042 */ 2043 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) 2044 { 2045 struct sci_port *s = to_sci_port(port); 2046 2047 if (mctrl & TIOCM_LOOP) { 2048 const struct plat_sci_reg *reg; 2049 2050 /* 2051 * Standard loopback mode for SCFCR ports. 2052 */ 2053 reg = sci_getreg(port, SCFCR); 2054 if (reg->size) 2055 serial_port_out(port, SCFCR, 2056 serial_port_in(port, SCFCR) | 2057 SCFCR_LOOP); 2058 } 2059 2060 mctrl_gpio_set(s->gpios, mctrl); 2061 2062 if (!s->has_rtscts) 2063 return; 2064 2065 if (!(mctrl & TIOCM_RTS)) { 2066 /* Disable Auto RTS */ 2067 serial_port_out(port, SCFCR, 2068 serial_port_in(port, SCFCR) & ~SCFCR_MCE); 2069 2070 /* Clear RTS */ 2071 sci_set_rts(port, 0); 2072 } else if (s->autorts) { 2073 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 2074 /* Enable RTS# pin function */ 2075 serial_port_out(port, SCPCR, 2076 serial_port_in(port, SCPCR) & ~SCPCR_RTSC); 2077 } 2078 2079 /* Enable Auto RTS */ 2080 serial_port_out(port, SCFCR, 2081 serial_port_in(port, SCFCR) | SCFCR_MCE); 2082 } else { 2083 /* Set RTS */ 2084 sci_set_rts(port, 1); 2085 } 2086 } 2087 2088 static unsigned int sci_get_mctrl(struct uart_port *port) 2089 { 2090 struct sci_port *s = to_sci_port(port); 2091 struct mctrl_gpios *gpios = s->gpios; 2092 unsigned int mctrl = 0; 2093 2094 mctrl_gpio_get(gpios, &mctrl); 2095 2096 /* 2097 * CTS/RTS is handled in hardware when supported, while nothing 2098 * else is wired up. 2099 */ 2100 if (s->autorts) { 2101 if (sci_get_cts(port)) 2102 mctrl |= TIOCM_CTS; 2103 } else if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)) { 2104 mctrl |= TIOCM_CTS; 2105 } 2106 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)) 2107 mctrl |= TIOCM_DSR; 2108 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)) 2109 mctrl |= TIOCM_CAR; 2110 2111 return mctrl; 2112 } 2113 2114 static void sci_enable_ms(struct uart_port *port) 2115 { 2116 mctrl_gpio_enable_ms(to_sci_port(port)->gpios); 2117 } 2118 2119 static void sci_break_ctl(struct uart_port *port, int break_state) 2120 { 2121 unsigned short scscr, scsptr; 2122 unsigned long flags; 2123 2124 /* check wheter the port has SCSPTR */ 2125 if (!sci_getreg(port, SCSPTR)->size) { 2126 /* 2127 * Not supported by hardware. Most parts couple break and rx 2128 * interrupts together, with break detection always enabled. 2129 */ 2130 return; 2131 } 2132 2133 spin_lock_irqsave(&port->lock, flags); 2134 scsptr = serial_port_in(port, SCSPTR); 2135 scscr = serial_port_in(port, SCSCR); 2136 2137 if (break_state == -1) { 2138 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT; 2139 scscr &= ~SCSCR_TE; 2140 } else { 2141 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO; 2142 scscr |= SCSCR_TE; 2143 } 2144 2145 serial_port_out(port, SCSPTR, scsptr); 2146 serial_port_out(port, SCSCR, scscr); 2147 spin_unlock_irqrestore(&port->lock, flags); 2148 } 2149 2150 static int sci_startup(struct uart_port *port) 2151 { 2152 struct sci_port *s = to_sci_port(port); 2153 int ret; 2154 2155 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 2156 2157 sci_request_dma(port); 2158 2159 ret = sci_request_irq(s); 2160 if (unlikely(ret < 0)) { 2161 sci_free_dma(port); 2162 return ret; 2163 } 2164 2165 return 0; 2166 } 2167 2168 static void sci_shutdown(struct uart_port *port) 2169 { 2170 struct sci_port *s = to_sci_port(port); 2171 unsigned long flags; 2172 u16 scr; 2173 2174 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 2175 2176 s->autorts = false; 2177 mctrl_gpio_disable_ms(to_sci_port(port)->gpios); 2178 2179 spin_lock_irqsave(&port->lock, flags); 2180 sci_stop_rx(port); 2181 sci_stop_tx(port); 2182 /* 2183 * Stop RX and TX, disable related interrupts, keep clock source 2184 * and HSCIF TOT bits 2185 */ 2186 scr = serial_port_in(port, SCSCR); 2187 serial_port_out(port, SCSCR, scr & 2188 (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot)); 2189 spin_unlock_irqrestore(&port->lock, flags); 2190 2191 #ifdef CONFIG_SERIAL_SH_SCI_DMA 2192 if (s->chan_rx_saved) { 2193 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__, 2194 port->line); 2195 hrtimer_cancel(&s->rx_timer); 2196 } 2197 #endif 2198 2199 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) 2200 del_timer_sync(&s->rx_fifo_timer); 2201 sci_free_irq(s); 2202 sci_free_dma(port); 2203 } 2204 2205 static int sci_sck_calc(struct sci_port *s, unsigned int bps, 2206 unsigned int *srr) 2207 { 2208 unsigned long freq = s->clk_rates[SCI_SCK]; 2209 int err, min_err = INT_MAX; 2210 unsigned int sr; 2211 2212 if (s->port.type != PORT_HSCIF) 2213 freq *= 2; 2214 2215 for_each_sr(sr, s) { 2216 err = DIV_ROUND_CLOSEST(freq, sr) - bps; 2217 if (abs(err) >= abs(min_err)) 2218 continue; 2219 2220 min_err = err; 2221 *srr = sr - 1; 2222 2223 if (!err) 2224 break; 2225 } 2226 2227 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err, 2228 *srr + 1); 2229 return min_err; 2230 } 2231 2232 static int sci_brg_calc(struct sci_port *s, unsigned int bps, 2233 unsigned long freq, unsigned int *dlr, 2234 unsigned int *srr) 2235 { 2236 int err, min_err = INT_MAX; 2237 unsigned int sr, dl; 2238 2239 if (s->port.type != PORT_HSCIF) 2240 freq *= 2; 2241 2242 for_each_sr(sr, s) { 2243 dl = DIV_ROUND_CLOSEST(freq, sr * bps); 2244 dl = clamp(dl, 1U, 65535U); 2245 2246 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps; 2247 if (abs(err) >= abs(min_err)) 2248 continue; 2249 2250 min_err = err; 2251 *dlr = dl; 2252 *srr = sr - 1; 2253 2254 if (!err) 2255 break; 2256 } 2257 2258 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps, 2259 min_err, *dlr, *srr + 1); 2260 return min_err; 2261 } 2262 2263 /* calculate sample rate, BRR, and clock select */ 2264 static int sci_scbrr_calc(struct sci_port *s, unsigned int bps, 2265 unsigned int *brr, unsigned int *srr, 2266 unsigned int *cks) 2267 { 2268 unsigned long freq = s->clk_rates[SCI_FCK]; 2269 unsigned int sr, br, prediv, scrate, c; 2270 int err, min_err = INT_MAX; 2271 2272 if (s->port.type != PORT_HSCIF) 2273 freq *= 2; 2274 2275 /* 2276 * Find the combination of sample rate and clock select with the 2277 * smallest deviation from the desired baud rate. 2278 * Prefer high sample rates to maximise the receive margin. 2279 * 2280 * M: Receive margin (%) 2281 * N: Ratio of bit rate to clock (N = sampling rate) 2282 * D: Clock duty (D = 0 to 1.0) 2283 * L: Frame length (L = 9 to 12) 2284 * F: Absolute value of clock frequency deviation 2285 * 2286 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) - 2287 * (|D - 0.5| / N * (1 + F))| 2288 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation. 2289 */ 2290 for_each_sr(sr, s) { 2291 for (c = 0; c <= 3; c++) { 2292 /* integerized formulas from HSCIF documentation */ 2293 prediv = sr * (1 << (2 * c + 1)); 2294 2295 /* 2296 * We need to calculate: 2297 * 2298 * br = freq / (prediv * bps) clamped to [1..256] 2299 * err = freq / (br * prediv) - bps 2300 * 2301 * Watch out for overflow when calculating the desired 2302 * sampling clock rate! 2303 */ 2304 if (bps > UINT_MAX / prediv) 2305 break; 2306 2307 scrate = prediv * bps; 2308 br = DIV_ROUND_CLOSEST(freq, scrate); 2309 br = clamp(br, 1U, 256U); 2310 2311 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps; 2312 if (abs(err) >= abs(min_err)) 2313 continue; 2314 2315 min_err = err; 2316 *brr = br - 1; 2317 *srr = sr - 1; 2318 *cks = c; 2319 2320 if (!err) 2321 goto found; 2322 } 2323 } 2324 2325 found: 2326 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps, 2327 min_err, *brr, *srr + 1, *cks); 2328 return min_err; 2329 } 2330 2331 static void sci_reset(struct uart_port *port) 2332 { 2333 const struct plat_sci_reg *reg; 2334 unsigned int status; 2335 struct sci_port *s = to_sci_port(port); 2336 2337 serial_port_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */ 2338 2339 reg = sci_getreg(port, SCFCR); 2340 if (reg->size) 2341 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); 2342 2343 sci_clear_SCxSR(port, 2344 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) & 2345 SCxSR_BREAK_CLEAR(port)); 2346 if (sci_getreg(port, SCLSR)->size) { 2347 status = serial_port_in(port, SCLSR); 2348 status &= ~(SCLSR_TO | SCLSR_ORER); 2349 serial_port_out(port, SCLSR, status); 2350 } 2351 2352 if (s->rx_trigger > 1) { 2353 if (s->rx_fifo_timeout) { 2354 scif_set_rtrg(port, 1); 2355 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0); 2356 } else { 2357 if (port->type == PORT_SCIFA || 2358 port->type == PORT_SCIFB) 2359 scif_set_rtrg(port, 1); 2360 else 2361 scif_set_rtrg(port, s->rx_trigger); 2362 } 2363 } 2364 } 2365 2366 static void sci_set_termios(struct uart_port *port, struct ktermios *termios, 2367 struct ktermios *old) 2368 { 2369 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits; 2370 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0; 2371 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0; 2372 struct sci_port *s = to_sci_port(port); 2373 const struct plat_sci_reg *reg; 2374 int min_err = INT_MAX, err; 2375 unsigned long max_freq = 0; 2376 int best_clk = -1; 2377 unsigned long flags; 2378 2379 if ((termios->c_cflag & CSIZE) == CS7) 2380 smr_val |= SCSMR_CHR; 2381 if (termios->c_cflag & PARENB) 2382 smr_val |= SCSMR_PE; 2383 if (termios->c_cflag & PARODD) 2384 smr_val |= SCSMR_PE | SCSMR_ODD; 2385 if (termios->c_cflag & CSTOPB) 2386 smr_val |= SCSMR_STOP; 2387 2388 /* 2389 * earlyprintk comes here early on with port->uartclk set to zero. 2390 * the clock framework is not up and running at this point so here 2391 * we assume that 115200 is the maximum baud rate. please note that 2392 * the baud rate is not programmed during earlyprintk - it is assumed 2393 * that the previous boot loader has enabled required clocks and 2394 * setup the baud rate generator hardware for us already. 2395 */ 2396 if (!port->uartclk) { 2397 baud = uart_get_baud_rate(port, termios, old, 0, 115200); 2398 goto done; 2399 } 2400 2401 for (i = 0; i < SCI_NUM_CLKS; i++) 2402 max_freq = max(max_freq, s->clk_rates[i]); 2403 2404 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s)); 2405 if (!baud) 2406 goto done; 2407 2408 /* 2409 * There can be multiple sources for the sampling clock. Find the one 2410 * that gives us the smallest deviation from the desired baud rate. 2411 */ 2412 2413 /* Optional Undivided External Clock */ 2414 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA && 2415 port->type != PORT_SCIFB) { 2416 err = sci_sck_calc(s, baud, &srr1); 2417 if (abs(err) < abs(min_err)) { 2418 best_clk = SCI_SCK; 2419 scr_val = SCSCR_CKE1; 2420 sccks = SCCKS_CKS; 2421 min_err = err; 2422 srr = srr1; 2423 if (!err) 2424 goto done; 2425 } 2426 } 2427 2428 /* Optional BRG Frequency Divided External Clock */ 2429 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) { 2430 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1, 2431 &srr1); 2432 if (abs(err) < abs(min_err)) { 2433 best_clk = SCI_SCIF_CLK; 2434 scr_val = SCSCR_CKE1; 2435 sccks = 0; 2436 min_err = err; 2437 dl = dl1; 2438 srr = srr1; 2439 if (!err) 2440 goto done; 2441 } 2442 } 2443 2444 /* Optional BRG Frequency Divided Internal Clock */ 2445 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) { 2446 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1, 2447 &srr1); 2448 if (abs(err) < abs(min_err)) { 2449 best_clk = SCI_BRG_INT; 2450 scr_val = SCSCR_CKE1; 2451 sccks = SCCKS_XIN; 2452 min_err = err; 2453 dl = dl1; 2454 srr = srr1; 2455 if (!min_err) 2456 goto done; 2457 } 2458 } 2459 2460 /* Divided Functional Clock using standard Bit Rate Register */ 2461 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1); 2462 if (abs(err) < abs(min_err)) { 2463 best_clk = SCI_FCK; 2464 scr_val = 0; 2465 min_err = err; 2466 brr = brr1; 2467 srr = srr1; 2468 cks = cks1; 2469 } 2470 2471 done: 2472 if (best_clk >= 0) 2473 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n", 2474 s->clks[best_clk], baud, min_err); 2475 2476 sci_port_enable(s); 2477 2478 /* 2479 * Program the optional External Baud Rate Generator (BRG) first. 2480 * It controls the mux to select (H)SCK or frequency divided clock. 2481 */ 2482 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) { 2483 serial_port_out(port, SCDL, dl); 2484 serial_port_out(port, SCCKS, sccks); 2485 } 2486 2487 spin_lock_irqsave(&port->lock, flags); 2488 2489 sci_reset(port); 2490 2491 uart_update_timeout(port, termios->c_cflag, baud); 2492 2493 /* byte size and parity */ 2494 switch (termios->c_cflag & CSIZE) { 2495 case CS5: 2496 bits = 7; 2497 break; 2498 case CS6: 2499 bits = 8; 2500 break; 2501 case CS7: 2502 bits = 9; 2503 break; 2504 default: 2505 bits = 10; 2506 break; 2507 } 2508 2509 if (termios->c_cflag & CSTOPB) 2510 bits++; 2511 if (termios->c_cflag & PARENB) 2512 bits++; 2513 2514 if (best_clk >= 0) { 2515 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 2516 switch (srr + 1) { 2517 case 5: smr_val |= SCSMR_SRC_5; break; 2518 case 7: smr_val |= SCSMR_SRC_7; break; 2519 case 11: smr_val |= SCSMR_SRC_11; break; 2520 case 13: smr_val |= SCSMR_SRC_13; break; 2521 case 16: smr_val |= SCSMR_SRC_16; break; 2522 case 17: smr_val |= SCSMR_SRC_17; break; 2523 case 19: smr_val |= SCSMR_SRC_19; break; 2524 case 27: smr_val |= SCSMR_SRC_27; break; 2525 } 2526 smr_val |= cks; 2527 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); 2528 serial_port_out(port, SCSMR, smr_val); 2529 serial_port_out(port, SCBRR, brr); 2530 if (sci_getreg(port, HSSRR)->size) { 2531 unsigned int hssrr = srr | HSCIF_SRE; 2532 /* Calculate deviation from intended rate at the 2533 * center of the last stop bit in sampling clocks. 2534 */ 2535 int last_stop = bits * 2 - 1; 2536 int deviation = DIV_ROUND_CLOSEST(min_err * last_stop * 2537 (int)(srr + 1), 2538 2 * (int)baud); 2539 2540 if (abs(deviation) >= 2) { 2541 /* At least two sampling clocks off at the 2542 * last stop bit; we can increase the error 2543 * margin by shifting the sampling point. 2544 */ 2545 int shift = clamp(deviation / 2, -8, 7); 2546 2547 hssrr |= (shift << HSCIF_SRHP_SHIFT) & 2548 HSCIF_SRHP_MASK; 2549 hssrr |= HSCIF_SRDE; 2550 } 2551 serial_port_out(port, HSSRR, hssrr); 2552 } 2553 2554 /* Wait one bit interval */ 2555 udelay((1000000 + (baud - 1)) / baud); 2556 } else { 2557 /* Don't touch the bit rate configuration */ 2558 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0); 2559 smr_val |= serial_port_in(port, SCSMR) & 2560 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS); 2561 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); 2562 serial_port_out(port, SCSMR, smr_val); 2563 } 2564 2565 sci_init_pins(port, termios->c_cflag); 2566 2567 port->status &= ~UPSTAT_AUTOCTS; 2568 s->autorts = false; 2569 reg = sci_getreg(port, SCFCR); 2570 if (reg->size) { 2571 unsigned short ctrl = serial_port_in(port, SCFCR); 2572 2573 if ((port->flags & UPF_HARD_FLOW) && 2574 (termios->c_cflag & CRTSCTS)) { 2575 /* There is no CTS interrupt to restart the hardware */ 2576 port->status |= UPSTAT_AUTOCTS; 2577 /* MCE is enabled when RTS is raised */ 2578 s->autorts = true; 2579 } 2580 2581 /* 2582 * As we've done a sci_reset() above, ensure we don't 2583 * interfere with the FIFOs while toggling MCE. As the 2584 * reset values could still be set, simply mask them out. 2585 */ 2586 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST); 2587 2588 serial_port_out(port, SCFCR, ctrl); 2589 } 2590 if (port->flags & UPF_HARD_FLOW) { 2591 /* Refresh (Auto) RTS */ 2592 sci_set_mctrl(port, port->mctrl); 2593 } 2594 2595 scr_val |= SCSCR_RE | SCSCR_TE | 2596 (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)); 2597 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); 2598 if ((srr + 1 == 5) && 2599 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) { 2600 /* 2601 * In asynchronous mode, when the sampling rate is 1/5, first 2602 * received data may become invalid on some SCIFA and SCIFB. 2603 * To avoid this problem wait more than 1 serial data time (1 2604 * bit time x serial data number) after setting SCSCR.RE = 1. 2605 */ 2606 udelay(DIV_ROUND_UP(10 * 1000000, baud)); 2607 } 2608 2609 /* 2610 * Calculate delay for 2 DMA buffers (4 FIFO). 2611 * See serial_core.c::uart_update_timeout(). 2612 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above 2613 * function calculates 1 jiffie for the data plus 5 jiffies for the 2614 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA 2615 * buffers (4 FIFO sizes), but when performing a faster transfer, the 2616 * value obtained by this formula is too small. Therefore, if the value 2617 * is smaller than 20ms, use 20ms as the timeout value for DMA. 2618 */ 2619 s->rx_frame = (10000 * bits) / (baud / 100); 2620 #ifdef CONFIG_SERIAL_SH_SCI_DMA 2621 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame; 2622 if (s->rx_timeout < 20) 2623 s->rx_timeout = 20; 2624 #endif 2625 2626 if ((termios->c_cflag & CREAD) != 0) 2627 sci_start_rx(port); 2628 2629 spin_unlock_irqrestore(&port->lock, flags); 2630 2631 sci_port_disable(s); 2632 2633 if (UART_ENABLE_MS(port, termios->c_cflag)) 2634 sci_enable_ms(port); 2635 } 2636 2637 static void sci_pm(struct uart_port *port, unsigned int state, 2638 unsigned int oldstate) 2639 { 2640 struct sci_port *sci_port = to_sci_port(port); 2641 2642 switch (state) { 2643 case UART_PM_STATE_OFF: 2644 sci_port_disable(sci_port); 2645 break; 2646 default: 2647 sci_port_enable(sci_port); 2648 break; 2649 } 2650 } 2651 2652 static const char *sci_type(struct uart_port *port) 2653 { 2654 switch (port->type) { 2655 case PORT_IRDA: 2656 return "irda"; 2657 case PORT_SCI: 2658 return "sci"; 2659 case PORT_SCIF: 2660 return "scif"; 2661 case PORT_SCIFA: 2662 return "scifa"; 2663 case PORT_SCIFB: 2664 return "scifb"; 2665 case PORT_HSCIF: 2666 return "hscif"; 2667 } 2668 2669 return NULL; 2670 } 2671 2672 static int sci_remap_port(struct uart_port *port) 2673 { 2674 struct sci_port *sport = to_sci_port(port); 2675 2676 /* 2677 * Nothing to do if there's already an established membase. 2678 */ 2679 if (port->membase) 2680 return 0; 2681 2682 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { 2683 port->membase = ioremap_nocache(port->mapbase, sport->reg_size); 2684 if (unlikely(!port->membase)) { 2685 dev_err(port->dev, "can't remap port#%d\n", port->line); 2686 return -ENXIO; 2687 } 2688 } else { 2689 /* 2690 * For the simple (and majority of) cases where we don't 2691 * need to do any remapping, just cast the cookie 2692 * directly. 2693 */ 2694 port->membase = (void __iomem *)(uintptr_t)port->mapbase; 2695 } 2696 2697 return 0; 2698 } 2699 2700 static void sci_release_port(struct uart_port *port) 2701 { 2702 struct sci_port *sport = to_sci_port(port); 2703 2704 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { 2705 iounmap(port->membase); 2706 port->membase = NULL; 2707 } 2708 2709 release_mem_region(port->mapbase, sport->reg_size); 2710 } 2711 2712 static int sci_request_port(struct uart_port *port) 2713 { 2714 struct resource *res; 2715 struct sci_port *sport = to_sci_port(port); 2716 int ret; 2717 2718 res = request_mem_region(port->mapbase, sport->reg_size, 2719 dev_name(port->dev)); 2720 if (unlikely(res == NULL)) { 2721 dev_err(port->dev, "request_mem_region failed."); 2722 return -EBUSY; 2723 } 2724 2725 ret = sci_remap_port(port); 2726 if (unlikely(ret != 0)) { 2727 release_resource(res); 2728 return ret; 2729 } 2730 2731 return 0; 2732 } 2733 2734 static void sci_config_port(struct uart_port *port, int flags) 2735 { 2736 if (flags & UART_CONFIG_TYPE) { 2737 struct sci_port *sport = to_sci_port(port); 2738 2739 port->type = sport->cfg->type; 2740 sci_request_port(port); 2741 } 2742 } 2743 2744 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser) 2745 { 2746 if (ser->baud_base < 2400) 2747 /* No paper tape reader for Mitch.. */ 2748 return -EINVAL; 2749 2750 return 0; 2751 } 2752 2753 static const struct uart_ops sci_uart_ops = { 2754 .tx_empty = sci_tx_empty, 2755 .set_mctrl = sci_set_mctrl, 2756 .get_mctrl = sci_get_mctrl, 2757 .start_tx = sci_start_tx, 2758 .stop_tx = sci_stop_tx, 2759 .stop_rx = sci_stop_rx, 2760 .enable_ms = sci_enable_ms, 2761 .break_ctl = sci_break_ctl, 2762 .startup = sci_startup, 2763 .shutdown = sci_shutdown, 2764 .flush_buffer = sci_flush_buffer, 2765 .set_termios = sci_set_termios, 2766 .pm = sci_pm, 2767 .type = sci_type, 2768 .release_port = sci_release_port, 2769 .request_port = sci_request_port, 2770 .config_port = sci_config_port, 2771 .verify_port = sci_verify_port, 2772 #ifdef CONFIG_CONSOLE_POLL 2773 .poll_get_char = sci_poll_get_char, 2774 .poll_put_char = sci_poll_put_char, 2775 #endif 2776 }; 2777 2778 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev) 2779 { 2780 const char *clk_names[] = { 2781 [SCI_FCK] = "fck", 2782 [SCI_SCK] = "sck", 2783 [SCI_BRG_INT] = "brg_int", 2784 [SCI_SCIF_CLK] = "scif_clk", 2785 }; 2786 struct clk *clk; 2787 unsigned int i; 2788 2789 if (sci_port->cfg->type == PORT_HSCIF) 2790 clk_names[SCI_SCK] = "hsck"; 2791 2792 for (i = 0; i < SCI_NUM_CLKS; i++) { 2793 clk = devm_clk_get(dev, clk_names[i]); 2794 if (PTR_ERR(clk) == -EPROBE_DEFER) 2795 return -EPROBE_DEFER; 2796 2797 if (IS_ERR(clk) && i == SCI_FCK) { 2798 /* 2799 * "fck" used to be called "sci_ick", and we need to 2800 * maintain DT backward compatibility. 2801 */ 2802 clk = devm_clk_get(dev, "sci_ick"); 2803 if (PTR_ERR(clk) == -EPROBE_DEFER) 2804 return -EPROBE_DEFER; 2805 2806 if (!IS_ERR(clk)) 2807 goto found; 2808 2809 /* 2810 * Not all SH platforms declare a clock lookup entry 2811 * for SCI devices, in which case we need to get the 2812 * global "peripheral_clk" clock. 2813 */ 2814 clk = devm_clk_get(dev, "peripheral_clk"); 2815 if (!IS_ERR(clk)) 2816 goto found; 2817 2818 dev_err(dev, "failed to get %s (%ld)\n", clk_names[i], 2819 PTR_ERR(clk)); 2820 return PTR_ERR(clk); 2821 } 2822 2823 found: 2824 if (IS_ERR(clk)) 2825 dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i], 2826 PTR_ERR(clk)); 2827 else 2828 dev_dbg(dev, "clk %s is %pC rate %lu\n", clk_names[i], 2829 clk, clk_get_rate(clk)); 2830 sci_port->clks[i] = IS_ERR(clk) ? NULL : clk; 2831 } 2832 return 0; 2833 } 2834 2835 static const struct sci_port_params * 2836 sci_probe_regmap(const struct plat_sci_port *cfg) 2837 { 2838 unsigned int regtype; 2839 2840 if (cfg->regtype != SCIx_PROBE_REGTYPE) 2841 return &sci_port_params[cfg->regtype]; 2842 2843 switch (cfg->type) { 2844 case PORT_SCI: 2845 regtype = SCIx_SCI_REGTYPE; 2846 break; 2847 case PORT_IRDA: 2848 regtype = SCIx_IRDA_REGTYPE; 2849 break; 2850 case PORT_SCIFA: 2851 regtype = SCIx_SCIFA_REGTYPE; 2852 break; 2853 case PORT_SCIFB: 2854 regtype = SCIx_SCIFB_REGTYPE; 2855 break; 2856 case PORT_SCIF: 2857 /* 2858 * The SH-4 is a bit of a misnomer here, although that's 2859 * where this particular port layout originated. This 2860 * configuration (or some slight variation thereof) 2861 * remains the dominant model for all SCIFs. 2862 */ 2863 regtype = SCIx_SH4_SCIF_REGTYPE; 2864 break; 2865 case PORT_HSCIF: 2866 regtype = SCIx_HSCIF_REGTYPE; 2867 break; 2868 default: 2869 pr_err("Can't probe register map for given port\n"); 2870 return NULL; 2871 } 2872 2873 return &sci_port_params[regtype]; 2874 } 2875 2876 static int sci_init_single(struct platform_device *dev, 2877 struct sci_port *sci_port, unsigned int index, 2878 const struct plat_sci_port *p, bool early) 2879 { 2880 struct uart_port *port = &sci_port->port; 2881 const struct resource *res; 2882 unsigned int i; 2883 int ret; 2884 2885 sci_port->cfg = p; 2886 2887 port->ops = &sci_uart_ops; 2888 port->iotype = UPIO_MEM; 2889 port->line = index; 2890 2891 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 2892 if (res == NULL) 2893 return -ENOMEM; 2894 2895 port->mapbase = res->start; 2896 sci_port->reg_size = resource_size(res); 2897 2898 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) { 2899 if (i) 2900 sci_port->irqs[i] = platform_get_irq_optional(dev, i); 2901 else 2902 sci_port->irqs[i] = platform_get_irq(dev, i); 2903 } 2904 2905 /* The SCI generates several interrupts. They can be muxed together or 2906 * connected to different interrupt lines. In the muxed case only one 2907 * interrupt resource is specified as there is only one interrupt ID. 2908 * In the non-muxed case, up to 6 interrupt signals might be generated 2909 * from the SCI, however those signals might have their own individual 2910 * interrupt ID numbers, or muxed together with another interrupt. 2911 */ 2912 if (sci_port->irqs[0] < 0) 2913 return -ENXIO; 2914 2915 if (sci_port->irqs[1] < 0) 2916 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++) 2917 sci_port->irqs[i] = sci_port->irqs[0]; 2918 2919 sci_port->params = sci_probe_regmap(p); 2920 if (unlikely(sci_port->params == NULL)) 2921 return -EINVAL; 2922 2923 switch (p->type) { 2924 case PORT_SCIFB: 2925 sci_port->rx_trigger = 48; 2926 break; 2927 case PORT_HSCIF: 2928 sci_port->rx_trigger = 64; 2929 break; 2930 case PORT_SCIFA: 2931 sci_port->rx_trigger = 32; 2932 break; 2933 case PORT_SCIF: 2934 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) 2935 /* RX triggering not implemented for this IP */ 2936 sci_port->rx_trigger = 1; 2937 else 2938 sci_port->rx_trigger = 8; 2939 break; 2940 default: 2941 sci_port->rx_trigger = 1; 2942 break; 2943 } 2944 2945 sci_port->rx_fifo_timeout = 0; 2946 sci_port->hscif_tot = 0; 2947 2948 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't 2949 * match the SoC datasheet, this should be investigated. Let platform 2950 * data override the sampling rate for now. 2951 */ 2952 sci_port->sampling_rate_mask = p->sampling_rate 2953 ? SCI_SR(p->sampling_rate) 2954 : sci_port->params->sampling_rate_mask; 2955 2956 if (!early) { 2957 ret = sci_init_clocks(sci_port, &dev->dev); 2958 if (ret < 0) 2959 return ret; 2960 2961 port->dev = &dev->dev; 2962 2963 pm_runtime_enable(&dev->dev); 2964 } 2965 2966 port->type = p->type; 2967 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags; 2968 port->fifosize = sci_port->params->fifosize; 2969 2970 if (port->type == PORT_SCI) { 2971 if (sci_port->reg_size >= 0x20) 2972 port->regshift = 2; 2973 else 2974 port->regshift = 1; 2975 } 2976 2977 /* 2978 * The UART port needs an IRQ value, so we peg this to the RX IRQ 2979 * for the multi-IRQ ports, which is where we are primarily 2980 * concerned with the shutdown path synchronization. 2981 * 2982 * For the muxed case there's nothing more to do. 2983 */ 2984 port->irq = sci_port->irqs[SCIx_RXI_IRQ]; 2985 port->irqflags = 0; 2986 2987 port->serial_in = sci_serial_in; 2988 port->serial_out = sci_serial_out; 2989 2990 return 0; 2991 } 2992 2993 static void sci_cleanup_single(struct sci_port *port) 2994 { 2995 pm_runtime_disable(port->port.dev); 2996 } 2997 2998 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ 2999 defined(CONFIG_SERIAL_SH_SCI_EARLYCON) 3000 static void serial_console_putchar(struct uart_port *port, int ch) 3001 { 3002 sci_poll_put_char(port, ch); 3003 } 3004 3005 /* 3006 * Print a string to the serial port trying not to disturb 3007 * any possible real use of the port... 3008 */ 3009 static void serial_console_write(struct console *co, const char *s, 3010 unsigned count) 3011 { 3012 struct sci_port *sci_port = &sci_ports[co->index]; 3013 struct uart_port *port = &sci_port->port; 3014 unsigned short bits, ctrl, ctrl_temp; 3015 unsigned long flags; 3016 int locked = 1; 3017 3018 #if defined(SUPPORT_SYSRQ) 3019 if (port->sysrq) 3020 locked = 0; 3021 else 3022 #endif 3023 if (oops_in_progress) 3024 locked = spin_trylock_irqsave(&port->lock, flags); 3025 else 3026 spin_lock_irqsave(&port->lock, flags); 3027 3028 /* first save SCSCR then disable interrupts, keep clock source */ 3029 ctrl = serial_port_in(port, SCSCR); 3030 ctrl_temp = SCSCR_RE | SCSCR_TE | 3031 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) | 3032 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0)); 3033 serial_port_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot); 3034 3035 uart_console_write(port, s, count, serial_console_putchar); 3036 3037 /* wait until fifo is empty and last bit has been transmitted */ 3038 bits = SCxSR_TDxE(port) | SCxSR_TEND(port); 3039 while ((serial_port_in(port, SCxSR) & bits) != bits) 3040 cpu_relax(); 3041 3042 /* restore the SCSCR */ 3043 serial_port_out(port, SCSCR, ctrl); 3044 3045 if (locked) 3046 spin_unlock_irqrestore(&port->lock, flags); 3047 } 3048 3049 static int serial_console_setup(struct console *co, char *options) 3050 { 3051 struct sci_port *sci_port; 3052 struct uart_port *port; 3053 int baud = 115200; 3054 int bits = 8; 3055 int parity = 'n'; 3056 int flow = 'n'; 3057 int ret; 3058 3059 /* 3060 * Refuse to handle any bogus ports. 3061 */ 3062 if (co->index < 0 || co->index >= SCI_NPORTS) 3063 return -ENODEV; 3064 3065 sci_port = &sci_ports[co->index]; 3066 port = &sci_port->port; 3067 3068 /* 3069 * Refuse to handle uninitialized ports. 3070 */ 3071 if (!port->ops) 3072 return -ENODEV; 3073 3074 ret = sci_remap_port(port); 3075 if (unlikely(ret != 0)) 3076 return ret; 3077 3078 if (options) 3079 uart_parse_options(options, &baud, &parity, &bits, &flow); 3080 3081 return uart_set_options(port, co, baud, parity, bits, flow); 3082 } 3083 3084 static struct console serial_console = { 3085 .name = "ttySC", 3086 .device = uart_console_device, 3087 .write = serial_console_write, 3088 .setup = serial_console_setup, 3089 .flags = CON_PRINTBUFFER, 3090 .index = -1, 3091 .data = &sci_uart_driver, 3092 }; 3093 3094 #ifdef CONFIG_SUPERH 3095 static struct console early_serial_console = { 3096 .name = "early_ttySC", 3097 .write = serial_console_write, 3098 .flags = CON_PRINTBUFFER, 3099 .index = -1, 3100 }; 3101 3102 static char early_serial_buf[32]; 3103 3104 static int sci_probe_earlyprintk(struct platform_device *pdev) 3105 { 3106 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev); 3107 3108 if (early_serial_console.data) 3109 return -EEXIST; 3110 3111 early_serial_console.index = pdev->id; 3112 3113 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true); 3114 3115 serial_console_setup(&early_serial_console, early_serial_buf); 3116 3117 if (!strstr(early_serial_buf, "keep")) 3118 early_serial_console.flags |= CON_BOOT; 3119 3120 register_console(&early_serial_console); 3121 return 0; 3122 } 3123 #endif 3124 3125 #define SCI_CONSOLE (&serial_console) 3126 3127 #else 3128 static inline int sci_probe_earlyprintk(struct platform_device *pdev) 3129 { 3130 return -EINVAL; 3131 } 3132 3133 #define SCI_CONSOLE NULL 3134 3135 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */ 3136 3137 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized"; 3138 3139 static DEFINE_MUTEX(sci_uart_registration_lock); 3140 static struct uart_driver sci_uart_driver = { 3141 .owner = THIS_MODULE, 3142 .driver_name = "sci", 3143 .dev_name = "ttySC", 3144 .major = SCI_MAJOR, 3145 .minor = SCI_MINOR_START, 3146 .nr = SCI_NPORTS, 3147 .cons = SCI_CONSOLE, 3148 }; 3149 3150 static int sci_remove(struct platform_device *dev) 3151 { 3152 struct sci_port *port = platform_get_drvdata(dev); 3153 unsigned int type = port->port.type; /* uart_remove_... clears it */ 3154 3155 sci_ports_in_use &= ~BIT(port->port.line); 3156 uart_remove_one_port(&sci_uart_driver, &port->port); 3157 3158 sci_cleanup_single(port); 3159 3160 if (port->port.fifosize > 1) 3161 device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger); 3162 if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF) 3163 device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout); 3164 3165 return 0; 3166 } 3167 3168 3169 #define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype)) 3170 #define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16) 3171 #define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff) 3172 3173 static const struct of_device_id of_sci_match[] = { 3174 /* SoC-specific types */ 3175 { 3176 .compatible = "renesas,scif-r7s72100", 3177 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE), 3178 }, 3179 { 3180 .compatible = "renesas,scif-r7s9210", 3181 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE), 3182 }, 3183 /* Family-specific types */ 3184 { 3185 .compatible = "renesas,rcar-gen1-scif", 3186 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3187 }, { 3188 .compatible = "renesas,rcar-gen2-scif", 3189 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3190 }, { 3191 .compatible = "renesas,rcar-gen3-scif", 3192 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3193 }, 3194 /* Generic types */ 3195 { 3196 .compatible = "renesas,scif", 3197 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE), 3198 }, { 3199 .compatible = "renesas,scifa", 3200 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE), 3201 }, { 3202 .compatible = "renesas,scifb", 3203 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE), 3204 }, { 3205 .compatible = "renesas,hscif", 3206 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE), 3207 }, { 3208 .compatible = "renesas,sci", 3209 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE), 3210 }, { 3211 /* Terminator */ 3212 }, 3213 }; 3214 MODULE_DEVICE_TABLE(of, of_sci_match); 3215 3216 static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev, 3217 unsigned int *dev_id) 3218 { 3219 struct device_node *np = pdev->dev.of_node; 3220 struct plat_sci_port *p; 3221 struct sci_port *sp; 3222 const void *data; 3223 int id; 3224 3225 if (!IS_ENABLED(CONFIG_OF) || !np) 3226 return NULL; 3227 3228 data = of_device_get_match_data(&pdev->dev); 3229 3230 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL); 3231 if (!p) 3232 return NULL; 3233 3234 /* Get the line number from the aliases node. */ 3235 id = of_alias_get_id(np, "serial"); 3236 if (id < 0 && ~sci_ports_in_use) 3237 id = ffz(sci_ports_in_use); 3238 if (id < 0) { 3239 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id); 3240 return NULL; 3241 } 3242 if (id >= ARRAY_SIZE(sci_ports)) { 3243 dev_err(&pdev->dev, "serial%d out of range\n", id); 3244 return NULL; 3245 } 3246 3247 sp = &sci_ports[id]; 3248 *dev_id = id; 3249 3250 p->type = SCI_OF_TYPE(data); 3251 p->regtype = SCI_OF_REGTYPE(data); 3252 3253 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts"); 3254 3255 return p; 3256 } 3257 3258 static int sci_probe_single(struct platform_device *dev, 3259 unsigned int index, 3260 struct plat_sci_port *p, 3261 struct sci_port *sciport) 3262 { 3263 int ret; 3264 3265 /* Sanity check */ 3266 if (unlikely(index >= SCI_NPORTS)) { 3267 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n", 3268 index+1, SCI_NPORTS); 3269 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n"); 3270 return -EINVAL; 3271 } 3272 BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8); 3273 if (sci_ports_in_use & BIT(index)) 3274 return -EBUSY; 3275 3276 mutex_lock(&sci_uart_registration_lock); 3277 if (!sci_uart_driver.state) { 3278 ret = uart_register_driver(&sci_uart_driver); 3279 if (ret) { 3280 mutex_unlock(&sci_uart_registration_lock); 3281 return ret; 3282 } 3283 } 3284 mutex_unlock(&sci_uart_registration_lock); 3285 3286 ret = sci_init_single(dev, sciport, index, p, false); 3287 if (ret) 3288 return ret; 3289 3290 sciport->gpios = mctrl_gpio_init(&sciport->port, 0); 3291 if (IS_ERR(sciport->gpios)) 3292 return PTR_ERR(sciport->gpios); 3293 3294 if (sciport->has_rtscts) { 3295 if (mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_CTS) || 3296 mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_RTS)) { 3297 dev_err(&dev->dev, "Conflicting RTS/CTS config\n"); 3298 return -EINVAL; 3299 } 3300 sciport->port.flags |= UPF_HARD_FLOW; 3301 } 3302 3303 ret = uart_add_one_port(&sci_uart_driver, &sciport->port); 3304 if (ret) { 3305 sci_cleanup_single(sciport); 3306 return ret; 3307 } 3308 3309 return 0; 3310 } 3311 3312 static int sci_probe(struct platform_device *dev) 3313 { 3314 struct plat_sci_port *p; 3315 struct sci_port *sp; 3316 unsigned int dev_id; 3317 int ret; 3318 3319 /* 3320 * If we've come here via earlyprintk initialization, head off to 3321 * the special early probe. We don't have sufficient device state 3322 * to make it beyond this yet. 3323 */ 3324 #ifdef CONFIG_SUPERH 3325 if (is_sh_early_platform_device(dev)) 3326 return sci_probe_earlyprintk(dev); 3327 #endif 3328 3329 if (dev->dev.of_node) { 3330 p = sci_parse_dt(dev, &dev_id); 3331 if (p == NULL) 3332 return -EINVAL; 3333 } else { 3334 p = dev->dev.platform_data; 3335 if (p == NULL) { 3336 dev_err(&dev->dev, "no platform data supplied\n"); 3337 return -EINVAL; 3338 } 3339 3340 dev_id = dev->id; 3341 } 3342 3343 sp = &sci_ports[dev_id]; 3344 platform_set_drvdata(dev, sp); 3345 3346 ret = sci_probe_single(dev, dev_id, p, sp); 3347 if (ret) 3348 return ret; 3349 3350 if (sp->port.fifosize > 1) { 3351 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_trigger); 3352 if (ret) 3353 return ret; 3354 } 3355 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB || 3356 sp->port.type == PORT_HSCIF) { 3357 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout); 3358 if (ret) { 3359 if (sp->port.fifosize > 1) { 3360 device_remove_file(&dev->dev, 3361 &dev_attr_rx_fifo_trigger); 3362 } 3363 return ret; 3364 } 3365 } 3366 3367 #ifdef CONFIG_SH_STANDARD_BIOS 3368 sh_bios_gdb_detach(); 3369 #endif 3370 3371 sci_ports_in_use |= BIT(dev_id); 3372 return 0; 3373 } 3374 3375 static __maybe_unused int sci_suspend(struct device *dev) 3376 { 3377 struct sci_port *sport = dev_get_drvdata(dev); 3378 3379 if (sport) 3380 uart_suspend_port(&sci_uart_driver, &sport->port); 3381 3382 return 0; 3383 } 3384 3385 static __maybe_unused int sci_resume(struct device *dev) 3386 { 3387 struct sci_port *sport = dev_get_drvdata(dev); 3388 3389 if (sport) 3390 uart_resume_port(&sci_uart_driver, &sport->port); 3391 3392 return 0; 3393 } 3394 3395 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume); 3396 3397 static struct platform_driver sci_driver = { 3398 .probe = sci_probe, 3399 .remove = sci_remove, 3400 .driver = { 3401 .name = "sh-sci", 3402 .pm = &sci_dev_pm_ops, 3403 .of_match_table = of_match_ptr(of_sci_match), 3404 }, 3405 }; 3406 3407 static int __init sci_init(void) 3408 { 3409 pr_info("%s\n", banner); 3410 3411 return platform_driver_register(&sci_driver); 3412 } 3413 3414 static void __exit sci_exit(void) 3415 { 3416 platform_driver_unregister(&sci_driver); 3417 3418 if (sci_uart_driver.state) 3419 uart_unregister_driver(&sci_uart_driver); 3420 } 3421 3422 #if defined(CONFIG_SUPERH) && defined(CONFIG_SERIAL_SH_SCI_CONSOLE) 3423 sh_early_platform_init_buffer("earlyprintk", &sci_driver, 3424 early_serial_buf, ARRAY_SIZE(early_serial_buf)); 3425 #endif 3426 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON 3427 static struct plat_sci_port port_cfg __initdata; 3428 3429 static int __init early_console_setup(struct earlycon_device *device, 3430 int type) 3431 { 3432 if (!device->port.membase) 3433 return -ENODEV; 3434 3435 device->port.serial_in = sci_serial_in; 3436 device->port.serial_out = sci_serial_out; 3437 device->port.type = type; 3438 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port)); 3439 port_cfg.type = type; 3440 sci_ports[0].cfg = &port_cfg; 3441 sci_ports[0].params = sci_probe_regmap(&port_cfg); 3442 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR); 3443 sci_serial_out(&sci_ports[0].port, SCSCR, 3444 SCSCR_RE | SCSCR_TE | port_cfg.scscr); 3445 3446 device->con->write = serial_console_write; 3447 return 0; 3448 } 3449 static int __init sci_early_console_setup(struct earlycon_device *device, 3450 const char *opt) 3451 { 3452 return early_console_setup(device, PORT_SCI); 3453 } 3454 static int __init scif_early_console_setup(struct earlycon_device *device, 3455 const char *opt) 3456 { 3457 return early_console_setup(device, PORT_SCIF); 3458 } 3459 static int __init rzscifa_early_console_setup(struct earlycon_device *device, 3460 const char *opt) 3461 { 3462 port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE; 3463 return early_console_setup(device, PORT_SCIF); 3464 } 3465 static int __init scifa_early_console_setup(struct earlycon_device *device, 3466 const char *opt) 3467 { 3468 return early_console_setup(device, PORT_SCIFA); 3469 } 3470 static int __init scifb_early_console_setup(struct earlycon_device *device, 3471 const char *opt) 3472 { 3473 return early_console_setup(device, PORT_SCIFB); 3474 } 3475 static int __init hscif_early_console_setup(struct earlycon_device *device, 3476 const char *opt) 3477 { 3478 return early_console_setup(device, PORT_HSCIF); 3479 } 3480 3481 OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup); 3482 OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup); 3483 OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup); 3484 OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup); 3485 OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup); 3486 OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup); 3487 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */ 3488 3489 module_init(sci_init); 3490 module_exit(sci_exit); 3491 3492 MODULE_LICENSE("GPL"); 3493 MODULE_ALIAS("platform:sh-sci"); 3494 MODULE_AUTHOR("Paul Mundt"); 3495 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver"); 3496