1 /* 2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) 3 * 4 * Copyright (C) 2002 - 2011 Paul Mundt 5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007). 6 * 7 * based off of the old drivers/char/sh-sci.c by: 8 * 9 * Copyright (C) 1999, 2000 Niibe Yutaka 10 * Copyright (C) 2000 Sugioka Toshinobu 11 * Modified to support multiple serial ports. Stuart Menefy (May 2000). 12 * Modified to support SecureEdge. David McCullough (2002) 13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003). 14 * Removed SH7300 support (Jul 2007). 15 * 16 * This file is subject to the terms and conditions of the GNU General Public 17 * License. See the file "COPYING" in the main directory of this archive 18 * for more details. 19 */ 20 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 21 #define SUPPORT_SYSRQ 22 #endif 23 24 #undef DEBUG 25 26 #include <linux/module.h> 27 #include <linux/errno.h> 28 #include <linux/sh_dma.h> 29 #include <linux/timer.h> 30 #include <linux/interrupt.h> 31 #include <linux/tty.h> 32 #include <linux/tty_flip.h> 33 #include <linux/serial.h> 34 #include <linux/major.h> 35 #include <linux/string.h> 36 #include <linux/sysrq.h> 37 #include <linux/ioport.h> 38 #include <linux/mm.h> 39 #include <linux/init.h> 40 #include <linux/delay.h> 41 #include <linux/console.h> 42 #include <linux/platform_device.h> 43 #include <linux/serial_sci.h> 44 #include <linux/notifier.h> 45 #include <linux/pm_runtime.h> 46 #include <linux/cpufreq.h> 47 #include <linux/clk.h> 48 #include <linux/ctype.h> 49 #include <linux/err.h> 50 #include <linux/dmaengine.h> 51 #include <linux/dma-mapping.h> 52 #include <linux/scatterlist.h> 53 #include <linux/slab.h> 54 #include <linux/gpio.h> 55 56 #ifdef CONFIG_SUPERH 57 #include <asm/sh_bios.h> 58 #endif 59 60 #include "sh-sci.h" 61 62 struct sci_port { 63 struct uart_port port; 64 65 /* Platform configuration */ 66 struct plat_sci_port *cfg; 67 68 /* Break timer */ 69 struct timer_list break_timer; 70 int break_flag; 71 72 /* Interface clock */ 73 struct clk *iclk; 74 /* Function clock */ 75 struct clk *fclk; 76 77 char *irqstr[SCIx_NR_IRQS]; 78 char *gpiostr[SCIx_NR_FNS]; 79 80 struct dma_chan *chan_tx; 81 struct dma_chan *chan_rx; 82 83 #ifdef CONFIG_SERIAL_SH_SCI_DMA 84 struct dma_async_tx_descriptor *desc_tx; 85 struct dma_async_tx_descriptor *desc_rx[2]; 86 dma_cookie_t cookie_tx; 87 dma_cookie_t cookie_rx[2]; 88 dma_cookie_t active_rx; 89 struct scatterlist sg_tx; 90 unsigned int sg_len_tx; 91 struct scatterlist sg_rx[2]; 92 size_t buf_len_rx; 93 struct sh_dmae_slave param_tx; 94 struct sh_dmae_slave param_rx; 95 struct work_struct work_tx; 96 struct work_struct work_rx; 97 struct timer_list rx_timer; 98 unsigned int rx_timeout; 99 #endif 100 101 struct notifier_block freq_transition; 102 }; 103 104 /* Function prototypes */ 105 static void sci_start_tx(struct uart_port *port); 106 static void sci_stop_tx(struct uart_port *port); 107 static void sci_start_rx(struct uart_port *port); 108 109 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS 110 111 static struct sci_port sci_ports[SCI_NPORTS]; 112 static struct uart_driver sci_uart_driver; 113 114 static inline struct sci_port * 115 to_sci_port(struct uart_port *uart) 116 { 117 return container_of(uart, struct sci_port, port); 118 } 119 120 struct plat_sci_reg { 121 u8 offset, size; 122 }; 123 124 /* Helper for invalidating specific entries of an inherited map. */ 125 #define sci_reg_invalid { .offset = 0, .size = 0 } 126 127 static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { 128 [SCIx_PROBE_REGTYPE] = { 129 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid, 130 }, 131 132 /* 133 * Common SCI definitions, dependent on the port's regshift 134 * value. 135 */ 136 [SCIx_SCI_REGTYPE] = { 137 [SCSMR] = { 0x00, 8 }, 138 [SCBRR] = { 0x01, 8 }, 139 [SCSCR] = { 0x02, 8 }, 140 [SCxTDR] = { 0x03, 8 }, 141 [SCxSR] = { 0x04, 8 }, 142 [SCxRDR] = { 0x05, 8 }, 143 [SCFCR] = sci_reg_invalid, 144 [SCFDR] = sci_reg_invalid, 145 [SCTFDR] = sci_reg_invalid, 146 [SCRFDR] = sci_reg_invalid, 147 [SCSPTR] = sci_reg_invalid, 148 [SCLSR] = sci_reg_invalid, 149 [HSSRR] = sci_reg_invalid, 150 }, 151 152 /* 153 * Common definitions for legacy IrDA ports, dependent on 154 * regshift value. 155 */ 156 [SCIx_IRDA_REGTYPE] = { 157 [SCSMR] = { 0x00, 8 }, 158 [SCBRR] = { 0x01, 8 }, 159 [SCSCR] = { 0x02, 8 }, 160 [SCxTDR] = { 0x03, 8 }, 161 [SCxSR] = { 0x04, 8 }, 162 [SCxRDR] = { 0x05, 8 }, 163 [SCFCR] = { 0x06, 8 }, 164 [SCFDR] = { 0x07, 16 }, 165 [SCTFDR] = sci_reg_invalid, 166 [SCRFDR] = sci_reg_invalid, 167 [SCSPTR] = sci_reg_invalid, 168 [SCLSR] = sci_reg_invalid, 169 [HSSRR] = sci_reg_invalid, 170 }, 171 172 /* 173 * Common SCIFA definitions. 174 */ 175 [SCIx_SCIFA_REGTYPE] = { 176 [SCSMR] = { 0x00, 16 }, 177 [SCBRR] = { 0x04, 8 }, 178 [SCSCR] = { 0x08, 16 }, 179 [SCxTDR] = { 0x20, 8 }, 180 [SCxSR] = { 0x14, 16 }, 181 [SCxRDR] = { 0x24, 8 }, 182 [SCFCR] = { 0x18, 16 }, 183 [SCFDR] = { 0x1c, 16 }, 184 [SCTFDR] = sci_reg_invalid, 185 [SCRFDR] = sci_reg_invalid, 186 [SCSPTR] = sci_reg_invalid, 187 [SCLSR] = sci_reg_invalid, 188 [HSSRR] = sci_reg_invalid, 189 }, 190 191 /* 192 * Common SCIFB definitions. 193 */ 194 [SCIx_SCIFB_REGTYPE] = { 195 [SCSMR] = { 0x00, 16 }, 196 [SCBRR] = { 0x04, 8 }, 197 [SCSCR] = { 0x08, 16 }, 198 [SCxTDR] = { 0x40, 8 }, 199 [SCxSR] = { 0x14, 16 }, 200 [SCxRDR] = { 0x60, 8 }, 201 [SCFCR] = { 0x18, 16 }, 202 [SCFDR] = sci_reg_invalid, 203 [SCTFDR] = { 0x38, 16 }, 204 [SCRFDR] = { 0x3c, 16 }, 205 [SCSPTR] = sci_reg_invalid, 206 [SCLSR] = sci_reg_invalid, 207 [HSSRR] = sci_reg_invalid, 208 }, 209 210 /* 211 * Common SH-2(A) SCIF definitions for ports with FIFO data 212 * count registers. 213 */ 214 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = { 215 [SCSMR] = { 0x00, 16 }, 216 [SCBRR] = { 0x04, 8 }, 217 [SCSCR] = { 0x08, 16 }, 218 [SCxTDR] = { 0x0c, 8 }, 219 [SCxSR] = { 0x10, 16 }, 220 [SCxRDR] = { 0x14, 8 }, 221 [SCFCR] = { 0x18, 16 }, 222 [SCFDR] = { 0x1c, 16 }, 223 [SCTFDR] = sci_reg_invalid, 224 [SCRFDR] = sci_reg_invalid, 225 [SCSPTR] = { 0x20, 16 }, 226 [SCLSR] = { 0x24, 16 }, 227 [HSSRR] = sci_reg_invalid, 228 }, 229 230 /* 231 * Common SH-3 SCIF definitions. 232 */ 233 [SCIx_SH3_SCIF_REGTYPE] = { 234 [SCSMR] = { 0x00, 8 }, 235 [SCBRR] = { 0x02, 8 }, 236 [SCSCR] = { 0x04, 8 }, 237 [SCxTDR] = { 0x06, 8 }, 238 [SCxSR] = { 0x08, 16 }, 239 [SCxRDR] = { 0x0a, 8 }, 240 [SCFCR] = { 0x0c, 8 }, 241 [SCFDR] = { 0x0e, 16 }, 242 [SCTFDR] = sci_reg_invalid, 243 [SCRFDR] = sci_reg_invalid, 244 [SCSPTR] = sci_reg_invalid, 245 [SCLSR] = sci_reg_invalid, 246 [HSSRR] = sci_reg_invalid, 247 }, 248 249 /* 250 * Common SH-4(A) SCIF(B) definitions. 251 */ 252 [SCIx_SH4_SCIF_REGTYPE] = { 253 [SCSMR] = { 0x00, 16 }, 254 [SCBRR] = { 0x04, 8 }, 255 [SCSCR] = { 0x08, 16 }, 256 [SCxTDR] = { 0x0c, 8 }, 257 [SCxSR] = { 0x10, 16 }, 258 [SCxRDR] = { 0x14, 8 }, 259 [SCFCR] = { 0x18, 16 }, 260 [SCFDR] = { 0x1c, 16 }, 261 [SCTFDR] = sci_reg_invalid, 262 [SCRFDR] = sci_reg_invalid, 263 [SCSPTR] = { 0x20, 16 }, 264 [SCLSR] = { 0x24, 16 }, 265 [HSSRR] = sci_reg_invalid, 266 }, 267 268 /* 269 * Common HSCIF definitions. 270 */ 271 [SCIx_HSCIF_REGTYPE] = { 272 [SCSMR] = { 0x00, 16 }, 273 [SCBRR] = { 0x04, 8 }, 274 [SCSCR] = { 0x08, 16 }, 275 [SCxTDR] = { 0x0c, 8 }, 276 [SCxSR] = { 0x10, 16 }, 277 [SCxRDR] = { 0x14, 8 }, 278 [SCFCR] = { 0x18, 16 }, 279 [SCFDR] = { 0x1c, 16 }, 280 [SCTFDR] = sci_reg_invalid, 281 [SCRFDR] = sci_reg_invalid, 282 [SCSPTR] = { 0x20, 16 }, 283 [SCLSR] = { 0x24, 16 }, 284 [HSSRR] = { 0x40, 16 }, 285 }, 286 287 /* 288 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR 289 * register. 290 */ 291 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = { 292 [SCSMR] = { 0x00, 16 }, 293 [SCBRR] = { 0x04, 8 }, 294 [SCSCR] = { 0x08, 16 }, 295 [SCxTDR] = { 0x0c, 8 }, 296 [SCxSR] = { 0x10, 16 }, 297 [SCxRDR] = { 0x14, 8 }, 298 [SCFCR] = { 0x18, 16 }, 299 [SCFDR] = { 0x1c, 16 }, 300 [SCTFDR] = sci_reg_invalid, 301 [SCRFDR] = sci_reg_invalid, 302 [SCSPTR] = sci_reg_invalid, 303 [SCLSR] = { 0x24, 16 }, 304 [HSSRR] = sci_reg_invalid, 305 }, 306 307 /* 308 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data 309 * count registers. 310 */ 311 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = { 312 [SCSMR] = { 0x00, 16 }, 313 [SCBRR] = { 0x04, 8 }, 314 [SCSCR] = { 0x08, 16 }, 315 [SCxTDR] = { 0x0c, 8 }, 316 [SCxSR] = { 0x10, 16 }, 317 [SCxRDR] = { 0x14, 8 }, 318 [SCFCR] = { 0x18, 16 }, 319 [SCFDR] = { 0x1c, 16 }, 320 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */ 321 [SCRFDR] = { 0x20, 16 }, 322 [SCSPTR] = { 0x24, 16 }, 323 [SCLSR] = { 0x28, 16 }, 324 [HSSRR] = sci_reg_invalid, 325 }, 326 327 /* 328 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR 329 * registers. 330 */ 331 [SCIx_SH7705_SCIF_REGTYPE] = { 332 [SCSMR] = { 0x00, 16 }, 333 [SCBRR] = { 0x04, 8 }, 334 [SCSCR] = { 0x08, 16 }, 335 [SCxTDR] = { 0x20, 8 }, 336 [SCxSR] = { 0x14, 16 }, 337 [SCxRDR] = { 0x24, 8 }, 338 [SCFCR] = { 0x18, 16 }, 339 [SCFDR] = { 0x1c, 16 }, 340 [SCTFDR] = sci_reg_invalid, 341 [SCRFDR] = sci_reg_invalid, 342 [SCSPTR] = sci_reg_invalid, 343 [SCLSR] = sci_reg_invalid, 344 [HSSRR] = sci_reg_invalid, 345 }, 346 }; 347 348 #define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset) 349 350 /* 351 * The "offset" here is rather misleading, in that it refers to an enum 352 * value relative to the port mapping rather than the fixed offset 353 * itself, which needs to be manually retrieved from the platform's 354 * register map for the given port. 355 */ 356 static unsigned int sci_serial_in(struct uart_port *p, int offset) 357 { 358 struct plat_sci_reg *reg = sci_getreg(p, offset); 359 360 if (reg->size == 8) 361 return ioread8(p->membase + (reg->offset << p->regshift)); 362 else if (reg->size == 16) 363 return ioread16(p->membase + (reg->offset << p->regshift)); 364 else 365 WARN(1, "Invalid register access\n"); 366 367 return 0; 368 } 369 370 static void sci_serial_out(struct uart_port *p, int offset, int value) 371 { 372 struct plat_sci_reg *reg = sci_getreg(p, offset); 373 374 if (reg->size == 8) 375 iowrite8(value, p->membase + (reg->offset << p->regshift)); 376 else if (reg->size == 16) 377 iowrite16(value, p->membase + (reg->offset << p->regshift)); 378 else 379 WARN(1, "Invalid register access\n"); 380 } 381 382 static int sci_probe_regmap(struct plat_sci_port *cfg) 383 { 384 switch (cfg->type) { 385 case PORT_SCI: 386 cfg->regtype = SCIx_SCI_REGTYPE; 387 break; 388 case PORT_IRDA: 389 cfg->regtype = SCIx_IRDA_REGTYPE; 390 break; 391 case PORT_SCIFA: 392 cfg->regtype = SCIx_SCIFA_REGTYPE; 393 break; 394 case PORT_SCIFB: 395 cfg->regtype = SCIx_SCIFB_REGTYPE; 396 break; 397 case PORT_SCIF: 398 /* 399 * The SH-4 is a bit of a misnomer here, although that's 400 * where this particular port layout originated. This 401 * configuration (or some slight variation thereof) 402 * remains the dominant model for all SCIFs. 403 */ 404 cfg->regtype = SCIx_SH4_SCIF_REGTYPE; 405 break; 406 case PORT_HSCIF: 407 cfg->regtype = SCIx_HSCIF_REGTYPE; 408 break; 409 default: 410 printk(KERN_ERR "Can't probe register map for given port\n"); 411 return -EINVAL; 412 } 413 414 return 0; 415 } 416 417 static void sci_port_enable(struct sci_port *sci_port) 418 { 419 if (!sci_port->port.dev) 420 return; 421 422 pm_runtime_get_sync(sci_port->port.dev); 423 424 clk_enable(sci_port->iclk); 425 sci_port->port.uartclk = clk_get_rate(sci_port->iclk); 426 clk_enable(sci_port->fclk); 427 } 428 429 static void sci_port_disable(struct sci_port *sci_port) 430 { 431 if (!sci_port->port.dev) 432 return; 433 434 clk_disable(sci_port->fclk); 435 clk_disable(sci_port->iclk); 436 437 pm_runtime_put_sync(sci_port->port.dev); 438 } 439 440 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) 441 442 #ifdef CONFIG_CONSOLE_POLL 443 static int sci_poll_get_char(struct uart_port *port) 444 { 445 unsigned short status; 446 int c; 447 448 do { 449 status = serial_port_in(port, SCxSR); 450 if (status & SCxSR_ERRORS(port)) { 451 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port)); 452 continue; 453 } 454 break; 455 } while (1); 456 457 if (!(status & SCxSR_RDxF(port))) 458 return NO_POLL_CHAR; 459 460 c = serial_port_in(port, SCxRDR); 461 462 /* Dummy read */ 463 serial_port_in(port, SCxSR); 464 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); 465 466 return c; 467 } 468 #endif 469 470 static void sci_poll_put_char(struct uart_port *port, unsigned char c) 471 { 472 unsigned short status; 473 474 do { 475 status = serial_port_in(port, SCxSR); 476 } while (!(status & SCxSR_TDxE(port))); 477 478 serial_port_out(port, SCxTDR, c); 479 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port)); 480 } 481 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */ 482 483 static void sci_init_pins(struct uart_port *port, unsigned int cflag) 484 { 485 struct sci_port *s = to_sci_port(port); 486 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR; 487 488 /* 489 * Use port-specific handler if provided. 490 */ 491 if (s->cfg->ops && s->cfg->ops->init_pins) { 492 s->cfg->ops->init_pins(port, cflag); 493 return; 494 } 495 496 /* 497 * For the generic path SCSPTR is necessary. Bail out if that's 498 * unavailable, too. 499 */ 500 if (!reg->size) 501 return; 502 503 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) && 504 ((!(cflag & CRTSCTS)))) { 505 unsigned short status; 506 507 status = serial_port_in(port, SCSPTR); 508 status &= ~SCSPTR_CTSIO; 509 status |= SCSPTR_RTSIO; 510 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */ 511 } 512 } 513 514 static int sci_txfill(struct uart_port *port) 515 { 516 struct plat_sci_reg *reg; 517 518 reg = sci_getreg(port, SCTFDR); 519 if (reg->size) 520 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1); 521 522 reg = sci_getreg(port, SCFDR); 523 if (reg->size) 524 return serial_port_in(port, SCFDR) >> 8; 525 526 return !(serial_port_in(port, SCxSR) & SCI_TDRE); 527 } 528 529 static int sci_txroom(struct uart_port *port) 530 { 531 return port->fifosize - sci_txfill(port); 532 } 533 534 static int sci_rxfill(struct uart_port *port) 535 { 536 struct plat_sci_reg *reg; 537 538 reg = sci_getreg(port, SCRFDR); 539 if (reg->size) 540 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1); 541 542 reg = sci_getreg(port, SCFDR); 543 if (reg->size) 544 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1); 545 546 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0; 547 } 548 549 /* 550 * SCI helper for checking the state of the muxed port/RXD pins. 551 */ 552 static inline int sci_rxd_in(struct uart_port *port) 553 { 554 struct sci_port *s = to_sci_port(port); 555 556 if (s->cfg->port_reg <= 0) 557 return 1; 558 559 /* Cast for ARM damage */ 560 return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg); 561 } 562 563 /* ********************************************************************** * 564 * the interrupt related routines * 565 * ********************************************************************** */ 566 567 static void sci_transmit_chars(struct uart_port *port) 568 { 569 struct circ_buf *xmit = &port->state->xmit; 570 unsigned int stopped = uart_tx_stopped(port); 571 unsigned short status; 572 unsigned short ctrl; 573 int count; 574 575 status = serial_port_in(port, SCxSR); 576 if (!(status & SCxSR_TDxE(port))) { 577 ctrl = serial_port_in(port, SCSCR); 578 if (uart_circ_empty(xmit)) 579 ctrl &= ~SCSCR_TIE; 580 else 581 ctrl |= SCSCR_TIE; 582 serial_port_out(port, SCSCR, ctrl); 583 return; 584 } 585 586 count = sci_txroom(port); 587 588 do { 589 unsigned char c; 590 591 if (port->x_char) { 592 c = port->x_char; 593 port->x_char = 0; 594 } else if (!uart_circ_empty(xmit) && !stopped) { 595 c = xmit->buf[xmit->tail]; 596 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 597 } else { 598 break; 599 } 600 601 serial_port_out(port, SCxTDR, c); 602 603 port->icount.tx++; 604 } while (--count > 0); 605 606 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); 607 608 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 609 uart_write_wakeup(port); 610 if (uart_circ_empty(xmit)) { 611 sci_stop_tx(port); 612 } else { 613 ctrl = serial_port_in(port, SCSCR); 614 615 if (port->type != PORT_SCI) { 616 serial_port_in(port, SCxSR); /* Dummy read */ 617 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); 618 } 619 620 ctrl |= SCSCR_TIE; 621 serial_port_out(port, SCSCR, ctrl); 622 } 623 } 624 625 /* On SH3, SCIF may read end-of-break as a space->mark char */ 626 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); }) 627 628 static void sci_receive_chars(struct uart_port *port) 629 { 630 struct sci_port *sci_port = to_sci_port(port); 631 struct tty_port *tport = &port->state->port; 632 int i, count, copied = 0; 633 unsigned short status; 634 unsigned char flag; 635 636 status = serial_port_in(port, SCxSR); 637 if (!(status & SCxSR_RDxF(port))) 638 return; 639 640 while (1) { 641 /* Don't copy more bytes than there is room for in the buffer */ 642 count = tty_buffer_request_room(tport, sci_rxfill(port)); 643 644 /* If for any reason we can't copy more data, we're done! */ 645 if (count == 0) 646 break; 647 648 if (port->type == PORT_SCI) { 649 char c = serial_port_in(port, SCxRDR); 650 if (uart_handle_sysrq_char(port, c) || 651 sci_port->break_flag) 652 count = 0; 653 else 654 tty_insert_flip_char(tport, c, TTY_NORMAL); 655 } else { 656 for (i = 0; i < count; i++) { 657 char c = serial_port_in(port, SCxRDR); 658 659 status = serial_port_in(port, SCxSR); 660 #if defined(CONFIG_CPU_SH3) 661 /* Skip "chars" during break */ 662 if (sci_port->break_flag) { 663 if ((c == 0) && 664 (status & SCxSR_FER(port))) { 665 count--; i--; 666 continue; 667 } 668 669 /* Nonzero => end-of-break */ 670 dev_dbg(port->dev, "debounce<%02x>\n", c); 671 sci_port->break_flag = 0; 672 673 if (STEPFN(c)) { 674 count--; i--; 675 continue; 676 } 677 } 678 #endif /* CONFIG_CPU_SH3 */ 679 if (uart_handle_sysrq_char(port, c)) { 680 count--; i--; 681 continue; 682 } 683 684 /* Store data and status */ 685 if (status & SCxSR_FER(port)) { 686 flag = TTY_FRAME; 687 port->icount.frame++; 688 dev_notice(port->dev, "frame error\n"); 689 } else if (status & SCxSR_PER(port)) { 690 flag = TTY_PARITY; 691 port->icount.parity++; 692 dev_notice(port->dev, "parity error\n"); 693 } else 694 flag = TTY_NORMAL; 695 696 tty_insert_flip_char(tport, c, flag); 697 } 698 } 699 700 serial_port_in(port, SCxSR); /* dummy read */ 701 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); 702 703 copied += count; 704 port->icount.rx += count; 705 } 706 707 if (copied) { 708 /* Tell the rest of the system the news. New characters! */ 709 tty_flip_buffer_push(tport); 710 } else { 711 serial_port_in(port, SCxSR); /* dummy read */ 712 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); 713 } 714 } 715 716 #define SCI_BREAK_JIFFIES (HZ/20) 717 718 /* 719 * The sci generates interrupts during the break, 720 * 1 per millisecond or so during the break period, for 9600 baud. 721 * So dont bother disabling interrupts. 722 * But dont want more than 1 break event. 723 * Use a kernel timer to periodically poll the rx line until 724 * the break is finished. 725 */ 726 static inline void sci_schedule_break_timer(struct sci_port *port) 727 { 728 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES); 729 } 730 731 /* Ensure that two consecutive samples find the break over. */ 732 static void sci_break_timer(unsigned long data) 733 { 734 struct sci_port *port = (struct sci_port *)data; 735 736 sci_port_enable(port); 737 738 if (sci_rxd_in(&port->port) == 0) { 739 port->break_flag = 1; 740 sci_schedule_break_timer(port); 741 } else if (port->break_flag == 1) { 742 /* break is over. */ 743 port->break_flag = 2; 744 sci_schedule_break_timer(port); 745 } else 746 port->break_flag = 0; 747 748 sci_port_disable(port); 749 } 750 751 static int sci_handle_errors(struct uart_port *port) 752 { 753 int copied = 0; 754 unsigned short status = serial_port_in(port, SCxSR); 755 struct tty_port *tport = &port->state->port; 756 struct sci_port *s = to_sci_port(port); 757 758 /* 759 * Handle overruns, if supported. 760 */ 761 if (s->cfg->overrun_bit != SCIx_NOT_SUPPORTED) { 762 if (status & (1 << s->cfg->overrun_bit)) { 763 port->icount.overrun++; 764 765 /* overrun error */ 766 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN)) 767 copied++; 768 769 dev_notice(port->dev, "overrun error"); 770 } 771 } 772 773 if (status & SCxSR_FER(port)) { 774 if (sci_rxd_in(port) == 0) { 775 /* Notify of BREAK */ 776 struct sci_port *sci_port = to_sci_port(port); 777 778 if (!sci_port->break_flag) { 779 port->icount.brk++; 780 781 sci_port->break_flag = 1; 782 sci_schedule_break_timer(sci_port); 783 784 /* Do sysrq handling. */ 785 if (uart_handle_break(port)) 786 return 0; 787 788 dev_dbg(port->dev, "BREAK detected\n"); 789 790 if (tty_insert_flip_char(tport, 0, TTY_BREAK)) 791 copied++; 792 } 793 794 } else { 795 /* frame error */ 796 port->icount.frame++; 797 798 if (tty_insert_flip_char(tport, 0, TTY_FRAME)) 799 copied++; 800 801 dev_notice(port->dev, "frame error\n"); 802 } 803 } 804 805 if (status & SCxSR_PER(port)) { 806 /* parity error */ 807 port->icount.parity++; 808 809 if (tty_insert_flip_char(tport, 0, TTY_PARITY)) 810 copied++; 811 812 dev_notice(port->dev, "parity error"); 813 } 814 815 if (copied) 816 tty_flip_buffer_push(tport); 817 818 return copied; 819 } 820 821 static int sci_handle_fifo_overrun(struct uart_port *port) 822 { 823 struct tty_port *tport = &port->state->port; 824 struct sci_port *s = to_sci_port(port); 825 struct plat_sci_reg *reg; 826 int copied = 0; 827 828 reg = sci_getreg(port, SCLSR); 829 if (!reg->size) 830 return 0; 831 832 if ((serial_port_in(port, SCLSR) & (1 << s->cfg->overrun_bit))) { 833 serial_port_out(port, SCLSR, 0); 834 835 port->icount.overrun++; 836 837 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 838 tty_flip_buffer_push(tport); 839 840 dev_notice(port->dev, "overrun error\n"); 841 copied++; 842 } 843 844 return copied; 845 } 846 847 static int sci_handle_breaks(struct uart_port *port) 848 { 849 int copied = 0; 850 unsigned short status = serial_port_in(port, SCxSR); 851 struct tty_port *tport = &port->state->port; 852 struct sci_port *s = to_sci_port(port); 853 854 if (uart_handle_break(port)) 855 return 0; 856 857 if (!s->break_flag && status & SCxSR_BRK(port)) { 858 #if defined(CONFIG_CPU_SH3) 859 /* Debounce break */ 860 s->break_flag = 1; 861 #endif 862 863 port->icount.brk++; 864 865 /* Notify of BREAK */ 866 if (tty_insert_flip_char(tport, 0, TTY_BREAK)) 867 copied++; 868 869 dev_dbg(port->dev, "BREAK detected\n"); 870 } 871 872 if (copied) 873 tty_flip_buffer_push(tport); 874 875 copied += sci_handle_fifo_overrun(port); 876 877 return copied; 878 } 879 880 static irqreturn_t sci_rx_interrupt(int irq, void *ptr) 881 { 882 #ifdef CONFIG_SERIAL_SH_SCI_DMA 883 struct uart_port *port = ptr; 884 struct sci_port *s = to_sci_port(port); 885 886 if (s->chan_rx) { 887 u16 scr = serial_port_in(port, SCSCR); 888 u16 ssr = serial_port_in(port, SCxSR); 889 890 /* Disable future Rx interrupts */ 891 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 892 disable_irq_nosync(irq); 893 scr |= 0x4000; 894 } else { 895 scr &= ~SCSCR_RIE; 896 } 897 serial_port_out(port, SCSCR, scr); 898 /* Clear current interrupt */ 899 serial_port_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port))); 900 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n", 901 jiffies, s->rx_timeout); 902 mod_timer(&s->rx_timer, jiffies + s->rx_timeout); 903 904 return IRQ_HANDLED; 905 } 906 #endif 907 908 /* I think sci_receive_chars has to be called irrespective 909 * of whether the I_IXOFF is set, otherwise, how is the interrupt 910 * to be disabled? 911 */ 912 sci_receive_chars(ptr); 913 914 return IRQ_HANDLED; 915 } 916 917 static irqreturn_t sci_tx_interrupt(int irq, void *ptr) 918 { 919 struct uart_port *port = ptr; 920 unsigned long flags; 921 922 spin_lock_irqsave(&port->lock, flags); 923 sci_transmit_chars(port); 924 spin_unlock_irqrestore(&port->lock, flags); 925 926 return IRQ_HANDLED; 927 } 928 929 static irqreturn_t sci_er_interrupt(int irq, void *ptr) 930 { 931 struct uart_port *port = ptr; 932 933 /* Handle errors */ 934 if (port->type == PORT_SCI) { 935 if (sci_handle_errors(port)) { 936 /* discard character in rx buffer */ 937 serial_port_in(port, SCxSR); 938 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); 939 } 940 } else { 941 sci_handle_fifo_overrun(port); 942 sci_rx_interrupt(irq, ptr); 943 } 944 945 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port)); 946 947 /* Kick the transmission */ 948 sci_tx_interrupt(irq, ptr); 949 950 return IRQ_HANDLED; 951 } 952 953 static irqreturn_t sci_br_interrupt(int irq, void *ptr) 954 { 955 struct uart_port *port = ptr; 956 957 /* Handle BREAKs */ 958 sci_handle_breaks(port); 959 serial_port_out(port, SCxSR, SCxSR_BREAK_CLEAR(port)); 960 961 return IRQ_HANDLED; 962 } 963 964 static inline unsigned long port_rx_irq_mask(struct uart_port *port) 965 { 966 /* 967 * Not all ports (such as SCIFA) will support REIE. Rather than 968 * special-casing the port type, we check the port initialization 969 * IRQ enable mask to see whether the IRQ is desired at all. If 970 * it's unset, it's logically inferred that there's no point in 971 * testing for it. 972 */ 973 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE); 974 } 975 976 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) 977 { 978 unsigned short ssr_status, scr_status, err_enabled; 979 struct uart_port *port = ptr; 980 struct sci_port *s = to_sci_port(port); 981 irqreturn_t ret = IRQ_NONE; 982 983 ssr_status = serial_port_in(port, SCxSR); 984 scr_status = serial_port_in(port, SCSCR); 985 err_enabled = scr_status & port_rx_irq_mask(port); 986 987 /* Tx Interrupt */ 988 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) && 989 !s->chan_tx) 990 ret = sci_tx_interrupt(irq, ptr); 991 992 /* 993 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF / 994 * DR flags 995 */ 996 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) && 997 (scr_status & SCSCR_RIE)) 998 ret = sci_rx_interrupt(irq, ptr); 999 1000 /* Error Interrupt */ 1001 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled) 1002 ret = sci_er_interrupt(irq, ptr); 1003 1004 /* Break Interrupt */ 1005 if ((ssr_status & SCxSR_BRK(port)) && err_enabled) 1006 ret = sci_br_interrupt(irq, ptr); 1007 1008 return ret; 1009 } 1010 1011 /* 1012 * Here we define a transition notifier so that we can update all of our 1013 * ports' baud rate when the peripheral clock changes. 1014 */ 1015 static int sci_notifier(struct notifier_block *self, 1016 unsigned long phase, void *p) 1017 { 1018 struct sci_port *sci_port; 1019 unsigned long flags; 1020 1021 sci_port = container_of(self, struct sci_port, freq_transition); 1022 1023 if ((phase == CPUFREQ_POSTCHANGE) || 1024 (phase == CPUFREQ_RESUMECHANGE)) { 1025 struct uart_port *port = &sci_port->port; 1026 1027 spin_lock_irqsave(&port->lock, flags); 1028 port->uartclk = clk_get_rate(sci_port->iclk); 1029 spin_unlock_irqrestore(&port->lock, flags); 1030 } 1031 1032 return NOTIFY_OK; 1033 } 1034 1035 static struct sci_irq_desc { 1036 const char *desc; 1037 irq_handler_t handler; 1038 } sci_irq_desc[] = { 1039 /* 1040 * Split out handlers, the default case. 1041 */ 1042 [SCIx_ERI_IRQ] = { 1043 .desc = "rx err", 1044 .handler = sci_er_interrupt, 1045 }, 1046 1047 [SCIx_RXI_IRQ] = { 1048 .desc = "rx full", 1049 .handler = sci_rx_interrupt, 1050 }, 1051 1052 [SCIx_TXI_IRQ] = { 1053 .desc = "tx empty", 1054 .handler = sci_tx_interrupt, 1055 }, 1056 1057 [SCIx_BRI_IRQ] = { 1058 .desc = "break", 1059 .handler = sci_br_interrupt, 1060 }, 1061 1062 /* 1063 * Special muxed handler. 1064 */ 1065 [SCIx_MUX_IRQ] = { 1066 .desc = "mux", 1067 .handler = sci_mpxed_interrupt, 1068 }, 1069 }; 1070 1071 static int sci_request_irq(struct sci_port *port) 1072 { 1073 struct uart_port *up = &port->port; 1074 int i, j, ret = 0; 1075 1076 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) { 1077 struct sci_irq_desc *desc; 1078 unsigned int irq; 1079 1080 if (SCIx_IRQ_IS_MUXED(port)) { 1081 i = SCIx_MUX_IRQ; 1082 irq = up->irq; 1083 } else { 1084 irq = port->cfg->irqs[i]; 1085 1086 /* 1087 * Certain port types won't support all of the 1088 * available interrupt sources. 1089 */ 1090 if (unlikely(!irq)) 1091 continue; 1092 } 1093 1094 desc = sci_irq_desc + i; 1095 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s", 1096 dev_name(up->dev), desc->desc); 1097 if (!port->irqstr[j]) { 1098 dev_err(up->dev, "Failed to allocate %s IRQ string\n", 1099 desc->desc); 1100 goto out_nomem; 1101 } 1102 1103 ret = request_irq(irq, desc->handler, up->irqflags, 1104 port->irqstr[j], port); 1105 if (unlikely(ret)) { 1106 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc); 1107 goto out_noirq; 1108 } 1109 } 1110 1111 return 0; 1112 1113 out_noirq: 1114 while (--i >= 0) 1115 free_irq(port->cfg->irqs[i], port); 1116 1117 out_nomem: 1118 while (--j >= 0) 1119 kfree(port->irqstr[j]); 1120 1121 return ret; 1122 } 1123 1124 static void sci_free_irq(struct sci_port *port) 1125 { 1126 int i; 1127 1128 /* 1129 * Intentionally in reverse order so we iterate over the muxed 1130 * IRQ first. 1131 */ 1132 for (i = 0; i < SCIx_NR_IRQS; i++) { 1133 unsigned int irq = port->cfg->irqs[i]; 1134 1135 /* 1136 * Certain port types won't support all of the available 1137 * interrupt sources. 1138 */ 1139 if (unlikely(!irq)) 1140 continue; 1141 1142 free_irq(port->cfg->irqs[i], port); 1143 kfree(port->irqstr[i]); 1144 1145 if (SCIx_IRQ_IS_MUXED(port)) { 1146 /* If there's only one IRQ, we're done. */ 1147 return; 1148 } 1149 } 1150 } 1151 1152 static const char *sci_gpio_names[SCIx_NR_FNS] = { 1153 "sck", "rxd", "txd", "cts", "rts", 1154 }; 1155 1156 static const char *sci_gpio_str(unsigned int index) 1157 { 1158 return sci_gpio_names[index]; 1159 } 1160 1161 static void sci_init_gpios(struct sci_port *port) 1162 { 1163 struct uart_port *up = &port->port; 1164 int i; 1165 1166 if (!port->cfg) 1167 return; 1168 1169 for (i = 0; i < SCIx_NR_FNS; i++) { 1170 const char *desc; 1171 int ret; 1172 1173 if (!port->cfg->gpios[i]) 1174 continue; 1175 1176 desc = sci_gpio_str(i); 1177 1178 port->gpiostr[i] = kasprintf(GFP_KERNEL, "%s:%s", 1179 dev_name(up->dev), desc); 1180 1181 /* 1182 * If we've failed the allocation, we can still continue 1183 * on with a NULL string. 1184 */ 1185 if (!port->gpiostr[i]) 1186 dev_notice(up->dev, "%s string allocation failure\n", 1187 desc); 1188 1189 ret = gpio_request(port->cfg->gpios[i], port->gpiostr[i]); 1190 if (unlikely(ret != 0)) { 1191 dev_notice(up->dev, "failed %s gpio request\n", desc); 1192 1193 /* 1194 * If we can't get the GPIO for whatever reason, 1195 * no point in keeping the verbose string around. 1196 */ 1197 kfree(port->gpiostr[i]); 1198 } 1199 } 1200 } 1201 1202 static void sci_free_gpios(struct sci_port *port) 1203 { 1204 int i; 1205 1206 for (i = 0; i < SCIx_NR_FNS; i++) 1207 if (port->cfg->gpios[i]) { 1208 gpio_free(port->cfg->gpios[i]); 1209 kfree(port->gpiostr[i]); 1210 } 1211 } 1212 1213 static unsigned int sci_tx_empty(struct uart_port *port) 1214 { 1215 unsigned short status = serial_port_in(port, SCxSR); 1216 unsigned short in_tx_fifo = sci_txfill(port); 1217 1218 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0; 1219 } 1220 1221 /* 1222 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally 1223 * CTS/RTS is supported in hardware by at least one port and controlled 1224 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently 1225 * handled via the ->init_pins() op, which is a bit of a one-way street, 1226 * lacking any ability to defer pin control -- this will later be 1227 * converted over to the GPIO framework). 1228 * 1229 * Other modes (such as loopback) are supported generically on certain 1230 * port types, but not others. For these it's sufficient to test for the 1231 * existence of the support register and simply ignore the port type. 1232 */ 1233 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) 1234 { 1235 if (mctrl & TIOCM_LOOP) { 1236 struct plat_sci_reg *reg; 1237 1238 /* 1239 * Standard loopback mode for SCFCR ports. 1240 */ 1241 reg = sci_getreg(port, SCFCR); 1242 if (reg->size) 1243 serial_port_out(port, SCFCR, serial_port_in(port, SCFCR) | 1); 1244 } 1245 } 1246 1247 static unsigned int sci_get_mctrl(struct uart_port *port) 1248 { 1249 /* 1250 * CTS/RTS is handled in hardware when supported, while nothing 1251 * else is wired up. Keep it simple and simply assert DSR/CAR. 1252 */ 1253 return TIOCM_DSR | TIOCM_CAR; 1254 } 1255 1256 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1257 static void sci_dma_tx_complete(void *arg) 1258 { 1259 struct sci_port *s = arg; 1260 struct uart_port *port = &s->port; 1261 struct circ_buf *xmit = &port->state->xmit; 1262 unsigned long flags; 1263 1264 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1265 1266 spin_lock_irqsave(&port->lock, flags); 1267 1268 xmit->tail += sg_dma_len(&s->sg_tx); 1269 xmit->tail &= UART_XMIT_SIZE - 1; 1270 1271 port->icount.tx += sg_dma_len(&s->sg_tx); 1272 1273 async_tx_ack(s->desc_tx); 1274 s->desc_tx = NULL; 1275 1276 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1277 uart_write_wakeup(port); 1278 1279 if (!uart_circ_empty(xmit)) { 1280 s->cookie_tx = 0; 1281 schedule_work(&s->work_tx); 1282 } else { 1283 s->cookie_tx = -EINVAL; 1284 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1285 u16 ctrl = serial_port_in(port, SCSCR); 1286 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE); 1287 } 1288 } 1289 1290 spin_unlock_irqrestore(&port->lock, flags); 1291 } 1292 1293 /* Locking: called with port lock held */ 1294 static int sci_dma_rx_push(struct sci_port *s, size_t count) 1295 { 1296 struct uart_port *port = &s->port; 1297 struct tty_port *tport = &port->state->port; 1298 int i, active, room; 1299 1300 room = tty_buffer_request_room(tport, count); 1301 1302 if (s->active_rx == s->cookie_rx[0]) { 1303 active = 0; 1304 } else if (s->active_rx == s->cookie_rx[1]) { 1305 active = 1; 1306 } else { 1307 dev_err(port->dev, "cookie %d not found!\n", s->active_rx); 1308 return 0; 1309 } 1310 1311 if (room < count) 1312 dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n", 1313 count - room); 1314 if (!room) 1315 return room; 1316 1317 for (i = 0; i < room; i++) 1318 tty_insert_flip_char(tport, ((u8 *)sg_virt(&s->sg_rx[active]))[i], 1319 TTY_NORMAL); 1320 1321 port->icount.rx += room; 1322 1323 return room; 1324 } 1325 1326 static void sci_dma_rx_complete(void *arg) 1327 { 1328 struct sci_port *s = arg; 1329 struct uart_port *port = &s->port; 1330 unsigned long flags; 1331 int count; 1332 1333 dev_dbg(port->dev, "%s(%d) active #%d\n", __func__, port->line, s->active_rx); 1334 1335 spin_lock_irqsave(&port->lock, flags); 1336 1337 count = sci_dma_rx_push(s, s->buf_len_rx); 1338 1339 mod_timer(&s->rx_timer, jiffies + s->rx_timeout); 1340 1341 spin_unlock_irqrestore(&port->lock, flags); 1342 1343 if (count) 1344 tty_flip_buffer_push(&port->state->port); 1345 1346 schedule_work(&s->work_rx); 1347 } 1348 1349 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio) 1350 { 1351 struct dma_chan *chan = s->chan_rx; 1352 struct uart_port *port = &s->port; 1353 1354 s->chan_rx = NULL; 1355 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL; 1356 dma_release_channel(chan); 1357 if (sg_dma_address(&s->sg_rx[0])) 1358 dma_free_coherent(port->dev, s->buf_len_rx * 2, 1359 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0])); 1360 if (enable_pio) 1361 sci_start_rx(port); 1362 } 1363 1364 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio) 1365 { 1366 struct dma_chan *chan = s->chan_tx; 1367 struct uart_port *port = &s->port; 1368 1369 s->chan_tx = NULL; 1370 s->cookie_tx = -EINVAL; 1371 dma_release_channel(chan); 1372 if (enable_pio) 1373 sci_start_tx(port); 1374 } 1375 1376 static void sci_submit_rx(struct sci_port *s) 1377 { 1378 struct dma_chan *chan = s->chan_rx; 1379 int i; 1380 1381 for (i = 0; i < 2; i++) { 1382 struct scatterlist *sg = &s->sg_rx[i]; 1383 struct dma_async_tx_descriptor *desc; 1384 1385 desc = dmaengine_prep_slave_sg(chan, 1386 sg, 1, DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT); 1387 1388 if (desc) { 1389 s->desc_rx[i] = desc; 1390 desc->callback = sci_dma_rx_complete; 1391 desc->callback_param = s; 1392 s->cookie_rx[i] = desc->tx_submit(desc); 1393 } 1394 1395 if (!desc || s->cookie_rx[i] < 0) { 1396 if (i) { 1397 async_tx_ack(s->desc_rx[0]); 1398 s->cookie_rx[0] = -EINVAL; 1399 } 1400 if (desc) { 1401 async_tx_ack(desc); 1402 s->cookie_rx[i] = -EINVAL; 1403 } 1404 dev_warn(s->port.dev, 1405 "failed to re-start DMA, using PIO\n"); 1406 sci_rx_dma_release(s, true); 1407 return; 1408 } 1409 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__, 1410 s->cookie_rx[i], i); 1411 } 1412 1413 s->active_rx = s->cookie_rx[0]; 1414 1415 dma_async_issue_pending(chan); 1416 } 1417 1418 static void work_fn_rx(struct work_struct *work) 1419 { 1420 struct sci_port *s = container_of(work, struct sci_port, work_rx); 1421 struct uart_port *port = &s->port; 1422 struct dma_async_tx_descriptor *desc; 1423 int new; 1424 1425 if (s->active_rx == s->cookie_rx[0]) { 1426 new = 0; 1427 } else if (s->active_rx == s->cookie_rx[1]) { 1428 new = 1; 1429 } else { 1430 dev_err(port->dev, "cookie %d not found!\n", s->active_rx); 1431 return; 1432 } 1433 desc = s->desc_rx[new]; 1434 1435 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) != 1436 DMA_COMPLETE) { 1437 /* Handle incomplete DMA receive */ 1438 struct dma_chan *chan = s->chan_rx; 1439 struct shdma_desc *sh_desc = container_of(desc, 1440 struct shdma_desc, async_tx); 1441 unsigned long flags; 1442 int count; 1443 1444 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0); 1445 dev_dbg(port->dev, "Read %zu bytes with cookie %d\n", 1446 sh_desc->partial, sh_desc->cookie); 1447 1448 spin_lock_irqsave(&port->lock, flags); 1449 count = sci_dma_rx_push(s, sh_desc->partial); 1450 spin_unlock_irqrestore(&port->lock, flags); 1451 1452 if (count) 1453 tty_flip_buffer_push(&port->state->port); 1454 1455 sci_submit_rx(s); 1456 1457 return; 1458 } 1459 1460 s->cookie_rx[new] = desc->tx_submit(desc); 1461 if (s->cookie_rx[new] < 0) { 1462 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n"); 1463 sci_rx_dma_release(s, true); 1464 return; 1465 } 1466 1467 s->active_rx = s->cookie_rx[!new]; 1468 1469 dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n", __func__, 1470 s->cookie_rx[new], new, s->active_rx); 1471 } 1472 1473 static void work_fn_tx(struct work_struct *work) 1474 { 1475 struct sci_port *s = container_of(work, struct sci_port, work_tx); 1476 struct dma_async_tx_descriptor *desc; 1477 struct dma_chan *chan = s->chan_tx; 1478 struct uart_port *port = &s->port; 1479 struct circ_buf *xmit = &port->state->xmit; 1480 struct scatterlist *sg = &s->sg_tx; 1481 1482 /* 1483 * DMA is idle now. 1484 * Port xmit buffer is already mapped, and it is one page... Just adjust 1485 * offsets and lengths. Since it is a circular buffer, we have to 1486 * transmit till the end, and then the rest. Take the port lock to get a 1487 * consistent xmit buffer state. 1488 */ 1489 spin_lock_irq(&port->lock); 1490 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1); 1491 sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) + 1492 sg->offset; 1493 sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE), 1494 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE)); 1495 spin_unlock_irq(&port->lock); 1496 1497 BUG_ON(!sg_dma_len(sg)); 1498 1499 desc = dmaengine_prep_slave_sg(chan, 1500 sg, s->sg_len_tx, DMA_MEM_TO_DEV, 1501 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1502 if (!desc) { 1503 /* switch to PIO */ 1504 sci_tx_dma_release(s, true); 1505 return; 1506 } 1507 1508 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE); 1509 1510 spin_lock_irq(&port->lock); 1511 s->desc_tx = desc; 1512 desc->callback = sci_dma_tx_complete; 1513 desc->callback_param = s; 1514 spin_unlock_irq(&port->lock); 1515 s->cookie_tx = desc->tx_submit(desc); 1516 if (s->cookie_tx < 0) { 1517 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n"); 1518 /* switch to PIO */ 1519 sci_tx_dma_release(s, true); 1520 return; 1521 } 1522 1523 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", __func__, 1524 xmit->buf, xmit->tail, xmit->head, s->cookie_tx); 1525 1526 dma_async_issue_pending(chan); 1527 } 1528 #endif 1529 1530 static void sci_start_tx(struct uart_port *port) 1531 { 1532 struct sci_port *s = to_sci_port(port); 1533 unsigned short ctrl; 1534 1535 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1536 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1537 u16 new, scr = serial_port_in(port, SCSCR); 1538 if (s->chan_tx) 1539 new = scr | 0x8000; 1540 else 1541 new = scr & ~0x8000; 1542 if (new != scr) 1543 serial_port_out(port, SCSCR, new); 1544 } 1545 1546 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) && 1547 s->cookie_tx < 0) { 1548 s->cookie_tx = 0; 1549 schedule_work(&s->work_tx); 1550 } 1551 #endif 1552 1553 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1554 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ 1555 ctrl = serial_port_in(port, SCSCR); 1556 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE); 1557 } 1558 } 1559 1560 static void sci_stop_tx(struct uart_port *port) 1561 { 1562 unsigned short ctrl; 1563 1564 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ 1565 ctrl = serial_port_in(port, SCSCR); 1566 1567 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1568 ctrl &= ~0x8000; 1569 1570 ctrl &= ~SCSCR_TIE; 1571 1572 serial_port_out(port, SCSCR, ctrl); 1573 } 1574 1575 static void sci_start_rx(struct uart_port *port) 1576 { 1577 unsigned short ctrl; 1578 1579 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port); 1580 1581 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1582 ctrl &= ~0x4000; 1583 1584 serial_port_out(port, SCSCR, ctrl); 1585 } 1586 1587 static void sci_stop_rx(struct uart_port *port) 1588 { 1589 unsigned short ctrl; 1590 1591 ctrl = serial_port_in(port, SCSCR); 1592 1593 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1594 ctrl &= ~0x4000; 1595 1596 ctrl &= ~port_rx_irq_mask(port); 1597 1598 serial_port_out(port, SCSCR, ctrl); 1599 } 1600 1601 static void sci_enable_ms(struct uart_port *port) 1602 { 1603 /* 1604 * Not supported by hardware, always a nop. 1605 */ 1606 } 1607 1608 static void sci_break_ctl(struct uart_port *port, int break_state) 1609 { 1610 struct sci_port *s = to_sci_port(port); 1611 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR; 1612 unsigned short scscr, scsptr; 1613 1614 /* check wheter the port has SCSPTR */ 1615 if (!reg->size) { 1616 /* 1617 * Not supported by hardware. Most parts couple break and rx 1618 * interrupts together, with break detection always enabled. 1619 */ 1620 return; 1621 } 1622 1623 scsptr = serial_port_in(port, SCSPTR); 1624 scscr = serial_port_in(port, SCSCR); 1625 1626 if (break_state == -1) { 1627 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT; 1628 scscr &= ~SCSCR_TE; 1629 } else { 1630 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO; 1631 scscr |= SCSCR_TE; 1632 } 1633 1634 serial_port_out(port, SCSPTR, scsptr); 1635 serial_port_out(port, SCSCR, scscr); 1636 } 1637 1638 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1639 static bool filter(struct dma_chan *chan, void *slave) 1640 { 1641 struct sh_dmae_slave *param = slave; 1642 1643 dev_dbg(chan->device->dev, "%s: slave ID %d\n", __func__, 1644 param->shdma_slave.slave_id); 1645 1646 chan->private = ¶m->shdma_slave; 1647 return true; 1648 } 1649 1650 static void rx_timer_fn(unsigned long arg) 1651 { 1652 struct sci_port *s = (struct sci_port *)arg; 1653 struct uart_port *port = &s->port; 1654 u16 scr = serial_port_in(port, SCSCR); 1655 1656 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1657 scr &= ~0x4000; 1658 enable_irq(s->cfg->irqs[1]); 1659 } 1660 serial_port_out(port, SCSCR, scr | SCSCR_RIE); 1661 dev_dbg(port->dev, "DMA Rx timed out\n"); 1662 schedule_work(&s->work_rx); 1663 } 1664 1665 static void sci_request_dma(struct uart_port *port) 1666 { 1667 struct sci_port *s = to_sci_port(port); 1668 struct sh_dmae_slave *param; 1669 struct dma_chan *chan; 1670 dma_cap_mask_t mask; 1671 int nent; 1672 1673 dev_dbg(port->dev, "%s: port %d\n", __func__, 1674 port->line); 1675 1676 if (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0) 1677 return; 1678 1679 dma_cap_zero(mask); 1680 dma_cap_set(DMA_SLAVE, mask); 1681 1682 param = &s->param_tx; 1683 1684 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */ 1685 param->shdma_slave.slave_id = s->cfg->dma_slave_tx; 1686 1687 s->cookie_tx = -EINVAL; 1688 chan = dma_request_channel(mask, filter, param); 1689 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan); 1690 if (chan) { 1691 s->chan_tx = chan; 1692 sg_init_table(&s->sg_tx, 1); 1693 /* UART circular tx buffer is an aligned page. */ 1694 BUG_ON((uintptr_t)port->state->xmit.buf & ~PAGE_MASK); 1695 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf), 1696 UART_XMIT_SIZE, 1697 (uintptr_t)port->state->xmit.buf & ~PAGE_MASK); 1698 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE); 1699 if (!nent) 1700 sci_tx_dma_release(s, false); 1701 else 1702 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__, 1703 sg_dma_len(&s->sg_tx), port->state->xmit.buf, 1704 &sg_dma_address(&s->sg_tx)); 1705 1706 s->sg_len_tx = nent; 1707 1708 INIT_WORK(&s->work_tx, work_fn_tx); 1709 } 1710 1711 param = &s->param_rx; 1712 1713 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */ 1714 param->shdma_slave.slave_id = s->cfg->dma_slave_rx; 1715 1716 chan = dma_request_channel(mask, filter, param); 1717 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan); 1718 if (chan) { 1719 dma_addr_t dma[2]; 1720 void *buf[2]; 1721 int i; 1722 1723 s->chan_rx = chan; 1724 1725 s->buf_len_rx = 2 * max(16, (int)port->fifosize); 1726 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2, 1727 &dma[0], GFP_KERNEL); 1728 1729 if (!buf[0]) { 1730 dev_warn(port->dev, 1731 "failed to allocate dma buffer, using PIO\n"); 1732 sci_rx_dma_release(s, true); 1733 return; 1734 } 1735 1736 buf[1] = buf[0] + s->buf_len_rx; 1737 dma[1] = dma[0] + s->buf_len_rx; 1738 1739 for (i = 0; i < 2; i++) { 1740 struct scatterlist *sg = &s->sg_rx[i]; 1741 1742 sg_init_table(sg, 1); 1743 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx, 1744 (uintptr_t)buf[i] & ~PAGE_MASK); 1745 sg_dma_address(sg) = dma[i]; 1746 } 1747 1748 INIT_WORK(&s->work_rx, work_fn_rx); 1749 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s); 1750 1751 sci_submit_rx(s); 1752 } 1753 } 1754 1755 static void sci_free_dma(struct uart_port *port) 1756 { 1757 struct sci_port *s = to_sci_port(port); 1758 1759 if (s->chan_tx) 1760 sci_tx_dma_release(s, false); 1761 if (s->chan_rx) 1762 sci_rx_dma_release(s, false); 1763 } 1764 #else 1765 static inline void sci_request_dma(struct uart_port *port) 1766 { 1767 } 1768 1769 static inline void sci_free_dma(struct uart_port *port) 1770 { 1771 } 1772 #endif 1773 1774 static int sci_startup(struct uart_port *port) 1775 { 1776 struct sci_port *s = to_sci_port(port); 1777 unsigned long flags; 1778 int ret; 1779 1780 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1781 1782 ret = sci_request_irq(s); 1783 if (unlikely(ret < 0)) 1784 return ret; 1785 1786 sci_request_dma(port); 1787 1788 spin_lock_irqsave(&port->lock, flags); 1789 sci_start_tx(port); 1790 sci_start_rx(port); 1791 spin_unlock_irqrestore(&port->lock, flags); 1792 1793 return 0; 1794 } 1795 1796 static void sci_shutdown(struct uart_port *port) 1797 { 1798 struct sci_port *s = to_sci_port(port); 1799 unsigned long flags; 1800 1801 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1802 1803 spin_lock_irqsave(&port->lock, flags); 1804 sci_stop_rx(port); 1805 sci_stop_tx(port); 1806 spin_unlock_irqrestore(&port->lock, flags); 1807 1808 sci_free_dma(port); 1809 sci_free_irq(s); 1810 } 1811 1812 static unsigned int sci_scbrr_calc(unsigned int algo_id, unsigned int bps, 1813 unsigned long freq) 1814 { 1815 switch (algo_id) { 1816 case SCBRR_ALGO_1: 1817 return ((freq + 16 * bps) / (16 * bps) - 1); 1818 case SCBRR_ALGO_2: 1819 return ((freq + 16 * bps) / (32 * bps) - 1); 1820 case SCBRR_ALGO_3: 1821 return (((freq * 2) + 16 * bps) / (16 * bps) - 1); 1822 case SCBRR_ALGO_4: 1823 return (((freq * 2) + 16 * bps) / (32 * bps) - 1); 1824 case SCBRR_ALGO_5: 1825 return (((freq * 1000 / 32) / bps) - 1); 1826 } 1827 1828 /* Warn, but use a safe default */ 1829 WARN_ON(1); 1830 1831 return ((freq + 16 * bps) / (32 * bps) - 1); 1832 } 1833 1834 /* calculate sample rate, BRR, and clock select for HSCIF */ 1835 static void sci_baud_calc_hscif(unsigned int bps, unsigned long freq, 1836 int *brr, unsigned int *srr, 1837 unsigned int *cks) 1838 { 1839 int sr, c, br, err; 1840 int min_err = 1000; /* 100% */ 1841 1842 /* Find the combination of sample rate and clock select with the 1843 smallest deviation from the desired baud rate. */ 1844 for (sr = 8; sr <= 32; sr++) { 1845 for (c = 0; c <= 3; c++) { 1846 /* integerized formulas from HSCIF documentation */ 1847 br = freq / (sr * (1 << (2 * c + 1)) * bps) - 1; 1848 if (br < 0 || br > 255) 1849 continue; 1850 err = freq / ((br + 1) * bps * sr * 1851 (1 << (2 * c + 1)) / 1000) - 1000; 1852 if (min_err > err) { 1853 min_err = err; 1854 *brr = br; 1855 *srr = sr - 1; 1856 *cks = c; 1857 } 1858 } 1859 } 1860 1861 if (min_err == 1000) { 1862 WARN_ON(1); 1863 /* use defaults */ 1864 *brr = 255; 1865 *srr = 15; 1866 *cks = 0; 1867 } 1868 } 1869 1870 static void sci_reset(struct uart_port *port) 1871 { 1872 struct plat_sci_reg *reg; 1873 unsigned int status; 1874 1875 do { 1876 status = serial_port_in(port, SCxSR); 1877 } while (!(status & SCxSR_TEND(port))); 1878 1879 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */ 1880 1881 reg = sci_getreg(port, SCFCR); 1882 if (reg->size) 1883 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); 1884 } 1885 1886 static void sci_set_termios(struct uart_port *port, struct ktermios *termios, 1887 struct ktermios *old) 1888 { 1889 struct sci_port *s = to_sci_port(port); 1890 struct plat_sci_reg *reg; 1891 unsigned int baud, smr_val, max_baud, cks = 0; 1892 int t = -1; 1893 unsigned int srr = 15; 1894 1895 /* 1896 * earlyprintk comes here early on with port->uartclk set to zero. 1897 * the clock framework is not up and running at this point so here 1898 * we assume that 115200 is the maximum baud rate. please note that 1899 * the baud rate is not programmed during earlyprintk - it is assumed 1900 * that the previous boot loader has enabled required clocks and 1901 * setup the baud rate generator hardware for us already. 1902 */ 1903 max_baud = port->uartclk ? port->uartclk / 16 : 115200; 1904 1905 baud = uart_get_baud_rate(port, termios, old, 0, max_baud); 1906 if (likely(baud && port->uartclk)) { 1907 if (s->cfg->scbrr_algo_id == SCBRR_ALGO_6) { 1908 sci_baud_calc_hscif(baud, port->uartclk, &t, &srr, 1909 &cks); 1910 } else { 1911 t = sci_scbrr_calc(s->cfg->scbrr_algo_id, baud, 1912 port->uartclk); 1913 for (cks = 0; t >= 256 && cks <= 3; cks++) 1914 t >>= 2; 1915 } 1916 } 1917 1918 sci_port_enable(s); 1919 1920 sci_reset(port); 1921 1922 smr_val = serial_port_in(port, SCSMR) & 3; 1923 1924 if ((termios->c_cflag & CSIZE) == CS7) 1925 smr_val |= 0x40; 1926 if (termios->c_cflag & PARENB) 1927 smr_val |= 0x20; 1928 if (termios->c_cflag & PARODD) 1929 smr_val |= 0x30; 1930 if (termios->c_cflag & CSTOPB) 1931 smr_val |= 0x08; 1932 1933 uart_update_timeout(port, termios->c_cflag, baud); 1934 1935 dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n", 1936 __func__, smr_val, cks, t, s->cfg->scscr); 1937 1938 if (t >= 0) { 1939 serial_port_out(port, SCSMR, (smr_val & ~3) | cks); 1940 serial_port_out(port, SCBRR, t); 1941 reg = sci_getreg(port, HSSRR); 1942 if (reg->size) 1943 serial_port_out(port, HSSRR, srr | HSCIF_SRE); 1944 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */ 1945 } else 1946 serial_port_out(port, SCSMR, smr_val); 1947 1948 sci_init_pins(port, termios->c_cflag); 1949 1950 reg = sci_getreg(port, SCFCR); 1951 if (reg->size) { 1952 unsigned short ctrl = serial_port_in(port, SCFCR); 1953 1954 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) { 1955 if (termios->c_cflag & CRTSCTS) 1956 ctrl |= SCFCR_MCE; 1957 else 1958 ctrl &= ~SCFCR_MCE; 1959 } 1960 1961 /* 1962 * As we've done a sci_reset() above, ensure we don't 1963 * interfere with the FIFOs while toggling MCE. As the 1964 * reset values could still be set, simply mask them out. 1965 */ 1966 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST); 1967 1968 serial_port_out(port, SCFCR, ctrl); 1969 } 1970 1971 serial_port_out(port, SCSCR, s->cfg->scscr); 1972 1973 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1974 /* 1975 * Calculate delay for 1.5 DMA buffers: see 1976 * drivers/serial/serial_core.c::uart_update_timeout(). With 10 bits 1977 * (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function 1978 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)." 1979 * Then below we calculate 3 jiffies (12ms) for 1.5 DMA buffers (3 FIFO 1980 * sizes), but it has been found out experimentally, that this is not 1981 * enough: the driver too often needlessly runs on a DMA timeout. 20ms 1982 * as a minimum seem to work perfectly. 1983 */ 1984 if (s->chan_rx) { 1985 s->rx_timeout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 / 1986 port->fifosize / 2; 1987 dev_dbg(port->dev, 1988 "DMA Rx t-out %ums, tty t-out %u jiffies\n", 1989 s->rx_timeout * 1000 / HZ, port->timeout); 1990 if (s->rx_timeout < msecs_to_jiffies(20)) 1991 s->rx_timeout = msecs_to_jiffies(20); 1992 } 1993 #endif 1994 1995 if ((termios->c_cflag & CREAD) != 0) 1996 sci_start_rx(port); 1997 1998 sci_port_disable(s); 1999 } 2000 2001 static void sci_pm(struct uart_port *port, unsigned int state, 2002 unsigned int oldstate) 2003 { 2004 struct sci_port *sci_port = to_sci_port(port); 2005 2006 switch (state) { 2007 case 3: 2008 sci_port_disable(sci_port); 2009 break; 2010 default: 2011 sci_port_enable(sci_port); 2012 break; 2013 } 2014 } 2015 2016 static const char *sci_type(struct uart_port *port) 2017 { 2018 switch (port->type) { 2019 case PORT_IRDA: 2020 return "irda"; 2021 case PORT_SCI: 2022 return "sci"; 2023 case PORT_SCIF: 2024 return "scif"; 2025 case PORT_SCIFA: 2026 return "scifa"; 2027 case PORT_SCIFB: 2028 return "scifb"; 2029 case PORT_HSCIF: 2030 return "hscif"; 2031 } 2032 2033 return NULL; 2034 } 2035 2036 static inline unsigned long sci_port_size(struct uart_port *port) 2037 { 2038 /* 2039 * Pick an arbitrary size that encapsulates all of the base 2040 * registers by default. This can be optimized later, or derived 2041 * from platform resource data at such a time that ports begin to 2042 * behave more erratically. 2043 */ 2044 if (port->type == PORT_HSCIF) 2045 return 96; 2046 else 2047 return 64; 2048 } 2049 2050 static int sci_remap_port(struct uart_port *port) 2051 { 2052 unsigned long size = sci_port_size(port); 2053 2054 /* 2055 * Nothing to do if there's already an established membase. 2056 */ 2057 if (port->membase) 2058 return 0; 2059 2060 if (port->flags & UPF_IOREMAP) { 2061 port->membase = ioremap_nocache(port->mapbase, size); 2062 if (unlikely(!port->membase)) { 2063 dev_err(port->dev, "can't remap port#%d\n", port->line); 2064 return -ENXIO; 2065 } 2066 } else { 2067 /* 2068 * For the simple (and majority of) cases where we don't 2069 * need to do any remapping, just cast the cookie 2070 * directly. 2071 */ 2072 port->membase = (void __iomem *)port->mapbase; 2073 } 2074 2075 return 0; 2076 } 2077 2078 static void sci_release_port(struct uart_port *port) 2079 { 2080 if (port->flags & UPF_IOREMAP) { 2081 iounmap(port->membase); 2082 port->membase = NULL; 2083 } 2084 2085 release_mem_region(port->mapbase, sci_port_size(port)); 2086 } 2087 2088 static int sci_request_port(struct uart_port *port) 2089 { 2090 unsigned long size = sci_port_size(port); 2091 struct resource *res; 2092 int ret; 2093 2094 res = request_mem_region(port->mapbase, size, dev_name(port->dev)); 2095 if (unlikely(res == NULL)) 2096 return -EBUSY; 2097 2098 ret = sci_remap_port(port); 2099 if (unlikely(ret != 0)) { 2100 release_resource(res); 2101 return ret; 2102 } 2103 2104 return 0; 2105 } 2106 2107 static void sci_config_port(struct uart_port *port, int flags) 2108 { 2109 if (flags & UART_CONFIG_TYPE) { 2110 struct sci_port *sport = to_sci_port(port); 2111 2112 port->type = sport->cfg->type; 2113 sci_request_port(port); 2114 } 2115 } 2116 2117 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser) 2118 { 2119 struct sci_port *s = to_sci_port(port); 2120 2121 if (ser->irq != s->cfg->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs) 2122 return -EINVAL; 2123 if (ser->baud_base < 2400) 2124 /* No paper tape reader for Mitch.. */ 2125 return -EINVAL; 2126 2127 return 0; 2128 } 2129 2130 static struct uart_ops sci_uart_ops = { 2131 .tx_empty = sci_tx_empty, 2132 .set_mctrl = sci_set_mctrl, 2133 .get_mctrl = sci_get_mctrl, 2134 .start_tx = sci_start_tx, 2135 .stop_tx = sci_stop_tx, 2136 .stop_rx = sci_stop_rx, 2137 .enable_ms = sci_enable_ms, 2138 .break_ctl = sci_break_ctl, 2139 .startup = sci_startup, 2140 .shutdown = sci_shutdown, 2141 .set_termios = sci_set_termios, 2142 .pm = sci_pm, 2143 .type = sci_type, 2144 .release_port = sci_release_port, 2145 .request_port = sci_request_port, 2146 .config_port = sci_config_port, 2147 .verify_port = sci_verify_port, 2148 #ifdef CONFIG_CONSOLE_POLL 2149 .poll_get_char = sci_poll_get_char, 2150 .poll_put_char = sci_poll_put_char, 2151 #endif 2152 }; 2153 2154 static int sci_init_single(struct platform_device *dev, 2155 struct sci_port *sci_port, 2156 unsigned int index, 2157 struct plat_sci_port *p) 2158 { 2159 struct uart_port *port = &sci_port->port; 2160 int ret; 2161 2162 sci_port->cfg = p; 2163 2164 port->ops = &sci_uart_ops; 2165 port->iotype = UPIO_MEM; 2166 port->line = index; 2167 2168 switch (p->type) { 2169 case PORT_SCIFB: 2170 port->fifosize = 256; 2171 break; 2172 case PORT_HSCIF: 2173 port->fifosize = 128; 2174 break; 2175 case PORT_SCIFA: 2176 port->fifosize = 64; 2177 break; 2178 case PORT_SCIF: 2179 port->fifosize = 16; 2180 break; 2181 default: 2182 port->fifosize = 1; 2183 break; 2184 } 2185 2186 if (p->regtype == SCIx_PROBE_REGTYPE) { 2187 ret = sci_probe_regmap(p); 2188 if (unlikely(ret)) 2189 return ret; 2190 } 2191 2192 if (dev) { 2193 sci_port->iclk = clk_get(&dev->dev, "sci_ick"); 2194 if (IS_ERR(sci_port->iclk)) { 2195 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk"); 2196 if (IS_ERR(sci_port->iclk)) { 2197 dev_err(&dev->dev, "can't get iclk\n"); 2198 return PTR_ERR(sci_port->iclk); 2199 } 2200 } 2201 2202 /* 2203 * The function clock is optional, ignore it if we can't 2204 * find it. 2205 */ 2206 sci_port->fclk = clk_get(&dev->dev, "sci_fck"); 2207 if (IS_ERR(sci_port->fclk)) 2208 sci_port->fclk = NULL; 2209 2210 port->dev = &dev->dev; 2211 2212 sci_init_gpios(sci_port); 2213 2214 pm_runtime_enable(&dev->dev); 2215 } 2216 2217 sci_port->break_timer.data = (unsigned long)sci_port; 2218 sci_port->break_timer.function = sci_break_timer; 2219 init_timer(&sci_port->break_timer); 2220 2221 /* 2222 * Establish some sensible defaults for the error detection. 2223 */ 2224 if (!p->error_mask) 2225 p->error_mask = (p->type == PORT_SCI) ? 2226 SCI_DEFAULT_ERROR_MASK : SCIF_DEFAULT_ERROR_MASK; 2227 2228 /* 2229 * Establish sensible defaults for the overrun detection, unless 2230 * the part has explicitly disabled support for it. 2231 */ 2232 if (p->overrun_bit != SCIx_NOT_SUPPORTED) { 2233 if (p->type == PORT_SCI) 2234 p->overrun_bit = 5; 2235 else if (p->scbrr_algo_id == SCBRR_ALGO_4) 2236 p->overrun_bit = 9; 2237 else 2238 p->overrun_bit = 0; 2239 2240 /* 2241 * Make the error mask inclusive of overrun detection, if 2242 * supported. 2243 */ 2244 p->error_mask |= (1 << p->overrun_bit); 2245 } 2246 2247 port->mapbase = p->mapbase; 2248 port->type = p->type; 2249 port->flags = p->flags; 2250 port->regshift = p->regshift; 2251 2252 /* 2253 * The UART port needs an IRQ value, so we peg this to the RX IRQ 2254 * for the multi-IRQ ports, which is where we are primarily 2255 * concerned with the shutdown path synchronization. 2256 * 2257 * For the muxed case there's nothing more to do. 2258 */ 2259 port->irq = p->irqs[SCIx_RXI_IRQ]; 2260 port->irqflags = 0; 2261 2262 port->serial_in = sci_serial_in; 2263 port->serial_out = sci_serial_out; 2264 2265 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0) 2266 dev_dbg(port->dev, "DMA tx %d, rx %d\n", 2267 p->dma_slave_tx, p->dma_slave_rx); 2268 2269 return 0; 2270 } 2271 2272 static void sci_cleanup_single(struct sci_port *port) 2273 { 2274 sci_free_gpios(port); 2275 2276 clk_put(port->iclk); 2277 clk_put(port->fclk); 2278 2279 pm_runtime_disable(port->port.dev); 2280 } 2281 2282 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE 2283 static void serial_console_putchar(struct uart_port *port, int ch) 2284 { 2285 sci_poll_put_char(port, ch); 2286 } 2287 2288 /* 2289 * Print a string to the serial port trying not to disturb 2290 * any possible real use of the port... 2291 */ 2292 static void serial_console_write(struct console *co, const char *s, 2293 unsigned count) 2294 { 2295 struct sci_port *sci_port = &sci_ports[co->index]; 2296 struct uart_port *port = &sci_port->port; 2297 unsigned short bits, ctrl; 2298 unsigned long flags; 2299 int locked = 1; 2300 2301 local_irq_save(flags); 2302 if (port->sysrq) 2303 locked = 0; 2304 else if (oops_in_progress) 2305 locked = spin_trylock(&port->lock); 2306 else 2307 spin_lock(&port->lock); 2308 2309 /* first save the SCSCR then disable the interrupts */ 2310 ctrl = serial_port_in(port, SCSCR); 2311 serial_port_out(port, SCSCR, sci_port->cfg->scscr); 2312 2313 uart_console_write(port, s, count, serial_console_putchar); 2314 2315 /* wait until fifo is empty and last bit has been transmitted */ 2316 bits = SCxSR_TDxE(port) | SCxSR_TEND(port); 2317 while ((serial_port_in(port, SCxSR) & bits) != bits) 2318 cpu_relax(); 2319 2320 /* restore the SCSCR */ 2321 serial_port_out(port, SCSCR, ctrl); 2322 2323 if (locked) 2324 spin_unlock(&port->lock); 2325 local_irq_restore(flags); 2326 } 2327 2328 static int serial_console_setup(struct console *co, char *options) 2329 { 2330 struct sci_port *sci_port; 2331 struct uart_port *port; 2332 int baud = 115200; 2333 int bits = 8; 2334 int parity = 'n'; 2335 int flow = 'n'; 2336 int ret; 2337 2338 /* 2339 * Refuse to handle any bogus ports. 2340 */ 2341 if (co->index < 0 || co->index >= SCI_NPORTS) 2342 return -ENODEV; 2343 2344 sci_port = &sci_ports[co->index]; 2345 port = &sci_port->port; 2346 2347 /* 2348 * Refuse to handle uninitialized ports. 2349 */ 2350 if (!port->ops) 2351 return -ENODEV; 2352 2353 ret = sci_remap_port(port); 2354 if (unlikely(ret != 0)) 2355 return ret; 2356 2357 if (options) 2358 uart_parse_options(options, &baud, &parity, &bits, &flow); 2359 2360 return uart_set_options(port, co, baud, parity, bits, flow); 2361 } 2362 2363 static struct console serial_console = { 2364 .name = "ttySC", 2365 .device = uart_console_device, 2366 .write = serial_console_write, 2367 .setup = serial_console_setup, 2368 .flags = CON_PRINTBUFFER, 2369 .index = -1, 2370 .data = &sci_uart_driver, 2371 }; 2372 2373 static struct console early_serial_console = { 2374 .name = "early_ttySC", 2375 .write = serial_console_write, 2376 .flags = CON_PRINTBUFFER, 2377 .index = -1, 2378 }; 2379 2380 static char early_serial_buf[32]; 2381 2382 static int sci_probe_earlyprintk(struct platform_device *pdev) 2383 { 2384 struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev); 2385 2386 if (early_serial_console.data) 2387 return -EEXIST; 2388 2389 early_serial_console.index = pdev->id; 2390 2391 sci_init_single(NULL, &sci_ports[pdev->id], pdev->id, cfg); 2392 2393 serial_console_setup(&early_serial_console, early_serial_buf); 2394 2395 if (!strstr(early_serial_buf, "keep")) 2396 early_serial_console.flags |= CON_BOOT; 2397 2398 register_console(&early_serial_console); 2399 return 0; 2400 } 2401 2402 #define SCI_CONSOLE (&serial_console) 2403 2404 #else 2405 static inline int sci_probe_earlyprintk(struct platform_device *pdev) 2406 { 2407 return -EINVAL; 2408 } 2409 2410 #define SCI_CONSOLE NULL 2411 2412 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */ 2413 2414 static char banner[] __initdata = 2415 KERN_INFO "SuperH (H)SCI(F) driver initialized\n"; 2416 2417 static struct uart_driver sci_uart_driver = { 2418 .owner = THIS_MODULE, 2419 .driver_name = "sci", 2420 .dev_name = "ttySC", 2421 .major = SCI_MAJOR, 2422 .minor = SCI_MINOR_START, 2423 .nr = SCI_NPORTS, 2424 .cons = SCI_CONSOLE, 2425 }; 2426 2427 static int sci_remove(struct platform_device *dev) 2428 { 2429 struct sci_port *port = platform_get_drvdata(dev); 2430 2431 cpufreq_unregister_notifier(&port->freq_transition, 2432 CPUFREQ_TRANSITION_NOTIFIER); 2433 2434 uart_remove_one_port(&sci_uart_driver, &port->port); 2435 2436 sci_cleanup_single(port); 2437 2438 return 0; 2439 } 2440 2441 static int sci_probe_single(struct platform_device *dev, 2442 unsigned int index, 2443 struct plat_sci_port *p, 2444 struct sci_port *sciport) 2445 { 2446 int ret; 2447 2448 /* Sanity check */ 2449 if (unlikely(index >= SCI_NPORTS)) { 2450 dev_notice(&dev->dev, "Attempting to register port " 2451 "%d when only %d are available.\n", 2452 index+1, SCI_NPORTS); 2453 dev_notice(&dev->dev, "Consider bumping " 2454 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n"); 2455 return -EINVAL; 2456 } 2457 2458 ret = sci_init_single(dev, sciport, index, p); 2459 if (ret) 2460 return ret; 2461 2462 ret = uart_add_one_port(&sci_uart_driver, &sciport->port); 2463 if (ret) { 2464 sci_cleanup_single(sciport); 2465 return ret; 2466 } 2467 2468 return 0; 2469 } 2470 2471 static int sci_probe(struct platform_device *dev) 2472 { 2473 struct plat_sci_port *p = dev_get_platdata(&dev->dev); 2474 struct sci_port *sp = &sci_ports[dev->id]; 2475 int ret; 2476 2477 /* 2478 * If we've come here via earlyprintk initialization, head off to 2479 * the special early probe. We don't have sufficient device state 2480 * to make it beyond this yet. 2481 */ 2482 if (is_early_platform_device(dev)) 2483 return sci_probe_earlyprintk(dev); 2484 2485 platform_set_drvdata(dev, sp); 2486 2487 ret = sci_probe_single(dev, dev->id, p, sp); 2488 if (ret) 2489 return ret; 2490 2491 sp->freq_transition.notifier_call = sci_notifier; 2492 2493 ret = cpufreq_register_notifier(&sp->freq_transition, 2494 CPUFREQ_TRANSITION_NOTIFIER); 2495 if (unlikely(ret < 0)) { 2496 sci_cleanup_single(sp); 2497 return ret; 2498 } 2499 2500 #ifdef CONFIG_SH_STANDARD_BIOS 2501 sh_bios_gdb_detach(); 2502 #endif 2503 2504 return 0; 2505 } 2506 2507 static int sci_suspend(struct device *dev) 2508 { 2509 struct sci_port *sport = dev_get_drvdata(dev); 2510 2511 if (sport) 2512 uart_suspend_port(&sci_uart_driver, &sport->port); 2513 2514 return 0; 2515 } 2516 2517 static int sci_resume(struct device *dev) 2518 { 2519 struct sci_port *sport = dev_get_drvdata(dev); 2520 2521 if (sport) 2522 uart_resume_port(&sci_uart_driver, &sport->port); 2523 2524 return 0; 2525 } 2526 2527 static const struct dev_pm_ops sci_dev_pm_ops = { 2528 .suspend = sci_suspend, 2529 .resume = sci_resume, 2530 }; 2531 2532 static struct platform_driver sci_driver = { 2533 .probe = sci_probe, 2534 .remove = sci_remove, 2535 .driver = { 2536 .name = "sh-sci", 2537 .owner = THIS_MODULE, 2538 .pm = &sci_dev_pm_ops, 2539 }, 2540 }; 2541 2542 static int __init sci_init(void) 2543 { 2544 int ret; 2545 2546 printk(banner); 2547 2548 ret = uart_register_driver(&sci_uart_driver); 2549 if (likely(ret == 0)) { 2550 ret = platform_driver_register(&sci_driver); 2551 if (unlikely(ret)) 2552 uart_unregister_driver(&sci_uart_driver); 2553 } 2554 2555 return ret; 2556 } 2557 2558 static void __exit sci_exit(void) 2559 { 2560 platform_driver_unregister(&sci_driver); 2561 uart_unregister_driver(&sci_uart_driver); 2562 } 2563 2564 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE 2565 early_platform_init_buffer("earlyprintk", &sci_driver, 2566 early_serial_buf, ARRAY_SIZE(early_serial_buf)); 2567 #endif 2568 module_init(sci_init); 2569 module_exit(sci_exit); 2570 2571 MODULE_LICENSE("GPL"); 2572 MODULE_ALIAS("platform:sh-sci"); 2573 MODULE_AUTHOR("Paul Mundt"); 2574 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver"); 2575