1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) 4 * 5 * Copyright (C) 2002 - 2011 Paul Mundt 6 * Copyright (C) 2015 Glider bvba 7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007). 8 * 9 * based off of the old drivers/char/sh-sci.c by: 10 * 11 * Copyright (C) 1999, 2000 Niibe Yutaka 12 * Copyright (C) 2000 Sugioka Toshinobu 13 * Modified to support multiple serial ports. Stuart Menefy (May 2000). 14 * Modified to support SecureEdge. David McCullough (2002) 15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003). 16 * Removed SH7300 support (Jul 2007). 17 */ 18 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 19 #define SUPPORT_SYSRQ 20 #endif 21 22 #undef DEBUG 23 24 #include <linux/clk.h> 25 #include <linux/console.h> 26 #include <linux/ctype.h> 27 #include <linux/cpufreq.h> 28 #include <linux/delay.h> 29 #include <linux/dmaengine.h> 30 #include <linux/dma-mapping.h> 31 #include <linux/err.h> 32 #include <linux/errno.h> 33 #include <linux/init.h> 34 #include <linux/interrupt.h> 35 #include <linux/ioport.h> 36 #include <linux/ktime.h> 37 #include <linux/major.h> 38 #include <linux/module.h> 39 #include <linux/mm.h> 40 #include <linux/of.h> 41 #include <linux/of_device.h> 42 #include <linux/platform_device.h> 43 #include <linux/pm_runtime.h> 44 #include <linux/scatterlist.h> 45 #include <linux/serial.h> 46 #include <linux/serial_sci.h> 47 #include <linux/sh_dma.h> 48 #include <linux/slab.h> 49 #include <linux/string.h> 50 #include <linux/sysrq.h> 51 #include <linux/timer.h> 52 #include <linux/tty.h> 53 #include <linux/tty_flip.h> 54 55 #ifdef CONFIG_SUPERH 56 #include <asm/sh_bios.h> 57 #endif 58 59 #include "serial_mctrl_gpio.h" 60 #include "sh-sci.h" 61 62 /* Offsets into the sci_port->irqs array */ 63 enum { 64 SCIx_ERI_IRQ, 65 SCIx_RXI_IRQ, 66 SCIx_TXI_IRQ, 67 SCIx_BRI_IRQ, 68 SCIx_DRI_IRQ, 69 SCIx_TEI_IRQ, 70 SCIx_NR_IRQS, 71 72 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */ 73 }; 74 75 #define SCIx_IRQ_IS_MUXED(port) \ 76 ((port)->irqs[SCIx_ERI_IRQ] == \ 77 (port)->irqs[SCIx_RXI_IRQ]) || \ 78 ((port)->irqs[SCIx_ERI_IRQ] && \ 79 ((port)->irqs[SCIx_RXI_IRQ] < 0)) 80 81 enum SCI_CLKS { 82 SCI_FCK, /* Functional Clock */ 83 SCI_SCK, /* Optional External Clock */ 84 SCI_BRG_INT, /* Optional BRG Internal Clock Source */ 85 SCI_SCIF_CLK, /* Optional BRG External Clock Source */ 86 SCI_NUM_CLKS 87 }; 88 89 /* Bit x set means sampling rate x + 1 is supported */ 90 #define SCI_SR(x) BIT((x) - 1) 91 #define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1) 92 93 #define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \ 94 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \ 95 SCI_SR(19) | SCI_SR(27) 96 97 #define min_sr(_port) ffs((_port)->sampling_rate_mask) 98 #define max_sr(_port) fls((_port)->sampling_rate_mask) 99 100 /* Iterate over all supported sampling rates, from high to low */ 101 #define for_each_sr(_sr, _port) \ 102 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \ 103 if ((_port)->sampling_rate_mask & SCI_SR((_sr))) 104 105 struct plat_sci_reg { 106 u8 offset, size; 107 }; 108 109 struct sci_port_params { 110 const struct plat_sci_reg regs[SCIx_NR_REGS]; 111 unsigned int fifosize; 112 unsigned int overrun_reg; 113 unsigned int overrun_mask; 114 unsigned int sampling_rate_mask; 115 unsigned int error_mask; 116 unsigned int error_clear; 117 }; 118 119 struct sci_port { 120 struct uart_port port; 121 122 /* Platform configuration */ 123 const struct sci_port_params *params; 124 const struct plat_sci_port *cfg; 125 unsigned int sampling_rate_mask; 126 resource_size_t reg_size; 127 struct mctrl_gpios *gpios; 128 129 /* Clocks */ 130 struct clk *clks[SCI_NUM_CLKS]; 131 unsigned long clk_rates[SCI_NUM_CLKS]; 132 133 int irqs[SCIx_NR_IRQS]; 134 char *irqstr[SCIx_NR_IRQS]; 135 136 struct dma_chan *chan_tx; 137 struct dma_chan *chan_rx; 138 139 #ifdef CONFIG_SERIAL_SH_SCI_DMA 140 struct dma_chan *chan_tx_saved; 141 struct dma_chan *chan_rx_saved; 142 dma_cookie_t cookie_tx; 143 dma_cookie_t cookie_rx[2]; 144 dma_cookie_t active_rx; 145 dma_addr_t tx_dma_addr; 146 unsigned int tx_dma_len; 147 struct scatterlist sg_rx[2]; 148 void *rx_buf[2]; 149 size_t buf_len_rx; 150 struct work_struct work_tx; 151 struct hrtimer rx_timer; 152 unsigned int rx_timeout; /* microseconds */ 153 #endif 154 unsigned int rx_frame; 155 int rx_trigger; 156 struct timer_list rx_fifo_timer; 157 int rx_fifo_timeout; 158 u16 hscif_tot; 159 160 bool has_rtscts; 161 bool autorts; 162 }; 163 164 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS 165 166 static struct sci_port sci_ports[SCI_NPORTS]; 167 static unsigned long sci_ports_in_use; 168 static struct uart_driver sci_uart_driver; 169 170 static inline struct sci_port * 171 to_sci_port(struct uart_port *uart) 172 { 173 return container_of(uart, struct sci_port, port); 174 } 175 176 static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { 177 /* 178 * Common SCI definitions, dependent on the port's regshift 179 * value. 180 */ 181 [SCIx_SCI_REGTYPE] = { 182 .regs = { 183 [SCSMR] = { 0x00, 8 }, 184 [SCBRR] = { 0x01, 8 }, 185 [SCSCR] = { 0x02, 8 }, 186 [SCxTDR] = { 0x03, 8 }, 187 [SCxSR] = { 0x04, 8 }, 188 [SCxRDR] = { 0x05, 8 }, 189 }, 190 .fifosize = 1, 191 .overrun_reg = SCxSR, 192 .overrun_mask = SCI_ORER, 193 .sampling_rate_mask = SCI_SR(32), 194 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, 195 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, 196 }, 197 198 /* 199 * Common definitions for legacy IrDA ports. 200 */ 201 [SCIx_IRDA_REGTYPE] = { 202 .regs = { 203 [SCSMR] = { 0x00, 8 }, 204 [SCBRR] = { 0x02, 8 }, 205 [SCSCR] = { 0x04, 8 }, 206 [SCxTDR] = { 0x06, 8 }, 207 [SCxSR] = { 0x08, 16 }, 208 [SCxRDR] = { 0x0a, 8 }, 209 [SCFCR] = { 0x0c, 8 }, 210 [SCFDR] = { 0x0e, 16 }, 211 }, 212 .fifosize = 1, 213 .overrun_reg = SCxSR, 214 .overrun_mask = SCI_ORER, 215 .sampling_rate_mask = SCI_SR(32), 216 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, 217 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, 218 }, 219 220 /* 221 * Common SCIFA definitions. 222 */ 223 [SCIx_SCIFA_REGTYPE] = { 224 .regs = { 225 [SCSMR] = { 0x00, 16 }, 226 [SCBRR] = { 0x04, 8 }, 227 [SCSCR] = { 0x08, 16 }, 228 [SCxTDR] = { 0x20, 8 }, 229 [SCxSR] = { 0x14, 16 }, 230 [SCxRDR] = { 0x24, 8 }, 231 [SCFCR] = { 0x18, 16 }, 232 [SCFDR] = { 0x1c, 16 }, 233 [SCPCR] = { 0x30, 16 }, 234 [SCPDR] = { 0x34, 16 }, 235 }, 236 .fifosize = 64, 237 .overrun_reg = SCxSR, 238 .overrun_mask = SCIFA_ORER, 239 .sampling_rate_mask = SCI_SR_SCIFAB, 240 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 241 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 242 }, 243 244 /* 245 * Common SCIFB definitions. 246 */ 247 [SCIx_SCIFB_REGTYPE] = { 248 .regs = { 249 [SCSMR] = { 0x00, 16 }, 250 [SCBRR] = { 0x04, 8 }, 251 [SCSCR] = { 0x08, 16 }, 252 [SCxTDR] = { 0x40, 8 }, 253 [SCxSR] = { 0x14, 16 }, 254 [SCxRDR] = { 0x60, 8 }, 255 [SCFCR] = { 0x18, 16 }, 256 [SCTFDR] = { 0x38, 16 }, 257 [SCRFDR] = { 0x3c, 16 }, 258 [SCPCR] = { 0x30, 16 }, 259 [SCPDR] = { 0x34, 16 }, 260 }, 261 .fifosize = 256, 262 .overrun_reg = SCxSR, 263 .overrun_mask = SCIFA_ORER, 264 .sampling_rate_mask = SCI_SR_SCIFAB, 265 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 266 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 267 }, 268 269 /* 270 * Common SH-2(A) SCIF definitions for ports with FIFO data 271 * count registers. 272 */ 273 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = { 274 .regs = { 275 [SCSMR] = { 0x00, 16 }, 276 [SCBRR] = { 0x04, 8 }, 277 [SCSCR] = { 0x08, 16 }, 278 [SCxTDR] = { 0x0c, 8 }, 279 [SCxSR] = { 0x10, 16 }, 280 [SCxRDR] = { 0x14, 8 }, 281 [SCFCR] = { 0x18, 16 }, 282 [SCFDR] = { 0x1c, 16 }, 283 [SCSPTR] = { 0x20, 16 }, 284 [SCLSR] = { 0x24, 16 }, 285 }, 286 .fifosize = 16, 287 .overrun_reg = SCLSR, 288 .overrun_mask = SCLSR_ORER, 289 .sampling_rate_mask = SCI_SR(32), 290 .error_mask = SCIF_DEFAULT_ERROR_MASK, 291 .error_clear = SCIF_ERROR_CLEAR, 292 }, 293 294 /* 295 * The "SCIFA" that is in RZ/T and RZ/A2. 296 * It looks like a normal SCIF with FIFO data, but with a 297 * compressed address space. Also, the break out of interrupts 298 * are different: ERI/BRI, RXI, TXI, TEI, DRI. 299 */ 300 [SCIx_RZ_SCIFA_REGTYPE] = { 301 .regs = { 302 [SCSMR] = { 0x00, 16 }, 303 [SCBRR] = { 0x02, 8 }, 304 [SCSCR] = { 0x04, 16 }, 305 [SCxTDR] = { 0x06, 8 }, 306 [SCxSR] = { 0x08, 16 }, 307 [SCxRDR] = { 0x0A, 8 }, 308 [SCFCR] = { 0x0C, 16 }, 309 [SCFDR] = { 0x0E, 16 }, 310 [SCSPTR] = { 0x10, 16 }, 311 [SCLSR] = { 0x12, 16 }, 312 }, 313 .fifosize = 16, 314 .overrun_reg = SCLSR, 315 .overrun_mask = SCLSR_ORER, 316 .sampling_rate_mask = SCI_SR(32), 317 .error_mask = SCIF_DEFAULT_ERROR_MASK, 318 .error_clear = SCIF_ERROR_CLEAR, 319 }, 320 321 /* 322 * Common SH-3 SCIF definitions. 323 */ 324 [SCIx_SH3_SCIF_REGTYPE] = { 325 .regs = { 326 [SCSMR] = { 0x00, 8 }, 327 [SCBRR] = { 0x02, 8 }, 328 [SCSCR] = { 0x04, 8 }, 329 [SCxTDR] = { 0x06, 8 }, 330 [SCxSR] = { 0x08, 16 }, 331 [SCxRDR] = { 0x0a, 8 }, 332 [SCFCR] = { 0x0c, 8 }, 333 [SCFDR] = { 0x0e, 16 }, 334 }, 335 .fifosize = 16, 336 .overrun_reg = SCLSR, 337 .overrun_mask = SCLSR_ORER, 338 .sampling_rate_mask = SCI_SR(32), 339 .error_mask = SCIF_DEFAULT_ERROR_MASK, 340 .error_clear = SCIF_ERROR_CLEAR, 341 }, 342 343 /* 344 * Common SH-4(A) SCIF(B) definitions. 345 */ 346 [SCIx_SH4_SCIF_REGTYPE] = { 347 .regs = { 348 [SCSMR] = { 0x00, 16 }, 349 [SCBRR] = { 0x04, 8 }, 350 [SCSCR] = { 0x08, 16 }, 351 [SCxTDR] = { 0x0c, 8 }, 352 [SCxSR] = { 0x10, 16 }, 353 [SCxRDR] = { 0x14, 8 }, 354 [SCFCR] = { 0x18, 16 }, 355 [SCFDR] = { 0x1c, 16 }, 356 [SCSPTR] = { 0x20, 16 }, 357 [SCLSR] = { 0x24, 16 }, 358 }, 359 .fifosize = 16, 360 .overrun_reg = SCLSR, 361 .overrun_mask = SCLSR_ORER, 362 .sampling_rate_mask = SCI_SR(32), 363 .error_mask = SCIF_DEFAULT_ERROR_MASK, 364 .error_clear = SCIF_ERROR_CLEAR, 365 }, 366 367 /* 368 * Common SCIF definitions for ports with a Baud Rate Generator for 369 * External Clock (BRG). 370 */ 371 [SCIx_SH4_SCIF_BRG_REGTYPE] = { 372 .regs = { 373 [SCSMR] = { 0x00, 16 }, 374 [SCBRR] = { 0x04, 8 }, 375 [SCSCR] = { 0x08, 16 }, 376 [SCxTDR] = { 0x0c, 8 }, 377 [SCxSR] = { 0x10, 16 }, 378 [SCxRDR] = { 0x14, 8 }, 379 [SCFCR] = { 0x18, 16 }, 380 [SCFDR] = { 0x1c, 16 }, 381 [SCSPTR] = { 0x20, 16 }, 382 [SCLSR] = { 0x24, 16 }, 383 [SCDL] = { 0x30, 16 }, 384 [SCCKS] = { 0x34, 16 }, 385 }, 386 .fifosize = 16, 387 .overrun_reg = SCLSR, 388 .overrun_mask = SCLSR_ORER, 389 .sampling_rate_mask = SCI_SR(32), 390 .error_mask = SCIF_DEFAULT_ERROR_MASK, 391 .error_clear = SCIF_ERROR_CLEAR, 392 }, 393 394 /* 395 * Common HSCIF definitions. 396 */ 397 [SCIx_HSCIF_REGTYPE] = { 398 .regs = { 399 [SCSMR] = { 0x00, 16 }, 400 [SCBRR] = { 0x04, 8 }, 401 [SCSCR] = { 0x08, 16 }, 402 [SCxTDR] = { 0x0c, 8 }, 403 [SCxSR] = { 0x10, 16 }, 404 [SCxRDR] = { 0x14, 8 }, 405 [SCFCR] = { 0x18, 16 }, 406 [SCFDR] = { 0x1c, 16 }, 407 [SCSPTR] = { 0x20, 16 }, 408 [SCLSR] = { 0x24, 16 }, 409 [HSSRR] = { 0x40, 16 }, 410 [SCDL] = { 0x30, 16 }, 411 [SCCKS] = { 0x34, 16 }, 412 [HSRTRGR] = { 0x54, 16 }, 413 [HSTTRGR] = { 0x58, 16 }, 414 }, 415 .fifosize = 128, 416 .overrun_reg = SCLSR, 417 .overrun_mask = SCLSR_ORER, 418 .sampling_rate_mask = SCI_SR_RANGE(8, 32), 419 .error_mask = SCIF_DEFAULT_ERROR_MASK, 420 .error_clear = SCIF_ERROR_CLEAR, 421 }, 422 423 /* 424 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR 425 * register. 426 */ 427 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = { 428 .regs = { 429 [SCSMR] = { 0x00, 16 }, 430 [SCBRR] = { 0x04, 8 }, 431 [SCSCR] = { 0x08, 16 }, 432 [SCxTDR] = { 0x0c, 8 }, 433 [SCxSR] = { 0x10, 16 }, 434 [SCxRDR] = { 0x14, 8 }, 435 [SCFCR] = { 0x18, 16 }, 436 [SCFDR] = { 0x1c, 16 }, 437 [SCLSR] = { 0x24, 16 }, 438 }, 439 .fifosize = 16, 440 .overrun_reg = SCLSR, 441 .overrun_mask = SCLSR_ORER, 442 .sampling_rate_mask = SCI_SR(32), 443 .error_mask = SCIF_DEFAULT_ERROR_MASK, 444 .error_clear = SCIF_ERROR_CLEAR, 445 }, 446 447 /* 448 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data 449 * count registers. 450 */ 451 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = { 452 .regs = { 453 [SCSMR] = { 0x00, 16 }, 454 [SCBRR] = { 0x04, 8 }, 455 [SCSCR] = { 0x08, 16 }, 456 [SCxTDR] = { 0x0c, 8 }, 457 [SCxSR] = { 0x10, 16 }, 458 [SCxRDR] = { 0x14, 8 }, 459 [SCFCR] = { 0x18, 16 }, 460 [SCFDR] = { 0x1c, 16 }, 461 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */ 462 [SCRFDR] = { 0x20, 16 }, 463 [SCSPTR] = { 0x24, 16 }, 464 [SCLSR] = { 0x28, 16 }, 465 }, 466 .fifosize = 16, 467 .overrun_reg = SCLSR, 468 .overrun_mask = SCLSR_ORER, 469 .sampling_rate_mask = SCI_SR(32), 470 .error_mask = SCIF_DEFAULT_ERROR_MASK, 471 .error_clear = SCIF_ERROR_CLEAR, 472 }, 473 474 /* 475 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR 476 * registers. 477 */ 478 [SCIx_SH7705_SCIF_REGTYPE] = { 479 .regs = { 480 [SCSMR] = { 0x00, 16 }, 481 [SCBRR] = { 0x04, 8 }, 482 [SCSCR] = { 0x08, 16 }, 483 [SCxTDR] = { 0x20, 8 }, 484 [SCxSR] = { 0x14, 16 }, 485 [SCxRDR] = { 0x24, 8 }, 486 [SCFCR] = { 0x18, 16 }, 487 [SCFDR] = { 0x1c, 16 }, 488 }, 489 .fifosize = 64, 490 .overrun_reg = SCxSR, 491 .overrun_mask = SCIFA_ORER, 492 .sampling_rate_mask = SCI_SR(16), 493 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 494 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 495 }, 496 }; 497 498 #define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset]) 499 500 /* 501 * The "offset" here is rather misleading, in that it refers to an enum 502 * value relative to the port mapping rather than the fixed offset 503 * itself, which needs to be manually retrieved from the platform's 504 * register map for the given port. 505 */ 506 static unsigned int sci_serial_in(struct uart_port *p, int offset) 507 { 508 const struct plat_sci_reg *reg = sci_getreg(p, offset); 509 510 if (reg->size == 8) 511 return ioread8(p->membase + (reg->offset << p->regshift)); 512 else if (reg->size == 16) 513 return ioread16(p->membase + (reg->offset << p->regshift)); 514 else 515 WARN(1, "Invalid register access\n"); 516 517 return 0; 518 } 519 520 static void sci_serial_out(struct uart_port *p, int offset, int value) 521 { 522 const struct plat_sci_reg *reg = sci_getreg(p, offset); 523 524 if (reg->size == 8) 525 iowrite8(value, p->membase + (reg->offset << p->regshift)); 526 else if (reg->size == 16) 527 iowrite16(value, p->membase + (reg->offset << p->regshift)); 528 else 529 WARN(1, "Invalid register access\n"); 530 } 531 532 static void sci_port_enable(struct sci_port *sci_port) 533 { 534 unsigned int i; 535 536 if (!sci_port->port.dev) 537 return; 538 539 pm_runtime_get_sync(sci_port->port.dev); 540 541 for (i = 0; i < SCI_NUM_CLKS; i++) { 542 clk_prepare_enable(sci_port->clks[i]); 543 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]); 544 } 545 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK]; 546 } 547 548 static void sci_port_disable(struct sci_port *sci_port) 549 { 550 unsigned int i; 551 552 if (!sci_port->port.dev) 553 return; 554 555 for (i = SCI_NUM_CLKS; i-- > 0; ) 556 clk_disable_unprepare(sci_port->clks[i]); 557 558 pm_runtime_put_sync(sci_port->port.dev); 559 } 560 561 static inline unsigned long port_rx_irq_mask(struct uart_port *port) 562 { 563 /* 564 * Not all ports (such as SCIFA) will support REIE. Rather than 565 * special-casing the port type, we check the port initialization 566 * IRQ enable mask to see whether the IRQ is desired at all. If 567 * it's unset, it's logically inferred that there's no point in 568 * testing for it. 569 */ 570 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE); 571 } 572 573 static void sci_start_tx(struct uart_port *port) 574 { 575 struct sci_port *s = to_sci_port(port); 576 unsigned short ctrl; 577 578 #ifdef CONFIG_SERIAL_SH_SCI_DMA 579 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 580 u16 new, scr = serial_port_in(port, SCSCR); 581 if (s->chan_tx) 582 new = scr | SCSCR_TDRQE; 583 else 584 new = scr & ~SCSCR_TDRQE; 585 if (new != scr) 586 serial_port_out(port, SCSCR, new); 587 } 588 589 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) && 590 dma_submit_error(s->cookie_tx)) { 591 s->cookie_tx = 0; 592 schedule_work(&s->work_tx); 593 } 594 #endif 595 596 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 597 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ 598 ctrl = serial_port_in(port, SCSCR); 599 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE); 600 } 601 } 602 603 static void sci_stop_tx(struct uart_port *port) 604 { 605 unsigned short ctrl; 606 607 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ 608 ctrl = serial_port_in(port, SCSCR); 609 610 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 611 ctrl &= ~SCSCR_TDRQE; 612 613 ctrl &= ~SCSCR_TIE; 614 615 serial_port_out(port, SCSCR, ctrl); 616 } 617 618 static void sci_start_rx(struct uart_port *port) 619 { 620 unsigned short ctrl; 621 622 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port); 623 624 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 625 ctrl &= ~SCSCR_RDRQE; 626 627 serial_port_out(port, SCSCR, ctrl); 628 } 629 630 static void sci_stop_rx(struct uart_port *port) 631 { 632 unsigned short ctrl; 633 634 ctrl = serial_port_in(port, SCSCR); 635 636 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 637 ctrl &= ~SCSCR_RDRQE; 638 639 ctrl &= ~port_rx_irq_mask(port); 640 641 serial_port_out(port, SCSCR, ctrl); 642 } 643 644 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask) 645 { 646 if (port->type == PORT_SCI) { 647 /* Just store the mask */ 648 serial_port_out(port, SCxSR, mask); 649 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) { 650 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */ 651 /* Only clear the status bits we want to clear */ 652 serial_port_out(port, SCxSR, 653 serial_port_in(port, SCxSR) & mask); 654 } else { 655 /* Store the mask, clear parity/framing errors */ 656 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC)); 657 } 658 } 659 660 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ 661 defined(CONFIG_SERIAL_SH_SCI_EARLYCON) 662 663 #ifdef CONFIG_CONSOLE_POLL 664 static int sci_poll_get_char(struct uart_port *port) 665 { 666 unsigned short status; 667 int c; 668 669 do { 670 status = serial_port_in(port, SCxSR); 671 if (status & SCxSR_ERRORS(port)) { 672 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); 673 continue; 674 } 675 break; 676 } while (1); 677 678 if (!(status & SCxSR_RDxF(port))) 679 return NO_POLL_CHAR; 680 681 c = serial_port_in(port, SCxRDR); 682 683 /* Dummy read */ 684 serial_port_in(port, SCxSR); 685 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 686 687 return c; 688 } 689 #endif 690 691 static void sci_poll_put_char(struct uart_port *port, unsigned char c) 692 { 693 unsigned short status; 694 695 do { 696 status = serial_port_in(port, SCxSR); 697 } while (!(status & SCxSR_TDxE(port))); 698 699 serial_port_out(port, SCxTDR, c); 700 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port)); 701 } 702 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE || 703 CONFIG_SERIAL_SH_SCI_EARLYCON */ 704 705 static void sci_init_pins(struct uart_port *port, unsigned int cflag) 706 { 707 struct sci_port *s = to_sci_port(port); 708 709 /* 710 * Use port-specific handler if provided. 711 */ 712 if (s->cfg->ops && s->cfg->ops->init_pins) { 713 s->cfg->ops->init_pins(port, cflag); 714 return; 715 } 716 717 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 718 u16 data = serial_port_in(port, SCPDR); 719 u16 ctrl = serial_port_in(port, SCPCR); 720 721 /* Enable RXD and TXD pin functions */ 722 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC); 723 if (to_sci_port(port)->has_rtscts) { 724 /* RTS# is output, active low, unless autorts */ 725 if (!(port->mctrl & TIOCM_RTS)) { 726 ctrl |= SCPCR_RTSC; 727 data |= SCPDR_RTSD; 728 } else if (!s->autorts) { 729 ctrl |= SCPCR_RTSC; 730 data &= ~SCPDR_RTSD; 731 } else { 732 /* Enable RTS# pin function */ 733 ctrl &= ~SCPCR_RTSC; 734 } 735 /* Enable CTS# pin function */ 736 ctrl &= ~SCPCR_CTSC; 737 } 738 serial_port_out(port, SCPDR, data); 739 serial_port_out(port, SCPCR, ctrl); 740 } else if (sci_getreg(port, SCSPTR)->size) { 741 u16 status = serial_port_in(port, SCSPTR); 742 743 /* RTS# is always output; and active low, unless autorts */ 744 status |= SCSPTR_RTSIO; 745 if (!(port->mctrl & TIOCM_RTS)) 746 status |= SCSPTR_RTSDT; 747 else if (!s->autorts) 748 status &= ~SCSPTR_RTSDT; 749 /* CTS# and SCK are inputs */ 750 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO); 751 serial_port_out(port, SCSPTR, status); 752 } 753 } 754 755 static int sci_txfill(struct uart_port *port) 756 { 757 struct sci_port *s = to_sci_port(port); 758 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; 759 const struct plat_sci_reg *reg; 760 761 reg = sci_getreg(port, SCTFDR); 762 if (reg->size) 763 return serial_port_in(port, SCTFDR) & fifo_mask; 764 765 reg = sci_getreg(port, SCFDR); 766 if (reg->size) 767 return serial_port_in(port, SCFDR) >> 8; 768 769 return !(serial_port_in(port, SCxSR) & SCI_TDRE); 770 } 771 772 static int sci_txroom(struct uart_port *port) 773 { 774 return port->fifosize - sci_txfill(port); 775 } 776 777 static int sci_rxfill(struct uart_port *port) 778 { 779 struct sci_port *s = to_sci_port(port); 780 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; 781 const struct plat_sci_reg *reg; 782 783 reg = sci_getreg(port, SCRFDR); 784 if (reg->size) 785 return serial_port_in(port, SCRFDR) & fifo_mask; 786 787 reg = sci_getreg(port, SCFDR); 788 if (reg->size) 789 return serial_port_in(port, SCFDR) & fifo_mask; 790 791 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0; 792 } 793 794 /* ********************************************************************** * 795 * the interrupt related routines * 796 * ********************************************************************** */ 797 798 static void sci_transmit_chars(struct uart_port *port) 799 { 800 struct circ_buf *xmit = &port->state->xmit; 801 unsigned int stopped = uart_tx_stopped(port); 802 unsigned short status; 803 unsigned short ctrl; 804 int count; 805 806 status = serial_port_in(port, SCxSR); 807 if (!(status & SCxSR_TDxE(port))) { 808 ctrl = serial_port_in(port, SCSCR); 809 if (uart_circ_empty(xmit)) 810 ctrl &= ~SCSCR_TIE; 811 else 812 ctrl |= SCSCR_TIE; 813 serial_port_out(port, SCSCR, ctrl); 814 return; 815 } 816 817 count = sci_txroom(port); 818 819 do { 820 unsigned char c; 821 822 if (port->x_char) { 823 c = port->x_char; 824 port->x_char = 0; 825 } else if (!uart_circ_empty(xmit) && !stopped) { 826 c = xmit->buf[xmit->tail]; 827 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 828 } else { 829 break; 830 } 831 832 serial_port_out(port, SCxTDR, c); 833 834 port->icount.tx++; 835 } while (--count > 0); 836 837 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port)); 838 839 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 840 uart_write_wakeup(port); 841 if (uart_circ_empty(xmit)) 842 sci_stop_tx(port); 843 844 } 845 846 /* On SH3, SCIF may read end-of-break as a space->mark char */ 847 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); }) 848 849 static void sci_receive_chars(struct uart_port *port) 850 { 851 struct tty_port *tport = &port->state->port; 852 int i, count, copied = 0; 853 unsigned short status; 854 unsigned char flag; 855 856 status = serial_port_in(port, SCxSR); 857 if (!(status & SCxSR_RDxF(port))) 858 return; 859 860 while (1) { 861 /* Don't copy more bytes than there is room for in the buffer */ 862 count = tty_buffer_request_room(tport, sci_rxfill(port)); 863 864 /* If for any reason we can't copy more data, we're done! */ 865 if (count == 0) 866 break; 867 868 if (port->type == PORT_SCI) { 869 char c = serial_port_in(port, SCxRDR); 870 if (uart_handle_sysrq_char(port, c)) 871 count = 0; 872 else 873 tty_insert_flip_char(tport, c, TTY_NORMAL); 874 } else { 875 for (i = 0; i < count; i++) { 876 char c = serial_port_in(port, SCxRDR); 877 878 status = serial_port_in(port, SCxSR); 879 if (uart_handle_sysrq_char(port, c)) { 880 count--; i--; 881 continue; 882 } 883 884 /* Store data and status */ 885 if (status & SCxSR_FER(port)) { 886 flag = TTY_FRAME; 887 port->icount.frame++; 888 dev_notice(port->dev, "frame error\n"); 889 } else if (status & SCxSR_PER(port)) { 890 flag = TTY_PARITY; 891 port->icount.parity++; 892 dev_notice(port->dev, "parity error\n"); 893 } else 894 flag = TTY_NORMAL; 895 896 tty_insert_flip_char(tport, c, flag); 897 } 898 } 899 900 serial_port_in(port, SCxSR); /* dummy read */ 901 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 902 903 copied += count; 904 port->icount.rx += count; 905 } 906 907 if (copied) { 908 /* Tell the rest of the system the news. New characters! */ 909 tty_flip_buffer_push(tport); 910 } else { 911 /* TTY buffers full; read from RX reg to prevent lockup */ 912 serial_port_in(port, SCxRDR); 913 serial_port_in(port, SCxSR); /* dummy read */ 914 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 915 } 916 } 917 918 static int sci_handle_errors(struct uart_port *port) 919 { 920 int copied = 0; 921 unsigned short status = serial_port_in(port, SCxSR); 922 struct tty_port *tport = &port->state->port; 923 struct sci_port *s = to_sci_port(port); 924 925 /* Handle overruns */ 926 if (status & s->params->overrun_mask) { 927 port->icount.overrun++; 928 929 /* overrun error */ 930 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN)) 931 copied++; 932 933 dev_notice(port->dev, "overrun error\n"); 934 } 935 936 if (status & SCxSR_FER(port)) { 937 /* frame error */ 938 port->icount.frame++; 939 940 if (tty_insert_flip_char(tport, 0, TTY_FRAME)) 941 copied++; 942 943 dev_notice(port->dev, "frame error\n"); 944 } 945 946 if (status & SCxSR_PER(port)) { 947 /* parity error */ 948 port->icount.parity++; 949 950 if (tty_insert_flip_char(tport, 0, TTY_PARITY)) 951 copied++; 952 953 dev_notice(port->dev, "parity error\n"); 954 } 955 956 if (copied) 957 tty_flip_buffer_push(tport); 958 959 return copied; 960 } 961 962 static int sci_handle_fifo_overrun(struct uart_port *port) 963 { 964 struct tty_port *tport = &port->state->port; 965 struct sci_port *s = to_sci_port(port); 966 const struct plat_sci_reg *reg; 967 int copied = 0; 968 u16 status; 969 970 reg = sci_getreg(port, s->params->overrun_reg); 971 if (!reg->size) 972 return 0; 973 974 status = serial_port_in(port, s->params->overrun_reg); 975 if (status & s->params->overrun_mask) { 976 status &= ~s->params->overrun_mask; 977 serial_port_out(port, s->params->overrun_reg, status); 978 979 port->icount.overrun++; 980 981 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 982 tty_flip_buffer_push(tport); 983 984 dev_dbg(port->dev, "overrun error\n"); 985 copied++; 986 } 987 988 return copied; 989 } 990 991 static int sci_handle_breaks(struct uart_port *port) 992 { 993 int copied = 0; 994 unsigned short status = serial_port_in(port, SCxSR); 995 struct tty_port *tport = &port->state->port; 996 997 if (uart_handle_break(port)) 998 return 0; 999 1000 if (status & SCxSR_BRK(port)) { 1001 port->icount.brk++; 1002 1003 /* Notify of BREAK */ 1004 if (tty_insert_flip_char(tport, 0, TTY_BREAK)) 1005 copied++; 1006 1007 dev_dbg(port->dev, "BREAK detected\n"); 1008 } 1009 1010 if (copied) 1011 tty_flip_buffer_push(tport); 1012 1013 copied += sci_handle_fifo_overrun(port); 1014 1015 return copied; 1016 } 1017 1018 static int scif_set_rtrg(struct uart_port *port, int rx_trig) 1019 { 1020 unsigned int bits; 1021 1022 if (rx_trig < 1) 1023 rx_trig = 1; 1024 if (rx_trig >= port->fifosize) 1025 rx_trig = port->fifosize; 1026 1027 /* HSCIF can be set to an arbitrary level. */ 1028 if (sci_getreg(port, HSRTRGR)->size) { 1029 serial_port_out(port, HSRTRGR, rx_trig); 1030 return rx_trig; 1031 } 1032 1033 switch (port->type) { 1034 case PORT_SCIF: 1035 if (rx_trig < 4) { 1036 bits = 0; 1037 rx_trig = 1; 1038 } else if (rx_trig < 8) { 1039 bits = SCFCR_RTRG0; 1040 rx_trig = 4; 1041 } else if (rx_trig < 14) { 1042 bits = SCFCR_RTRG1; 1043 rx_trig = 8; 1044 } else { 1045 bits = SCFCR_RTRG0 | SCFCR_RTRG1; 1046 rx_trig = 14; 1047 } 1048 break; 1049 case PORT_SCIFA: 1050 case PORT_SCIFB: 1051 if (rx_trig < 16) { 1052 bits = 0; 1053 rx_trig = 1; 1054 } else if (rx_trig < 32) { 1055 bits = SCFCR_RTRG0; 1056 rx_trig = 16; 1057 } else if (rx_trig < 48) { 1058 bits = SCFCR_RTRG1; 1059 rx_trig = 32; 1060 } else { 1061 bits = SCFCR_RTRG0 | SCFCR_RTRG1; 1062 rx_trig = 48; 1063 } 1064 break; 1065 default: 1066 WARN(1, "unknown FIFO configuration"); 1067 return 1; 1068 } 1069 1070 serial_port_out(port, SCFCR, 1071 (serial_port_in(port, SCFCR) & 1072 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits); 1073 1074 return rx_trig; 1075 } 1076 1077 static int scif_rtrg_enabled(struct uart_port *port) 1078 { 1079 if (sci_getreg(port, HSRTRGR)->size) 1080 return serial_port_in(port, HSRTRGR) != 0; 1081 else 1082 return (serial_port_in(port, SCFCR) & 1083 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0; 1084 } 1085 1086 static void rx_fifo_timer_fn(struct timer_list *t) 1087 { 1088 struct sci_port *s = from_timer(s, t, rx_fifo_timer); 1089 struct uart_port *port = &s->port; 1090 1091 dev_dbg(port->dev, "Rx timed out\n"); 1092 scif_set_rtrg(port, 1); 1093 } 1094 1095 static ssize_t rx_fifo_trigger_show(struct device *dev, 1096 struct device_attribute *attr, char *buf) 1097 { 1098 struct uart_port *port = dev_get_drvdata(dev); 1099 struct sci_port *sci = to_sci_port(port); 1100 1101 return sprintf(buf, "%d\n", sci->rx_trigger); 1102 } 1103 1104 static ssize_t rx_fifo_trigger_store(struct device *dev, 1105 struct device_attribute *attr, 1106 const char *buf, size_t count) 1107 { 1108 struct uart_port *port = dev_get_drvdata(dev); 1109 struct sci_port *sci = to_sci_port(port); 1110 int ret; 1111 long r; 1112 1113 ret = kstrtol(buf, 0, &r); 1114 if (ret) 1115 return ret; 1116 1117 sci->rx_trigger = scif_set_rtrg(port, r); 1118 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1119 scif_set_rtrg(port, 1); 1120 1121 return count; 1122 } 1123 1124 static DEVICE_ATTR_RW(rx_fifo_trigger); 1125 1126 static ssize_t rx_fifo_timeout_show(struct device *dev, 1127 struct device_attribute *attr, 1128 char *buf) 1129 { 1130 struct uart_port *port = dev_get_drvdata(dev); 1131 struct sci_port *sci = to_sci_port(port); 1132 int v; 1133 1134 if (port->type == PORT_HSCIF) 1135 v = sci->hscif_tot >> HSSCR_TOT_SHIFT; 1136 else 1137 v = sci->rx_fifo_timeout; 1138 1139 return sprintf(buf, "%d\n", v); 1140 } 1141 1142 static ssize_t rx_fifo_timeout_store(struct device *dev, 1143 struct device_attribute *attr, 1144 const char *buf, 1145 size_t count) 1146 { 1147 struct uart_port *port = dev_get_drvdata(dev); 1148 struct sci_port *sci = to_sci_port(port); 1149 int ret; 1150 long r; 1151 1152 ret = kstrtol(buf, 0, &r); 1153 if (ret) 1154 return ret; 1155 1156 if (port->type == PORT_HSCIF) { 1157 if (r < 0 || r > 3) 1158 return -EINVAL; 1159 sci->hscif_tot = r << HSSCR_TOT_SHIFT; 1160 } else { 1161 sci->rx_fifo_timeout = r; 1162 scif_set_rtrg(port, 1); 1163 if (r > 0) 1164 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0); 1165 } 1166 1167 return count; 1168 } 1169 1170 static DEVICE_ATTR_RW(rx_fifo_timeout); 1171 1172 1173 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1174 static void sci_dma_tx_complete(void *arg) 1175 { 1176 struct sci_port *s = arg; 1177 struct uart_port *port = &s->port; 1178 struct circ_buf *xmit = &port->state->xmit; 1179 unsigned long flags; 1180 1181 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1182 1183 spin_lock_irqsave(&port->lock, flags); 1184 1185 xmit->tail += s->tx_dma_len; 1186 xmit->tail &= UART_XMIT_SIZE - 1; 1187 1188 port->icount.tx += s->tx_dma_len; 1189 1190 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1191 uart_write_wakeup(port); 1192 1193 if (!uart_circ_empty(xmit)) { 1194 s->cookie_tx = 0; 1195 schedule_work(&s->work_tx); 1196 } else { 1197 s->cookie_tx = -EINVAL; 1198 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1199 u16 ctrl = serial_port_in(port, SCSCR); 1200 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE); 1201 } 1202 } 1203 1204 spin_unlock_irqrestore(&port->lock, flags); 1205 } 1206 1207 /* Locking: called with port lock held */ 1208 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count) 1209 { 1210 struct uart_port *port = &s->port; 1211 struct tty_port *tport = &port->state->port; 1212 int copied; 1213 1214 copied = tty_insert_flip_string(tport, buf, count); 1215 if (copied < count) 1216 port->icount.buf_overrun++; 1217 1218 port->icount.rx += copied; 1219 1220 return copied; 1221 } 1222 1223 static int sci_dma_rx_find_active(struct sci_port *s) 1224 { 1225 unsigned int i; 1226 1227 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) 1228 if (s->active_rx == s->cookie_rx[i]) 1229 return i; 1230 1231 return -1; 1232 } 1233 1234 static void sci_dma_rx_chan_invalidate(struct sci_port *s) 1235 { 1236 unsigned int i; 1237 1238 s->chan_rx = NULL; 1239 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) 1240 s->cookie_rx[i] = -EINVAL; 1241 s->active_rx = 0; 1242 } 1243 1244 static void sci_dma_rx_release(struct sci_port *s) 1245 { 1246 struct dma_chan *chan = s->chan_rx_saved; 1247 1248 s->chan_rx_saved = NULL; 1249 sci_dma_rx_chan_invalidate(s); 1250 dmaengine_terminate_sync(chan); 1251 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0], 1252 sg_dma_address(&s->sg_rx[0])); 1253 dma_release_channel(chan); 1254 } 1255 1256 static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec) 1257 { 1258 long sec = usec / 1000000; 1259 long nsec = (usec % 1000000) * 1000; 1260 ktime_t t = ktime_set(sec, nsec); 1261 1262 hrtimer_start(hrt, t, HRTIMER_MODE_REL); 1263 } 1264 1265 static void sci_dma_rx_reenable_irq(struct sci_port *s) 1266 { 1267 struct uart_port *port = &s->port; 1268 u16 scr; 1269 1270 /* Direct new serial port interrupts back to CPU */ 1271 scr = serial_port_in(port, SCSCR); 1272 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1273 scr &= ~SCSCR_RDRQE; 1274 enable_irq(s->irqs[SCIx_RXI_IRQ]); 1275 } 1276 serial_port_out(port, SCSCR, scr | SCSCR_RIE); 1277 } 1278 1279 static void sci_dma_rx_complete(void *arg) 1280 { 1281 struct sci_port *s = arg; 1282 struct dma_chan *chan = s->chan_rx; 1283 struct uart_port *port = &s->port; 1284 struct dma_async_tx_descriptor *desc; 1285 unsigned long flags; 1286 int active, count = 0; 1287 1288 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line, 1289 s->active_rx); 1290 1291 spin_lock_irqsave(&port->lock, flags); 1292 1293 active = sci_dma_rx_find_active(s); 1294 if (active >= 0) 1295 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx); 1296 1297 start_hrtimer_us(&s->rx_timer, s->rx_timeout); 1298 1299 if (count) 1300 tty_flip_buffer_push(&port->state->port); 1301 1302 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1, 1303 DMA_DEV_TO_MEM, 1304 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1305 if (!desc) 1306 goto fail; 1307 1308 desc->callback = sci_dma_rx_complete; 1309 desc->callback_param = s; 1310 s->cookie_rx[active] = dmaengine_submit(desc); 1311 if (dma_submit_error(s->cookie_rx[active])) 1312 goto fail; 1313 1314 s->active_rx = s->cookie_rx[!active]; 1315 1316 dma_async_issue_pending(chan); 1317 1318 spin_unlock_irqrestore(&port->lock, flags); 1319 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n", 1320 __func__, s->cookie_rx[active], active, s->active_rx); 1321 return; 1322 1323 fail: 1324 spin_unlock_irqrestore(&port->lock, flags); 1325 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n"); 1326 /* Switch to PIO */ 1327 spin_lock_irqsave(&port->lock, flags); 1328 dmaengine_terminate_async(chan); 1329 sci_dma_rx_chan_invalidate(s); 1330 sci_dma_rx_reenable_irq(s); 1331 spin_unlock_irqrestore(&port->lock, flags); 1332 } 1333 1334 static void sci_dma_tx_release(struct sci_port *s) 1335 { 1336 struct dma_chan *chan = s->chan_tx_saved; 1337 1338 cancel_work_sync(&s->work_tx); 1339 s->chan_tx_saved = s->chan_tx = NULL; 1340 s->cookie_tx = -EINVAL; 1341 dmaengine_terminate_sync(chan); 1342 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE, 1343 DMA_TO_DEVICE); 1344 dma_release_channel(chan); 1345 } 1346 1347 static int sci_dma_rx_submit(struct sci_port *s, bool port_lock_held) 1348 { 1349 struct dma_chan *chan = s->chan_rx; 1350 struct uart_port *port = &s->port; 1351 unsigned long flags; 1352 int i; 1353 1354 for (i = 0; i < 2; i++) { 1355 struct scatterlist *sg = &s->sg_rx[i]; 1356 struct dma_async_tx_descriptor *desc; 1357 1358 desc = dmaengine_prep_slave_sg(chan, 1359 sg, 1, DMA_DEV_TO_MEM, 1360 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1361 if (!desc) 1362 goto fail; 1363 1364 desc->callback = sci_dma_rx_complete; 1365 desc->callback_param = s; 1366 s->cookie_rx[i] = dmaengine_submit(desc); 1367 if (dma_submit_error(s->cookie_rx[i])) 1368 goto fail; 1369 1370 } 1371 1372 s->active_rx = s->cookie_rx[0]; 1373 1374 dma_async_issue_pending(chan); 1375 return 0; 1376 1377 fail: 1378 /* Switch to PIO */ 1379 if (!port_lock_held) 1380 spin_lock_irqsave(&port->lock, flags); 1381 if (i) 1382 dmaengine_terminate_async(chan); 1383 sci_dma_rx_chan_invalidate(s); 1384 sci_start_rx(port); 1385 if (!port_lock_held) 1386 spin_unlock_irqrestore(&port->lock, flags); 1387 return -EAGAIN; 1388 } 1389 1390 static void sci_dma_tx_work_fn(struct work_struct *work) 1391 { 1392 struct sci_port *s = container_of(work, struct sci_port, work_tx); 1393 struct dma_async_tx_descriptor *desc; 1394 struct dma_chan *chan = s->chan_tx; 1395 struct uart_port *port = &s->port; 1396 struct circ_buf *xmit = &port->state->xmit; 1397 unsigned long flags; 1398 dma_addr_t buf; 1399 int head, tail; 1400 1401 /* 1402 * DMA is idle now. 1403 * Port xmit buffer is already mapped, and it is one page... Just adjust 1404 * offsets and lengths. Since it is a circular buffer, we have to 1405 * transmit till the end, and then the rest. Take the port lock to get a 1406 * consistent xmit buffer state. 1407 */ 1408 spin_lock_irq(&port->lock); 1409 head = xmit->head; 1410 tail = xmit->tail; 1411 buf = s->tx_dma_addr + (tail & (UART_XMIT_SIZE - 1)); 1412 s->tx_dma_len = min_t(unsigned int, 1413 CIRC_CNT(head, tail, UART_XMIT_SIZE), 1414 CIRC_CNT_TO_END(head, tail, UART_XMIT_SIZE)); 1415 if (!s->tx_dma_len) { 1416 /* Transmit buffer has been flushed */ 1417 spin_unlock_irq(&port->lock); 1418 return; 1419 } 1420 1421 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len, 1422 DMA_MEM_TO_DEV, 1423 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1424 if (!desc) { 1425 spin_unlock_irq(&port->lock); 1426 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n"); 1427 goto switch_to_pio; 1428 } 1429 1430 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len, 1431 DMA_TO_DEVICE); 1432 1433 desc->callback = sci_dma_tx_complete; 1434 desc->callback_param = s; 1435 s->cookie_tx = dmaengine_submit(desc); 1436 if (dma_submit_error(s->cookie_tx)) { 1437 spin_unlock_irq(&port->lock); 1438 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n"); 1439 goto switch_to_pio; 1440 } 1441 1442 spin_unlock_irq(&port->lock); 1443 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", 1444 __func__, xmit->buf, tail, head, s->cookie_tx); 1445 1446 dma_async_issue_pending(chan); 1447 return; 1448 1449 switch_to_pio: 1450 spin_lock_irqsave(&port->lock, flags); 1451 s->chan_tx = NULL; 1452 sci_start_tx(port); 1453 spin_unlock_irqrestore(&port->lock, flags); 1454 return; 1455 } 1456 1457 static enum hrtimer_restart sci_dma_rx_timer_fn(struct hrtimer *t) 1458 { 1459 struct sci_port *s = container_of(t, struct sci_port, rx_timer); 1460 struct dma_chan *chan = s->chan_rx; 1461 struct uart_port *port = &s->port; 1462 struct dma_tx_state state; 1463 enum dma_status status; 1464 unsigned long flags; 1465 unsigned int read; 1466 int active, count; 1467 1468 dev_dbg(port->dev, "DMA Rx timed out\n"); 1469 1470 spin_lock_irqsave(&port->lock, flags); 1471 1472 active = sci_dma_rx_find_active(s); 1473 if (active < 0) { 1474 spin_unlock_irqrestore(&port->lock, flags); 1475 return HRTIMER_NORESTART; 1476 } 1477 1478 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); 1479 if (status == DMA_COMPLETE) { 1480 spin_unlock_irqrestore(&port->lock, flags); 1481 dev_dbg(port->dev, "Cookie %d #%d has already completed\n", 1482 s->active_rx, active); 1483 1484 /* Let packet complete handler take care of the packet */ 1485 return HRTIMER_NORESTART; 1486 } 1487 1488 dmaengine_pause(chan); 1489 1490 /* 1491 * sometimes DMA transfer doesn't stop even if it is stopped and 1492 * data keeps on coming until transaction is complete so check 1493 * for DMA_COMPLETE again 1494 * Let packet complete handler take care of the packet 1495 */ 1496 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); 1497 if (status == DMA_COMPLETE) { 1498 spin_unlock_irqrestore(&port->lock, flags); 1499 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped"); 1500 return HRTIMER_NORESTART; 1501 } 1502 1503 /* Handle incomplete DMA receive */ 1504 dmaengine_terminate_async(s->chan_rx); 1505 read = sg_dma_len(&s->sg_rx[active]) - state.residue; 1506 1507 if (read) { 1508 count = sci_dma_rx_push(s, s->rx_buf[active], read); 1509 if (count) 1510 tty_flip_buffer_push(&port->state->port); 1511 } 1512 1513 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1514 sci_dma_rx_submit(s, true); 1515 1516 sci_dma_rx_reenable_irq(s); 1517 1518 spin_unlock_irqrestore(&port->lock, flags); 1519 1520 return HRTIMER_NORESTART; 1521 } 1522 1523 static struct dma_chan *sci_request_dma_chan(struct uart_port *port, 1524 enum dma_transfer_direction dir) 1525 { 1526 struct dma_chan *chan; 1527 struct dma_slave_config cfg; 1528 int ret; 1529 1530 chan = dma_request_slave_channel(port->dev, 1531 dir == DMA_MEM_TO_DEV ? "tx" : "rx"); 1532 if (!chan) { 1533 dev_dbg(port->dev, "dma_request_slave_channel failed\n"); 1534 return NULL; 1535 } 1536 1537 memset(&cfg, 0, sizeof(cfg)); 1538 cfg.direction = dir; 1539 if (dir == DMA_MEM_TO_DEV) { 1540 cfg.dst_addr = port->mapbase + 1541 (sci_getreg(port, SCxTDR)->offset << port->regshift); 1542 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1543 } else { 1544 cfg.src_addr = port->mapbase + 1545 (sci_getreg(port, SCxRDR)->offset << port->regshift); 1546 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1547 } 1548 1549 ret = dmaengine_slave_config(chan, &cfg); 1550 if (ret) { 1551 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret); 1552 dma_release_channel(chan); 1553 return NULL; 1554 } 1555 1556 return chan; 1557 } 1558 1559 static void sci_request_dma(struct uart_port *port) 1560 { 1561 struct sci_port *s = to_sci_port(port); 1562 struct dma_chan *chan; 1563 1564 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line); 1565 1566 /* 1567 * DMA on console may interfere with Kernel log messages which use 1568 * plain putchar(). So, simply don't use it with a console. 1569 */ 1570 if (uart_console(port)) 1571 return; 1572 1573 if (!port->dev->of_node) 1574 return; 1575 1576 s->cookie_tx = -EINVAL; 1577 1578 /* 1579 * Don't request a dma channel if no channel was specified 1580 * in the device tree. 1581 */ 1582 if (!of_find_property(port->dev->of_node, "dmas", NULL)) 1583 return; 1584 1585 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV); 1586 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan); 1587 if (chan) { 1588 /* UART circular tx buffer is an aligned page. */ 1589 s->tx_dma_addr = dma_map_single(chan->device->dev, 1590 port->state->xmit.buf, 1591 UART_XMIT_SIZE, 1592 DMA_TO_DEVICE); 1593 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) { 1594 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n"); 1595 dma_release_channel(chan); 1596 } else { 1597 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n", 1598 __func__, UART_XMIT_SIZE, 1599 port->state->xmit.buf, &s->tx_dma_addr); 1600 1601 INIT_WORK(&s->work_tx, sci_dma_tx_work_fn); 1602 s->chan_tx_saved = s->chan_tx = chan; 1603 } 1604 } 1605 1606 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM); 1607 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan); 1608 if (chan) { 1609 unsigned int i; 1610 dma_addr_t dma; 1611 void *buf; 1612 1613 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize); 1614 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2, 1615 &dma, GFP_KERNEL); 1616 if (!buf) { 1617 dev_warn(port->dev, 1618 "Failed to allocate Rx dma buffer, using PIO\n"); 1619 dma_release_channel(chan); 1620 return; 1621 } 1622 1623 for (i = 0; i < 2; i++) { 1624 struct scatterlist *sg = &s->sg_rx[i]; 1625 1626 sg_init_table(sg, 1); 1627 s->rx_buf[i] = buf; 1628 sg_dma_address(sg) = dma; 1629 sg_dma_len(sg) = s->buf_len_rx; 1630 1631 buf += s->buf_len_rx; 1632 dma += s->buf_len_rx; 1633 } 1634 1635 hrtimer_init(&s->rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 1636 s->rx_timer.function = sci_dma_rx_timer_fn; 1637 1638 s->chan_rx_saved = s->chan_rx = chan; 1639 1640 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1641 sci_dma_rx_submit(s, false); 1642 } 1643 } 1644 1645 static void sci_free_dma(struct uart_port *port) 1646 { 1647 struct sci_port *s = to_sci_port(port); 1648 1649 if (s->chan_tx_saved) 1650 sci_dma_tx_release(s); 1651 if (s->chan_rx_saved) 1652 sci_dma_rx_release(s); 1653 } 1654 1655 static void sci_flush_buffer(struct uart_port *port) 1656 { 1657 struct sci_port *s = to_sci_port(port); 1658 1659 /* 1660 * In uart_flush_buffer(), the xmit circular buffer has just been 1661 * cleared, so we have to reset tx_dma_len accordingly, and stop any 1662 * pending transfers 1663 */ 1664 s->tx_dma_len = 0; 1665 if (s->chan_tx) { 1666 dmaengine_terminate_async(s->chan_tx); 1667 s->cookie_tx = -EINVAL; 1668 } 1669 } 1670 #else /* !CONFIG_SERIAL_SH_SCI_DMA */ 1671 static inline void sci_request_dma(struct uart_port *port) 1672 { 1673 } 1674 1675 static inline void sci_free_dma(struct uart_port *port) 1676 { 1677 } 1678 1679 #define sci_flush_buffer NULL 1680 #endif /* !CONFIG_SERIAL_SH_SCI_DMA */ 1681 1682 static irqreturn_t sci_rx_interrupt(int irq, void *ptr) 1683 { 1684 struct uart_port *port = ptr; 1685 struct sci_port *s = to_sci_port(port); 1686 1687 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1688 if (s->chan_rx) { 1689 u16 scr = serial_port_in(port, SCSCR); 1690 u16 ssr = serial_port_in(port, SCxSR); 1691 1692 /* Disable future Rx interrupts */ 1693 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1694 disable_irq_nosync(irq); 1695 scr |= SCSCR_RDRQE; 1696 } else { 1697 if (sci_dma_rx_submit(s, false) < 0) 1698 goto handle_pio; 1699 1700 scr &= ~SCSCR_RIE; 1701 } 1702 serial_port_out(port, SCSCR, scr); 1703 /* Clear current interrupt */ 1704 serial_port_out(port, SCxSR, 1705 ssr & ~(SCIF_DR | SCxSR_RDxF(port))); 1706 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n", 1707 jiffies, s->rx_timeout); 1708 start_hrtimer_us(&s->rx_timer, s->rx_timeout); 1709 1710 return IRQ_HANDLED; 1711 } 1712 1713 handle_pio: 1714 #endif 1715 1716 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) { 1717 if (!scif_rtrg_enabled(port)) 1718 scif_set_rtrg(port, s->rx_trigger); 1719 1720 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP( 1721 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000)); 1722 } 1723 1724 /* I think sci_receive_chars has to be called irrespective 1725 * of whether the I_IXOFF is set, otherwise, how is the interrupt 1726 * to be disabled? 1727 */ 1728 sci_receive_chars(port); 1729 1730 return IRQ_HANDLED; 1731 } 1732 1733 static irqreturn_t sci_tx_interrupt(int irq, void *ptr) 1734 { 1735 struct uart_port *port = ptr; 1736 unsigned long flags; 1737 1738 spin_lock_irqsave(&port->lock, flags); 1739 sci_transmit_chars(port); 1740 spin_unlock_irqrestore(&port->lock, flags); 1741 1742 return IRQ_HANDLED; 1743 } 1744 1745 static irqreturn_t sci_br_interrupt(int irq, void *ptr) 1746 { 1747 struct uart_port *port = ptr; 1748 1749 /* Handle BREAKs */ 1750 sci_handle_breaks(port); 1751 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port)); 1752 1753 return IRQ_HANDLED; 1754 } 1755 1756 static irqreturn_t sci_er_interrupt(int irq, void *ptr) 1757 { 1758 struct uart_port *port = ptr; 1759 struct sci_port *s = to_sci_port(port); 1760 1761 if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) { 1762 /* Break and Error interrupts are muxed */ 1763 unsigned short ssr_status = serial_port_in(port, SCxSR); 1764 1765 /* Break Interrupt */ 1766 if (ssr_status & SCxSR_BRK(port)) 1767 sci_br_interrupt(irq, ptr); 1768 1769 /* Break only? */ 1770 if (!(ssr_status & SCxSR_ERRORS(port))) 1771 return IRQ_HANDLED; 1772 } 1773 1774 /* Handle errors */ 1775 if (port->type == PORT_SCI) { 1776 if (sci_handle_errors(port)) { 1777 /* discard character in rx buffer */ 1778 serial_port_in(port, SCxSR); 1779 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 1780 } 1781 } else { 1782 sci_handle_fifo_overrun(port); 1783 if (!s->chan_rx) 1784 sci_receive_chars(port); 1785 } 1786 1787 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); 1788 1789 /* Kick the transmission */ 1790 if (!s->chan_tx) 1791 sci_tx_interrupt(irq, ptr); 1792 1793 return IRQ_HANDLED; 1794 } 1795 1796 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) 1797 { 1798 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0; 1799 struct uart_port *port = ptr; 1800 struct sci_port *s = to_sci_port(port); 1801 irqreturn_t ret = IRQ_NONE; 1802 1803 ssr_status = serial_port_in(port, SCxSR); 1804 scr_status = serial_port_in(port, SCSCR); 1805 if (s->params->overrun_reg == SCxSR) 1806 orer_status = ssr_status; 1807 else if (sci_getreg(port, s->params->overrun_reg)->size) 1808 orer_status = serial_port_in(port, s->params->overrun_reg); 1809 1810 err_enabled = scr_status & port_rx_irq_mask(port); 1811 1812 /* Tx Interrupt */ 1813 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) && 1814 !s->chan_tx) 1815 ret = sci_tx_interrupt(irq, ptr); 1816 1817 /* 1818 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF / 1819 * DR flags 1820 */ 1821 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) && 1822 (scr_status & SCSCR_RIE)) 1823 ret = sci_rx_interrupt(irq, ptr); 1824 1825 /* Error Interrupt */ 1826 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled) 1827 ret = sci_er_interrupt(irq, ptr); 1828 1829 /* Break Interrupt */ 1830 if ((ssr_status & SCxSR_BRK(port)) && err_enabled) 1831 ret = sci_br_interrupt(irq, ptr); 1832 1833 /* Overrun Interrupt */ 1834 if (orer_status & s->params->overrun_mask) { 1835 sci_handle_fifo_overrun(port); 1836 ret = IRQ_HANDLED; 1837 } 1838 1839 return ret; 1840 } 1841 1842 static const struct sci_irq_desc { 1843 const char *desc; 1844 irq_handler_t handler; 1845 } sci_irq_desc[] = { 1846 /* 1847 * Split out handlers, the default case. 1848 */ 1849 [SCIx_ERI_IRQ] = { 1850 .desc = "rx err", 1851 .handler = sci_er_interrupt, 1852 }, 1853 1854 [SCIx_RXI_IRQ] = { 1855 .desc = "rx full", 1856 .handler = sci_rx_interrupt, 1857 }, 1858 1859 [SCIx_TXI_IRQ] = { 1860 .desc = "tx empty", 1861 .handler = sci_tx_interrupt, 1862 }, 1863 1864 [SCIx_BRI_IRQ] = { 1865 .desc = "break", 1866 .handler = sci_br_interrupt, 1867 }, 1868 1869 [SCIx_DRI_IRQ] = { 1870 .desc = "rx ready", 1871 .handler = sci_rx_interrupt, 1872 }, 1873 1874 [SCIx_TEI_IRQ] = { 1875 .desc = "tx end", 1876 .handler = sci_tx_interrupt, 1877 }, 1878 1879 /* 1880 * Special muxed handler. 1881 */ 1882 [SCIx_MUX_IRQ] = { 1883 .desc = "mux", 1884 .handler = sci_mpxed_interrupt, 1885 }, 1886 }; 1887 1888 static int sci_request_irq(struct sci_port *port) 1889 { 1890 struct uart_port *up = &port->port; 1891 int i, j, w, ret = 0; 1892 1893 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) { 1894 const struct sci_irq_desc *desc; 1895 int irq; 1896 1897 /* Check if already registered (muxed) */ 1898 for (w = 0; w < i; w++) 1899 if (port->irqs[w] == port->irqs[i]) 1900 w = i + 1; 1901 if (w > i) 1902 continue; 1903 1904 if (SCIx_IRQ_IS_MUXED(port)) { 1905 i = SCIx_MUX_IRQ; 1906 irq = up->irq; 1907 } else { 1908 irq = port->irqs[i]; 1909 1910 /* 1911 * Certain port types won't support all of the 1912 * available interrupt sources. 1913 */ 1914 if (unlikely(irq < 0)) 1915 continue; 1916 } 1917 1918 desc = sci_irq_desc + i; 1919 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s", 1920 dev_name(up->dev), desc->desc); 1921 if (!port->irqstr[j]) { 1922 ret = -ENOMEM; 1923 goto out_nomem; 1924 } 1925 1926 ret = request_irq(irq, desc->handler, up->irqflags, 1927 port->irqstr[j], port); 1928 if (unlikely(ret)) { 1929 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc); 1930 goto out_noirq; 1931 } 1932 } 1933 1934 return 0; 1935 1936 out_noirq: 1937 while (--i >= 0) 1938 free_irq(port->irqs[i], port); 1939 1940 out_nomem: 1941 while (--j >= 0) 1942 kfree(port->irqstr[j]); 1943 1944 return ret; 1945 } 1946 1947 static void sci_free_irq(struct sci_port *port) 1948 { 1949 int i, j; 1950 1951 /* 1952 * Intentionally in reverse order so we iterate over the muxed 1953 * IRQ first. 1954 */ 1955 for (i = 0; i < SCIx_NR_IRQS; i++) { 1956 int irq = port->irqs[i]; 1957 1958 /* 1959 * Certain port types won't support all of the available 1960 * interrupt sources. 1961 */ 1962 if (unlikely(irq < 0)) 1963 continue; 1964 1965 /* Check if already freed (irq was muxed) */ 1966 for (j = 0; j < i; j++) 1967 if (port->irqs[j] == irq) 1968 j = i + 1; 1969 if (j > i) 1970 continue; 1971 1972 free_irq(port->irqs[i], port); 1973 kfree(port->irqstr[i]); 1974 1975 if (SCIx_IRQ_IS_MUXED(port)) { 1976 /* If there's only one IRQ, we're done. */ 1977 return; 1978 } 1979 } 1980 } 1981 1982 static unsigned int sci_tx_empty(struct uart_port *port) 1983 { 1984 unsigned short status = serial_port_in(port, SCxSR); 1985 unsigned short in_tx_fifo = sci_txfill(port); 1986 1987 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0; 1988 } 1989 1990 static void sci_set_rts(struct uart_port *port, bool state) 1991 { 1992 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1993 u16 data = serial_port_in(port, SCPDR); 1994 1995 /* Active low */ 1996 if (state) 1997 data &= ~SCPDR_RTSD; 1998 else 1999 data |= SCPDR_RTSD; 2000 serial_port_out(port, SCPDR, data); 2001 2002 /* RTS# is output */ 2003 serial_port_out(port, SCPCR, 2004 serial_port_in(port, SCPCR) | SCPCR_RTSC); 2005 } else if (sci_getreg(port, SCSPTR)->size) { 2006 u16 ctrl = serial_port_in(port, SCSPTR); 2007 2008 /* Active low */ 2009 if (state) 2010 ctrl &= ~SCSPTR_RTSDT; 2011 else 2012 ctrl |= SCSPTR_RTSDT; 2013 serial_port_out(port, SCSPTR, ctrl); 2014 } 2015 } 2016 2017 static bool sci_get_cts(struct uart_port *port) 2018 { 2019 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 2020 /* Active low */ 2021 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD); 2022 } else if (sci_getreg(port, SCSPTR)->size) { 2023 /* Active low */ 2024 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT); 2025 } 2026 2027 return true; 2028 } 2029 2030 /* 2031 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally 2032 * CTS/RTS is supported in hardware by at least one port and controlled 2033 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently 2034 * handled via the ->init_pins() op, which is a bit of a one-way street, 2035 * lacking any ability to defer pin control -- this will later be 2036 * converted over to the GPIO framework). 2037 * 2038 * Other modes (such as loopback) are supported generically on certain 2039 * port types, but not others. For these it's sufficient to test for the 2040 * existence of the support register and simply ignore the port type. 2041 */ 2042 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) 2043 { 2044 struct sci_port *s = to_sci_port(port); 2045 2046 if (mctrl & TIOCM_LOOP) { 2047 const struct plat_sci_reg *reg; 2048 2049 /* 2050 * Standard loopback mode for SCFCR ports. 2051 */ 2052 reg = sci_getreg(port, SCFCR); 2053 if (reg->size) 2054 serial_port_out(port, SCFCR, 2055 serial_port_in(port, SCFCR) | 2056 SCFCR_LOOP); 2057 } 2058 2059 mctrl_gpio_set(s->gpios, mctrl); 2060 2061 if (!s->has_rtscts) 2062 return; 2063 2064 if (!(mctrl & TIOCM_RTS)) { 2065 /* Disable Auto RTS */ 2066 serial_port_out(port, SCFCR, 2067 serial_port_in(port, SCFCR) & ~SCFCR_MCE); 2068 2069 /* Clear RTS */ 2070 sci_set_rts(port, 0); 2071 } else if (s->autorts) { 2072 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 2073 /* Enable RTS# pin function */ 2074 serial_port_out(port, SCPCR, 2075 serial_port_in(port, SCPCR) & ~SCPCR_RTSC); 2076 } 2077 2078 /* Enable Auto RTS */ 2079 serial_port_out(port, SCFCR, 2080 serial_port_in(port, SCFCR) | SCFCR_MCE); 2081 } else { 2082 /* Set RTS */ 2083 sci_set_rts(port, 1); 2084 } 2085 } 2086 2087 static unsigned int sci_get_mctrl(struct uart_port *port) 2088 { 2089 struct sci_port *s = to_sci_port(port); 2090 struct mctrl_gpios *gpios = s->gpios; 2091 unsigned int mctrl = 0; 2092 2093 mctrl_gpio_get(gpios, &mctrl); 2094 2095 /* 2096 * CTS/RTS is handled in hardware when supported, while nothing 2097 * else is wired up. 2098 */ 2099 if (s->autorts) { 2100 if (sci_get_cts(port)) 2101 mctrl |= TIOCM_CTS; 2102 } else if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)) { 2103 mctrl |= TIOCM_CTS; 2104 } 2105 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)) 2106 mctrl |= TIOCM_DSR; 2107 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)) 2108 mctrl |= TIOCM_CAR; 2109 2110 return mctrl; 2111 } 2112 2113 static void sci_enable_ms(struct uart_port *port) 2114 { 2115 mctrl_gpio_enable_ms(to_sci_port(port)->gpios); 2116 } 2117 2118 static void sci_break_ctl(struct uart_port *port, int break_state) 2119 { 2120 unsigned short scscr, scsptr; 2121 unsigned long flags; 2122 2123 /* check wheter the port has SCSPTR */ 2124 if (!sci_getreg(port, SCSPTR)->size) { 2125 /* 2126 * Not supported by hardware. Most parts couple break and rx 2127 * interrupts together, with break detection always enabled. 2128 */ 2129 return; 2130 } 2131 2132 spin_lock_irqsave(&port->lock, flags); 2133 scsptr = serial_port_in(port, SCSPTR); 2134 scscr = serial_port_in(port, SCSCR); 2135 2136 if (break_state == -1) { 2137 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT; 2138 scscr &= ~SCSCR_TE; 2139 } else { 2140 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO; 2141 scscr |= SCSCR_TE; 2142 } 2143 2144 serial_port_out(port, SCSPTR, scsptr); 2145 serial_port_out(port, SCSCR, scscr); 2146 spin_unlock_irqrestore(&port->lock, flags); 2147 } 2148 2149 static int sci_startup(struct uart_port *port) 2150 { 2151 struct sci_port *s = to_sci_port(port); 2152 int ret; 2153 2154 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 2155 2156 sci_request_dma(port); 2157 2158 ret = sci_request_irq(s); 2159 if (unlikely(ret < 0)) { 2160 sci_free_dma(port); 2161 return ret; 2162 } 2163 2164 return 0; 2165 } 2166 2167 static void sci_shutdown(struct uart_port *port) 2168 { 2169 struct sci_port *s = to_sci_port(port); 2170 unsigned long flags; 2171 u16 scr; 2172 2173 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 2174 2175 s->autorts = false; 2176 mctrl_gpio_disable_ms(to_sci_port(port)->gpios); 2177 2178 spin_lock_irqsave(&port->lock, flags); 2179 sci_stop_rx(port); 2180 sci_stop_tx(port); 2181 /* 2182 * Stop RX and TX, disable related interrupts, keep clock source 2183 * and HSCIF TOT bits 2184 */ 2185 scr = serial_port_in(port, SCSCR); 2186 serial_port_out(port, SCSCR, scr & 2187 (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot)); 2188 spin_unlock_irqrestore(&port->lock, flags); 2189 2190 #ifdef CONFIG_SERIAL_SH_SCI_DMA 2191 if (s->chan_rx_saved) { 2192 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__, 2193 port->line); 2194 hrtimer_cancel(&s->rx_timer); 2195 } 2196 #endif 2197 2198 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) 2199 del_timer_sync(&s->rx_fifo_timer); 2200 sci_free_irq(s); 2201 sci_free_dma(port); 2202 } 2203 2204 static int sci_sck_calc(struct sci_port *s, unsigned int bps, 2205 unsigned int *srr) 2206 { 2207 unsigned long freq = s->clk_rates[SCI_SCK]; 2208 int err, min_err = INT_MAX; 2209 unsigned int sr; 2210 2211 if (s->port.type != PORT_HSCIF) 2212 freq *= 2; 2213 2214 for_each_sr(sr, s) { 2215 err = DIV_ROUND_CLOSEST(freq, sr) - bps; 2216 if (abs(err) >= abs(min_err)) 2217 continue; 2218 2219 min_err = err; 2220 *srr = sr - 1; 2221 2222 if (!err) 2223 break; 2224 } 2225 2226 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err, 2227 *srr + 1); 2228 return min_err; 2229 } 2230 2231 static int sci_brg_calc(struct sci_port *s, unsigned int bps, 2232 unsigned long freq, unsigned int *dlr, 2233 unsigned int *srr) 2234 { 2235 int err, min_err = INT_MAX; 2236 unsigned int sr, dl; 2237 2238 if (s->port.type != PORT_HSCIF) 2239 freq *= 2; 2240 2241 for_each_sr(sr, s) { 2242 dl = DIV_ROUND_CLOSEST(freq, sr * bps); 2243 dl = clamp(dl, 1U, 65535U); 2244 2245 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps; 2246 if (abs(err) >= abs(min_err)) 2247 continue; 2248 2249 min_err = err; 2250 *dlr = dl; 2251 *srr = sr - 1; 2252 2253 if (!err) 2254 break; 2255 } 2256 2257 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps, 2258 min_err, *dlr, *srr + 1); 2259 return min_err; 2260 } 2261 2262 /* calculate sample rate, BRR, and clock select */ 2263 static int sci_scbrr_calc(struct sci_port *s, unsigned int bps, 2264 unsigned int *brr, unsigned int *srr, 2265 unsigned int *cks) 2266 { 2267 unsigned long freq = s->clk_rates[SCI_FCK]; 2268 unsigned int sr, br, prediv, scrate, c; 2269 int err, min_err = INT_MAX; 2270 2271 if (s->port.type != PORT_HSCIF) 2272 freq *= 2; 2273 2274 /* 2275 * Find the combination of sample rate and clock select with the 2276 * smallest deviation from the desired baud rate. 2277 * Prefer high sample rates to maximise the receive margin. 2278 * 2279 * M: Receive margin (%) 2280 * N: Ratio of bit rate to clock (N = sampling rate) 2281 * D: Clock duty (D = 0 to 1.0) 2282 * L: Frame length (L = 9 to 12) 2283 * F: Absolute value of clock frequency deviation 2284 * 2285 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) - 2286 * (|D - 0.5| / N * (1 + F))| 2287 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation. 2288 */ 2289 for_each_sr(sr, s) { 2290 for (c = 0; c <= 3; c++) { 2291 /* integerized formulas from HSCIF documentation */ 2292 prediv = sr * (1 << (2 * c + 1)); 2293 2294 /* 2295 * We need to calculate: 2296 * 2297 * br = freq / (prediv * bps) clamped to [1..256] 2298 * err = freq / (br * prediv) - bps 2299 * 2300 * Watch out for overflow when calculating the desired 2301 * sampling clock rate! 2302 */ 2303 if (bps > UINT_MAX / prediv) 2304 break; 2305 2306 scrate = prediv * bps; 2307 br = DIV_ROUND_CLOSEST(freq, scrate); 2308 br = clamp(br, 1U, 256U); 2309 2310 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps; 2311 if (abs(err) >= abs(min_err)) 2312 continue; 2313 2314 min_err = err; 2315 *brr = br - 1; 2316 *srr = sr - 1; 2317 *cks = c; 2318 2319 if (!err) 2320 goto found; 2321 } 2322 } 2323 2324 found: 2325 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps, 2326 min_err, *brr, *srr + 1, *cks); 2327 return min_err; 2328 } 2329 2330 static void sci_reset(struct uart_port *port) 2331 { 2332 const struct plat_sci_reg *reg; 2333 unsigned int status; 2334 struct sci_port *s = to_sci_port(port); 2335 2336 serial_port_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */ 2337 2338 reg = sci_getreg(port, SCFCR); 2339 if (reg->size) 2340 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); 2341 2342 sci_clear_SCxSR(port, 2343 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) & 2344 SCxSR_BREAK_CLEAR(port)); 2345 if (sci_getreg(port, SCLSR)->size) { 2346 status = serial_port_in(port, SCLSR); 2347 status &= ~(SCLSR_TO | SCLSR_ORER); 2348 serial_port_out(port, SCLSR, status); 2349 } 2350 2351 if (s->rx_trigger > 1) { 2352 if (s->rx_fifo_timeout) { 2353 scif_set_rtrg(port, 1); 2354 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0); 2355 } else { 2356 if (port->type == PORT_SCIFA || 2357 port->type == PORT_SCIFB) 2358 scif_set_rtrg(port, 1); 2359 else 2360 scif_set_rtrg(port, s->rx_trigger); 2361 } 2362 } 2363 } 2364 2365 static void sci_set_termios(struct uart_port *port, struct ktermios *termios, 2366 struct ktermios *old) 2367 { 2368 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits; 2369 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0; 2370 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0; 2371 struct sci_port *s = to_sci_port(port); 2372 const struct plat_sci_reg *reg; 2373 int min_err = INT_MAX, err; 2374 unsigned long max_freq = 0; 2375 int best_clk = -1; 2376 unsigned long flags; 2377 2378 if ((termios->c_cflag & CSIZE) == CS7) 2379 smr_val |= SCSMR_CHR; 2380 if (termios->c_cflag & PARENB) 2381 smr_val |= SCSMR_PE; 2382 if (termios->c_cflag & PARODD) 2383 smr_val |= SCSMR_PE | SCSMR_ODD; 2384 if (termios->c_cflag & CSTOPB) 2385 smr_val |= SCSMR_STOP; 2386 2387 /* 2388 * earlyprintk comes here early on with port->uartclk set to zero. 2389 * the clock framework is not up and running at this point so here 2390 * we assume that 115200 is the maximum baud rate. please note that 2391 * the baud rate is not programmed during earlyprintk - it is assumed 2392 * that the previous boot loader has enabled required clocks and 2393 * setup the baud rate generator hardware for us already. 2394 */ 2395 if (!port->uartclk) { 2396 baud = uart_get_baud_rate(port, termios, old, 0, 115200); 2397 goto done; 2398 } 2399 2400 for (i = 0; i < SCI_NUM_CLKS; i++) 2401 max_freq = max(max_freq, s->clk_rates[i]); 2402 2403 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s)); 2404 if (!baud) 2405 goto done; 2406 2407 /* 2408 * There can be multiple sources for the sampling clock. Find the one 2409 * that gives us the smallest deviation from the desired baud rate. 2410 */ 2411 2412 /* Optional Undivided External Clock */ 2413 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA && 2414 port->type != PORT_SCIFB) { 2415 err = sci_sck_calc(s, baud, &srr1); 2416 if (abs(err) < abs(min_err)) { 2417 best_clk = SCI_SCK; 2418 scr_val = SCSCR_CKE1; 2419 sccks = SCCKS_CKS; 2420 min_err = err; 2421 srr = srr1; 2422 if (!err) 2423 goto done; 2424 } 2425 } 2426 2427 /* Optional BRG Frequency Divided External Clock */ 2428 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) { 2429 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1, 2430 &srr1); 2431 if (abs(err) < abs(min_err)) { 2432 best_clk = SCI_SCIF_CLK; 2433 scr_val = SCSCR_CKE1; 2434 sccks = 0; 2435 min_err = err; 2436 dl = dl1; 2437 srr = srr1; 2438 if (!err) 2439 goto done; 2440 } 2441 } 2442 2443 /* Optional BRG Frequency Divided Internal Clock */ 2444 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) { 2445 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1, 2446 &srr1); 2447 if (abs(err) < abs(min_err)) { 2448 best_clk = SCI_BRG_INT; 2449 scr_val = SCSCR_CKE1; 2450 sccks = SCCKS_XIN; 2451 min_err = err; 2452 dl = dl1; 2453 srr = srr1; 2454 if (!min_err) 2455 goto done; 2456 } 2457 } 2458 2459 /* Divided Functional Clock using standard Bit Rate Register */ 2460 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1); 2461 if (abs(err) < abs(min_err)) { 2462 best_clk = SCI_FCK; 2463 scr_val = 0; 2464 min_err = err; 2465 brr = brr1; 2466 srr = srr1; 2467 cks = cks1; 2468 } 2469 2470 done: 2471 if (best_clk >= 0) 2472 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n", 2473 s->clks[best_clk], baud, min_err); 2474 2475 sci_port_enable(s); 2476 2477 /* 2478 * Program the optional External Baud Rate Generator (BRG) first. 2479 * It controls the mux to select (H)SCK or frequency divided clock. 2480 */ 2481 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) { 2482 serial_port_out(port, SCDL, dl); 2483 serial_port_out(port, SCCKS, sccks); 2484 } 2485 2486 spin_lock_irqsave(&port->lock, flags); 2487 2488 sci_reset(port); 2489 2490 uart_update_timeout(port, termios->c_cflag, baud); 2491 2492 /* byte size and parity */ 2493 switch (termios->c_cflag & CSIZE) { 2494 case CS5: 2495 bits = 7; 2496 break; 2497 case CS6: 2498 bits = 8; 2499 break; 2500 case CS7: 2501 bits = 9; 2502 break; 2503 default: 2504 bits = 10; 2505 break; 2506 } 2507 2508 if (termios->c_cflag & CSTOPB) 2509 bits++; 2510 if (termios->c_cflag & PARENB) 2511 bits++; 2512 2513 if (best_clk >= 0) { 2514 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 2515 switch (srr + 1) { 2516 case 5: smr_val |= SCSMR_SRC_5; break; 2517 case 7: smr_val |= SCSMR_SRC_7; break; 2518 case 11: smr_val |= SCSMR_SRC_11; break; 2519 case 13: smr_val |= SCSMR_SRC_13; break; 2520 case 16: smr_val |= SCSMR_SRC_16; break; 2521 case 17: smr_val |= SCSMR_SRC_17; break; 2522 case 19: smr_val |= SCSMR_SRC_19; break; 2523 case 27: smr_val |= SCSMR_SRC_27; break; 2524 } 2525 smr_val |= cks; 2526 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); 2527 serial_port_out(port, SCSMR, smr_val); 2528 serial_port_out(port, SCBRR, brr); 2529 if (sci_getreg(port, HSSRR)->size) { 2530 unsigned int hssrr = srr | HSCIF_SRE; 2531 /* Calculate deviation from intended rate at the 2532 * center of the last stop bit in sampling clocks. 2533 */ 2534 int last_stop = bits * 2 - 1; 2535 int deviation = DIV_ROUND_CLOSEST(min_err * last_stop * 2536 (int)(srr + 1), 2537 2 * (int)baud); 2538 2539 if (abs(deviation) >= 2) { 2540 /* At least two sampling clocks off at the 2541 * last stop bit; we can increase the error 2542 * margin by shifting the sampling point. 2543 */ 2544 int shift = clamp(deviation / 2, -8, 7); 2545 2546 hssrr |= (shift << HSCIF_SRHP_SHIFT) & 2547 HSCIF_SRHP_MASK; 2548 hssrr |= HSCIF_SRDE; 2549 } 2550 serial_port_out(port, HSSRR, hssrr); 2551 } 2552 2553 /* Wait one bit interval */ 2554 udelay((1000000 + (baud - 1)) / baud); 2555 } else { 2556 /* Don't touch the bit rate configuration */ 2557 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0); 2558 smr_val |= serial_port_in(port, SCSMR) & 2559 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS); 2560 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); 2561 serial_port_out(port, SCSMR, smr_val); 2562 } 2563 2564 sci_init_pins(port, termios->c_cflag); 2565 2566 port->status &= ~UPSTAT_AUTOCTS; 2567 s->autorts = false; 2568 reg = sci_getreg(port, SCFCR); 2569 if (reg->size) { 2570 unsigned short ctrl = serial_port_in(port, SCFCR); 2571 2572 if ((port->flags & UPF_HARD_FLOW) && 2573 (termios->c_cflag & CRTSCTS)) { 2574 /* There is no CTS interrupt to restart the hardware */ 2575 port->status |= UPSTAT_AUTOCTS; 2576 /* MCE is enabled when RTS is raised */ 2577 s->autorts = true; 2578 } 2579 2580 /* 2581 * As we've done a sci_reset() above, ensure we don't 2582 * interfere with the FIFOs while toggling MCE. As the 2583 * reset values could still be set, simply mask them out. 2584 */ 2585 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST); 2586 2587 serial_port_out(port, SCFCR, ctrl); 2588 } 2589 if (port->flags & UPF_HARD_FLOW) { 2590 /* Refresh (Auto) RTS */ 2591 sci_set_mctrl(port, port->mctrl); 2592 } 2593 2594 scr_val |= SCSCR_RE | SCSCR_TE | 2595 (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)); 2596 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); 2597 if ((srr + 1 == 5) && 2598 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) { 2599 /* 2600 * In asynchronous mode, when the sampling rate is 1/5, first 2601 * received data may become invalid on some SCIFA and SCIFB. 2602 * To avoid this problem wait more than 1 serial data time (1 2603 * bit time x serial data number) after setting SCSCR.RE = 1. 2604 */ 2605 udelay(DIV_ROUND_UP(10 * 1000000, baud)); 2606 } 2607 2608 /* 2609 * Calculate delay for 2 DMA buffers (4 FIFO). 2610 * See serial_core.c::uart_update_timeout(). 2611 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above 2612 * function calculates 1 jiffie for the data plus 5 jiffies for the 2613 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA 2614 * buffers (4 FIFO sizes), but when performing a faster transfer, the 2615 * value obtained by this formula is too small. Therefore, if the value 2616 * is smaller than 20ms, use 20ms as the timeout value for DMA. 2617 */ 2618 s->rx_frame = (10000 * bits) / (baud / 100); 2619 #ifdef CONFIG_SERIAL_SH_SCI_DMA 2620 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame; 2621 if (s->rx_timeout < 20) 2622 s->rx_timeout = 20; 2623 #endif 2624 2625 if ((termios->c_cflag & CREAD) != 0) 2626 sci_start_rx(port); 2627 2628 spin_unlock_irqrestore(&port->lock, flags); 2629 2630 sci_port_disable(s); 2631 2632 if (UART_ENABLE_MS(port, termios->c_cflag)) 2633 sci_enable_ms(port); 2634 } 2635 2636 static void sci_pm(struct uart_port *port, unsigned int state, 2637 unsigned int oldstate) 2638 { 2639 struct sci_port *sci_port = to_sci_port(port); 2640 2641 switch (state) { 2642 case UART_PM_STATE_OFF: 2643 sci_port_disable(sci_port); 2644 break; 2645 default: 2646 sci_port_enable(sci_port); 2647 break; 2648 } 2649 } 2650 2651 static const char *sci_type(struct uart_port *port) 2652 { 2653 switch (port->type) { 2654 case PORT_IRDA: 2655 return "irda"; 2656 case PORT_SCI: 2657 return "sci"; 2658 case PORT_SCIF: 2659 return "scif"; 2660 case PORT_SCIFA: 2661 return "scifa"; 2662 case PORT_SCIFB: 2663 return "scifb"; 2664 case PORT_HSCIF: 2665 return "hscif"; 2666 } 2667 2668 return NULL; 2669 } 2670 2671 static int sci_remap_port(struct uart_port *port) 2672 { 2673 struct sci_port *sport = to_sci_port(port); 2674 2675 /* 2676 * Nothing to do if there's already an established membase. 2677 */ 2678 if (port->membase) 2679 return 0; 2680 2681 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { 2682 port->membase = ioremap_nocache(port->mapbase, sport->reg_size); 2683 if (unlikely(!port->membase)) { 2684 dev_err(port->dev, "can't remap port#%d\n", port->line); 2685 return -ENXIO; 2686 } 2687 } else { 2688 /* 2689 * For the simple (and majority of) cases where we don't 2690 * need to do any remapping, just cast the cookie 2691 * directly. 2692 */ 2693 port->membase = (void __iomem *)(uintptr_t)port->mapbase; 2694 } 2695 2696 return 0; 2697 } 2698 2699 static void sci_release_port(struct uart_port *port) 2700 { 2701 struct sci_port *sport = to_sci_port(port); 2702 2703 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { 2704 iounmap(port->membase); 2705 port->membase = NULL; 2706 } 2707 2708 release_mem_region(port->mapbase, sport->reg_size); 2709 } 2710 2711 static int sci_request_port(struct uart_port *port) 2712 { 2713 struct resource *res; 2714 struct sci_port *sport = to_sci_port(port); 2715 int ret; 2716 2717 res = request_mem_region(port->mapbase, sport->reg_size, 2718 dev_name(port->dev)); 2719 if (unlikely(res == NULL)) { 2720 dev_err(port->dev, "request_mem_region failed."); 2721 return -EBUSY; 2722 } 2723 2724 ret = sci_remap_port(port); 2725 if (unlikely(ret != 0)) { 2726 release_resource(res); 2727 return ret; 2728 } 2729 2730 return 0; 2731 } 2732 2733 static void sci_config_port(struct uart_port *port, int flags) 2734 { 2735 if (flags & UART_CONFIG_TYPE) { 2736 struct sci_port *sport = to_sci_port(port); 2737 2738 port->type = sport->cfg->type; 2739 sci_request_port(port); 2740 } 2741 } 2742 2743 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser) 2744 { 2745 if (ser->baud_base < 2400) 2746 /* No paper tape reader for Mitch.. */ 2747 return -EINVAL; 2748 2749 return 0; 2750 } 2751 2752 static const struct uart_ops sci_uart_ops = { 2753 .tx_empty = sci_tx_empty, 2754 .set_mctrl = sci_set_mctrl, 2755 .get_mctrl = sci_get_mctrl, 2756 .start_tx = sci_start_tx, 2757 .stop_tx = sci_stop_tx, 2758 .stop_rx = sci_stop_rx, 2759 .enable_ms = sci_enable_ms, 2760 .break_ctl = sci_break_ctl, 2761 .startup = sci_startup, 2762 .shutdown = sci_shutdown, 2763 .flush_buffer = sci_flush_buffer, 2764 .set_termios = sci_set_termios, 2765 .pm = sci_pm, 2766 .type = sci_type, 2767 .release_port = sci_release_port, 2768 .request_port = sci_request_port, 2769 .config_port = sci_config_port, 2770 .verify_port = sci_verify_port, 2771 #ifdef CONFIG_CONSOLE_POLL 2772 .poll_get_char = sci_poll_get_char, 2773 .poll_put_char = sci_poll_put_char, 2774 #endif 2775 }; 2776 2777 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev) 2778 { 2779 const char *clk_names[] = { 2780 [SCI_FCK] = "fck", 2781 [SCI_SCK] = "sck", 2782 [SCI_BRG_INT] = "brg_int", 2783 [SCI_SCIF_CLK] = "scif_clk", 2784 }; 2785 struct clk *clk; 2786 unsigned int i; 2787 2788 if (sci_port->cfg->type == PORT_HSCIF) 2789 clk_names[SCI_SCK] = "hsck"; 2790 2791 for (i = 0; i < SCI_NUM_CLKS; i++) { 2792 clk = devm_clk_get(dev, clk_names[i]); 2793 if (PTR_ERR(clk) == -EPROBE_DEFER) 2794 return -EPROBE_DEFER; 2795 2796 if (IS_ERR(clk) && i == SCI_FCK) { 2797 /* 2798 * "fck" used to be called "sci_ick", and we need to 2799 * maintain DT backward compatibility. 2800 */ 2801 clk = devm_clk_get(dev, "sci_ick"); 2802 if (PTR_ERR(clk) == -EPROBE_DEFER) 2803 return -EPROBE_DEFER; 2804 2805 if (!IS_ERR(clk)) 2806 goto found; 2807 2808 /* 2809 * Not all SH platforms declare a clock lookup entry 2810 * for SCI devices, in which case we need to get the 2811 * global "peripheral_clk" clock. 2812 */ 2813 clk = devm_clk_get(dev, "peripheral_clk"); 2814 if (!IS_ERR(clk)) 2815 goto found; 2816 2817 dev_err(dev, "failed to get %s (%ld)\n", clk_names[i], 2818 PTR_ERR(clk)); 2819 return PTR_ERR(clk); 2820 } 2821 2822 found: 2823 if (IS_ERR(clk)) 2824 dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i], 2825 PTR_ERR(clk)); 2826 else 2827 dev_dbg(dev, "clk %s is %pC rate %lu\n", clk_names[i], 2828 clk, clk_get_rate(clk)); 2829 sci_port->clks[i] = IS_ERR(clk) ? NULL : clk; 2830 } 2831 return 0; 2832 } 2833 2834 static const struct sci_port_params * 2835 sci_probe_regmap(const struct plat_sci_port *cfg) 2836 { 2837 unsigned int regtype; 2838 2839 if (cfg->regtype != SCIx_PROBE_REGTYPE) 2840 return &sci_port_params[cfg->regtype]; 2841 2842 switch (cfg->type) { 2843 case PORT_SCI: 2844 regtype = SCIx_SCI_REGTYPE; 2845 break; 2846 case PORT_IRDA: 2847 regtype = SCIx_IRDA_REGTYPE; 2848 break; 2849 case PORT_SCIFA: 2850 regtype = SCIx_SCIFA_REGTYPE; 2851 break; 2852 case PORT_SCIFB: 2853 regtype = SCIx_SCIFB_REGTYPE; 2854 break; 2855 case PORT_SCIF: 2856 /* 2857 * The SH-4 is a bit of a misnomer here, although that's 2858 * where this particular port layout originated. This 2859 * configuration (or some slight variation thereof) 2860 * remains the dominant model for all SCIFs. 2861 */ 2862 regtype = SCIx_SH4_SCIF_REGTYPE; 2863 break; 2864 case PORT_HSCIF: 2865 regtype = SCIx_HSCIF_REGTYPE; 2866 break; 2867 default: 2868 pr_err("Can't probe register map for given port\n"); 2869 return NULL; 2870 } 2871 2872 return &sci_port_params[regtype]; 2873 } 2874 2875 static int sci_init_single(struct platform_device *dev, 2876 struct sci_port *sci_port, unsigned int index, 2877 const struct plat_sci_port *p, bool early) 2878 { 2879 struct uart_port *port = &sci_port->port; 2880 const struct resource *res; 2881 unsigned int i; 2882 int ret; 2883 2884 sci_port->cfg = p; 2885 2886 port->ops = &sci_uart_ops; 2887 port->iotype = UPIO_MEM; 2888 port->line = index; 2889 2890 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 2891 if (res == NULL) 2892 return -ENOMEM; 2893 2894 port->mapbase = res->start; 2895 sci_port->reg_size = resource_size(res); 2896 2897 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) { 2898 if (i) 2899 sci_port->irqs[i] = platform_get_irq_optional(dev, i); 2900 else 2901 sci_port->irqs[i] = platform_get_irq(dev, i); 2902 } 2903 2904 /* The SCI generates several interrupts. They can be muxed together or 2905 * connected to different interrupt lines. In the muxed case only one 2906 * interrupt resource is specified as there is only one interrupt ID. 2907 * In the non-muxed case, up to 6 interrupt signals might be generated 2908 * from the SCI, however those signals might have their own individual 2909 * interrupt ID numbers, or muxed together with another interrupt. 2910 */ 2911 if (sci_port->irqs[0] < 0) 2912 return -ENXIO; 2913 2914 if (sci_port->irqs[1] < 0) 2915 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++) 2916 sci_port->irqs[i] = sci_port->irqs[0]; 2917 2918 sci_port->params = sci_probe_regmap(p); 2919 if (unlikely(sci_port->params == NULL)) 2920 return -EINVAL; 2921 2922 switch (p->type) { 2923 case PORT_SCIFB: 2924 sci_port->rx_trigger = 48; 2925 break; 2926 case PORT_HSCIF: 2927 sci_port->rx_trigger = 64; 2928 break; 2929 case PORT_SCIFA: 2930 sci_port->rx_trigger = 32; 2931 break; 2932 case PORT_SCIF: 2933 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) 2934 /* RX triggering not implemented for this IP */ 2935 sci_port->rx_trigger = 1; 2936 else 2937 sci_port->rx_trigger = 8; 2938 break; 2939 default: 2940 sci_port->rx_trigger = 1; 2941 break; 2942 } 2943 2944 sci_port->rx_fifo_timeout = 0; 2945 sci_port->hscif_tot = 0; 2946 2947 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't 2948 * match the SoC datasheet, this should be investigated. Let platform 2949 * data override the sampling rate for now. 2950 */ 2951 sci_port->sampling_rate_mask = p->sampling_rate 2952 ? SCI_SR(p->sampling_rate) 2953 : sci_port->params->sampling_rate_mask; 2954 2955 if (!early) { 2956 ret = sci_init_clocks(sci_port, &dev->dev); 2957 if (ret < 0) 2958 return ret; 2959 2960 port->dev = &dev->dev; 2961 2962 pm_runtime_enable(&dev->dev); 2963 } 2964 2965 port->type = p->type; 2966 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags; 2967 port->fifosize = sci_port->params->fifosize; 2968 2969 if (port->type == PORT_SCI) { 2970 if (sci_port->reg_size >= 0x20) 2971 port->regshift = 2; 2972 else 2973 port->regshift = 1; 2974 } 2975 2976 /* 2977 * The UART port needs an IRQ value, so we peg this to the RX IRQ 2978 * for the multi-IRQ ports, which is where we are primarily 2979 * concerned with the shutdown path synchronization. 2980 * 2981 * For the muxed case there's nothing more to do. 2982 */ 2983 port->irq = sci_port->irqs[SCIx_RXI_IRQ]; 2984 port->irqflags = 0; 2985 2986 port->serial_in = sci_serial_in; 2987 port->serial_out = sci_serial_out; 2988 2989 return 0; 2990 } 2991 2992 static void sci_cleanup_single(struct sci_port *port) 2993 { 2994 pm_runtime_disable(port->port.dev); 2995 } 2996 2997 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ 2998 defined(CONFIG_SERIAL_SH_SCI_EARLYCON) 2999 static void serial_console_putchar(struct uart_port *port, int ch) 3000 { 3001 sci_poll_put_char(port, ch); 3002 } 3003 3004 /* 3005 * Print a string to the serial port trying not to disturb 3006 * any possible real use of the port... 3007 */ 3008 static void serial_console_write(struct console *co, const char *s, 3009 unsigned count) 3010 { 3011 struct sci_port *sci_port = &sci_ports[co->index]; 3012 struct uart_port *port = &sci_port->port; 3013 unsigned short bits, ctrl, ctrl_temp; 3014 unsigned long flags; 3015 int locked = 1; 3016 3017 #if defined(SUPPORT_SYSRQ) 3018 if (port->sysrq) 3019 locked = 0; 3020 else 3021 #endif 3022 if (oops_in_progress) 3023 locked = spin_trylock_irqsave(&port->lock, flags); 3024 else 3025 spin_lock_irqsave(&port->lock, flags); 3026 3027 /* first save SCSCR then disable interrupts, keep clock source */ 3028 ctrl = serial_port_in(port, SCSCR); 3029 ctrl_temp = SCSCR_RE | SCSCR_TE | 3030 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) | 3031 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0)); 3032 serial_port_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot); 3033 3034 uart_console_write(port, s, count, serial_console_putchar); 3035 3036 /* wait until fifo is empty and last bit has been transmitted */ 3037 bits = SCxSR_TDxE(port) | SCxSR_TEND(port); 3038 while ((serial_port_in(port, SCxSR) & bits) != bits) 3039 cpu_relax(); 3040 3041 /* restore the SCSCR */ 3042 serial_port_out(port, SCSCR, ctrl); 3043 3044 if (locked) 3045 spin_unlock_irqrestore(&port->lock, flags); 3046 } 3047 3048 static int serial_console_setup(struct console *co, char *options) 3049 { 3050 struct sci_port *sci_port; 3051 struct uart_port *port; 3052 int baud = 115200; 3053 int bits = 8; 3054 int parity = 'n'; 3055 int flow = 'n'; 3056 int ret; 3057 3058 /* 3059 * Refuse to handle any bogus ports. 3060 */ 3061 if (co->index < 0 || co->index >= SCI_NPORTS) 3062 return -ENODEV; 3063 3064 sci_port = &sci_ports[co->index]; 3065 port = &sci_port->port; 3066 3067 /* 3068 * Refuse to handle uninitialized ports. 3069 */ 3070 if (!port->ops) 3071 return -ENODEV; 3072 3073 ret = sci_remap_port(port); 3074 if (unlikely(ret != 0)) 3075 return ret; 3076 3077 if (options) 3078 uart_parse_options(options, &baud, &parity, &bits, &flow); 3079 3080 return uart_set_options(port, co, baud, parity, bits, flow); 3081 } 3082 3083 static struct console serial_console = { 3084 .name = "ttySC", 3085 .device = uart_console_device, 3086 .write = serial_console_write, 3087 .setup = serial_console_setup, 3088 .flags = CON_PRINTBUFFER, 3089 .index = -1, 3090 .data = &sci_uart_driver, 3091 }; 3092 3093 static struct console early_serial_console = { 3094 .name = "early_ttySC", 3095 .write = serial_console_write, 3096 .flags = CON_PRINTBUFFER, 3097 .index = -1, 3098 }; 3099 3100 static char early_serial_buf[32]; 3101 3102 static int sci_probe_earlyprintk(struct platform_device *pdev) 3103 { 3104 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev); 3105 3106 if (early_serial_console.data) 3107 return -EEXIST; 3108 3109 early_serial_console.index = pdev->id; 3110 3111 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true); 3112 3113 serial_console_setup(&early_serial_console, early_serial_buf); 3114 3115 if (!strstr(early_serial_buf, "keep")) 3116 early_serial_console.flags |= CON_BOOT; 3117 3118 register_console(&early_serial_console); 3119 return 0; 3120 } 3121 3122 #define SCI_CONSOLE (&serial_console) 3123 3124 #else 3125 static inline int sci_probe_earlyprintk(struct platform_device *pdev) 3126 { 3127 return -EINVAL; 3128 } 3129 3130 #define SCI_CONSOLE NULL 3131 3132 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */ 3133 3134 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized"; 3135 3136 static DEFINE_MUTEX(sci_uart_registration_lock); 3137 static struct uart_driver sci_uart_driver = { 3138 .owner = THIS_MODULE, 3139 .driver_name = "sci", 3140 .dev_name = "ttySC", 3141 .major = SCI_MAJOR, 3142 .minor = SCI_MINOR_START, 3143 .nr = SCI_NPORTS, 3144 .cons = SCI_CONSOLE, 3145 }; 3146 3147 static int sci_remove(struct platform_device *dev) 3148 { 3149 struct sci_port *port = platform_get_drvdata(dev); 3150 unsigned int type = port->port.type; /* uart_remove_... clears it */ 3151 3152 sci_ports_in_use &= ~BIT(port->port.line); 3153 uart_remove_one_port(&sci_uart_driver, &port->port); 3154 3155 sci_cleanup_single(port); 3156 3157 if (port->port.fifosize > 1) 3158 device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger); 3159 if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF) 3160 device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout); 3161 3162 return 0; 3163 } 3164 3165 3166 #define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype)) 3167 #define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16) 3168 #define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff) 3169 3170 static const struct of_device_id of_sci_match[] = { 3171 /* SoC-specific types */ 3172 { 3173 .compatible = "renesas,scif-r7s72100", 3174 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE), 3175 }, 3176 { 3177 .compatible = "renesas,scif-r7s9210", 3178 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE), 3179 }, 3180 /* Family-specific types */ 3181 { 3182 .compatible = "renesas,rcar-gen1-scif", 3183 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3184 }, { 3185 .compatible = "renesas,rcar-gen2-scif", 3186 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3187 }, { 3188 .compatible = "renesas,rcar-gen3-scif", 3189 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3190 }, 3191 /* Generic types */ 3192 { 3193 .compatible = "renesas,scif", 3194 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE), 3195 }, { 3196 .compatible = "renesas,scifa", 3197 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE), 3198 }, { 3199 .compatible = "renesas,scifb", 3200 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE), 3201 }, { 3202 .compatible = "renesas,hscif", 3203 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE), 3204 }, { 3205 .compatible = "renesas,sci", 3206 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE), 3207 }, { 3208 /* Terminator */ 3209 }, 3210 }; 3211 MODULE_DEVICE_TABLE(of, of_sci_match); 3212 3213 static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev, 3214 unsigned int *dev_id) 3215 { 3216 struct device_node *np = pdev->dev.of_node; 3217 struct plat_sci_port *p; 3218 struct sci_port *sp; 3219 const void *data; 3220 int id; 3221 3222 if (!IS_ENABLED(CONFIG_OF) || !np) 3223 return NULL; 3224 3225 data = of_device_get_match_data(&pdev->dev); 3226 3227 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL); 3228 if (!p) 3229 return NULL; 3230 3231 /* Get the line number from the aliases node. */ 3232 id = of_alias_get_id(np, "serial"); 3233 if (id < 0 && ~sci_ports_in_use) 3234 id = ffz(sci_ports_in_use); 3235 if (id < 0) { 3236 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id); 3237 return NULL; 3238 } 3239 if (id >= ARRAY_SIZE(sci_ports)) { 3240 dev_err(&pdev->dev, "serial%d out of range\n", id); 3241 return NULL; 3242 } 3243 3244 sp = &sci_ports[id]; 3245 *dev_id = id; 3246 3247 p->type = SCI_OF_TYPE(data); 3248 p->regtype = SCI_OF_REGTYPE(data); 3249 3250 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts"); 3251 3252 return p; 3253 } 3254 3255 static int sci_probe_single(struct platform_device *dev, 3256 unsigned int index, 3257 struct plat_sci_port *p, 3258 struct sci_port *sciport) 3259 { 3260 int ret; 3261 3262 /* Sanity check */ 3263 if (unlikely(index >= SCI_NPORTS)) { 3264 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n", 3265 index+1, SCI_NPORTS); 3266 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n"); 3267 return -EINVAL; 3268 } 3269 BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8); 3270 if (sci_ports_in_use & BIT(index)) 3271 return -EBUSY; 3272 3273 mutex_lock(&sci_uart_registration_lock); 3274 if (!sci_uart_driver.state) { 3275 ret = uart_register_driver(&sci_uart_driver); 3276 if (ret) { 3277 mutex_unlock(&sci_uart_registration_lock); 3278 return ret; 3279 } 3280 } 3281 mutex_unlock(&sci_uart_registration_lock); 3282 3283 ret = sci_init_single(dev, sciport, index, p, false); 3284 if (ret) 3285 return ret; 3286 3287 sciport->gpios = mctrl_gpio_init(&sciport->port, 0); 3288 if (IS_ERR(sciport->gpios)) 3289 return PTR_ERR(sciport->gpios); 3290 3291 if (sciport->has_rtscts) { 3292 if (mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_CTS) || 3293 mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_RTS)) { 3294 dev_err(&dev->dev, "Conflicting RTS/CTS config\n"); 3295 return -EINVAL; 3296 } 3297 sciport->port.flags |= UPF_HARD_FLOW; 3298 } 3299 3300 ret = uart_add_one_port(&sci_uart_driver, &sciport->port); 3301 if (ret) { 3302 sci_cleanup_single(sciport); 3303 return ret; 3304 } 3305 3306 return 0; 3307 } 3308 3309 static int sci_probe(struct platform_device *dev) 3310 { 3311 struct plat_sci_port *p; 3312 struct sci_port *sp; 3313 unsigned int dev_id; 3314 int ret; 3315 3316 /* 3317 * If we've come here via earlyprintk initialization, head off to 3318 * the special early probe. We don't have sufficient device state 3319 * to make it beyond this yet. 3320 */ 3321 if (is_early_platform_device(dev)) 3322 return sci_probe_earlyprintk(dev); 3323 3324 if (dev->dev.of_node) { 3325 p = sci_parse_dt(dev, &dev_id); 3326 if (p == NULL) 3327 return -EINVAL; 3328 } else { 3329 p = dev->dev.platform_data; 3330 if (p == NULL) { 3331 dev_err(&dev->dev, "no platform data supplied\n"); 3332 return -EINVAL; 3333 } 3334 3335 dev_id = dev->id; 3336 } 3337 3338 sp = &sci_ports[dev_id]; 3339 platform_set_drvdata(dev, sp); 3340 3341 ret = sci_probe_single(dev, dev_id, p, sp); 3342 if (ret) 3343 return ret; 3344 3345 if (sp->port.fifosize > 1) { 3346 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_trigger); 3347 if (ret) 3348 return ret; 3349 } 3350 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB || 3351 sp->port.type == PORT_HSCIF) { 3352 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout); 3353 if (ret) { 3354 if (sp->port.fifosize > 1) { 3355 device_remove_file(&dev->dev, 3356 &dev_attr_rx_fifo_trigger); 3357 } 3358 return ret; 3359 } 3360 } 3361 3362 #ifdef CONFIG_SH_STANDARD_BIOS 3363 sh_bios_gdb_detach(); 3364 #endif 3365 3366 sci_ports_in_use |= BIT(dev_id); 3367 return 0; 3368 } 3369 3370 static __maybe_unused int sci_suspend(struct device *dev) 3371 { 3372 struct sci_port *sport = dev_get_drvdata(dev); 3373 3374 if (sport) 3375 uart_suspend_port(&sci_uart_driver, &sport->port); 3376 3377 return 0; 3378 } 3379 3380 static __maybe_unused int sci_resume(struct device *dev) 3381 { 3382 struct sci_port *sport = dev_get_drvdata(dev); 3383 3384 if (sport) 3385 uart_resume_port(&sci_uart_driver, &sport->port); 3386 3387 return 0; 3388 } 3389 3390 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume); 3391 3392 static struct platform_driver sci_driver = { 3393 .probe = sci_probe, 3394 .remove = sci_remove, 3395 .driver = { 3396 .name = "sh-sci", 3397 .pm = &sci_dev_pm_ops, 3398 .of_match_table = of_match_ptr(of_sci_match), 3399 }, 3400 }; 3401 3402 static int __init sci_init(void) 3403 { 3404 pr_info("%s\n", banner); 3405 3406 return platform_driver_register(&sci_driver); 3407 } 3408 3409 static void __exit sci_exit(void) 3410 { 3411 platform_driver_unregister(&sci_driver); 3412 3413 if (sci_uart_driver.state) 3414 uart_unregister_driver(&sci_uart_driver); 3415 } 3416 3417 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE 3418 early_platform_init_buffer("earlyprintk", &sci_driver, 3419 early_serial_buf, ARRAY_SIZE(early_serial_buf)); 3420 #endif 3421 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON 3422 static struct plat_sci_port port_cfg __initdata; 3423 3424 static int __init early_console_setup(struct earlycon_device *device, 3425 int type) 3426 { 3427 if (!device->port.membase) 3428 return -ENODEV; 3429 3430 device->port.serial_in = sci_serial_in; 3431 device->port.serial_out = sci_serial_out; 3432 device->port.type = type; 3433 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port)); 3434 port_cfg.type = type; 3435 sci_ports[0].cfg = &port_cfg; 3436 sci_ports[0].params = sci_probe_regmap(&port_cfg); 3437 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR); 3438 sci_serial_out(&sci_ports[0].port, SCSCR, 3439 SCSCR_RE | SCSCR_TE | port_cfg.scscr); 3440 3441 device->con->write = serial_console_write; 3442 return 0; 3443 } 3444 static int __init sci_early_console_setup(struct earlycon_device *device, 3445 const char *opt) 3446 { 3447 return early_console_setup(device, PORT_SCI); 3448 } 3449 static int __init scif_early_console_setup(struct earlycon_device *device, 3450 const char *opt) 3451 { 3452 return early_console_setup(device, PORT_SCIF); 3453 } 3454 static int __init rzscifa_early_console_setup(struct earlycon_device *device, 3455 const char *opt) 3456 { 3457 port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE; 3458 return early_console_setup(device, PORT_SCIF); 3459 } 3460 static int __init scifa_early_console_setup(struct earlycon_device *device, 3461 const char *opt) 3462 { 3463 return early_console_setup(device, PORT_SCIFA); 3464 } 3465 static int __init scifb_early_console_setup(struct earlycon_device *device, 3466 const char *opt) 3467 { 3468 return early_console_setup(device, PORT_SCIFB); 3469 } 3470 static int __init hscif_early_console_setup(struct earlycon_device *device, 3471 const char *opt) 3472 { 3473 return early_console_setup(device, PORT_HSCIF); 3474 } 3475 3476 OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup); 3477 OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup); 3478 OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup); 3479 OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup); 3480 OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup); 3481 OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup); 3482 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */ 3483 3484 module_init(sci_init); 3485 module_exit(sci_exit); 3486 3487 MODULE_LICENSE("GPL"); 3488 MODULE_ALIAS("platform:sh-sci"); 3489 MODULE_AUTHOR("Paul Mundt"); 3490 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver"); 3491