xref: /openbmc/linux/drivers/tty/serial/sh-sci.c (revision da2ef666)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * SuperH on-chip serial module support.  (SCI with no FIFO / with FIFO)
4  *
5  *  Copyright (C) 2002 - 2011  Paul Mundt
6  *  Copyright (C) 2015 Glider bvba
7  *  Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
8  *
9  * based off of the old drivers/char/sh-sci.c by:
10  *
11  *   Copyright (C) 1999, 2000  Niibe Yutaka
12  *   Copyright (C) 2000  Sugioka Toshinobu
13  *   Modified to support multiple serial ports. Stuart Menefy (May 2000).
14  *   Modified to support SecureEdge. David McCullough (2002)
15  *   Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
16  *   Removed SH7300 support (Jul 2007).
17  */
18 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
19 #define SUPPORT_SYSRQ
20 #endif
21 
22 #undef DEBUG
23 
24 #include <linux/clk.h>
25 #include <linux/console.h>
26 #include <linux/ctype.h>
27 #include <linux/cpufreq.h>
28 #include <linux/delay.h>
29 #include <linux/dmaengine.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/err.h>
32 #include <linux/errno.h>
33 #include <linux/init.h>
34 #include <linux/interrupt.h>
35 #include <linux/ioport.h>
36 #include <linux/ktime.h>
37 #include <linux/major.h>
38 #include <linux/module.h>
39 #include <linux/mm.h>
40 #include <linux/of.h>
41 #include <linux/of_device.h>
42 #include <linux/platform_device.h>
43 #include <linux/pm_runtime.h>
44 #include <linux/scatterlist.h>
45 #include <linux/serial.h>
46 #include <linux/serial_sci.h>
47 #include <linux/sh_dma.h>
48 #include <linux/slab.h>
49 #include <linux/string.h>
50 #include <linux/sysrq.h>
51 #include <linux/timer.h>
52 #include <linux/tty.h>
53 #include <linux/tty_flip.h>
54 
55 #ifdef CONFIG_SUPERH
56 #include <asm/sh_bios.h>
57 #endif
58 
59 #include "serial_mctrl_gpio.h"
60 #include "sh-sci.h"
61 
62 /* Offsets into the sci_port->irqs array */
63 enum {
64 	SCIx_ERI_IRQ,
65 	SCIx_RXI_IRQ,
66 	SCIx_TXI_IRQ,
67 	SCIx_BRI_IRQ,
68 	SCIx_DRI_IRQ,
69 	SCIx_TEI_IRQ,
70 	SCIx_NR_IRQS,
71 
72 	SCIx_MUX_IRQ = SCIx_NR_IRQS,	/* special case */
73 };
74 
75 #define SCIx_IRQ_IS_MUXED(port)			\
76 	((port)->irqs[SCIx_ERI_IRQ] ==	\
77 	 (port)->irqs[SCIx_RXI_IRQ]) ||	\
78 	((port)->irqs[SCIx_ERI_IRQ] &&	\
79 	 ((port)->irqs[SCIx_RXI_IRQ] < 0))
80 
81 enum SCI_CLKS {
82 	SCI_FCK,		/* Functional Clock */
83 	SCI_SCK,		/* Optional External Clock */
84 	SCI_BRG_INT,		/* Optional BRG Internal Clock Source */
85 	SCI_SCIF_CLK,		/* Optional BRG External Clock Source */
86 	SCI_NUM_CLKS
87 };
88 
89 /* Bit x set means sampling rate x + 1 is supported */
90 #define SCI_SR(x)		BIT((x) - 1)
91 #define SCI_SR_RANGE(x, y)	GENMASK((y) - 1, (x) - 1)
92 
93 #define SCI_SR_SCIFAB		SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
94 				SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
95 				SCI_SR(19) | SCI_SR(27)
96 
97 #define min_sr(_port)		ffs((_port)->sampling_rate_mask)
98 #define max_sr(_port)		fls((_port)->sampling_rate_mask)
99 
100 /* Iterate over all supported sampling rates, from high to low */
101 #define for_each_sr(_sr, _port)						\
102 	for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--)	\
103 		if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
104 
105 struct plat_sci_reg {
106 	u8 offset, size;
107 };
108 
109 struct sci_port_params {
110 	const struct plat_sci_reg regs[SCIx_NR_REGS];
111 	unsigned int fifosize;
112 	unsigned int overrun_reg;
113 	unsigned int overrun_mask;
114 	unsigned int sampling_rate_mask;
115 	unsigned int error_mask;
116 	unsigned int error_clear;
117 };
118 
119 struct sci_port {
120 	struct uart_port	port;
121 
122 	/* Platform configuration */
123 	const struct sci_port_params *params;
124 	const struct plat_sci_port *cfg;
125 	unsigned int		sampling_rate_mask;
126 	resource_size_t		reg_size;
127 	struct mctrl_gpios	*gpios;
128 
129 	/* Clocks */
130 	struct clk		*clks[SCI_NUM_CLKS];
131 	unsigned long		clk_rates[SCI_NUM_CLKS];
132 
133 	int			irqs[SCIx_NR_IRQS];
134 	char			*irqstr[SCIx_NR_IRQS];
135 
136 	struct dma_chan			*chan_tx;
137 	struct dma_chan			*chan_rx;
138 
139 #ifdef CONFIG_SERIAL_SH_SCI_DMA
140 	struct dma_chan			*chan_tx_saved;
141 	struct dma_chan			*chan_rx_saved;
142 	dma_cookie_t			cookie_tx;
143 	dma_cookie_t			cookie_rx[2];
144 	dma_cookie_t			active_rx;
145 	dma_addr_t			tx_dma_addr;
146 	unsigned int			tx_dma_len;
147 	struct scatterlist		sg_rx[2];
148 	void				*rx_buf[2];
149 	size_t				buf_len_rx;
150 	struct work_struct		work_tx;
151 	struct hrtimer			rx_timer;
152 	unsigned int			rx_timeout;	/* microseconds */
153 #endif
154 	unsigned int			rx_frame;
155 	int				rx_trigger;
156 	struct timer_list		rx_fifo_timer;
157 	int				rx_fifo_timeout;
158 	u16				hscif_tot;
159 
160 	bool has_rtscts;
161 	bool autorts;
162 };
163 
164 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
165 
166 static struct sci_port sci_ports[SCI_NPORTS];
167 static unsigned long sci_ports_in_use;
168 static struct uart_driver sci_uart_driver;
169 
170 static inline struct sci_port *
171 to_sci_port(struct uart_port *uart)
172 {
173 	return container_of(uart, struct sci_port, port);
174 }
175 
176 static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
177 	/*
178 	 * Common SCI definitions, dependent on the port's regshift
179 	 * value.
180 	 */
181 	[SCIx_SCI_REGTYPE] = {
182 		.regs = {
183 			[SCSMR]		= { 0x00,  8 },
184 			[SCBRR]		= { 0x01,  8 },
185 			[SCSCR]		= { 0x02,  8 },
186 			[SCxTDR]	= { 0x03,  8 },
187 			[SCxSR]		= { 0x04,  8 },
188 			[SCxRDR]	= { 0x05,  8 },
189 		},
190 		.fifosize = 1,
191 		.overrun_reg = SCxSR,
192 		.overrun_mask = SCI_ORER,
193 		.sampling_rate_mask = SCI_SR(32),
194 		.error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
195 		.error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
196 	},
197 
198 	/*
199 	 * Common definitions for legacy IrDA ports.
200 	 */
201 	[SCIx_IRDA_REGTYPE] = {
202 		.regs = {
203 			[SCSMR]		= { 0x00,  8 },
204 			[SCBRR]		= { 0x02,  8 },
205 			[SCSCR]		= { 0x04,  8 },
206 			[SCxTDR]	= { 0x06,  8 },
207 			[SCxSR]		= { 0x08, 16 },
208 			[SCxRDR]	= { 0x0a,  8 },
209 			[SCFCR]		= { 0x0c,  8 },
210 			[SCFDR]		= { 0x0e, 16 },
211 		},
212 		.fifosize = 1,
213 		.overrun_reg = SCxSR,
214 		.overrun_mask = SCI_ORER,
215 		.sampling_rate_mask = SCI_SR(32),
216 		.error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
217 		.error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
218 	},
219 
220 	/*
221 	 * Common SCIFA definitions.
222 	 */
223 	[SCIx_SCIFA_REGTYPE] = {
224 		.regs = {
225 			[SCSMR]		= { 0x00, 16 },
226 			[SCBRR]		= { 0x04,  8 },
227 			[SCSCR]		= { 0x08, 16 },
228 			[SCxTDR]	= { 0x20,  8 },
229 			[SCxSR]		= { 0x14, 16 },
230 			[SCxRDR]	= { 0x24,  8 },
231 			[SCFCR]		= { 0x18, 16 },
232 			[SCFDR]		= { 0x1c, 16 },
233 			[SCPCR]		= { 0x30, 16 },
234 			[SCPDR]		= { 0x34, 16 },
235 		},
236 		.fifosize = 64,
237 		.overrun_reg = SCxSR,
238 		.overrun_mask = SCIFA_ORER,
239 		.sampling_rate_mask = SCI_SR_SCIFAB,
240 		.error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
241 		.error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
242 	},
243 
244 	/*
245 	 * Common SCIFB definitions.
246 	 */
247 	[SCIx_SCIFB_REGTYPE] = {
248 		.regs = {
249 			[SCSMR]		= { 0x00, 16 },
250 			[SCBRR]		= { 0x04,  8 },
251 			[SCSCR]		= { 0x08, 16 },
252 			[SCxTDR]	= { 0x40,  8 },
253 			[SCxSR]		= { 0x14, 16 },
254 			[SCxRDR]	= { 0x60,  8 },
255 			[SCFCR]		= { 0x18, 16 },
256 			[SCTFDR]	= { 0x38, 16 },
257 			[SCRFDR]	= { 0x3c, 16 },
258 			[SCPCR]		= { 0x30, 16 },
259 			[SCPDR]		= { 0x34, 16 },
260 		},
261 		.fifosize = 256,
262 		.overrun_reg = SCxSR,
263 		.overrun_mask = SCIFA_ORER,
264 		.sampling_rate_mask = SCI_SR_SCIFAB,
265 		.error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
266 		.error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
267 	},
268 
269 	/*
270 	 * Common SH-2(A) SCIF definitions for ports with FIFO data
271 	 * count registers.
272 	 */
273 	[SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
274 		.regs = {
275 			[SCSMR]		= { 0x00, 16 },
276 			[SCBRR]		= { 0x04,  8 },
277 			[SCSCR]		= { 0x08, 16 },
278 			[SCxTDR]	= { 0x0c,  8 },
279 			[SCxSR]		= { 0x10, 16 },
280 			[SCxRDR]	= { 0x14,  8 },
281 			[SCFCR]		= { 0x18, 16 },
282 			[SCFDR]		= { 0x1c, 16 },
283 			[SCSPTR]	= { 0x20, 16 },
284 			[SCLSR]		= { 0x24, 16 },
285 		},
286 		.fifosize = 16,
287 		.overrun_reg = SCLSR,
288 		.overrun_mask = SCLSR_ORER,
289 		.sampling_rate_mask = SCI_SR(32),
290 		.error_mask = SCIF_DEFAULT_ERROR_MASK,
291 		.error_clear = SCIF_ERROR_CLEAR,
292 	},
293 
294 	/*
295 	 * Common SH-3 SCIF definitions.
296 	 */
297 	[SCIx_SH3_SCIF_REGTYPE] = {
298 		.regs = {
299 			[SCSMR]		= { 0x00,  8 },
300 			[SCBRR]		= { 0x02,  8 },
301 			[SCSCR]		= { 0x04,  8 },
302 			[SCxTDR]	= { 0x06,  8 },
303 			[SCxSR]		= { 0x08, 16 },
304 			[SCxRDR]	= { 0x0a,  8 },
305 			[SCFCR]		= { 0x0c,  8 },
306 			[SCFDR]		= { 0x0e, 16 },
307 		},
308 		.fifosize = 16,
309 		.overrun_reg = SCLSR,
310 		.overrun_mask = SCLSR_ORER,
311 		.sampling_rate_mask = SCI_SR(32),
312 		.error_mask = SCIF_DEFAULT_ERROR_MASK,
313 		.error_clear = SCIF_ERROR_CLEAR,
314 	},
315 
316 	/*
317 	 * Common SH-4(A) SCIF(B) definitions.
318 	 */
319 	[SCIx_SH4_SCIF_REGTYPE] = {
320 		.regs = {
321 			[SCSMR]		= { 0x00, 16 },
322 			[SCBRR]		= { 0x02,  8 },
323 			[SCSCR]		= { 0x04, 16 },
324 			[SCxTDR]	= { 0x06,  8 },
325 			[SCxSR]		= { 0x08, 16 },
326 			[SCxRDR]	= { 0x0a,  8 },
327 			[SCFCR]		= { 0x0c, 16 },
328 			[SCFDR]		= { 0x0e, 16 },
329 			[SCSPTR]	= { 0x10, 16 },
330 			[SCLSR]		= { 0x12, 16 },
331 		},
332 		.fifosize = 16,
333 		.overrun_reg = SCLSR,
334 		.overrun_mask = SCLSR_ORER,
335 		.sampling_rate_mask = SCI_SR(32),
336 		.error_mask = SCIF_DEFAULT_ERROR_MASK,
337 		.error_clear = SCIF_ERROR_CLEAR,
338 	},
339 
340 	/*
341 	 * Common SCIF definitions for ports with a Baud Rate Generator for
342 	 * External Clock (BRG).
343 	 */
344 	[SCIx_SH4_SCIF_BRG_REGTYPE] = {
345 		.regs = {
346 			[SCSMR]		= { 0x00, 16 },
347 			[SCBRR]		= { 0x04,  8 },
348 			[SCSCR]		= { 0x08, 16 },
349 			[SCxTDR]	= { 0x0c,  8 },
350 			[SCxSR]		= { 0x10, 16 },
351 			[SCxRDR]	= { 0x14,  8 },
352 			[SCFCR]		= { 0x18, 16 },
353 			[SCFDR]		= { 0x1c, 16 },
354 			[SCSPTR]	= { 0x20, 16 },
355 			[SCLSR]		= { 0x24, 16 },
356 			[SCDL]		= { 0x30, 16 },
357 			[SCCKS]		= { 0x34, 16 },
358 		},
359 		.fifosize = 16,
360 		.overrun_reg = SCLSR,
361 		.overrun_mask = SCLSR_ORER,
362 		.sampling_rate_mask = SCI_SR(32),
363 		.error_mask = SCIF_DEFAULT_ERROR_MASK,
364 		.error_clear = SCIF_ERROR_CLEAR,
365 	},
366 
367 	/*
368 	 * Common HSCIF definitions.
369 	 */
370 	[SCIx_HSCIF_REGTYPE] = {
371 		.regs = {
372 			[SCSMR]		= { 0x00, 16 },
373 			[SCBRR]		= { 0x04,  8 },
374 			[SCSCR]		= { 0x08, 16 },
375 			[SCxTDR]	= { 0x0c,  8 },
376 			[SCxSR]		= { 0x10, 16 },
377 			[SCxRDR]	= { 0x14,  8 },
378 			[SCFCR]		= { 0x18, 16 },
379 			[SCFDR]		= { 0x1c, 16 },
380 			[SCSPTR]	= { 0x20, 16 },
381 			[SCLSR]		= { 0x24, 16 },
382 			[HSSRR]		= { 0x40, 16 },
383 			[SCDL]		= { 0x30, 16 },
384 			[SCCKS]		= { 0x34, 16 },
385 			[HSRTRGR]	= { 0x54, 16 },
386 			[HSTTRGR]	= { 0x58, 16 },
387 		},
388 		.fifosize = 128,
389 		.overrun_reg = SCLSR,
390 		.overrun_mask = SCLSR_ORER,
391 		.sampling_rate_mask = SCI_SR_RANGE(8, 32),
392 		.error_mask = SCIF_DEFAULT_ERROR_MASK,
393 		.error_clear = SCIF_ERROR_CLEAR,
394 	},
395 
396 	/*
397 	 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
398 	 * register.
399 	 */
400 	[SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
401 		.regs = {
402 			[SCSMR]		= { 0x00, 16 },
403 			[SCBRR]		= { 0x04,  8 },
404 			[SCSCR]		= { 0x08, 16 },
405 			[SCxTDR]	= { 0x0c,  8 },
406 			[SCxSR]		= { 0x10, 16 },
407 			[SCxRDR]	= { 0x14,  8 },
408 			[SCFCR]		= { 0x18, 16 },
409 			[SCFDR]		= { 0x1c, 16 },
410 			[SCLSR]		= { 0x24, 16 },
411 		},
412 		.fifosize = 16,
413 		.overrun_reg = SCLSR,
414 		.overrun_mask = SCLSR_ORER,
415 		.sampling_rate_mask = SCI_SR(32),
416 		.error_mask = SCIF_DEFAULT_ERROR_MASK,
417 		.error_clear = SCIF_ERROR_CLEAR,
418 	},
419 
420 	/*
421 	 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
422 	 * count registers.
423 	 */
424 	[SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
425 		.regs = {
426 			[SCSMR]		= { 0x00, 16 },
427 			[SCBRR]		= { 0x04,  8 },
428 			[SCSCR]		= { 0x08, 16 },
429 			[SCxTDR]	= { 0x0c,  8 },
430 			[SCxSR]		= { 0x10, 16 },
431 			[SCxRDR]	= { 0x14,  8 },
432 			[SCFCR]		= { 0x18, 16 },
433 			[SCFDR]		= { 0x1c, 16 },
434 			[SCTFDR]	= { 0x1c, 16 },	/* aliased to SCFDR */
435 			[SCRFDR]	= { 0x20, 16 },
436 			[SCSPTR]	= { 0x24, 16 },
437 			[SCLSR]		= { 0x28, 16 },
438 		},
439 		.fifosize = 16,
440 		.overrun_reg = SCLSR,
441 		.overrun_mask = SCLSR_ORER,
442 		.sampling_rate_mask = SCI_SR(32),
443 		.error_mask = SCIF_DEFAULT_ERROR_MASK,
444 		.error_clear = SCIF_ERROR_CLEAR,
445 	},
446 
447 	/*
448 	 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
449 	 * registers.
450 	 */
451 	[SCIx_SH7705_SCIF_REGTYPE] = {
452 		.regs = {
453 			[SCSMR]		= { 0x00, 16 },
454 			[SCBRR]		= { 0x04,  8 },
455 			[SCSCR]		= { 0x08, 16 },
456 			[SCxTDR]	= { 0x20,  8 },
457 			[SCxSR]		= { 0x14, 16 },
458 			[SCxRDR]	= { 0x24,  8 },
459 			[SCFCR]		= { 0x18, 16 },
460 			[SCFDR]		= { 0x1c, 16 },
461 		},
462 		.fifosize = 64,
463 		.overrun_reg = SCxSR,
464 		.overrun_mask = SCIFA_ORER,
465 		.sampling_rate_mask = SCI_SR(16),
466 		.error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
467 		.error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
468 	},
469 };
470 
471 #define sci_getreg(up, offset)		(&to_sci_port(up)->params->regs[offset])
472 
473 /*
474  * The "offset" here is rather misleading, in that it refers to an enum
475  * value relative to the port mapping rather than the fixed offset
476  * itself, which needs to be manually retrieved from the platform's
477  * register map for the given port.
478  */
479 static unsigned int sci_serial_in(struct uart_port *p, int offset)
480 {
481 	const struct plat_sci_reg *reg = sci_getreg(p, offset);
482 
483 	if (reg->size == 8)
484 		return ioread8(p->membase + (reg->offset << p->regshift));
485 	else if (reg->size == 16)
486 		return ioread16(p->membase + (reg->offset << p->regshift));
487 	else
488 		WARN(1, "Invalid register access\n");
489 
490 	return 0;
491 }
492 
493 static void sci_serial_out(struct uart_port *p, int offset, int value)
494 {
495 	const struct plat_sci_reg *reg = sci_getreg(p, offset);
496 
497 	if (reg->size == 8)
498 		iowrite8(value, p->membase + (reg->offset << p->regshift));
499 	else if (reg->size == 16)
500 		iowrite16(value, p->membase + (reg->offset << p->regshift));
501 	else
502 		WARN(1, "Invalid register access\n");
503 }
504 
505 static void sci_port_enable(struct sci_port *sci_port)
506 {
507 	unsigned int i;
508 
509 	if (!sci_port->port.dev)
510 		return;
511 
512 	pm_runtime_get_sync(sci_port->port.dev);
513 
514 	for (i = 0; i < SCI_NUM_CLKS; i++) {
515 		clk_prepare_enable(sci_port->clks[i]);
516 		sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
517 	}
518 	sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
519 }
520 
521 static void sci_port_disable(struct sci_port *sci_port)
522 {
523 	unsigned int i;
524 
525 	if (!sci_port->port.dev)
526 		return;
527 
528 	for (i = SCI_NUM_CLKS; i-- > 0; )
529 		clk_disable_unprepare(sci_port->clks[i]);
530 
531 	pm_runtime_put_sync(sci_port->port.dev);
532 }
533 
534 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
535 {
536 	/*
537 	 * Not all ports (such as SCIFA) will support REIE. Rather than
538 	 * special-casing the port type, we check the port initialization
539 	 * IRQ enable mask to see whether the IRQ is desired at all. If
540 	 * it's unset, it's logically inferred that there's no point in
541 	 * testing for it.
542 	 */
543 	return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
544 }
545 
546 static void sci_start_tx(struct uart_port *port)
547 {
548 	struct sci_port *s = to_sci_port(port);
549 	unsigned short ctrl;
550 
551 #ifdef CONFIG_SERIAL_SH_SCI_DMA
552 	if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
553 		u16 new, scr = serial_port_in(port, SCSCR);
554 		if (s->chan_tx)
555 			new = scr | SCSCR_TDRQE;
556 		else
557 			new = scr & ~SCSCR_TDRQE;
558 		if (new != scr)
559 			serial_port_out(port, SCSCR, new);
560 	}
561 
562 	if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
563 	    dma_submit_error(s->cookie_tx)) {
564 		s->cookie_tx = 0;
565 		schedule_work(&s->work_tx);
566 	}
567 #endif
568 
569 	if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
570 		/* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
571 		ctrl = serial_port_in(port, SCSCR);
572 		serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
573 	}
574 }
575 
576 static void sci_stop_tx(struct uart_port *port)
577 {
578 	unsigned short ctrl;
579 
580 	/* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
581 	ctrl = serial_port_in(port, SCSCR);
582 
583 	if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
584 		ctrl &= ~SCSCR_TDRQE;
585 
586 	ctrl &= ~SCSCR_TIE;
587 
588 	serial_port_out(port, SCSCR, ctrl);
589 }
590 
591 static void sci_start_rx(struct uart_port *port)
592 {
593 	unsigned short ctrl;
594 
595 	ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
596 
597 	if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
598 		ctrl &= ~SCSCR_RDRQE;
599 
600 	serial_port_out(port, SCSCR, ctrl);
601 }
602 
603 static void sci_stop_rx(struct uart_port *port)
604 {
605 	unsigned short ctrl;
606 
607 	ctrl = serial_port_in(port, SCSCR);
608 
609 	if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
610 		ctrl &= ~SCSCR_RDRQE;
611 
612 	ctrl &= ~port_rx_irq_mask(port);
613 
614 	serial_port_out(port, SCSCR, ctrl);
615 }
616 
617 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
618 {
619 	if (port->type == PORT_SCI) {
620 		/* Just store the mask */
621 		serial_port_out(port, SCxSR, mask);
622 	} else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) {
623 		/* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
624 		/* Only clear the status bits we want to clear */
625 		serial_port_out(port, SCxSR,
626 				serial_port_in(port, SCxSR) & mask);
627 	} else {
628 		/* Store the mask, clear parity/framing errors */
629 		serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
630 	}
631 }
632 
633 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
634     defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
635 
636 #ifdef CONFIG_CONSOLE_POLL
637 static int sci_poll_get_char(struct uart_port *port)
638 {
639 	unsigned short status;
640 	int c;
641 
642 	do {
643 		status = serial_port_in(port, SCxSR);
644 		if (status & SCxSR_ERRORS(port)) {
645 			sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
646 			continue;
647 		}
648 		break;
649 	} while (1);
650 
651 	if (!(status & SCxSR_RDxF(port)))
652 		return NO_POLL_CHAR;
653 
654 	c = serial_port_in(port, SCxRDR);
655 
656 	/* Dummy read */
657 	serial_port_in(port, SCxSR);
658 	sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
659 
660 	return c;
661 }
662 #endif
663 
664 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
665 {
666 	unsigned short status;
667 
668 	do {
669 		status = serial_port_in(port, SCxSR);
670 	} while (!(status & SCxSR_TDxE(port)));
671 
672 	serial_port_out(port, SCxTDR, c);
673 	sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
674 }
675 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
676 	  CONFIG_SERIAL_SH_SCI_EARLYCON */
677 
678 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
679 {
680 	struct sci_port *s = to_sci_port(port);
681 
682 	/*
683 	 * Use port-specific handler if provided.
684 	 */
685 	if (s->cfg->ops && s->cfg->ops->init_pins) {
686 		s->cfg->ops->init_pins(port, cflag);
687 		return;
688 	}
689 
690 	if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
691 		u16 data = serial_port_in(port, SCPDR);
692 		u16 ctrl = serial_port_in(port, SCPCR);
693 
694 		/* Enable RXD and TXD pin functions */
695 		ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
696 		if (to_sci_port(port)->has_rtscts) {
697 			/* RTS# is output, active low, unless autorts */
698 			if (!(port->mctrl & TIOCM_RTS)) {
699 				ctrl |= SCPCR_RTSC;
700 				data |= SCPDR_RTSD;
701 			} else if (!s->autorts) {
702 				ctrl |= SCPCR_RTSC;
703 				data &= ~SCPDR_RTSD;
704 			} else {
705 				/* Enable RTS# pin function */
706 				ctrl &= ~SCPCR_RTSC;
707 			}
708 			/* Enable CTS# pin function */
709 			ctrl &= ~SCPCR_CTSC;
710 		}
711 		serial_port_out(port, SCPDR, data);
712 		serial_port_out(port, SCPCR, ctrl);
713 	} else if (sci_getreg(port, SCSPTR)->size) {
714 		u16 status = serial_port_in(port, SCSPTR);
715 
716 		/* RTS# is always output; and active low, unless autorts */
717 		status |= SCSPTR_RTSIO;
718 		if (!(port->mctrl & TIOCM_RTS))
719 			status |= SCSPTR_RTSDT;
720 		else if (!s->autorts)
721 			status &= ~SCSPTR_RTSDT;
722 		/* CTS# and SCK are inputs */
723 		status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO);
724 		serial_port_out(port, SCSPTR, status);
725 	}
726 }
727 
728 static int sci_txfill(struct uart_port *port)
729 {
730 	struct sci_port *s = to_sci_port(port);
731 	unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
732 	const struct plat_sci_reg *reg;
733 
734 	reg = sci_getreg(port, SCTFDR);
735 	if (reg->size)
736 		return serial_port_in(port, SCTFDR) & fifo_mask;
737 
738 	reg = sci_getreg(port, SCFDR);
739 	if (reg->size)
740 		return serial_port_in(port, SCFDR) >> 8;
741 
742 	return !(serial_port_in(port, SCxSR) & SCI_TDRE);
743 }
744 
745 static int sci_txroom(struct uart_port *port)
746 {
747 	return port->fifosize - sci_txfill(port);
748 }
749 
750 static int sci_rxfill(struct uart_port *port)
751 {
752 	struct sci_port *s = to_sci_port(port);
753 	unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
754 	const struct plat_sci_reg *reg;
755 
756 	reg = sci_getreg(port, SCRFDR);
757 	if (reg->size)
758 		return serial_port_in(port, SCRFDR) & fifo_mask;
759 
760 	reg = sci_getreg(port, SCFDR);
761 	if (reg->size)
762 		return serial_port_in(port, SCFDR) & fifo_mask;
763 
764 	return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
765 }
766 
767 /* ********************************************************************** *
768  *                   the interrupt related routines                       *
769  * ********************************************************************** */
770 
771 static void sci_transmit_chars(struct uart_port *port)
772 {
773 	struct circ_buf *xmit = &port->state->xmit;
774 	unsigned int stopped = uart_tx_stopped(port);
775 	unsigned short status;
776 	unsigned short ctrl;
777 	int count;
778 
779 	status = serial_port_in(port, SCxSR);
780 	if (!(status & SCxSR_TDxE(port))) {
781 		ctrl = serial_port_in(port, SCSCR);
782 		if (uart_circ_empty(xmit))
783 			ctrl &= ~SCSCR_TIE;
784 		else
785 			ctrl |= SCSCR_TIE;
786 		serial_port_out(port, SCSCR, ctrl);
787 		return;
788 	}
789 
790 	count = sci_txroom(port);
791 
792 	do {
793 		unsigned char c;
794 
795 		if (port->x_char) {
796 			c = port->x_char;
797 			port->x_char = 0;
798 		} else if (!uart_circ_empty(xmit) && !stopped) {
799 			c = xmit->buf[xmit->tail];
800 			xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
801 		} else {
802 			break;
803 		}
804 
805 		serial_port_out(port, SCxTDR, c);
806 
807 		port->icount.tx++;
808 	} while (--count > 0);
809 
810 	sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
811 
812 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
813 		uart_write_wakeup(port);
814 	if (uart_circ_empty(xmit)) {
815 		sci_stop_tx(port);
816 	} else {
817 		ctrl = serial_port_in(port, SCSCR);
818 
819 		if (port->type != PORT_SCI) {
820 			serial_port_in(port, SCxSR); /* Dummy read */
821 			sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
822 		}
823 
824 		ctrl |= SCSCR_TIE;
825 		serial_port_out(port, SCSCR, ctrl);
826 	}
827 }
828 
829 /* On SH3, SCIF may read end-of-break as a space->mark char */
830 #define STEPFN(c)  ({int __c = (c); (((__c-1)|(__c)) == -1); })
831 
832 static void sci_receive_chars(struct uart_port *port)
833 {
834 	struct tty_port *tport = &port->state->port;
835 	int i, count, copied = 0;
836 	unsigned short status;
837 	unsigned char flag;
838 
839 	status = serial_port_in(port, SCxSR);
840 	if (!(status & SCxSR_RDxF(port)))
841 		return;
842 
843 	while (1) {
844 		/* Don't copy more bytes than there is room for in the buffer */
845 		count = tty_buffer_request_room(tport, sci_rxfill(port));
846 
847 		/* If for any reason we can't copy more data, we're done! */
848 		if (count == 0)
849 			break;
850 
851 		if (port->type == PORT_SCI) {
852 			char c = serial_port_in(port, SCxRDR);
853 			if (uart_handle_sysrq_char(port, c))
854 				count = 0;
855 			else
856 				tty_insert_flip_char(tport, c, TTY_NORMAL);
857 		} else {
858 			for (i = 0; i < count; i++) {
859 				char c = serial_port_in(port, SCxRDR);
860 
861 				status = serial_port_in(port, SCxSR);
862 				if (uart_handle_sysrq_char(port, c)) {
863 					count--; i--;
864 					continue;
865 				}
866 
867 				/* Store data and status */
868 				if (status & SCxSR_FER(port)) {
869 					flag = TTY_FRAME;
870 					port->icount.frame++;
871 					dev_notice(port->dev, "frame error\n");
872 				} else if (status & SCxSR_PER(port)) {
873 					flag = TTY_PARITY;
874 					port->icount.parity++;
875 					dev_notice(port->dev, "parity error\n");
876 				} else
877 					flag = TTY_NORMAL;
878 
879 				tty_insert_flip_char(tport, c, flag);
880 			}
881 		}
882 
883 		serial_port_in(port, SCxSR); /* dummy read */
884 		sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
885 
886 		copied += count;
887 		port->icount.rx += count;
888 	}
889 
890 	if (copied) {
891 		/* Tell the rest of the system the news. New characters! */
892 		tty_flip_buffer_push(tport);
893 	} else {
894 		/* TTY buffers full; read from RX reg to prevent lockup */
895 		serial_port_in(port, SCxRDR);
896 		serial_port_in(port, SCxSR); /* dummy read */
897 		sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
898 	}
899 }
900 
901 static int sci_handle_errors(struct uart_port *port)
902 {
903 	int copied = 0;
904 	unsigned short status = serial_port_in(port, SCxSR);
905 	struct tty_port *tport = &port->state->port;
906 	struct sci_port *s = to_sci_port(port);
907 
908 	/* Handle overruns */
909 	if (status & s->params->overrun_mask) {
910 		port->icount.overrun++;
911 
912 		/* overrun error */
913 		if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
914 			copied++;
915 
916 		dev_notice(port->dev, "overrun error\n");
917 	}
918 
919 	if (status & SCxSR_FER(port)) {
920 		/* frame error */
921 		port->icount.frame++;
922 
923 		if (tty_insert_flip_char(tport, 0, TTY_FRAME))
924 			copied++;
925 
926 		dev_notice(port->dev, "frame error\n");
927 	}
928 
929 	if (status & SCxSR_PER(port)) {
930 		/* parity error */
931 		port->icount.parity++;
932 
933 		if (tty_insert_flip_char(tport, 0, TTY_PARITY))
934 			copied++;
935 
936 		dev_notice(port->dev, "parity error\n");
937 	}
938 
939 	if (copied)
940 		tty_flip_buffer_push(tport);
941 
942 	return copied;
943 }
944 
945 static int sci_handle_fifo_overrun(struct uart_port *port)
946 {
947 	struct tty_port *tport = &port->state->port;
948 	struct sci_port *s = to_sci_port(port);
949 	const struct plat_sci_reg *reg;
950 	int copied = 0;
951 	u16 status;
952 
953 	reg = sci_getreg(port, s->params->overrun_reg);
954 	if (!reg->size)
955 		return 0;
956 
957 	status = serial_port_in(port, s->params->overrun_reg);
958 	if (status & s->params->overrun_mask) {
959 		status &= ~s->params->overrun_mask;
960 		serial_port_out(port, s->params->overrun_reg, status);
961 
962 		port->icount.overrun++;
963 
964 		tty_insert_flip_char(tport, 0, TTY_OVERRUN);
965 		tty_flip_buffer_push(tport);
966 
967 		dev_dbg(port->dev, "overrun error\n");
968 		copied++;
969 	}
970 
971 	return copied;
972 }
973 
974 static int sci_handle_breaks(struct uart_port *port)
975 {
976 	int copied = 0;
977 	unsigned short status = serial_port_in(port, SCxSR);
978 	struct tty_port *tport = &port->state->port;
979 
980 	if (uart_handle_break(port))
981 		return 0;
982 
983 	if (status & SCxSR_BRK(port)) {
984 		port->icount.brk++;
985 
986 		/* Notify of BREAK */
987 		if (tty_insert_flip_char(tport, 0, TTY_BREAK))
988 			copied++;
989 
990 		dev_dbg(port->dev, "BREAK detected\n");
991 	}
992 
993 	if (copied)
994 		tty_flip_buffer_push(tport);
995 
996 	copied += sci_handle_fifo_overrun(port);
997 
998 	return copied;
999 }
1000 
1001 static int scif_set_rtrg(struct uart_port *port, int rx_trig)
1002 {
1003 	unsigned int bits;
1004 
1005 	if (rx_trig < 1)
1006 		rx_trig = 1;
1007 	if (rx_trig >= port->fifosize)
1008 		rx_trig = port->fifosize;
1009 
1010 	/* HSCIF can be set to an arbitrary level. */
1011 	if (sci_getreg(port, HSRTRGR)->size) {
1012 		serial_port_out(port, HSRTRGR, rx_trig);
1013 		return rx_trig;
1014 	}
1015 
1016 	switch (port->type) {
1017 	case PORT_SCIF:
1018 		if (rx_trig < 4) {
1019 			bits = 0;
1020 			rx_trig = 1;
1021 		} else if (rx_trig < 8) {
1022 			bits = SCFCR_RTRG0;
1023 			rx_trig = 4;
1024 		} else if (rx_trig < 14) {
1025 			bits = SCFCR_RTRG1;
1026 			rx_trig = 8;
1027 		} else {
1028 			bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1029 			rx_trig = 14;
1030 		}
1031 		break;
1032 	case PORT_SCIFA:
1033 	case PORT_SCIFB:
1034 		if (rx_trig < 16) {
1035 			bits = 0;
1036 			rx_trig = 1;
1037 		} else if (rx_trig < 32) {
1038 			bits = SCFCR_RTRG0;
1039 			rx_trig = 16;
1040 		} else if (rx_trig < 48) {
1041 			bits = SCFCR_RTRG1;
1042 			rx_trig = 32;
1043 		} else {
1044 			bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1045 			rx_trig = 48;
1046 		}
1047 		break;
1048 	default:
1049 		WARN(1, "unknown FIFO configuration");
1050 		return 1;
1051 	}
1052 
1053 	serial_port_out(port, SCFCR,
1054 		(serial_port_in(port, SCFCR) &
1055 		~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits);
1056 
1057 	return rx_trig;
1058 }
1059 
1060 static int scif_rtrg_enabled(struct uart_port *port)
1061 {
1062 	if (sci_getreg(port, HSRTRGR)->size)
1063 		return serial_port_in(port, HSRTRGR) != 0;
1064 	else
1065 		return (serial_port_in(port, SCFCR) &
1066 			(SCFCR_RTRG0 | SCFCR_RTRG1)) != 0;
1067 }
1068 
1069 static void rx_fifo_timer_fn(struct timer_list *t)
1070 {
1071 	struct sci_port *s = from_timer(s, t, rx_fifo_timer);
1072 	struct uart_port *port = &s->port;
1073 
1074 	dev_dbg(port->dev, "Rx timed out\n");
1075 	scif_set_rtrg(port, 1);
1076 }
1077 
1078 static ssize_t rx_trigger_show(struct device *dev,
1079 			       struct device_attribute *attr,
1080 			       char *buf)
1081 {
1082 	struct uart_port *port = dev_get_drvdata(dev);
1083 	struct sci_port *sci = to_sci_port(port);
1084 
1085 	return sprintf(buf, "%d\n", sci->rx_trigger);
1086 }
1087 
1088 static ssize_t rx_trigger_store(struct device *dev,
1089 				struct device_attribute *attr,
1090 				const char *buf,
1091 				size_t count)
1092 {
1093 	struct uart_port *port = dev_get_drvdata(dev);
1094 	struct sci_port *sci = to_sci_port(port);
1095 	int ret;
1096 	long r;
1097 
1098 	ret = kstrtol(buf, 0, &r);
1099 	if (ret)
1100 		return ret;
1101 
1102 	sci->rx_trigger = scif_set_rtrg(port, r);
1103 	if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1104 		scif_set_rtrg(port, 1);
1105 
1106 	return count;
1107 }
1108 
1109 static DEVICE_ATTR(rx_fifo_trigger, 0644, rx_trigger_show, rx_trigger_store);
1110 
1111 static ssize_t rx_fifo_timeout_show(struct device *dev,
1112 			       struct device_attribute *attr,
1113 			       char *buf)
1114 {
1115 	struct uart_port *port = dev_get_drvdata(dev);
1116 	struct sci_port *sci = to_sci_port(port);
1117 	int v;
1118 
1119 	if (port->type == PORT_HSCIF)
1120 		v = sci->hscif_tot >> HSSCR_TOT_SHIFT;
1121 	else
1122 		v = sci->rx_fifo_timeout;
1123 
1124 	return sprintf(buf, "%d\n", v);
1125 }
1126 
1127 static ssize_t rx_fifo_timeout_store(struct device *dev,
1128 				struct device_attribute *attr,
1129 				const char *buf,
1130 				size_t count)
1131 {
1132 	struct uart_port *port = dev_get_drvdata(dev);
1133 	struct sci_port *sci = to_sci_port(port);
1134 	int ret;
1135 	long r;
1136 
1137 	ret = kstrtol(buf, 0, &r);
1138 	if (ret)
1139 		return ret;
1140 
1141 	if (port->type == PORT_HSCIF) {
1142 		if (r < 0 || r > 3)
1143 			return -EINVAL;
1144 		sci->hscif_tot = r << HSSCR_TOT_SHIFT;
1145 	} else {
1146 		sci->rx_fifo_timeout = r;
1147 		scif_set_rtrg(port, 1);
1148 		if (r > 0)
1149 			timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0);
1150 	}
1151 
1152 	return count;
1153 }
1154 
1155 static DEVICE_ATTR_RW(rx_fifo_timeout);
1156 
1157 
1158 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1159 static void sci_dma_tx_complete(void *arg)
1160 {
1161 	struct sci_port *s = arg;
1162 	struct uart_port *port = &s->port;
1163 	struct circ_buf *xmit = &port->state->xmit;
1164 	unsigned long flags;
1165 
1166 	dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1167 
1168 	spin_lock_irqsave(&port->lock, flags);
1169 
1170 	xmit->tail += s->tx_dma_len;
1171 	xmit->tail &= UART_XMIT_SIZE - 1;
1172 
1173 	port->icount.tx += s->tx_dma_len;
1174 
1175 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1176 		uart_write_wakeup(port);
1177 
1178 	if (!uart_circ_empty(xmit)) {
1179 		s->cookie_tx = 0;
1180 		schedule_work(&s->work_tx);
1181 	} else {
1182 		s->cookie_tx = -EINVAL;
1183 		if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1184 			u16 ctrl = serial_port_in(port, SCSCR);
1185 			serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1186 		}
1187 	}
1188 
1189 	spin_unlock_irqrestore(&port->lock, flags);
1190 }
1191 
1192 /* Locking: called with port lock held */
1193 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1194 {
1195 	struct uart_port *port = &s->port;
1196 	struct tty_port *tport = &port->state->port;
1197 	int copied;
1198 
1199 	copied = tty_insert_flip_string(tport, buf, count);
1200 	if (copied < count)
1201 		port->icount.buf_overrun++;
1202 
1203 	port->icount.rx += copied;
1204 
1205 	return copied;
1206 }
1207 
1208 static int sci_dma_rx_find_active(struct sci_port *s)
1209 {
1210 	unsigned int i;
1211 
1212 	for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1213 		if (s->active_rx == s->cookie_rx[i])
1214 			return i;
1215 
1216 	return -1;
1217 }
1218 
1219 static void sci_rx_dma_release(struct sci_port *s)
1220 {
1221 	struct dma_chan *chan = s->chan_rx_saved;
1222 
1223 	s->chan_rx_saved = s->chan_rx = NULL;
1224 	s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1225 	dmaengine_terminate_sync(chan);
1226 	dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1227 			  sg_dma_address(&s->sg_rx[0]));
1228 	dma_release_channel(chan);
1229 }
1230 
1231 static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec)
1232 {
1233 	long sec = usec / 1000000;
1234 	long nsec = (usec % 1000000) * 1000;
1235 	ktime_t t = ktime_set(sec, nsec);
1236 
1237 	hrtimer_start(hrt, t, HRTIMER_MODE_REL);
1238 }
1239 
1240 static void sci_dma_rx_complete(void *arg)
1241 {
1242 	struct sci_port *s = arg;
1243 	struct dma_chan *chan = s->chan_rx;
1244 	struct uart_port *port = &s->port;
1245 	struct dma_async_tx_descriptor *desc;
1246 	unsigned long flags;
1247 	int active, count = 0;
1248 
1249 	dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1250 		s->active_rx);
1251 
1252 	spin_lock_irqsave(&port->lock, flags);
1253 
1254 	active = sci_dma_rx_find_active(s);
1255 	if (active >= 0)
1256 		count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
1257 
1258 	start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1259 
1260 	if (count)
1261 		tty_flip_buffer_push(&port->state->port);
1262 
1263 	desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1264 				       DMA_DEV_TO_MEM,
1265 				       DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1266 	if (!desc)
1267 		goto fail;
1268 
1269 	desc->callback = sci_dma_rx_complete;
1270 	desc->callback_param = s;
1271 	s->cookie_rx[active] = dmaengine_submit(desc);
1272 	if (dma_submit_error(s->cookie_rx[active]))
1273 		goto fail;
1274 
1275 	s->active_rx = s->cookie_rx[!active];
1276 
1277 	dma_async_issue_pending(chan);
1278 
1279 	spin_unlock_irqrestore(&port->lock, flags);
1280 	dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1281 		__func__, s->cookie_rx[active], active, s->active_rx);
1282 	return;
1283 
1284 fail:
1285 	spin_unlock_irqrestore(&port->lock, flags);
1286 	dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1287 	/* Switch to PIO */
1288 	spin_lock_irqsave(&port->lock, flags);
1289 	s->chan_rx = NULL;
1290 	sci_start_rx(port);
1291 	spin_unlock_irqrestore(&port->lock, flags);
1292 }
1293 
1294 static void sci_tx_dma_release(struct sci_port *s)
1295 {
1296 	struct dma_chan *chan = s->chan_tx_saved;
1297 
1298 	cancel_work_sync(&s->work_tx);
1299 	s->chan_tx_saved = s->chan_tx = NULL;
1300 	s->cookie_tx = -EINVAL;
1301 	dmaengine_terminate_sync(chan);
1302 	dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1303 			 DMA_TO_DEVICE);
1304 	dma_release_channel(chan);
1305 }
1306 
1307 static void sci_submit_rx(struct sci_port *s)
1308 {
1309 	struct dma_chan *chan = s->chan_rx;
1310 	struct uart_port *port = &s->port;
1311 	unsigned long flags;
1312 	int i;
1313 
1314 	for (i = 0; i < 2; i++) {
1315 		struct scatterlist *sg = &s->sg_rx[i];
1316 		struct dma_async_tx_descriptor *desc;
1317 
1318 		desc = dmaengine_prep_slave_sg(chan,
1319 			sg, 1, DMA_DEV_TO_MEM,
1320 			DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1321 		if (!desc)
1322 			goto fail;
1323 
1324 		desc->callback = sci_dma_rx_complete;
1325 		desc->callback_param = s;
1326 		s->cookie_rx[i] = dmaengine_submit(desc);
1327 		if (dma_submit_error(s->cookie_rx[i]))
1328 			goto fail;
1329 
1330 	}
1331 
1332 	s->active_rx = s->cookie_rx[0];
1333 
1334 	dma_async_issue_pending(chan);
1335 	return;
1336 
1337 fail:
1338 	if (i)
1339 		dmaengine_terminate_async(chan);
1340 	for (i = 0; i < 2; i++)
1341 		s->cookie_rx[i] = -EINVAL;
1342 	s->active_rx = -EINVAL;
1343 	/* Switch to PIO */
1344 	spin_lock_irqsave(&port->lock, flags);
1345 	s->chan_rx = NULL;
1346 	sci_start_rx(port);
1347 	spin_unlock_irqrestore(&port->lock, flags);
1348 }
1349 
1350 static void work_fn_tx(struct work_struct *work)
1351 {
1352 	struct sci_port *s = container_of(work, struct sci_port, work_tx);
1353 	struct dma_async_tx_descriptor *desc;
1354 	struct dma_chan *chan = s->chan_tx;
1355 	struct uart_port *port = &s->port;
1356 	struct circ_buf *xmit = &port->state->xmit;
1357 	unsigned long flags;
1358 	dma_addr_t buf;
1359 
1360 	/*
1361 	 * DMA is idle now.
1362 	 * Port xmit buffer is already mapped, and it is one page... Just adjust
1363 	 * offsets and lengths. Since it is a circular buffer, we have to
1364 	 * transmit till the end, and then the rest. Take the port lock to get a
1365 	 * consistent xmit buffer state.
1366 	 */
1367 	spin_lock_irq(&port->lock);
1368 	buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1));
1369 	s->tx_dma_len = min_t(unsigned int,
1370 		CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1371 		CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1372 	spin_unlock_irq(&port->lock);
1373 
1374 	desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1375 					   DMA_MEM_TO_DEV,
1376 					   DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1377 	if (!desc) {
1378 		dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1379 		goto switch_to_pio;
1380 	}
1381 
1382 	dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1383 				   DMA_TO_DEVICE);
1384 
1385 	spin_lock_irq(&port->lock);
1386 	desc->callback = sci_dma_tx_complete;
1387 	desc->callback_param = s;
1388 	spin_unlock_irq(&port->lock);
1389 	s->cookie_tx = dmaengine_submit(desc);
1390 	if (dma_submit_error(s->cookie_tx)) {
1391 		dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1392 		goto switch_to_pio;
1393 	}
1394 
1395 	dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1396 		__func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1397 
1398 	dma_async_issue_pending(chan);
1399 	return;
1400 
1401 switch_to_pio:
1402 	spin_lock_irqsave(&port->lock, flags);
1403 	s->chan_tx = NULL;
1404 	sci_start_tx(port);
1405 	spin_unlock_irqrestore(&port->lock, flags);
1406 	return;
1407 }
1408 
1409 static enum hrtimer_restart rx_timer_fn(struct hrtimer *t)
1410 {
1411 	struct sci_port *s = container_of(t, struct sci_port, rx_timer);
1412 	struct dma_chan *chan = s->chan_rx;
1413 	struct uart_port *port = &s->port;
1414 	struct dma_tx_state state;
1415 	enum dma_status status;
1416 	unsigned long flags;
1417 	unsigned int read;
1418 	int active, count;
1419 	u16 scr;
1420 
1421 	dev_dbg(port->dev, "DMA Rx timed out\n");
1422 
1423 	spin_lock_irqsave(&port->lock, flags);
1424 
1425 	active = sci_dma_rx_find_active(s);
1426 	if (active < 0) {
1427 		spin_unlock_irqrestore(&port->lock, flags);
1428 		return HRTIMER_NORESTART;
1429 	}
1430 
1431 	status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1432 	if (status == DMA_COMPLETE) {
1433 		spin_unlock_irqrestore(&port->lock, flags);
1434 		dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1435 			s->active_rx, active);
1436 
1437 		/* Let packet complete handler take care of the packet */
1438 		return HRTIMER_NORESTART;
1439 	}
1440 
1441 	dmaengine_pause(chan);
1442 
1443 	/*
1444 	 * sometimes DMA transfer doesn't stop even if it is stopped and
1445 	 * data keeps on coming until transaction is complete so check
1446 	 * for DMA_COMPLETE again
1447 	 * Let packet complete handler take care of the packet
1448 	 */
1449 	status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1450 	if (status == DMA_COMPLETE) {
1451 		spin_unlock_irqrestore(&port->lock, flags);
1452 		dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1453 		return HRTIMER_NORESTART;
1454 	}
1455 
1456 	/* Handle incomplete DMA receive */
1457 	dmaengine_terminate_async(s->chan_rx);
1458 	read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1459 
1460 	if (read) {
1461 		count = sci_dma_rx_push(s, s->rx_buf[active], read);
1462 		if (count)
1463 			tty_flip_buffer_push(&port->state->port);
1464 	}
1465 
1466 	if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1467 		sci_submit_rx(s);
1468 
1469 	/* Direct new serial port interrupts back to CPU */
1470 	scr = serial_port_in(port, SCSCR);
1471 	if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1472 		scr &= ~SCSCR_RDRQE;
1473 		enable_irq(s->irqs[SCIx_RXI_IRQ]);
1474 	}
1475 	serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1476 
1477 	spin_unlock_irqrestore(&port->lock, flags);
1478 
1479 	return HRTIMER_NORESTART;
1480 }
1481 
1482 static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1483 					     enum dma_transfer_direction dir)
1484 {
1485 	struct dma_chan *chan;
1486 	struct dma_slave_config cfg;
1487 	int ret;
1488 
1489 	chan = dma_request_slave_channel(port->dev,
1490 					 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1491 	if (!chan) {
1492 		dev_warn(port->dev, "dma_request_slave_channel failed\n");
1493 		return NULL;
1494 	}
1495 
1496 	memset(&cfg, 0, sizeof(cfg));
1497 	cfg.direction = dir;
1498 	if (dir == DMA_MEM_TO_DEV) {
1499 		cfg.dst_addr = port->mapbase +
1500 			(sci_getreg(port, SCxTDR)->offset << port->regshift);
1501 		cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1502 	} else {
1503 		cfg.src_addr = port->mapbase +
1504 			(sci_getreg(port, SCxRDR)->offset << port->regshift);
1505 		cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1506 	}
1507 
1508 	ret = dmaengine_slave_config(chan, &cfg);
1509 	if (ret) {
1510 		dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1511 		dma_release_channel(chan);
1512 		return NULL;
1513 	}
1514 
1515 	return chan;
1516 }
1517 
1518 static void sci_request_dma(struct uart_port *port)
1519 {
1520 	struct sci_port *s = to_sci_port(port);
1521 	struct dma_chan *chan;
1522 
1523 	dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1524 
1525 	if (!port->dev->of_node)
1526 		return;
1527 
1528 	s->cookie_tx = -EINVAL;
1529 
1530 	/*
1531 	 * Don't request a dma channel if no channel was specified
1532 	 * in the device tree.
1533 	 */
1534 	if (!of_find_property(port->dev->of_node, "dmas", NULL))
1535 		return;
1536 
1537 	chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV);
1538 	dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1539 	if (chan) {
1540 		/* UART circular tx buffer is an aligned page. */
1541 		s->tx_dma_addr = dma_map_single(chan->device->dev,
1542 						port->state->xmit.buf,
1543 						UART_XMIT_SIZE,
1544 						DMA_TO_DEVICE);
1545 		if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1546 			dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1547 			dma_release_channel(chan);
1548 		} else {
1549 			dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1550 				__func__, UART_XMIT_SIZE,
1551 				port->state->xmit.buf, &s->tx_dma_addr);
1552 
1553 			INIT_WORK(&s->work_tx, work_fn_tx);
1554 			s->chan_tx_saved = s->chan_tx = chan;
1555 		}
1556 	}
1557 
1558 	chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM);
1559 	dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1560 	if (chan) {
1561 		unsigned int i;
1562 		dma_addr_t dma;
1563 		void *buf;
1564 
1565 		s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1566 		buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1567 					 &dma, GFP_KERNEL);
1568 		if (!buf) {
1569 			dev_warn(port->dev,
1570 				 "Failed to allocate Rx dma buffer, using PIO\n");
1571 			dma_release_channel(chan);
1572 			return;
1573 		}
1574 
1575 		for (i = 0; i < 2; i++) {
1576 			struct scatterlist *sg = &s->sg_rx[i];
1577 
1578 			sg_init_table(sg, 1);
1579 			s->rx_buf[i] = buf;
1580 			sg_dma_address(sg) = dma;
1581 			sg_dma_len(sg) = s->buf_len_rx;
1582 
1583 			buf += s->buf_len_rx;
1584 			dma += s->buf_len_rx;
1585 		}
1586 
1587 		hrtimer_init(&s->rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1588 		s->rx_timer.function = rx_timer_fn;
1589 
1590 		if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1591 			sci_submit_rx(s);
1592 
1593 		s->chan_rx_saved = s->chan_rx = chan;
1594 	}
1595 }
1596 
1597 static void sci_free_dma(struct uart_port *port)
1598 {
1599 	struct sci_port *s = to_sci_port(port);
1600 
1601 	if (s->chan_tx_saved)
1602 		sci_tx_dma_release(s);
1603 	if (s->chan_rx_saved)
1604 		sci_rx_dma_release(s);
1605 }
1606 
1607 static void sci_flush_buffer(struct uart_port *port)
1608 {
1609 	/*
1610 	 * In uart_flush_buffer(), the xmit circular buffer has just been
1611 	 * cleared, so we have to reset tx_dma_len accordingly.
1612 	 */
1613 	to_sci_port(port)->tx_dma_len = 0;
1614 }
1615 #else /* !CONFIG_SERIAL_SH_SCI_DMA */
1616 static inline void sci_request_dma(struct uart_port *port)
1617 {
1618 }
1619 
1620 static inline void sci_free_dma(struct uart_port *port)
1621 {
1622 }
1623 
1624 #define sci_flush_buffer	NULL
1625 #endif /* !CONFIG_SERIAL_SH_SCI_DMA */
1626 
1627 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1628 {
1629 	struct uart_port *port = ptr;
1630 	struct sci_port *s = to_sci_port(port);
1631 
1632 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1633 	if (s->chan_rx) {
1634 		u16 scr = serial_port_in(port, SCSCR);
1635 		u16 ssr = serial_port_in(port, SCxSR);
1636 
1637 		/* Disable future Rx interrupts */
1638 		if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1639 			disable_irq_nosync(irq);
1640 			scr |= SCSCR_RDRQE;
1641 		} else {
1642 			scr &= ~SCSCR_RIE;
1643 			sci_submit_rx(s);
1644 		}
1645 		serial_port_out(port, SCSCR, scr);
1646 		/* Clear current interrupt */
1647 		serial_port_out(port, SCxSR,
1648 				ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1649 		dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n",
1650 			jiffies, s->rx_timeout);
1651 		start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1652 
1653 		return IRQ_HANDLED;
1654 	}
1655 #endif
1656 
1657 	if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) {
1658 		if (!scif_rtrg_enabled(port))
1659 			scif_set_rtrg(port, s->rx_trigger);
1660 
1661 		mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP(
1662 			  s->rx_frame * HZ * s->rx_fifo_timeout, 1000000));
1663 	}
1664 
1665 	/* I think sci_receive_chars has to be called irrespective
1666 	 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1667 	 * to be disabled?
1668 	 */
1669 	sci_receive_chars(ptr);
1670 
1671 	return IRQ_HANDLED;
1672 }
1673 
1674 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1675 {
1676 	struct uart_port *port = ptr;
1677 	unsigned long flags;
1678 
1679 	spin_lock_irqsave(&port->lock, flags);
1680 	sci_transmit_chars(port);
1681 	spin_unlock_irqrestore(&port->lock, flags);
1682 
1683 	return IRQ_HANDLED;
1684 }
1685 
1686 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1687 {
1688 	struct uart_port *port = ptr;
1689 
1690 	/* Handle BREAKs */
1691 	sci_handle_breaks(port);
1692 	sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1693 
1694 	return IRQ_HANDLED;
1695 }
1696 
1697 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1698 {
1699 	struct uart_port *port = ptr;
1700 	struct sci_port *s = to_sci_port(port);
1701 
1702 	if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) {
1703 		/* Break and Error interrupts are muxed */
1704 		unsigned short ssr_status = serial_port_in(port, SCxSR);
1705 
1706 		/* Break Interrupt */
1707 		if (ssr_status & SCxSR_BRK(port))
1708 			sci_br_interrupt(irq, ptr);
1709 
1710 		/* Break only? */
1711 		if (!(ssr_status & SCxSR_ERRORS(port)))
1712 			return IRQ_HANDLED;
1713 	}
1714 
1715 	/* Handle errors */
1716 	if (port->type == PORT_SCI) {
1717 		if (sci_handle_errors(port)) {
1718 			/* discard character in rx buffer */
1719 			serial_port_in(port, SCxSR);
1720 			sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1721 		}
1722 	} else {
1723 		sci_handle_fifo_overrun(port);
1724 		if (!s->chan_rx)
1725 			sci_receive_chars(ptr);
1726 	}
1727 
1728 	sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1729 
1730 	/* Kick the transmission */
1731 	if (!s->chan_tx)
1732 		sci_tx_interrupt(irq, ptr);
1733 
1734 	return IRQ_HANDLED;
1735 }
1736 
1737 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1738 {
1739 	unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1740 	struct uart_port *port = ptr;
1741 	struct sci_port *s = to_sci_port(port);
1742 	irqreturn_t ret = IRQ_NONE;
1743 
1744 	ssr_status = serial_port_in(port, SCxSR);
1745 	scr_status = serial_port_in(port, SCSCR);
1746 	if (s->params->overrun_reg == SCxSR)
1747 		orer_status = ssr_status;
1748 	else if (sci_getreg(port, s->params->overrun_reg)->size)
1749 		orer_status = serial_port_in(port, s->params->overrun_reg);
1750 
1751 	err_enabled = scr_status & port_rx_irq_mask(port);
1752 
1753 	/* Tx Interrupt */
1754 	if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1755 	    !s->chan_tx)
1756 		ret = sci_tx_interrupt(irq, ptr);
1757 
1758 	/*
1759 	 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1760 	 * DR flags
1761 	 */
1762 	if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1763 	    (scr_status & SCSCR_RIE))
1764 		ret = sci_rx_interrupt(irq, ptr);
1765 
1766 	/* Error Interrupt */
1767 	if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1768 		ret = sci_er_interrupt(irq, ptr);
1769 
1770 	/* Break Interrupt */
1771 	if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1772 		ret = sci_br_interrupt(irq, ptr);
1773 
1774 	/* Overrun Interrupt */
1775 	if (orer_status & s->params->overrun_mask) {
1776 		sci_handle_fifo_overrun(port);
1777 		ret = IRQ_HANDLED;
1778 	}
1779 
1780 	return ret;
1781 }
1782 
1783 static const struct sci_irq_desc {
1784 	const char	*desc;
1785 	irq_handler_t	handler;
1786 } sci_irq_desc[] = {
1787 	/*
1788 	 * Split out handlers, the default case.
1789 	 */
1790 	[SCIx_ERI_IRQ] = {
1791 		.desc = "rx err",
1792 		.handler = sci_er_interrupt,
1793 	},
1794 
1795 	[SCIx_RXI_IRQ] = {
1796 		.desc = "rx full",
1797 		.handler = sci_rx_interrupt,
1798 	},
1799 
1800 	[SCIx_TXI_IRQ] = {
1801 		.desc = "tx empty",
1802 		.handler = sci_tx_interrupt,
1803 	},
1804 
1805 	[SCIx_BRI_IRQ] = {
1806 		.desc = "break",
1807 		.handler = sci_br_interrupt,
1808 	},
1809 
1810 	[SCIx_DRI_IRQ] = {
1811 		.desc = "rx ready",
1812 		.handler = sci_rx_interrupt,
1813 	},
1814 
1815 	[SCIx_TEI_IRQ] = {
1816 		.desc = "tx end",
1817 		.handler = sci_tx_interrupt,
1818 	},
1819 
1820 	/*
1821 	 * Special muxed handler.
1822 	 */
1823 	[SCIx_MUX_IRQ] = {
1824 		.desc = "mux",
1825 		.handler = sci_mpxed_interrupt,
1826 	},
1827 };
1828 
1829 static int sci_request_irq(struct sci_port *port)
1830 {
1831 	struct uart_port *up = &port->port;
1832 	int i, j, w, ret = 0;
1833 
1834 	for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1835 		const struct sci_irq_desc *desc;
1836 		int irq;
1837 
1838 		/* Check if already registered (muxed) */
1839 		for (w = 0; w < i; w++)
1840 			if (port->irqs[w] == port->irqs[i])
1841 				w = i + 1;
1842 		if (w > i)
1843 			continue;
1844 
1845 		if (SCIx_IRQ_IS_MUXED(port)) {
1846 			i = SCIx_MUX_IRQ;
1847 			irq = up->irq;
1848 		} else {
1849 			irq = port->irqs[i];
1850 
1851 			/*
1852 			 * Certain port types won't support all of the
1853 			 * available interrupt sources.
1854 			 */
1855 			if (unlikely(irq < 0))
1856 				continue;
1857 		}
1858 
1859 		desc = sci_irq_desc + i;
1860 		port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1861 					    dev_name(up->dev), desc->desc);
1862 		if (!port->irqstr[j]) {
1863 			ret = -ENOMEM;
1864 			goto out_nomem;
1865 		}
1866 
1867 		ret = request_irq(irq, desc->handler, up->irqflags,
1868 				  port->irqstr[j], port);
1869 		if (unlikely(ret)) {
1870 			dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1871 			goto out_noirq;
1872 		}
1873 	}
1874 
1875 	return 0;
1876 
1877 out_noirq:
1878 	while (--i >= 0)
1879 		free_irq(port->irqs[i], port);
1880 
1881 out_nomem:
1882 	while (--j >= 0)
1883 		kfree(port->irqstr[j]);
1884 
1885 	return ret;
1886 }
1887 
1888 static void sci_free_irq(struct sci_port *port)
1889 {
1890 	int i;
1891 
1892 	/*
1893 	 * Intentionally in reverse order so we iterate over the muxed
1894 	 * IRQ first.
1895 	 */
1896 	for (i = 0; i < SCIx_NR_IRQS; i++) {
1897 		int irq = port->irqs[i];
1898 
1899 		/*
1900 		 * Certain port types won't support all of the available
1901 		 * interrupt sources.
1902 		 */
1903 		if (unlikely(irq < 0))
1904 			continue;
1905 
1906 		free_irq(port->irqs[i], port);
1907 		kfree(port->irqstr[i]);
1908 
1909 		if (SCIx_IRQ_IS_MUXED(port)) {
1910 			/* If there's only one IRQ, we're done. */
1911 			return;
1912 		}
1913 	}
1914 }
1915 
1916 static unsigned int sci_tx_empty(struct uart_port *port)
1917 {
1918 	unsigned short status = serial_port_in(port, SCxSR);
1919 	unsigned short in_tx_fifo = sci_txfill(port);
1920 
1921 	return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1922 }
1923 
1924 static void sci_set_rts(struct uart_port *port, bool state)
1925 {
1926 	if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1927 		u16 data = serial_port_in(port, SCPDR);
1928 
1929 		/* Active low */
1930 		if (state)
1931 			data &= ~SCPDR_RTSD;
1932 		else
1933 			data |= SCPDR_RTSD;
1934 		serial_port_out(port, SCPDR, data);
1935 
1936 		/* RTS# is output */
1937 		serial_port_out(port, SCPCR,
1938 				serial_port_in(port, SCPCR) | SCPCR_RTSC);
1939 	} else if (sci_getreg(port, SCSPTR)->size) {
1940 		u16 ctrl = serial_port_in(port, SCSPTR);
1941 
1942 		/* Active low */
1943 		if (state)
1944 			ctrl &= ~SCSPTR_RTSDT;
1945 		else
1946 			ctrl |= SCSPTR_RTSDT;
1947 		serial_port_out(port, SCSPTR, ctrl);
1948 	}
1949 }
1950 
1951 static bool sci_get_cts(struct uart_port *port)
1952 {
1953 	if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1954 		/* Active low */
1955 		return !(serial_port_in(port, SCPDR) & SCPDR_CTSD);
1956 	} else if (sci_getreg(port, SCSPTR)->size) {
1957 		/* Active low */
1958 		return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT);
1959 	}
1960 
1961 	return true;
1962 }
1963 
1964 /*
1965  * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1966  * CTS/RTS is supported in hardware by at least one port and controlled
1967  * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1968  * handled via the ->init_pins() op, which is a bit of a one-way street,
1969  * lacking any ability to defer pin control -- this will later be
1970  * converted over to the GPIO framework).
1971  *
1972  * Other modes (such as loopback) are supported generically on certain
1973  * port types, but not others. For these it's sufficient to test for the
1974  * existence of the support register and simply ignore the port type.
1975  */
1976 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1977 {
1978 	struct sci_port *s = to_sci_port(port);
1979 
1980 	if (mctrl & TIOCM_LOOP) {
1981 		const struct plat_sci_reg *reg;
1982 
1983 		/*
1984 		 * Standard loopback mode for SCFCR ports.
1985 		 */
1986 		reg = sci_getreg(port, SCFCR);
1987 		if (reg->size)
1988 			serial_port_out(port, SCFCR,
1989 					serial_port_in(port, SCFCR) |
1990 					SCFCR_LOOP);
1991 	}
1992 
1993 	mctrl_gpio_set(s->gpios, mctrl);
1994 
1995 	if (!s->has_rtscts)
1996 		return;
1997 
1998 	if (!(mctrl & TIOCM_RTS)) {
1999 		/* Disable Auto RTS */
2000 		serial_port_out(port, SCFCR,
2001 				serial_port_in(port, SCFCR) & ~SCFCR_MCE);
2002 
2003 		/* Clear RTS */
2004 		sci_set_rts(port, 0);
2005 	} else if (s->autorts) {
2006 		if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2007 			/* Enable RTS# pin function */
2008 			serial_port_out(port, SCPCR,
2009 				serial_port_in(port, SCPCR) & ~SCPCR_RTSC);
2010 		}
2011 
2012 		/* Enable Auto RTS */
2013 		serial_port_out(port, SCFCR,
2014 				serial_port_in(port, SCFCR) | SCFCR_MCE);
2015 	} else {
2016 		/* Set RTS */
2017 		sci_set_rts(port, 1);
2018 	}
2019 }
2020 
2021 static unsigned int sci_get_mctrl(struct uart_port *port)
2022 {
2023 	struct sci_port *s = to_sci_port(port);
2024 	struct mctrl_gpios *gpios = s->gpios;
2025 	unsigned int mctrl = 0;
2026 
2027 	mctrl_gpio_get(gpios, &mctrl);
2028 
2029 	/*
2030 	 * CTS/RTS is handled in hardware when supported, while nothing
2031 	 * else is wired up.
2032 	 */
2033 	if (s->autorts) {
2034 		if (sci_get_cts(port))
2035 			mctrl |= TIOCM_CTS;
2036 	} else if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS))) {
2037 		mctrl |= TIOCM_CTS;
2038 	}
2039 	if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)))
2040 		mctrl |= TIOCM_DSR;
2041 	if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)))
2042 		mctrl |= TIOCM_CAR;
2043 
2044 	return mctrl;
2045 }
2046 
2047 static void sci_enable_ms(struct uart_port *port)
2048 {
2049 	mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
2050 }
2051 
2052 static void sci_break_ctl(struct uart_port *port, int break_state)
2053 {
2054 	unsigned short scscr, scsptr;
2055 	unsigned long flags;
2056 
2057 	/* check wheter the port has SCSPTR */
2058 	if (!sci_getreg(port, SCSPTR)->size) {
2059 		/*
2060 		 * Not supported by hardware. Most parts couple break and rx
2061 		 * interrupts together, with break detection always enabled.
2062 		 */
2063 		return;
2064 	}
2065 
2066 	spin_lock_irqsave(&port->lock, flags);
2067 	scsptr = serial_port_in(port, SCSPTR);
2068 	scscr = serial_port_in(port, SCSCR);
2069 
2070 	if (break_state == -1) {
2071 		scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
2072 		scscr &= ~SCSCR_TE;
2073 	} else {
2074 		scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
2075 		scscr |= SCSCR_TE;
2076 	}
2077 
2078 	serial_port_out(port, SCSPTR, scsptr);
2079 	serial_port_out(port, SCSCR, scscr);
2080 	spin_unlock_irqrestore(&port->lock, flags);
2081 }
2082 
2083 static int sci_startup(struct uart_port *port)
2084 {
2085 	struct sci_port *s = to_sci_port(port);
2086 	int ret;
2087 
2088 	dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2089 
2090 	sci_request_dma(port);
2091 
2092 	ret = sci_request_irq(s);
2093 	if (unlikely(ret < 0)) {
2094 		sci_free_dma(port);
2095 		return ret;
2096 	}
2097 
2098 	return 0;
2099 }
2100 
2101 static void sci_shutdown(struct uart_port *port)
2102 {
2103 	struct sci_port *s = to_sci_port(port);
2104 	unsigned long flags;
2105 	u16 scr;
2106 
2107 	dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2108 
2109 	s->autorts = false;
2110 	mctrl_gpio_disable_ms(to_sci_port(port)->gpios);
2111 
2112 	spin_lock_irqsave(&port->lock, flags);
2113 	sci_stop_rx(port);
2114 	sci_stop_tx(port);
2115 	/*
2116 	 * Stop RX and TX, disable related interrupts, keep clock source
2117 	 * and HSCIF TOT bits
2118 	 */
2119 	scr = serial_port_in(port, SCSCR);
2120 	serial_port_out(port, SCSCR, scr &
2121 			(SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot));
2122 	spin_unlock_irqrestore(&port->lock, flags);
2123 
2124 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2125 	if (s->chan_rx_saved) {
2126 		dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
2127 			port->line);
2128 		hrtimer_cancel(&s->rx_timer);
2129 	}
2130 #endif
2131 
2132 	if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0)
2133 		del_timer_sync(&s->rx_fifo_timer);
2134 	sci_free_irq(s);
2135 	sci_free_dma(port);
2136 }
2137 
2138 static int sci_sck_calc(struct sci_port *s, unsigned int bps,
2139 			unsigned int *srr)
2140 {
2141 	unsigned long freq = s->clk_rates[SCI_SCK];
2142 	int err, min_err = INT_MAX;
2143 	unsigned int sr;
2144 
2145 	if (s->port.type != PORT_HSCIF)
2146 		freq *= 2;
2147 
2148 	for_each_sr(sr, s) {
2149 		err = DIV_ROUND_CLOSEST(freq, sr) - bps;
2150 		if (abs(err) >= abs(min_err))
2151 			continue;
2152 
2153 		min_err = err;
2154 		*srr = sr - 1;
2155 
2156 		if (!err)
2157 			break;
2158 	}
2159 
2160 	dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
2161 		*srr + 1);
2162 	return min_err;
2163 }
2164 
2165 static int sci_brg_calc(struct sci_port *s, unsigned int bps,
2166 			unsigned long freq, unsigned int *dlr,
2167 			unsigned int *srr)
2168 {
2169 	int err, min_err = INT_MAX;
2170 	unsigned int sr, dl;
2171 
2172 	if (s->port.type != PORT_HSCIF)
2173 		freq *= 2;
2174 
2175 	for_each_sr(sr, s) {
2176 		dl = DIV_ROUND_CLOSEST(freq, sr * bps);
2177 		dl = clamp(dl, 1U, 65535U);
2178 
2179 		err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
2180 		if (abs(err) >= abs(min_err))
2181 			continue;
2182 
2183 		min_err = err;
2184 		*dlr = dl;
2185 		*srr = sr - 1;
2186 
2187 		if (!err)
2188 			break;
2189 	}
2190 
2191 	dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
2192 		min_err, *dlr, *srr + 1);
2193 	return min_err;
2194 }
2195 
2196 /* calculate sample rate, BRR, and clock select */
2197 static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
2198 			  unsigned int *brr, unsigned int *srr,
2199 			  unsigned int *cks)
2200 {
2201 	unsigned long freq = s->clk_rates[SCI_FCK];
2202 	unsigned int sr, br, prediv, scrate, c;
2203 	int err, min_err = INT_MAX;
2204 
2205 	if (s->port.type != PORT_HSCIF)
2206 		freq *= 2;
2207 
2208 	/*
2209 	 * Find the combination of sample rate and clock select with the
2210 	 * smallest deviation from the desired baud rate.
2211 	 * Prefer high sample rates to maximise the receive margin.
2212 	 *
2213 	 * M: Receive margin (%)
2214 	 * N: Ratio of bit rate to clock (N = sampling rate)
2215 	 * D: Clock duty (D = 0 to 1.0)
2216 	 * L: Frame length (L = 9 to 12)
2217 	 * F: Absolute value of clock frequency deviation
2218 	 *
2219 	 *  M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
2220 	 *      (|D - 0.5| / N * (1 + F))|
2221 	 *  NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
2222 	 */
2223 	for_each_sr(sr, s) {
2224 		for (c = 0; c <= 3; c++) {
2225 			/* integerized formulas from HSCIF documentation */
2226 			prediv = sr * (1 << (2 * c + 1));
2227 
2228 			/*
2229 			 * We need to calculate:
2230 			 *
2231 			 *     br = freq / (prediv * bps) clamped to [1..256]
2232 			 *     err = freq / (br * prediv) - bps
2233 			 *
2234 			 * Watch out for overflow when calculating the desired
2235 			 * sampling clock rate!
2236 			 */
2237 			if (bps > UINT_MAX / prediv)
2238 				break;
2239 
2240 			scrate = prediv * bps;
2241 			br = DIV_ROUND_CLOSEST(freq, scrate);
2242 			br = clamp(br, 1U, 256U);
2243 
2244 			err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
2245 			if (abs(err) >= abs(min_err))
2246 				continue;
2247 
2248 			min_err = err;
2249 			*brr = br - 1;
2250 			*srr = sr - 1;
2251 			*cks = c;
2252 
2253 			if (!err)
2254 				goto found;
2255 		}
2256 	}
2257 
2258 found:
2259 	dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2260 		min_err, *brr, *srr + 1, *cks);
2261 	return min_err;
2262 }
2263 
2264 static void sci_reset(struct uart_port *port)
2265 {
2266 	const struct plat_sci_reg *reg;
2267 	unsigned int status;
2268 	struct sci_port *s = to_sci_port(port);
2269 
2270 	serial_port_out(port, SCSCR, s->hscif_tot);	/* TE=0, RE=0, CKE1=0 */
2271 
2272 	reg = sci_getreg(port, SCFCR);
2273 	if (reg->size)
2274 		serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2275 
2276 	sci_clear_SCxSR(port,
2277 			SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
2278 			SCxSR_BREAK_CLEAR(port));
2279 	if (sci_getreg(port, SCLSR)->size) {
2280 		status = serial_port_in(port, SCLSR);
2281 		status &= ~(SCLSR_TO | SCLSR_ORER);
2282 		serial_port_out(port, SCLSR, status);
2283 	}
2284 
2285 	if (s->rx_trigger > 1) {
2286 		if (s->rx_fifo_timeout) {
2287 			scif_set_rtrg(port, 1);
2288 			timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0);
2289 		} else {
2290 			if (port->type == PORT_SCIFA ||
2291 			    port->type == PORT_SCIFB)
2292 				scif_set_rtrg(port, 1);
2293 			else
2294 				scif_set_rtrg(port, s->rx_trigger);
2295 		}
2296 	}
2297 }
2298 
2299 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2300 			    struct ktermios *old)
2301 {
2302 	unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits;
2303 	unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
2304 	unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
2305 	struct sci_port *s = to_sci_port(port);
2306 	const struct plat_sci_reg *reg;
2307 	int min_err = INT_MAX, err;
2308 	unsigned long max_freq = 0;
2309 	int best_clk = -1;
2310 	unsigned long flags;
2311 
2312 	if ((termios->c_cflag & CSIZE) == CS7)
2313 		smr_val |= SCSMR_CHR;
2314 	if (termios->c_cflag & PARENB)
2315 		smr_val |= SCSMR_PE;
2316 	if (termios->c_cflag & PARODD)
2317 		smr_val |= SCSMR_PE | SCSMR_ODD;
2318 	if (termios->c_cflag & CSTOPB)
2319 		smr_val |= SCSMR_STOP;
2320 
2321 	/*
2322 	 * earlyprintk comes here early on with port->uartclk set to zero.
2323 	 * the clock framework is not up and running at this point so here
2324 	 * we assume that 115200 is the maximum baud rate. please note that
2325 	 * the baud rate is not programmed during earlyprintk - it is assumed
2326 	 * that the previous boot loader has enabled required clocks and
2327 	 * setup the baud rate generator hardware for us already.
2328 	 */
2329 	if (!port->uartclk) {
2330 		baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2331 		goto done;
2332 	}
2333 
2334 	for (i = 0; i < SCI_NUM_CLKS; i++)
2335 		max_freq = max(max_freq, s->clk_rates[i]);
2336 
2337 	baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
2338 	if (!baud)
2339 		goto done;
2340 
2341 	/*
2342 	 * There can be multiple sources for the sampling clock.  Find the one
2343 	 * that gives us the smallest deviation from the desired baud rate.
2344 	 */
2345 
2346 	/* Optional Undivided External Clock */
2347 	if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
2348 	    port->type != PORT_SCIFB) {
2349 		err = sci_sck_calc(s, baud, &srr1);
2350 		if (abs(err) < abs(min_err)) {
2351 			best_clk = SCI_SCK;
2352 			scr_val = SCSCR_CKE1;
2353 			sccks = SCCKS_CKS;
2354 			min_err = err;
2355 			srr = srr1;
2356 			if (!err)
2357 				goto done;
2358 		}
2359 	}
2360 
2361 	/* Optional BRG Frequency Divided External Clock */
2362 	if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2363 		err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
2364 				   &srr1);
2365 		if (abs(err) < abs(min_err)) {
2366 			best_clk = SCI_SCIF_CLK;
2367 			scr_val = SCSCR_CKE1;
2368 			sccks = 0;
2369 			min_err = err;
2370 			dl = dl1;
2371 			srr = srr1;
2372 			if (!err)
2373 				goto done;
2374 		}
2375 	}
2376 
2377 	/* Optional BRG Frequency Divided Internal Clock */
2378 	if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2379 		err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
2380 				   &srr1);
2381 		if (abs(err) < abs(min_err)) {
2382 			best_clk = SCI_BRG_INT;
2383 			scr_val = SCSCR_CKE1;
2384 			sccks = SCCKS_XIN;
2385 			min_err = err;
2386 			dl = dl1;
2387 			srr = srr1;
2388 			if (!min_err)
2389 				goto done;
2390 		}
2391 	}
2392 
2393 	/* Divided Functional Clock using standard Bit Rate Register */
2394 	err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2395 	if (abs(err) < abs(min_err)) {
2396 		best_clk = SCI_FCK;
2397 		scr_val = 0;
2398 		min_err = err;
2399 		brr = brr1;
2400 		srr = srr1;
2401 		cks = cks1;
2402 	}
2403 
2404 done:
2405 	if (best_clk >= 0)
2406 		dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2407 			s->clks[best_clk], baud, min_err);
2408 
2409 	sci_port_enable(s);
2410 
2411 	/*
2412 	 * Program the optional External Baud Rate Generator (BRG) first.
2413 	 * It controls the mux to select (H)SCK or frequency divided clock.
2414 	 */
2415 	if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2416 		serial_port_out(port, SCDL, dl);
2417 		serial_port_out(port, SCCKS, sccks);
2418 	}
2419 
2420 	spin_lock_irqsave(&port->lock, flags);
2421 
2422 	sci_reset(port);
2423 
2424 	uart_update_timeout(port, termios->c_cflag, baud);
2425 
2426 	/* byte size and parity */
2427 	switch (termios->c_cflag & CSIZE) {
2428 	case CS5:
2429 		bits = 7;
2430 		break;
2431 	case CS6:
2432 		bits = 8;
2433 		break;
2434 	case CS7:
2435 		bits = 9;
2436 		break;
2437 	default:
2438 		bits = 10;
2439 		break;
2440 	}
2441 
2442 	if (termios->c_cflag & CSTOPB)
2443 		bits++;
2444 	if (termios->c_cflag & PARENB)
2445 		bits++;
2446 
2447 	if (best_clk >= 0) {
2448 		if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
2449 			switch (srr + 1) {
2450 			case 5:  smr_val |= SCSMR_SRC_5;  break;
2451 			case 7:  smr_val |= SCSMR_SRC_7;  break;
2452 			case 11: smr_val |= SCSMR_SRC_11; break;
2453 			case 13: smr_val |= SCSMR_SRC_13; break;
2454 			case 16: smr_val |= SCSMR_SRC_16; break;
2455 			case 17: smr_val |= SCSMR_SRC_17; break;
2456 			case 19: smr_val |= SCSMR_SRC_19; break;
2457 			case 27: smr_val |= SCSMR_SRC_27; break;
2458 			}
2459 		smr_val |= cks;
2460 		serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2461 		serial_port_out(port, SCSMR, smr_val);
2462 		serial_port_out(port, SCBRR, brr);
2463 		if (sci_getreg(port, HSSRR)->size) {
2464 			unsigned int hssrr = srr | HSCIF_SRE;
2465 			/* Calculate deviation from intended rate at the
2466 			 * center of the last stop bit in sampling clocks.
2467 			 */
2468 			int last_stop = bits * 2 - 1;
2469 			int deviation = min_err * srr * last_stop / 2 / baud;
2470 
2471 			if (abs(deviation) >= 2) {
2472 				/* At least two sampling clocks off at the
2473 				 * last stop bit; we can increase the error
2474 				 * margin by shifting the sampling point.
2475 				 */
2476 				int shift = min(-8, max(7, deviation / 2));
2477 
2478 				hssrr |= (shift << HSCIF_SRHP_SHIFT) &
2479 					 HSCIF_SRHP_MASK;
2480 				hssrr |= HSCIF_SRDE;
2481 			}
2482 			serial_port_out(port, HSSRR, hssrr);
2483 		}
2484 
2485 		/* Wait one bit interval */
2486 		udelay((1000000 + (baud - 1)) / baud);
2487 	} else {
2488 		/* Don't touch the bit rate configuration */
2489 		scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
2490 		smr_val |= serial_port_in(port, SCSMR) &
2491 			   (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
2492 		serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2493 		serial_port_out(port, SCSMR, smr_val);
2494 	}
2495 
2496 	sci_init_pins(port, termios->c_cflag);
2497 
2498 	port->status &= ~UPSTAT_AUTOCTS;
2499 	s->autorts = false;
2500 	reg = sci_getreg(port, SCFCR);
2501 	if (reg->size) {
2502 		unsigned short ctrl = serial_port_in(port, SCFCR);
2503 
2504 		if ((port->flags & UPF_HARD_FLOW) &&
2505 		    (termios->c_cflag & CRTSCTS)) {
2506 			/* There is no CTS interrupt to restart the hardware */
2507 			port->status |= UPSTAT_AUTOCTS;
2508 			/* MCE is enabled when RTS is raised */
2509 			s->autorts = true;
2510 		}
2511 
2512 		/*
2513 		 * As we've done a sci_reset() above, ensure we don't
2514 		 * interfere with the FIFOs while toggling MCE. As the
2515 		 * reset values could still be set, simply mask them out.
2516 		 */
2517 		ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2518 
2519 		serial_port_out(port, SCFCR, ctrl);
2520 	}
2521 	if (port->flags & UPF_HARD_FLOW) {
2522 		/* Refresh (Auto) RTS */
2523 		sci_set_mctrl(port, port->mctrl);
2524 	}
2525 
2526 	scr_val |= SCSCR_RE | SCSCR_TE |
2527 		   (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0));
2528 	serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2529 	if ((srr + 1 == 5) &&
2530 	    (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
2531 		/*
2532 		 * In asynchronous mode, when the sampling rate is 1/5, first
2533 		 * received data may become invalid on some SCIFA and SCIFB.
2534 		 * To avoid this problem wait more than 1 serial data time (1
2535 		 * bit time x serial data number) after setting SCSCR.RE = 1.
2536 		 */
2537 		udelay(DIV_ROUND_UP(10 * 1000000, baud));
2538 	}
2539 
2540 	/*
2541 	 * Calculate delay for 2 DMA buffers (4 FIFO).
2542 	 * See serial_core.c::uart_update_timeout().
2543 	 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2544 	 * function calculates 1 jiffie for the data plus 5 jiffies for the
2545 	 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2546 	 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2547 	 * value obtained by this formula is too small. Therefore, if the value
2548 	 * is smaller than 20ms, use 20ms as the timeout value for DMA.
2549 	 */
2550 	s->rx_frame = (10000 * bits) / (baud / 100);
2551 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2552 	s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame;
2553 	if (s->rx_timeout < 20)
2554 		s->rx_timeout = 20;
2555 #endif
2556 
2557 	if ((termios->c_cflag & CREAD) != 0)
2558 		sci_start_rx(port);
2559 
2560 	spin_unlock_irqrestore(&port->lock, flags);
2561 
2562 	sci_port_disable(s);
2563 
2564 	if (UART_ENABLE_MS(port, termios->c_cflag))
2565 		sci_enable_ms(port);
2566 }
2567 
2568 static void sci_pm(struct uart_port *port, unsigned int state,
2569 		   unsigned int oldstate)
2570 {
2571 	struct sci_port *sci_port = to_sci_port(port);
2572 
2573 	switch (state) {
2574 	case UART_PM_STATE_OFF:
2575 		sci_port_disable(sci_port);
2576 		break;
2577 	default:
2578 		sci_port_enable(sci_port);
2579 		break;
2580 	}
2581 }
2582 
2583 static const char *sci_type(struct uart_port *port)
2584 {
2585 	switch (port->type) {
2586 	case PORT_IRDA:
2587 		return "irda";
2588 	case PORT_SCI:
2589 		return "sci";
2590 	case PORT_SCIF:
2591 		return "scif";
2592 	case PORT_SCIFA:
2593 		return "scifa";
2594 	case PORT_SCIFB:
2595 		return "scifb";
2596 	case PORT_HSCIF:
2597 		return "hscif";
2598 	}
2599 
2600 	return NULL;
2601 }
2602 
2603 static int sci_remap_port(struct uart_port *port)
2604 {
2605 	struct sci_port *sport = to_sci_port(port);
2606 
2607 	/*
2608 	 * Nothing to do if there's already an established membase.
2609 	 */
2610 	if (port->membase)
2611 		return 0;
2612 
2613 	if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2614 		port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
2615 		if (unlikely(!port->membase)) {
2616 			dev_err(port->dev, "can't remap port#%d\n", port->line);
2617 			return -ENXIO;
2618 		}
2619 	} else {
2620 		/*
2621 		 * For the simple (and majority of) cases where we don't
2622 		 * need to do any remapping, just cast the cookie
2623 		 * directly.
2624 		 */
2625 		port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2626 	}
2627 
2628 	return 0;
2629 }
2630 
2631 static void sci_release_port(struct uart_port *port)
2632 {
2633 	struct sci_port *sport = to_sci_port(port);
2634 
2635 	if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2636 		iounmap(port->membase);
2637 		port->membase = NULL;
2638 	}
2639 
2640 	release_mem_region(port->mapbase, sport->reg_size);
2641 }
2642 
2643 static int sci_request_port(struct uart_port *port)
2644 {
2645 	struct resource *res;
2646 	struct sci_port *sport = to_sci_port(port);
2647 	int ret;
2648 
2649 	res = request_mem_region(port->mapbase, sport->reg_size,
2650 				 dev_name(port->dev));
2651 	if (unlikely(res == NULL)) {
2652 		dev_err(port->dev, "request_mem_region failed.");
2653 		return -EBUSY;
2654 	}
2655 
2656 	ret = sci_remap_port(port);
2657 	if (unlikely(ret != 0)) {
2658 		release_resource(res);
2659 		return ret;
2660 	}
2661 
2662 	return 0;
2663 }
2664 
2665 static void sci_config_port(struct uart_port *port, int flags)
2666 {
2667 	if (flags & UART_CONFIG_TYPE) {
2668 		struct sci_port *sport = to_sci_port(port);
2669 
2670 		port->type = sport->cfg->type;
2671 		sci_request_port(port);
2672 	}
2673 }
2674 
2675 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2676 {
2677 	if (ser->baud_base < 2400)
2678 		/* No paper tape reader for Mitch.. */
2679 		return -EINVAL;
2680 
2681 	return 0;
2682 }
2683 
2684 static const struct uart_ops sci_uart_ops = {
2685 	.tx_empty	= sci_tx_empty,
2686 	.set_mctrl	= sci_set_mctrl,
2687 	.get_mctrl	= sci_get_mctrl,
2688 	.start_tx	= sci_start_tx,
2689 	.stop_tx	= sci_stop_tx,
2690 	.stop_rx	= sci_stop_rx,
2691 	.enable_ms	= sci_enable_ms,
2692 	.break_ctl	= sci_break_ctl,
2693 	.startup	= sci_startup,
2694 	.shutdown	= sci_shutdown,
2695 	.flush_buffer	= sci_flush_buffer,
2696 	.set_termios	= sci_set_termios,
2697 	.pm		= sci_pm,
2698 	.type		= sci_type,
2699 	.release_port	= sci_release_port,
2700 	.request_port	= sci_request_port,
2701 	.config_port	= sci_config_port,
2702 	.verify_port	= sci_verify_port,
2703 #ifdef CONFIG_CONSOLE_POLL
2704 	.poll_get_char	= sci_poll_get_char,
2705 	.poll_put_char	= sci_poll_put_char,
2706 #endif
2707 };
2708 
2709 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2710 {
2711 	const char *clk_names[] = {
2712 		[SCI_FCK] = "fck",
2713 		[SCI_SCK] = "sck",
2714 		[SCI_BRG_INT] = "brg_int",
2715 		[SCI_SCIF_CLK] = "scif_clk",
2716 	};
2717 	struct clk *clk;
2718 	unsigned int i;
2719 
2720 	if (sci_port->cfg->type == PORT_HSCIF)
2721 		clk_names[SCI_SCK] = "hsck";
2722 
2723 	for (i = 0; i < SCI_NUM_CLKS; i++) {
2724 		clk = devm_clk_get(dev, clk_names[i]);
2725 		if (PTR_ERR(clk) == -EPROBE_DEFER)
2726 			return -EPROBE_DEFER;
2727 
2728 		if (IS_ERR(clk) && i == SCI_FCK) {
2729 			/*
2730 			 * "fck" used to be called "sci_ick", and we need to
2731 			 * maintain DT backward compatibility.
2732 			 */
2733 			clk = devm_clk_get(dev, "sci_ick");
2734 			if (PTR_ERR(clk) == -EPROBE_DEFER)
2735 				return -EPROBE_DEFER;
2736 
2737 			if (!IS_ERR(clk))
2738 				goto found;
2739 
2740 			/*
2741 			 * Not all SH platforms declare a clock lookup entry
2742 			 * for SCI devices, in which case we need to get the
2743 			 * global "peripheral_clk" clock.
2744 			 */
2745 			clk = devm_clk_get(dev, "peripheral_clk");
2746 			if (!IS_ERR(clk))
2747 				goto found;
2748 
2749 			dev_err(dev, "failed to get %s (%ld)\n", clk_names[i],
2750 				PTR_ERR(clk));
2751 			return PTR_ERR(clk);
2752 		}
2753 
2754 found:
2755 		if (IS_ERR(clk))
2756 			dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i],
2757 				PTR_ERR(clk));
2758 		else
2759 			dev_dbg(dev, "clk %s is %pC rate %lu\n", clk_names[i],
2760 				clk, clk_get_rate(clk));
2761 		sci_port->clks[i] = IS_ERR(clk) ? NULL : clk;
2762 	}
2763 	return 0;
2764 }
2765 
2766 static const struct sci_port_params *
2767 sci_probe_regmap(const struct plat_sci_port *cfg)
2768 {
2769 	unsigned int regtype;
2770 
2771 	if (cfg->regtype != SCIx_PROBE_REGTYPE)
2772 		return &sci_port_params[cfg->regtype];
2773 
2774 	switch (cfg->type) {
2775 	case PORT_SCI:
2776 		regtype = SCIx_SCI_REGTYPE;
2777 		break;
2778 	case PORT_IRDA:
2779 		regtype = SCIx_IRDA_REGTYPE;
2780 		break;
2781 	case PORT_SCIFA:
2782 		regtype = SCIx_SCIFA_REGTYPE;
2783 		break;
2784 	case PORT_SCIFB:
2785 		regtype = SCIx_SCIFB_REGTYPE;
2786 		break;
2787 	case PORT_SCIF:
2788 		/*
2789 		 * The SH-4 is a bit of a misnomer here, although that's
2790 		 * where this particular port layout originated. This
2791 		 * configuration (or some slight variation thereof)
2792 		 * remains the dominant model for all SCIFs.
2793 		 */
2794 		regtype = SCIx_SH4_SCIF_REGTYPE;
2795 		break;
2796 	case PORT_HSCIF:
2797 		regtype = SCIx_HSCIF_REGTYPE;
2798 		break;
2799 	default:
2800 		pr_err("Can't probe register map for given port\n");
2801 		return NULL;
2802 	}
2803 
2804 	return &sci_port_params[regtype];
2805 }
2806 
2807 static int sci_init_single(struct platform_device *dev,
2808 			   struct sci_port *sci_port, unsigned int index,
2809 			   const struct plat_sci_port *p, bool early)
2810 {
2811 	struct uart_port *port = &sci_port->port;
2812 	const struct resource *res;
2813 	unsigned int i, regtype;
2814 	int ret;
2815 
2816 	sci_port->cfg	= p;
2817 
2818 	port->ops	= &sci_uart_ops;
2819 	port->iotype	= UPIO_MEM;
2820 	port->line	= index;
2821 
2822 	res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2823 	if (res == NULL)
2824 		return -ENOMEM;
2825 
2826 	port->mapbase = res->start;
2827 	sci_port->reg_size = resource_size(res);
2828 
2829 	for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2830 		sci_port->irqs[i] = platform_get_irq(dev, i);
2831 
2832 	/* The SCI generates several interrupts. They can be muxed together or
2833 	 * connected to different interrupt lines. In the muxed case only one
2834 	 * interrupt resource is specified as there is only one interrupt ID.
2835 	 * In the non-muxed case, up to 6 interrupt signals might be generated
2836 	 * from the SCI, however those signals might have their own individual
2837 	 * interrupt ID numbers, or muxed together with another interrupt.
2838 	 */
2839 	if (sci_port->irqs[0] < 0)
2840 		return -ENXIO;
2841 
2842 	if (sci_port->irqs[1] < 0)
2843 		for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++)
2844 			sci_port->irqs[i] = sci_port->irqs[0];
2845 
2846 	sci_port->params = sci_probe_regmap(p);
2847 	if (unlikely(sci_port->params == NULL))
2848 		return -EINVAL;
2849 
2850 	regtype = sci_port->params - sci_port_params;
2851 	switch (p->type) {
2852 	case PORT_SCIFB:
2853 		sci_port->rx_trigger = 48;
2854 		break;
2855 	case PORT_HSCIF:
2856 		sci_port->rx_trigger = 64;
2857 		break;
2858 	case PORT_SCIFA:
2859 		sci_port->rx_trigger = 32;
2860 		break;
2861 	case PORT_SCIF:
2862 		if (p->regtype == SCIx_SH7705_SCIF_REGTYPE)
2863 			/* RX triggering not implemented for this IP */
2864 			sci_port->rx_trigger = 1;
2865 		else
2866 			sci_port->rx_trigger = 8;
2867 		break;
2868 	default:
2869 		sci_port->rx_trigger = 1;
2870 		break;
2871 	}
2872 
2873 	sci_port->rx_fifo_timeout = 0;
2874 	sci_port->hscif_tot = 0;
2875 
2876 	/* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2877 	 * match the SoC datasheet, this should be investigated. Let platform
2878 	 * data override the sampling rate for now.
2879 	 */
2880 	sci_port->sampling_rate_mask = p->sampling_rate
2881 				     ? SCI_SR(p->sampling_rate)
2882 				     : sci_port->params->sampling_rate_mask;
2883 
2884 	if (!early) {
2885 		ret = sci_init_clocks(sci_port, &dev->dev);
2886 		if (ret < 0)
2887 			return ret;
2888 
2889 		port->dev = &dev->dev;
2890 
2891 		pm_runtime_enable(&dev->dev);
2892 	}
2893 
2894 	port->type		= p->type;
2895 	port->flags		= UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags;
2896 	port->fifosize		= sci_port->params->fifosize;
2897 
2898 	if (port->type == PORT_SCI) {
2899 		if (sci_port->reg_size >= 0x20)
2900 			port->regshift = 2;
2901 		else
2902 			port->regshift = 1;
2903 	}
2904 
2905 	if (regtype == SCIx_SH4_SCIF_REGTYPE)
2906 		if (sci_port->reg_size >= 0x20)
2907 			port->regshift = 1;
2908 
2909 	/*
2910 	 * The UART port needs an IRQ value, so we peg this to the RX IRQ
2911 	 * for the multi-IRQ ports, which is where we are primarily
2912 	 * concerned with the shutdown path synchronization.
2913 	 *
2914 	 * For the muxed case there's nothing more to do.
2915 	 */
2916 	port->irq		= sci_port->irqs[SCIx_RXI_IRQ];
2917 	port->irqflags		= 0;
2918 
2919 	port->serial_in		= sci_serial_in;
2920 	port->serial_out	= sci_serial_out;
2921 
2922 	return 0;
2923 }
2924 
2925 static void sci_cleanup_single(struct sci_port *port)
2926 {
2927 	pm_runtime_disable(port->port.dev);
2928 }
2929 
2930 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
2931     defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
2932 static void serial_console_putchar(struct uart_port *port, int ch)
2933 {
2934 	sci_poll_put_char(port, ch);
2935 }
2936 
2937 /*
2938  *	Print a string to the serial port trying not to disturb
2939  *	any possible real use of the port...
2940  */
2941 static void serial_console_write(struct console *co, const char *s,
2942 				 unsigned count)
2943 {
2944 	struct sci_port *sci_port = &sci_ports[co->index];
2945 	struct uart_port *port = &sci_port->port;
2946 	unsigned short bits, ctrl, ctrl_temp;
2947 	unsigned long flags;
2948 	int locked = 1;
2949 
2950 #if defined(SUPPORT_SYSRQ)
2951 	if (port->sysrq)
2952 		locked = 0;
2953 	else
2954 #endif
2955 	if (oops_in_progress)
2956 		locked = spin_trylock_irqsave(&port->lock, flags);
2957 	else
2958 		spin_lock_irqsave(&port->lock, flags);
2959 
2960 	/* first save SCSCR then disable interrupts, keep clock source */
2961 	ctrl = serial_port_in(port, SCSCR);
2962 	ctrl_temp = SCSCR_RE | SCSCR_TE |
2963 		    (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
2964 		    (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
2965 	serial_port_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot);
2966 
2967 	uart_console_write(port, s, count, serial_console_putchar);
2968 
2969 	/* wait until fifo is empty and last bit has been transmitted */
2970 	bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
2971 	while ((serial_port_in(port, SCxSR) & bits) != bits)
2972 		cpu_relax();
2973 
2974 	/* restore the SCSCR */
2975 	serial_port_out(port, SCSCR, ctrl);
2976 
2977 	if (locked)
2978 		spin_unlock_irqrestore(&port->lock, flags);
2979 }
2980 
2981 static int serial_console_setup(struct console *co, char *options)
2982 {
2983 	struct sci_port *sci_port;
2984 	struct uart_port *port;
2985 	int baud = 115200;
2986 	int bits = 8;
2987 	int parity = 'n';
2988 	int flow = 'n';
2989 	int ret;
2990 
2991 	/*
2992 	 * Refuse to handle any bogus ports.
2993 	 */
2994 	if (co->index < 0 || co->index >= SCI_NPORTS)
2995 		return -ENODEV;
2996 
2997 	sci_port = &sci_ports[co->index];
2998 	port = &sci_port->port;
2999 
3000 	/*
3001 	 * Refuse to handle uninitialized ports.
3002 	 */
3003 	if (!port->ops)
3004 		return -ENODEV;
3005 
3006 	ret = sci_remap_port(port);
3007 	if (unlikely(ret != 0))
3008 		return ret;
3009 
3010 	if (options)
3011 		uart_parse_options(options, &baud, &parity, &bits, &flow);
3012 
3013 	return uart_set_options(port, co, baud, parity, bits, flow);
3014 }
3015 
3016 static struct console serial_console = {
3017 	.name		= "ttySC",
3018 	.device		= uart_console_device,
3019 	.write		= serial_console_write,
3020 	.setup		= serial_console_setup,
3021 	.flags		= CON_PRINTBUFFER,
3022 	.index		= -1,
3023 	.data		= &sci_uart_driver,
3024 };
3025 
3026 static struct console early_serial_console = {
3027 	.name           = "early_ttySC",
3028 	.write          = serial_console_write,
3029 	.flags          = CON_PRINTBUFFER,
3030 	.index		= -1,
3031 };
3032 
3033 static char early_serial_buf[32];
3034 
3035 static int sci_probe_earlyprintk(struct platform_device *pdev)
3036 {
3037 	const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
3038 
3039 	if (early_serial_console.data)
3040 		return -EEXIST;
3041 
3042 	early_serial_console.index = pdev->id;
3043 
3044 	sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
3045 
3046 	serial_console_setup(&early_serial_console, early_serial_buf);
3047 
3048 	if (!strstr(early_serial_buf, "keep"))
3049 		early_serial_console.flags |= CON_BOOT;
3050 
3051 	register_console(&early_serial_console);
3052 	return 0;
3053 }
3054 
3055 #define SCI_CONSOLE	(&serial_console)
3056 
3057 #else
3058 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
3059 {
3060 	return -EINVAL;
3061 }
3062 
3063 #define SCI_CONSOLE	NULL
3064 
3065 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */
3066 
3067 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
3068 
3069 static DEFINE_MUTEX(sci_uart_registration_lock);
3070 static struct uart_driver sci_uart_driver = {
3071 	.owner		= THIS_MODULE,
3072 	.driver_name	= "sci",
3073 	.dev_name	= "ttySC",
3074 	.major		= SCI_MAJOR,
3075 	.minor		= SCI_MINOR_START,
3076 	.nr		= SCI_NPORTS,
3077 	.cons		= SCI_CONSOLE,
3078 };
3079 
3080 static int sci_remove(struct platform_device *dev)
3081 {
3082 	struct sci_port *port = platform_get_drvdata(dev);
3083 
3084 	sci_ports_in_use &= ~BIT(port->port.line);
3085 	uart_remove_one_port(&sci_uart_driver, &port->port);
3086 
3087 	sci_cleanup_single(port);
3088 
3089 	if (port->port.fifosize > 1) {
3090 		sysfs_remove_file(&dev->dev.kobj,
3091 				  &dev_attr_rx_fifo_trigger.attr);
3092 	}
3093 	if (port->port.type == PORT_SCIFA || port->port.type == PORT_SCIFB ||
3094 	    port->port.type == PORT_HSCIF) {
3095 		sysfs_remove_file(&dev->dev.kobj,
3096 				  &dev_attr_rx_fifo_timeout.attr);
3097 	}
3098 
3099 	return 0;
3100 }
3101 
3102 
3103 #define SCI_OF_DATA(type, regtype)	(void *)((type) << 16 | (regtype))
3104 #define SCI_OF_TYPE(data)		((unsigned long)(data) >> 16)
3105 #define SCI_OF_REGTYPE(data)		((unsigned long)(data) & 0xffff)
3106 
3107 static const struct of_device_id of_sci_match[] = {
3108 	/* SoC-specific types */
3109 	{
3110 		.compatible = "renesas,scif-r7s72100",
3111 		.data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
3112 	},
3113 	/* Family-specific types */
3114 	{
3115 		.compatible = "renesas,rcar-gen1-scif",
3116 		.data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3117 	}, {
3118 		.compatible = "renesas,rcar-gen2-scif",
3119 		.data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3120 	}, {
3121 		.compatible = "renesas,rcar-gen3-scif",
3122 		.data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3123 	},
3124 	/* Generic types */
3125 	{
3126 		.compatible = "renesas,scif",
3127 		.data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
3128 	}, {
3129 		.compatible = "renesas,scifa",
3130 		.data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
3131 	}, {
3132 		.compatible = "renesas,scifb",
3133 		.data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
3134 	}, {
3135 		.compatible = "renesas,hscif",
3136 		.data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
3137 	}, {
3138 		.compatible = "renesas,sci",
3139 		.data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
3140 	}, {
3141 		/* Terminator */
3142 	},
3143 };
3144 MODULE_DEVICE_TABLE(of, of_sci_match);
3145 
3146 static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
3147 					  unsigned int *dev_id)
3148 {
3149 	struct device_node *np = pdev->dev.of_node;
3150 	struct plat_sci_port *p;
3151 	struct sci_port *sp;
3152 	const void *data;
3153 	int id;
3154 
3155 	if (!IS_ENABLED(CONFIG_OF) || !np)
3156 		return NULL;
3157 
3158 	data = of_device_get_match_data(&pdev->dev);
3159 
3160 	p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
3161 	if (!p)
3162 		return NULL;
3163 
3164 	/* Get the line number from the aliases node. */
3165 	id = of_alias_get_id(np, "serial");
3166 	if (id < 0 && ~sci_ports_in_use)
3167 		id = ffz(sci_ports_in_use);
3168 	if (id < 0) {
3169 		dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
3170 		return NULL;
3171 	}
3172 	if (id >= ARRAY_SIZE(sci_ports)) {
3173 		dev_err(&pdev->dev, "serial%d out of range\n", id);
3174 		return NULL;
3175 	}
3176 
3177 	sp = &sci_ports[id];
3178 	*dev_id = id;
3179 
3180 	p->type = SCI_OF_TYPE(data);
3181 	p->regtype = SCI_OF_REGTYPE(data);
3182 
3183 	sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts");
3184 
3185 	return p;
3186 }
3187 
3188 static int sci_probe_single(struct platform_device *dev,
3189 				      unsigned int index,
3190 				      struct plat_sci_port *p,
3191 				      struct sci_port *sciport)
3192 {
3193 	int ret;
3194 
3195 	/* Sanity check */
3196 	if (unlikely(index >= SCI_NPORTS)) {
3197 		dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
3198 			   index+1, SCI_NPORTS);
3199 		dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
3200 		return -EINVAL;
3201 	}
3202 	BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8);
3203 	if (sci_ports_in_use & BIT(index))
3204 		return -EBUSY;
3205 
3206 	mutex_lock(&sci_uart_registration_lock);
3207 	if (!sci_uart_driver.state) {
3208 		ret = uart_register_driver(&sci_uart_driver);
3209 		if (ret) {
3210 			mutex_unlock(&sci_uart_registration_lock);
3211 			return ret;
3212 		}
3213 	}
3214 	mutex_unlock(&sci_uart_registration_lock);
3215 
3216 	ret = sci_init_single(dev, sciport, index, p, false);
3217 	if (ret)
3218 		return ret;
3219 
3220 	sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
3221 	if (IS_ERR(sciport->gpios) && PTR_ERR(sciport->gpios) != -ENOSYS)
3222 		return PTR_ERR(sciport->gpios);
3223 
3224 	if (sciport->has_rtscts) {
3225 		if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
3226 							UART_GPIO_CTS)) ||
3227 		    !IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
3228 							UART_GPIO_RTS))) {
3229 			dev_err(&dev->dev, "Conflicting RTS/CTS config\n");
3230 			return -EINVAL;
3231 		}
3232 		sciport->port.flags |= UPF_HARD_FLOW;
3233 	}
3234 
3235 	ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
3236 	if (ret) {
3237 		sci_cleanup_single(sciport);
3238 		return ret;
3239 	}
3240 
3241 	return 0;
3242 }
3243 
3244 static int sci_probe(struct platform_device *dev)
3245 {
3246 	struct plat_sci_port *p;
3247 	struct sci_port *sp;
3248 	unsigned int dev_id;
3249 	int ret;
3250 
3251 	/*
3252 	 * If we've come here via earlyprintk initialization, head off to
3253 	 * the special early probe. We don't have sufficient device state
3254 	 * to make it beyond this yet.
3255 	 */
3256 	if (is_early_platform_device(dev))
3257 		return sci_probe_earlyprintk(dev);
3258 
3259 	if (dev->dev.of_node) {
3260 		p = sci_parse_dt(dev, &dev_id);
3261 		if (p == NULL)
3262 			return -EINVAL;
3263 	} else {
3264 		p = dev->dev.platform_data;
3265 		if (p == NULL) {
3266 			dev_err(&dev->dev, "no platform data supplied\n");
3267 			return -EINVAL;
3268 		}
3269 
3270 		dev_id = dev->id;
3271 	}
3272 
3273 	sp = &sci_ports[dev_id];
3274 	platform_set_drvdata(dev, sp);
3275 
3276 	ret = sci_probe_single(dev, dev_id, p, sp);
3277 	if (ret)
3278 		return ret;
3279 
3280 	if (sp->port.fifosize > 1) {
3281 		ret = sysfs_create_file(&dev->dev.kobj,
3282 				&dev_attr_rx_fifo_trigger.attr);
3283 		if (ret)
3284 			return ret;
3285 	}
3286 	if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB ||
3287 	    sp->port.type == PORT_HSCIF) {
3288 		ret = sysfs_create_file(&dev->dev.kobj,
3289 				&dev_attr_rx_fifo_timeout.attr);
3290 		if (ret) {
3291 			if (sp->port.fifosize > 1) {
3292 				sysfs_remove_file(&dev->dev.kobj,
3293 					&dev_attr_rx_fifo_trigger.attr);
3294 			}
3295 			return ret;
3296 		}
3297 	}
3298 
3299 #ifdef CONFIG_SH_STANDARD_BIOS
3300 	sh_bios_gdb_detach();
3301 #endif
3302 
3303 	sci_ports_in_use |= BIT(dev_id);
3304 	return 0;
3305 }
3306 
3307 static __maybe_unused int sci_suspend(struct device *dev)
3308 {
3309 	struct sci_port *sport = dev_get_drvdata(dev);
3310 
3311 	if (sport)
3312 		uart_suspend_port(&sci_uart_driver, &sport->port);
3313 
3314 	return 0;
3315 }
3316 
3317 static __maybe_unused int sci_resume(struct device *dev)
3318 {
3319 	struct sci_port *sport = dev_get_drvdata(dev);
3320 
3321 	if (sport)
3322 		uart_resume_port(&sci_uart_driver, &sport->port);
3323 
3324 	return 0;
3325 }
3326 
3327 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
3328 
3329 static struct platform_driver sci_driver = {
3330 	.probe		= sci_probe,
3331 	.remove		= sci_remove,
3332 	.driver		= {
3333 		.name	= "sh-sci",
3334 		.pm	= &sci_dev_pm_ops,
3335 		.of_match_table = of_match_ptr(of_sci_match),
3336 	},
3337 };
3338 
3339 static int __init sci_init(void)
3340 {
3341 	pr_info("%s\n", banner);
3342 
3343 	return platform_driver_register(&sci_driver);
3344 }
3345 
3346 static void __exit sci_exit(void)
3347 {
3348 	platform_driver_unregister(&sci_driver);
3349 
3350 	if (sci_uart_driver.state)
3351 		uart_unregister_driver(&sci_uart_driver);
3352 }
3353 
3354 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
3355 early_platform_init_buffer("earlyprintk", &sci_driver,
3356 			   early_serial_buf, ARRAY_SIZE(early_serial_buf));
3357 #endif
3358 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
3359 static struct plat_sci_port port_cfg __initdata;
3360 
3361 static int __init early_console_setup(struct earlycon_device *device,
3362 				      int type)
3363 {
3364 	if (!device->port.membase)
3365 		return -ENODEV;
3366 
3367 	device->port.serial_in = sci_serial_in;
3368 	device->port.serial_out	= sci_serial_out;
3369 	device->port.type = type;
3370 	memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
3371 	port_cfg.type = type;
3372 	sci_ports[0].cfg = &port_cfg;
3373 	sci_ports[0].params = sci_probe_regmap(&port_cfg);
3374 	port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR);
3375 	sci_serial_out(&sci_ports[0].port, SCSCR,
3376 		       SCSCR_RE | SCSCR_TE | port_cfg.scscr);
3377 
3378 	device->con->write = serial_console_write;
3379 	return 0;
3380 }
3381 static int __init sci_early_console_setup(struct earlycon_device *device,
3382 					  const char *opt)
3383 {
3384 	return early_console_setup(device, PORT_SCI);
3385 }
3386 static int __init scif_early_console_setup(struct earlycon_device *device,
3387 					  const char *opt)
3388 {
3389 	return early_console_setup(device, PORT_SCIF);
3390 }
3391 static int __init scifa_early_console_setup(struct earlycon_device *device,
3392 					  const char *opt)
3393 {
3394 	return early_console_setup(device, PORT_SCIFA);
3395 }
3396 static int __init scifb_early_console_setup(struct earlycon_device *device,
3397 					  const char *opt)
3398 {
3399 	return early_console_setup(device, PORT_SCIFB);
3400 }
3401 static int __init hscif_early_console_setup(struct earlycon_device *device,
3402 					  const char *opt)
3403 {
3404 	return early_console_setup(device, PORT_HSCIF);
3405 }
3406 
3407 OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
3408 OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
3409 OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
3410 OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
3411 OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
3412 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
3413 
3414 module_init(sci_init);
3415 module_exit(sci_exit);
3416 
3417 MODULE_LICENSE("GPL");
3418 MODULE_ALIAS("platform:sh-sci");
3419 MODULE_AUTHOR("Paul Mundt");
3420 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
3421