1 /* 2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) 3 * 4 * Copyright (C) 2002 - 2011 Paul Mundt 5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007). 6 * 7 * based off of the old drivers/char/sh-sci.c by: 8 * 9 * Copyright (C) 1999, 2000 Niibe Yutaka 10 * Copyright (C) 2000 Sugioka Toshinobu 11 * Modified to support multiple serial ports. Stuart Menefy (May 2000). 12 * Modified to support SecureEdge. David McCullough (2002) 13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003). 14 * Removed SH7300 support (Jul 2007). 15 * 16 * This file is subject to the terms and conditions of the GNU General Public 17 * License. See the file "COPYING" in the main directory of this archive 18 * for more details. 19 */ 20 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 21 #define SUPPORT_SYSRQ 22 #endif 23 24 #undef DEBUG 25 26 #include <linux/module.h> 27 #include <linux/errno.h> 28 #include <linux/timer.h> 29 #include <linux/interrupt.h> 30 #include <linux/tty.h> 31 #include <linux/tty_flip.h> 32 #include <linux/serial.h> 33 #include <linux/major.h> 34 #include <linux/string.h> 35 #include <linux/sysrq.h> 36 #include <linux/ioport.h> 37 #include <linux/mm.h> 38 #include <linux/init.h> 39 #include <linux/delay.h> 40 #include <linux/console.h> 41 #include <linux/platform_device.h> 42 #include <linux/serial_sci.h> 43 #include <linux/notifier.h> 44 #include <linux/pm_runtime.h> 45 #include <linux/cpufreq.h> 46 #include <linux/clk.h> 47 #include <linux/ctype.h> 48 #include <linux/err.h> 49 #include <linux/dmaengine.h> 50 #include <linux/dma-mapping.h> 51 #include <linux/scatterlist.h> 52 #include <linux/slab.h> 53 #include <linux/gpio.h> 54 55 #ifdef CONFIG_SUPERH 56 #include <asm/sh_bios.h> 57 #endif 58 59 #include "sh-sci.h" 60 61 struct sci_port { 62 struct uart_port port; 63 64 /* Platform configuration */ 65 struct plat_sci_port *cfg; 66 67 /* Break timer */ 68 struct timer_list break_timer; 69 int break_flag; 70 71 /* Interface clock */ 72 struct clk *iclk; 73 /* Function clock */ 74 struct clk *fclk; 75 76 char *irqstr[SCIx_NR_IRQS]; 77 char *gpiostr[SCIx_NR_FNS]; 78 79 struct dma_chan *chan_tx; 80 struct dma_chan *chan_rx; 81 82 #ifdef CONFIG_SERIAL_SH_SCI_DMA 83 struct dma_async_tx_descriptor *desc_tx; 84 struct dma_async_tx_descriptor *desc_rx[2]; 85 dma_cookie_t cookie_tx; 86 dma_cookie_t cookie_rx[2]; 87 dma_cookie_t active_rx; 88 struct scatterlist sg_tx; 89 unsigned int sg_len_tx; 90 struct scatterlist sg_rx[2]; 91 size_t buf_len_rx; 92 struct sh_dmae_slave param_tx; 93 struct sh_dmae_slave param_rx; 94 struct work_struct work_tx; 95 struct work_struct work_rx; 96 struct timer_list rx_timer; 97 unsigned int rx_timeout; 98 #endif 99 100 struct notifier_block freq_transition; 101 102 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE 103 unsigned short saved_smr; 104 unsigned short saved_fcr; 105 unsigned char saved_brr; 106 #endif 107 }; 108 109 /* Function prototypes */ 110 static void sci_start_tx(struct uart_port *port); 111 static void sci_stop_tx(struct uart_port *port); 112 static void sci_start_rx(struct uart_port *port); 113 114 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS 115 116 static struct sci_port sci_ports[SCI_NPORTS]; 117 static struct uart_driver sci_uart_driver; 118 119 static inline struct sci_port * 120 to_sci_port(struct uart_port *uart) 121 { 122 return container_of(uart, struct sci_port, port); 123 } 124 125 struct plat_sci_reg { 126 u8 offset, size; 127 }; 128 129 /* Helper for invalidating specific entries of an inherited map. */ 130 #define sci_reg_invalid { .offset = 0, .size = 0 } 131 132 static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { 133 [SCIx_PROBE_REGTYPE] = { 134 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid, 135 }, 136 137 /* 138 * Common SCI definitions, dependent on the port's regshift 139 * value. 140 */ 141 [SCIx_SCI_REGTYPE] = { 142 [SCSMR] = { 0x00, 8 }, 143 [SCBRR] = { 0x01, 8 }, 144 [SCSCR] = { 0x02, 8 }, 145 [SCxTDR] = { 0x03, 8 }, 146 [SCxSR] = { 0x04, 8 }, 147 [SCxRDR] = { 0x05, 8 }, 148 [SCFCR] = sci_reg_invalid, 149 [SCFDR] = sci_reg_invalid, 150 [SCTFDR] = sci_reg_invalid, 151 [SCRFDR] = sci_reg_invalid, 152 [SCSPTR] = sci_reg_invalid, 153 [SCLSR] = sci_reg_invalid, 154 }, 155 156 /* 157 * Common definitions for legacy IrDA ports, dependent on 158 * regshift value. 159 */ 160 [SCIx_IRDA_REGTYPE] = { 161 [SCSMR] = { 0x00, 8 }, 162 [SCBRR] = { 0x01, 8 }, 163 [SCSCR] = { 0x02, 8 }, 164 [SCxTDR] = { 0x03, 8 }, 165 [SCxSR] = { 0x04, 8 }, 166 [SCxRDR] = { 0x05, 8 }, 167 [SCFCR] = { 0x06, 8 }, 168 [SCFDR] = { 0x07, 16 }, 169 [SCTFDR] = sci_reg_invalid, 170 [SCRFDR] = sci_reg_invalid, 171 [SCSPTR] = sci_reg_invalid, 172 [SCLSR] = sci_reg_invalid, 173 }, 174 175 /* 176 * Common SCIFA definitions. 177 */ 178 [SCIx_SCIFA_REGTYPE] = { 179 [SCSMR] = { 0x00, 16 }, 180 [SCBRR] = { 0x04, 8 }, 181 [SCSCR] = { 0x08, 16 }, 182 [SCxTDR] = { 0x20, 8 }, 183 [SCxSR] = { 0x14, 16 }, 184 [SCxRDR] = { 0x24, 8 }, 185 [SCFCR] = { 0x18, 16 }, 186 [SCFDR] = { 0x1c, 16 }, 187 [SCTFDR] = sci_reg_invalid, 188 [SCRFDR] = sci_reg_invalid, 189 [SCSPTR] = sci_reg_invalid, 190 [SCLSR] = sci_reg_invalid, 191 }, 192 193 /* 194 * Common SCIFB definitions. 195 */ 196 [SCIx_SCIFB_REGTYPE] = { 197 [SCSMR] = { 0x00, 16 }, 198 [SCBRR] = { 0x04, 8 }, 199 [SCSCR] = { 0x08, 16 }, 200 [SCxTDR] = { 0x40, 8 }, 201 [SCxSR] = { 0x14, 16 }, 202 [SCxRDR] = { 0x60, 8 }, 203 [SCFCR] = { 0x18, 16 }, 204 [SCFDR] = { 0x1c, 16 }, 205 [SCTFDR] = sci_reg_invalid, 206 [SCRFDR] = sci_reg_invalid, 207 [SCSPTR] = sci_reg_invalid, 208 [SCLSR] = sci_reg_invalid, 209 }, 210 211 /* 212 * Common SH-2(A) SCIF definitions for ports with FIFO data 213 * count registers. 214 */ 215 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = { 216 [SCSMR] = { 0x00, 16 }, 217 [SCBRR] = { 0x04, 8 }, 218 [SCSCR] = { 0x08, 16 }, 219 [SCxTDR] = { 0x0c, 8 }, 220 [SCxSR] = { 0x10, 16 }, 221 [SCxRDR] = { 0x14, 8 }, 222 [SCFCR] = { 0x18, 16 }, 223 [SCFDR] = { 0x1c, 16 }, 224 [SCTFDR] = sci_reg_invalid, 225 [SCRFDR] = sci_reg_invalid, 226 [SCSPTR] = { 0x20, 16 }, 227 [SCLSR] = { 0x24, 16 }, 228 }, 229 230 /* 231 * Common SH-3 SCIF definitions. 232 */ 233 [SCIx_SH3_SCIF_REGTYPE] = { 234 [SCSMR] = { 0x00, 8 }, 235 [SCBRR] = { 0x02, 8 }, 236 [SCSCR] = { 0x04, 8 }, 237 [SCxTDR] = { 0x06, 8 }, 238 [SCxSR] = { 0x08, 16 }, 239 [SCxRDR] = { 0x0a, 8 }, 240 [SCFCR] = { 0x0c, 8 }, 241 [SCFDR] = { 0x0e, 16 }, 242 [SCTFDR] = sci_reg_invalid, 243 [SCRFDR] = sci_reg_invalid, 244 [SCSPTR] = sci_reg_invalid, 245 [SCLSR] = sci_reg_invalid, 246 }, 247 248 /* 249 * Common SH-4(A) SCIF(B) definitions. 250 */ 251 [SCIx_SH4_SCIF_REGTYPE] = { 252 [SCSMR] = { 0x00, 16 }, 253 [SCBRR] = { 0x04, 8 }, 254 [SCSCR] = { 0x08, 16 }, 255 [SCxTDR] = { 0x0c, 8 }, 256 [SCxSR] = { 0x10, 16 }, 257 [SCxRDR] = { 0x14, 8 }, 258 [SCFCR] = { 0x18, 16 }, 259 [SCFDR] = { 0x1c, 16 }, 260 [SCTFDR] = sci_reg_invalid, 261 [SCRFDR] = sci_reg_invalid, 262 [SCSPTR] = { 0x20, 16 }, 263 [SCLSR] = { 0x24, 16 }, 264 }, 265 266 /* 267 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR 268 * register. 269 */ 270 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = { 271 [SCSMR] = { 0x00, 16 }, 272 [SCBRR] = { 0x04, 8 }, 273 [SCSCR] = { 0x08, 16 }, 274 [SCxTDR] = { 0x0c, 8 }, 275 [SCxSR] = { 0x10, 16 }, 276 [SCxRDR] = { 0x14, 8 }, 277 [SCFCR] = { 0x18, 16 }, 278 [SCFDR] = { 0x1c, 16 }, 279 [SCTFDR] = sci_reg_invalid, 280 [SCRFDR] = sci_reg_invalid, 281 [SCSPTR] = sci_reg_invalid, 282 [SCLSR] = { 0x24, 16 }, 283 }, 284 285 /* 286 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data 287 * count registers. 288 */ 289 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = { 290 [SCSMR] = { 0x00, 16 }, 291 [SCBRR] = { 0x04, 8 }, 292 [SCSCR] = { 0x08, 16 }, 293 [SCxTDR] = { 0x0c, 8 }, 294 [SCxSR] = { 0x10, 16 }, 295 [SCxRDR] = { 0x14, 8 }, 296 [SCFCR] = { 0x18, 16 }, 297 [SCFDR] = { 0x1c, 16 }, 298 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */ 299 [SCRFDR] = { 0x20, 16 }, 300 [SCSPTR] = { 0x24, 16 }, 301 [SCLSR] = { 0x28, 16 }, 302 }, 303 304 /* 305 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR 306 * registers. 307 */ 308 [SCIx_SH7705_SCIF_REGTYPE] = { 309 [SCSMR] = { 0x00, 16 }, 310 [SCBRR] = { 0x04, 8 }, 311 [SCSCR] = { 0x08, 16 }, 312 [SCxTDR] = { 0x20, 8 }, 313 [SCxSR] = { 0x14, 16 }, 314 [SCxRDR] = { 0x24, 8 }, 315 [SCFCR] = { 0x18, 16 }, 316 [SCFDR] = { 0x1c, 16 }, 317 [SCTFDR] = sci_reg_invalid, 318 [SCRFDR] = sci_reg_invalid, 319 [SCSPTR] = sci_reg_invalid, 320 [SCLSR] = sci_reg_invalid, 321 }, 322 }; 323 324 #define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset) 325 326 /* 327 * The "offset" here is rather misleading, in that it refers to an enum 328 * value relative to the port mapping rather than the fixed offset 329 * itself, which needs to be manually retrieved from the platform's 330 * register map for the given port. 331 */ 332 static unsigned int sci_serial_in(struct uart_port *p, int offset) 333 { 334 struct plat_sci_reg *reg = sci_getreg(p, offset); 335 336 if (reg->size == 8) 337 return ioread8(p->membase + (reg->offset << p->regshift)); 338 else if (reg->size == 16) 339 return ioread16(p->membase + (reg->offset << p->regshift)); 340 else 341 WARN(1, "Invalid register access\n"); 342 343 return 0; 344 } 345 346 static void sci_serial_out(struct uart_port *p, int offset, int value) 347 { 348 struct plat_sci_reg *reg = sci_getreg(p, offset); 349 350 if (reg->size == 8) 351 iowrite8(value, p->membase + (reg->offset << p->regshift)); 352 else if (reg->size == 16) 353 iowrite16(value, p->membase + (reg->offset << p->regshift)); 354 else 355 WARN(1, "Invalid register access\n"); 356 } 357 358 static int sci_probe_regmap(struct plat_sci_port *cfg) 359 { 360 switch (cfg->type) { 361 case PORT_SCI: 362 cfg->regtype = SCIx_SCI_REGTYPE; 363 break; 364 case PORT_IRDA: 365 cfg->regtype = SCIx_IRDA_REGTYPE; 366 break; 367 case PORT_SCIFA: 368 cfg->regtype = SCIx_SCIFA_REGTYPE; 369 break; 370 case PORT_SCIFB: 371 cfg->regtype = SCIx_SCIFB_REGTYPE; 372 break; 373 case PORT_SCIF: 374 /* 375 * The SH-4 is a bit of a misnomer here, although that's 376 * where this particular port layout originated. This 377 * configuration (or some slight variation thereof) 378 * remains the dominant model for all SCIFs. 379 */ 380 cfg->regtype = SCIx_SH4_SCIF_REGTYPE; 381 break; 382 default: 383 printk(KERN_ERR "Can't probe register map for given port\n"); 384 return -EINVAL; 385 } 386 387 return 0; 388 } 389 390 static void sci_port_enable(struct sci_port *sci_port) 391 { 392 if (!sci_port->port.dev) 393 return; 394 395 pm_runtime_get_sync(sci_port->port.dev); 396 397 clk_enable(sci_port->iclk); 398 sci_port->port.uartclk = clk_get_rate(sci_port->iclk); 399 clk_enable(sci_port->fclk); 400 } 401 402 static void sci_port_disable(struct sci_port *sci_port) 403 { 404 if (!sci_port->port.dev) 405 return; 406 407 clk_disable(sci_port->fclk); 408 clk_disable(sci_port->iclk); 409 410 pm_runtime_put_sync(sci_port->port.dev); 411 } 412 413 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) 414 415 #ifdef CONFIG_CONSOLE_POLL 416 static int sci_poll_get_char(struct uart_port *port) 417 { 418 unsigned short status; 419 int c; 420 421 do { 422 status = serial_port_in(port, SCxSR); 423 if (status & SCxSR_ERRORS(port)) { 424 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port)); 425 continue; 426 } 427 break; 428 } while (1); 429 430 if (!(status & SCxSR_RDxF(port))) 431 return NO_POLL_CHAR; 432 433 c = serial_port_in(port, SCxRDR); 434 435 /* Dummy read */ 436 serial_port_in(port, SCxSR); 437 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); 438 439 return c; 440 } 441 #endif 442 443 static void sci_poll_put_char(struct uart_port *port, unsigned char c) 444 { 445 unsigned short status; 446 447 do { 448 status = serial_port_in(port, SCxSR); 449 } while (!(status & SCxSR_TDxE(port))); 450 451 serial_port_out(port, SCxTDR, c); 452 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port)); 453 } 454 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */ 455 456 static void sci_init_pins(struct uart_port *port, unsigned int cflag) 457 { 458 struct sci_port *s = to_sci_port(port); 459 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR; 460 461 /* 462 * Use port-specific handler if provided. 463 */ 464 if (s->cfg->ops && s->cfg->ops->init_pins) { 465 s->cfg->ops->init_pins(port, cflag); 466 return; 467 } 468 469 /* 470 * For the generic path SCSPTR is necessary. Bail out if that's 471 * unavailable, too. 472 */ 473 if (!reg->size) 474 return; 475 476 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) && 477 ((!(cflag & CRTSCTS)))) { 478 unsigned short status; 479 480 status = serial_port_in(port, SCSPTR); 481 status &= ~SCSPTR_CTSIO; 482 status |= SCSPTR_RTSIO; 483 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */ 484 } 485 } 486 487 static int sci_txfill(struct uart_port *port) 488 { 489 struct plat_sci_reg *reg; 490 491 reg = sci_getreg(port, SCTFDR); 492 if (reg->size) 493 return serial_port_in(port, SCTFDR) & 0xff; 494 495 reg = sci_getreg(port, SCFDR); 496 if (reg->size) 497 return serial_port_in(port, SCFDR) >> 8; 498 499 return !(serial_port_in(port, SCxSR) & SCI_TDRE); 500 } 501 502 static int sci_txroom(struct uart_port *port) 503 { 504 return port->fifosize - sci_txfill(port); 505 } 506 507 static int sci_rxfill(struct uart_port *port) 508 { 509 struct plat_sci_reg *reg; 510 511 reg = sci_getreg(port, SCRFDR); 512 if (reg->size) 513 return serial_port_in(port, SCRFDR) & 0xff; 514 515 reg = sci_getreg(port, SCFDR); 516 if (reg->size) 517 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1); 518 519 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0; 520 } 521 522 /* 523 * SCI helper for checking the state of the muxed port/RXD pins. 524 */ 525 static inline int sci_rxd_in(struct uart_port *port) 526 { 527 struct sci_port *s = to_sci_port(port); 528 529 if (s->cfg->port_reg <= 0) 530 return 1; 531 532 return !!__raw_readb(s->cfg->port_reg); 533 } 534 535 /* ********************************************************************** * 536 * the interrupt related routines * 537 * ********************************************************************** */ 538 539 static void sci_transmit_chars(struct uart_port *port) 540 { 541 struct circ_buf *xmit = &port->state->xmit; 542 unsigned int stopped = uart_tx_stopped(port); 543 unsigned short status; 544 unsigned short ctrl; 545 int count; 546 547 status = serial_port_in(port, SCxSR); 548 if (!(status & SCxSR_TDxE(port))) { 549 ctrl = serial_port_in(port, SCSCR); 550 if (uart_circ_empty(xmit)) 551 ctrl &= ~SCSCR_TIE; 552 else 553 ctrl |= SCSCR_TIE; 554 serial_port_out(port, SCSCR, ctrl); 555 return; 556 } 557 558 count = sci_txroom(port); 559 560 do { 561 unsigned char c; 562 563 if (port->x_char) { 564 c = port->x_char; 565 port->x_char = 0; 566 } else if (!uart_circ_empty(xmit) && !stopped) { 567 c = xmit->buf[xmit->tail]; 568 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 569 } else { 570 break; 571 } 572 573 serial_port_out(port, SCxTDR, c); 574 575 port->icount.tx++; 576 } while (--count > 0); 577 578 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); 579 580 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 581 uart_write_wakeup(port); 582 if (uart_circ_empty(xmit)) { 583 sci_stop_tx(port); 584 } else { 585 ctrl = serial_port_in(port, SCSCR); 586 587 if (port->type != PORT_SCI) { 588 serial_port_in(port, SCxSR); /* Dummy read */ 589 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); 590 } 591 592 ctrl |= SCSCR_TIE; 593 serial_port_out(port, SCSCR, ctrl); 594 } 595 } 596 597 /* On SH3, SCIF may read end-of-break as a space->mark char */ 598 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); }) 599 600 static void sci_receive_chars(struct uart_port *port) 601 { 602 struct sci_port *sci_port = to_sci_port(port); 603 struct tty_struct *tty = port->state->port.tty; 604 int i, count, copied = 0; 605 unsigned short status; 606 unsigned char flag; 607 608 status = serial_port_in(port, SCxSR); 609 if (!(status & SCxSR_RDxF(port))) 610 return; 611 612 while (1) { 613 /* Don't copy more bytes than there is room for in the buffer */ 614 count = tty_buffer_request_room(tty, sci_rxfill(port)); 615 616 /* If for any reason we can't copy more data, we're done! */ 617 if (count == 0) 618 break; 619 620 if (port->type == PORT_SCI) { 621 char c = serial_port_in(port, SCxRDR); 622 if (uart_handle_sysrq_char(port, c) || 623 sci_port->break_flag) 624 count = 0; 625 else 626 tty_insert_flip_char(tty, c, TTY_NORMAL); 627 } else { 628 for (i = 0; i < count; i++) { 629 char c = serial_port_in(port, SCxRDR); 630 631 status = serial_port_in(port, SCxSR); 632 #if defined(CONFIG_CPU_SH3) 633 /* Skip "chars" during break */ 634 if (sci_port->break_flag) { 635 if ((c == 0) && 636 (status & SCxSR_FER(port))) { 637 count--; i--; 638 continue; 639 } 640 641 /* Nonzero => end-of-break */ 642 dev_dbg(port->dev, "debounce<%02x>\n", c); 643 sci_port->break_flag = 0; 644 645 if (STEPFN(c)) { 646 count--; i--; 647 continue; 648 } 649 } 650 #endif /* CONFIG_CPU_SH3 */ 651 if (uart_handle_sysrq_char(port, c)) { 652 count--; i--; 653 continue; 654 } 655 656 /* Store data and status */ 657 if (status & SCxSR_FER(port)) { 658 flag = TTY_FRAME; 659 port->icount.frame++; 660 dev_notice(port->dev, "frame error\n"); 661 } else if (status & SCxSR_PER(port)) { 662 flag = TTY_PARITY; 663 port->icount.parity++; 664 dev_notice(port->dev, "parity error\n"); 665 } else 666 flag = TTY_NORMAL; 667 668 tty_insert_flip_char(tty, c, flag); 669 } 670 } 671 672 serial_port_in(port, SCxSR); /* dummy read */ 673 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); 674 675 copied += count; 676 port->icount.rx += count; 677 } 678 679 if (copied) { 680 /* Tell the rest of the system the news. New characters! */ 681 tty_flip_buffer_push(tty); 682 } else { 683 serial_port_in(port, SCxSR); /* dummy read */ 684 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); 685 } 686 } 687 688 #define SCI_BREAK_JIFFIES (HZ/20) 689 690 /* 691 * The sci generates interrupts during the break, 692 * 1 per millisecond or so during the break period, for 9600 baud. 693 * So dont bother disabling interrupts. 694 * But dont want more than 1 break event. 695 * Use a kernel timer to periodically poll the rx line until 696 * the break is finished. 697 */ 698 static inline void sci_schedule_break_timer(struct sci_port *port) 699 { 700 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES); 701 } 702 703 /* Ensure that two consecutive samples find the break over. */ 704 static void sci_break_timer(unsigned long data) 705 { 706 struct sci_port *port = (struct sci_port *)data; 707 708 sci_port_enable(port); 709 710 if (sci_rxd_in(&port->port) == 0) { 711 port->break_flag = 1; 712 sci_schedule_break_timer(port); 713 } else if (port->break_flag == 1) { 714 /* break is over. */ 715 port->break_flag = 2; 716 sci_schedule_break_timer(port); 717 } else 718 port->break_flag = 0; 719 720 sci_port_disable(port); 721 } 722 723 static int sci_handle_errors(struct uart_port *port) 724 { 725 int copied = 0; 726 unsigned short status = serial_port_in(port, SCxSR); 727 struct tty_struct *tty = port->state->port.tty; 728 struct sci_port *s = to_sci_port(port); 729 730 /* 731 * Handle overruns, if supported. 732 */ 733 if (s->cfg->overrun_bit != SCIx_NOT_SUPPORTED) { 734 if (status & (1 << s->cfg->overrun_bit)) { 735 port->icount.overrun++; 736 737 /* overrun error */ 738 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN)) 739 copied++; 740 741 dev_notice(port->dev, "overrun error"); 742 } 743 } 744 745 if (status & SCxSR_FER(port)) { 746 if (sci_rxd_in(port) == 0) { 747 /* Notify of BREAK */ 748 struct sci_port *sci_port = to_sci_port(port); 749 750 if (!sci_port->break_flag) { 751 port->icount.brk++; 752 753 sci_port->break_flag = 1; 754 sci_schedule_break_timer(sci_port); 755 756 /* Do sysrq handling. */ 757 if (uart_handle_break(port)) 758 return 0; 759 760 dev_dbg(port->dev, "BREAK detected\n"); 761 762 if (tty_insert_flip_char(tty, 0, TTY_BREAK)) 763 copied++; 764 } 765 766 } else { 767 /* frame error */ 768 port->icount.frame++; 769 770 if (tty_insert_flip_char(tty, 0, TTY_FRAME)) 771 copied++; 772 773 dev_notice(port->dev, "frame error\n"); 774 } 775 } 776 777 if (status & SCxSR_PER(port)) { 778 /* parity error */ 779 port->icount.parity++; 780 781 if (tty_insert_flip_char(tty, 0, TTY_PARITY)) 782 copied++; 783 784 dev_notice(port->dev, "parity error"); 785 } 786 787 if (copied) 788 tty_flip_buffer_push(tty); 789 790 return copied; 791 } 792 793 static int sci_handle_fifo_overrun(struct uart_port *port) 794 { 795 struct tty_struct *tty = port->state->port.tty; 796 struct sci_port *s = to_sci_port(port); 797 struct plat_sci_reg *reg; 798 int copied = 0; 799 800 reg = sci_getreg(port, SCLSR); 801 if (!reg->size) 802 return 0; 803 804 if ((serial_port_in(port, SCLSR) & (1 << s->cfg->overrun_bit))) { 805 serial_port_out(port, SCLSR, 0); 806 807 port->icount.overrun++; 808 809 tty_insert_flip_char(tty, 0, TTY_OVERRUN); 810 tty_flip_buffer_push(tty); 811 812 dev_notice(port->dev, "overrun error\n"); 813 copied++; 814 } 815 816 return copied; 817 } 818 819 static int sci_handle_breaks(struct uart_port *port) 820 { 821 int copied = 0; 822 unsigned short status = serial_port_in(port, SCxSR); 823 struct tty_struct *tty = port->state->port.tty; 824 struct sci_port *s = to_sci_port(port); 825 826 if (uart_handle_break(port)) 827 return 0; 828 829 if (!s->break_flag && status & SCxSR_BRK(port)) { 830 #if defined(CONFIG_CPU_SH3) 831 /* Debounce break */ 832 s->break_flag = 1; 833 #endif 834 835 port->icount.brk++; 836 837 /* Notify of BREAK */ 838 if (tty_insert_flip_char(tty, 0, TTY_BREAK)) 839 copied++; 840 841 dev_dbg(port->dev, "BREAK detected\n"); 842 } 843 844 if (copied) 845 tty_flip_buffer_push(tty); 846 847 copied += sci_handle_fifo_overrun(port); 848 849 return copied; 850 } 851 852 static irqreturn_t sci_rx_interrupt(int irq, void *ptr) 853 { 854 #ifdef CONFIG_SERIAL_SH_SCI_DMA 855 struct uart_port *port = ptr; 856 struct sci_port *s = to_sci_port(port); 857 858 if (s->chan_rx) { 859 u16 scr = serial_port_in(port, SCSCR); 860 u16 ssr = serial_port_in(port, SCxSR); 861 862 /* Disable future Rx interrupts */ 863 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 864 disable_irq_nosync(irq); 865 scr |= 0x4000; 866 } else { 867 scr &= ~SCSCR_RIE; 868 } 869 serial_port_out(port, SCSCR, scr); 870 /* Clear current interrupt */ 871 serial_port_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port))); 872 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n", 873 jiffies, s->rx_timeout); 874 mod_timer(&s->rx_timer, jiffies + s->rx_timeout); 875 876 return IRQ_HANDLED; 877 } 878 #endif 879 880 /* I think sci_receive_chars has to be called irrespective 881 * of whether the I_IXOFF is set, otherwise, how is the interrupt 882 * to be disabled? 883 */ 884 sci_receive_chars(ptr); 885 886 return IRQ_HANDLED; 887 } 888 889 static irqreturn_t sci_tx_interrupt(int irq, void *ptr) 890 { 891 struct uart_port *port = ptr; 892 unsigned long flags; 893 894 spin_lock_irqsave(&port->lock, flags); 895 sci_transmit_chars(port); 896 spin_unlock_irqrestore(&port->lock, flags); 897 898 return IRQ_HANDLED; 899 } 900 901 static irqreturn_t sci_er_interrupt(int irq, void *ptr) 902 { 903 struct uart_port *port = ptr; 904 905 /* Handle errors */ 906 if (port->type == PORT_SCI) { 907 if (sci_handle_errors(port)) { 908 /* discard character in rx buffer */ 909 serial_port_in(port, SCxSR); 910 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); 911 } 912 } else { 913 sci_handle_fifo_overrun(port); 914 sci_rx_interrupt(irq, ptr); 915 } 916 917 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port)); 918 919 /* Kick the transmission */ 920 sci_tx_interrupt(irq, ptr); 921 922 return IRQ_HANDLED; 923 } 924 925 static irqreturn_t sci_br_interrupt(int irq, void *ptr) 926 { 927 struct uart_port *port = ptr; 928 929 /* Handle BREAKs */ 930 sci_handle_breaks(port); 931 serial_port_out(port, SCxSR, SCxSR_BREAK_CLEAR(port)); 932 933 return IRQ_HANDLED; 934 } 935 936 static inline unsigned long port_rx_irq_mask(struct uart_port *port) 937 { 938 /* 939 * Not all ports (such as SCIFA) will support REIE. Rather than 940 * special-casing the port type, we check the port initialization 941 * IRQ enable mask to see whether the IRQ is desired at all. If 942 * it's unset, it's logically inferred that there's no point in 943 * testing for it. 944 */ 945 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE); 946 } 947 948 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) 949 { 950 unsigned short ssr_status, scr_status, err_enabled; 951 struct uart_port *port = ptr; 952 struct sci_port *s = to_sci_port(port); 953 irqreturn_t ret = IRQ_NONE; 954 955 ssr_status = serial_port_in(port, SCxSR); 956 scr_status = serial_port_in(port, SCSCR); 957 err_enabled = scr_status & port_rx_irq_mask(port); 958 959 /* Tx Interrupt */ 960 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) && 961 !s->chan_tx) 962 ret = sci_tx_interrupt(irq, ptr); 963 964 /* 965 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF / 966 * DR flags 967 */ 968 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) && 969 (scr_status & SCSCR_RIE)) 970 ret = sci_rx_interrupt(irq, ptr); 971 972 /* Error Interrupt */ 973 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled) 974 ret = sci_er_interrupt(irq, ptr); 975 976 /* Break Interrupt */ 977 if ((ssr_status & SCxSR_BRK(port)) && err_enabled) 978 ret = sci_br_interrupt(irq, ptr); 979 980 return ret; 981 } 982 983 /* 984 * Here we define a transition notifier so that we can update all of our 985 * ports' baud rate when the peripheral clock changes. 986 */ 987 static int sci_notifier(struct notifier_block *self, 988 unsigned long phase, void *p) 989 { 990 struct sci_port *sci_port; 991 unsigned long flags; 992 993 sci_port = container_of(self, struct sci_port, freq_transition); 994 995 if ((phase == CPUFREQ_POSTCHANGE) || 996 (phase == CPUFREQ_RESUMECHANGE)) { 997 struct uart_port *port = &sci_port->port; 998 999 spin_lock_irqsave(&port->lock, flags); 1000 port->uartclk = clk_get_rate(sci_port->iclk); 1001 spin_unlock_irqrestore(&port->lock, flags); 1002 } 1003 1004 return NOTIFY_OK; 1005 } 1006 1007 static struct sci_irq_desc { 1008 const char *desc; 1009 irq_handler_t handler; 1010 } sci_irq_desc[] = { 1011 /* 1012 * Split out handlers, the default case. 1013 */ 1014 [SCIx_ERI_IRQ] = { 1015 .desc = "rx err", 1016 .handler = sci_er_interrupt, 1017 }, 1018 1019 [SCIx_RXI_IRQ] = { 1020 .desc = "rx full", 1021 .handler = sci_rx_interrupt, 1022 }, 1023 1024 [SCIx_TXI_IRQ] = { 1025 .desc = "tx empty", 1026 .handler = sci_tx_interrupt, 1027 }, 1028 1029 [SCIx_BRI_IRQ] = { 1030 .desc = "break", 1031 .handler = sci_br_interrupt, 1032 }, 1033 1034 /* 1035 * Special muxed handler. 1036 */ 1037 [SCIx_MUX_IRQ] = { 1038 .desc = "mux", 1039 .handler = sci_mpxed_interrupt, 1040 }, 1041 }; 1042 1043 static int sci_request_irq(struct sci_port *port) 1044 { 1045 struct uart_port *up = &port->port; 1046 int i, j, ret = 0; 1047 1048 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) { 1049 struct sci_irq_desc *desc; 1050 unsigned int irq; 1051 1052 if (SCIx_IRQ_IS_MUXED(port)) { 1053 i = SCIx_MUX_IRQ; 1054 irq = up->irq; 1055 } else 1056 irq = port->cfg->irqs[i]; 1057 1058 desc = sci_irq_desc + i; 1059 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s", 1060 dev_name(up->dev), desc->desc); 1061 if (!port->irqstr[j]) { 1062 dev_err(up->dev, "Failed to allocate %s IRQ string\n", 1063 desc->desc); 1064 goto out_nomem; 1065 } 1066 1067 ret = request_irq(irq, desc->handler, up->irqflags, 1068 port->irqstr[j], port); 1069 if (unlikely(ret)) { 1070 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc); 1071 goto out_noirq; 1072 } 1073 } 1074 1075 return 0; 1076 1077 out_noirq: 1078 while (--i >= 0) 1079 free_irq(port->cfg->irqs[i], port); 1080 1081 out_nomem: 1082 while (--j >= 0) 1083 kfree(port->irqstr[j]); 1084 1085 return ret; 1086 } 1087 1088 static void sci_free_irq(struct sci_port *port) 1089 { 1090 int i; 1091 1092 /* 1093 * Intentionally in reverse order so we iterate over the muxed 1094 * IRQ first. 1095 */ 1096 for (i = 0; i < SCIx_NR_IRQS; i++) { 1097 free_irq(port->cfg->irqs[i], port); 1098 kfree(port->irqstr[i]); 1099 1100 if (SCIx_IRQ_IS_MUXED(port)) { 1101 /* If there's only one IRQ, we're done. */ 1102 return; 1103 } 1104 } 1105 } 1106 1107 static const char *sci_gpio_names[SCIx_NR_FNS] = { 1108 "sck", "rxd", "txd", "cts", "rts", 1109 }; 1110 1111 static const char *sci_gpio_str(unsigned int index) 1112 { 1113 return sci_gpio_names[index]; 1114 } 1115 1116 static void __devinit sci_init_gpios(struct sci_port *port) 1117 { 1118 struct uart_port *up = &port->port; 1119 int i; 1120 1121 if (!port->cfg) 1122 return; 1123 1124 for (i = 0; i < SCIx_NR_FNS; i++) { 1125 const char *desc; 1126 int ret; 1127 1128 if (!port->cfg->gpios[i]) 1129 continue; 1130 1131 desc = sci_gpio_str(i); 1132 1133 port->gpiostr[i] = kasprintf(GFP_KERNEL, "%s:%s", 1134 dev_name(up->dev), desc); 1135 1136 /* 1137 * If we've failed the allocation, we can still continue 1138 * on with a NULL string. 1139 */ 1140 if (!port->gpiostr[i]) 1141 dev_notice(up->dev, "%s string allocation failure\n", 1142 desc); 1143 1144 ret = gpio_request(port->cfg->gpios[i], port->gpiostr[i]); 1145 if (unlikely(ret != 0)) { 1146 dev_notice(up->dev, "failed %s gpio request\n", desc); 1147 1148 /* 1149 * If we can't get the GPIO for whatever reason, 1150 * no point in keeping the verbose string around. 1151 */ 1152 kfree(port->gpiostr[i]); 1153 } 1154 } 1155 } 1156 1157 static void sci_free_gpios(struct sci_port *port) 1158 { 1159 int i; 1160 1161 for (i = 0; i < SCIx_NR_FNS; i++) 1162 if (port->cfg->gpios[i]) { 1163 gpio_free(port->cfg->gpios[i]); 1164 kfree(port->gpiostr[i]); 1165 } 1166 } 1167 1168 static unsigned int sci_tx_empty(struct uart_port *port) 1169 { 1170 unsigned short status = serial_port_in(port, SCxSR); 1171 unsigned short in_tx_fifo = sci_txfill(port); 1172 1173 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0; 1174 } 1175 1176 /* 1177 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally 1178 * CTS/RTS is supported in hardware by at least one port and controlled 1179 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently 1180 * handled via the ->init_pins() op, which is a bit of a one-way street, 1181 * lacking any ability to defer pin control -- this will later be 1182 * converted over to the GPIO framework). 1183 * 1184 * Other modes (such as loopback) are supported generically on certain 1185 * port types, but not others. For these it's sufficient to test for the 1186 * existence of the support register and simply ignore the port type. 1187 */ 1188 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) 1189 { 1190 if (mctrl & TIOCM_LOOP) { 1191 struct plat_sci_reg *reg; 1192 1193 /* 1194 * Standard loopback mode for SCFCR ports. 1195 */ 1196 reg = sci_getreg(port, SCFCR); 1197 if (reg->size) 1198 serial_port_out(port, SCFCR, serial_port_in(port, SCFCR) | 1); 1199 } 1200 } 1201 1202 static unsigned int sci_get_mctrl(struct uart_port *port) 1203 { 1204 /* 1205 * CTS/RTS is handled in hardware when supported, while nothing 1206 * else is wired up. Keep it simple and simply assert DSR/CAR. 1207 */ 1208 return TIOCM_DSR | TIOCM_CAR; 1209 } 1210 1211 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1212 static void sci_dma_tx_complete(void *arg) 1213 { 1214 struct sci_port *s = arg; 1215 struct uart_port *port = &s->port; 1216 struct circ_buf *xmit = &port->state->xmit; 1217 unsigned long flags; 1218 1219 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1220 1221 spin_lock_irqsave(&port->lock, flags); 1222 1223 xmit->tail += sg_dma_len(&s->sg_tx); 1224 xmit->tail &= UART_XMIT_SIZE - 1; 1225 1226 port->icount.tx += sg_dma_len(&s->sg_tx); 1227 1228 async_tx_ack(s->desc_tx); 1229 s->desc_tx = NULL; 1230 1231 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1232 uart_write_wakeup(port); 1233 1234 if (!uart_circ_empty(xmit)) { 1235 s->cookie_tx = 0; 1236 schedule_work(&s->work_tx); 1237 } else { 1238 s->cookie_tx = -EINVAL; 1239 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1240 u16 ctrl = serial_port_in(port, SCSCR); 1241 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE); 1242 } 1243 } 1244 1245 spin_unlock_irqrestore(&port->lock, flags); 1246 } 1247 1248 /* Locking: called with port lock held */ 1249 static int sci_dma_rx_push(struct sci_port *s, struct tty_struct *tty, 1250 size_t count) 1251 { 1252 struct uart_port *port = &s->port; 1253 int i, active, room; 1254 1255 room = tty_buffer_request_room(tty, count); 1256 1257 if (s->active_rx == s->cookie_rx[0]) { 1258 active = 0; 1259 } else if (s->active_rx == s->cookie_rx[1]) { 1260 active = 1; 1261 } else { 1262 dev_err(port->dev, "cookie %d not found!\n", s->active_rx); 1263 return 0; 1264 } 1265 1266 if (room < count) 1267 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n", 1268 count - room); 1269 if (!room) 1270 return room; 1271 1272 for (i = 0; i < room; i++) 1273 tty_insert_flip_char(tty, ((u8 *)sg_virt(&s->sg_rx[active]))[i], 1274 TTY_NORMAL); 1275 1276 port->icount.rx += room; 1277 1278 return room; 1279 } 1280 1281 static void sci_dma_rx_complete(void *arg) 1282 { 1283 struct sci_port *s = arg; 1284 struct uart_port *port = &s->port; 1285 struct tty_struct *tty = port->state->port.tty; 1286 unsigned long flags; 1287 int count; 1288 1289 dev_dbg(port->dev, "%s(%d) active #%d\n", __func__, port->line, s->active_rx); 1290 1291 spin_lock_irqsave(&port->lock, flags); 1292 1293 count = sci_dma_rx_push(s, tty, s->buf_len_rx); 1294 1295 mod_timer(&s->rx_timer, jiffies + s->rx_timeout); 1296 1297 spin_unlock_irqrestore(&port->lock, flags); 1298 1299 if (count) 1300 tty_flip_buffer_push(tty); 1301 1302 schedule_work(&s->work_rx); 1303 } 1304 1305 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio) 1306 { 1307 struct dma_chan *chan = s->chan_rx; 1308 struct uart_port *port = &s->port; 1309 1310 s->chan_rx = NULL; 1311 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL; 1312 dma_release_channel(chan); 1313 if (sg_dma_address(&s->sg_rx[0])) 1314 dma_free_coherent(port->dev, s->buf_len_rx * 2, 1315 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0])); 1316 if (enable_pio) 1317 sci_start_rx(port); 1318 } 1319 1320 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio) 1321 { 1322 struct dma_chan *chan = s->chan_tx; 1323 struct uart_port *port = &s->port; 1324 1325 s->chan_tx = NULL; 1326 s->cookie_tx = -EINVAL; 1327 dma_release_channel(chan); 1328 if (enable_pio) 1329 sci_start_tx(port); 1330 } 1331 1332 static void sci_submit_rx(struct sci_port *s) 1333 { 1334 struct dma_chan *chan = s->chan_rx; 1335 int i; 1336 1337 for (i = 0; i < 2; i++) { 1338 struct scatterlist *sg = &s->sg_rx[i]; 1339 struct dma_async_tx_descriptor *desc; 1340 1341 desc = dmaengine_prep_slave_sg(chan, 1342 sg, 1, DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT); 1343 1344 if (desc) { 1345 s->desc_rx[i] = desc; 1346 desc->callback = sci_dma_rx_complete; 1347 desc->callback_param = s; 1348 s->cookie_rx[i] = desc->tx_submit(desc); 1349 } 1350 1351 if (!desc || s->cookie_rx[i] < 0) { 1352 if (i) { 1353 async_tx_ack(s->desc_rx[0]); 1354 s->cookie_rx[0] = -EINVAL; 1355 } 1356 if (desc) { 1357 async_tx_ack(desc); 1358 s->cookie_rx[i] = -EINVAL; 1359 } 1360 dev_warn(s->port.dev, 1361 "failed to re-start DMA, using PIO\n"); 1362 sci_rx_dma_release(s, true); 1363 return; 1364 } 1365 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__, 1366 s->cookie_rx[i], i); 1367 } 1368 1369 s->active_rx = s->cookie_rx[0]; 1370 1371 dma_async_issue_pending(chan); 1372 } 1373 1374 static void work_fn_rx(struct work_struct *work) 1375 { 1376 struct sci_port *s = container_of(work, struct sci_port, work_rx); 1377 struct uart_port *port = &s->port; 1378 struct dma_async_tx_descriptor *desc; 1379 int new; 1380 1381 if (s->active_rx == s->cookie_rx[0]) { 1382 new = 0; 1383 } else if (s->active_rx == s->cookie_rx[1]) { 1384 new = 1; 1385 } else { 1386 dev_err(port->dev, "cookie %d not found!\n", s->active_rx); 1387 return; 1388 } 1389 desc = s->desc_rx[new]; 1390 1391 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) != 1392 DMA_SUCCESS) { 1393 /* Handle incomplete DMA receive */ 1394 struct tty_struct *tty = port->state->port.tty; 1395 struct dma_chan *chan = s->chan_rx; 1396 struct sh_desc *sh_desc = container_of(desc, struct sh_desc, 1397 async_tx); 1398 unsigned long flags; 1399 int count; 1400 1401 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0); 1402 dev_dbg(port->dev, "Read %u bytes with cookie %d\n", 1403 sh_desc->partial, sh_desc->cookie); 1404 1405 spin_lock_irqsave(&port->lock, flags); 1406 count = sci_dma_rx_push(s, tty, sh_desc->partial); 1407 spin_unlock_irqrestore(&port->lock, flags); 1408 1409 if (count) 1410 tty_flip_buffer_push(tty); 1411 1412 sci_submit_rx(s); 1413 1414 return; 1415 } 1416 1417 s->cookie_rx[new] = desc->tx_submit(desc); 1418 if (s->cookie_rx[new] < 0) { 1419 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n"); 1420 sci_rx_dma_release(s, true); 1421 return; 1422 } 1423 1424 s->active_rx = s->cookie_rx[!new]; 1425 1426 dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n", __func__, 1427 s->cookie_rx[new], new, s->active_rx); 1428 } 1429 1430 static void work_fn_tx(struct work_struct *work) 1431 { 1432 struct sci_port *s = container_of(work, struct sci_port, work_tx); 1433 struct dma_async_tx_descriptor *desc; 1434 struct dma_chan *chan = s->chan_tx; 1435 struct uart_port *port = &s->port; 1436 struct circ_buf *xmit = &port->state->xmit; 1437 struct scatterlist *sg = &s->sg_tx; 1438 1439 /* 1440 * DMA is idle now. 1441 * Port xmit buffer is already mapped, and it is one page... Just adjust 1442 * offsets and lengths. Since it is a circular buffer, we have to 1443 * transmit till the end, and then the rest. Take the port lock to get a 1444 * consistent xmit buffer state. 1445 */ 1446 spin_lock_irq(&port->lock); 1447 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1); 1448 sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) + 1449 sg->offset; 1450 sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE), 1451 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE)); 1452 spin_unlock_irq(&port->lock); 1453 1454 BUG_ON(!sg_dma_len(sg)); 1455 1456 desc = dmaengine_prep_slave_sg(chan, 1457 sg, s->sg_len_tx, DMA_MEM_TO_DEV, 1458 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1459 if (!desc) { 1460 /* switch to PIO */ 1461 sci_tx_dma_release(s, true); 1462 return; 1463 } 1464 1465 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE); 1466 1467 spin_lock_irq(&port->lock); 1468 s->desc_tx = desc; 1469 desc->callback = sci_dma_tx_complete; 1470 desc->callback_param = s; 1471 spin_unlock_irq(&port->lock); 1472 s->cookie_tx = desc->tx_submit(desc); 1473 if (s->cookie_tx < 0) { 1474 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n"); 1475 /* switch to PIO */ 1476 sci_tx_dma_release(s, true); 1477 return; 1478 } 1479 1480 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", __func__, 1481 xmit->buf, xmit->tail, xmit->head, s->cookie_tx); 1482 1483 dma_async_issue_pending(chan); 1484 } 1485 #endif 1486 1487 static void sci_start_tx(struct uart_port *port) 1488 { 1489 struct sci_port *s = to_sci_port(port); 1490 unsigned short ctrl; 1491 1492 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1493 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1494 u16 new, scr = serial_port_in(port, SCSCR); 1495 if (s->chan_tx) 1496 new = scr | 0x8000; 1497 else 1498 new = scr & ~0x8000; 1499 if (new != scr) 1500 serial_port_out(port, SCSCR, new); 1501 } 1502 1503 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) && 1504 s->cookie_tx < 0) { 1505 s->cookie_tx = 0; 1506 schedule_work(&s->work_tx); 1507 } 1508 #endif 1509 1510 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1511 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ 1512 ctrl = serial_port_in(port, SCSCR); 1513 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE); 1514 } 1515 } 1516 1517 static void sci_stop_tx(struct uart_port *port) 1518 { 1519 unsigned short ctrl; 1520 1521 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ 1522 ctrl = serial_port_in(port, SCSCR); 1523 1524 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1525 ctrl &= ~0x8000; 1526 1527 ctrl &= ~SCSCR_TIE; 1528 1529 serial_port_out(port, SCSCR, ctrl); 1530 } 1531 1532 static void sci_start_rx(struct uart_port *port) 1533 { 1534 unsigned short ctrl; 1535 1536 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port); 1537 1538 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1539 ctrl &= ~0x4000; 1540 1541 serial_port_out(port, SCSCR, ctrl); 1542 } 1543 1544 static void sci_stop_rx(struct uart_port *port) 1545 { 1546 unsigned short ctrl; 1547 1548 ctrl = serial_port_in(port, SCSCR); 1549 1550 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1551 ctrl &= ~0x4000; 1552 1553 ctrl &= ~port_rx_irq_mask(port); 1554 1555 serial_port_out(port, SCSCR, ctrl); 1556 } 1557 1558 static void sci_enable_ms(struct uart_port *port) 1559 { 1560 /* 1561 * Not supported by hardware, always a nop. 1562 */ 1563 } 1564 1565 static void sci_break_ctl(struct uart_port *port, int break_state) 1566 { 1567 /* 1568 * Not supported by hardware. Most parts couple break and rx 1569 * interrupts together, with break detection always enabled. 1570 */ 1571 } 1572 1573 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1574 static bool filter(struct dma_chan *chan, void *slave) 1575 { 1576 struct sh_dmae_slave *param = slave; 1577 1578 dev_dbg(chan->device->dev, "%s: slave ID %d\n", __func__, 1579 param->slave_id); 1580 1581 chan->private = param; 1582 return true; 1583 } 1584 1585 static void rx_timer_fn(unsigned long arg) 1586 { 1587 struct sci_port *s = (struct sci_port *)arg; 1588 struct uart_port *port = &s->port; 1589 u16 scr = serial_port_in(port, SCSCR); 1590 1591 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1592 scr &= ~0x4000; 1593 enable_irq(s->cfg->irqs[1]); 1594 } 1595 serial_port_out(port, SCSCR, scr | SCSCR_RIE); 1596 dev_dbg(port->dev, "DMA Rx timed out\n"); 1597 schedule_work(&s->work_rx); 1598 } 1599 1600 static void sci_request_dma(struct uart_port *port) 1601 { 1602 struct sci_port *s = to_sci_port(port); 1603 struct sh_dmae_slave *param; 1604 struct dma_chan *chan; 1605 dma_cap_mask_t mask; 1606 int nent; 1607 1608 dev_dbg(port->dev, "%s: port %d\n", __func__, 1609 port->line); 1610 1611 if (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0) 1612 return; 1613 1614 dma_cap_zero(mask); 1615 dma_cap_set(DMA_SLAVE, mask); 1616 1617 param = &s->param_tx; 1618 1619 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */ 1620 param->slave_id = s->cfg->dma_slave_tx; 1621 1622 s->cookie_tx = -EINVAL; 1623 chan = dma_request_channel(mask, filter, param); 1624 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan); 1625 if (chan) { 1626 s->chan_tx = chan; 1627 sg_init_table(&s->sg_tx, 1); 1628 /* UART circular tx buffer is an aligned page. */ 1629 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK); 1630 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf), 1631 UART_XMIT_SIZE, (int)port->state->xmit.buf & ~PAGE_MASK); 1632 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE); 1633 if (!nent) 1634 sci_tx_dma_release(s, false); 1635 else 1636 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__, 1637 sg_dma_len(&s->sg_tx), 1638 port->state->xmit.buf, sg_dma_address(&s->sg_tx)); 1639 1640 s->sg_len_tx = nent; 1641 1642 INIT_WORK(&s->work_tx, work_fn_tx); 1643 } 1644 1645 param = &s->param_rx; 1646 1647 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */ 1648 param->slave_id = s->cfg->dma_slave_rx; 1649 1650 chan = dma_request_channel(mask, filter, param); 1651 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan); 1652 if (chan) { 1653 dma_addr_t dma[2]; 1654 void *buf[2]; 1655 int i; 1656 1657 s->chan_rx = chan; 1658 1659 s->buf_len_rx = 2 * max(16, (int)port->fifosize); 1660 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2, 1661 &dma[0], GFP_KERNEL); 1662 1663 if (!buf[0]) { 1664 dev_warn(port->dev, 1665 "failed to allocate dma buffer, using PIO\n"); 1666 sci_rx_dma_release(s, true); 1667 return; 1668 } 1669 1670 buf[1] = buf[0] + s->buf_len_rx; 1671 dma[1] = dma[0] + s->buf_len_rx; 1672 1673 for (i = 0; i < 2; i++) { 1674 struct scatterlist *sg = &s->sg_rx[i]; 1675 1676 sg_init_table(sg, 1); 1677 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx, 1678 (int)buf[i] & ~PAGE_MASK); 1679 sg_dma_address(sg) = dma[i]; 1680 } 1681 1682 INIT_WORK(&s->work_rx, work_fn_rx); 1683 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s); 1684 1685 sci_submit_rx(s); 1686 } 1687 } 1688 1689 static void sci_free_dma(struct uart_port *port) 1690 { 1691 struct sci_port *s = to_sci_port(port); 1692 1693 if (s->chan_tx) 1694 sci_tx_dma_release(s, false); 1695 if (s->chan_rx) 1696 sci_rx_dma_release(s, false); 1697 } 1698 #else 1699 static inline void sci_request_dma(struct uart_port *port) 1700 { 1701 } 1702 1703 static inline void sci_free_dma(struct uart_port *port) 1704 { 1705 } 1706 #endif 1707 1708 static int sci_startup(struct uart_port *port) 1709 { 1710 struct sci_port *s = to_sci_port(port); 1711 int ret; 1712 1713 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1714 1715 pm_runtime_put_noidle(port->dev); 1716 1717 sci_port_enable(s); 1718 1719 ret = sci_request_irq(s); 1720 if (unlikely(ret < 0)) 1721 return ret; 1722 1723 sci_request_dma(port); 1724 1725 sci_start_tx(port); 1726 sci_start_rx(port); 1727 1728 return 0; 1729 } 1730 1731 static void sci_shutdown(struct uart_port *port) 1732 { 1733 struct sci_port *s = to_sci_port(port); 1734 1735 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1736 1737 sci_stop_rx(port); 1738 sci_stop_tx(port); 1739 1740 sci_free_dma(port); 1741 sci_free_irq(s); 1742 1743 sci_port_disable(s); 1744 1745 pm_runtime_get_noresume(port->dev); 1746 } 1747 1748 static unsigned int sci_scbrr_calc(unsigned int algo_id, unsigned int bps, 1749 unsigned long freq) 1750 { 1751 switch (algo_id) { 1752 case SCBRR_ALGO_1: 1753 return ((freq + 16 * bps) / (16 * bps) - 1); 1754 case SCBRR_ALGO_2: 1755 return ((freq + 16 * bps) / (32 * bps) - 1); 1756 case SCBRR_ALGO_3: 1757 return (((freq * 2) + 16 * bps) / (16 * bps) - 1); 1758 case SCBRR_ALGO_4: 1759 return (((freq * 2) + 16 * bps) / (32 * bps) - 1); 1760 case SCBRR_ALGO_5: 1761 return (((freq * 1000 / 32) / bps) - 1); 1762 } 1763 1764 /* Warn, but use a safe default */ 1765 WARN_ON(1); 1766 1767 return ((freq + 16 * bps) / (32 * bps) - 1); 1768 } 1769 1770 static void sci_reset(struct uart_port *port) 1771 { 1772 struct plat_sci_reg *reg; 1773 unsigned int status; 1774 1775 do { 1776 status = serial_port_in(port, SCxSR); 1777 } while (!(status & SCxSR_TEND(port))); 1778 1779 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */ 1780 1781 reg = sci_getreg(port, SCFCR); 1782 if (reg->size) 1783 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); 1784 } 1785 1786 static void sci_set_termios(struct uart_port *port, struct ktermios *termios, 1787 struct ktermios *old) 1788 { 1789 struct sci_port *s = to_sci_port(port); 1790 struct plat_sci_reg *reg; 1791 unsigned int baud, smr_val, max_baud; 1792 int t = -1; 1793 1794 /* 1795 * earlyprintk comes here early on with port->uartclk set to zero. 1796 * the clock framework is not up and running at this point so here 1797 * we assume that 115200 is the maximum baud rate. please note that 1798 * the baud rate is not programmed during earlyprintk - it is assumed 1799 * that the previous boot loader has enabled required clocks and 1800 * setup the baud rate generator hardware for us already. 1801 */ 1802 max_baud = port->uartclk ? port->uartclk / 16 : 115200; 1803 1804 baud = uart_get_baud_rate(port, termios, old, 0, max_baud); 1805 if (likely(baud && port->uartclk)) 1806 t = sci_scbrr_calc(s->cfg->scbrr_algo_id, baud, port->uartclk); 1807 1808 sci_port_enable(s); 1809 1810 sci_reset(port); 1811 1812 smr_val = serial_port_in(port, SCSMR) & 3; 1813 1814 if ((termios->c_cflag & CSIZE) == CS7) 1815 smr_val |= 0x40; 1816 if (termios->c_cflag & PARENB) 1817 smr_val |= 0x20; 1818 if (termios->c_cflag & PARODD) 1819 smr_val |= 0x30; 1820 if (termios->c_cflag & CSTOPB) 1821 smr_val |= 0x08; 1822 1823 uart_update_timeout(port, termios->c_cflag, baud); 1824 1825 serial_port_out(port, SCSMR, smr_val); 1826 1827 dev_dbg(port->dev, "%s: SMR %x, t %x, SCSCR %x\n", __func__, smr_val, t, 1828 s->cfg->scscr); 1829 1830 if (t > 0) { 1831 if (t >= 256) { 1832 serial_port_out(port, SCSMR, (serial_port_in(port, SCSMR) & ~3) | 1); 1833 t >>= 2; 1834 } else 1835 serial_port_out(port, SCSMR, serial_port_in(port, SCSMR) & ~3); 1836 1837 serial_port_out(port, SCBRR, t); 1838 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */ 1839 } 1840 1841 sci_init_pins(port, termios->c_cflag); 1842 1843 reg = sci_getreg(port, SCFCR); 1844 if (reg->size) { 1845 unsigned short ctrl = serial_port_in(port, SCFCR); 1846 1847 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) { 1848 if (termios->c_cflag & CRTSCTS) 1849 ctrl |= SCFCR_MCE; 1850 else 1851 ctrl &= ~SCFCR_MCE; 1852 } 1853 1854 /* 1855 * As we've done a sci_reset() above, ensure we don't 1856 * interfere with the FIFOs while toggling MCE. As the 1857 * reset values could still be set, simply mask them out. 1858 */ 1859 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST); 1860 1861 serial_port_out(port, SCFCR, ctrl); 1862 } 1863 1864 serial_port_out(port, SCSCR, s->cfg->scscr); 1865 1866 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1867 /* 1868 * Calculate delay for 1.5 DMA buffers: see 1869 * drivers/serial/serial_core.c::uart_update_timeout(). With 10 bits 1870 * (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function 1871 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)." 1872 * Then below we calculate 3 jiffies (12ms) for 1.5 DMA buffers (3 FIFO 1873 * sizes), but it has been found out experimentally, that this is not 1874 * enough: the driver too often needlessly runs on a DMA timeout. 20ms 1875 * as a minimum seem to work perfectly. 1876 */ 1877 if (s->chan_rx) { 1878 s->rx_timeout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 / 1879 port->fifosize / 2; 1880 dev_dbg(port->dev, 1881 "DMA Rx t-out %ums, tty t-out %u jiffies\n", 1882 s->rx_timeout * 1000 / HZ, port->timeout); 1883 if (s->rx_timeout < msecs_to_jiffies(20)) 1884 s->rx_timeout = msecs_to_jiffies(20); 1885 } 1886 #endif 1887 1888 if ((termios->c_cflag & CREAD) != 0) 1889 sci_start_rx(port); 1890 1891 sci_port_disable(s); 1892 } 1893 1894 static const char *sci_type(struct uart_port *port) 1895 { 1896 switch (port->type) { 1897 case PORT_IRDA: 1898 return "irda"; 1899 case PORT_SCI: 1900 return "sci"; 1901 case PORT_SCIF: 1902 return "scif"; 1903 case PORT_SCIFA: 1904 return "scifa"; 1905 case PORT_SCIFB: 1906 return "scifb"; 1907 } 1908 1909 return NULL; 1910 } 1911 1912 static inline unsigned long sci_port_size(struct uart_port *port) 1913 { 1914 /* 1915 * Pick an arbitrary size that encapsulates all of the base 1916 * registers by default. This can be optimized later, or derived 1917 * from platform resource data at such a time that ports begin to 1918 * behave more erratically. 1919 */ 1920 return 64; 1921 } 1922 1923 static int sci_remap_port(struct uart_port *port) 1924 { 1925 unsigned long size = sci_port_size(port); 1926 1927 /* 1928 * Nothing to do if there's already an established membase. 1929 */ 1930 if (port->membase) 1931 return 0; 1932 1933 if (port->flags & UPF_IOREMAP) { 1934 port->membase = ioremap_nocache(port->mapbase, size); 1935 if (unlikely(!port->membase)) { 1936 dev_err(port->dev, "can't remap port#%d\n", port->line); 1937 return -ENXIO; 1938 } 1939 } else { 1940 /* 1941 * For the simple (and majority of) cases where we don't 1942 * need to do any remapping, just cast the cookie 1943 * directly. 1944 */ 1945 port->membase = (void __iomem *)port->mapbase; 1946 } 1947 1948 return 0; 1949 } 1950 1951 static void sci_release_port(struct uart_port *port) 1952 { 1953 if (port->flags & UPF_IOREMAP) { 1954 iounmap(port->membase); 1955 port->membase = NULL; 1956 } 1957 1958 release_mem_region(port->mapbase, sci_port_size(port)); 1959 } 1960 1961 static int sci_request_port(struct uart_port *port) 1962 { 1963 unsigned long size = sci_port_size(port); 1964 struct resource *res; 1965 int ret; 1966 1967 res = request_mem_region(port->mapbase, size, dev_name(port->dev)); 1968 if (unlikely(res == NULL)) 1969 return -EBUSY; 1970 1971 ret = sci_remap_port(port); 1972 if (unlikely(ret != 0)) { 1973 release_resource(res); 1974 return ret; 1975 } 1976 1977 return 0; 1978 } 1979 1980 static void sci_config_port(struct uart_port *port, int flags) 1981 { 1982 if (flags & UART_CONFIG_TYPE) { 1983 struct sci_port *sport = to_sci_port(port); 1984 1985 port->type = sport->cfg->type; 1986 sci_request_port(port); 1987 } 1988 } 1989 1990 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser) 1991 { 1992 struct sci_port *s = to_sci_port(port); 1993 1994 if (ser->irq != s->cfg->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs) 1995 return -EINVAL; 1996 if (ser->baud_base < 2400) 1997 /* No paper tape reader for Mitch.. */ 1998 return -EINVAL; 1999 2000 return 0; 2001 } 2002 2003 static struct uart_ops sci_uart_ops = { 2004 .tx_empty = sci_tx_empty, 2005 .set_mctrl = sci_set_mctrl, 2006 .get_mctrl = sci_get_mctrl, 2007 .start_tx = sci_start_tx, 2008 .stop_tx = sci_stop_tx, 2009 .stop_rx = sci_stop_rx, 2010 .enable_ms = sci_enable_ms, 2011 .break_ctl = sci_break_ctl, 2012 .startup = sci_startup, 2013 .shutdown = sci_shutdown, 2014 .set_termios = sci_set_termios, 2015 .type = sci_type, 2016 .release_port = sci_release_port, 2017 .request_port = sci_request_port, 2018 .config_port = sci_config_port, 2019 .verify_port = sci_verify_port, 2020 #ifdef CONFIG_CONSOLE_POLL 2021 .poll_get_char = sci_poll_get_char, 2022 .poll_put_char = sci_poll_put_char, 2023 #endif 2024 }; 2025 2026 static int __devinit sci_init_single(struct platform_device *dev, 2027 struct sci_port *sci_port, 2028 unsigned int index, 2029 struct plat_sci_port *p) 2030 { 2031 struct uart_port *port = &sci_port->port; 2032 int ret; 2033 2034 sci_port->cfg = p; 2035 2036 port->ops = &sci_uart_ops; 2037 port->iotype = UPIO_MEM; 2038 port->line = index; 2039 2040 switch (p->type) { 2041 case PORT_SCIFB: 2042 port->fifosize = 256; 2043 break; 2044 case PORT_SCIFA: 2045 port->fifosize = 64; 2046 break; 2047 case PORT_SCIF: 2048 port->fifosize = 16; 2049 break; 2050 default: 2051 port->fifosize = 1; 2052 break; 2053 } 2054 2055 if (p->regtype == SCIx_PROBE_REGTYPE) { 2056 ret = sci_probe_regmap(p); 2057 if (unlikely(ret)) 2058 return ret; 2059 } 2060 2061 if (dev) { 2062 sci_port->iclk = clk_get(&dev->dev, "sci_ick"); 2063 if (IS_ERR(sci_port->iclk)) { 2064 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk"); 2065 if (IS_ERR(sci_port->iclk)) { 2066 dev_err(&dev->dev, "can't get iclk\n"); 2067 return PTR_ERR(sci_port->iclk); 2068 } 2069 } 2070 2071 /* 2072 * The function clock is optional, ignore it if we can't 2073 * find it. 2074 */ 2075 sci_port->fclk = clk_get(&dev->dev, "sci_fck"); 2076 if (IS_ERR(sci_port->fclk)) 2077 sci_port->fclk = NULL; 2078 2079 port->dev = &dev->dev; 2080 2081 sci_init_gpios(sci_port); 2082 2083 pm_runtime_irq_safe(&dev->dev); 2084 pm_runtime_get_noresume(&dev->dev); 2085 pm_runtime_enable(&dev->dev); 2086 } 2087 2088 sci_port->break_timer.data = (unsigned long)sci_port; 2089 sci_port->break_timer.function = sci_break_timer; 2090 init_timer(&sci_port->break_timer); 2091 2092 /* 2093 * Establish some sensible defaults for the error detection. 2094 */ 2095 if (!p->error_mask) 2096 p->error_mask = (p->type == PORT_SCI) ? 2097 SCI_DEFAULT_ERROR_MASK : SCIF_DEFAULT_ERROR_MASK; 2098 2099 /* 2100 * Establish sensible defaults for the overrun detection, unless 2101 * the part has explicitly disabled support for it. 2102 */ 2103 if (p->overrun_bit != SCIx_NOT_SUPPORTED) { 2104 if (p->type == PORT_SCI) 2105 p->overrun_bit = 5; 2106 else if (p->scbrr_algo_id == SCBRR_ALGO_4) 2107 p->overrun_bit = 9; 2108 else 2109 p->overrun_bit = 0; 2110 2111 /* 2112 * Make the error mask inclusive of overrun detection, if 2113 * supported. 2114 */ 2115 p->error_mask |= (1 << p->overrun_bit); 2116 } 2117 2118 port->mapbase = p->mapbase; 2119 port->type = p->type; 2120 port->flags = p->flags; 2121 port->regshift = p->regshift; 2122 2123 /* 2124 * The UART port needs an IRQ value, so we peg this to the RX IRQ 2125 * for the multi-IRQ ports, which is where we are primarily 2126 * concerned with the shutdown path synchronization. 2127 * 2128 * For the muxed case there's nothing more to do. 2129 */ 2130 port->irq = p->irqs[SCIx_RXI_IRQ]; 2131 port->irqflags = 0; 2132 2133 port->serial_in = sci_serial_in; 2134 port->serial_out = sci_serial_out; 2135 2136 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0) 2137 dev_dbg(port->dev, "DMA tx %d, rx %d\n", 2138 p->dma_slave_tx, p->dma_slave_rx); 2139 2140 return 0; 2141 } 2142 2143 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE 2144 static void serial_console_putchar(struct uart_port *port, int ch) 2145 { 2146 sci_poll_put_char(port, ch); 2147 } 2148 2149 /* 2150 * Print a string to the serial port trying not to disturb 2151 * any possible real use of the port... 2152 */ 2153 static void serial_console_write(struct console *co, const char *s, 2154 unsigned count) 2155 { 2156 struct sci_port *sci_port = &sci_ports[co->index]; 2157 struct uart_port *port = &sci_port->port; 2158 unsigned short bits; 2159 2160 sci_port_enable(sci_port); 2161 2162 uart_console_write(port, s, count, serial_console_putchar); 2163 2164 /* wait until fifo is empty and last bit has been transmitted */ 2165 bits = SCxSR_TDxE(port) | SCxSR_TEND(port); 2166 while ((serial_port_in(port, SCxSR) & bits) != bits) 2167 cpu_relax(); 2168 2169 sci_port_disable(sci_port); 2170 } 2171 2172 static int __devinit serial_console_setup(struct console *co, char *options) 2173 { 2174 struct sci_port *sci_port; 2175 struct uart_port *port; 2176 int baud = 115200; 2177 int bits = 8; 2178 int parity = 'n'; 2179 int flow = 'n'; 2180 int ret; 2181 2182 /* 2183 * Refuse to handle any bogus ports. 2184 */ 2185 if (co->index < 0 || co->index >= SCI_NPORTS) 2186 return -ENODEV; 2187 2188 sci_port = &sci_ports[co->index]; 2189 port = &sci_port->port; 2190 2191 /* 2192 * Refuse to handle uninitialized ports. 2193 */ 2194 if (!port->ops) 2195 return -ENODEV; 2196 2197 ret = sci_remap_port(port); 2198 if (unlikely(ret != 0)) 2199 return ret; 2200 2201 sci_port_enable(sci_port); 2202 2203 if (options) 2204 uart_parse_options(options, &baud, &parity, &bits, &flow); 2205 2206 sci_port_disable(sci_port); 2207 2208 return uart_set_options(port, co, baud, parity, bits, flow); 2209 } 2210 2211 static struct console serial_console = { 2212 .name = "ttySC", 2213 .device = uart_console_device, 2214 .write = serial_console_write, 2215 .setup = serial_console_setup, 2216 .flags = CON_PRINTBUFFER, 2217 .index = -1, 2218 .data = &sci_uart_driver, 2219 }; 2220 2221 static struct console early_serial_console = { 2222 .name = "early_ttySC", 2223 .write = serial_console_write, 2224 .flags = CON_PRINTBUFFER, 2225 .index = -1, 2226 }; 2227 2228 static char early_serial_buf[32]; 2229 2230 static int __devinit sci_probe_earlyprintk(struct platform_device *pdev) 2231 { 2232 struct plat_sci_port *cfg = pdev->dev.platform_data; 2233 2234 if (early_serial_console.data) 2235 return -EEXIST; 2236 2237 early_serial_console.index = pdev->id; 2238 2239 sci_init_single(NULL, &sci_ports[pdev->id], pdev->id, cfg); 2240 2241 serial_console_setup(&early_serial_console, early_serial_buf); 2242 2243 if (!strstr(early_serial_buf, "keep")) 2244 early_serial_console.flags |= CON_BOOT; 2245 2246 register_console(&early_serial_console); 2247 return 0; 2248 } 2249 2250 #define uart_console(port) ((port)->cons->index == (port)->line) 2251 2252 static int sci_runtime_suspend(struct device *dev) 2253 { 2254 struct sci_port *sci_port = dev_get_drvdata(dev); 2255 struct uart_port *port = &sci_port->port; 2256 2257 if (uart_console(port)) { 2258 struct plat_sci_reg *reg; 2259 2260 sci_port->saved_smr = serial_port_in(port, SCSMR); 2261 sci_port->saved_brr = serial_port_in(port, SCBRR); 2262 2263 reg = sci_getreg(port, SCFCR); 2264 if (reg->size) 2265 sci_port->saved_fcr = serial_port_in(port, SCFCR); 2266 else 2267 sci_port->saved_fcr = 0; 2268 } 2269 return 0; 2270 } 2271 2272 static int sci_runtime_resume(struct device *dev) 2273 { 2274 struct sci_port *sci_port = dev_get_drvdata(dev); 2275 struct uart_port *port = &sci_port->port; 2276 2277 if (uart_console(port)) { 2278 sci_reset(port); 2279 serial_port_out(port, SCSMR, sci_port->saved_smr); 2280 serial_port_out(port, SCBRR, sci_port->saved_brr); 2281 2282 if (sci_port->saved_fcr) 2283 serial_port_out(port, SCFCR, sci_port->saved_fcr); 2284 2285 serial_port_out(port, SCSCR, sci_port->cfg->scscr); 2286 } 2287 return 0; 2288 } 2289 2290 #define SCI_CONSOLE (&serial_console) 2291 2292 #else 2293 static inline int __devinit sci_probe_earlyprintk(struct platform_device *pdev) 2294 { 2295 return -EINVAL; 2296 } 2297 2298 #define SCI_CONSOLE NULL 2299 #define sci_runtime_suspend NULL 2300 #define sci_runtime_resume NULL 2301 2302 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */ 2303 2304 static char banner[] __initdata = 2305 KERN_INFO "SuperH SCI(F) driver initialized\n"; 2306 2307 static struct uart_driver sci_uart_driver = { 2308 .owner = THIS_MODULE, 2309 .driver_name = "sci", 2310 .dev_name = "ttySC", 2311 .major = SCI_MAJOR, 2312 .minor = SCI_MINOR_START, 2313 .nr = SCI_NPORTS, 2314 .cons = SCI_CONSOLE, 2315 }; 2316 2317 static int sci_remove(struct platform_device *dev) 2318 { 2319 struct sci_port *port = platform_get_drvdata(dev); 2320 2321 cpufreq_unregister_notifier(&port->freq_transition, 2322 CPUFREQ_TRANSITION_NOTIFIER); 2323 2324 sci_free_gpios(port); 2325 2326 uart_remove_one_port(&sci_uart_driver, &port->port); 2327 2328 clk_put(port->iclk); 2329 clk_put(port->fclk); 2330 2331 pm_runtime_disable(&dev->dev); 2332 return 0; 2333 } 2334 2335 static int __devinit sci_probe_single(struct platform_device *dev, 2336 unsigned int index, 2337 struct plat_sci_port *p, 2338 struct sci_port *sciport) 2339 { 2340 int ret; 2341 2342 /* Sanity check */ 2343 if (unlikely(index >= SCI_NPORTS)) { 2344 dev_notice(&dev->dev, "Attempting to register port " 2345 "%d when only %d are available.\n", 2346 index+1, SCI_NPORTS); 2347 dev_notice(&dev->dev, "Consider bumping " 2348 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n"); 2349 return 0; 2350 } 2351 2352 ret = sci_init_single(dev, sciport, index, p); 2353 if (ret) 2354 return ret; 2355 2356 return uart_add_one_port(&sci_uart_driver, &sciport->port); 2357 } 2358 2359 static int __devinit sci_probe(struct platform_device *dev) 2360 { 2361 struct plat_sci_port *p = dev->dev.platform_data; 2362 struct sci_port *sp = &sci_ports[dev->id]; 2363 int ret; 2364 2365 /* 2366 * If we've come here via earlyprintk initialization, head off to 2367 * the special early probe. We don't have sufficient device state 2368 * to make it beyond this yet. 2369 */ 2370 if (is_early_platform_device(dev)) 2371 return sci_probe_earlyprintk(dev); 2372 2373 platform_set_drvdata(dev, sp); 2374 2375 ret = sci_probe_single(dev, dev->id, p, sp); 2376 if (ret) 2377 goto err_unreg; 2378 2379 sp->freq_transition.notifier_call = sci_notifier; 2380 2381 ret = cpufreq_register_notifier(&sp->freq_transition, 2382 CPUFREQ_TRANSITION_NOTIFIER); 2383 if (unlikely(ret < 0)) 2384 goto err_unreg; 2385 2386 #ifdef CONFIG_SH_STANDARD_BIOS 2387 sh_bios_gdb_detach(); 2388 #endif 2389 2390 return 0; 2391 2392 err_unreg: 2393 sci_remove(dev); 2394 return ret; 2395 } 2396 2397 static int sci_suspend(struct device *dev) 2398 { 2399 struct sci_port *sport = dev_get_drvdata(dev); 2400 2401 if (sport) 2402 uart_suspend_port(&sci_uart_driver, &sport->port); 2403 2404 return 0; 2405 } 2406 2407 static int sci_resume(struct device *dev) 2408 { 2409 struct sci_port *sport = dev_get_drvdata(dev); 2410 2411 if (sport) 2412 uart_resume_port(&sci_uart_driver, &sport->port); 2413 2414 return 0; 2415 } 2416 2417 static const struct dev_pm_ops sci_dev_pm_ops = { 2418 .runtime_suspend = sci_runtime_suspend, 2419 .runtime_resume = sci_runtime_resume, 2420 .suspend = sci_suspend, 2421 .resume = sci_resume, 2422 }; 2423 2424 static struct platform_driver sci_driver = { 2425 .probe = sci_probe, 2426 .remove = sci_remove, 2427 .driver = { 2428 .name = "sh-sci", 2429 .owner = THIS_MODULE, 2430 .pm = &sci_dev_pm_ops, 2431 }, 2432 }; 2433 2434 static int __init sci_init(void) 2435 { 2436 int ret; 2437 2438 printk(banner); 2439 2440 ret = uart_register_driver(&sci_uart_driver); 2441 if (likely(ret == 0)) { 2442 ret = platform_driver_register(&sci_driver); 2443 if (unlikely(ret)) 2444 uart_unregister_driver(&sci_uart_driver); 2445 } 2446 2447 return ret; 2448 } 2449 2450 static void __exit sci_exit(void) 2451 { 2452 platform_driver_unregister(&sci_driver); 2453 uart_unregister_driver(&sci_uart_driver); 2454 } 2455 2456 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE 2457 early_platform_init_buffer("earlyprintk", &sci_driver, 2458 early_serial_buf, ARRAY_SIZE(early_serial_buf)); 2459 #endif 2460 module_init(sci_init); 2461 module_exit(sci_exit); 2462 2463 MODULE_LICENSE("GPL"); 2464 MODULE_ALIAS("platform:sh-sci"); 2465 MODULE_AUTHOR("Paul Mundt"); 2466 MODULE_DESCRIPTION("SuperH SCI(F) serial driver"); 2467