1 /* 2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) 3 * 4 * Copyright (C) 2002 - 2011 Paul Mundt 5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007). 6 * 7 * based off of the old drivers/char/sh-sci.c by: 8 * 9 * Copyright (C) 1999, 2000 Niibe Yutaka 10 * Copyright (C) 2000 Sugioka Toshinobu 11 * Modified to support multiple serial ports. Stuart Menefy (May 2000). 12 * Modified to support SecureEdge. David McCullough (2002) 13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003). 14 * Removed SH7300 support (Jul 2007). 15 * 16 * This file is subject to the terms and conditions of the GNU General Public 17 * License. See the file "COPYING" in the main directory of this archive 18 * for more details. 19 */ 20 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 21 #define SUPPORT_SYSRQ 22 #endif 23 24 #undef DEBUG 25 26 #include <linux/module.h> 27 #include <linux/errno.h> 28 #include <linux/sh_dma.h> 29 #include <linux/timer.h> 30 #include <linux/interrupt.h> 31 #include <linux/tty.h> 32 #include <linux/tty_flip.h> 33 #include <linux/serial.h> 34 #include <linux/major.h> 35 #include <linux/string.h> 36 #include <linux/sysrq.h> 37 #include <linux/ioport.h> 38 #include <linux/mm.h> 39 #include <linux/init.h> 40 #include <linux/delay.h> 41 #include <linux/console.h> 42 #include <linux/platform_device.h> 43 #include <linux/serial_sci.h> 44 #include <linux/notifier.h> 45 #include <linux/pm_runtime.h> 46 #include <linux/cpufreq.h> 47 #include <linux/clk.h> 48 #include <linux/ctype.h> 49 #include <linux/err.h> 50 #include <linux/dmaengine.h> 51 #include <linux/dma-mapping.h> 52 #include <linux/scatterlist.h> 53 #include <linux/slab.h> 54 #include <linux/gpio.h> 55 56 #ifdef CONFIG_SUPERH 57 #include <asm/sh_bios.h> 58 #endif 59 60 #include "sh-sci.h" 61 62 struct sci_port { 63 struct uart_port port; 64 65 /* Platform configuration */ 66 struct plat_sci_port *cfg; 67 68 /* Break timer */ 69 struct timer_list break_timer; 70 int break_flag; 71 72 /* Interface clock */ 73 struct clk *iclk; 74 /* Function clock */ 75 struct clk *fclk; 76 77 char *irqstr[SCIx_NR_IRQS]; 78 char *gpiostr[SCIx_NR_FNS]; 79 80 struct dma_chan *chan_tx; 81 struct dma_chan *chan_rx; 82 83 #ifdef CONFIG_SERIAL_SH_SCI_DMA 84 struct dma_async_tx_descriptor *desc_tx; 85 struct dma_async_tx_descriptor *desc_rx[2]; 86 dma_cookie_t cookie_tx; 87 dma_cookie_t cookie_rx[2]; 88 dma_cookie_t active_rx; 89 struct scatterlist sg_tx; 90 unsigned int sg_len_tx; 91 struct scatterlist sg_rx[2]; 92 size_t buf_len_rx; 93 struct sh_dmae_slave param_tx; 94 struct sh_dmae_slave param_rx; 95 struct work_struct work_tx; 96 struct work_struct work_rx; 97 struct timer_list rx_timer; 98 unsigned int rx_timeout; 99 #endif 100 101 struct notifier_block freq_transition; 102 }; 103 104 /* Function prototypes */ 105 static void sci_start_tx(struct uart_port *port); 106 static void sci_stop_tx(struct uart_port *port); 107 static void sci_start_rx(struct uart_port *port); 108 109 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS 110 111 static struct sci_port sci_ports[SCI_NPORTS]; 112 static struct uart_driver sci_uart_driver; 113 114 static inline struct sci_port * 115 to_sci_port(struct uart_port *uart) 116 { 117 return container_of(uart, struct sci_port, port); 118 } 119 120 struct plat_sci_reg { 121 u8 offset, size; 122 }; 123 124 /* Helper for invalidating specific entries of an inherited map. */ 125 #define sci_reg_invalid { .offset = 0, .size = 0 } 126 127 static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { 128 [SCIx_PROBE_REGTYPE] = { 129 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid, 130 }, 131 132 /* 133 * Common SCI definitions, dependent on the port's regshift 134 * value. 135 */ 136 [SCIx_SCI_REGTYPE] = { 137 [SCSMR] = { 0x00, 8 }, 138 [SCBRR] = { 0x01, 8 }, 139 [SCSCR] = { 0x02, 8 }, 140 [SCxTDR] = { 0x03, 8 }, 141 [SCxSR] = { 0x04, 8 }, 142 [SCxRDR] = { 0x05, 8 }, 143 [SCFCR] = sci_reg_invalid, 144 [SCFDR] = sci_reg_invalid, 145 [SCTFDR] = sci_reg_invalid, 146 [SCRFDR] = sci_reg_invalid, 147 [SCSPTR] = sci_reg_invalid, 148 [SCLSR] = sci_reg_invalid, 149 }, 150 151 /* 152 * Common definitions for legacy IrDA ports, dependent on 153 * regshift value. 154 */ 155 [SCIx_IRDA_REGTYPE] = { 156 [SCSMR] = { 0x00, 8 }, 157 [SCBRR] = { 0x01, 8 }, 158 [SCSCR] = { 0x02, 8 }, 159 [SCxTDR] = { 0x03, 8 }, 160 [SCxSR] = { 0x04, 8 }, 161 [SCxRDR] = { 0x05, 8 }, 162 [SCFCR] = { 0x06, 8 }, 163 [SCFDR] = { 0x07, 16 }, 164 [SCTFDR] = sci_reg_invalid, 165 [SCRFDR] = sci_reg_invalid, 166 [SCSPTR] = sci_reg_invalid, 167 [SCLSR] = sci_reg_invalid, 168 }, 169 170 /* 171 * Common SCIFA definitions. 172 */ 173 [SCIx_SCIFA_REGTYPE] = { 174 [SCSMR] = { 0x00, 16 }, 175 [SCBRR] = { 0x04, 8 }, 176 [SCSCR] = { 0x08, 16 }, 177 [SCxTDR] = { 0x20, 8 }, 178 [SCxSR] = { 0x14, 16 }, 179 [SCxRDR] = { 0x24, 8 }, 180 [SCFCR] = { 0x18, 16 }, 181 [SCFDR] = { 0x1c, 16 }, 182 [SCTFDR] = sci_reg_invalid, 183 [SCRFDR] = sci_reg_invalid, 184 [SCSPTR] = sci_reg_invalid, 185 [SCLSR] = sci_reg_invalid, 186 }, 187 188 /* 189 * Common SCIFB definitions. 190 */ 191 [SCIx_SCIFB_REGTYPE] = { 192 [SCSMR] = { 0x00, 16 }, 193 [SCBRR] = { 0x04, 8 }, 194 [SCSCR] = { 0x08, 16 }, 195 [SCxTDR] = { 0x40, 8 }, 196 [SCxSR] = { 0x14, 16 }, 197 [SCxRDR] = { 0x60, 8 }, 198 [SCFCR] = { 0x18, 16 }, 199 [SCFDR] = sci_reg_invalid, 200 [SCTFDR] = { 0x38, 16 }, 201 [SCRFDR] = { 0x3c, 16 }, 202 [SCSPTR] = sci_reg_invalid, 203 [SCLSR] = sci_reg_invalid, 204 }, 205 206 /* 207 * Common SH-2(A) SCIF definitions for ports with FIFO data 208 * count registers. 209 */ 210 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = { 211 [SCSMR] = { 0x00, 16 }, 212 [SCBRR] = { 0x04, 8 }, 213 [SCSCR] = { 0x08, 16 }, 214 [SCxTDR] = { 0x0c, 8 }, 215 [SCxSR] = { 0x10, 16 }, 216 [SCxRDR] = { 0x14, 8 }, 217 [SCFCR] = { 0x18, 16 }, 218 [SCFDR] = { 0x1c, 16 }, 219 [SCTFDR] = sci_reg_invalid, 220 [SCRFDR] = sci_reg_invalid, 221 [SCSPTR] = { 0x20, 16 }, 222 [SCLSR] = { 0x24, 16 }, 223 }, 224 225 /* 226 * Common SH-3 SCIF definitions. 227 */ 228 [SCIx_SH3_SCIF_REGTYPE] = { 229 [SCSMR] = { 0x00, 8 }, 230 [SCBRR] = { 0x02, 8 }, 231 [SCSCR] = { 0x04, 8 }, 232 [SCxTDR] = { 0x06, 8 }, 233 [SCxSR] = { 0x08, 16 }, 234 [SCxRDR] = { 0x0a, 8 }, 235 [SCFCR] = { 0x0c, 8 }, 236 [SCFDR] = { 0x0e, 16 }, 237 [SCTFDR] = sci_reg_invalid, 238 [SCRFDR] = sci_reg_invalid, 239 [SCSPTR] = sci_reg_invalid, 240 [SCLSR] = sci_reg_invalid, 241 }, 242 243 /* 244 * Common SH-4(A) SCIF(B) definitions. 245 */ 246 [SCIx_SH4_SCIF_REGTYPE] = { 247 [SCSMR] = { 0x00, 16 }, 248 [SCBRR] = { 0x04, 8 }, 249 [SCSCR] = { 0x08, 16 }, 250 [SCxTDR] = { 0x0c, 8 }, 251 [SCxSR] = { 0x10, 16 }, 252 [SCxRDR] = { 0x14, 8 }, 253 [SCFCR] = { 0x18, 16 }, 254 [SCFDR] = { 0x1c, 16 }, 255 [SCTFDR] = sci_reg_invalid, 256 [SCRFDR] = sci_reg_invalid, 257 [SCSPTR] = { 0x20, 16 }, 258 [SCLSR] = { 0x24, 16 }, 259 }, 260 261 /* 262 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR 263 * register. 264 */ 265 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = { 266 [SCSMR] = { 0x00, 16 }, 267 [SCBRR] = { 0x04, 8 }, 268 [SCSCR] = { 0x08, 16 }, 269 [SCxTDR] = { 0x0c, 8 }, 270 [SCxSR] = { 0x10, 16 }, 271 [SCxRDR] = { 0x14, 8 }, 272 [SCFCR] = { 0x18, 16 }, 273 [SCFDR] = { 0x1c, 16 }, 274 [SCTFDR] = sci_reg_invalid, 275 [SCRFDR] = sci_reg_invalid, 276 [SCSPTR] = sci_reg_invalid, 277 [SCLSR] = { 0x24, 16 }, 278 }, 279 280 /* 281 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data 282 * count registers. 283 */ 284 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = { 285 [SCSMR] = { 0x00, 16 }, 286 [SCBRR] = { 0x04, 8 }, 287 [SCSCR] = { 0x08, 16 }, 288 [SCxTDR] = { 0x0c, 8 }, 289 [SCxSR] = { 0x10, 16 }, 290 [SCxRDR] = { 0x14, 8 }, 291 [SCFCR] = { 0x18, 16 }, 292 [SCFDR] = { 0x1c, 16 }, 293 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */ 294 [SCRFDR] = { 0x20, 16 }, 295 [SCSPTR] = { 0x24, 16 }, 296 [SCLSR] = { 0x28, 16 }, 297 }, 298 299 /* 300 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR 301 * registers. 302 */ 303 [SCIx_SH7705_SCIF_REGTYPE] = { 304 [SCSMR] = { 0x00, 16 }, 305 [SCBRR] = { 0x04, 8 }, 306 [SCSCR] = { 0x08, 16 }, 307 [SCxTDR] = { 0x20, 8 }, 308 [SCxSR] = { 0x14, 16 }, 309 [SCxRDR] = { 0x24, 8 }, 310 [SCFCR] = { 0x18, 16 }, 311 [SCFDR] = { 0x1c, 16 }, 312 [SCTFDR] = sci_reg_invalid, 313 [SCRFDR] = sci_reg_invalid, 314 [SCSPTR] = sci_reg_invalid, 315 [SCLSR] = sci_reg_invalid, 316 }, 317 }; 318 319 #define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset) 320 321 /* 322 * The "offset" here is rather misleading, in that it refers to an enum 323 * value relative to the port mapping rather than the fixed offset 324 * itself, which needs to be manually retrieved from the platform's 325 * register map for the given port. 326 */ 327 static unsigned int sci_serial_in(struct uart_port *p, int offset) 328 { 329 struct plat_sci_reg *reg = sci_getreg(p, offset); 330 331 if (reg->size == 8) 332 return ioread8(p->membase + (reg->offset << p->regshift)); 333 else if (reg->size == 16) 334 return ioread16(p->membase + (reg->offset << p->regshift)); 335 else 336 WARN(1, "Invalid register access\n"); 337 338 return 0; 339 } 340 341 static void sci_serial_out(struct uart_port *p, int offset, int value) 342 { 343 struct plat_sci_reg *reg = sci_getreg(p, offset); 344 345 if (reg->size == 8) 346 iowrite8(value, p->membase + (reg->offset << p->regshift)); 347 else if (reg->size == 16) 348 iowrite16(value, p->membase + (reg->offset << p->regshift)); 349 else 350 WARN(1, "Invalid register access\n"); 351 } 352 353 static int sci_probe_regmap(struct plat_sci_port *cfg) 354 { 355 switch (cfg->type) { 356 case PORT_SCI: 357 cfg->regtype = SCIx_SCI_REGTYPE; 358 break; 359 case PORT_IRDA: 360 cfg->regtype = SCIx_IRDA_REGTYPE; 361 break; 362 case PORT_SCIFA: 363 cfg->regtype = SCIx_SCIFA_REGTYPE; 364 break; 365 case PORT_SCIFB: 366 cfg->regtype = SCIx_SCIFB_REGTYPE; 367 break; 368 case PORT_SCIF: 369 /* 370 * The SH-4 is a bit of a misnomer here, although that's 371 * where this particular port layout originated. This 372 * configuration (or some slight variation thereof) 373 * remains the dominant model for all SCIFs. 374 */ 375 cfg->regtype = SCIx_SH4_SCIF_REGTYPE; 376 break; 377 default: 378 printk(KERN_ERR "Can't probe register map for given port\n"); 379 return -EINVAL; 380 } 381 382 return 0; 383 } 384 385 static void sci_port_enable(struct sci_port *sci_port) 386 { 387 if (!sci_port->port.dev) 388 return; 389 390 pm_runtime_get_sync(sci_port->port.dev); 391 392 clk_enable(sci_port->iclk); 393 sci_port->port.uartclk = clk_get_rate(sci_port->iclk); 394 clk_enable(sci_port->fclk); 395 } 396 397 static void sci_port_disable(struct sci_port *sci_port) 398 { 399 if (!sci_port->port.dev) 400 return; 401 402 clk_disable(sci_port->fclk); 403 clk_disable(sci_port->iclk); 404 405 pm_runtime_put_sync(sci_port->port.dev); 406 } 407 408 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) 409 410 #ifdef CONFIG_CONSOLE_POLL 411 static int sci_poll_get_char(struct uart_port *port) 412 { 413 unsigned short status; 414 int c; 415 416 do { 417 status = serial_port_in(port, SCxSR); 418 if (status & SCxSR_ERRORS(port)) { 419 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port)); 420 continue; 421 } 422 break; 423 } while (1); 424 425 if (!(status & SCxSR_RDxF(port))) 426 return NO_POLL_CHAR; 427 428 c = serial_port_in(port, SCxRDR); 429 430 /* Dummy read */ 431 serial_port_in(port, SCxSR); 432 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); 433 434 return c; 435 } 436 #endif 437 438 static void sci_poll_put_char(struct uart_port *port, unsigned char c) 439 { 440 unsigned short status; 441 442 do { 443 status = serial_port_in(port, SCxSR); 444 } while (!(status & SCxSR_TDxE(port))); 445 446 serial_port_out(port, SCxTDR, c); 447 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port)); 448 } 449 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */ 450 451 static void sci_init_pins(struct uart_port *port, unsigned int cflag) 452 { 453 struct sci_port *s = to_sci_port(port); 454 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR; 455 456 /* 457 * Use port-specific handler if provided. 458 */ 459 if (s->cfg->ops && s->cfg->ops->init_pins) { 460 s->cfg->ops->init_pins(port, cflag); 461 return; 462 } 463 464 /* 465 * For the generic path SCSPTR is necessary. Bail out if that's 466 * unavailable, too. 467 */ 468 if (!reg->size) 469 return; 470 471 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) && 472 ((!(cflag & CRTSCTS)))) { 473 unsigned short status; 474 475 status = serial_port_in(port, SCSPTR); 476 status &= ~SCSPTR_CTSIO; 477 status |= SCSPTR_RTSIO; 478 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */ 479 } 480 } 481 482 static int sci_txfill(struct uart_port *port) 483 { 484 struct plat_sci_reg *reg; 485 486 reg = sci_getreg(port, SCTFDR); 487 if (reg->size) 488 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1); 489 490 reg = sci_getreg(port, SCFDR); 491 if (reg->size) 492 return serial_port_in(port, SCFDR) >> 8; 493 494 return !(serial_port_in(port, SCxSR) & SCI_TDRE); 495 } 496 497 static int sci_txroom(struct uart_port *port) 498 { 499 return port->fifosize - sci_txfill(port); 500 } 501 502 static int sci_rxfill(struct uart_port *port) 503 { 504 struct plat_sci_reg *reg; 505 506 reg = sci_getreg(port, SCRFDR); 507 if (reg->size) 508 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1); 509 510 reg = sci_getreg(port, SCFDR); 511 if (reg->size) 512 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1); 513 514 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0; 515 } 516 517 /* 518 * SCI helper for checking the state of the muxed port/RXD pins. 519 */ 520 static inline int sci_rxd_in(struct uart_port *port) 521 { 522 struct sci_port *s = to_sci_port(port); 523 524 if (s->cfg->port_reg <= 0) 525 return 1; 526 527 /* Cast for ARM damage */ 528 return !!__raw_readb((void __iomem *)s->cfg->port_reg); 529 } 530 531 /* ********************************************************************** * 532 * the interrupt related routines * 533 * ********************************************************************** */ 534 535 static void sci_transmit_chars(struct uart_port *port) 536 { 537 struct circ_buf *xmit = &port->state->xmit; 538 unsigned int stopped = uart_tx_stopped(port); 539 unsigned short status; 540 unsigned short ctrl; 541 int count; 542 543 status = serial_port_in(port, SCxSR); 544 if (!(status & SCxSR_TDxE(port))) { 545 ctrl = serial_port_in(port, SCSCR); 546 if (uart_circ_empty(xmit)) 547 ctrl &= ~SCSCR_TIE; 548 else 549 ctrl |= SCSCR_TIE; 550 serial_port_out(port, SCSCR, ctrl); 551 return; 552 } 553 554 count = sci_txroom(port); 555 556 do { 557 unsigned char c; 558 559 if (port->x_char) { 560 c = port->x_char; 561 port->x_char = 0; 562 } else if (!uart_circ_empty(xmit) && !stopped) { 563 c = xmit->buf[xmit->tail]; 564 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 565 } else { 566 break; 567 } 568 569 serial_port_out(port, SCxTDR, c); 570 571 port->icount.tx++; 572 } while (--count > 0); 573 574 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); 575 576 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 577 uart_write_wakeup(port); 578 if (uart_circ_empty(xmit)) { 579 sci_stop_tx(port); 580 } else { 581 ctrl = serial_port_in(port, SCSCR); 582 583 if (port->type != PORT_SCI) { 584 serial_port_in(port, SCxSR); /* Dummy read */ 585 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); 586 } 587 588 ctrl |= SCSCR_TIE; 589 serial_port_out(port, SCSCR, ctrl); 590 } 591 } 592 593 /* On SH3, SCIF may read end-of-break as a space->mark char */ 594 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); }) 595 596 static void sci_receive_chars(struct uart_port *port) 597 { 598 struct sci_port *sci_port = to_sci_port(port); 599 struct tty_port *tport = &port->state->port; 600 int i, count, copied = 0; 601 unsigned short status; 602 unsigned char flag; 603 604 status = serial_port_in(port, SCxSR); 605 if (!(status & SCxSR_RDxF(port))) 606 return; 607 608 while (1) { 609 /* Don't copy more bytes than there is room for in the buffer */ 610 count = tty_buffer_request_room(tport, sci_rxfill(port)); 611 612 /* If for any reason we can't copy more data, we're done! */ 613 if (count == 0) 614 break; 615 616 if (port->type == PORT_SCI) { 617 char c = serial_port_in(port, SCxRDR); 618 if (uart_handle_sysrq_char(port, c) || 619 sci_port->break_flag) 620 count = 0; 621 else 622 tty_insert_flip_char(tport, c, TTY_NORMAL); 623 } else { 624 for (i = 0; i < count; i++) { 625 char c = serial_port_in(port, SCxRDR); 626 627 status = serial_port_in(port, SCxSR); 628 #if defined(CONFIG_CPU_SH3) 629 /* Skip "chars" during break */ 630 if (sci_port->break_flag) { 631 if ((c == 0) && 632 (status & SCxSR_FER(port))) { 633 count--; i--; 634 continue; 635 } 636 637 /* Nonzero => end-of-break */ 638 dev_dbg(port->dev, "debounce<%02x>\n", c); 639 sci_port->break_flag = 0; 640 641 if (STEPFN(c)) { 642 count--; i--; 643 continue; 644 } 645 } 646 #endif /* CONFIG_CPU_SH3 */ 647 if (uart_handle_sysrq_char(port, c)) { 648 count--; i--; 649 continue; 650 } 651 652 /* Store data and status */ 653 if (status & SCxSR_FER(port)) { 654 flag = TTY_FRAME; 655 port->icount.frame++; 656 dev_notice(port->dev, "frame error\n"); 657 } else if (status & SCxSR_PER(port)) { 658 flag = TTY_PARITY; 659 port->icount.parity++; 660 dev_notice(port->dev, "parity error\n"); 661 } else 662 flag = TTY_NORMAL; 663 664 tty_insert_flip_char(tport, c, flag); 665 } 666 } 667 668 serial_port_in(port, SCxSR); /* dummy read */ 669 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); 670 671 copied += count; 672 port->icount.rx += count; 673 } 674 675 if (copied) { 676 /* Tell the rest of the system the news. New characters! */ 677 tty_flip_buffer_push(tport); 678 } else { 679 serial_port_in(port, SCxSR); /* dummy read */ 680 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); 681 } 682 } 683 684 #define SCI_BREAK_JIFFIES (HZ/20) 685 686 /* 687 * The sci generates interrupts during the break, 688 * 1 per millisecond or so during the break period, for 9600 baud. 689 * So dont bother disabling interrupts. 690 * But dont want more than 1 break event. 691 * Use a kernel timer to periodically poll the rx line until 692 * the break is finished. 693 */ 694 static inline void sci_schedule_break_timer(struct sci_port *port) 695 { 696 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES); 697 } 698 699 /* Ensure that two consecutive samples find the break over. */ 700 static void sci_break_timer(unsigned long data) 701 { 702 struct sci_port *port = (struct sci_port *)data; 703 704 sci_port_enable(port); 705 706 if (sci_rxd_in(&port->port) == 0) { 707 port->break_flag = 1; 708 sci_schedule_break_timer(port); 709 } else if (port->break_flag == 1) { 710 /* break is over. */ 711 port->break_flag = 2; 712 sci_schedule_break_timer(port); 713 } else 714 port->break_flag = 0; 715 716 sci_port_disable(port); 717 } 718 719 static int sci_handle_errors(struct uart_port *port) 720 { 721 int copied = 0; 722 unsigned short status = serial_port_in(port, SCxSR); 723 struct tty_port *tport = &port->state->port; 724 struct sci_port *s = to_sci_port(port); 725 726 /* 727 * Handle overruns, if supported. 728 */ 729 if (s->cfg->overrun_bit != SCIx_NOT_SUPPORTED) { 730 if (status & (1 << s->cfg->overrun_bit)) { 731 port->icount.overrun++; 732 733 /* overrun error */ 734 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN)) 735 copied++; 736 737 dev_notice(port->dev, "overrun error"); 738 } 739 } 740 741 if (status & SCxSR_FER(port)) { 742 if (sci_rxd_in(port) == 0) { 743 /* Notify of BREAK */ 744 struct sci_port *sci_port = to_sci_port(port); 745 746 if (!sci_port->break_flag) { 747 port->icount.brk++; 748 749 sci_port->break_flag = 1; 750 sci_schedule_break_timer(sci_port); 751 752 /* Do sysrq handling. */ 753 if (uart_handle_break(port)) 754 return 0; 755 756 dev_dbg(port->dev, "BREAK detected\n"); 757 758 if (tty_insert_flip_char(tport, 0, TTY_BREAK)) 759 copied++; 760 } 761 762 } else { 763 /* frame error */ 764 port->icount.frame++; 765 766 if (tty_insert_flip_char(tport, 0, TTY_FRAME)) 767 copied++; 768 769 dev_notice(port->dev, "frame error\n"); 770 } 771 } 772 773 if (status & SCxSR_PER(port)) { 774 /* parity error */ 775 port->icount.parity++; 776 777 if (tty_insert_flip_char(tport, 0, TTY_PARITY)) 778 copied++; 779 780 dev_notice(port->dev, "parity error"); 781 } 782 783 if (copied) 784 tty_flip_buffer_push(tport); 785 786 return copied; 787 } 788 789 static int sci_handle_fifo_overrun(struct uart_port *port) 790 { 791 struct tty_port *tport = &port->state->port; 792 struct sci_port *s = to_sci_port(port); 793 struct plat_sci_reg *reg; 794 int copied = 0; 795 796 reg = sci_getreg(port, SCLSR); 797 if (!reg->size) 798 return 0; 799 800 if ((serial_port_in(port, SCLSR) & (1 << s->cfg->overrun_bit))) { 801 serial_port_out(port, SCLSR, 0); 802 803 port->icount.overrun++; 804 805 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 806 tty_flip_buffer_push(tport); 807 808 dev_notice(port->dev, "overrun error\n"); 809 copied++; 810 } 811 812 return copied; 813 } 814 815 static int sci_handle_breaks(struct uart_port *port) 816 { 817 int copied = 0; 818 unsigned short status = serial_port_in(port, SCxSR); 819 struct tty_port *tport = &port->state->port; 820 struct sci_port *s = to_sci_port(port); 821 822 if (uart_handle_break(port)) 823 return 0; 824 825 if (!s->break_flag && status & SCxSR_BRK(port)) { 826 #if defined(CONFIG_CPU_SH3) 827 /* Debounce break */ 828 s->break_flag = 1; 829 #endif 830 831 port->icount.brk++; 832 833 /* Notify of BREAK */ 834 if (tty_insert_flip_char(tport, 0, TTY_BREAK)) 835 copied++; 836 837 dev_dbg(port->dev, "BREAK detected\n"); 838 } 839 840 if (copied) 841 tty_flip_buffer_push(tport); 842 843 copied += sci_handle_fifo_overrun(port); 844 845 return copied; 846 } 847 848 static irqreturn_t sci_rx_interrupt(int irq, void *ptr) 849 { 850 #ifdef CONFIG_SERIAL_SH_SCI_DMA 851 struct uart_port *port = ptr; 852 struct sci_port *s = to_sci_port(port); 853 854 if (s->chan_rx) { 855 u16 scr = serial_port_in(port, SCSCR); 856 u16 ssr = serial_port_in(port, SCxSR); 857 858 /* Disable future Rx interrupts */ 859 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 860 disable_irq_nosync(irq); 861 scr |= 0x4000; 862 } else { 863 scr &= ~SCSCR_RIE; 864 } 865 serial_port_out(port, SCSCR, scr); 866 /* Clear current interrupt */ 867 serial_port_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port))); 868 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n", 869 jiffies, s->rx_timeout); 870 mod_timer(&s->rx_timer, jiffies + s->rx_timeout); 871 872 return IRQ_HANDLED; 873 } 874 #endif 875 876 /* I think sci_receive_chars has to be called irrespective 877 * of whether the I_IXOFF is set, otherwise, how is the interrupt 878 * to be disabled? 879 */ 880 sci_receive_chars(ptr); 881 882 return IRQ_HANDLED; 883 } 884 885 static irqreturn_t sci_tx_interrupt(int irq, void *ptr) 886 { 887 struct uart_port *port = ptr; 888 unsigned long flags; 889 890 spin_lock_irqsave(&port->lock, flags); 891 sci_transmit_chars(port); 892 spin_unlock_irqrestore(&port->lock, flags); 893 894 return IRQ_HANDLED; 895 } 896 897 static irqreturn_t sci_er_interrupt(int irq, void *ptr) 898 { 899 struct uart_port *port = ptr; 900 901 /* Handle errors */ 902 if (port->type == PORT_SCI) { 903 if (sci_handle_errors(port)) { 904 /* discard character in rx buffer */ 905 serial_port_in(port, SCxSR); 906 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); 907 } 908 } else { 909 sci_handle_fifo_overrun(port); 910 sci_rx_interrupt(irq, ptr); 911 } 912 913 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port)); 914 915 /* Kick the transmission */ 916 sci_tx_interrupt(irq, ptr); 917 918 return IRQ_HANDLED; 919 } 920 921 static irqreturn_t sci_br_interrupt(int irq, void *ptr) 922 { 923 struct uart_port *port = ptr; 924 925 /* Handle BREAKs */ 926 sci_handle_breaks(port); 927 serial_port_out(port, SCxSR, SCxSR_BREAK_CLEAR(port)); 928 929 return IRQ_HANDLED; 930 } 931 932 static inline unsigned long port_rx_irq_mask(struct uart_port *port) 933 { 934 /* 935 * Not all ports (such as SCIFA) will support REIE. Rather than 936 * special-casing the port type, we check the port initialization 937 * IRQ enable mask to see whether the IRQ is desired at all. If 938 * it's unset, it's logically inferred that there's no point in 939 * testing for it. 940 */ 941 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE); 942 } 943 944 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) 945 { 946 unsigned short ssr_status, scr_status, err_enabled; 947 struct uart_port *port = ptr; 948 struct sci_port *s = to_sci_port(port); 949 irqreturn_t ret = IRQ_NONE; 950 951 ssr_status = serial_port_in(port, SCxSR); 952 scr_status = serial_port_in(port, SCSCR); 953 err_enabled = scr_status & port_rx_irq_mask(port); 954 955 /* Tx Interrupt */ 956 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) && 957 !s->chan_tx) 958 ret = sci_tx_interrupt(irq, ptr); 959 960 /* 961 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF / 962 * DR flags 963 */ 964 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) && 965 (scr_status & SCSCR_RIE)) 966 ret = sci_rx_interrupt(irq, ptr); 967 968 /* Error Interrupt */ 969 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled) 970 ret = sci_er_interrupt(irq, ptr); 971 972 /* Break Interrupt */ 973 if ((ssr_status & SCxSR_BRK(port)) && err_enabled) 974 ret = sci_br_interrupt(irq, ptr); 975 976 return ret; 977 } 978 979 /* 980 * Here we define a transition notifier so that we can update all of our 981 * ports' baud rate when the peripheral clock changes. 982 */ 983 static int sci_notifier(struct notifier_block *self, 984 unsigned long phase, void *p) 985 { 986 struct sci_port *sci_port; 987 unsigned long flags; 988 989 sci_port = container_of(self, struct sci_port, freq_transition); 990 991 if ((phase == CPUFREQ_POSTCHANGE) || 992 (phase == CPUFREQ_RESUMECHANGE)) { 993 struct uart_port *port = &sci_port->port; 994 995 spin_lock_irqsave(&port->lock, flags); 996 port->uartclk = clk_get_rate(sci_port->iclk); 997 spin_unlock_irqrestore(&port->lock, flags); 998 } 999 1000 return NOTIFY_OK; 1001 } 1002 1003 static struct sci_irq_desc { 1004 const char *desc; 1005 irq_handler_t handler; 1006 } sci_irq_desc[] = { 1007 /* 1008 * Split out handlers, the default case. 1009 */ 1010 [SCIx_ERI_IRQ] = { 1011 .desc = "rx err", 1012 .handler = sci_er_interrupt, 1013 }, 1014 1015 [SCIx_RXI_IRQ] = { 1016 .desc = "rx full", 1017 .handler = sci_rx_interrupt, 1018 }, 1019 1020 [SCIx_TXI_IRQ] = { 1021 .desc = "tx empty", 1022 .handler = sci_tx_interrupt, 1023 }, 1024 1025 [SCIx_BRI_IRQ] = { 1026 .desc = "break", 1027 .handler = sci_br_interrupt, 1028 }, 1029 1030 /* 1031 * Special muxed handler. 1032 */ 1033 [SCIx_MUX_IRQ] = { 1034 .desc = "mux", 1035 .handler = sci_mpxed_interrupt, 1036 }, 1037 }; 1038 1039 static int sci_request_irq(struct sci_port *port) 1040 { 1041 struct uart_port *up = &port->port; 1042 int i, j, ret = 0; 1043 1044 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) { 1045 struct sci_irq_desc *desc; 1046 unsigned int irq; 1047 1048 if (SCIx_IRQ_IS_MUXED(port)) { 1049 i = SCIx_MUX_IRQ; 1050 irq = up->irq; 1051 } else { 1052 irq = port->cfg->irqs[i]; 1053 1054 /* 1055 * Certain port types won't support all of the 1056 * available interrupt sources. 1057 */ 1058 if (unlikely(!irq)) 1059 continue; 1060 } 1061 1062 desc = sci_irq_desc + i; 1063 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s", 1064 dev_name(up->dev), desc->desc); 1065 if (!port->irqstr[j]) { 1066 dev_err(up->dev, "Failed to allocate %s IRQ string\n", 1067 desc->desc); 1068 goto out_nomem; 1069 } 1070 1071 ret = request_irq(irq, desc->handler, up->irqflags, 1072 port->irqstr[j], port); 1073 if (unlikely(ret)) { 1074 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc); 1075 goto out_noirq; 1076 } 1077 } 1078 1079 return 0; 1080 1081 out_noirq: 1082 while (--i >= 0) 1083 free_irq(port->cfg->irqs[i], port); 1084 1085 out_nomem: 1086 while (--j >= 0) 1087 kfree(port->irqstr[j]); 1088 1089 return ret; 1090 } 1091 1092 static void sci_free_irq(struct sci_port *port) 1093 { 1094 int i; 1095 1096 /* 1097 * Intentionally in reverse order so we iterate over the muxed 1098 * IRQ first. 1099 */ 1100 for (i = 0; i < SCIx_NR_IRQS; i++) { 1101 unsigned int irq = port->cfg->irqs[i]; 1102 1103 /* 1104 * Certain port types won't support all of the available 1105 * interrupt sources. 1106 */ 1107 if (unlikely(!irq)) 1108 continue; 1109 1110 free_irq(port->cfg->irqs[i], port); 1111 kfree(port->irqstr[i]); 1112 1113 if (SCIx_IRQ_IS_MUXED(port)) { 1114 /* If there's only one IRQ, we're done. */ 1115 return; 1116 } 1117 } 1118 } 1119 1120 static const char *sci_gpio_names[SCIx_NR_FNS] = { 1121 "sck", "rxd", "txd", "cts", "rts", 1122 }; 1123 1124 static const char *sci_gpio_str(unsigned int index) 1125 { 1126 return sci_gpio_names[index]; 1127 } 1128 1129 static void sci_init_gpios(struct sci_port *port) 1130 { 1131 struct uart_port *up = &port->port; 1132 int i; 1133 1134 if (!port->cfg) 1135 return; 1136 1137 for (i = 0; i < SCIx_NR_FNS; i++) { 1138 const char *desc; 1139 int ret; 1140 1141 if (!port->cfg->gpios[i]) 1142 continue; 1143 1144 desc = sci_gpio_str(i); 1145 1146 port->gpiostr[i] = kasprintf(GFP_KERNEL, "%s:%s", 1147 dev_name(up->dev), desc); 1148 1149 /* 1150 * If we've failed the allocation, we can still continue 1151 * on with a NULL string. 1152 */ 1153 if (!port->gpiostr[i]) 1154 dev_notice(up->dev, "%s string allocation failure\n", 1155 desc); 1156 1157 ret = gpio_request(port->cfg->gpios[i], port->gpiostr[i]); 1158 if (unlikely(ret != 0)) { 1159 dev_notice(up->dev, "failed %s gpio request\n", desc); 1160 1161 /* 1162 * If we can't get the GPIO for whatever reason, 1163 * no point in keeping the verbose string around. 1164 */ 1165 kfree(port->gpiostr[i]); 1166 } 1167 } 1168 } 1169 1170 static void sci_free_gpios(struct sci_port *port) 1171 { 1172 int i; 1173 1174 for (i = 0; i < SCIx_NR_FNS; i++) 1175 if (port->cfg->gpios[i]) { 1176 gpio_free(port->cfg->gpios[i]); 1177 kfree(port->gpiostr[i]); 1178 } 1179 } 1180 1181 static unsigned int sci_tx_empty(struct uart_port *port) 1182 { 1183 unsigned short status = serial_port_in(port, SCxSR); 1184 unsigned short in_tx_fifo = sci_txfill(port); 1185 1186 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0; 1187 } 1188 1189 /* 1190 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally 1191 * CTS/RTS is supported in hardware by at least one port and controlled 1192 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently 1193 * handled via the ->init_pins() op, which is a bit of a one-way street, 1194 * lacking any ability to defer pin control -- this will later be 1195 * converted over to the GPIO framework). 1196 * 1197 * Other modes (such as loopback) are supported generically on certain 1198 * port types, but not others. For these it's sufficient to test for the 1199 * existence of the support register and simply ignore the port type. 1200 */ 1201 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) 1202 { 1203 if (mctrl & TIOCM_LOOP) { 1204 struct plat_sci_reg *reg; 1205 1206 /* 1207 * Standard loopback mode for SCFCR ports. 1208 */ 1209 reg = sci_getreg(port, SCFCR); 1210 if (reg->size) 1211 serial_port_out(port, SCFCR, serial_port_in(port, SCFCR) | 1); 1212 } 1213 } 1214 1215 static unsigned int sci_get_mctrl(struct uart_port *port) 1216 { 1217 /* 1218 * CTS/RTS is handled in hardware when supported, while nothing 1219 * else is wired up. Keep it simple and simply assert DSR/CAR. 1220 */ 1221 return TIOCM_DSR | TIOCM_CAR; 1222 } 1223 1224 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1225 static void sci_dma_tx_complete(void *arg) 1226 { 1227 struct sci_port *s = arg; 1228 struct uart_port *port = &s->port; 1229 struct circ_buf *xmit = &port->state->xmit; 1230 unsigned long flags; 1231 1232 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1233 1234 spin_lock_irqsave(&port->lock, flags); 1235 1236 xmit->tail += sg_dma_len(&s->sg_tx); 1237 xmit->tail &= UART_XMIT_SIZE - 1; 1238 1239 port->icount.tx += sg_dma_len(&s->sg_tx); 1240 1241 async_tx_ack(s->desc_tx); 1242 s->desc_tx = NULL; 1243 1244 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1245 uart_write_wakeup(port); 1246 1247 if (!uart_circ_empty(xmit)) { 1248 s->cookie_tx = 0; 1249 schedule_work(&s->work_tx); 1250 } else { 1251 s->cookie_tx = -EINVAL; 1252 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1253 u16 ctrl = serial_port_in(port, SCSCR); 1254 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE); 1255 } 1256 } 1257 1258 spin_unlock_irqrestore(&port->lock, flags); 1259 } 1260 1261 /* Locking: called with port lock held */ 1262 static int sci_dma_rx_push(struct sci_port *s, size_t count) 1263 { 1264 struct uart_port *port = &s->port; 1265 struct tty_port *tport = &port->state->port; 1266 int i, active, room; 1267 1268 room = tty_buffer_request_room(tport, count); 1269 1270 if (s->active_rx == s->cookie_rx[0]) { 1271 active = 0; 1272 } else if (s->active_rx == s->cookie_rx[1]) { 1273 active = 1; 1274 } else { 1275 dev_err(port->dev, "cookie %d not found!\n", s->active_rx); 1276 return 0; 1277 } 1278 1279 if (room < count) 1280 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n", 1281 count - room); 1282 if (!room) 1283 return room; 1284 1285 for (i = 0; i < room; i++) 1286 tty_insert_flip_char(tport, ((u8 *)sg_virt(&s->sg_rx[active]))[i], 1287 TTY_NORMAL); 1288 1289 port->icount.rx += room; 1290 1291 return room; 1292 } 1293 1294 static void sci_dma_rx_complete(void *arg) 1295 { 1296 struct sci_port *s = arg; 1297 struct uart_port *port = &s->port; 1298 unsigned long flags; 1299 int count; 1300 1301 dev_dbg(port->dev, "%s(%d) active #%d\n", __func__, port->line, s->active_rx); 1302 1303 spin_lock_irqsave(&port->lock, flags); 1304 1305 count = sci_dma_rx_push(s, s->buf_len_rx); 1306 1307 mod_timer(&s->rx_timer, jiffies + s->rx_timeout); 1308 1309 spin_unlock_irqrestore(&port->lock, flags); 1310 1311 if (count) 1312 tty_flip_buffer_push(&port->state->port); 1313 1314 schedule_work(&s->work_rx); 1315 } 1316 1317 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio) 1318 { 1319 struct dma_chan *chan = s->chan_rx; 1320 struct uart_port *port = &s->port; 1321 1322 s->chan_rx = NULL; 1323 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL; 1324 dma_release_channel(chan); 1325 if (sg_dma_address(&s->sg_rx[0])) 1326 dma_free_coherent(port->dev, s->buf_len_rx * 2, 1327 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0])); 1328 if (enable_pio) 1329 sci_start_rx(port); 1330 } 1331 1332 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio) 1333 { 1334 struct dma_chan *chan = s->chan_tx; 1335 struct uart_port *port = &s->port; 1336 1337 s->chan_tx = NULL; 1338 s->cookie_tx = -EINVAL; 1339 dma_release_channel(chan); 1340 if (enable_pio) 1341 sci_start_tx(port); 1342 } 1343 1344 static void sci_submit_rx(struct sci_port *s) 1345 { 1346 struct dma_chan *chan = s->chan_rx; 1347 int i; 1348 1349 for (i = 0; i < 2; i++) { 1350 struct scatterlist *sg = &s->sg_rx[i]; 1351 struct dma_async_tx_descriptor *desc; 1352 1353 desc = dmaengine_prep_slave_sg(chan, 1354 sg, 1, DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT); 1355 1356 if (desc) { 1357 s->desc_rx[i] = desc; 1358 desc->callback = sci_dma_rx_complete; 1359 desc->callback_param = s; 1360 s->cookie_rx[i] = desc->tx_submit(desc); 1361 } 1362 1363 if (!desc || s->cookie_rx[i] < 0) { 1364 if (i) { 1365 async_tx_ack(s->desc_rx[0]); 1366 s->cookie_rx[0] = -EINVAL; 1367 } 1368 if (desc) { 1369 async_tx_ack(desc); 1370 s->cookie_rx[i] = -EINVAL; 1371 } 1372 dev_warn(s->port.dev, 1373 "failed to re-start DMA, using PIO\n"); 1374 sci_rx_dma_release(s, true); 1375 return; 1376 } 1377 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__, 1378 s->cookie_rx[i], i); 1379 } 1380 1381 s->active_rx = s->cookie_rx[0]; 1382 1383 dma_async_issue_pending(chan); 1384 } 1385 1386 static void work_fn_rx(struct work_struct *work) 1387 { 1388 struct sci_port *s = container_of(work, struct sci_port, work_rx); 1389 struct uart_port *port = &s->port; 1390 struct dma_async_tx_descriptor *desc; 1391 int new; 1392 1393 if (s->active_rx == s->cookie_rx[0]) { 1394 new = 0; 1395 } else if (s->active_rx == s->cookie_rx[1]) { 1396 new = 1; 1397 } else { 1398 dev_err(port->dev, "cookie %d not found!\n", s->active_rx); 1399 return; 1400 } 1401 desc = s->desc_rx[new]; 1402 1403 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) != 1404 DMA_SUCCESS) { 1405 /* Handle incomplete DMA receive */ 1406 struct dma_chan *chan = s->chan_rx; 1407 struct shdma_desc *sh_desc = container_of(desc, 1408 struct shdma_desc, async_tx); 1409 unsigned long flags; 1410 int count; 1411 1412 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0); 1413 dev_dbg(port->dev, "Read %u bytes with cookie %d\n", 1414 sh_desc->partial, sh_desc->cookie); 1415 1416 spin_lock_irqsave(&port->lock, flags); 1417 count = sci_dma_rx_push(s, sh_desc->partial); 1418 spin_unlock_irqrestore(&port->lock, flags); 1419 1420 if (count) 1421 tty_flip_buffer_push(&port->state->port); 1422 1423 sci_submit_rx(s); 1424 1425 return; 1426 } 1427 1428 s->cookie_rx[new] = desc->tx_submit(desc); 1429 if (s->cookie_rx[new] < 0) { 1430 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n"); 1431 sci_rx_dma_release(s, true); 1432 return; 1433 } 1434 1435 s->active_rx = s->cookie_rx[!new]; 1436 1437 dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n", __func__, 1438 s->cookie_rx[new], new, s->active_rx); 1439 } 1440 1441 static void work_fn_tx(struct work_struct *work) 1442 { 1443 struct sci_port *s = container_of(work, struct sci_port, work_tx); 1444 struct dma_async_tx_descriptor *desc; 1445 struct dma_chan *chan = s->chan_tx; 1446 struct uart_port *port = &s->port; 1447 struct circ_buf *xmit = &port->state->xmit; 1448 struct scatterlist *sg = &s->sg_tx; 1449 1450 /* 1451 * DMA is idle now. 1452 * Port xmit buffer is already mapped, and it is one page... Just adjust 1453 * offsets and lengths. Since it is a circular buffer, we have to 1454 * transmit till the end, and then the rest. Take the port lock to get a 1455 * consistent xmit buffer state. 1456 */ 1457 spin_lock_irq(&port->lock); 1458 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1); 1459 sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) + 1460 sg->offset; 1461 sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE), 1462 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE)); 1463 spin_unlock_irq(&port->lock); 1464 1465 BUG_ON(!sg_dma_len(sg)); 1466 1467 desc = dmaengine_prep_slave_sg(chan, 1468 sg, s->sg_len_tx, DMA_MEM_TO_DEV, 1469 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1470 if (!desc) { 1471 /* switch to PIO */ 1472 sci_tx_dma_release(s, true); 1473 return; 1474 } 1475 1476 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE); 1477 1478 spin_lock_irq(&port->lock); 1479 s->desc_tx = desc; 1480 desc->callback = sci_dma_tx_complete; 1481 desc->callback_param = s; 1482 spin_unlock_irq(&port->lock); 1483 s->cookie_tx = desc->tx_submit(desc); 1484 if (s->cookie_tx < 0) { 1485 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n"); 1486 /* switch to PIO */ 1487 sci_tx_dma_release(s, true); 1488 return; 1489 } 1490 1491 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", __func__, 1492 xmit->buf, xmit->tail, xmit->head, s->cookie_tx); 1493 1494 dma_async_issue_pending(chan); 1495 } 1496 #endif 1497 1498 static void sci_start_tx(struct uart_port *port) 1499 { 1500 struct sci_port *s = to_sci_port(port); 1501 unsigned short ctrl; 1502 1503 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1504 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1505 u16 new, scr = serial_port_in(port, SCSCR); 1506 if (s->chan_tx) 1507 new = scr | 0x8000; 1508 else 1509 new = scr & ~0x8000; 1510 if (new != scr) 1511 serial_port_out(port, SCSCR, new); 1512 } 1513 1514 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) && 1515 s->cookie_tx < 0) { 1516 s->cookie_tx = 0; 1517 schedule_work(&s->work_tx); 1518 } 1519 #endif 1520 1521 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1522 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ 1523 ctrl = serial_port_in(port, SCSCR); 1524 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE); 1525 } 1526 } 1527 1528 static void sci_stop_tx(struct uart_port *port) 1529 { 1530 unsigned short ctrl; 1531 1532 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ 1533 ctrl = serial_port_in(port, SCSCR); 1534 1535 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1536 ctrl &= ~0x8000; 1537 1538 ctrl &= ~SCSCR_TIE; 1539 1540 serial_port_out(port, SCSCR, ctrl); 1541 } 1542 1543 static void sci_start_rx(struct uart_port *port) 1544 { 1545 unsigned short ctrl; 1546 1547 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port); 1548 1549 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1550 ctrl &= ~0x4000; 1551 1552 serial_port_out(port, SCSCR, ctrl); 1553 } 1554 1555 static void sci_stop_rx(struct uart_port *port) 1556 { 1557 unsigned short ctrl; 1558 1559 ctrl = serial_port_in(port, SCSCR); 1560 1561 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1562 ctrl &= ~0x4000; 1563 1564 ctrl &= ~port_rx_irq_mask(port); 1565 1566 serial_port_out(port, SCSCR, ctrl); 1567 } 1568 1569 static void sci_enable_ms(struct uart_port *port) 1570 { 1571 /* 1572 * Not supported by hardware, always a nop. 1573 */ 1574 } 1575 1576 static void sci_break_ctl(struct uart_port *port, int break_state) 1577 { 1578 struct sci_port *s = to_sci_port(port); 1579 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR; 1580 unsigned short scscr, scsptr; 1581 1582 /* check wheter the port has SCSPTR */ 1583 if (!reg->size) { 1584 /* 1585 * Not supported by hardware. Most parts couple break and rx 1586 * interrupts together, with break detection always enabled. 1587 */ 1588 return; 1589 } 1590 1591 scsptr = serial_port_in(port, SCSPTR); 1592 scscr = serial_port_in(port, SCSCR); 1593 1594 if (break_state == -1) { 1595 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT; 1596 scscr &= ~SCSCR_TE; 1597 } else { 1598 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO; 1599 scscr |= SCSCR_TE; 1600 } 1601 1602 serial_port_out(port, SCSPTR, scsptr); 1603 serial_port_out(port, SCSCR, scscr); 1604 } 1605 1606 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1607 static bool filter(struct dma_chan *chan, void *slave) 1608 { 1609 struct sh_dmae_slave *param = slave; 1610 1611 dev_dbg(chan->device->dev, "%s: slave ID %d\n", __func__, 1612 param->shdma_slave.slave_id); 1613 1614 chan->private = ¶m->shdma_slave; 1615 return true; 1616 } 1617 1618 static void rx_timer_fn(unsigned long arg) 1619 { 1620 struct sci_port *s = (struct sci_port *)arg; 1621 struct uart_port *port = &s->port; 1622 u16 scr = serial_port_in(port, SCSCR); 1623 1624 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1625 scr &= ~0x4000; 1626 enable_irq(s->cfg->irqs[1]); 1627 } 1628 serial_port_out(port, SCSCR, scr | SCSCR_RIE); 1629 dev_dbg(port->dev, "DMA Rx timed out\n"); 1630 schedule_work(&s->work_rx); 1631 } 1632 1633 static void sci_request_dma(struct uart_port *port) 1634 { 1635 struct sci_port *s = to_sci_port(port); 1636 struct sh_dmae_slave *param; 1637 struct dma_chan *chan; 1638 dma_cap_mask_t mask; 1639 int nent; 1640 1641 dev_dbg(port->dev, "%s: port %d\n", __func__, 1642 port->line); 1643 1644 if (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0) 1645 return; 1646 1647 dma_cap_zero(mask); 1648 dma_cap_set(DMA_SLAVE, mask); 1649 1650 param = &s->param_tx; 1651 1652 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */ 1653 param->shdma_slave.slave_id = s->cfg->dma_slave_tx; 1654 1655 s->cookie_tx = -EINVAL; 1656 chan = dma_request_channel(mask, filter, param); 1657 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan); 1658 if (chan) { 1659 s->chan_tx = chan; 1660 sg_init_table(&s->sg_tx, 1); 1661 /* UART circular tx buffer is an aligned page. */ 1662 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK); 1663 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf), 1664 UART_XMIT_SIZE, (int)port->state->xmit.buf & ~PAGE_MASK); 1665 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE); 1666 if (!nent) 1667 sci_tx_dma_release(s, false); 1668 else 1669 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__, 1670 sg_dma_len(&s->sg_tx), 1671 port->state->xmit.buf, sg_dma_address(&s->sg_tx)); 1672 1673 s->sg_len_tx = nent; 1674 1675 INIT_WORK(&s->work_tx, work_fn_tx); 1676 } 1677 1678 param = &s->param_rx; 1679 1680 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */ 1681 param->shdma_slave.slave_id = s->cfg->dma_slave_rx; 1682 1683 chan = dma_request_channel(mask, filter, param); 1684 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan); 1685 if (chan) { 1686 dma_addr_t dma[2]; 1687 void *buf[2]; 1688 int i; 1689 1690 s->chan_rx = chan; 1691 1692 s->buf_len_rx = 2 * max(16, (int)port->fifosize); 1693 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2, 1694 &dma[0], GFP_KERNEL); 1695 1696 if (!buf[0]) { 1697 dev_warn(port->dev, 1698 "failed to allocate dma buffer, using PIO\n"); 1699 sci_rx_dma_release(s, true); 1700 return; 1701 } 1702 1703 buf[1] = buf[0] + s->buf_len_rx; 1704 dma[1] = dma[0] + s->buf_len_rx; 1705 1706 for (i = 0; i < 2; i++) { 1707 struct scatterlist *sg = &s->sg_rx[i]; 1708 1709 sg_init_table(sg, 1); 1710 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx, 1711 (int)buf[i] & ~PAGE_MASK); 1712 sg_dma_address(sg) = dma[i]; 1713 } 1714 1715 INIT_WORK(&s->work_rx, work_fn_rx); 1716 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s); 1717 1718 sci_submit_rx(s); 1719 } 1720 } 1721 1722 static void sci_free_dma(struct uart_port *port) 1723 { 1724 struct sci_port *s = to_sci_port(port); 1725 1726 if (s->chan_tx) 1727 sci_tx_dma_release(s, false); 1728 if (s->chan_rx) 1729 sci_rx_dma_release(s, false); 1730 } 1731 #else 1732 static inline void sci_request_dma(struct uart_port *port) 1733 { 1734 } 1735 1736 static inline void sci_free_dma(struct uart_port *port) 1737 { 1738 } 1739 #endif 1740 1741 static int sci_startup(struct uart_port *port) 1742 { 1743 struct sci_port *s = to_sci_port(port); 1744 unsigned long flags; 1745 int ret; 1746 1747 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1748 1749 ret = sci_request_irq(s); 1750 if (unlikely(ret < 0)) 1751 return ret; 1752 1753 sci_request_dma(port); 1754 1755 spin_lock_irqsave(&port->lock, flags); 1756 sci_start_tx(port); 1757 sci_start_rx(port); 1758 spin_unlock_irqrestore(&port->lock, flags); 1759 1760 return 0; 1761 } 1762 1763 static void sci_shutdown(struct uart_port *port) 1764 { 1765 struct sci_port *s = to_sci_port(port); 1766 unsigned long flags; 1767 1768 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1769 1770 spin_lock_irqsave(&port->lock, flags); 1771 sci_stop_rx(port); 1772 sci_stop_tx(port); 1773 spin_unlock_irqrestore(&port->lock, flags); 1774 1775 sci_free_dma(port); 1776 sci_free_irq(s); 1777 } 1778 1779 static unsigned int sci_scbrr_calc(unsigned int algo_id, unsigned int bps, 1780 unsigned long freq) 1781 { 1782 switch (algo_id) { 1783 case SCBRR_ALGO_1: 1784 return ((freq + 16 * bps) / (16 * bps) - 1); 1785 case SCBRR_ALGO_2: 1786 return ((freq + 16 * bps) / (32 * bps) - 1); 1787 case SCBRR_ALGO_3: 1788 return (((freq * 2) + 16 * bps) / (16 * bps) - 1); 1789 case SCBRR_ALGO_4: 1790 return (((freq * 2) + 16 * bps) / (32 * bps) - 1); 1791 case SCBRR_ALGO_5: 1792 return (((freq * 1000 / 32) / bps) - 1); 1793 } 1794 1795 /* Warn, but use a safe default */ 1796 WARN_ON(1); 1797 1798 return ((freq + 16 * bps) / (32 * bps) - 1); 1799 } 1800 1801 static void sci_reset(struct uart_port *port) 1802 { 1803 struct plat_sci_reg *reg; 1804 unsigned int status; 1805 1806 do { 1807 status = serial_port_in(port, SCxSR); 1808 } while (!(status & SCxSR_TEND(port))); 1809 1810 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */ 1811 1812 reg = sci_getreg(port, SCFCR); 1813 if (reg->size) 1814 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); 1815 } 1816 1817 static void sci_set_termios(struct uart_port *port, struct ktermios *termios, 1818 struct ktermios *old) 1819 { 1820 struct sci_port *s = to_sci_port(port); 1821 struct plat_sci_reg *reg; 1822 unsigned int baud, smr_val, max_baud, cks; 1823 int t = -1; 1824 1825 /* 1826 * earlyprintk comes here early on with port->uartclk set to zero. 1827 * the clock framework is not up and running at this point so here 1828 * we assume that 115200 is the maximum baud rate. please note that 1829 * the baud rate is not programmed during earlyprintk - it is assumed 1830 * that the previous boot loader has enabled required clocks and 1831 * setup the baud rate generator hardware for us already. 1832 */ 1833 max_baud = port->uartclk ? port->uartclk / 16 : 115200; 1834 1835 baud = uart_get_baud_rate(port, termios, old, 0, max_baud); 1836 if (likely(baud && port->uartclk)) 1837 t = sci_scbrr_calc(s->cfg->scbrr_algo_id, baud, port->uartclk); 1838 1839 sci_port_enable(s); 1840 1841 sci_reset(port); 1842 1843 smr_val = serial_port_in(port, SCSMR) & 3; 1844 1845 if ((termios->c_cflag & CSIZE) == CS7) 1846 smr_val |= 0x40; 1847 if (termios->c_cflag & PARENB) 1848 smr_val |= 0x20; 1849 if (termios->c_cflag & PARODD) 1850 smr_val |= 0x30; 1851 if (termios->c_cflag & CSTOPB) 1852 smr_val |= 0x08; 1853 1854 uart_update_timeout(port, termios->c_cflag, baud); 1855 1856 for (cks = 0; t >= 256 && cks <= 3; cks++) 1857 t >>= 2; 1858 1859 dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n", 1860 __func__, smr_val, cks, t, s->cfg->scscr); 1861 1862 if (t >= 0) { 1863 serial_port_out(port, SCSMR, (smr_val & ~3) | cks); 1864 serial_port_out(port, SCBRR, t); 1865 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */ 1866 } else 1867 serial_port_out(port, SCSMR, smr_val); 1868 1869 sci_init_pins(port, termios->c_cflag); 1870 1871 reg = sci_getreg(port, SCFCR); 1872 if (reg->size) { 1873 unsigned short ctrl = serial_port_in(port, SCFCR); 1874 1875 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) { 1876 if (termios->c_cflag & CRTSCTS) 1877 ctrl |= SCFCR_MCE; 1878 else 1879 ctrl &= ~SCFCR_MCE; 1880 } 1881 1882 /* 1883 * As we've done a sci_reset() above, ensure we don't 1884 * interfere with the FIFOs while toggling MCE. As the 1885 * reset values could still be set, simply mask them out. 1886 */ 1887 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST); 1888 1889 serial_port_out(port, SCFCR, ctrl); 1890 } 1891 1892 serial_port_out(port, SCSCR, s->cfg->scscr); 1893 1894 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1895 /* 1896 * Calculate delay for 1.5 DMA buffers: see 1897 * drivers/serial/serial_core.c::uart_update_timeout(). With 10 bits 1898 * (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function 1899 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)." 1900 * Then below we calculate 3 jiffies (12ms) for 1.5 DMA buffers (3 FIFO 1901 * sizes), but it has been found out experimentally, that this is not 1902 * enough: the driver too often needlessly runs on a DMA timeout. 20ms 1903 * as a minimum seem to work perfectly. 1904 */ 1905 if (s->chan_rx) { 1906 s->rx_timeout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 / 1907 port->fifosize / 2; 1908 dev_dbg(port->dev, 1909 "DMA Rx t-out %ums, tty t-out %u jiffies\n", 1910 s->rx_timeout * 1000 / HZ, port->timeout); 1911 if (s->rx_timeout < msecs_to_jiffies(20)) 1912 s->rx_timeout = msecs_to_jiffies(20); 1913 } 1914 #endif 1915 1916 if ((termios->c_cflag & CREAD) != 0) 1917 sci_start_rx(port); 1918 1919 sci_port_disable(s); 1920 } 1921 1922 static void sci_pm(struct uart_port *port, unsigned int state, 1923 unsigned int oldstate) 1924 { 1925 struct sci_port *sci_port = to_sci_port(port); 1926 1927 switch (state) { 1928 case 3: 1929 sci_port_disable(sci_port); 1930 break; 1931 default: 1932 sci_port_enable(sci_port); 1933 break; 1934 } 1935 } 1936 1937 static const char *sci_type(struct uart_port *port) 1938 { 1939 switch (port->type) { 1940 case PORT_IRDA: 1941 return "irda"; 1942 case PORT_SCI: 1943 return "sci"; 1944 case PORT_SCIF: 1945 return "scif"; 1946 case PORT_SCIFA: 1947 return "scifa"; 1948 case PORT_SCIFB: 1949 return "scifb"; 1950 } 1951 1952 return NULL; 1953 } 1954 1955 static inline unsigned long sci_port_size(struct uart_port *port) 1956 { 1957 /* 1958 * Pick an arbitrary size that encapsulates all of the base 1959 * registers by default. This can be optimized later, or derived 1960 * from platform resource data at such a time that ports begin to 1961 * behave more erratically. 1962 */ 1963 return 64; 1964 } 1965 1966 static int sci_remap_port(struct uart_port *port) 1967 { 1968 unsigned long size = sci_port_size(port); 1969 1970 /* 1971 * Nothing to do if there's already an established membase. 1972 */ 1973 if (port->membase) 1974 return 0; 1975 1976 if (port->flags & UPF_IOREMAP) { 1977 port->membase = ioremap_nocache(port->mapbase, size); 1978 if (unlikely(!port->membase)) { 1979 dev_err(port->dev, "can't remap port#%d\n", port->line); 1980 return -ENXIO; 1981 } 1982 } else { 1983 /* 1984 * For the simple (and majority of) cases where we don't 1985 * need to do any remapping, just cast the cookie 1986 * directly. 1987 */ 1988 port->membase = (void __iomem *)port->mapbase; 1989 } 1990 1991 return 0; 1992 } 1993 1994 static void sci_release_port(struct uart_port *port) 1995 { 1996 if (port->flags & UPF_IOREMAP) { 1997 iounmap(port->membase); 1998 port->membase = NULL; 1999 } 2000 2001 release_mem_region(port->mapbase, sci_port_size(port)); 2002 } 2003 2004 static int sci_request_port(struct uart_port *port) 2005 { 2006 unsigned long size = sci_port_size(port); 2007 struct resource *res; 2008 int ret; 2009 2010 res = request_mem_region(port->mapbase, size, dev_name(port->dev)); 2011 if (unlikely(res == NULL)) 2012 return -EBUSY; 2013 2014 ret = sci_remap_port(port); 2015 if (unlikely(ret != 0)) { 2016 release_resource(res); 2017 return ret; 2018 } 2019 2020 return 0; 2021 } 2022 2023 static void sci_config_port(struct uart_port *port, int flags) 2024 { 2025 if (flags & UART_CONFIG_TYPE) { 2026 struct sci_port *sport = to_sci_port(port); 2027 2028 port->type = sport->cfg->type; 2029 sci_request_port(port); 2030 } 2031 } 2032 2033 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser) 2034 { 2035 struct sci_port *s = to_sci_port(port); 2036 2037 if (ser->irq != s->cfg->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs) 2038 return -EINVAL; 2039 if (ser->baud_base < 2400) 2040 /* No paper tape reader for Mitch.. */ 2041 return -EINVAL; 2042 2043 return 0; 2044 } 2045 2046 static struct uart_ops sci_uart_ops = { 2047 .tx_empty = sci_tx_empty, 2048 .set_mctrl = sci_set_mctrl, 2049 .get_mctrl = sci_get_mctrl, 2050 .start_tx = sci_start_tx, 2051 .stop_tx = sci_stop_tx, 2052 .stop_rx = sci_stop_rx, 2053 .enable_ms = sci_enable_ms, 2054 .break_ctl = sci_break_ctl, 2055 .startup = sci_startup, 2056 .shutdown = sci_shutdown, 2057 .set_termios = sci_set_termios, 2058 .pm = sci_pm, 2059 .type = sci_type, 2060 .release_port = sci_release_port, 2061 .request_port = sci_request_port, 2062 .config_port = sci_config_port, 2063 .verify_port = sci_verify_port, 2064 #ifdef CONFIG_CONSOLE_POLL 2065 .poll_get_char = sci_poll_get_char, 2066 .poll_put_char = sci_poll_put_char, 2067 #endif 2068 }; 2069 2070 static int sci_init_single(struct platform_device *dev, 2071 struct sci_port *sci_port, 2072 unsigned int index, 2073 struct plat_sci_port *p) 2074 { 2075 struct uart_port *port = &sci_port->port; 2076 int ret; 2077 2078 sci_port->cfg = p; 2079 2080 port->ops = &sci_uart_ops; 2081 port->iotype = UPIO_MEM; 2082 port->line = index; 2083 2084 switch (p->type) { 2085 case PORT_SCIFB: 2086 port->fifosize = 256; 2087 break; 2088 case PORT_SCIFA: 2089 port->fifosize = 64; 2090 break; 2091 case PORT_SCIF: 2092 port->fifosize = 16; 2093 break; 2094 default: 2095 port->fifosize = 1; 2096 break; 2097 } 2098 2099 if (p->regtype == SCIx_PROBE_REGTYPE) { 2100 ret = sci_probe_regmap(p); 2101 if (unlikely(ret)) 2102 return ret; 2103 } 2104 2105 if (dev) { 2106 sci_port->iclk = clk_get(&dev->dev, "sci_ick"); 2107 if (IS_ERR(sci_port->iclk)) { 2108 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk"); 2109 if (IS_ERR(sci_port->iclk)) { 2110 dev_err(&dev->dev, "can't get iclk\n"); 2111 return PTR_ERR(sci_port->iclk); 2112 } 2113 } 2114 2115 /* 2116 * The function clock is optional, ignore it if we can't 2117 * find it. 2118 */ 2119 sci_port->fclk = clk_get(&dev->dev, "sci_fck"); 2120 if (IS_ERR(sci_port->fclk)) 2121 sci_port->fclk = NULL; 2122 2123 port->dev = &dev->dev; 2124 2125 sci_init_gpios(sci_port); 2126 2127 pm_runtime_enable(&dev->dev); 2128 } 2129 2130 sci_port->break_timer.data = (unsigned long)sci_port; 2131 sci_port->break_timer.function = sci_break_timer; 2132 init_timer(&sci_port->break_timer); 2133 2134 /* 2135 * Establish some sensible defaults for the error detection. 2136 */ 2137 if (!p->error_mask) 2138 p->error_mask = (p->type == PORT_SCI) ? 2139 SCI_DEFAULT_ERROR_MASK : SCIF_DEFAULT_ERROR_MASK; 2140 2141 /* 2142 * Establish sensible defaults for the overrun detection, unless 2143 * the part has explicitly disabled support for it. 2144 */ 2145 if (p->overrun_bit != SCIx_NOT_SUPPORTED) { 2146 if (p->type == PORT_SCI) 2147 p->overrun_bit = 5; 2148 else if (p->scbrr_algo_id == SCBRR_ALGO_4) 2149 p->overrun_bit = 9; 2150 else 2151 p->overrun_bit = 0; 2152 2153 /* 2154 * Make the error mask inclusive of overrun detection, if 2155 * supported. 2156 */ 2157 p->error_mask |= (1 << p->overrun_bit); 2158 } 2159 2160 port->mapbase = p->mapbase; 2161 port->type = p->type; 2162 port->flags = p->flags; 2163 port->regshift = p->regshift; 2164 2165 /* 2166 * The UART port needs an IRQ value, so we peg this to the RX IRQ 2167 * for the multi-IRQ ports, which is where we are primarily 2168 * concerned with the shutdown path synchronization. 2169 * 2170 * For the muxed case there's nothing more to do. 2171 */ 2172 port->irq = p->irqs[SCIx_RXI_IRQ]; 2173 port->irqflags = 0; 2174 2175 port->serial_in = sci_serial_in; 2176 port->serial_out = sci_serial_out; 2177 2178 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0) 2179 dev_dbg(port->dev, "DMA tx %d, rx %d\n", 2180 p->dma_slave_tx, p->dma_slave_rx); 2181 2182 return 0; 2183 } 2184 2185 static void sci_cleanup_single(struct sci_port *port) 2186 { 2187 sci_free_gpios(port); 2188 2189 clk_put(port->iclk); 2190 clk_put(port->fclk); 2191 2192 pm_runtime_disable(port->port.dev); 2193 } 2194 2195 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE 2196 static void serial_console_putchar(struct uart_port *port, int ch) 2197 { 2198 sci_poll_put_char(port, ch); 2199 } 2200 2201 /* 2202 * Print a string to the serial port trying not to disturb 2203 * any possible real use of the port... 2204 */ 2205 static void serial_console_write(struct console *co, const char *s, 2206 unsigned count) 2207 { 2208 struct sci_port *sci_port = &sci_ports[co->index]; 2209 struct uart_port *port = &sci_port->port; 2210 unsigned short bits, ctrl; 2211 unsigned long flags; 2212 int locked = 1; 2213 2214 local_irq_save(flags); 2215 if (port->sysrq) 2216 locked = 0; 2217 else if (oops_in_progress) 2218 locked = spin_trylock(&port->lock); 2219 else 2220 spin_lock(&port->lock); 2221 2222 /* first save the SCSCR then disable the interrupts */ 2223 ctrl = serial_port_in(port, SCSCR); 2224 serial_port_out(port, SCSCR, sci_port->cfg->scscr); 2225 2226 uart_console_write(port, s, count, serial_console_putchar); 2227 2228 /* wait until fifo is empty and last bit has been transmitted */ 2229 bits = SCxSR_TDxE(port) | SCxSR_TEND(port); 2230 while ((serial_port_in(port, SCxSR) & bits) != bits) 2231 cpu_relax(); 2232 2233 /* restore the SCSCR */ 2234 serial_port_out(port, SCSCR, ctrl); 2235 2236 if (locked) 2237 spin_unlock(&port->lock); 2238 local_irq_restore(flags); 2239 } 2240 2241 static int serial_console_setup(struct console *co, char *options) 2242 { 2243 struct sci_port *sci_port; 2244 struct uart_port *port; 2245 int baud = 115200; 2246 int bits = 8; 2247 int parity = 'n'; 2248 int flow = 'n'; 2249 int ret; 2250 2251 /* 2252 * Refuse to handle any bogus ports. 2253 */ 2254 if (co->index < 0 || co->index >= SCI_NPORTS) 2255 return -ENODEV; 2256 2257 sci_port = &sci_ports[co->index]; 2258 port = &sci_port->port; 2259 2260 /* 2261 * Refuse to handle uninitialized ports. 2262 */ 2263 if (!port->ops) 2264 return -ENODEV; 2265 2266 ret = sci_remap_port(port); 2267 if (unlikely(ret != 0)) 2268 return ret; 2269 2270 if (options) 2271 uart_parse_options(options, &baud, &parity, &bits, &flow); 2272 2273 return uart_set_options(port, co, baud, parity, bits, flow); 2274 } 2275 2276 static struct console serial_console = { 2277 .name = "ttySC", 2278 .device = uart_console_device, 2279 .write = serial_console_write, 2280 .setup = serial_console_setup, 2281 .flags = CON_PRINTBUFFER, 2282 .index = -1, 2283 .data = &sci_uart_driver, 2284 }; 2285 2286 static struct console early_serial_console = { 2287 .name = "early_ttySC", 2288 .write = serial_console_write, 2289 .flags = CON_PRINTBUFFER, 2290 .index = -1, 2291 }; 2292 2293 static char early_serial_buf[32]; 2294 2295 static int sci_probe_earlyprintk(struct platform_device *pdev) 2296 { 2297 struct plat_sci_port *cfg = pdev->dev.platform_data; 2298 2299 if (early_serial_console.data) 2300 return -EEXIST; 2301 2302 early_serial_console.index = pdev->id; 2303 2304 sci_init_single(NULL, &sci_ports[pdev->id], pdev->id, cfg); 2305 2306 serial_console_setup(&early_serial_console, early_serial_buf); 2307 2308 if (!strstr(early_serial_buf, "keep")) 2309 early_serial_console.flags |= CON_BOOT; 2310 2311 register_console(&early_serial_console); 2312 return 0; 2313 } 2314 2315 #define SCI_CONSOLE (&serial_console) 2316 2317 #else 2318 static inline int sci_probe_earlyprintk(struct platform_device *pdev) 2319 { 2320 return -EINVAL; 2321 } 2322 2323 #define SCI_CONSOLE NULL 2324 2325 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */ 2326 2327 static char banner[] __initdata = 2328 KERN_INFO "SuperH SCI(F) driver initialized\n"; 2329 2330 static struct uart_driver sci_uart_driver = { 2331 .owner = THIS_MODULE, 2332 .driver_name = "sci", 2333 .dev_name = "ttySC", 2334 .major = SCI_MAJOR, 2335 .minor = SCI_MINOR_START, 2336 .nr = SCI_NPORTS, 2337 .cons = SCI_CONSOLE, 2338 }; 2339 2340 static int sci_remove(struct platform_device *dev) 2341 { 2342 struct sci_port *port = platform_get_drvdata(dev); 2343 2344 cpufreq_unregister_notifier(&port->freq_transition, 2345 CPUFREQ_TRANSITION_NOTIFIER); 2346 2347 uart_remove_one_port(&sci_uart_driver, &port->port); 2348 2349 sci_cleanup_single(port); 2350 2351 return 0; 2352 } 2353 2354 static int sci_probe_single(struct platform_device *dev, 2355 unsigned int index, 2356 struct plat_sci_port *p, 2357 struct sci_port *sciport) 2358 { 2359 int ret; 2360 2361 /* Sanity check */ 2362 if (unlikely(index >= SCI_NPORTS)) { 2363 dev_notice(&dev->dev, "Attempting to register port " 2364 "%d when only %d are available.\n", 2365 index+1, SCI_NPORTS); 2366 dev_notice(&dev->dev, "Consider bumping " 2367 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n"); 2368 return -EINVAL; 2369 } 2370 2371 ret = sci_init_single(dev, sciport, index, p); 2372 if (ret) 2373 return ret; 2374 2375 ret = uart_add_one_port(&sci_uart_driver, &sciport->port); 2376 if (ret) { 2377 sci_cleanup_single(sciport); 2378 return ret; 2379 } 2380 2381 return 0; 2382 } 2383 2384 static int sci_probe(struct platform_device *dev) 2385 { 2386 struct plat_sci_port *p = dev->dev.platform_data; 2387 struct sci_port *sp = &sci_ports[dev->id]; 2388 int ret; 2389 2390 /* 2391 * If we've come here via earlyprintk initialization, head off to 2392 * the special early probe. We don't have sufficient device state 2393 * to make it beyond this yet. 2394 */ 2395 if (is_early_platform_device(dev)) 2396 return sci_probe_earlyprintk(dev); 2397 2398 platform_set_drvdata(dev, sp); 2399 2400 ret = sci_probe_single(dev, dev->id, p, sp); 2401 if (ret) 2402 return ret; 2403 2404 sp->freq_transition.notifier_call = sci_notifier; 2405 2406 ret = cpufreq_register_notifier(&sp->freq_transition, 2407 CPUFREQ_TRANSITION_NOTIFIER); 2408 if (unlikely(ret < 0)) { 2409 sci_cleanup_single(sp); 2410 return ret; 2411 } 2412 2413 #ifdef CONFIG_SH_STANDARD_BIOS 2414 sh_bios_gdb_detach(); 2415 #endif 2416 2417 return 0; 2418 } 2419 2420 static int sci_suspend(struct device *dev) 2421 { 2422 struct sci_port *sport = dev_get_drvdata(dev); 2423 2424 if (sport) 2425 uart_suspend_port(&sci_uart_driver, &sport->port); 2426 2427 return 0; 2428 } 2429 2430 static int sci_resume(struct device *dev) 2431 { 2432 struct sci_port *sport = dev_get_drvdata(dev); 2433 2434 if (sport) 2435 uart_resume_port(&sci_uart_driver, &sport->port); 2436 2437 return 0; 2438 } 2439 2440 static const struct dev_pm_ops sci_dev_pm_ops = { 2441 .suspend = sci_suspend, 2442 .resume = sci_resume, 2443 }; 2444 2445 static struct platform_driver sci_driver = { 2446 .probe = sci_probe, 2447 .remove = sci_remove, 2448 .driver = { 2449 .name = "sh-sci", 2450 .owner = THIS_MODULE, 2451 .pm = &sci_dev_pm_ops, 2452 }, 2453 }; 2454 2455 static int __init sci_init(void) 2456 { 2457 int ret; 2458 2459 printk(banner); 2460 2461 ret = uart_register_driver(&sci_uart_driver); 2462 if (likely(ret == 0)) { 2463 ret = platform_driver_register(&sci_driver); 2464 if (unlikely(ret)) 2465 uart_unregister_driver(&sci_uart_driver); 2466 } 2467 2468 return ret; 2469 } 2470 2471 static void __exit sci_exit(void) 2472 { 2473 platform_driver_unregister(&sci_driver); 2474 uart_unregister_driver(&sci_uart_driver); 2475 } 2476 2477 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE 2478 early_platform_init_buffer("earlyprintk", &sci_driver, 2479 early_serial_buf, ARRAY_SIZE(early_serial_buf)); 2480 #endif 2481 module_init(sci_init); 2482 module_exit(sci_exit); 2483 2484 MODULE_LICENSE("GPL"); 2485 MODULE_ALIAS("platform:sh-sci"); 2486 MODULE_AUTHOR("Paul Mundt"); 2487 MODULE_DESCRIPTION("SuperH SCI(F) serial driver"); 2488