1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) 4 * 5 * Copyright (C) 2002 - 2011 Paul Mundt 6 * Copyright (C) 2015 Glider bvba 7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007). 8 * 9 * based off of the old drivers/char/sh-sci.c by: 10 * 11 * Copyright (C) 1999, 2000 Niibe Yutaka 12 * Copyright (C) 2000 Sugioka Toshinobu 13 * Modified to support multiple serial ports. Stuart Menefy (May 2000). 14 * Modified to support SecureEdge. David McCullough (2002) 15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003). 16 * Removed SH7300 support (Jul 2007). 17 */ 18 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 19 #define SUPPORT_SYSRQ 20 #endif 21 22 #undef DEBUG 23 24 #include <linux/clk.h> 25 #include <linux/console.h> 26 #include <linux/ctype.h> 27 #include <linux/cpufreq.h> 28 #include <linux/delay.h> 29 #include <linux/dmaengine.h> 30 #include <linux/dma-mapping.h> 31 #include <linux/err.h> 32 #include <linux/errno.h> 33 #include <linux/init.h> 34 #include <linux/interrupt.h> 35 #include <linux/ioport.h> 36 #include <linux/ktime.h> 37 #include <linux/major.h> 38 #include <linux/module.h> 39 #include <linux/mm.h> 40 #include <linux/of.h> 41 #include <linux/of_device.h> 42 #include <linux/platform_device.h> 43 #include <linux/pm_runtime.h> 44 #include <linux/scatterlist.h> 45 #include <linux/serial.h> 46 #include <linux/serial_sci.h> 47 #include <linux/sh_dma.h> 48 #include <linux/slab.h> 49 #include <linux/string.h> 50 #include <linux/sysrq.h> 51 #include <linux/timer.h> 52 #include <linux/tty.h> 53 #include <linux/tty_flip.h> 54 55 #ifdef CONFIG_SUPERH 56 #include <asm/sh_bios.h> 57 #endif 58 59 #include "serial_mctrl_gpio.h" 60 #include "sh-sci.h" 61 62 /* Offsets into the sci_port->irqs array */ 63 enum { 64 SCIx_ERI_IRQ, 65 SCIx_RXI_IRQ, 66 SCIx_TXI_IRQ, 67 SCIx_BRI_IRQ, 68 SCIx_NR_IRQS, 69 70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */ 71 }; 72 73 #define SCIx_IRQ_IS_MUXED(port) \ 74 ((port)->irqs[SCIx_ERI_IRQ] == \ 75 (port)->irqs[SCIx_RXI_IRQ]) || \ 76 ((port)->irqs[SCIx_ERI_IRQ] && \ 77 ((port)->irqs[SCIx_RXI_IRQ] < 0)) 78 79 enum SCI_CLKS { 80 SCI_FCK, /* Functional Clock */ 81 SCI_SCK, /* Optional External Clock */ 82 SCI_BRG_INT, /* Optional BRG Internal Clock Source */ 83 SCI_SCIF_CLK, /* Optional BRG External Clock Source */ 84 SCI_NUM_CLKS 85 }; 86 87 /* Bit x set means sampling rate x + 1 is supported */ 88 #define SCI_SR(x) BIT((x) - 1) 89 #define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1) 90 91 #define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \ 92 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \ 93 SCI_SR(19) | SCI_SR(27) 94 95 #define min_sr(_port) ffs((_port)->sampling_rate_mask) 96 #define max_sr(_port) fls((_port)->sampling_rate_mask) 97 98 /* Iterate over all supported sampling rates, from high to low */ 99 #define for_each_sr(_sr, _port) \ 100 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \ 101 if ((_port)->sampling_rate_mask & SCI_SR((_sr))) 102 103 struct plat_sci_reg { 104 u8 offset, size; 105 }; 106 107 struct sci_port_params { 108 const struct plat_sci_reg regs[SCIx_NR_REGS]; 109 unsigned int fifosize; 110 unsigned int overrun_reg; 111 unsigned int overrun_mask; 112 unsigned int sampling_rate_mask; 113 unsigned int error_mask; 114 unsigned int error_clear; 115 }; 116 117 struct sci_port { 118 struct uart_port port; 119 120 /* Platform configuration */ 121 const struct sci_port_params *params; 122 const struct plat_sci_port *cfg; 123 unsigned int sampling_rate_mask; 124 resource_size_t reg_size; 125 struct mctrl_gpios *gpios; 126 127 /* Clocks */ 128 struct clk *clks[SCI_NUM_CLKS]; 129 unsigned long clk_rates[SCI_NUM_CLKS]; 130 131 int irqs[SCIx_NR_IRQS]; 132 char *irqstr[SCIx_NR_IRQS]; 133 134 struct dma_chan *chan_tx; 135 struct dma_chan *chan_rx; 136 137 #ifdef CONFIG_SERIAL_SH_SCI_DMA 138 dma_cookie_t cookie_tx; 139 dma_cookie_t cookie_rx[2]; 140 dma_cookie_t active_rx; 141 dma_addr_t tx_dma_addr; 142 unsigned int tx_dma_len; 143 struct scatterlist sg_rx[2]; 144 void *rx_buf[2]; 145 size_t buf_len_rx; 146 struct work_struct work_tx; 147 struct hrtimer rx_timer; 148 unsigned int rx_timeout; /* microseconds */ 149 #endif 150 unsigned int rx_frame; 151 int rx_trigger; 152 struct timer_list rx_fifo_timer; 153 int rx_fifo_timeout; 154 u16 hscif_tot; 155 156 bool has_rtscts; 157 bool autorts; 158 }; 159 160 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS 161 162 static struct sci_port sci_ports[SCI_NPORTS]; 163 static unsigned long sci_ports_in_use; 164 static struct uart_driver sci_uart_driver; 165 166 static inline struct sci_port * 167 to_sci_port(struct uart_port *uart) 168 { 169 return container_of(uart, struct sci_port, port); 170 } 171 172 static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { 173 /* 174 * Common SCI definitions, dependent on the port's regshift 175 * value. 176 */ 177 [SCIx_SCI_REGTYPE] = { 178 .regs = { 179 [SCSMR] = { 0x00, 8 }, 180 [SCBRR] = { 0x01, 8 }, 181 [SCSCR] = { 0x02, 8 }, 182 [SCxTDR] = { 0x03, 8 }, 183 [SCxSR] = { 0x04, 8 }, 184 [SCxRDR] = { 0x05, 8 }, 185 }, 186 .fifosize = 1, 187 .overrun_reg = SCxSR, 188 .overrun_mask = SCI_ORER, 189 .sampling_rate_mask = SCI_SR(32), 190 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, 191 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, 192 }, 193 194 /* 195 * Common definitions for legacy IrDA ports. 196 */ 197 [SCIx_IRDA_REGTYPE] = { 198 .regs = { 199 [SCSMR] = { 0x00, 8 }, 200 [SCBRR] = { 0x02, 8 }, 201 [SCSCR] = { 0x04, 8 }, 202 [SCxTDR] = { 0x06, 8 }, 203 [SCxSR] = { 0x08, 16 }, 204 [SCxRDR] = { 0x0a, 8 }, 205 [SCFCR] = { 0x0c, 8 }, 206 [SCFDR] = { 0x0e, 16 }, 207 }, 208 .fifosize = 1, 209 .overrun_reg = SCxSR, 210 .overrun_mask = SCI_ORER, 211 .sampling_rate_mask = SCI_SR(32), 212 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, 213 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, 214 }, 215 216 /* 217 * Common SCIFA definitions. 218 */ 219 [SCIx_SCIFA_REGTYPE] = { 220 .regs = { 221 [SCSMR] = { 0x00, 16 }, 222 [SCBRR] = { 0x04, 8 }, 223 [SCSCR] = { 0x08, 16 }, 224 [SCxTDR] = { 0x20, 8 }, 225 [SCxSR] = { 0x14, 16 }, 226 [SCxRDR] = { 0x24, 8 }, 227 [SCFCR] = { 0x18, 16 }, 228 [SCFDR] = { 0x1c, 16 }, 229 [SCPCR] = { 0x30, 16 }, 230 [SCPDR] = { 0x34, 16 }, 231 }, 232 .fifosize = 64, 233 .overrun_reg = SCxSR, 234 .overrun_mask = SCIFA_ORER, 235 .sampling_rate_mask = SCI_SR_SCIFAB, 236 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 237 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 238 }, 239 240 /* 241 * Common SCIFB definitions. 242 */ 243 [SCIx_SCIFB_REGTYPE] = { 244 .regs = { 245 [SCSMR] = { 0x00, 16 }, 246 [SCBRR] = { 0x04, 8 }, 247 [SCSCR] = { 0x08, 16 }, 248 [SCxTDR] = { 0x40, 8 }, 249 [SCxSR] = { 0x14, 16 }, 250 [SCxRDR] = { 0x60, 8 }, 251 [SCFCR] = { 0x18, 16 }, 252 [SCTFDR] = { 0x38, 16 }, 253 [SCRFDR] = { 0x3c, 16 }, 254 [SCPCR] = { 0x30, 16 }, 255 [SCPDR] = { 0x34, 16 }, 256 }, 257 .fifosize = 256, 258 .overrun_reg = SCxSR, 259 .overrun_mask = SCIFA_ORER, 260 .sampling_rate_mask = SCI_SR_SCIFAB, 261 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 262 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 263 }, 264 265 /* 266 * Common SH-2(A) SCIF definitions for ports with FIFO data 267 * count registers. 268 */ 269 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = { 270 .regs = { 271 [SCSMR] = { 0x00, 16 }, 272 [SCBRR] = { 0x04, 8 }, 273 [SCSCR] = { 0x08, 16 }, 274 [SCxTDR] = { 0x0c, 8 }, 275 [SCxSR] = { 0x10, 16 }, 276 [SCxRDR] = { 0x14, 8 }, 277 [SCFCR] = { 0x18, 16 }, 278 [SCFDR] = { 0x1c, 16 }, 279 [SCSPTR] = { 0x20, 16 }, 280 [SCLSR] = { 0x24, 16 }, 281 }, 282 .fifosize = 16, 283 .overrun_reg = SCLSR, 284 .overrun_mask = SCLSR_ORER, 285 .sampling_rate_mask = SCI_SR(32), 286 .error_mask = SCIF_DEFAULT_ERROR_MASK, 287 .error_clear = SCIF_ERROR_CLEAR, 288 }, 289 290 /* 291 * Common SH-3 SCIF definitions. 292 */ 293 [SCIx_SH3_SCIF_REGTYPE] = { 294 .regs = { 295 [SCSMR] = { 0x00, 8 }, 296 [SCBRR] = { 0x02, 8 }, 297 [SCSCR] = { 0x04, 8 }, 298 [SCxTDR] = { 0x06, 8 }, 299 [SCxSR] = { 0x08, 16 }, 300 [SCxRDR] = { 0x0a, 8 }, 301 [SCFCR] = { 0x0c, 8 }, 302 [SCFDR] = { 0x0e, 16 }, 303 }, 304 .fifosize = 16, 305 .overrun_reg = SCLSR, 306 .overrun_mask = SCLSR_ORER, 307 .sampling_rate_mask = SCI_SR(32), 308 .error_mask = SCIF_DEFAULT_ERROR_MASK, 309 .error_clear = SCIF_ERROR_CLEAR, 310 }, 311 312 /* 313 * Common SH-4(A) SCIF(B) definitions. 314 */ 315 [SCIx_SH4_SCIF_REGTYPE] = { 316 .regs = { 317 [SCSMR] = { 0x00, 16 }, 318 [SCBRR] = { 0x04, 8 }, 319 [SCSCR] = { 0x08, 16 }, 320 [SCxTDR] = { 0x0c, 8 }, 321 [SCxSR] = { 0x10, 16 }, 322 [SCxRDR] = { 0x14, 8 }, 323 [SCFCR] = { 0x18, 16 }, 324 [SCFDR] = { 0x1c, 16 }, 325 [SCSPTR] = { 0x20, 16 }, 326 [SCLSR] = { 0x24, 16 }, 327 }, 328 .fifosize = 16, 329 .overrun_reg = SCLSR, 330 .overrun_mask = SCLSR_ORER, 331 .sampling_rate_mask = SCI_SR(32), 332 .error_mask = SCIF_DEFAULT_ERROR_MASK, 333 .error_clear = SCIF_ERROR_CLEAR, 334 }, 335 336 /* 337 * Common SCIF definitions for ports with a Baud Rate Generator for 338 * External Clock (BRG). 339 */ 340 [SCIx_SH4_SCIF_BRG_REGTYPE] = { 341 .regs = { 342 [SCSMR] = { 0x00, 16 }, 343 [SCBRR] = { 0x04, 8 }, 344 [SCSCR] = { 0x08, 16 }, 345 [SCxTDR] = { 0x0c, 8 }, 346 [SCxSR] = { 0x10, 16 }, 347 [SCxRDR] = { 0x14, 8 }, 348 [SCFCR] = { 0x18, 16 }, 349 [SCFDR] = { 0x1c, 16 }, 350 [SCSPTR] = { 0x20, 16 }, 351 [SCLSR] = { 0x24, 16 }, 352 [SCDL] = { 0x30, 16 }, 353 [SCCKS] = { 0x34, 16 }, 354 }, 355 .fifosize = 16, 356 .overrun_reg = SCLSR, 357 .overrun_mask = SCLSR_ORER, 358 .sampling_rate_mask = SCI_SR(32), 359 .error_mask = SCIF_DEFAULT_ERROR_MASK, 360 .error_clear = SCIF_ERROR_CLEAR, 361 }, 362 363 /* 364 * Common HSCIF definitions. 365 */ 366 [SCIx_HSCIF_REGTYPE] = { 367 .regs = { 368 [SCSMR] = { 0x00, 16 }, 369 [SCBRR] = { 0x04, 8 }, 370 [SCSCR] = { 0x08, 16 }, 371 [SCxTDR] = { 0x0c, 8 }, 372 [SCxSR] = { 0x10, 16 }, 373 [SCxRDR] = { 0x14, 8 }, 374 [SCFCR] = { 0x18, 16 }, 375 [SCFDR] = { 0x1c, 16 }, 376 [SCSPTR] = { 0x20, 16 }, 377 [SCLSR] = { 0x24, 16 }, 378 [HSSRR] = { 0x40, 16 }, 379 [SCDL] = { 0x30, 16 }, 380 [SCCKS] = { 0x34, 16 }, 381 [HSRTRGR] = { 0x54, 16 }, 382 [HSTTRGR] = { 0x58, 16 }, 383 }, 384 .fifosize = 128, 385 .overrun_reg = SCLSR, 386 .overrun_mask = SCLSR_ORER, 387 .sampling_rate_mask = SCI_SR_RANGE(8, 32), 388 .error_mask = SCIF_DEFAULT_ERROR_MASK, 389 .error_clear = SCIF_ERROR_CLEAR, 390 }, 391 392 /* 393 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR 394 * register. 395 */ 396 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = { 397 .regs = { 398 [SCSMR] = { 0x00, 16 }, 399 [SCBRR] = { 0x04, 8 }, 400 [SCSCR] = { 0x08, 16 }, 401 [SCxTDR] = { 0x0c, 8 }, 402 [SCxSR] = { 0x10, 16 }, 403 [SCxRDR] = { 0x14, 8 }, 404 [SCFCR] = { 0x18, 16 }, 405 [SCFDR] = { 0x1c, 16 }, 406 [SCLSR] = { 0x24, 16 }, 407 }, 408 .fifosize = 16, 409 .overrun_reg = SCLSR, 410 .overrun_mask = SCLSR_ORER, 411 .sampling_rate_mask = SCI_SR(32), 412 .error_mask = SCIF_DEFAULT_ERROR_MASK, 413 .error_clear = SCIF_ERROR_CLEAR, 414 }, 415 416 /* 417 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data 418 * count registers. 419 */ 420 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = { 421 .regs = { 422 [SCSMR] = { 0x00, 16 }, 423 [SCBRR] = { 0x04, 8 }, 424 [SCSCR] = { 0x08, 16 }, 425 [SCxTDR] = { 0x0c, 8 }, 426 [SCxSR] = { 0x10, 16 }, 427 [SCxRDR] = { 0x14, 8 }, 428 [SCFCR] = { 0x18, 16 }, 429 [SCFDR] = { 0x1c, 16 }, 430 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */ 431 [SCRFDR] = { 0x20, 16 }, 432 [SCSPTR] = { 0x24, 16 }, 433 [SCLSR] = { 0x28, 16 }, 434 }, 435 .fifosize = 16, 436 .overrun_reg = SCLSR, 437 .overrun_mask = SCLSR_ORER, 438 .sampling_rate_mask = SCI_SR(32), 439 .error_mask = SCIF_DEFAULT_ERROR_MASK, 440 .error_clear = SCIF_ERROR_CLEAR, 441 }, 442 443 /* 444 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR 445 * registers. 446 */ 447 [SCIx_SH7705_SCIF_REGTYPE] = { 448 .regs = { 449 [SCSMR] = { 0x00, 16 }, 450 [SCBRR] = { 0x04, 8 }, 451 [SCSCR] = { 0x08, 16 }, 452 [SCxTDR] = { 0x20, 8 }, 453 [SCxSR] = { 0x14, 16 }, 454 [SCxRDR] = { 0x24, 8 }, 455 [SCFCR] = { 0x18, 16 }, 456 [SCFDR] = { 0x1c, 16 }, 457 }, 458 .fifosize = 64, 459 .overrun_reg = SCxSR, 460 .overrun_mask = SCIFA_ORER, 461 .sampling_rate_mask = SCI_SR(16), 462 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 463 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 464 }, 465 }; 466 467 #define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset]) 468 469 /* 470 * The "offset" here is rather misleading, in that it refers to an enum 471 * value relative to the port mapping rather than the fixed offset 472 * itself, which needs to be manually retrieved from the platform's 473 * register map for the given port. 474 */ 475 static unsigned int sci_serial_in(struct uart_port *p, int offset) 476 { 477 const struct plat_sci_reg *reg = sci_getreg(p, offset); 478 479 if (reg->size == 8) 480 return ioread8(p->membase + (reg->offset << p->regshift)); 481 else if (reg->size == 16) 482 return ioread16(p->membase + (reg->offset << p->regshift)); 483 else 484 WARN(1, "Invalid register access\n"); 485 486 return 0; 487 } 488 489 static void sci_serial_out(struct uart_port *p, int offset, int value) 490 { 491 const struct plat_sci_reg *reg = sci_getreg(p, offset); 492 493 if (reg->size == 8) 494 iowrite8(value, p->membase + (reg->offset << p->regshift)); 495 else if (reg->size == 16) 496 iowrite16(value, p->membase + (reg->offset << p->regshift)); 497 else 498 WARN(1, "Invalid register access\n"); 499 } 500 501 static void sci_port_enable(struct sci_port *sci_port) 502 { 503 unsigned int i; 504 505 if (!sci_port->port.dev) 506 return; 507 508 pm_runtime_get_sync(sci_port->port.dev); 509 510 for (i = 0; i < SCI_NUM_CLKS; i++) { 511 clk_prepare_enable(sci_port->clks[i]); 512 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]); 513 } 514 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK]; 515 } 516 517 static void sci_port_disable(struct sci_port *sci_port) 518 { 519 unsigned int i; 520 521 if (!sci_port->port.dev) 522 return; 523 524 for (i = SCI_NUM_CLKS; i-- > 0; ) 525 clk_disable_unprepare(sci_port->clks[i]); 526 527 pm_runtime_put_sync(sci_port->port.dev); 528 } 529 530 static inline unsigned long port_rx_irq_mask(struct uart_port *port) 531 { 532 /* 533 * Not all ports (such as SCIFA) will support REIE. Rather than 534 * special-casing the port type, we check the port initialization 535 * IRQ enable mask to see whether the IRQ is desired at all. If 536 * it's unset, it's logically inferred that there's no point in 537 * testing for it. 538 */ 539 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE); 540 } 541 542 static void sci_start_tx(struct uart_port *port) 543 { 544 struct sci_port *s = to_sci_port(port); 545 unsigned short ctrl; 546 547 #ifdef CONFIG_SERIAL_SH_SCI_DMA 548 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 549 u16 new, scr = serial_port_in(port, SCSCR); 550 if (s->chan_tx) 551 new = scr | SCSCR_TDRQE; 552 else 553 new = scr & ~SCSCR_TDRQE; 554 if (new != scr) 555 serial_port_out(port, SCSCR, new); 556 } 557 558 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) && 559 dma_submit_error(s->cookie_tx)) { 560 s->cookie_tx = 0; 561 schedule_work(&s->work_tx); 562 } 563 #endif 564 565 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 566 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ 567 ctrl = serial_port_in(port, SCSCR); 568 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE); 569 } 570 } 571 572 static void sci_stop_tx(struct uart_port *port) 573 { 574 unsigned short ctrl; 575 576 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ 577 ctrl = serial_port_in(port, SCSCR); 578 579 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 580 ctrl &= ~SCSCR_TDRQE; 581 582 ctrl &= ~SCSCR_TIE; 583 584 serial_port_out(port, SCSCR, ctrl); 585 } 586 587 static void sci_start_rx(struct uart_port *port) 588 { 589 unsigned short ctrl; 590 591 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port); 592 593 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 594 ctrl &= ~SCSCR_RDRQE; 595 596 serial_port_out(port, SCSCR, ctrl); 597 } 598 599 static void sci_stop_rx(struct uart_port *port) 600 { 601 unsigned short ctrl; 602 603 ctrl = serial_port_in(port, SCSCR); 604 605 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 606 ctrl &= ~SCSCR_RDRQE; 607 608 ctrl &= ~port_rx_irq_mask(port); 609 610 serial_port_out(port, SCSCR, ctrl); 611 } 612 613 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask) 614 { 615 if (port->type == PORT_SCI) { 616 /* Just store the mask */ 617 serial_port_out(port, SCxSR, mask); 618 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) { 619 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */ 620 /* Only clear the status bits we want to clear */ 621 serial_port_out(port, SCxSR, 622 serial_port_in(port, SCxSR) & mask); 623 } else { 624 /* Store the mask, clear parity/framing errors */ 625 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC)); 626 } 627 } 628 629 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ 630 defined(CONFIG_SERIAL_SH_SCI_EARLYCON) 631 632 #ifdef CONFIG_CONSOLE_POLL 633 static int sci_poll_get_char(struct uart_port *port) 634 { 635 unsigned short status; 636 int c; 637 638 do { 639 status = serial_port_in(port, SCxSR); 640 if (status & SCxSR_ERRORS(port)) { 641 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); 642 continue; 643 } 644 break; 645 } while (1); 646 647 if (!(status & SCxSR_RDxF(port))) 648 return NO_POLL_CHAR; 649 650 c = serial_port_in(port, SCxRDR); 651 652 /* Dummy read */ 653 serial_port_in(port, SCxSR); 654 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 655 656 return c; 657 } 658 #endif 659 660 static void sci_poll_put_char(struct uart_port *port, unsigned char c) 661 { 662 unsigned short status; 663 664 do { 665 status = serial_port_in(port, SCxSR); 666 } while (!(status & SCxSR_TDxE(port))); 667 668 serial_port_out(port, SCxTDR, c); 669 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port)); 670 } 671 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE || 672 CONFIG_SERIAL_SH_SCI_EARLYCON */ 673 674 static void sci_init_pins(struct uart_port *port, unsigned int cflag) 675 { 676 struct sci_port *s = to_sci_port(port); 677 678 /* 679 * Use port-specific handler if provided. 680 */ 681 if (s->cfg->ops && s->cfg->ops->init_pins) { 682 s->cfg->ops->init_pins(port, cflag); 683 return; 684 } 685 686 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 687 u16 data = serial_port_in(port, SCPDR); 688 u16 ctrl = serial_port_in(port, SCPCR); 689 690 /* Enable RXD and TXD pin functions */ 691 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC); 692 if (to_sci_port(port)->has_rtscts) { 693 /* RTS# is output, active low, unless autorts */ 694 if (!(port->mctrl & TIOCM_RTS)) { 695 ctrl |= SCPCR_RTSC; 696 data |= SCPDR_RTSD; 697 } else if (!s->autorts) { 698 ctrl |= SCPCR_RTSC; 699 data &= ~SCPDR_RTSD; 700 } else { 701 /* Enable RTS# pin function */ 702 ctrl &= ~SCPCR_RTSC; 703 } 704 /* Enable CTS# pin function */ 705 ctrl &= ~SCPCR_CTSC; 706 } 707 serial_port_out(port, SCPDR, data); 708 serial_port_out(port, SCPCR, ctrl); 709 } else if (sci_getreg(port, SCSPTR)->size) { 710 u16 status = serial_port_in(port, SCSPTR); 711 712 /* RTS# is always output; and active low, unless autorts */ 713 status |= SCSPTR_RTSIO; 714 if (!(port->mctrl & TIOCM_RTS)) 715 status |= SCSPTR_RTSDT; 716 else if (!s->autorts) 717 status &= ~SCSPTR_RTSDT; 718 /* CTS# and SCK are inputs */ 719 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO); 720 serial_port_out(port, SCSPTR, status); 721 } 722 } 723 724 static int sci_txfill(struct uart_port *port) 725 { 726 struct sci_port *s = to_sci_port(port); 727 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; 728 const struct plat_sci_reg *reg; 729 730 reg = sci_getreg(port, SCTFDR); 731 if (reg->size) 732 return serial_port_in(port, SCTFDR) & fifo_mask; 733 734 reg = sci_getreg(port, SCFDR); 735 if (reg->size) 736 return serial_port_in(port, SCFDR) >> 8; 737 738 return !(serial_port_in(port, SCxSR) & SCI_TDRE); 739 } 740 741 static int sci_txroom(struct uart_port *port) 742 { 743 return port->fifosize - sci_txfill(port); 744 } 745 746 static int sci_rxfill(struct uart_port *port) 747 { 748 struct sci_port *s = to_sci_port(port); 749 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; 750 const struct plat_sci_reg *reg; 751 752 reg = sci_getreg(port, SCRFDR); 753 if (reg->size) 754 return serial_port_in(port, SCRFDR) & fifo_mask; 755 756 reg = sci_getreg(port, SCFDR); 757 if (reg->size) 758 return serial_port_in(port, SCFDR) & fifo_mask; 759 760 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0; 761 } 762 763 /* ********************************************************************** * 764 * the interrupt related routines * 765 * ********************************************************************** */ 766 767 static void sci_transmit_chars(struct uart_port *port) 768 { 769 struct circ_buf *xmit = &port->state->xmit; 770 unsigned int stopped = uart_tx_stopped(port); 771 unsigned short status; 772 unsigned short ctrl; 773 int count; 774 775 status = serial_port_in(port, SCxSR); 776 if (!(status & SCxSR_TDxE(port))) { 777 ctrl = serial_port_in(port, SCSCR); 778 if (uart_circ_empty(xmit)) 779 ctrl &= ~SCSCR_TIE; 780 else 781 ctrl |= SCSCR_TIE; 782 serial_port_out(port, SCSCR, ctrl); 783 return; 784 } 785 786 count = sci_txroom(port); 787 788 do { 789 unsigned char c; 790 791 if (port->x_char) { 792 c = port->x_char; 793 port->x_char = 0; 794 } else if (!uart_circ_empty(xmit) && !stopped) { 795 c = xmit->buf[xmit->tail]; 796 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 797 } else { 798 break; 799 } 800 801 serial_port_out(port, SCxTDR, c); 802 803 port->icount.tx++; 804 } while (--count > 0); 805 806 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port)); 807 808 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 809 uart_write_wakeup(port); 810 if (uart_circ_empty(xmit)) { 811 sci_stop_tx(port); 812 } else { 813 ctrl = serial_port_in(port, SCSCR); 814 815 if (port->type != PORT_SCI) { 816 serial_port_in(port, SCxSR); /* Dummy read */ 817 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port)); 818 } 819 820 ctrl |= SCSCR_TIE; 821 serial_port_out(port, SCSCR, ctrl); 822 } 823 } 824 825 /* On SH3, SCIF may read end-of-break as a space->mark char */ 826 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); }) 827 828 static void sci_receive_chars(struct uart_port *port) 829 { 830 struct tty_port *tport = &port->state->port; 831 int i, count, copied = 0; 832 unsigned short status; 833 unsigned char flag; 834 835 status = serial_port_in(port, SCxSR); 836 if (!(status & SCxSR_RDxF(port))) 837 return; 838 839 while (1) { 840 /* Don't copy more bytes than there is room for in the buffer */ 841 count = tty_buffer_request_room(tport, sci_rxfill(port)); 842 843 /* If for any reason we can't copy more data, we're done! */ 844 if (count == 0) 845 break; 846 847 if (port->type == PORT_SCI) { 848 char c = serial_port_in(port, SCxRDR); 849 if (uart_handle_sysrq_char(port, c)) 850 count = 0; 851 else 852 tty_insert_flip_char(tport, c, TTY_NORMAL); 853 } else { 854 for (i = 0; i < count; i++) { 855 char c = serial_port_in(port, SCxRDR); 856 857 status = serial_port_in(port, SCxSR); 858 if (uart_handle_sysrq_char(port, c)) { 859 count--; i--; 860 continue; 861 } 862 863 /* Store data and status */ 864 if (status & SCxSR_FER(port)) { 865 flag = TTY_FRAME; 866 port->icount.frame++; 867 dev_notice(port->dev, "frame error\n"); 868 } else if (status & SCxSR_PER(port)) { 869 flag = TTY_PARITY; 870 port->icount.parity++; 871 dev_notice(port->dev, "parity error\n"); 872 } else 873 flag = TTY_NORMAL; 874 875 tty_insert_flip_char(tport, c, flag); 876 } 877 } 878 879 serial_port_in(port, SCxSR); /* dummy read */ 880 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 881 882 copied += count; 883 port->icount.rx += count; 884 } 885 886 if (copied) { 887 /* Tell the rest of the system the news. New characters! */ 888 tty_flip_buffer_push(tport); 889 } else { 890 /* TTY buffers full; read from RX reg to prevent lockup */ 891 serial_port_in(port, SCxRDR); 892 serial_port_in(port, SCxSR); /* dummy read */ 893 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 894 } 895 } 896 897 static int sci_handle_errors(struct uart_port *port) 898 { 899 int copied = 0; 900 unsigned short status = serial_port_in(port, SCxSR); 901 struct tty_port *tport = &port->state->port; 902 struct sci_port *s = to_sci_port(port); 903 904 /* Handle overruns */ 905 if (status & s->params->overrun_mask) { 906 port->icount.overrun++; 907 908 /* overrun error */ 909 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN)) 910 copied++; 911 912 dev_notice(port->dev, "overrun error\n"); 913 } 914 915 if (status & SCxSR_FER(port)) { 916 /* frame error */ 917 port->icount.frame++; 918 919 if (tty_insert_flip_char(tport, 0, TTY_FRAME)) 920 copied++; 921 922 dev_notice(port->dev, "frame error\n"); 923 } 924 925 if (status & SCxSR_PER(port)) { 926 /* parity error */ 927 port->icount.parity++; 928 929 if (tty_insert_flip_char(tport, 0, TTY_PARITY)) 930 copied++; 931 932 dev_notice(port->dev, "parity error\n"); 933 } 934 935 if (copied) 936 tty_flip_buffer_push(tport); 937 938 return copied; 939 } 940 941 static int sci_handle_fifo_overrun(struct uart_port *port) 942 { 943 struct tty_port *tport = &port->state->port; 944 struct sci_port *s = to_sci_port(port); 945 const struct plat_sci_reg *reg; 946 int copied = 0; 947 u16 status; 948 949 reg = sci_getreg(port, s->params->overrun_reg); 950 if (!reg->size) 951 return 0; 952 953 status = serial_port_in(port, s->params->overrun_reg); 954 if (status & s->params->overrun_mask) { 955 status &= ~s->params->overrun_mask; 956 serial_port_out(port, s->params->overrun_reg, status); 957 958 port->icount.overrun++; 959 960 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 961 tty_flip_buffer_push(tport); 962 963 dev_dbg(port->dev, "overrun error\n"); 964 copied++; 965 } 966 967 return copied; 968 } 969 970 static int sci_handle_breaks(struct uart_port *port) 971 { 972 int copied = 0; 973 unsigned short status = serial_port_in(port, SCxSR); 974 struct tty_port *tport = &port->state->port; 975 976 if (uart_handle_break(port)) 977 return 0; 978 979 if (status & SCxSR_BRK(port)) { 980 port->icount.brk++; 981 982 /* Notify of BREAK */ 983 if (tty_insert_flip_char(tport, 0, TTY_BREAK)) 984 copied++; 985 986 dev_dbg(port->dev, "BREAK detected\n"); 987 } 988 989 if (copied) 990 tty_flip_buffer_push(tport); 991 992 copied += sci_handle_fifo_overrun(port); 993 994 return copied; 995 } 996 997 static int scif_set_rtrg(struct uart_port *port, int rx_trig) 998 { 999 unsigned int bits; 1000 1001 if (rx_trig < 1) 1002 rx_trig = 1; 1003 if (rx_trig >= port->fifosize) 1004 rx_trig = port->fifosize; 1005 1006 /* HSCIF can be set to an arbitrary level. */ 1007 if (sci_getreg(port, HSRTRGR)->size) { 1008 serial_port_out(port, HSRTRGR, rx_trig); 1009 return rx_trig; 1010 } 1011 1012 switch (port->type) { 1013 case PORT_SCIF: 1014 if (rx_trig < 4) { 1015 bits = 0; 1016 rx_trig = 1; 1017 } else if (rx_trig < 8) { 1018 bits = SCFCR_RTRG0; 1019 rx_trig = 4; 1020 } else if (rx_trig < 14) { 1021 bits = SCFCR_RTRG1; 1022 rx_trig = 8; 1023 } else { 1024 bits = SCFCR_RTRG0 | SCFCR_RTRG1; 1025 rx_trig = 14; 1026 } 1027 break; 1028 case PORT_SCIFA: 1029 case PORT_SCIFB: 1030 if (rx_trig < 16) { 1031 bits = 0; 1032 rx_trig = 1; 1033 } else if (rx_trig < 32) { 1034 bits = SCFCR_RTRG0; 1035 rx_trig = 16; 1036 } else if (rx_trig < 48) { 1037 bits = SCFCR_RTRG1; 1038 rx_trig = 32; 1039 } else { 1040 bits = SCFCR_RTRG0 | SCFCR_RTRG1; 1041 rx_trig = 48; 1042 } 1043 break; 1044 default: 1045 WARN(1, "unknown FIFO configuration"); 1046 return 1; 1047 } 1048 1049 serial_port_out(port, SCFCR, 1050 (serial_port_in(port, SCFCR) & 1051 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits); 1052 1053 return rx_trig; 1054 } 1055 1056 static int scif_rtrg_enabled(struct uart_port *port) 1057 { 1058 if (sci_getreg(port, HSRTRGR)->size) 1059 return serial_port_in(port, HSRTRGR) != 0; 1060 else 1061 return (serial_port_in(port, SCFCR) & 1062 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0; 1063 } 1064 1065 static void rx_fifo_timer_fn(struct timer_list *t) 1066 { 1067 struct sci_port *s = from_timer(s, t, rx_fifo_timer); 1068 struct uart_port *port = &s->port; 1069 1070 dev_dbg(port->dev, "Rx timed out\n"); 1071 scif_set_rtrg(port, 1); 1072 } 1073 1074 static ssize_t rx_trigger_show(struct device *dev, 1075 struct device_attribute *attr, 1076 char *buf) 1077 { 1078 struct uart_port *port = dev_get_drvdata(dev); 1079 struct sci_port *sci = to_sci_port(port); 1080 1081 return sprintf(buf, "%d\n", sci->rx_trigger); 1082 } 1083 1084 static ssize_t rx_trigger_store(struct device *dev, 1085 struct device_attribute *attr, 1086 const char *buf, 1087 size_t count) 1088 { 1089 struct uart_port *port = dev_get_drvdata(dev); 1090 struct sci_port *sci = to_sci_port(port); 1091 int ret; 1092 long r; 1093 1094 ret = kstrtol(buf, 0, &r); 1095 if (ret) 1096 return ret; 1097 1098 sci->rx_trigger = scif_set_rtrg(port, r); 1099 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1100 scif_set_rtrg(port, 1); 1101 1102 return count; 1103 } 1104 1105 static DEVICE_ATTR(rx_fifo_trigger, 0644, rx_trigger_show, rx_trigger_store); 1106 1107 static ssize_t rx_fifo_timeout_show(struct device *dev, 1108 struct device_attribute *attr, 1109 char *buf) 1110 { 1111 struct uart_port *port = dev_get_drvdata(dev); 1112 struct sci_port *sci = to_sci_port(port); 1113 int v; 1114 1115 if (port->type == PORT_HSCIF) 1116 v = sci->hscif_tot >> HSSCR_TOT_SHIFT; 1117 else 1118 v = sci->rx_fifo_timeout; 1119 1120 return sprintf(buf, "%d\n", v); 1121 } 1122 1123 static ssize_t rx_fifo_timeout_store(struct device *dev, 1124 struct device_attribute *attr, 1125 const char *buf, 1126 size_t count) 1127 { 1128 struct uart_port *port = dev_get_drvdata(dev); 1129 struct sci_port *sci = to_sci_port(port); 1130 int ret; 1131 long r; 1132 1133 ret = kstrtol(buf, 0, &r); 1134 if (ret) 1135 return ret; 1136 1137 if (port->type == PORT_HSCIF) { 1138 if (r < 0 || r > 3) 1139 return -EINVAL; 1140 sci->hscif_tot = r << HSSCR_TOT_SHIFT; 1141 } else { 1142 sci->rx_fifo_timeout = r; 1143 scif_set_rtrg(port, 1); 1144 if (r > 0) 1145 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0); 1146 } 1147 1148 return count; 1149 } 1150 1151 static DEVICE_ATTR_RW(rx_fifo_timeout); 1152 1153 1154 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1155 static void sci_dma_tx_complete(void *arg) 1156 { 1157 struct sci_port *s = arg; 1158 struct uart_port *port = &s->port; 1159 struct circ_buf *xmit = &port->state->xmit; 1160 unsigned long flags; 1161 1162 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1163 1164 spin_lock_irqsave(&port->lock, flags); 1165 1166 xmit->tail += s->tx_dma_len; 1167 xmit->tail &= UART_XMIT_SIZE - 1; 1168 1169 port->icount.tx += s->tx_dma_len; 1170 1171 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1172 uart_write_wakeup(port); 1173 1174 if (!uart_circ_empty(xmit)) { 1175 s->cookie_tx = 0; 1176 schedule_work(&s->work_tx); 1177 } else { 1178 s->cookie_tx = -EINVAL; 1179 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1180 u16 ctrl = serial_port_in(port, SCSCR); 1181 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE); 1182 } 1183 } 1184 1185 spin_unlock_irqrestore(&port->lock, flags); 1186 } 1187 1188 /* Locking: called with port lock held */ 1189 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count) 1190 { 1191 struct uart_port *port = &s->port; 1192 struct tty_port *tport = &port->state->port; 1193 int copied; 1194 1195 copied = tty_insert_flip_string(tport, buf, count); 1196 if (copied < count) 1197 port->icount.buf_overrun++; 1198 1199 port->icount.rx += copied; 1200 1201 return copied; 1202 } 1203 1204 static int sci_dma_rx_find_active(struct sci_port *s) 1205 { 1206 unsigned int i; 1207 1208 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) 1209 if (s->active_rx == s->cookie_rx[i]) 1210 return i; 1211 1212 return -1; 1213 } 1214 1215 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio) 1216 { 1217 struct dma_chan *chan = s->chan_rx; 1218 struct uart_port *port = &s->port; 1219 unsigned long flags; 1220 1221 spin_lock_irqsave(&port->lock, flags); 1222 s->chan_rx = NULL; 1223 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL; 1224 spin_unlock_irqrestore(&port->lock, flags); 1225 dmaengine_terminate_all(chan); 1226 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0], 1227 sg_dma_address(&s->sg_rx[0])); 1228 dma_release_channel(chan); 1229 if (enable_pio) { 1230 spin_lock_irqsave(&port->lock, flags); 1231 sci_start_rx(port); 1232 spin_unlock_irqrestore(&port->lock, flags); 1233 } 1234 } 1235 1236 static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec) 1237 { 1238 long sec = usec / 1000000; 1239 long nsec = (usec % 1000000) * 1000; 1240 ktime_t t = ktime_set(sec, nsec); 1241 1242 hrtimer_start(hrt, t, HRTIMER_MODE_REL); 1243 } 1244 1245 static void sci_dma_rx_complete(void *arg) 1246 { 1247 struct sci_port *s = arg; 1248 struct dma_chan *chan = s->chan_rx; 1249 struct uart_port *port = &s->port; 1250 struct dma_async_tx_descriptor *desc; 1251 unsigned long flags; 1252 int active, count = 0; 1253 1254 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line, 1255 s->active_rx); 1256 1257 spin_lock_irqsave(&port->lock, flags); 1258 1259 active = sci_dma_rx_find_active(s); 1260 if (active >= 0) 1261 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx); 1262 1263 start_hrtimer_us(&s->rx_timer, s->rx_timeout); 1264 1265 if (count) 1266 tty_flip_buffer_push(&port->state->port); 1267 1268 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1, 1269 DMA_DEV_TO_MEM, 1270 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1271 if (!desc) 1272 goto fail; 1273 1274 desc->callback = sci_dma_rx_complete; 1275 desc->callback_param = s; 1276 s->cookie_rx[active] = dmaengine_submit(desc); 1277 if (dma_submit_error(s->cookie_rx[active])) 1278 goto fail; 1279 1280 s->active_rx = s->cookie_rx[!active]; 1281 1282 dma_async_issue_pending(chan); 1283 1284 spin_unlock_irqrestore(&port->lock, flags); 1285 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n", 1286 __func__, s->cookie_rx[active], active, s->active_rx); 1287 return; 1288 1289 fail: 1290 spin_unlock_irqrestore(&port->lock, flags); 1291 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n"); 1292 sci_rx_dma_release(s, true); 1293 } 1294 1295 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio) 1296 { 1297 struct dma_chan *chan = s->chan_tx; 1298 struct uart_port *port = &s->port; 1299 unsigned long flags; 1300 1301 spin_lock_irqsave(&port->lock, flags); 1302 s->chan_tx = NULL; 1303 s->cookie_tx = -EINVAL; 1304 spin_unlock_irqrestore(&port->lock, flags); 1305 dmaengine_terminate_all(chan); 1306 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE, 1307 DMA_TO_DEVICE); 1308 dma_release_channel(chan); 1309 if (enable_pio) { 1310 spin_lock_irqsave(&port->lock, flags); 1311 sci_start_tx(port); 1312 spin_unlock_irqrestore(&port->lock, flags); 1313 } 1314 } 1315 1316 static void sci_submit_rx(struct sci_port *s) 1317 { 1318 struct dma_chan *chan = s->chan_rx; 1319 int i; 1320 1321 for (i = 0; i < 2; i++) { 1322 struct scatterlist *sg = &s->sg_rx[i]; 1323 struct dma_async_tx_descriptor *desc; 1324 1325 desc = dmaengine_prep_slave_sg(chan, 1326 sg, 1, DMA_DEV_TO_MEM, 1327 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1328 if (!desc) 1329 goto fail; 1330 1331 desc->callback = sci_dma_rx_complete; 1332 desc->callback_param = s; 1333 s->cookie_rx[i] = dmaengine_submit(desc); 1334 if (dma_submit_error(s->cookie_rx[i])) 1335 goto fail; 1336 1337 } 1338 1339 s->active_rx = s->cookie_rx[0]; 1340 1341 dma_async_issue_pending(chan); 1342 return; 1343 1344 fail: 1345 if (i) 1346 dmaengine_terminate_all(chan); 1347 for (i = 0; i < 2; i++) 1348 s->cookie_rx[i] = -EINVAL; 1349 s->active_rx = -EINVAL; 1350 sci_rx_dma_release(s, true); 1351 } 1352 1353 static void work_fn_tx(struct work_struct *work) 1354 { 1355 struct sci_port *s = container_of(work, struct sci_port, work_tx); 1356 struct dma_async_tx_descriptor *desc; 1357 struct dma_chan *chan = s->chan_tx; 1358 struct uart_port *port = &s->port; 1359 struct circ_buf *xmit = &port->state->xmit; 1360 dma_addr_t buf; 1361 1362 /* 1363 * DMA is idle now. 1364 * Port xmit buffer is already mapped, and it is one page... Just adjust 1365 * offsets and lengths. Since it is a circular buffer, we have to 1366 * transmit till the end, and then the rest. Take the port lock to get a 1367 * consistent xmit buffer state. 1368 */ 1369 spin_lock_irq(&port->lock); 1370 buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1)); 1371 s->tx_dma_len = min_t(unsigned int, 1372 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE), 1373 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE)); 1374 spin_unlock_irq(&port->lock); 1375 1376 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len, 1377 DMA_MEM_TO_DEV, 1378 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1379 if (!desc) { 1380 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n"); 1381 /* switch to PIO */ 1382 sci_tx_dma_release(s, true); 1383 return; 1384 } 1385 1386 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len, 1387 DMA_TO_DEVICE); 1388 1389 spin_lock_irq(&port->lock); 1390 desc->callback = sci_dma_tx_complete; 1391 desc->callback_param = s; 1392 spin_unlock_irq(&port->lock); 1393 s->cookie_tx = dmaengine_submit(desc); 1394 if (dma_submit_error(s->cookie_tx)) { 1395 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n"); 1396 /* switch to PIO */ 1397 sci_tx_dma_release(s, true); 1398 return; 1399 } 1400 1401 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", 1402 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx); 1403 1404 dma_async_issue_pending(chan); 1405 } 1406 1407 static enum hrtimer_restart rx_timer_fn(struct hrtimer *t) 1408 { 1409 struct sci_port *s = container_of(t, struct sci_port, rx_timer); 1410 struct dma_chan *chan = s->chan_rx; 1411 struct uart_port *port = &s->port; 1412 struct dma_tx_state state; 1413 enum dma_status status; 1414 unsigned long flags; 1415 unsigned int read; 1416 int active, count; 1417 u16 scr; 1418 1419 dev_dbg(port->dev, "DMA Rx timed out\n"); 1420 1421 spin_lock_irqsave(&port->lock, flags); 1422 1423 active = sci_dma_rx_find_active(s); 1424 if (active < 0) { 1425 spin_unlock_irqrestore(&port->lock, flags); 1426 return HRTIMER_NORESTART; 1427 } 1428 1429 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); 1430 if (status == DMA_COMPLETE) { 1431 spin_unlock_irqrestore(&port->lock, flags); 1432 dev_dbg(port->dev, "Cookie %d #%d has already completed\n", 1433 s->active_rx, active); 1434 1435 /* Let packet complete handler take care of the packet */ 1436 return HRTIMER_NORESTART; 1437 } 1438 1439 dmaengine_pause(chan); 1440 1441 /* 1442 * sometimes DMA transfer doesn't stop even if it is stopped and 1443 * data keeps on coming until transaction is complete so check 1444 * for DMA_COMPLETE again 1445 * Let packet complete handler take care of the packet 1446 */ 1447 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); 1448 if (status == DMA_COMPLETE) { 1449 spin_unlock_irqrestore(&port->lock, flags); 1450 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped"); 1451 return HRTIMER_NORESTART; 1452 } 1453 1454 /* Handle incomplete DMA receive */ 1455 dmaengine_terminate_all(s->chan_rx); 1456 read = sg_dma_len(&s->sg_rx[active]) - state.residue; 1457 1458 if (read) { 1459 count = sci_dma_rx_push(s, s->rx_buf[active], read); 1460 if (count) 1461 tty_flip_buffer_push(&port->state->port); 1462 } 1463 1464 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1465 sci_submit_rx(s); 1466 1467 /* Direct new serial port interrupts back to CPU */ 1468 scr = serial_port_in(port, SCSCR); 1469 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1470 scr &= ~SCSCR_RDRQE; 1471 enable_irq(s->irqs[SCIx_RXI_IRQ]); 1472 } 1473 serial_port_out(port, SCSCR, scr | SCSCR_RIE); 1474 1475 spin_unlock_irqrestore(&port->lock, flags); 1476 1477 return HRTIMER_NORESTART; 1478 } 1479 1480 static struct dma_chan *sci_request_dma_chan(struct uart_port *port, 1481 enum dma_transfer_direction dir) 1482 { 1483 struct dma_chan *chan; 1484 struct dma_slave_config cfg; 1485 int ret; 1486 1487 chan = dma_request_slave_channel(port->dev, 1488 dir == DMA_MEM_TO_DEV ? "tx" : "rx"); 1489 if (!chan) { 1490 dev_warn(port->dev, "dma_request_slave_channel failed\n"); 1491 return NULL; 1492 } 1493 1494 memset(&cfg, 0, sizeof(cfg)); 1495 cfg.direction = dir; 1496 if (dir == DMA_MEM_TO_DEV) { 1497 cfg.dst_addr = port->mapbase + 1498 (sci_getreg(port, SCxTDR)->offset << port->regshift); 1499 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1500 } else { 1501 cfg.src_addr = port->mapbase + 1502 (sci_getreg(port, SCxRDR)->offset << port->regshift); 1503 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1504 } 1505 1506 ret = dmaengine_slave_config(chan, &cfg); 1507 if (ret) { 1508 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret); 1509 dma_release_channel(chan); 1510 return NULL; 1511 } 1512 1513 return chan; 1514 } 1515 1516 static void sci_request_dma(struct uart_port *port) 1517 { 1518 struct sci_port *s = to_sci_port(port); 1519 struct dma_chan *chan; 1520 1521 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line); 1522 1523 if (!port->dev->of_node) 1524 return; 1525 1526 s->cookie_tx = -EINVAL; 1527 1528 /* 1529 * Don't request a dma channel if no channel was specified 1530 * in the device tree. 1531 */ 1532 if (!of_find_property(port->dev->of_node, "dmas", NULL)) 1533 return; 1534 1535 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV); 1536 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan); 1537 if (chan) { 1538 s->chan_tx = chan; 1539 /* UART circular tx buffer is an aligned page. */ 1540 s->tx_dma_addr = dma_map_single(chan->device->dev, 1541 port->state->xmit.buf, 1542 UART_XMIT_SIZE, 1543 DMA_TO_DEVICE); 1544 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) { 1545 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n"); 1546 dma_release_channel(chan); 1547 s->chan_tx = NULL; 1548 } else { 1549 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n", 1550 __func__, UART_XMIT_SIZE, 1551 port->state->xmit.buf, &s->tx_dma_addr); 1552 } 1553 1554 INIT_WORK(&s->work_tx, work_fn_tx); 1555 } 1556 1557 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM); 1558 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan); 1559 if (chan) { 1560 unsigned int i; 1561 dma_addr_t dma; 1562 void *buf; 1563 1564 s->chan_rx = chan; 1565 1566 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize); 1567 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2, 1568 &dma, GFP_KERNEL); 1569 if (!buf) { 1570 dev_warn(port->dev, 1571 "Failed to allocate Rx dma buffer, using PIO\n"); 1572 dma_release_channel(chan); 1573 s->chan_rx = NULL; 1574 return; 1575 } 1576 1577 for (i = 0; i < 2; i++) { 1578 struct scatterlist *sg = &s->sg_rx[i]; 1579 1580 sg_init_table(sg, 1); 1581 s->rx_buf[i] = buf; 1582 sg_dma_address(sg) = dma; 1583 sg_dma_len(sg) = s->buf_len_rx; 1584 1585 buf += s->buf_len_rx; 1586 dma += s->buf_len_rx; 1587 } 1588 1589 hrtimer_init(&s->rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 1590 s->rx_timer.function = rx_timer_fn; 1591 1592 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1593 sci_submit_rx(s); 1594 } 1595 } 1596 1597 static void sci_free_dma(struct uart_port *port) 1598 { 1599 struct sci_port *s = to_sci_port(port); 1600 1601 if (s->chan_tx) 1602 sci_tx_dma_release(s, false); 1603 if (s->chan_rx) 1604 sci_rx_dma_release(s, false); 1605 } 1606 1607 static void sci_flush_buffer(struct uart_port *port) 1608 { 1609 /* 1610 * In uart_flush_buffer(), the xmit circular buffer has just been 1611 * cleared, so we have to reset tx_dma_len accordingly. 1612 */ 1613 to_sci_port(port)->tx_dma_len = 0; 1614 } 1615 #else /* !CONFIG_SERIAL_SH_SCI_DMA */ 1616 static inline void sci_request_dma(struct uart_port *port) 1617 { 1618 } 1619 1620 static inline void sci_free_dma(struct uart_port *port) 1621 { 1622 } 1623 1624 #define sci_flush_buffer NULL 1625 #endif /* !CONFIG_SERIAL_SH_SCI_DMA */ 1626 1627 static irqreturn_t sci_rx_interrupt(int irq, void *ptr) 1628 { 1629 struct uart_port *port = ptr; 1630 struct sci_port *s = to_sci_port(port); 1631 1632 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1633 if (s->chan_rx) { 1634 u16 scr = serial_port_in(port, SCSCR); 1635 u16 ssr = serial_port_in(port, SCxSR); 1636 1637 /* Disable future Rx interrupts */ 1638 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1639 disable_irq_nosync(irq); 1640 scr |= SCSCR_RDRQE; 1641 } else { 1642 scr &= ~SCSCR_RIE; 1643 sci_submit_rx(s); 1644 } 1645 serial_port_out(port, SCSCR, scr); 1646 /* Clear current interrupt */ 1647 serial_port_out(port, SCxSR, 1648 ssr & ~(SCIF_DR | SCxSR_RDxF(port))); 1649 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n", 1650 jiffies, s->rx_timeout); 1651 start_hrtimer_us(&s->rx_timer, s->rx_timeout); 1652 1653 return IRQ_HANDLED; 1654 } 1655 #endif 1656 1657 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) { 1658 if (!scif_rtrg_enabled(port)) 1659 scif_set_rtrg(port, s->rx_trigger); 1660 1661 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP( 1662 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000)); 1663 } 1664 1665 /* I think sci_receive_chars has to be called irrespective 1666 * of whether the I_IXOFF is set, otherwise, how is the interrupt 1667 * to be disabled? 1668 */ 1669 sci_receive_chars(ptr); 1670 1671 return IRQ_HANDLED; 1672 } 1673 1674 static irqreturn_t sci_tx_interrupt(int irq, void *ptr) 1675 { 1676 struct uart_port *port = ptr; 1677 unsigned long flags; 1678 1679 spin_lock_irqsave(&port->lock, flags); 1680 sci_transmit_chars(port); 1681 spin_unlock_irqrestore(&port->lock, flags); 1682 1683 return IRQ_HANDLED; 1684 } 1685 1686 static irqreturn_t sci_er_interrupt(int irq, void *ptr) 1687 { 1688 struct uart_port *port = ptr; 1689 struct sci_port *s = to_sci_port(port); 1690 1691 /* Handle errors */ 1692 if (port->type == PORT_SCI) { 1693 if (sci_handle_errors(port)) { 1694 /* discard character in rx buffer */ 1695 serial_port_in(port, SCxSR); 1696 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 1697 } 1698 } else { 1699 sci_handle_fifo_overrun(port); 1700 if (!s->chan_rx) 1701 sci_receive_chars(ptr); 1702 } 1703 1704 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); 1705 1706 /* Kick the transmission */ 1707 if (!s->chan_tx) 1708 sci_tx_interrupt(irq, ptr); 1709 1710 return IRQ_HANDLED; 1711 } 1712 1713 static irqreturn_t sci_br_interrupt(int irq, void *ptr) 1714 { 1715 struct uart_port *port = ptr; 1716 1717 /* Handle BREAKs */ 1718 sci_handle_breaks(port); 1719 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port)); 1720 1721 return IRQ_HANDLED; 1722 } 1723 1724 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) 1725 { 1726 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0; 1727 struct uart_port *port = ptr; 1728 struct sci_port *s = to_sci_port(port); 1729 irqreturn_t ret = IRQ_NONE; 1730 1731 ssr_status = serial_port_in(port, SCxSR); 1732 scr_status = serial_port_in(port, SCSCR); 1733 if (s->params->overrun_reg == SCxSR) 1734 orer_status = ssr_status; 1735 else if (sci_getreg(port, s->params->overrun_reg)->size) 1736 orer_status = serial_port_in(port, s->params->overrun_reg); 1737 1738 err_enabled = scr_status & port_rx_irq_mask(port); 1739 1740 /* Tx Interrupt */ 1741 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) && 1742 !s->chan_tx) 1743 ret = sci_tx_interrupt(irq, ptr); 1744 1745 /* 1746 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF / 1747 * DR flags 1748 */ 1749 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) && 1750 (scr_status & SCSCR_RIE)) 1751 ret = sci_rx_interrupt(irq, ptr); 1752 1753 /* Error Interrupt */ 1754 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled) 1755 ret = sci_er_interrupt(irq, ptr); 1756 1757 /* Break Interrupt */ 1758 if ((ssr_status & SCxSR_BRK(port)) && err_enabled) 1759 ret = sci_br_interrupt(irq, ptr); 1760 1761 /* Overrun Interrupt */ 1762 if (orer_status & s->params->overrun_mask) { 1763 sci_handle_fifo_overrun(port); 1764 ret = IRQ_HANDLED; 1765 } 1766 1767 return ret; 1768 } 1769 1770 static const struct sci_irq_desc { 1771 const char *desc; 1772 irq_handler_t handler; 1773 } sci_irq_desc[] = { 1774 /* 1775 * Split out handlers, the default case. 1776 */ 1777 [SCIx_ERI_IRQ] = { 1778 .desc = "rx err", 1779 .handler = sci_er_interrupt, 1780 }, 1781 1782 [SCIx_RXI_IRQ] = { 1783 .desc = "rx full", 1784 .handler = sci_rx_interrupt, 1785 }, 1786 1787 [SCIx_TXI_IRQ] = { 1788 .desc = "tx empty", 1789 .handler = sci_tx_interrupt, 1790 }, 1791 1792 [SCIx_BRI_IRQ] = { 1793 .desc = "break", 1794 .handler = sci_br_interrupt, 1795 }, 1796 1797 /* 1798 * Special muxed handler. 1799 */ 1800 [SCIx_MUX_IRQ] = { 1801 .desc = "mux", 1802 .handler = sci_mpxed_interrupt, 1803 }, 1804 }; 1805 1806 static int sci_request_irq(struct sci_port *port) 1807 { 1808 struct uart_port *up = &port->port; 1809 int i, j, ret = 0; 1810 1811 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) { 1812 const struct sci_irq_desc *desc; 1813 int irq; 1814 1815 if (SCIx_IRQ_IS_MUXED(port)) { 1816 i = SCIx_MUX_IRQ; 1817 irq = up->irq; 1818 } else { 1819 irq = port->irqs[i]; 1820 1821 /* 1822 * Certain port types won't support all of the 1823 * available interrupt sources. 1824 */ 1825 if (unlikely(irq < 0)) 1826 continue; 1827 } 1828 1829 desc = sci_irq_desc + i; 1830 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s", 1831 dev_name(up->dev), desc->desc); 1832 if (!port->irqstr[j]) { 1833 ret = -ENOMEM; 1834 goto out_nomem; 1835 } 1836 1837 ret = request_irq(irq, desc->handler, up->irqflags, 1838 port->irqstr[j], port); 1839 if (unlikely(ret)) { 1840 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc); 1841 goto out_noirq; 1842 } 1843 } 1844 1845 return 0; 1846 1847 out_noirq: 1848 while (--i >= 0) 1849 free_irq(port->irqs[i], port); 1850 1851 out_nomem: 1852 while (--j >= 0) 1853 kfree(port->irqstr[j]); 1854 1855 return ret; 1856 } 1857 1858 static void sci_free_irq(struct sci_port *port) 1859 { 1860 int i; 1861 1862 /* 1863 * Intentionally in reverse order so we iterate over the muxed 1864 * IRQ first. 1865 */ 1866 for (i = 0; i < SCIx_NR_IRQS; i++) { 1867 int irq = port->irqs[i]; 1868 1869 /* 1870 * Certain port types won't support all of the available 1871 * interrupt sources. 1872 */ 1873 if (unlikely(irq < 0)) 1874 continue; 1875 1876 free_irq(port->irqs[i], port); 1877 kfree(port->irqstr[i]); 1878 1879 if (SCIx_IRQ_IS_MUXED(port)) { 1880 /* If there's only one IRQ, we're done. */ 1881 return; 1882 } 1883 } 1884 } 1885 1886 static unsigned int sci_tx_empty(struct uart_port *port) 1887 { 1888 unsigned short status = serial_port_in(port, SCxSR); 1889 unsigned short in_tx_fifo = sci_txfill(port); 1890 1891 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0; 1892 } 1893 1894 static void sci_set_rts(struct uart_port *port, bool state) 1895 { 1896 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1897 u16 data = serial_port_in(port, SCPDR); 1898 1899 /* Active low */ 1900 if (state) 1901 data &= ~SCPDR_RTSD; 1902 else 1903 data |= SCPDR_RTSD; 1904 serial_port_out(port, SCPDR, data); 1905 1906 /* RTS# is output */ 1907 serial_port_out(port, SCPCR, 1908 serial_port_in(port, SCPCR) | SCPCR_RTSC); 1909 } else if (sci_getreg(port, SCSPTR)->size) { 1910 u16 ctrl = serial_port_in(port, SCSPTR); 1911 1912 /* Active low */ 1913 if (state) 1914 ctrl &= ~SCSPTR_RTSDT; 1915 else 1916 ctrl |= SCSPTR_RTSDT; 1917 serial_port_out(port, SCSPTR, ctrl); 1918 } 1919 } 1920 1921 static bool sci_get_cts(struct uart_port *port) 1922 { 1923 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1924 /* Active low */ 1925 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD); 1926 } else if (sci_getreg(port, SCSPTR)->size) { 1927 /* Active low */ 1928 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT); 1929 } 1930 1931 return true; 1932 } 1933 1934 /* 1935 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally 1936 * CTS/RTS is supported in hardware by at least one port and controlled 1937 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently 1938 * handled via the ->init_pins() op, which is a bit of a one-way street, 1939 * lacking any ability to defer pin control -- this will later be 1940 * converted over to the GPIO framework). 1941 * 1942 * Other modes (such as loopback) are supported generically on certain 1943 * port types, but not others. For these it's sufficient to test for the 1944 * existence of the support register and simply ignore the port type. 1945 */ 1946 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) 1947 { 1948 struct sci_port *s = to_sci_port(port); 1949 1950 if (mctrl & TIOCM_LOOP) { 1951 const struct plat_sci_reg *reg; 1952 1953 /* 1954 * Standard loopback mode for SCFCR ports. 1955 */ 1956 reg = sci_getreg(port, SCFCR); 1957 if (reg->size) 1958 serial_port_out(port, SCFCR, 1959 serial_port_in(port, SCFCR) | 1960 SCFCR_LOOP); 1961 } 1962 1963 mctrl_gpio_set(s->gpios, mctrl); 1964 1965 if (!s->has_rtscts) 1966 return; 1967 1968 if (!(mctrl & TIOCM_RTS)) { 1969 /* Disable Auto RTS */ 1970 serial_port_out(port, SCFCR, 1971 serial_port_in(port, SCFCR) & ~SCFCR_MCE); 1972 1973 /* Clear RTS */ 1974 sci_set_rts(port, 0); 1975 } else if (s->autorts) { 1976 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1977 /* Enable RTS# pin function */ 1978 serial_port_out(port, SCPCR, 1979 serial_port_in(port, SCPCR) & ~SCPCR_RTSC); 1980 } 1981 1982 /* Enable Auto RTS */ 1983 serial_port_out(port, SCFCR, 1984 serial_port_in(port, SCFCR) | SCFCR_MCE); 1985 } else { 1986 /* Set RTS */ 1987 sci_set_rts(port, 1); 1988 } 1989 } 1990 1991 static unsigned int sci_get_mctrl(struct uart_port *port) 1992 { 1993 struct sci_port *s = to_sci_port(port); 1994 struct mctrl_gpios *gpios = s->gpios; 1995 unsigned int mctrl = 0; 1996 1997 mctrl_gpio_get(gpios, &mctrl); 1998 1999 /* 2000 * CTS/RTS is handled in hardware when supported, while nothing 2001 * else is wired up. 2002 */ 2003 if (s->autorts) { 2004 if (sci_get_cts(port)) 2005 mctrl |= TIOCM_CTS; 2006 } else if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS))) { 2007 mctrl |= TIOCM_CTS; 2008 } 2009 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR))) 2010 mctrl |= TIOCM_DSR; 2011 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD))) 2012 mctrl |= TIOCM_CAR; 2013 2014 return mctrl; 2015 } 2016 2017 static void sci_enable_ms(struct uart_port *port) 2018 { 2019 mctrl_gpio_enable_ms(to_sci_port(port)->gpios); 2020 } 2021 2022 static void sci_break_ctl(struct uart_port *port, int break_state) 2023 { 2024 unsigned short scscr, scsptr; 2025 unsigned long flags; 2026 2027 /* check wheter the port has SCSPTR */ 2028 if (!sci_getreg(port, SCSPTR)->size) { 2029 /* 2030 * Not supported by hardware. Most parts couple break and rx 2031 * interrupts together, with break detection always enabled. 2032 */ 2033 return; 2034 } 2035 2036 spin_lock_irqsave(&port->lock, flags); 2037 scsptr = serial_port_in(port, SCSPTR); 2038 scscr = serial_port_in(port, SCSCR); 2039 2040 if (break_state == -1) { 2041 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT; 2042 scscr &= ~SCSCR_TE; 2043 } else { 2044 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO; 2045 scscr |= SCSCR_TE; 2046 } 2047 2048 serial_port_out(port, SCSPTR, scsptr); 2049 serial_port_out(port, SCSCR, scscr); 2050 spin_unlock_irqrestore(&port->lock, flags); 2051 } 2052 2053 static int sci_startup(struct uart_port *port) 2054 { 2055 struct sci_port *s = to_sci_port(port); 2056 int ret; 2057 2058 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 2059 2060 sci_request_dma(port); 2061 2062 ret = sci_request_irq(s); 2063 if (unlikely(ret < 0)) { 2064 sci_free_dma(port); 2065 return ret; 2066 } 2067 2068 return 0; 2069 } 2070 2071 static void sci_shutdown(struct uart_port *port) 2072 { 2073 struct sci_port *s = to_sci_port(port); 2074 unsigned long flags; 2075 u16 scr; 2076 2077 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 2078 2079 s->autorts = false; 2080 mctrl_gpio_disable_ms(to_sci_port(port)->gpios); 2081 2082 spin_lock_irqsave(&port->lock, flags); 2083 sci_stop_rx(port); 2084 sci_stop_tx(port); 2085 /* 2086 * Stop RX and TX, disable related interrupts, keep clock source 2087 * and HSCIF TOT bits 2088 */ 2089 scr = serial_port_in(port, SCSCR); 2090 serial_port_out(port, SCSCR, scr & 2091 (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot)); 2092 spin_unlock_irqrestore(&port->lock, flags); 2093 2094 #ifdef CONFIG_SERIAL_SH_SCI_DMA 2095 if (s->chan_rx) { 2096 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__, 2097 port->line); 2098 hrtimer_cancel(&s->rx_timer); 2099 } 2100 #endif 2101 2102 sci_free_irq(s); 2103 sci_free_dma(port); 2104 } 2105 2106 static int sci_sck_calc(struct sci_port *s, unsigned int bps, 2107 unsigned int *srr) 2108 { 2109 unsigned long freq = s->clk_rates[SCI_SCK]; 2110 int err, min_err = INT_MAX; 2111 unsigned int sr; 2112 2113 if (s->port.type != PORT_HSCIF) 2114 freq *= 2; 2115 2116 for_each_sr(sr, s) { 2117 err = DIV_ROUND_CLOSEST(freq, sr) - bps; 2118 if (abs(err) >= abs(min_err)) 2119 continue; 2120 2121 min_err = err; 2122 *srr = sr - 1; 2123 2124 if (!err) 2125 break; 2126 } 2127 2128 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err, 2129 *srr + 1); 2130 return min_err; 2131 } 2132 2133 static int sci_brg_calc(struct sci_port *s, unsigned int bps, 2134 unsigned long freq, unsigned int *dlr, 2135 unsigned int *srr) 2136 { 2137 int err, min_err = INT_MAX; 2138 unsigned int sr, dl; 2139 2140 if (s->port.type != PORT_HSCIF) 2141 freq *= 2; 2142 2143 for_each_sr(sr, s) { 2144 dl = DIV_ROUND_CLOSEST(freq, sr * bps); 2145 dl = clamp(dl, 1U, 65535U); 2146 2147 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps; 2148 if (abs(err) >= abs(min_err)) 2149 continue; 2150 2151 min_err = err; 2152 *dlr = dl; 2153 *srr = sr - 1; 2154 2155 if (!err) 2156 break; 2157 } 2158 2159 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps, 2160 min_err, *dlr, *srr + 1); 2161 return min_err; 2162 } 2163 2164 /* calculate sample rate, BRR, and clock select */ 2165 static int sci_scbrr_calc(struct sci_port *s, unsigned int bps, 2166 unsigned int *brr, unsigned int *srr, 2167 unsigned int *cks) 2168 { 2169 unsigned long freq = s->clk_rates[SCI_FCK]; 2170 unsigned int sr, br, prediv, scrate, c; 2171 int err, min_err = INT_MAX; 2172 2173 if (s->port.type != PORT_HSCIF) 2174 freq *= 2; 2175 2176 /* 2177 * Find the combination of sample rate and clock select with the 2178 * smallest deviation from the desired baud rate. 2179 * Prefer high sample rates to maximise the receive margin. 2180 * 2181 * M: Receive margin (%) 2182 * N: Ratio of bit rate to clock (N = sampling rate) 2183 * D: Clock duty (D = 0 to 1.0) 2184 * L: Frame length (L = 9 to 12) 2185 * F: Absolute value of clock frequency deviation 2186 * 2187 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) - 2188 * (|D - 0.5| / N * (1 + F))| 2189 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation. 2190 */ 2191 for_each_sr(sr, s) { 2192 for (c = 0; c <= 3; c++) { 2193 /* integerized formulas from HSCIF documentation */ 2194 prediv = sr * (1 << (2 * c + 1)); 2195 2196 /* 2197 * We need to calculate: 2198 * 2199 * br = freq / (prediv * bps) clamped to [1..256] 2200 * err = freq / (br * prediv) - bps 2201 * 2202 * Watch out for overflow when calculating the desired 2203 * sampling clock rate! 2204 */ 2205 if (bps > UINT_MAX / prediv) 2206 break; 2207 2208 scrate = prediv * bps; 2209 br = DIV_ROUND_CLOSEST(freq, scrate); 2210 br = clamp(br, 1U, 256U); 2211 2212 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps; 2213 if (abs(err) >= abs(min_err)) 2214 continue; 2215 2216 min_err = err; 2217 *brr = br - 1; 2218 *srr = sr - 1; 2219 *cks = c; 2220 2221 if (!err) 2222 goto found; 2223 } 2224 } 2225 2226 found: 2227 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps, 2228 min_err, *brr, *srr + 1, *cks); 2229 return min_err; 2230 } 2231 2232 static void sci_reset(struct uart_port *port) 2233 { 2234 const struct plat_sci_reg *reg; 2235 unsigned int status; 2236 struct sci_port *s = to_sci_port(port); 2237 2238 serial_port_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */ 2239 2240 reg = sci_getreg(port, SCFCR); 2241 if (reg->size) 2242 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); 2243 2244 sci_clear_SCxSR(port, 2245 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) & 2246 SCxSR_BREAK_CLEAR(port)); 2247 if (sci_getreg(port, SCLSR)->size) { 2248 status = serial_port_in(port, SCLSR); 2249 status &= ~(SCLSR_TO | SCLSR_ORER); 2250 serial_port_out(port, SCLSR, status); 2251 } 2252 2253 if (s->rx_trigger > 1) { 2254 if (s->rx_fifo_timeout) { 2255 scif_set_rtrg(port, 1); 2256 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0); 2257 } else { 2258 if (port->type == PORT_SCIFA || 2259 port->type == PORT_SCIFB) 2260 scif_set_rtrg(port, 1); 2261 else 2262 scif_set_rtrg(port, s->rx_trigger); 2263 } 2264 } 2265 } 2266 2267 static void sci_set_termios(struct uart_port *port, struct ktermios *termios, 2268 struct ktermios *old) 2269 { 2270 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits; 2271 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0; 2272 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0; 2273 struct sci_port *s = to_sci_port(port); 2274 const struct plat_sci_reg *reg; 2275 int min_err = INT_MAX, err; 2276 unsigned long max_freq = 0; 2277 int best_clk = -1; 2278 unsigned long flags; 2279 2280 if ((termios->c_cflag & CSIZE) == CS7) 2281 smr_val |= SCSMR_CHR; 2282 if (termios->c_cflag & PARENB) 2283 smr_val |= SCSMR_PE; 2284 if (termios->c_cflag & PARODD) 2285 smr_val |= SCSMR_PE | SCSMR_ODD; 2286 if (termios->c_cflag & CSTOPB) 2287 smr_val |= SCSMR_STOP; 2288 2289 /* 2290 * earlyprintk comes here early on with port->uartclk set to zero. 2291 * the clock framework is not up and running at this point so here 2292 * we assume that 115200 is the maximum baud rate. please note that 2293 * the baud rate is not programmed during earlyprintk - it is assumed 2294 * that the previous boot loader has enabled required clocks and 2295 * setup the baud rate generator hardware for us already. 2296 */ 2297 if (!port->uartclk) { 2298 baud = uart_get_baud_rate(port, termios, old, 0, 115200); 2299 goto done; 2300 } 2301 2302 for (i = 0; i < SCI_NUM_CLKS; i++) 2303 max_freq = max(max_freq, s->clk_rates[i]); 2304 2305 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s)); 2306 if (!baud) 2307 goto done; 2308 2309 /* 2310 * There can be multiple sources for the sampling clock. Find the one 2311 * that gives us the smallest deviation from the desired baud rate. 2312 */ 2313 2314 /* Optional Undivided External Clock */ 2315 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA && 2316 port->type != PORT_SCIFB) { 2317 err = sci_sck_calc(s, baud, &srr1); 2318 if (abs(err) < abs(min_err)) { 2319 best_clk = SCI_SCK; 2320 scr_val = SCSCR_CKE1; 2321 sccks = SCCKS_CKS; 2322 min_err = err; 2323 srr = srr1; 2324 if (!err) 2325 goto done; 2326 } 2327 } 2328 2329 /* Optional BRG Frequency Divided External Clock */ 2330 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) { 2331 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1, 2332 &srr1); 2333 if (abs(err) < abs(min_err)) { 2334 best_clk = SCI_SCIF_CLK; 2335 scr_val = SCSCR_CKE1; 2336 sccks = 0; 2337 min_err = err; 2338 dl = dl1; 2339 srr = srr1; 2340 if (!err) 2341 goto done; 2342 } 2343 } 2344 2345 /* Optional BRG Frequency Divided Internal Clock */ 2346 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) { 2347 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1, 2348 &srr1); 2349 if (abs(err) < abs(min_err)) { 2350 best_clk = SCI_BRG_INT; 2351 scr_val = SCSCR_CKE1; 2352 sccks = SCCKS_XIN; 2353 min_err = err; 2354 dl = dl1; 2355 srr = srr1; 2356 if (!min_err) 2357 goto done; 2358 } 2359 } 2360 2361 /* Divided Functional Clock using standard Bit Rate Register */ 2362 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1); 2363 if (abs(err) < abs(min_err)) { 2364 best_clk = SCI_FCK; 2365 scr_val = 0; 2366 min_err = err; 2367 brr = brr1; 2368 srr = srr1; 2369 cks = cks1; 2370 } 2371 2372 done: 2373 if (best_clk >= 0) 2374 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n", 2375 s->clks[best_clk], baud, min_err); 2376 2377 sci_port_enable(s); 2378 2379 /* 2380 * Program the optional External Baud Rate Generator (BRG) first. 2381 * It controls the mux to select (H)SCK or frequency divided clock. 2382 */ 2383 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) { 2384 serial_port_out(port, SCDL, dl); 2385 serial_port_out(port, SCCKS, sccks); 2386 } 2387 2388 spin_lock_irqsave(&port->lock, flags); 2389 2390 sci_reset(port); 2391 2392 uart_update_timeout(port, termios->c_cflag, baud); 2393 2394 /* byte size and parity */ 2395 switch (termios->c_cflag & CSIZE) { 2396 case CS5: 2397 bits = 7; 2398 break; 2399 case CS6: 2400 bits = 8; 2401 break; 2402 case CS7: 2403 bits = 9; 2404 break; 2405 default: 2406 bits = 10; 2407 break; 2408 } 2409 2410 if (termios->c_cflag & CSTOPB) 2411 bits++; 2412 if (termios->c_cflag & PARENB) 2413 bits++; 2414 2415 if (best_clk >= 0) { 2416 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 2417 switch (srr + 1) { 2418 case 5: smr_val |= SCSMR_SRC_5; break; 2419 case 7: smr_val |= SCSMR_SRC_7; break; 2420 case 11: smr_val |= SCSMR_SRC_11; break; 2421 case 13: smr_val |= SCSMR_SRC_13; break; 2422 case 16: smr_val |= SCSMR_SRC_16; break; 2423 case 17: smr_val |= SCSMR_SRC_17; break; 2424 case 19: smr_val |= SCSMR_SRC_19; break; 2425 case 27: smr_val |= SCSMR_SRC_27; break; 2426 } 2427 smr_val |= cks; 2428 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); 2429 serial_port_out(port, SCSMR, smr_val); 2430 serial_port_out(port, SCBRR, brr); 2431 if (sci_getreg(port, HSSRR)->size) { 2432 unsigned int hssrr = srr | HSCIF_SRE; 2433 /* Calculate deviation from intended rate at the 2434 * center of the last stop bit in sampling clocks. 2435 */ 2436 int last_stop = bits * 2 - 1; 2437 int deviation = min_err * srr * last_stop / 2 / baud; 2438 2439 if (abs(deviation) >= 2) { 2440 /* At least two sampling clocks off at the 2441 * last stop bit; we can increase the error 2442 * margin by shifting the sampling point. 2443 */ 2444 int shift = min(-8, max(7, deviation / 2)); 2445 2446 hssrr |= (shift << HSCIF_SRHP_SHIFT) & 2447 HSCIF_SRHP_MASK; 2448 hssrr |= HSCIF_SRDE; 2449 } 2450 serial_port_out(port, HSSRR, hssrr); 2451 } 2452 2453 /* Wait one bit interval */ 2454 udelay((1000000 + (baud - 1)) / baud); 2455 } else { 2456 /* Don't touch the bit rate configuration */ 2457 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0); 2458 smr_val |= serial_port_in(port, SCSMR) & 2459 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS); 2460 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); 2461 serial_port_out(port, SCSMR, smr_val); 2462 } 2463 2464 sci_init_pins(port, termios->c_cflag); 2465 2466 port->status &= ~UPSTAT_AUTOCTS; 2467 s->autorts = false; 2468 reg = sci_getreg(port, SCFCR); 2469 if (reg->size) { 2470 unsigned short ctrl = serial_port_in(port, SCFCR); 2471 2472 if ((port->flags & UPF_HARD_FLOW) && 2473 (termios->c_cflag & CRTSCTS)) { 2474 /* There is no CTS interrupt to restart the hardware */ 2475 port->status |= UPSTAT_AUTOCTS; 2476 /* MCE is enabled when RTS is raised */ 2477 s->autorts = true; 2478 } 2479 2480 /* 2481 * As we've done a sci_reset() above, ensure we don't 2482 * interfere with the FIFOs while toggling MCE. As the 2483 * reset values could still be set, simply mask them out. 2484 */ 2485 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST); 2486 2487 serial_port_out(port, SCFCR, ctrl); 2488 } 2489 if (port->flags & UPF_HARD_FLOW) { 2490 /* Refresh (Auto) RTS */ 2491 sci_set_mctrl(port, port->mctrl); 2492 } 2493 2494 scr_val |= SCSCR_RE | SCSCR_TE | 2495 (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)); 2496 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); 2497 if ((srr + 1 == 5) && 2498 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) { 2499 /* 2500 * In asynchronous mode, when the sampling rate is 1/5, first 2501 * received data may become invalid on some SCIFA and SCIFB. 2502 * To avoid this problem wait more than 1 serial data time (1 2503 * bit time x serial data number) after setting SCSCR.RE = 1. 2504 */ 2505 udelay(DIV_ROUND_UP(10 * 1000000, baud)); 2506 } 2507 2508 /* 2509 * Calculate delay for 2 DMA buffers (4 FIFO). 2510 * See serial_core.c::uart_update_timeout(). 2511 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above 2512 * function calculates 1 jiffie for the data plus 5 jiffies for the 2513 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA 2514 * buffers (4 FIFO sizes), but when performing a faster transfer, the 2515 * value obtained by this formula is too small. Therefore, if the value 2516 * is smaller than 20ms, use 20ms as the timeout value for DMA. 2517 */ 2518 s->rx_frame = (10000 * bits) / (baud / 100); 2519 #ifdef CONFIG_SERIAL_SH_SCI_DMA 2520 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame; 2521 if (s->rx_timeout < 20) 2522 s->rx_timeout = 20; 2523 #endif 2524 2525 if ((termios->c_cflag & CREAD) != 0) 2526 sci_start_rx(port); 2527 2528 spin_unlock_irqrestore(&port->lock, flags); 2529 2530 sci_port_disable(s); 2531 2532 if (UART_ENABLE_MS(port, termios->c_cflag)) 2533 sci_enable_ms(port); 2534 } 2535 2536 static void sci_pm(struct uart_port *port, unsigned int state, 2537 unsigned int oldstate) 2538 { 2539 struct sci_port *sci_port = to_sci_port(port); 2540 2541 switch (state) { 2542 case UART_PM_STATE_OFF: 2543 sci_port_disable(sci_port); 2544 break; 2545 default: 2546 sci_port_enable(sci_port); 2547 break; 2548 } 2549 } 2550 2551 static const char *sci_type(struct uart_port *port) 2552 { 2553 switch (port->type) { 2554 case PORT_IRDA: 2555 return "irda"; 2556 case PORT_SCI: 2557 return "sci"; 2558 case PORT_SCIF: 2559 return "scif"; 2560 case PORT_SCIFA: 2561 return "scifa"; 2562 case PORT_SCIFB: 2563 return "scifb"; 2564 case PORT_HSCIF: 2565 return "hscif"; 2566 } 2567 2568 return NULL; 2569 } 2570 2571 static int sci_remap_port(struct uart_port *port) 2572 { 2573 struct sci_port *sport = to_sci_port(port); 2574 2575 /* 2576 * Nothing to do if there's already an established membase. 2577 */ 2578 if (port->membase) 2579 return 0; 2580 2581 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { 2582 port->membase = ioremap_nocache(port->mapbase, sport->reg_size); 2583 if (unlikely(!port->membase)) { 2584 dev_err(port->dev, "can't remap port#%d\n", port->line); 2585 return -ENXIO; 2586 } 2587 } else { 2588 /* 2589 * For the simple (and majority of) cases where we don't 2590 * need to do any remapping, just cast the cookie 2591 * directly. 2592 */ 2593 port->membase = (void __iomem *)(uintptr_t)port->mapbase; 2594 } 2595 2596 return 0; 2597 } 2598 2599 static void sci_release_port(struct uart_port *port) 2600 { 2601 struct sci_port *sport = to_sci_port(port); 2602 2603 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { 2604 iounmap(port->membase); 2605 port->membase = NULL; 2606 } 2607 2608 release_mem_region(port->mapbase, sport->reg_size); 2609 } 2610 2611 static int sci_request_port(struct uart_port *port) 2612 { 2613 struct resource *res; 2614 struct sci_port *sport = to_sci_port(port); 2615 int ret; 2616 2617 res = request_mem_region(port->mapbase, sport->reg_size, 2618 dev_name(port->dev)); 2619 if (unlikely(res == NULL)) { 2620 dev_err(port->dev, "request_mem_region failed."); 2621 return -EBUSY; 2622 } 2623 2624 ret = sci_remap_port(port); 2625 if (unlikely(ret != 0)) { 2626 release_resource(res); 2627 return ret; 2628 } 2629 2630 return 0; 2631 } 2632 2633 static void sci_config_port(struct uart_port *port, int flags) 2634 { 2635 if (flags & UART_CONFIG_TYPE) { 2636 struct sci_port *sport = to_sci_port(port); 2637 2638 port->type = sport->cfg->type; 2639 sci_request_port(port); 2640 } 2641 } 2642 2643 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser) 2644 { 2645 if (ser->baud_base < 2400) 2646 /* No paper tape reader for Mitch.. */ 2647 return -EINVAL; 2648 2649 return 0; 2650 } 2651 2652 static const struct uart_ops sci_uart_ops = { 2653 .tx_empty = sci_tx_empty, 2654 .set_mctrl = sci_set_mctrl, 2655 .get_mctrl = sci_get_mctrl, 2656 .start_tx = sci_start_tx, 2657 .stop_tx = sci_stop_tx, 2658 .stop_rx = sci_stop_rx, 2659 .enable_ms = sci_enable_ms, 2660 .break_ctl = sci_break_ctl, 2661 .startup = sci_startup, 2662 .shutdown = sci_shutdown, 2663 .flush_buffer = sci_flush_buffer, 2664 .set_termios = sci_set_termios, 2665 .pm = sci_pm, 2666 .type = sci_type, 2667 .release_port = sci_release_port, 2668 .request_port = sci_request_port, 2669 .config_port = sci_config_port, 2670 .verify_port = sci_verify_port, 2671 #ifdef CONFIG_CONSOLE_POLL 2672 .poll_get_char = sci_poll_get_char, 2673 .poll_put_char = sci_poll_put_char, 2674 #endif 2675 }; 2676 2677 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev) 2678 { 2679 const char *clk_names[] = { 2680 [SCI_FCK] = "fck", 2681 [SCI_SCK] = "sck", 2682 [SCI_BRG_INT] = "brg_int", 2683 [SCI_SCIF_CLK] = "scif_clk", 2684 }; 2685 struct clk *clk; 2686 unsigned int i; 2687 2688 if (sci_port->cfg->type == PORT_HSCIF) 2689 clk_names[SCI_SCK] = "hsck"; 2690 2691 for (i = 0; i < SCI_NUM_CLKS; i++) { 2692 clk = devm_clk_get(dev, clk_names[i]); 2693 if (PTR_ERR(clk) == -EPROBE_DEFER) 2694 return -EPROBE_DEFER; 2695 2696 if (IS_ERR(clk) && i == SCI_FCK) { 2697 /* 2698 * "fck" used to be called "sci_ick", and we need to 2699 * maintain DT backward compatibility. 2700 */ 2701 clk = devm_clk_get(dev, "sci_ick"); 2702 if (PTR_ERR(clk) == -EPROBE_DEFER) 2703 return -EPROBE_DEFER; 2704 2705 if (!IS_ERR(clk)) 2706 goto found; 2707 2708 /* 2709 * Not all SH platforms declare a clock lookup entry 2710 * for SCI devices, in which case we need to get the 2711 * global "peripheral_clk" clock. 2712 */ 2713 clk = devm_clk_get(dev, "peripheral_clk"); 2714 if (!IS_ERR(clk)) 2715 goto found; 2716 2717 dev_err(dev, "failed to get %s (%ld)\n", clk_names[i], 2718 PTR_ERR(clk)); 2719 return PTR_ERR(clk); 2720 } 2721 2722 found: 2723 if (IS_ERR(clk)) 2724 dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i], 2725 PTR_ERR(clk)); 2726 else 2727 dev_dbg(dev, "clk %s is %pC rate %lu\n", clk_names[i], 2728 clk, clk_get_rate(clk)); 2729 sci_port->clks[i] = IS_ERR(clk) ? NULL : clk; 2730 } 2731 return 0; 2732 } 2733 2734 static const struct sci_port_params * 2735 sci_probe_regmap(const struct plat_sci_port *cfg) 2736 { 2737 unsigned int regtype; 2738 2739 if (cfg->regtype != SCIx_PROBE_REGTYPE) 2740 return &sci_port_params[cfg->regtype]; 2741 2742 switch (cfg->type) { 2743 case PORT_SCI: 2744 regtype = SCIx_SCI_REGTYPE; 2745 break; 2746 case PORT_IRDA: 2747 regtype = SCIx_IRDA_REGTYPE; 2748 break; 2749 case PORT_SCIFA: 2750 regtype = SCIx_SCIFA_REGTYPE; 2751 break; 2752 case PORT_SCIFB: 2753 regtype = SCIx_SCIFB_REGTYPE; 2754 break; 2755 case PORT_SCIF: 2756 /* 2757 * The SH-4 is a bit of a misnomer here, although that's 2758 * where this particular port layout originated. This 2759 * configuration (or some slight variation thereof) 2760 * remains the dominant model for all SCIFs. 2761 */ 2762 regtype = SCIx_SH4_SCIF_REGTYPE; 2763 break; 2764 case PORT_HSCIF: 2765 regtype = SCIx_HSCIF_REGTYPE; 2766 break; 2767 default: 2768 pr_err("Can't probe register map for given port\n"); 2769 return NULL; 2770 } 2771 2772 return &sci_port_params[regtype]; 2773 } 2774 2775 static int sci_init_single(struct platform_device *dev, 2776 struct sci_port *sci_port, unsigned int index, 2777 const struct plat_sci_port *p, bool early) 2778 { 2779 struct uart_port *port = &sci_port->port; 2780 const struct resource *res; 2781 unsigned int i; 2782 int ret; 2783 2784 sci_port->cfg = p; 2785 2786 port->ops = &sci_uart_ops; 2787 port->iotype = UPIO_MEM; 2788 port->line = index; 2789 2790 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 2791 if (res == NULL) 2792 return -ENOMEM; 2793 2794 port->mapbase = res->start; 2795 sci_port->reg_size = resource_size(res); 2796 2797 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) 2798 sci_port->irqs[i] = platform_get_irq(dev, i); 2799 2800 /* The SCI generates several interrupts. They can be muxed together or 2801 * connected to different interrupt lines. In the muxed case only one 2802 * interrupt resource is specified. In the non-muxed case three or four 2803 * interrupt resources are specified, as the BRI interrupt is optional. 2804 */ 2805 if (sci_port->irqs[0] < 0) 2806 return -ENXIO; 2807 2808 if (sci_port->irqs[1] < 0) { 2809 sci_port->irqs[1] = sci_port->irqs[0]; 2810 sci_port->irqs[2] = sci_port->irqs[0]; 2811 sci_port->irqs[3] = sci_port->irqs[0]; 2812 } 2813 2814 sci_port->params = sci_probe_regmap(p); 2815 if (unlikely(sci_port->params == NULL)) 2816 return -EINVAL; 2817 2818 switch (p->type) { 2819 case PORT_SCIFB: 2820 sci_port->rx_trigger = 48; 2821 break; 2822 case PORT_HSCIF: 2823 sci_port->rx_trigger = 64; 2824 break; 2825 case PORT_SCIFA: 2826 sci_port->rx_trigger = 32; 2827 break; 2828 case PORT_SCIF: 2829 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) 2830 /* RX triggering not implemented for this IP */ 2831 sci_port->rx_trigger = 1; 2832 else 2833 sci_port->rx_trigger = 8; 2834 break; 2835 default: 2836 sci_port->rx_trigger = 1; 2837 break; 2838 } 2839 2840 sci_port->rx_fifo_timeout = 0; 2841 sci_port->hscif_tot = 0; 2842 2843 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't 2844 * match the SoC datasheet, this should be investigated. Let platform 2845 * data override the sampling rate for now. 2846 */ 2847 sci_port->sampling_rate_mask = p->sampling_rate 2848 ? SCI_SR(p->sampling_rate) 2849 : sci_port->params->sampling_rate_mask; 2850 2851 if (!early) { 2852 ret = sci_init_clocks(sci_port, &dev->dev); 2853 if (ret < 0) 2854 return ret; 2855 2856 port->dev = &dev->dev; 2857 2858 pm_runtime_enable(&dev->dev); 2859 } 2860 2861 port->type = p->type; 2862 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags; 2863 port->fifosize = sci_port->params->fifosize; 2864 2865 if (port->type == PORT_SCI) { 2866 if (sci_port->reg_size >= 0x20) 2867 port->regshift = 2; 2868 else 2869 port->regshift = 1; 2870 } 2871 2872 /* 2873 * The UART port needs an IRQ value, so we peg this to the RX IRQ 2874 * for the multi-IRQ ports, which is where we are primarily 2875 * concerned with the shutdown path synchronization. 2876 * 2877 * For the muxed case there's nothing more to do. 2878 */ 2879 port->irq = sci_port->irqs[SCIx_RXI_IRQ]; 2880 port->irqflags = 0; 2881 2882 port->serial_in = sci_serial_in; 2883 port->serial_out = sci_serial_out; 2884 2885 return 0; 2886 } 2887 2888 static void sci_cleanup_single(struct sci_port *port) 2889 { 2890 pm_runtime_disable(port->port.dev); 2891 } 2892 2893 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ 2894 defined(CONFIG_SERIAL_SH_SCI_EARLYCON) 2895 static void serial_console_putchar(struct uart_port *port, int ch) 2896 { 2897 sci_poll_put_char(port, ch); 2898 } 2899 2900 /* 2901 * Print a string to the serial port trying not to disturb 2902 * any possible real use of the port... 2903 */ 2904 static void serial_console_write(struct console *co, const char *s, 2905 unsigned count) 2906 { 2907 struct sci_port *sci_port = &sci_ports[co->index]; 2908 struct uart_port *port = &sci_port->port; 2909 unsigned short bits, ctrl, ctrl_temp; 2910 unsigned long flags; 2911 int locked = 1; 2912 2913 #if defined(SUPPORT_SYSRQ) 2914 if (port->sysrq) 2915 locked = 0; 2916 else 2917 #endif 2918 if (oops_in_progress) 2919 locked = spin_trylock_irqsave(&port->lock, flags); 2920 else 2921 spin_lock_irqsave(&port->lock, flags); 2922 2923 /* first save SCSCR then disable interrupts, keep clock source */ 2924 ctrl = serial_port_in(port, SCSCR); 2925 ctrl_temp = SCSCR_RE | SCSCR_TE | 2926 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) | 2927 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0)); 2928 serial_port_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot); 2929 2930 uart_console_write(port, s, count, serial_console_putchar); 2931 2932 /* wait until fifo is empty and last bit has been transmitted */ 2933 bits = SCxSR_TDxE(port) | SCxSR_TEND(port); 2934 while ((serial_port_in(port, SCxSR) & bits) != bits) 2935 cpu_relax(); 2936 2937 /* restore the SCSCR */ 2938 serial_port_out(port, SCSCR, ctrl); 2939 2940 if (locked) 2941 spin_unlock_irqrestore(&port->lock, flags); 2942 } 2943 2944 static int serial_console_setup(struct console *co, char *options) 2945 { 2946 struct sci_port *sci_port; 2947 struct uart_port *port; 2948 int baud = 115200; 2949 int bits = 8; 2950 int parity = 'n'; 2951 int flow = 'n'; 2952 int ret; 2953 2954 /* 2955 * Refuse to handle any bogus ports. 2956 */ 2957 if (co->index < 0 || co->index >= SCI_NPORTS) 2958 return -ENODEV; 2959 2960 sci_port = &sci_ports[co->index]; 2961 port = &sci_port->port; 2962 2963 /* 2964 * Refuse to handle uninitialized ports. 2965 */ 2966 if (!port->ops) 2967 return -ENODEV; 2968 2969 ret = sci_remap_port(port); 2970 if (unlikely(ret != 0)) 2971 return ret; 2972 2973 if (options) 2974 uart_parse_options(options, &baud, &parity, &bits, &flow); 2975 2976 return uart_set_options(port, co, baud, parity, bits, flow); 2977 } 2978 2979 static struct console serial_console = { 2980 .name = "ttySC", 2981 .device = uart_console_device, 2982 .write = serial_console_write, 2983 .setup = serial_console_setup, 2984 .flags = CON_PRINTBUFFER, 2985 .index = -1, 2986 .data = &sci_uart_driver, 2987 }; 2988 2989 static struct console early_serial_console = { 2990 .name = "early_ttySC", 2991 .write = serial_console_write, 2992 .flags = CON_PRINTBUFFER, 2993 .index = -1, 2994 }; 2995 2996 static char early_serial_buf[32]; 2997 2998 static int sci_probe_earlyprintk(struct platform_device *pdev) 2999 { 3000 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev); 3001 3002 if (early_serial_console.data) 3003 return -EEXIST; 3004 3005 early_serial_console.index = pdev->id; 3006 3007 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true); 3008 3009 serial_console_setup(&early_serial_console, early_serial_buf); 3010 3011 if (!strstr(early_serial_buf, "keep")) 3012 early_serial_console.flags |= CON_BOOT; 3013 3014 register_console(&early_serial_console); 3015 return 0; 3016 } 3017 3018 #define SCI_CONSOLE (&serial_console) 3019 3020 #else 3021 static inline int sci_probe_earlyprintk(struct platform_device *pdev) 3022 { 3023 return -EINVAL; 3024 } 3025 3026 #define SCI_CONSOLE NULL 3027 3028 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */ 3029 3030 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized"; 3031 3032 static DEFINE_MUTEX(sci_uart_registration_lock); 3033 static struct uart_driver sci_uart_driver = { 3034 .owner = THIS_MODULE, 3035 .driver_name = "sci", 3036 .dev_name = "ttySC", 3037 .major = SCI_MAJOR, 3038 .minor = SCI_MINOR_START, 3039 .nr = SCI_NPORTS, 3040 .cons = SCI_CONSOLE, 3041 }; 3042 3043 static int sci_remove(struct platform_device *dev) 3044 { 3045 struct sci_port *port = platform_get_drvdata(dev); 3046 3047 sci_ports_in_use &= ~BIT(port->port.line); 3048 uart_remove_one_port(&sci_uart_driver, &port->port); 3049 3050 sci_cleanup_single(port); 3051 3052 if (port->port.fifosize > 1) { 3053 sysfs_remove_file(&dev->dev.kobj, 3054 &dev_attr_rx_fifo_trigger.attr); 3055 } 3056 if (port->port.type == PORT_SCIFA || port->port.type == PORT_SCIFB || 3057 port->port.type == PORT_HSCIF) { 3058 sysfs_remove_file(&dev->dev.kobj, 3059 &dev_attr_rx_fifo_timeout.attr); 3060 } 3061 3062 return 0; 3063 } 3064 3065 3066 #define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype)) 3067 #define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16) 3068 #define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff) 3069 3070 static const struct of_device_id of_sci_match[] = { 3071 /* SoC-specific types */ 3072 { 3073 .compatible = "renesas,scif-r7s72100", 3074 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE), 3075 }, 3076 /* Family-specific types */ 3077 { 3078 .compatible = "renesas,rcar-gen1-scif", 3079 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3080 }, { 3081 .compatible = "renesas,rcar-gen2-scif", 3082 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3083 }, { 3084 .compatible = "renesas,rcar-gen3-scif", 3085 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3086 }, 3087 /* Generic types */ 3088 { 3089 .compatible = "renesas,scif", 3090 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE), 3091 }, { 3092 .compatible = "renesas,scifa", 3093 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE), 3094 }, { 3095 .compatible = "renesas,scifb", 3096 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE), 3097 }, { 3098 .compatible = "renesas,hscif", 3099 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE), 3100 }, { 3101 .compatible = "renesas,sci", 3102 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE), 3103 }, { 3104 /* Terminator */ 3105 }, 3106 }; 3107 MODULE_DEVICE_TABLE(of, of_sci_match); 3108 3109 static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev, 3110 unsigned int *dev_id) 3111 { 3112 struct device_node *np = pdev->dev.of_node; 3113 struct plat_sci_port *p; 3114 struct sci_port *sp; 3115 const void *data; 3116 int id; 3117 3118 if (!IS_ENABLED(CONFIG_OF) || !np) 3119 return NULL; 3120 3121 data = of_device_get_match_data(&pdev->dev); 3122 3123 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL); 3124 if (!p) 3125 return NULL; 3126 3127 /* Get the line number from the aliases node. */ 3128 id = of_alias_get_id(np, "serial"); 3129 if (id < 0 && ~sci_ports_in_use) 3130 id = ffz(sci_ports_in_use); 3131 if (id < 0) { 3132 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id); 3133 return NULL; 3134 } 3135 if (id >= ARRAY_SIZE(sci_ports)) { 3136 dev_err(&pdev->dev, "serial%d out of range\n", id); 3137 return NULL; 3138 } 3139 3140 sp = &sci_ports[id]; 3141 *dev_id = id; 3142 3143 p->type = SCI_OF_TYPE(data); 3144 p->regtype = SCI_OF_REGTYPE(data); 3145 3146 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts"); 3147 3148 return p; 3149 } 3150 3151 static int sci_probe_single(struct platform_device *dev, 3152 unsigned int index, 3153 struct plat_sci_port *p, 3154 struct sci_port *sciport) 3155 { 3156 int ret; 3157 3158 /* Sanity check */ 3159 if (unlikely(index >= SCI_NPORTS)) { 3160 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n", 3161 index+1, SCI_NPORTS); 3162 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n"); 3163 return -EINVAL; 3164 } 3165 BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8); 3166 if (sci_ports_in_use & BIT(index)) 3167 return -EBUSY; 3168 3169 mutex_lock(&sci_uart_registration_lock); 3170 if (!sci_uart_driver.state) { 3171 ret = uart_register_driver(&sci_uart_driver); 3172 if (ret) { 3173 mutex_unlock(&sci_uart_registration_lock); 3174 return ret; 3175 } 3176 } 3177 mutex_unlock(&sci_uart_registration_lock); 3178 3179 ret = sci_init_single(dev, sciport, index, p, false); 3180 if (ret) 3181 return ret; 3182 3183 sciport->gpios = mctrl_gpio_init(&sciport->port, 0); 3184 if (IS_ERR(sciport->gpios) && PTR_ERR(sciport->gpios) != -ENOSYS) 3185 return PTR_ERR(sciport->gpios); 3186 3187 if (sciport->has_rtscts) { 3188 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios, 3189 UART_GPIO_CTS)) || 3190 !IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios, 3191 UART_GPIO_RTS))) { 3192 dev_err(&dev->dev, "Conflicting RTS/CTS config\n"); 3193 return -EINVAL; 3194 } 3195 sciport->port.flags |= UPF_HARD_FLOW; 3196 } 3197 3198 ret = uart_add_one_port(&sci_uart_driver, &sciport->port); 3199 if (ret) { 3200 sci_cleanup_single(sciport); 3201 return ret; 3202 } 3203 3204 return 0; 3205 } 3206 3207 static int sci_probe(struct platform_device *dev) 3208 { 3209 struct plat_sci_port *p; 3210 struct sci_port *sp; 3211 unsigned int dev_id; 3212 int ret; 3213 3214 /* 3215 * If we've come here via earlyprintk initialization, head off to 3216 * the special early probe. We don't have sufficient device state 3217 * to make it beyond this yet. 3218 */ 3219 if (is_early_platform_device(dev)) 3220 return sci_probe_earlyprintk(dev); 3221 3222 if (dev->dev.of_node) { 3223 p = sci_parse_dt(dev, &dev_id); 3224 if (p == NULL) 3225 return -EINVAL; 3226 } else { 3227 p = dev->dev.platform_data; 3228 if (p == NULL) { 3229 dev_err(&dev->dev, "no platform data supplied\n"); 3230 return -EINVAL; 3231 } 3232 3233 dev_id = dev->id; 3234 } 3235 3236 sp = &sci_ports[dev_id]; 3237 platform_set_drvdata(dev, sp); 3238 3239 ret = sci_probe_single(dev, dev_id, p, sp); 3240 if (ret) 3241 return ret; 3242 3243 if (sp->port.fifosize > 1) { 3244 ret = sysfs_create_file(&dev->dev.kobj, 3245 &dev_attr_rx_fifo_trigger.attr); 3246 if (ret) 3247 return ret; 3248 } 3249 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB || 3250 sp->port.type == PORT_HSCIF) { 3251 ret = sysfs_create_file(&dev->dev.kobj, 3252 &dev_attr_rx_fifo_timeout.attr); 3253 if (ret) { 3254 if (sp->port.fifosize > 1) { 3255 sysfs_remove_file(&dev->dev.kobj, 3256 &dev_attr_rx_fifo_trigger.attr); 3257 } 3258 return ret; 3259 } 3260 } 3261 3262 #ifdef CONFIG_SH_STANDARD_BIOS 3263 sh_bios_gdb_detach(); 3264 #endif 3265 3266 sci_ports_in_use |= BIT(dev_id); 3267 return 0; 3268 } 3269 3270 static __maybe_unused int sci_suspend(struct device *dev) 3271 { 3272 struct sci_port *sport = dev_get_drvdata(dev); 3273 3274 if (sport) 3275 uart_suspend_port(&sci_uart_driver, &sport->port); 3276 3277 return 0; 3278 } 3279 3280 static __maybe_unused int sci_resume(struct device *dev) 3281 { 3282 struct sci_port *sport = dev_get_drvdata(dev); 3283 3284 if (sport) 3285 uart_resume_port(&sci_uart_driver, &sport->port); 3286 3287 return 0; 3288 } 3289 3290 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume); 3291 3292 static struct platform_driver sci_driver = { 3293 .probe = sci_probe, 3294 .remove = sci_remove, 3295 .driver = { 3296 .name = "sh-sci", 3297 .pm = &sci_dev_pm_ops, 3298 .of_match_table = of_match_ptr(of_sci_match), 3299 }, 3300 }; 3301 3302 static int __init sci_init(void) 3303 { 3304 pr_info("%s\n", banner); 3305 3306 return platform_driver_register(&sci_driver); 3307 } 3308 3309 static void __exit sci_exit(void) 3310 { 3311 platform_driver_unregister(&sci_driver); 3312 3313 if (sci_uart_driver.state) 3314 uart_unregister_driver(&sci_uart_driver); 3315 } 3316 3317 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE 3318 early_platform_init_buffer("earlyprintk", &sci_driver, 3319 early_serial_buf, ARRAY_SIZE(early_serial_buf)); 3320 #endif 3321 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON 3322 static struct plat_sci_port port_cfg __initdata; 3323 3324 static int __init early_console_setup(struct earlycon_device *device, 3325 int type) 3326 { 3327 if (!device->port.membase) 3328 return -ENODEV; 3329 3330 device->port.serial_in = sci_serial_in; 3331 device->port.serial_out = sci_serial_out; 3332 device->port.type = type; 3333 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port)); 3334 port_cfg.type = type; 3335 sci_ports[0].cfg = &port_cfg; 3336 sci_ports[0].params = sci_probe_regmap(&port_cfg); 3337 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR); 3338 sci_serial_out(&sci_ports[0].port, SCSCR, 3339 SCSCR_RE | SCSCR_TE | port_cfg.scscr); 3340 3341 device->con->write = serial_console_write; 3342 return 0; 3343 } 3344 static int __init sci_early_console_setup(struct earlycon_device *device, 3345 const char *opt) 3346 { 3347 return early_console_setup(device, PORT_SCI); 3348 } 3349 static int __init scif_early_console_setup(struct earlycon_device *device, 3350 const char *opt) 3351 { 3352 return early_console_setup(device, PORT_SCIF); 3353 } 3354 static int __init scifa_early_console_setup(struct earlycon_device *device, 3355 const char *opt) 3356 { 3357 return early_console_setup(device, PORT_SCIFA); 3358 } 3359 static int __init scifb_early_console_setup(struct earlycon_device *device, 3360 const char *opt) 3361 { 3362 return early_console_setup(device, PORT_SCIFB); 3363 } 3364 static int __init hscif_early_console_setup(struct earlycon_device *device, 3365 const char *opt) 3366 { 3367 return early_console_setup(device, PORT_HSCIF); 3368 } 3369 3370 OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup); 3371 OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup); 3372 OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup); 3373 OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup); 3374 OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup); 3375 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */ 3376 3377 module_init(sci_init); 3378 module_exit(sci_exit); 3379 3380 MODULE_LICENSE("GPL"); 3381 MODULE_ALIAS("platform:sh-sci"); 3382 MODULE_AUTHOR("Paul Mundt"); 3383 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver"); 3384