1 /* 2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) 3 * 4 * Copyright (C) 2002 - 2011 Paul Mundt 5 * Copyright (C) 2015 Glider bvba 6 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007). 7 * 8 * based off of the old drivers/char/sh-sci.c by: 9 * 10 * Copyright (C) 1999, 2000 Niibe Yutaka 11 * Copyright (C) 2000 Sugioka Toshinobu 12 * Modified to support multiple serial ports. Stuart Menefy (May 2000). 13 * Modified to support SecureEdge. David McCullough (2002) 14 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003). 15 * Removed SH7300 support (Jul 2007). 16 * 17 * This file is subject to the terms and conditions of the GNU General Public 18 * License. See the file "COPYING" in the main directory of this archive 19 * for more details. 20 */ 21 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 22 #define SUPPORT_SYSRQ 23 #endif 24 25 #undef DEBUG 26 27 #include <linux/clk.h> 28 #include <linux/console.h> 29 #include <linux/ctype.h> 30 #include <linux/cpufreq.h> 31 #include <linux/delay.h> 32 #include <linux/dmaengine.h> 33 #include <linux/dma-mapping.h> 34 #include <linux/err.h> 35 #include <linux/errno.h> 36 #include <linux/init.h> 37 #include <linux/interrupt.h> 38 #include <linux/ioport.h> 39 #include <linux/major.h> 40 #include <linux/module.h> 41 #include <linux/mm.h> 42 #include <linux/of.h> 43 #include <linux/platform_device.h> 44 #include <linux/pm_runtime.h> 45 #include <linux/scatterlist.h> 46 #include <linux/serial.h> 47 #include <linux/serial_sci.h> 48 #include <linux/sh_dma.h> 49 #include <linux/slab.h> 50 #include <linux/string.h> 51 #include <linux/sysrq.h> 52 #include <linux/timer.h> 53 #include <linux/tty.h> 54 #include <linux/tty_flip.h> 55 56 #ifdef CONFIG_SUPERH 57 #include <asm/sh_bios.h> 58 #endif 59 60 #include "serial_mctrl_gpio.h" 61 #include "sh-sci.h" 62 63 /* Offsets into the sci_port->irqs array */ 64 enum { 65 SCIx_ERI_IRQ, 66 SCIx_RXI_IRQ, 67 SCIx_TXI_IRQ, 68 SCIx_BRI_IRQ, 69 SCIx_NR_IRQS, 70 71 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */ 72 }; 73 74 #define SCIx_IRQ_IS_MUXED(port) \ 75 ((port)->irqs[SCIx_ERI_IRQ] == \ 76 (port)->irqs[SCIx_RXI_IRQ]) || \ 77 ((port)->irqs[SCIx_ERI_IRQ] && \ 78 ((port)->irqs[SCIx_RXI_IRQ] < 0)) 79 80 enum SCI_CLKS { 81 SCI_FCK, /* Functional Clock */ 82 SCI_SCK, /* Optional External Clock */ 83 SCI_BRG_INT, /* Optional BRG Internal Clock Source */ 84 SCI_SCIF_CLK, /* Optional BRG External Clock Source */ 85 SCI_NUM_CLKS 86 }; 87 88 /* Bit x set means sampling rate x + 1 is supported */ 89 #define SCI_SR(x) BIT((x) - 1) 90 #define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1) 91 92 #define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \ 93 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \ 94 SCI_SR(19) | SCI_SR(27) 95 96 #define min_sr(_port) ffs((_port)->sampling_rate_mask) 97 #define max_sr(_port) fls((_port)->sampling_rate_mask) 98 99 /* Iterate over all supported sampling rates, from high to low */ 100 #define for_each_sr(_sr, _port) \ 101 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \ 102 if ((_port)->sampling_rate_mask & SCI_SR((_sr))) 103 104 struct plat_sci_reg { 105 u8 offset, size; 106 }; 107 108 struct sci_port_params { 109 const struct plat_sci_reg regs[SCIx_NR_REGS]; 110 unsigned int fifosize; 111 unsigned int overrun_reg; 112 unsigned int overrun_mask; 113 unsigned int sampling_rate_mask; 114 unsigned int error_mask; 115 unsigned int error_clear; 116 }; 117 118 struct sci_port { 119 struct uart_port port; 120 121 /* Platform configuration */ 122 const struct sci_port_params *params; 123 const struct plat_sci_port *cfg; 124 unsigned int sampling_rate_mask; 125 resource_size_t reg_size; 126 struct mctrl_gpios *gpios; 127 128 /* Clocks */ 129 struct clk *clks[SCI_NUM_CLKS]; 130 unsigned long clk_rates[SCI_NUM_CLKS]; 131 132 int irqs[SCIx_NR_IRQS]; 133 char *irqstr[SCIx_NR_IRQS]; 134 135 struct dma_chan *chan_tx; 136 struct dma_chan *chan_rx; 137 138 #ifdef CONFIG_SERIAL_SH_SCI_DMA 139 dma_cookie_t cookie_tx; 140 dma_cookie_t cookie_rx[2]; 141 dma_cookie_t active_rx; 142 dma_addr_t tx_dma_addr; 143 unsigned int tx_dma_len; 144 struct scatterlist sg_rx[2]; 145 void *rx_buf[2]; 146 size_t buf_len_rx; 147 struct work_struct work_tx; 148 struct timer_list rx_timer; 149 unsigned int rx_timeout; 150 #endif 151 unsigned int rx_frame; 152 int rx_trigger; 153 struct timer_list rx_fifo_timer; 154 int rx_fifo_timeout; 155 156 bool has_rtscts; 157 bool autorts; 158 }; 159 160 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS 161 162 static struct sci_port sci_ports[SCI_NPORTS]; 163 static struct uart_driver sci_uart_driver; 164 165 static inline struct sci_port * 166 to_sci_port(struct uart_port *uart) 167 { 168 return container_of(uart, struct sci_port, port); 169 } 170 171 static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { 172 /* 173 * Common SCI definitions, dependent on the port's regshift 174 * value. 175 */ 176 [SCIx_SCI_REGTYPE] = { 177 .regs = { 178 [SCSMR] = { 0x00, 8 }, 179 [SCBRR] = { 0x01, 8 }, 180 [SCSCR] = { 0x02, 8 }, 181 [SCxTDR] = { 0x03, 8 }, 182 [SCxSR] = { 0x04, 8 }, 183 [SCxRDR] = { 0x05, 8 }, 184 }, 185 .fifosize = 1, 186 .overrun_reg = SCxSR, 187 .overrun_mask = SCI_ORER, 188 .sampling_rate_mask = SCI_SR(32), 189 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, 190 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, 191 }, 192 193 /* 194 * Common definitions for legacy IrDA ports. 195 */ 196 [SCIx_IRDA_REGTYPE] = { 197 .regs = { 198 [SCSMR] = { 0x00, 8 }, 199 [SCBRR] = { 0x02, 8 }, 200 [SCSCR] = { 0x04, 8 }, 201 [SCxTDR] = { 0x06, 8 }, 202 [SCxSR] = { 0x08, 16 }, 203 [SCxRDR] = { 0x0a, 8 }, 204 [SCFCR] = { 0x0c, 8 }, 205 [SCFDR] = { 0x0e, 16 }, 206 }, 207 .fifosize = 1, 208 .overrun_reg = SCxSR, 209 .overrun_mask = SCI_ORER, 210 .sampling_rate_mask = SCI_SR(32), 211 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, 212 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, 213 }, 214 215 /* 216 * Common SCIFA definitions. 217 */ 218 [SCIx_SCIFA_REGTYPE] = { 219 .regs = { 220 [SCSMR] = { 0x00, 16 }, 221 [SCBRR] = { 0x04, 8 }, 222 [SCSCR] = { 0x08, 16 }, 223 [SCxTDR] = { 0x20, 8 }, 224 [SCxSR] = { 0x14, 16 }, 225 [SCxRDR] = { 0x24, 8 }, 226 [SCFCR] = { 0x18, 16 }, 227 [SCFDR] = { 0x1c, 16 }, 228 [SCPCR] = { 0x30, 16 }, 229 [SCPDR] = { 0x34, 16 }, 230 }, 231 .fifosize = 64, 232 .overrun_reg = SCxSR, 233 .overrun_mask = SCIFA_ORER, 234 .sampling_rate_mask = SCI_SR_SCIFAB, 235 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 236 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 237 }, 238 239 /* 240 * Common SCIFB definitions. 241 */ 242 [SCIx_SCIFB_REGTYPE] = { 243 .regs = { 244 [SCSMR] = { 0x00, 16 }, 245 [SCBRR] = { 0x04, 8 }, 246 [SCSCR] = { 0x08, 16 }, 247 [SCxTDR] = { 0x40, 8 }, 248 [SCxSR] = { 0x14, 16 }, 249 [SCxRDR] = { 0x60, 8 }, 250 [SCFCR] = { 0x18, 16 }, 251 [SCTFDR] = { 0x38, 16 }, 252 [SCRFDR] = { 0x3c, 16 }, 253 [SCPCR] = { 0x30, 16 }, 254 [SCPDR] = { 0x34, 16 }, 255 }, 256 .fifosize = 256, 257 .overrun_reg = SCxSR, 258 .overrun_mask = SCIFA_ORER, 259 .sampling_rate_mask = SCI_SR_SCIFAB, 260 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 261 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 262 }, 263 264 /* 265 * Common SH-2(A) SCIF definitions for ports with FIFO data 266 * count registers. 267 */ 268 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = { 269 .regs = { 270 [SCSMR] = { 0x00, 16 }, 271 [SCBRR] = { 0x04, 8 }, 272 [SCSCR] = { 0x08, 16 }, 273 [SCxTDR] = { 0x0c, 8 }, 274 [SCxSR] = { 0x10, 16 }, 275 [SCxRDR] = { 0x14, 8 }, 276 [SCFCR] = { 0x18, 16 }, 277 [SCFDR] = { 0x1c, 16 }, 278 [SCSPTR] = { 0x20, 16 }, 279 [SCLSR] = { 0x24, 16 }, 280 }, 281 .fifosize = 16, 282 .overrun_reg = SCLSR, 283 .overrun_mask = SCLSR_ORER, 284 .sampling_rate_mask = SCI_SR(32), 285 .error_mask = SCIF_DEFAULT_ERROR_MASK, 286 .error_clear = SCIF_ERROR_CLEAR, 287 }, 288 289 /* 290 * Common SH-3 SCIF definitions. 291 */ 292 [SCIx_SH3_SCIF_REGTYPE] = { 293 .regs = { 294 [SCSMR] = { 0x00, 8 }, 295 [SCBRR] = { 0x02, 8 }, 296 [SCSCR] = { 0x04, 8 }, 297 [SCxTDR] = { 0x06, 8 }, 298 [SCxSR] = { 0x08, 16 }, 299 [SCxRDR] = { 0x0a, 8 }, 300 [SCFCR] = { 0x0c, 8 }, 301 [SCFDR] = { 0x0e, 16 }, 302 }, 303 .fifosize = 16, 304 .overrun_reg = SCLSR, 305 .overrun_mask = SCLSR_ORER, 306 .sampling_rate_mask = SCI_SR(32), 307 .error_mask = SCIF_DEFAULT_ERROR_MASK, 308 .error_clear = SCIF_ERROR_CLEAR, 309 }, 310 311 /* 312 * Common SH-4(A) SCIF(B) definitions. 313 */ 314 [SCIx_SH4_SCIF_REGTYPE] = { 315 .regs = { 316 [SCSMR] = { 0x00, 16 }, 317 [SCBRR] = { 0x04, 8 }, 318 [SCSCR] = { 0x08, 16 }, 319 [SCxTDR] = { 0x0c, 8 }, 320 [SCxSR] = { 0x10, 16 }, 321 [SCxRDR] = { 0x14, 8 }, 322 [SCFCR] = { 0x18, 16 }, 323 [SCFDR] = { 0x1c, 16 }, 324 [SCSPTR] = { 0x20, 16 }, 325 [SCLSR] = { 0x24, 16 }, 326 }, 327 .fifosize = 16, 328 .overrun_reg = SCLSR, 329 .overrun_mask = SCLSR_ORER, 330 .sampling_rate_mask = SCI_SR(32), 331 .error_mask = SCIF_DEFAULT_ERROR_MASK, 332 .error_clear = SCIF_ERROR_CLEAR, 333 }, 334 335 /* 336 * Common SCIF definitions for ports with a Baud Rate Generator for 337 * External Clock (BRG). 338 */ 339 [SCIx_SH4_SCIF_BRG_REGTYPE] = { 340 .regs = { 341 [SCSMR] = { 0x00, 16 }, 342 [SCBRR] = { 0x04, 8 }, 343 [SCSCR] = { 0x08, 16 }, 344 [SCxTDR] = { 0x0c, 8 }, 345 [SCxSR] = { 0x10, 16 }, 346 [SCxRDR] = { 0x14, 8 }, 347 [SCFCR] = { 0x18, 16 }, 348 [SCFDR] = { 0x1c, 16 }, 349 [SCSPTR] = { 0x20, 16 }, 350 [SCLSR] = { 0x24, 16 }, 351 [SCDL] = { 0x30, 16 }, 352 [SCCKS] = { 0x34, 16 }, 353 }, 354 .fifosize = 16, 355 .overrun_reg = SCLSR, 356 .overrun_mask = SCLSR_ORER, 357 .sampling_rate_mask = SCI_SR(32), 358 .error_mask = SCIF_DEFAULT_ERROR_MASK, 359 .error_clear = SCIF_ERROR_CLEAR, 360 }, 361 362 /* 363 * Common HSCIF definitions. 364 */ 365 [SCIx_HSCIF_REGTYPE] = { 366 .regs = { 367 [SCSMR] = { 0x00, 16 }, 368 [SCBRR] = { 0x04, 8 }, 369 [SCSCR] = { 0x08, 16 }, 370 [SCxTDR] = { 0x0c, 8 }, 371 [SCxSR] = { 0x10, 16 }, 372 [SCxRDR] = { 0x14, 8 }, 373 [SCFCR] = { 0x18, 16 }, 374 [SCFDR] = { 0x1c, 16 }, 375 [SCSPTR] = { 0x20, 16 }, 376 [SCLSR] = { 0x24, 16 }, 377 [HSSRR] = { 0x40, 16 }, 378 [SCDL] = { 0x30, 16 }, 379 [SCCKS] = { 0x34, 16 }, 380 [HSRTRGR] = { 0x54, 16 }, 381 [HSTTRGR] = { 0x58, 16 }, 382 }, 383 .fifosize = 128, 384 .overrun_reg = SCLSR, 385 .overrun_mask = SCLSR_ORER, 386 .sampling_rate_mask = SCI_SR_RANGE(8, 32), 387 .error_mask = SCIF_DEFAULT_ERROR_MASK, 388 .error_clear = SCIF_ERROR_CLEAR, 389 }, 390 391 /* 392 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR 393 * register. 394 */ 395 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = { 396 .regs = { 397 [SCSMR] = { 0x00, 16 }, 398 [SCBRR] = { 0x04, 8 }, 399 [SCSCR] = { 0x08, 16 }, 400 [SCxTDR] = { 0x0c, 8 }, 401 [SCxSR] = { 0x10, 16 }, 402 [SCxRDR] = { 0x14, 8 }, 403 [SCFCR] = { 0x18, 16 }, 404 [SCFDR] = { 0x1c, 16 }, 405 [SCLSR] = { 0x24, 16 }, 406 }, 407 .fifosize = 16, 408 .overrun_reg = SCLSR, 409 .overrun_mask = SCLSR_ORER, 410 .sampling_rate_mask = SCI_SR(32), 411 .error_mask = SCIF_DEFAULT_ERROR_MASK, 412 .error_clear = SCIF_ERROR_CLEAR, 413 }, 414 415 /* 416 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data 417 * count registers. 418 */ 419 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = { 420 .regs = { 421 [SCSMR] = { 0x00, 16 }, 422 [SCBRR] = { 0x04, 8 }, 423 [SCSCR] = { 0x08, 16 }, 424 [SCxTDR] = { 0x0c, 8 }, 425 [SCxSR] = { 0x10, 16 }, 426 [SCxRDR] = { 0x14, 8 }, 427 [SCFCR] = { 0x18, 16 }, 428 [SCFDR] = { 0x1c, 16 }, 429 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */ 430 [SCRFDR] = { 0x20, 16 }, 431 [SCSPTR] = { 0x24, 16 }, 432 [SCLSR] = { 0x28, 16 }, 433 }, 434 .fifosize = 16, 435 .overrun_reg = SCLSR, 436 .overrun_mask = SCLSR_ORER, 437 .sampling_rate_mask = SCI_SR(32), 438 .error_mask = SCIF_DEFAULT_ERROR_MASK, 439 .error_clear = SCIF_ERROR_CLEAR, 440 }, 441 442 /* 443 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR 444 * registers. 445 */ 446 [SCIx_SH7705_SCIF_REGTYPE] = { 447 .regs = { 448 [SCSMR] = { 0x00, 16 }, 449 [SCBRR] = { 0x04, 8 }, 450 [SCSCR] = { 0x08, 16 }, 451 [SCxTDR] = { 0x20, 8 }, 452 [SCxSR] = { 0x14, 16 }, 453 [SCxRDR] = { 0x24, 8 }, 454 [SCFCR] = { 0x18, 16 }, 455 [SCFDR] = { 0x1c, 16 }, 456 }, 457 .fifosize = 64, 458 .overrun_reg = SCxSR, 459 .overrun_mask = SCIFA_ORER, 460 .sampling_rate_mask = SCI_SR(16), 461 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 462 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 463 }, 464 }; 465 466 #define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset]) 467 468 /* 469 * The "offset" here is rather misleading, in that it refers to an enum 470 * value relative to the port mapping rather than the fixed offset 471 * itself, which needs to be manually retrieved from the platform's 472 * register map for the given port. 473 */ 474 static unsigned int sci_serial_in(struct uart_port *p, int offset) 475 { 476 const struct plat_sci_reg *reg = sci_getreg(p, offset); 477 478 if (reg->size == 8) 479 return ioread8(p->membase + (reg->offset << p->regshift)); 480 else if (reg->size == 16) 481 return ioread16(p->membase + (reg->offset << p->regshift)); 482 else 483 WARN(1, "Invalid register access\n"); 484 485 return 0; 486 } 487 488 static void sci_serial_out(struct uart_port *p, int offset, int value) 489 { 490 const struct plat_sci_reg *reg = sci_getreg(p, offset); 491 492 if (reg->size == 8) 493 iowrite8(value, p->membase + (reg->offset << p->regshift)); 494 else if (reg->size == 16) 495 iowrite16(value, p->membase + (reg->offset << p->regshift)); 496 else 497 WARN(1, "Invalid register access\n"); 498 } 499 500 static void sci_port_enable(struct sci_port *sci_port) 501 { 502 unsigned int i; 503 504 if (!sci_port->port.dev) 505 return; 506 507 pm_runtime_get_sync(sci_port->port.dev); 508 509 for (i = 0; i < SCI_NUM_CLKS; i++) { 510 clk_prepare_enable(sci_port->clks[i]); 511 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]); 512 } 513 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK]; 514 } 515 516 static void sci_port_disable(struct sci_port *sci_port) 517 { 518 unsigned int i; 519 520 if (!sci_port->port.dev) 521 return; 522 523 for (i = SCI_NUM_CLKS; i-- > 0; ) 524 clk_disable_unprepare(sci_port->clks[i]); 525 526 pm_runtime_put_sync(sci_port->port.dev); 527 } 528 529 static inline unsigned long port_rx_irq_mask(struct uart_port *port) 530 { 531 /* 532 * Not all ports (such as SCIFA) will support REIE. Rather than 533 * special-casing the port type, we check the port initialization 534 * IRQ enable mask to see whether the IRQ is desired at all. If 535 * it's unset, it's logically inferred that there's no point in 536 * testing for it. 537 */ 538 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE); 539 } 540 541 static void sci_start_tx(struct uart_port *port) 542 { 543 struct sci_port *s = to_sci_port(port); 544 unsigned short ctrl; 545 546 #ifdef CONFIG_SERIAL_SH_SCI_DMA 547 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 548 u16 new, scr = serial_port_in(port, SCSCR); 549 if (s->chan_tx) 550 new = scr | SCSCR_TDRQE; 551 else 552 new = scr & ~SCSCR_TDRQE; 553 if (new != scr) 554 serial_port_out(port, SCSCR, new); 555 } 556 557 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) && 558 dma_submit_error(s->cookie_tx)) { 559 s->cookie_tx = 0; 560 schedule_work(&s->work_tx); 561 } 562 #endif 563 564 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 565 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ 566 ctrl = serial_port_in(port, SCSCR); 567 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE); 568 } 569 } 570 571 static void sci_stop_tx(struct uart_port *port) 572 { 573 unsigned short ctrl; 574 575 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ 576 ctrl = serial_port_in(port, SCSCR); 577 578 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 579 ctrl &= ~SCSCR_TDRQE; 580 581 ctrl &= ~SCSCR_TIE; 582 583 serial_port_out(port, SCSCR, ctrl); 584 } 585 586 static void sci_start_rx(struct uart_port *port) 587 { 588 unsigned short ctrl; 589 590 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port); 591 592 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 593 ctrl &= ~SCSCR_RDRQE; 594 595 serial_port_out(port, SCSCR, ctrl); 596 } 597 598 static void sci_stop_rx(struct uart_port *port) 599 { 600 unsigned short ctrl; 601 602 ctrl = serial_port_in(port, SCSCR); 603 604 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 605 ctrl &= ~SCSCR_RDRQE; 606 607 ctrl &= ~port_rx_irq_mask(port); 608 609 serial_port_out(port, SCSCR, ctrl); 610 } 611 612 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask) 613 { 614 if (port->type == PORT_SCI) { 615 /* Just store the mask */ 616 serial_port_out(port, SCxSR, mask); 617 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) { 618 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */ 619 /* Only clear the status bits we want to clear */ 620 serial_port_out(port, SCxSR, 621 serial_port_in(port, SCxSR) & mask); 622 } else { 623 /* Store the mask, clear parity/framing errors */ 624 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC)); 625 } 626 } 627 628 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ 629 defined(CONFIG_SERIAL_SH_SCI_EARLYCON) 630 631 #ifdef CONFIG_CONSOLE_POLL 632 static int sci_poll_get_char(struct uart_port *port) 633 { 634 unsigned short status; 635 int c; 636 637 do { 638 status = serial_port_in(port, SCxSR); 639 if (status & SCxSR_ERRORS(port)) { 640 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); 641 continue; 642 } 643 break; 644 } while (1); 645 646 if (!(status & SCxSR_RDxF(port))) 647 return NO_POLL_CHAR; 648 649 c = serial_port_in(port, SCxRDR); 650 651 /* Dummy read */ 652 serial_port_in(port, SCxSR); 653 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 654 655 return c; 656 } 657 #endif 658 659 static void sci_poll_put_char(struct uart_port *port, unsigned char c) 660 { 661 unsigned short status; 662 663 do { 664 status = serial_port_in(port, SCxSR); 665 } while (!(status & SCxSR_TDxE(port))); 666 667 serial_port_out(port, SCxTDR, c); 668 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port)); 669 } 670 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE || 671 CONFIG_SERIAL_SH_SCI_EARLYCON */ 672 673 static void sci_init_pins(struct uart_port *port, unsigned int cflag) 674 { 675 struct sci_port *s = to_sci_port(port); 676 677 /* 678 * Use port-specific handler if provided. 679 */ 680 if (s->cfg->ops && s->cfg->ops->init_pins) { 681 s->cfg->ops->init_pins(port, cflag); 682 return; 683 } 684 685 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 686 u16 data = serial_port_in(port, SCPDR); 687 u16 ctrl = serial_port_in(port, SCPCR); 688 689 /* Enable RXD and TXD pin functions */ 690 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC); 691 if (to_sci_port(port)->has_rtscts) { 692 /* RTS# is output, active low, unless autorts */ 693 if (!(port->mctrl & TIOCM_RTS)) { 694 ctrl |= SCPCR_RTSC; 695 data |= SCPDR_RTSD; 696 } else if (!s->autorts) { 697 ctrl |= SCPCR_RTSC; 698 data &= ~SCPDR_RTSD; 699 } else { 700 /* Enable RTS# pin function */ 701 ctrl &= ~SCPCR_RTSC; 702 } 703 /* Enable CTS# pin function */ 704 ctrl &= ~SCPCR_CTSC; 705 } 706 serial_port_out(port, SCPDR, data); 707 serial_port_out(port, SCPCR, ctrl); 708 } else if (sci_getreg(port, SCSPTR)->size) { 709 u16 status = serial_port_in(port, SCSPTR); 710 711 /* RTS# is always output; and active low, unless autorts */ 712 status |= SCSPTR_RTSIO; 713 if (!(port->mctrl & TIOCM_RTS)) 714 status |= SCSPTR_RTSDT; 715 else if (!s->autorts) 716 status &= ~SCSPTR_RTSDT; 717 /* CTS# and SCK are inputs */ 718 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO); 719 serial_port_out(port, SCSPTR, status); 720 } 721 } 722 723 static int sci_txfill(struct uart_port *port) 724 { 725 struct sci_port *s = to_sci_port(port); 726 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; 727 const struct plat_sci_reg *reg; 728 729 reg = sci_getreg(port, SCTFDR); 730 if (reg->size) 731 return serial_port_in(port, SCTFDR) & fifo_mask; 732 733 reg = sci_getreg(port, SCFDR); 734 if (reg->size) 735 return serial_port_in(port, SCFDR) >> 8; 736 737 return !(serial_port_in(port, SCxSR) & SCI_TDRE); 738 } 739 740 static int sci_txroom(struct uart_port *port) 741 { 742 return port->fifosize - sci_txfill(port); 743 } 744 745 static int sci_rxfill(struct uart_port *port) 746 { 747 struct sci_port *s = to_sci_port(port); 748 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; 749 const struct plat_sci_reg *reg; 750 751 reg = sci_getreg(port, SCRFDR); 752 if (reg->size) 753 return serial_port_in(port, SCRFDR) & fifo_mask; 754 755 reg = sci_getreg(port, SCFDR); 756 if (reg->size) 757 return serial_port_in(port, SCFDR) & fifo_mask; 758 759 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0; 760 } 761 762 /* ********************************************************************** * 763 * the interrupt related routines * 764 * ********************************************************************** */ 765 766 static void sci_transmit_chars(struct uart_port *port) 767 { 768 struct circ_buf *xmit = &port->state->xmit; 769 unsigned int stopped = uart_tx_stopped(port); 770 unsigned short status; 771 unsigned short ctrl; 772 int count; 773 774 status = serial_port_in(port, SCxSR); 775 if (!(status & SCxSR_TDxE(port))) { 776 ctrl = serial_port_in(port, SCSCR); 777 if (uart_circ_empty(xmit)) 778 ctrl &= ~SCSCR_TIE; 779 else 780 ctrl |= SCSCR_TIE; 781 serial_port_out(port, SCSCR, ctrl); 782 return; 783 } 784 785 count = sci_txroom(port); 786 787 do { 788 unsigned char c; 789 790 if (port->x_char) { 791 c = port->x_char; 792 port->x_char = 0; 793 } else if (!uart_circ_empty(xmit) && !stopped) { 794 c = xmit->buf[xmit->tail]; 795 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 796 } else { 797 break; 798 } 799 800 serial_port_out(port, SCxTDR, c); 801 802 port->icount.tx++; 803 } while (--count > 0); 804 805 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port)); 806 807 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 808 uart_write_wakeup(port); 809 if (uart_circ_empty(xmit)) { 810 sci_stop_tx(port); 811 } else { 812 ctrl = serial_port_in(port, SCSCR); 813 814 if (port->type != PORT_SCI) { 815 serial_port_in(port, SCxSR); /* Dummy read */ 816 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port)); 817 } 818 819 ctrl |= SCSCR_TIE; 820 serial_port_out(port, SCSCR, ctrl); 821 } 822 } 823 824 /* On SH3, SCIF may read end-of-break as a space->mark char */ 825 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); }) 826 827 static void sci_receive_chars(struct uart_port *port) 828 { 829 struct tty_port *tport = &port->state->port; 830 int i, count, copied = 0; 831 unsigned short status; 832 unsigned char flag; 833 834 status = serial_port_in(port, SCxSR); 835 if (!(status & SCxSR_RDxF(port))) 836 return; 837 838 while (1) { 839 /* Don't copy more bytes than there is room for in the buffer */ 840 count = tty_buffer_request_room(tport, sci_rxfill(port)); 841 842 /* If for any reason we can't copy more data, we're done! */ 843 if (count == 0) 844 break; 845 846 if (port->type == PORT_SCI) { 847 char c = serial_port_in(port, SCxRDR); 848 if (uart_handle_sysrq_char(port, c)) 849 count = 0; 850 else 851 tty_insert_flip_char(tport, c, TTY_NORMAL); 852 } else { 853 for (i = 0; i < count; i++) { 854 char c = serial_port_in(port, SCxRDR); 855 856 status = serial_port_in(port, SCxSR); 857 if (uart_handle_sysrq_char(port, c)) { 858 count--; i--; 859 continue; 860 } 861 862 /* Store data and status */ 863 if (status & SCxSR_FER(port)) { 864 flag = TTY_FRAME; 865 port->icount.frame++; 866 dev_notice(port->dev, "frame error\n"); 867 } else if (status & SCxSR_PER(port)) { 868 flag = TTY_PARITY; 869 port->icount.parity++; 870 dev_notice(port->dev, "parity error\n"); 871 } else 872 flag = TTY_NORMAL; 873 874 tty_insert_flip_char(tport, c, flag); 875 } 876 } 877 878 serial_port_in(port, SCxSR); /* dummy read */ 879 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 880 881 copied += count; 882 port->icount.rx += count; 883 } 884 885 if (copied) { 886 /* Tell the rest of the system the news. New characters! */ 887 tty_flip_buffer_push(tport); 888 } else { 889 serial_port_in(port, SCxSR); /* dummy read */ 890 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 891 } 892 } 893 894 static int sci_handle_errors(struct uart_port *port) 895 { 896 int copied = 0; 897 unsigned short status = serial_port_in(port, SCxSR); 898 struct tty_port *tport = &port->state->port; 899 struct sci_port *s = to_sci_port(port); 900 901 /* Handle overruns */ 902 if (status & s->params->overrun_mask) { 903 port->icount.overrun++; 904 905 /* overrun error */ 906 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN)) 907 copied++; 908 909 dev_notice(port->dev, "overrun error\n"); 910 } 911 912 if (status & SCxSR_FER(port)) { 913 /* frame error */ 914 port->icount.frame++; 915 916 if (tty_insert_flip_char(tport, 0, TTY_FRAME)) 917 copied++; 918 919 dev_notice(port->dev, "frame error\n"); 920 } 921 922 if (status & SCxSR_PER(port)) { 923 /* parity error */ 924 port->icount.parity++; 925 926 if (tty_insert_flip_char(tport, 0, TTY_PARITY)) 927 copied++; 928 929 dev_notice(port->dev, "parity error\n"); 930 } 931 932 if (copied) 933 tty_flip_buffer_push(tport); 934 935 return copied; 936 } 937 938 static int sci_handle_fifo_overrun(struct uart_port *port) 939 { 940 struct tty_port *tport = &port->state->port; 941 struct sci_port *s = to_sci_port(port); 942 const struct plat_sci_reg *reg; 943 int copied = 0; 944 u16 status; 945 946 reg = sci_getreg(port, s->params->overrun_reg); 947 if (!reg->size) 948 return 0; 949 950 status = serial_port_in(port, s->params->overrun_reg); 951 if (status & s->params->overrun_mask) { 952 status &= ~s->params->overrun_mask; 953 serial_port_out(port, s->params->overrun_reg, status); 954 955 port->icount.overrun++; 956 957 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 958 tty_flip_buffer_push(tport); 959 960 dev_dbg(port->dev, "overrun error\n"); 961 copied++; 962 } 963 964 return copied; 965 } 966 967 static int sci_handle_breaks(struct uart_port *port) 968 { 969 int copied = 0; 970 unsigned short status = serial_port_in(port, SCxSR); 971 struct tty_port *tport = &port->state->port; 972 973 if (uart_handle_break(port)) 974 return 0; 975 976 if (status & SCxSR_BRK(port)) { 977 port->icount.brk++; 978 979 /* Notify of BREAK */ 980 if (tty_insert_flip_char(tport, 0, TTY_BREAK)) 981 copied++; 982 983 dev_dbg(port->dev, "BREAK detected\n"); 984 } 985 986 if (copied) 987 tty_flip_buffer_push(tport); 988 989 copied += sci_handle_fifo_overrun(port); 990 991 return copied; 992 } 993 994 static int scif_set_rtrg(struct uart_port *port, int rx_trig) 995 { 996 unsigned int bits; 997 998 if (rx_trig < 1) 999 rx_trig = 1; 1000 if (rx_trig >= port->fifosize) 1001 rx_trig = port->fifosize; 1002 1003 /* HSCIF can be set to an arbitrary level. */ 1004 if (sci_getreg(port, HSRTRGR)->size) { 1005 serial_port_out(port, HSRTRGR, rx_trig); 1006 return rx_trig; 1007 } 1008 1009 switch (port->type) { 1010 case PORT_SCIF: 1011 if (rx_trig < 4) { 1012 bits = 0; 1013 rx_trig = 1; 1014 } else if (rx_trig < 8) { 1015 bits = SCFCR_RTRG0; 1016 rx_trig = 4; 1017 } else if (rx_trig < 14) { 1018 bits = SCFCR_RTRG1; 1019 rx_trig = 8; 1020 } else { 1021 bits = SCFCR_RTRG0 | SCFCR_RTRG1; 1022 rx_trig = 14; 1023 } 1024 break; 1025 case PORT_SCIFA: 1026 case PORT_SCIFB: 1027 if (rx_trig < 16) { 1028 bits = 0; 1029 rx_trig = 1; 1030 } else if (rx_trig < 32) { 1031 bits = SCFCR_RTRG0; 1032 rx_trig = 16; 1033 } else if (rx_trig < 48) { 1034 bits = SCFCR_RTRG1; 1035 rx_trig = 32; 1036 } else { 1037 bits = SCFCR_RTRG0 | SCFCR_RTRG1; 1038 rx_trig = 48; 1039 } 1040 break; 1041 default: 1042 WARN(1, "unknown FIFO configuration"); 1043 return 1; 1044 } 1045 1046 serial_port_out(port, SCFCR, 1047 (serial_port_in(port, SCFCR) & 1048 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits); 1049 1050 return rx_trig; 1051 } 1052 1053 static int scif_rtrg_enabled(struct uart_port *port) 1054 { 1055 if (sci_getreg(port, HSRTRGR)->size) 1056 return serial_port_in(port, HSRTRGR) != 0; 1057 else 1058 return (serial_port_in(port, SCFCR) & 1059 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0; 1060 } 1061 1062 static void rx_fifo_timer_fn(unsigned long arg) 1063 { 1064 struct sci_port *s = (struct sci_port *)arg; 1065 struct uart_port *port = &s->port; 1066 1067 dev_dbg(port->dev, "Rx timed out\n"); 1068 scif_set_rtrg(port, 1); 1069 } 1070 1071 static ssize_t rx_trigger_show(struct device *dev, 1072 struct device_attribute *attr, 1073 char *buf) 1074 { 1075 struct uart_port *port = dev_get_drvdata(dev); 1076 struct sci_port *sci = to_sci_port(port); 1077 1078 return sprintf(buf, "%d\n", sci->rx_trigger); 1079 } 1080 1081 static ssize_t rx_trigger_store(struct device *dev, 1082 struct device_attribute *attr, 1083 const char *buf, 1084 size_t count) 1085 { 1086 struct uart_port *port = dev_get_drvdata(dev); 1087 struct sci_port *sci = to_sci_port(port); 1088 long r; 1089 1090 if (kstrtol(buf, 0, &r) == -EINVAL) 1091 return -EINVAL; 1092 1093 sci->rx_trigger = scif_set_rtrg(port, r); 1094 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1095 scif_set_rtrg(port, 1); 1096 1097 return count; 1098 } 1099 1100 static DEVICE_ATTR(rx_fifo_trigger, 0644, rx_trigger_show, rx_trigger_store); 1101 1102 static ssize_t rx_fifo_timeout_show(struct device *dev, 1103 struct device_attribute *attr, 1104 char *buf) 1105 { 1106 struct uart_port *port = dev_get_drvdata(dev); 1107 struct sci_port *sci = to_sci_port(port); 1108 1109 return sprintf(buf, "%d\n", sci->rx_fifo_timeout); 1110 } 1111 1112 static ssize_t rx_fifo_timeout_store(struct device *dev, 1113 struct device_attribute *attr, 1114 const char *buf, 1115 size_t count) 1116 { 1117 struct uart_port *port = dev_get_drvdata(dev); 1118 struct sci_port *sci = to_sci_port(port); 1119 long r; 1120 1121 if (kstrtol(buf, 0, &r) == -EINVAL) 1122 return -EINVAL; 1123 sci->rx_fifo_timeout = r; 1124 scif_set_rtrg(port, 1); 1125 if (r > 0) 1126 setup_timer(&sci->rx_fifo_timer, rx_fifo_timer_fn, 1127 (unsigned long)sci); 1128 return count; 1129 } 1130 1131 static DEVICE_ATTR(rx_fifo_timeout, 0644, rx_fifo_timeout_show, rx_fifo_timeout_store); 1132 1133 1134 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1135 static void sci_dma_tx_complete(void *arg) 1136 { 1137 struct sci_port *s = arg; 1138 struct uart_port *port = &s->port; 1139 struct circ_buf *xmit = &port->state->xmit; 1140 unsigned long flags; 1141 1142 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1143 1144 spin_lock_irqsave(&port->lock, flags); 1145 1146 xmit->tail += s->tx_dma_len; 1147 xmit->tail &= UART_XMIT_SIZE - 1; 1148 1149 port->icount.tx += s->tx_dma_len; 1150 1151 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1152 uart_write_wakeup(port); 1153 1154 if (!uart_circ_empty(xmit)) { 1155 s->cookie_tx = 0; 1156 schedule_work(&s->work_tx); 1157 } else { 1158 s->cookie_tx = -EINVAL; 1159 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1160 u16 ctrl = serial_port_in(port, SCSCR); 1161 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE); 1162 } 1163 } 1164 1165 spin_unlock_irqrestore(&port->lock, flags); 1166 } 1167 1168 /* Locking: called with port lock held */ 1169 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count) 1170 { 1171 struct uart_port *port = &s->port; 1172 struct tty_port *tport = &port->state->port; 1173 int copied; 1174 1175 copied = tty_insert_flip_string(tport, buf, count); 1176 if (copied < count) 1177 port->icount.buf_overrun++; 1178 1179 port->icount.rx += copied; 1180 1181 return copied; 1182 } 1183 1184 static int sci_dma_rx_find_active(struct sci_port *s) 1185 { 1186 unsigned int i; 1187 1188 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) 1189 if (s->active_rx == s->cookie_rx[i]) 1190 return i; 1191 1192 return -1; 1193 } 1194 1195 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio) 1196 { 1197 struct dma_chan *chan = s->chan_rx; 1198 struct uart_port *port = &s->port; 1199 unsigned long flags; 1200 1201 spin_lock_irqsave(&port->lock, flags); 1202 s->chan_rx = NULL; 1203 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL; 1204 spin_unlock_irqrestore(&port->lock, flags); 1205 dmaengine_terminate_all(chan); 1206 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0], 1207 sg_dma_address(&s->sg_rx[0])); 1208 dma_release_channel(chan); 1209 if (enable_pio) 1210 sci_start_rx(port); 1211 } 1212 1213 static void sci_dma_rx_complete(void *arg) 1214 { 1215 struct sci_port *s = arg; 1216 struct dma_chan *chan = s->chan_rx; 1217 struct uart_port *port = &s->port; 1218 struct dma_async_tx_descriptor *desc; 1219 unsigned long flags; 1220 int active, count = 0; 1221 1222 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line, 1223 s->active_rx); 1224 1225 spin_lock_irqsave(&port->lock, flags); 1226 1227 active = sci_dma_rx_find_active(s); 1228 if (active >= 0) 1229 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx); 1230 1231 mod_timer(&s->rx_timer, jiffies + s->rx_timeout); 1232 1233 if (count) 1234 tty_flip_buffer_push(&port->state->port); 1235 1236 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1, 1237 DMA_DEV_TO_MEM, 1238 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1239 if (!desc) 1240 goto fail; 1241 1242 desc->callback = sci_dma_rx_complete; 1243 desc->callback_param = s; 1244 s->cookie_rx[active] = dmaengine_submit(desc); 1245 if (dma_submit_error(s->cookie_rx[active])) 1246 goto fail; 1247 1248 s->active_rx = s->cookie_rx[!active]; 1249 1250 dma_async_issue_pending(chan); 1251 1252 spin_unlock_irqrestore(&port->lock, flags); 1253 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n", 1254 __func__, s->cookie_rx[active], active, s->active_rx); 1255 return; 1256 1257 fail: 1258 spin_unlock_irqrestore(&port->lock, flags); 1259 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n"); 1260 sci_rx_dma_release(s, true); 1261 } 1262 1263 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio) 1264 { 1265 struct dma_chan *chan = s->chan_tx; 1266 struct uart_port *port = &s->port; 1267 unsigned long flags; 1268 1269 spin_lock_irqsave(&port->lock, flags); 1270 s->chan_tx = NULL; 1271 s->cookie_tx = -EINVAL; 1272 spin_unlock_irqrestore(&port->lock, flags); 1273 dmaengine_terminate_all(chan); 1274 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE, 1275 DMA_TO_DEVICE); 1276 dma_release_channel(chan); 1277 if (enable_pio) 1278 sci_start_tx(port); 1279 } 1280 1281 static void sci_submit_rx(struct sci_port *s) 1282 { 1283 struct dma_chan *chan = s->chan_rx; 1284 int i; 1285 1286 for (i = 0; i < 2; i++) { 1287 struct scatterlist *sg = &s->sg_rx[i]; 1288 struct dma_async_tx_descriptor *desc; 1289 1290 desc = dmaengine_prep_slave_sg(chan, 1291 sg, 1, DMA_DEV_TO_MEM, 1292 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1293 if (!desc) 1294 goto fail; 1295 1296 desc->callback = sci_dma_rx_complete; 1297 desc->callback_param = s; 1298 s->cookie_rx[i] = dmaengine_submit(desc); 1299 if (dma_submit_error(s->cookie_rx[i])) 1300 goto fail; 1301 1302 } 1303 1304 s->active_rx = s->cookie_rx[0]; 1305 1306 dma_async_issue_pending(chan); 1307 return; 1308 1309 fail: 1310 if (i) 1311 dmaengine_terminate_all(chan); 1312 for (i = 0; i < 2; i++) 1313 s->cookie_rx[i] = -EINVAL; 1314 s->active_rx = -EINVAL; 1315 sci_rx_dma_release(s, true); 1316 } 1317 1318 static void work_fn_tx(struct work_struct *work) 1319 { 1320 struct sci_port *s = container_of(work, struct sci_port, work_tx); 1321 struct dma_async_tx_descriptor *desc; 1322 struct dma_chan *chan = s->chan_tx; 1323 struct uart_port *port = &s->port; 1324 struct circ_buf *xmit = &port->state->xmit; 1325 dma_addr_t buf; 1326 1327 /* 1328 * DMA is idle now. 1329 * Port xmit buffer is already mapped, and it is one page... Just adjust 1330 * offsets and lengths. Since it is a circular buffer, we have to 1331 * transmit till the end, and then the rest. Take the port lock to get a 1332 * consistent xmit buffer state. 1333 */ 1334 spin_lock_irq(&port->lock); 1335 buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1)); 1336 s->tx_dma_len = min_t(unsigned int, 1337 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE), 1338 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE)); 1339 spin_unlock_irq(&port->lock); 1340 1341 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len, 1342 DMA_MEM_TO_DEV, 1343 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1344 if (!desc) { 1345 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n"); 1346 /* switch to PIO */ 1347 sci_tx_dma_release(s, true); 1348 return; 1349 } 1350 1351 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len, 1352 DMA_TO_DEVICE); 1353 1354 spin_lock_irq(&port->lock); 1355 desc->callback = sci_dma_tx_complete; 1356 desc->callback_param = s; 1357 spin_unlock_irq(&port->lock); 1358 s->cookie_tx = dmaengine_submit(desc); 1359 if (dma_submit_error(s->cookie_tx)) { 1360 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n"); 1361 /* switch to PIO */ 1362 sci_tx_dma_release(s, true); 1363 return; 1364 } 1365 1366 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", 1367 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx); 1368 1369 dma_async_issue_pending(chan); 1370 } 1371 1372 static void rx_timer_fn(unsigned long arg) 1373 { 1374 struct sci_port *s = (struct sci_port *)arg; 1375 struct dma_chan *chan = s->chan_rx; 1376 struct uart_port *port = &s->port; 1377 struct dma_tx_state state; 1378 enum dma_status status; 1379 unsigned long flags; 1380 unsigned int read; 1381 int active, count; 1382 u16 scr; 1383 1384 dev_dbg(port->dev, "DMA Rx timed out\n"); 1385 1386 spin_lock_irqsave(&port->lock, flags); 1387 1388 active = sci_dma_rx_find_active(s); 1389 if (active < 0) { 1390 spin_unlock_irqrestore(&port->lock, flags); 1391 return; 1392 } 1393 1394 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); 1395 if (status == DMA_COMPLETE) { 1396 spin_unlock_irqrestore(&port->lock, flags); 1397 dev_dbg(port->dev, "Cookie %d #%d has already completed\n", 1398 s->active_rx, active); 1399 1400 /* Let packet complete handler take care of the packet */ 1401 return; 1402 } 1403 1404 dmaengine_pause(chan); 1405 1406 /* 1407 * sometimes DMA transfer doesn't stop even if it is stopped and 1408 * data keeps on coming until transaction is complete so check 1409 * for DMA_COMPLETE again 1410 * Let packet complete handler take care of the packet 1411 */ 1412 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); 1413 if (status == DMA_COMPLETE) { 1414 spin_unlock_irqrestore(&port->lock, flags); 1415 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped"); 1416 return; 1417 } 1418 1419 /* Handle incomplete DMA receive */ 1420 dmaengine_terminate_all(s->chan_rx); 1421 read = sg_dma_len(&s->sg_rx[active]) - state.residue; 1422 1423 if (read) { 1424 count = sci_dma_rx_push(s, s->rx_buf[active], read); 1425 if (count) 1426 tty_flip_buffer_push(&port->state->port); 1427 } 1428 1429 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1430 sci_submit_rx(s); 1431 1432 /* Direct new serial port interrupts back to CPU */ 1433 scr = serial_port_in(port, SCSCR); 1434 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1435 scr &= ~SCSCR_RDRQE; 1436 enable_irq(s->irqs[SCIx_RXI_IRQ]); 1437 } 1438 serial_port_out(port, SCSCR, scr | SCSCR_RIE); 1439 1440 spin_unlock_irqrestore(&port->lock, flags); 1441 } 1442 1443 static struct dma_chan *sci_request_dma_chan(struct uart_port *port, 1444 enum dma_transfer_direction dir) 1445 { 1446 struct dma_chan *chan; 1447 struct dma_slave_config cfg; 1448 int ret; 1449 1450 chan = dma_request_slave_channel(port->dev, 1451 dir == DMA_MEM_TO_DEV ? "tx" : "rx"); 1452 if (!chan) { 1453 dev_warn(port->dev, 1454 "dma_request_slave_channel_compat failed\n"); 1455 return NULL; 1456 } 1457 1458 memset(&cfg, 0, sizeof(cfg)); 1459 cfg.direction = dir; 1460 if (dir == DMA_MEM_TO_DEV) { 1461 cfg.dst_addr = port->mapbase + 1462 (sci_getreg(port, SCxTDR)->offset << port->regshift); 1463 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1464 } else { 1465 cfg.src_addr = port->mapbase + 1466 (sci_getreg(port, SCxRDR)->offset << port->regshift); 1467 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1468 } 1469 1470 ret = dmaengine_slave_config(chan, &cfg); 1471 if (ret) { 1472 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret); 1473 dma_release_channel(chan); 1474 return NULL; 1475 } 1476 1477 return chan; 1478 } 1479 1480 static void sci_request_dma(struct uart_port *port) 1481 { 1482 struct sci_port *s = to_sci_port(port); 1483 struct dma_chan *chan; 1484 1485 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line); 1486 1487 if (!port->dev->of_node) 1488 return; 1489 1490 s->cookie_tx = -EINVAL; 1491 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV); 1492 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan); 1493 if (chan) { 1494 s->chan_tx = chan; 1495 /* UART circular tx buffer is an aligned page. */ 1496 s->tx_dma_addr = dma_map_single(chan->device->dev, 1497 port->state->xmit.buf, 1498 UART_XMIT_SIZE, 1499 DMA_TO_DEVICE); 1500 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) { 1501 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n"); 1502 dma_release_channel(chan); 1503 s->chan_tx = NULL; 1504 } else { 1505 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n", 1506 __func__, UART_XMIT_SIZE, 1507 port->state->xmit.buf, &s->tx_dma_addr); 1508 } 1509 1510 INIT_WORK(&s->work_tx, work_fn_tx); 1511 } 1512 1513 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM); 1514 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan); 1515 if (chan) { 1516 unsigned int i; 1517 dma_addr_t dma; 1518 void *buf; 1519 1520 s->chan_rx = chan; 1521 1522 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize); 1523 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2, 1524 &dma, GFP_KERNEL); 1525 if (!buf) { 1526 dev_warn(port->dev, 1527 "Failed to allocate Rx dma buffer, using PIO\n"); 1528 dma_release_channel(chan); 1529 s->chan_rx = NULL; 1530 return; 1531 } 1532 1533 for (i = 0; i < 2; i++) { 1534 struct scatterlist *sg = &s->sg_rx[i]; 1535 1536 sg_init_table(sg, 1); 1537 s->rx_buf[i] = buf; 1538 sg_dma_address(sg) = dma; 1539 sg_dma_len(sg) = s->buf_len_rx; 1540 1541 buf += s->buf_len_rx; 1542 dma += s->buf_len_rx; 1543 } 1544 1545 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s); 1546 1547 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1548 sci_submit_rx(s); 1549 } 1550 } 1551 1552 static void sci_free_dma(struct uart_port *port) 1553 { 1554 struct sci_port *s = to_sci_port(port); 1555 1556 if (s->chan_tx) 1557 sci_tx_dma_release(s, false); 1558 if (s->chan_rx) 1559 sci_rx_dma_release(s, false); 1560 } 1561 #else 1562 static inline void sci_request_dma(struct uart_port *port) 1563 { 1564 } 1565 1566 static inline void sci_free_dma(struct uart_port *port) 1567 { 1568 } 1569 #endif 1570 1571 static irqreturn_t sci_rx_interrupt(int irq, void *ptr) 1572 { 1573 struct uart_port *port = ptr; 1574 struct sci_port *s = to_sci_port(port); 1575 1576 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1577 if (s->chan_rx) { 1578 u16 scr = serial_port_in(port, SCSCR); 1579 u16 ssr = serial_port_in(port, SCxSR); 1580 1581 /* Disable future Rx interrupts */ 1582 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1583 disable_irq_nosync(irq); 1584 scr |= SCSCR_RDRQE; 1585 } else { 1586 scr &= ~SCSCR_RIE; 1587 sci_submit_rx(s); 1588 } 1589 serial_port_out(port, SCSCR, scr); 1590 /* Clear current interrupt */ 1591 serial_port_out(port, SCxSR, 1592 ssr & ~(SCIF_DR | SCxSR_RDxF(port))); 1593 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n", 1594 jiffies, s->rx_timeout); 1595 mod_timer(&s->rx_timer, jiffies + s->rx_timeout); 1596 1597 return IRQ_HANDLED; 1598 } 1599 #endif 1600 1601 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) { 1602 if (!scif_rtrg_enabled(port)) 1603 scif_set_rtrg(port, s->rx_trigger); 1604 1605 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP( 1606 s->rx_frame * s->rx_fifo_timeout, 1000)); 1607 } 1608 1609 /* I think sci_receive_chars has to be called irrespective 1610 * of whether the I_IXOFF is set, otherwise, how is the interrupt 1611 * to be disabled? 1612 */ 1613 sci_receive_chars(ptr); 1614 1615 return IRQ_HANDLED; 1616 } 1617 1618 static irqreturn_t sci_tx_interrupt(int irq, void *ptr) 1619 { 1620 struct uart_port *port = ptr; 1621 unsigned long flags; 1622 1623 spin_lock_irqsave(&port->lock, flags); 1624 sci_transmit_chars(port); 1625 spin_unlock_irqrestore(&port->lock, flags); 1626 1627 return IRQ_HANDLED; 1628 } 1629 1630 static irqreturn_t sci_er_interrupt(int irq, void *ptr) 1631 { 1632 struct uart_port *port = ptr; 1633 struct sci_port *s = to_sci_port(port); 1634 1635 /* Handle errors */ 1636 if (port->type == PORT_SCI) { 1637 if (sci_handle_errors(port)) { 1638 /* discard character in rx buffer */ 1639 serial_port_in(port, SCxSR); 1640 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 1641 } 1642 } else { 1643 sci_handle_fifo_overrun(port); 1644 if (!s->chan_rx) 1645 sci_receive_chars(ptr); 1646 } 1647 1648 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); 1649 1650 /* Kick the transmission */ 1651 if (!s->chan_tx) 1652 sci_tx_interrupt(irq, ptr); 1653 1654 return IRQ_HANDLED; 1655 } 1656 1657 static irqreturn_t sci_br_interrupt(int irq, void *ptr) 1658 { 1659 struct uart_port *port = ptr; 1660 1661 /* Handle BREAKs */ 1662 sci_handle_breaks(port); 1663 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port)); 1664 1665 return IRQ_HANDLED; 1666 } 1667 1668 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) 1669 { 1670 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0; 1671 struct uart_port *port = ptr; 1672 struct sci_port *s = to_sci_port(port); 1673 irqreturn_t ret = IRQ_NONE; 1674 1675 ssr_status = serial_port_in(port, SCxSR); 1676 scr_status = serial_port_in(port, SCSCR); 1677 if (s->params->overrun_reg == SCxSR) 1678 orer_status = ssr_status; 1679 else if (sci_getreg(port, s->params->overrun_reg)->size) 1680 orer_status = serial_port_in(port, s->params->overrun_reg); 1681 1682 err_enabled = scr_status & port_rx_irq_mask(port); 1683 1684 /* Tx Interrupt */ 1685 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) && 1686 !s->chan_tx) 1687 ret = sci_tx_interrupt(irq, ptr); 1688 1689 /* 1690 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF / 1691 * DR flags 1692 */ 1693 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) && 1694 (scr_status & SCSCR_RIE)) 1695 ret = sci_rx_interrupt(irq, ptr); 1696 1697 /* Error Interrupt */ 1698 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled) 1699 ret = sci_er_interrupt(irq, ptr); 1700 1701 /* Break Interrupt */ 1702 if ((ssr_status & SCxSR_BRK(port)) && err_enabled) 1703 ret = sci_br_interrupt(irq, ptr); 1704 1705 /* Overrun Interrupt */ 1706 if (orer_status & s->params->overrun_mask) { 1707 sci_handle_fifo_overrun(port); 1708 ret = IRQ_HANDLED; 1709 } 1710 1711 return ret; 1712 } 1713 1714 static const struct sci_irq_desc { 1715 const char *desc; 1716 irq_handler_t handler; 1717 } sci_irq_desc[] = { 1718 /* 1719 * Split out handlers, the default case. 1720 */ 1721 [SCIx_ERI_IRQ] = { 1722 .desc = "rx err", 1723 .handler = sci_er_interrupt, 1724 }, 1725 1726 [SCIx_RXI_IRQ] = { 1727 .desc = "rx full", 1728 .handler = sci_rx_interrupt, 1729 }, 1730 1731 [SCIx_TXI_IRQ] = { 1732 .desc = "tx empty", 1733 .handler = sci_tx_interrupt, 1734 }, 1735 1736 [SCIx_BRI_IRQ] = { 1737 .desc = "break", 1738 .handler = sci_br_interrupt, 1739 }, 1740 1741 /* 1742 * Special muxed handler. 1743 */ 1744 [SCIx_MUX_IRQ] = { 1745 .desc = "mux", 1746 .handler = sci_mpxed_interrupt, 1747 }, 1748 }; 1749 1750 static int sci_request_irq(struct sci_port *port) 1751 { 1752 struct uart_port *up = &port->port; 1753 int i, j, ret = 0; 1754 1755 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) { 1756 const struct sci_irq_desc *desc; 1757 int irq; 1758 1759 if (SCIx_IRQ_IS_MUXED(port)) { 1760 i = SCIx_MUX_IRQ; 1761 irq = up->irq; 1762 } else { 1763 irq = port->irqs[i]; 1764 1765 /* 1766 * Certain port types won't support all of the 1767 * available interrupt sources. 1768 */ 1769 if (unlikely(irq < 0)) 1770 continue; 1771 } 1772 1773 desc = sci_irq_desc + i; 1774 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s", 1775 dev_name(up->dev), desc->desc); 1776 if (!port->irqstr[j]) { 1777 ret = -ENOMEM; 1778 goto out_nomem; 1779 } 1780 1781 ret = request_irq(irq, desc->handler, up->irqflags, 1782 port->irqstr[j], port); 1783 if (unlikely(ret)) { 1784 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc); 1785 goto out_noirq; 1786 } 1787 } 1788 1789 return 0; 1790 1791 out_noirq: 1792 while (--i >= 0) 1793 free_irq(port->irqs[i], port); 1794 1795 out_nomem: 1796 while (--j >= 0) 1797 kfree(port->irqstr[j]); 1798 1799 return ret; 1800 } 1801 1802 static void sci_free_irq(struct sci_port *port) 1803 { 1804 int i; 1805 1806 /* 1807 * Intentionally in reverse order so we iterate over the muxed 1808 * IRQ first. 1809 */ 1810 for (i = 0; i < SCIx_NR_IRQS; i++) { 1811 int irq = port->irqs[i]; 1812 1813 /* 1814 * Certain port types won't support all of the available 1815 * interrupt sources. 1816 */ 1817 if (unlikely(irq < 0)) 1818 continue; 1819 1820 free_irq(port->irqs[i], port); 1821 kfree(port->irqstr[i]); 1822 1823 if (SCIx_IRQ_IS_MUXED(port)) { 1824 /* If there's only one IRQ, we're done. */ 1825 return; 1826 } 1827 } 1828 } 1829 1830 static unsigned int sci_tx_empty(struct uart_port *port) 1831 { 1832 unsigned short status = serial_port_in(port, SCxSR); 1833 unsigned short in_tx_fifo = sci_txfill(port); 1834 1835 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0; 1836 } 1837 1838 static void sci_set_rts(struct uart_port *port, bool state) 1839 { 1840 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1841 u16 data = serial_port_in(port, SCPDR); 1842 1843 /* Active low */ 1844 if (state) 1845 data &= ~SCPDR_RTSD; 1846 else 1847 data |= SCPDR_RTSD; 1848 serial_port_out(port, SCPDR, data); 1849 1850 /* RTS# is output */ 1851 serial_port_out(port, SCPCR, 1852 serial_port_in(port, SCPCR) | SCPCR_RTSC); 1853 } else if (sci_getreg(port, SCSPTR)->size) { 1854 u16 ctrl = serial_port_in(port, SCSPTR); 1855 1856 /* Active low */ 1857 if (state) 1858 ctrl &= ~SCSPTR_RTSDT; 1859 else 1860 ctrl |= SCSPTR_RTSDT; 1861 serial_port_out(port, SCSPTR, ctrl); 1862 } 1863 } 1864 1865 static bool sci_get_cts(struct uart_port *port) 1866 { 1867 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1868 /* Active low */ 1869 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD); 1870 } else if (sci_getreg(port, SCSPTR)->size) { 1871 /* Active low */ 1872 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT); 1873 } 1874 1875 return true; 1876 } 1877 1878 /* 1879 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally 1880 * CTS/RTS is supported in hardware by at least one port and controlled 1881 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently 1882 * handled via the ->init_pins() op, which is a bit of a one-way street, 1883 * lacking any ability to defer pin control -- this will later be 1884 * converted over to the GPIO framework). 1885 * 1886 * Other modes (such as loopback) are supported generically on certain 1887 * port types, but not others. For these it's sufficient to test for the 1888 * existence of the support register and simply ignore the port type. 1889 */ 1890 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) 1891 { 1892 struct sci_port *s = to_sci_port(port); 1893 1894 if (mctrl & TIOCM_LOOP) { 1895 const struct plat_sci_reg *reg; 1896 1897 /* 1898 * Standard loopback mode for SCFCR ports. 1899 */ 1900 reg = sci_getreg(port, SCFCR); 1901 if (reg->size) 1902 serial_port_out(port, SCFCR, 1903 serial_port_in(port, SCFCR) | 1904 SCFCR_LOOP); 1905 } 1906 1907 mctrl_gpio_set(s->gpios, mctrl); 1908 1909 if (!s->has_rtscts) 1910 return; 1911 1912 if (!(mctrl & TIOCM_RTS)) { 1913 /* Disable Auto RTS */ 1914 serial_port_out(port, SCFCR, 1915 serial_port_in(port, SCFCR) & ~SCFCR_MCE); 1916 1917 /* Clear RTS */ 1918 sci_set_rts(port, 0); 1919 } else if (s->autorts) { 1920 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1921 /* Enable RTS# pin function */ 1922 serial_port_out(port, SCPCR, 1923 serial_port_in(port, SCPCR) & ~SCPCR_RTSC); 1924 } 1925 1926 /* Enable Auto RTS */ 1927 serial_port_out(port, SCFCR, 1928 serial_port_in(port, SCFCR) | SCFCR_MCE); 1929 } else { 1930 /* Set RTS */ 1931 sci_set_rts(port, 1); 1932 } 1933 } 1934 1935 static unsigned int sci_get_mctrl(struct uart_port *port) 1936 { 1937 struct sci_port *s = to_sci_port(port); 1938 struct mctrl_gpios *gpios = s->gpios; 1939 unsigned int mctrl = 0; 1940 1941 mctrl_gpio_get(gpios, &mctrl); 1942 1943 /* 1944 * CTS/RTS is handled in hardware when supported, while nothing 1945 * else is wired up. 1946 */ 1947 if (s->autorts) { 1948 if (sci_get_cts(port)) 1949 mctrl |= TIOCM_CTS; 1950 } else if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS))) { 1951 mctrl |= TIOCM_CTS; 1952 } 1953 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR))) 1954 mctrl |= TIOCM_DSR; 1955 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD))) 1956 mctrl |= TIOCM_CAR; 1957 1958 return mctrl; 1959 } 1960 1961 static void sci_enable_ms(struct uart_port *port) 1962 { 1963 mctrl_gpio_enable_ms(to_sci_port(port)->gpios); 1964 } 1965 1966 static void sci_break_ctl(struct uart_port *port, int break_state) 1967 { 1968 unsigned short scscr, scsptr; 1969 1970 /* check wheter the port has SCSPTR */ 1971 if (!sci_getreg(port, SCSPTR)->size) { 1972 /* 1973 * Not supported by hardware. Most parts couple break and rx 1974 * interrupts together, with break detection always enabled. 1975 */ 1976 return; 1977 } 1978 1979 scsptr = serial_port_in(port, SCSPTR); 1980 scscr = serial_port_in(port, SCSCR); 1981 1982 if (break_state == -1) { 1983 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT; 1984 scscr &= ~SCSCR_TE; 1985 } else { 1986 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO; 1987 scscr |= SCSCR_TE; 1988 } 1989 1990 serial_port_out(port, SCSPTR, scsptr); 1991 serial_port_out(port, SCSCR, scscr); 1992 } 1993 1994 static int sci_startup(struct uart_port *port) 1995 { 1996 struct sci_port *s = to_sci_port(port); 1997 int ret; 1998 1999 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 2000 2001 sci_request_dma(port); 2002 2003 ret = sci_request_irq(s); 2004 if (unlikely(ret < 0)) { 2005 sci_free_dma(port); 2006 return ret; 2007 } 2008 2009 return 0; 2010 } 2011 2012 static void sci_shutdown(struct uart_port *port) 2013 { 2014 struct sci_port *s = to_sci_port(port); 2015 unsigned long flags; 2016 u16 scr; 2017 2018 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 2019 2020 s->autorts = false; 2021 mctrl_gpio_disable_ms(to_sci_port(port)->gpios); 2022 2023 spin_lock_irqsave(&port->lock, flags); 2024 sci_stop_rx(port); 2025 sci_stop_tx(port); 2026 /* Stop RX and TX, disable related interrupts, keep clock source */ 2027 scr = serial_port_in(port, SCSCR); 2028 serial_port_out(port, SCSCR, scr & (SCSCR_CKE1 | SCSCR_CKE0)); 2029 spin_unlock_irqrestore(&port->lock, flags); 2030 2031 #ifdef CONFIG_SERIAL_SH_SCI_DMA 2032 if (s->chan_rx) { 2033 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__, 2034 port->line); 2035 del_timer_sync(&s->rx_timer); 2036 } 2037 #endif 2038 2039 sci_free_irq(s); 2040 sci_free_dma(port); 2041 } 2042 2043 static int sci_sck_calc(struct sci_port *s, unsigned int bps, 2044 unsigned int *srr) 2045 { 2046 unsigned long freq = s->clk_rates[SCI_SCK]; 2047 int err, min_err = INT_MAX; 2048 unsigned int sr; 2049 2050 if (s->port.type != PORT_HSCIF) 2051 freq *= 2; 2052 2053 for_each_sr(sr, s) { 2054 err = DIV_ROUND_CLOSEST(freq, sr) - bps; 2055 if (abs(err) >= abs(min_err)) 2056 continue; 2057 2058 min_err = err; 2059 *srr = sr - 1; 2060 2061 if (!err) 2062 break; 2063 } 2064 2065 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err, 2066 *srr + 1); 2067 return min_err; 2068 } 2069 2070 static int sci_brg_calc(struct sci_port *s, unsigned int bps, 2071 unsigned long freq, unsigned int *dlr, 2072 unsigned int *srr) 2073 { 2074 int err, min_err = INT_MAX; 2075 unsigned int sr, dl; 2076 2077 if (s->port.type != PORT_HSCIF) 2078 freq *= 2; 2079 2080 for_each_sr(sr, s) { 2081 dl = DIV_ROUND_CLOSEST(freq, sr * bps); 2082 dl = clamp(dl, 1U, 65535U); 2083 2084 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps; 2085 if (abs(err) >= abs(min_err)) 2086 continue; 2087 2088 min_err = err; 2089 *dlr = dl; 2090 *srr = sr - 1; 2091 2092 if (!err) 2093 break; 2094 } 2095 2096 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps, 2097 min_err, *dlr, *srr + 1); 2098 return min_err; 2099 } 2100 2101 /* calculate sample rate, BRR, and clock select */ 2102 static int sci_scbrr_calc(struct sci_port *s, unsigned int bps, 2103 unsigned int *brr, unsigned int *srr, 2104 unsigned int *cks) 2105 { 2106 unsigned long freq = s->clk_rates[SCI_FCK]; 2107 unsigned int sr, br, prediv, scrate, c; 2108 int err, min_err = INT_MAX; 2109 2110 if (s->port.type != PORT_HSCIF) 2111 freq *= 2; 2112 2113 /* 2114 * Find the combination of sample rate and clock select with the 2115 * smallest deviation from the desired baud rate. 2116 * Prefer high sample rates to maximise the receive margin. 2117 * 2118 * M: Receive margin (%) 2119 * N: Ratio of bit rate to clock (N = sampling rate) 2120 * D: Clock duty (D = 0 to 1.0) 2121 * L: Frame length (L = 9 to 12) 2122 * F: Absolute value of clock frequency deviation 2123 * 2124 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) - 2125 * (|D - 0.5| / N * (1 + F))| 2126 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation. 2127 */ 2128 for_each_sr(sr, s) { 2129 for (c = 0; c <= 3; c++) { 2130 /* integerized formulas from HSCIF documentation */ 2131 prediv = sr * (1 << (2 * c + 1)); 2132 2133 /* 2134 * We need to calculate: 2135 * 2136 * br = freq / (prediv * bps) clamped to [1..256] 2137 * err = freq / (br * prediv) - bps 2138 * 2139 * Watch out for overflow when calculating the desired 2140 * sampling clock rate! 2141 */ 2142 if (bps > UINT_MAX / prediv) 2143 break; 2144 2145 scrate = prediv * bps; 2146 br = DIV_ROUND_CLOSEST(freq, scrate); 2147 br = clamp(br, 1U, 256U); 2148 2149 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps; 2150 if (abs(err) >= abs(min_err)) 2151 continue; 2152 2153 min_err = err; 2154 *brr = br - 1; 2155 *srr = sr - 1; 2156 *cks = c; 2157 2158 if (!err) 2159 goto found; 2160 } 2161 } 2162 2163 found: 2164 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps, 2165 min_err, *brr, *srr + 1, *cks); 2166 return min_err; 2167 } 2168 2169 static void sci_reset(struct uart_port *port) 2170 { 2171 const struct plat_sci_reg *reg; 2172 unsigned int status; 2173 struct sci_port *s = to_sci_port(port); 2174 2175 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */ 2176 2177 reg = sci_getreg(port, SCFCR); 2178 if (reg->size) 2179 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); 2180 2181 sci_clear_SCxSR(port, 2182 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) & 2183 SCxSR_BREAK_CLEAR(port)); 2184 if (sci_getreg(port, SCLSR)->size) { 2185 status = serial_port_in(port, SCLSR); 2186 status &= ~(SCLSR_TO | SCLSR_ORER); 2187 serial_port_out(port, SCLSR, status); 2188 } 2189 2190 if (s->rx_trigger > 1) { 2191 if (s->rx_fifo_timeout) { 2192 scif_set_rtrg(port, 1); 2193 setup_timer(&s->rx_fifo_timer, rx_fifo_timer_fn, 2194 (unsigned long)s); 2195 } else { 2196 if (port->type == PORT_SCIFA || 2197 port->type == PORT_SCIFB) 2198 scif_set_rtrg(port, 1); 2199 else 2200 scif_set_rtrg(port, s->rx_trigger); 2201 } 2202 } 2203 } 2204 2205 static void sci_set_termios(struct uart_port *port, struct ktermios *termios, 2206 struct ktermios *old) 2207 { 2208 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits; 2209 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0; 2210 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0; 2211 struct sci_port *s = to_sci_port(port); 2212 const struct plat_sci_reg *reg; 2213 int min_err = INT_MAX, err; 2214 unsigned long max_freq = 0; 2215 int best_clk = -1; 2216 2217 if ((termios->c_cflag & CSIZE) == CS7) 2218 smr_val |= SCSMR_CHR; 2219 if (termios->c_cflag & PARENB) 2220 smr_val |= SCSMR_PE; 2221 if (termios->c_cflag & PARODD) 2222 smr_val |= SCSMR_PE | SCSMR_ODD; 2223 if (termios->c_cflag & CSTOPB) 2224 smr_val |= SCSMR_STOP; 2225 2226 /* 2227 * earlyprintk comes here early on with port->uartclk set to zero. 2228 * the clock framework is not up and running at this point so here 2229 * we assume that 115200 is the maximum baud rate. please note that 2230 * the baud rate is not programmed during earlyprintk - it is assumed 2231 * that the previous boot loader has enabled required clocks and 2232 * setup the baud rate generator hardware for us already. 2233 */ 2234 if (!port->uartclk) { 2235 baud = uart_get_baud_rate(port, termios, old, 0, 115200); 2236 goto done; 2237 } 2238 2239 for (i = 0; i < SCI_NUM_CLKS; i++) 2240 max_freq = max(max_freq, s->clk_rates[i]); 2241 2242 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s)); 2243 if (!baud) 2244 goto done; 2245 2246 /* 2247 * There can be multiple sources for the sampling clock. Find the one 2248 * that gives us the smallest deviation from the desired baud rate. 2249 */ 2250 2251 /* Optional Undivided External Clock */ 2252 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA && 2253 port->type != PORT_SCIFB) { 2254 err = sci_sck_calc(s, baud, &srr1); 2255 if (abs(err) < abs(min_err)) { 2256 best_clk = SCI_SCK; 2257 scr_val = SCSCR_CKE1; 2258 sccks = SCCKS_CKS; 2259 min_err = err; 2260 srr = srr1; 2261 if (!err) 2262 goto done; 2263 } 2264 } 2265 2266 /* Optional BRG Frequency Divided External Clock */ 2267 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) { 2268 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1, 2269 &srr1); 2270 if (abs(err) < abs(min_err)) { 2271 best_clk = SCI_SCIF_CLK; 2272 scr_val = SCSCR_CKE1; 2273 sccks = 0; 2274 min_err = err; 2275 dl = dl1; 2276 srr = srr1; 2277 if (!err) 2278 goto done; 2279 } 2280 } 2281 2282 /* Optional BRG Frequency Divided Internal Clock */ 2283 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) { 2284 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1, 2285 &srr1); 2286 if (abs(err) < abs(min_err)) { 2287 best_clk = SCI_BRG_INT; 2288 scr_val = SCSCR_CKE1; 2289 sccks = SCCKS_XIN; 2290 min_err = err; 2291 dl = dl1; 2292 srr = srr1; 2293 if (!min_err) 2294 goto done; 2295 } 2296 } 2297 2298 /* Divided Functional Clock using standard Bit Rate Register */ 2299 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1); 2300 if (abs(err) < abs(min_err)) { 2301 best_clk = SCI_FCK; 2302 scr_val = 0; 2303 min_err = err; 2304 brr = brr1; 2305 srr = srr1; 2306 cks = cks1; 2307 } 2308 2309 done: 2310 if (best_clk >= 0) 2311 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n", 2312 s->clks[best_clk], baud, min_err); 2313 2314 sci_port_enable(s); 2315 2316 /* 2317 * Program the optional External Baud Rate Generator (BRG) first. 2318 * It controls the mux to select (H)SCK or frequency divided clock. 2319 */ 2320 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) { 2321 serial_port_out(port, SCDL, dl); 2322 serial_port_out(port, SCCKS, sccks); 2323 } 2324 2325 sci_reset(port); 2326 2327 uart_update_timeout(port, termios->c_cflag, baud); 2328 2329 if (best_clk >= 0) { 2330 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 2331 switch (srr + 1) { 2332 case 5: smr_val |= SCSMR_SRC_5; break; 2333 case 7: smr_val |= SCSMR_SRC_7; break; 2334 case 11: smr_val |= SCSMR_SRC_11; break; 2335 case 13: smr_val |= SCSMR_SRC_13; break; 2336 case 16: smr_val |= SCSMR_SRC_16; break; 2337 case 17: smr_val |= SCSMR_SRC_17; break; 2338 case 19: smr_val |= SCSMR_SRC_19; break; 2339 case 27: smr_val |= SCSMR_SRC_27; break; 2340 } 2341 smr_val |= cks; 2342 dev_dbg(port->dev, 2343 "SCR 0x%x SMR 0x%x BRR %u CKS 0x%x DL %u SRR %u\n", 2344 scr_val, smr_val, brr, sccks, dl, srr); 2345 serial_port_out(port, SCSCR, scr_val); 2346 serial_port_out(port, SCSMR, smr_val); 2347 serial_port_out(port, SCBRR, brr); 2348 if (sci_getreg(port, HSSRR)->size) 2349 serial_port_out(port, HSSRR, srr | HSCIF_SRE); 2350 2351 /* Wait one bit interval */ 2352 udelay((1000000 + (baud - 1)) / baud); 2353 } else { 2354 /* Don't touch the bit rate configuration */ 2355 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0); 2356 smr_val |= serial_port_in(port, SCSMR) & 2357 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS); 2358 dev_dbg(port->dev, "SCR 0x%x SMR 0x%x\n", scr_val, smr_val); 2359 serial_port_out(port, SCSCR, scr_val); 2360 serial_port_out(port, SCSMR, smr_val); 2361 } 2362 2363 sci_init_pins(port, termios->c_cflag); 2364 2365 port->status &= ~UPSTAT_AUTOCTS; 2366 s->autorts = false; 2367 reg = sci_getreg(port, SCFCR); 2368 if (reg->size) { 2369 unsigned short ctrl = serial_port_in(port, SCFCR); 2370 2371 if ((port->flags & UPF_HARD_FLOW) && 2372 (termios->c_cflag & CRTSCTS)) { 2373 /* There is no CTS interrupt to restart the hardware */ 2374 port->status |= UPSTAT_AUTOCTS; 2375 /* MCE is enabled when RTS is raised */ 2376 s->autorts = true; 2377 } 2378 2379 /* 2380 * As we've done a sci_reset() above, ensure we don't 2381 * interfere with the FIFOs while toggling MCE. As the 2382 * reset values could still be set, simply mask them out. 2383 */ 2384 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST); 2385 2386 serial_port_out(port, SCFCR, ctrl); 2387 } 2388 if (port->flags & UPF_HARD_FLOW) { 2389 /* Refresh (Auto) RTS */ 2390 sci_set_mctrl(port, port->mctrl); 2391 } 2392 2393 scr_val |= SCSCR_RE | SCSCR_TE | 2394 (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)); 2395 dev_dbg(port->dev, "SCSCR 0x%x\n", scr_val); 2396 serial_port_out(port, SCSCR, scr_val); 2397 if ((srr + 1 == 5) && 2398 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) { 2399 /* 2400 * In asynchronous mode, when the sampling rate is 1/5, first 2401 * received data may become invalid on some SCIFA and SCIFB. 2402 * To avoid this problem wait more than 1 serial data time (1 2403 * bit time x serial data number) after setting SCSCR.RE = 1. 2404 */ 2405 udelay(DIV_ROUND_UP(10 * 1000000, baud)); 2406 } 2407 2408 /* 2409 * Calculate delay for 2 DMA buffers (4 FIFO). 2410 * See serial_core.c::uart_update_timeout(). 2411 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above 2412 * function calculates 1 jiffie for the data plus 5 jiffies for the 2413 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA 2414 * buffers (4 FIFO sizes), but when performing a faster transfer, the 2415 * value obtained by this formula is too small. Therefore, if the value 2416 * is smaller than 20ms, use 20ms as the timeout value for DMA. 2417 */ 2418 /* byte size and parity */ 2419 switch (termios->c_cflag & CSIZE) { 2420 case CS5: 2421 bits = 7; 2422 break; 2423 case CS6: 2424 bits = 8; 2425 break; 2426 case CS7: 2427 bits = 9; 2428 break; 2429 default: 2430 bits = 10; 2431 break; 2432 } 2433 2434 if (termios->c_cflag & CSTOPB) 2435 bits++; 2436 if (termios->c_cflag & PARENB) 2437 bits++; 2438 2439 s->rx_frame = (100 * bits * HZ) / (baud / 10); 2440 #ifdef CONFIG_SERIAL_SH_SCI_DMA 2441 s->rx_timeout = DIV_ROUND_UP(s->buf_len_rx * 2 * s->rx_frame, 1000); 2442 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n", 2443 s->rx_timeout * 1000 / HZ, port->timeout); 2444 if (s->rx_timeout < msecs_to_jiffies(20)) 2445 s->rx_timeout = msecs_to_jiffies(20); 2446 #endif 2447 2448 if ((termios->c_cflag & CREAD) != 0) 2449 sci_start_rx(port); 2450 2451 sci_port_disable(s); 2452 2453 if (UART_ENABLE_MS(port, termios->c_cflag)) 2454 sci_enable_ms(port); 2455 } 2456 2457 static void sci_pm(struct uart_port *port, unsigned int state, 2458 unsigned int oldstate) 2459 { 2460 struct sci_port *sci_port = to_sci_port(port); 2461 2462 switch (state) { 2463 case UART_PM_STATE_OFF: 2464 sci_port_disable(sci_port); 2465 break; 2466 default: 2467 sci_port_enable(sci_port); 2468 break; 2469 } 2470 } 2471 2472 static const char *sci_type(struct uart_port *port) 2473 { 2474 switch (port->type) { 2475 case PORT_IRDA: 2476 return "irda"; 2477 case PORT_SCI: 2478 return "sci"; 2479 case PORT_SCIF: 2480 return "scif"; 2481 case PORT_SCIFA: 2482 return "scifa"; 2483 case PORT_SCIFB: 2484 return "scifb"; 2485 case PORT_HSCIF: 2486 return "hscif"; 2487 } 2488 2489 return NULL; 2490 } 2491 2492 static int sci_remap_port(struct uart_port *port) 2493 { 2494 struct sci_port *sport = to_sci_port(port); 2495 2496 /* 2497 * Nothing to do if there's already an established membase. 2498 */ 2499 if (port->membase) 2500 return 0; 2501 2502 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { 2503 port->membase = ioremap_nocache(port->mapbase, sport->reg_size); 2504 if (unlikely(!port->membase)) { 2505 dev_err(port->dev, "can't remap port#%d\n", port->line); 2506 return -ENXIO; 2507 } 2508 } else { 2509 /* 2510 * For the simple (and majority of) cases where we don't 2511 * need to do any remapping, just cast the cookie 2512 * directly. 2513 */ 2514 port->membase = (void __iomem *)(uintptr_t)port->mapbase; 2515 } 2516 2517 return 0; 2518 } 2519 2520 static void sci_release_port(struct uart_port *port) 2521 { 2522 struct sci_port *sport = to_sci_port(port); 2523 2524 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { 2525 iounmap(port->membase); 2526 port->membase = NULL; 2527 } 2528 2529 release_mem_region(port->mapbase, sport->reg_size); 2530 } 2531 2532 static int sci_request_port(struct uart_port *port) 2533 { 2534 struct resource *res; 2535 struct sci_port *sport = to_sci_port(port); 2536 int ret; 2537 2538 res = request_mem_region(port->mapbase, sport->reg_size, 2539 dev_name(port->dev)); 2540 if (unlikely(res == NULL)) { 2541 dev_err(port->dev, "request_mem_region failed."); 2542 return -EBUSY; 2543 } 2544 2545 ret = sci_remap_port(port); 2546 if (unlikely(ret != 0)) { 2547 release_resource(res); 2548 return ret; 2549 } 2550 2551 return 0; 2552 } 2553 2554 static void sci_config_port(struct uart_port *port, int flags) 2555 { 2556 if (flags & UART_CONFIG_TYPE) { 2557 struct sci_port *sport = to_sci_port(port); 2558 2559 port->type = sport->cfg->type; 2560 sci_request_port(port); 2561 } 2562 } 2563 2564 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser) 2565 { 2566 if (ser->baud_base < 2400) 2567 /* No paper tape reader for Mitch.. */ 2568 return -EINVAL; 2569 2570 return 0; 2571 } 2572 2573 static const struct uart_ops sci_uart_ops = { 2574 .tx_empty = sci_tx_empty, 2575 .set_mctrl = sci_set_mctrl, 2576 .get_mctrl = sci_get_mctrl, 2577 .start_tx = sci_start_tx, 2578 .stop_tx = sci_stop_tx, 2579 .stop_rx = sci_stop_rx, 2580 .enable_ms = sci_enable_ms, 2581 .break_ctl = sci_break_ctl, 2582 .startup = sci_startup, 2583 .shutdown = sci_shutdown, 2584 .set_termios = sci_set_termios, 2585 .pm = sci_pm, 2586 .type = sci_type, 2587 .release_port = sci_release_port, 2588 .request_port = sci_request_port, 2589 .config_port = sci_config_port, 2590 .verify_port = sci_verify_port, 2591 #ifdef CONFIG_CONSOLE_POLL 2592 .poll_get_char = sci_poll_get_char, 2593 .poll_put_char = sci_poll_put_char, 2594 #endif 2595 }; 2596 2597 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev) 2598 { 2599 const char *clk_names[] = { 2600 [SCI_FCK] = "fck", 2601 [SCI_SCK] = "sck", 2602 [SCI_BRG_INT] = "brg_int", 2603 [SCI_SCIF_CLK] = "scif_clk", 2604 }; 2605 struct clk *clk; 2606 unsigned int i; 2607 2608 if (sci_port->cfg->type == PORT_HSCIF) 2609 clk_names[SCI_SCK] = "hsck"; 2610 2611 for (i = 0; i < SCI_NUM_CLKS; i++) { 2612 clk = devm_clk_get(dev, clk_names[i]); 2613 if (PTR_ERR(clk) == -EPROBE_DEFER) 2614 return -EPROBE_DEFER; 2615 2616 if (IS_ERR(clk) && i == SCI_FCK) { 2617 /* 2618 * "fck" used to be called "sci_ick", and we need to 2619 * maintain DT backward compatibility. 2620 */ 2621 clk = devm_clk_get(dev, "sci_ick"); 2622 if (PTR_ERR(clk) == -EPROBE_DEFER) 2623 return -EPROBE_DEFER; 2624 2625 if (!IS_ERR(clk)) 2626 goto found; 2627 2628 /* 2629 * Not all SH platforms declare a clock lookup entry 2630 * for SCI devices, in which case we need to get the 2631 * global "peripheral_clk" clock. 2632 */ 2633 clk = devm_clk_get(dev, "peripheral_clk"); 2634 if (!IS_ERR(clk)) 2635 goto found; 2636 2637 dev_err(dev, "failed to get %s (%ld)\n", clk_names[i], 2638 PTR_ERR(clk)); 2639 return PTR_ERR(clk); 2640 } 2641 2642 found: 2643 if (IS_ERR(clk)) 2644 dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i], 2645 PTR_ERR(clk)); 2646 else 2647 dev_dbg(dev, "clk %s is %pC rate %pCr\n", clk_names[i], 2648 clk, clk); 2649 sci_port->clks[i] = IS_ERR(clk) ? NULL : clk; 2650 } 2651 return 0; 2652 } 2653 2654 static const struct sci_port_params * 2655 sci_probe_regmap(const struct plat_sci_port *cfg) 2656 { 2657 unsigned int regtype; 2658 2659 if (cfg->regtype != SCIx_PROBE_REGTYPE) 2660 return &sci_port_params[cfg->regtype]; 2661 2662 switch (cfg->type) { 2663 case PORT_SCI: 2664 regtype = SCIx_SCI_REGTYPE; 2665 break; 2666 case PORT_IRDA: 2667 regtype = SCIx_IRDA_REGTYPE; 2668 break; 2669 case PORT_SCIFA: 2670 regtype = SCIx_SCIFA_REGTYPE; 2671 break; 2672 case PORT_SCIFB: 2673 regtype = SCIx_SCIFB_REGTYPE; 2674 break; 2675 case PORT_SCIF: 2676 /* 2677 * The SH-4 is a bit of a misnomer here, although that's 2678 * where this particular port layout originated. This 2679 * configuration (or some slight variation thereof) 2680 * remains the dominant model for all SCIFs. 2681 */ 2682 regtype = SCIx_SH4_SCIF_REGTYPE; 2683 break; 2684 case PORT_HSCIF: 2685 regtype = SCIx_HSCIF_REGTYPE; 2686 break; 2687 default: 2688 pr_err("Can't probe register map for given port\n"); 2689 return NULL; 2690 } 2691 2692 return &sci_port_params[regtype]; 2693 } 2694 2695 static int sci_init_single(struct platform_device *dev, 2696 struct sci_port *sci_port, unsigned int index, 2697 const struct plat_sci_port *p, bool early) 2698 { 2699 struct uart_port *port = &sci_port->port; 2700 const struct resource *res; 2701 unsigned int i; 2702 int ret; 2703 2704 sci_port->cfg = p; 2705 2706 port->ops = &sci_uart_ops; 2707 port->iotype = UPIO_MEM; 2708 port->line = index; 2709 2710 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 2711 if (res == NULL) 2712 return -ENOMEM; 2713 2714 port->mapbase = res->start; 2715 sci_port->reg_size = resource_size(res); 2716 2717 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) 2718 sci_port->irqs[i] = platform_get_irq(dev, i); 2719 2720 /* The SCI generates several interrupts. They can be muxed together or 2721 * connected to different interrupt lines. In the muxed case only one 2722 * interrupt resource is specified. In the non-muxed case three or four 2723 * interrupt resources are specified, as the BRI interrupt is optional. 2724 */ 2725 if (sci_port->irqs[0] < 0) 2726 return -ENXIO; 2727 2728 if (sci_port->irqs[1] < 0) { 2729 sci_port->irqs[1] = sci_port->irqs[0]; 2730 sci_port->irqs[2] = sci_port->irqs[0]; 2731 sci_port->irqs[3] = sci_port->irqs[0]; 2732 } 2733 2734 sci_port->params = sci_probe_regmap(p); 2735 if (unlikely(sci_port->params == NULL)) 2736 return -EINVAL; 2737 2738 switch (p->type) { 2739 case PORT_SCIFB: 2740 sci_port->rx_trigger = 48; 2741 break; 2742 case PORT_HSCIF: 2743 sci_port->rx_trigger = 64; 2744 break; 2745 case PORT_SCIFA: 2746 sci_port->rx_trigger = 32; 2747 break; 2748 case PORT_SCIF: 2749 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) 2750 /* RX triggering not implemented for this IP */ 2751 sci_port->rx_trigger = 1; 2752 else 2753 sci_port->rx_trigger = 8; 2754 break; 2755 default: 2756 sci_port->rx_trigger = 1; 2757 break; 2758 } 2759 2760 sci_port->rx_fifo_timeout = 0; 2761 2762 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't 2763 * match the SoC datasheet, this should be investigated. Let platform 2764 * data override the sampling rate for now. 2765 */ 2766 sci_port->sampling_rate_mask = p->sampling_rate 2767 ? SCI_SR(p->sampling_rate) 2768 : sci_port->params->sampling_rate_mask; 2769 2770 if (!early) { 2771 ret = sci_init_clocks(sci_port, &dev->dev); 2772 if (ret < 0) 2773 return ret; 2774 2775 port->dev = &dev->dev; 2776 2777 pm_runtime_enable(&dev->dev); 2778 } 2779 2780 port->type = p->type; 2781 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags; 2782 port->fifosize = sci_port->params->fifosize; 2783 2784 if (port->type == PORT_SCI) { 2785 if (sci_port->reg_size >= 0x20) 2786 port->regshift = 2; 2787 else 2788 port->regshift = 1; 2789 } 2790 2791 /* 2792 * The UART port needs an IRQ value, so we peg this to the RX IRQ 2793 * for the multi-IRQ ports, which is where we are primarily 2794 * concerned with the shutdown path synchronization. 2795 * 2796 * For the muxed case there's nothing more to do. 2797 */ 2798 port->irq = sci_port->irqs[SCIx_RXI_IRQ]; 2799 port->irqflags = 0; 2800 2801 port->serial_in = sci_serial_in; 2802 port->serial_out = sci_serial_out; 2803 2804 return 0; 2805 } 2806 2807 static void sci_cleanup_single(struct sci_port *port) 2808 { 2809 pm_runtime_disable(port->port.dev); 2810 } 2811 2812 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ 2813 defined(CONFIG_SERIAL_SH_SCI_EARLYCON) 2814 static void serial_console_putchar(struct uart_port *port, int ch) 2815 { 2816 sci_poll_put_char(port, ch); 2817 } 2818 2819 /* 2820 * Print a string to the serial port trying not to disturb 2821 * any possible real use of the port... 2822 */ 2823 static void serial_console_write(struct console *co, const char *s, 2824 unsigned count) 2825 { 2826 struct sci_port *sci_port = &sci_ports[co->index]; 2827 struct uart_port *port = &sci_port->port; 2828 unsigned short bits, ctrl, ctrl_temp; 2829 unsigned long flags; 2830 int locked = 1; 2831 2832 local_irq_save(flags); 2833 #if defined(SUPPORT_SYSRQ) 2834 if (port->sysrq) 2835 locked = 0; 2836 else 2837 #endif 2838 if (oops_in_progress) 2839 locked = spin_trylock(&port->lock); 2840 else 2841 spin_lock(&port->lock); 2842 2843 /* first save SCSCR then disable interrupts, keep clock source */ 2844 ctrl = serial_port_in(port, SCSCR); 2845 ctrl_temp = SCSCR_RE | SCSCR_TE | 2846 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) | 2847 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0)); 2848 serial_port_out(port, SCSCR, ctrl_temp); 2849 2850 uart_console_write(port, s, count, serial_console_putchar); 2851 2852 /* wait until fifo is empty and last bit has been transmitted */ 2853 bits = SCxSR_TDxE(port) | SCxSR_TEND(port); 2854 while ((serial_port_in(port, SCxSR) & bits) != bits) 2855 cpu_relax(); 2856 2857 /* restore the SCSCR */ 2858 serial_port_out(port, SCSCR, ctrl); 2859 2860 if (locked) 2861 spin_unlock(&port->lock); 2862 local_irq_restore(flags); 2863 } 2864 2865 static int serial_console_setup(struct console *co, char *options) 2866 { 2867 struct sci_port *sci_port; 2868 struct uart_port *port; 2869 int baud = 115200; 2870 int bits = 8; 2871 int parity = 'n'; 2872 int flow = 'n'; 2873 int ret; 2874 2875 /* 2876 * Refuse to handle any bogus ports. 2877 */ 2878 if (co->index < 0 || co->index >= SCI_NPORTS) 2879 return -ENODEV; 2880 2881 sci_port = &sci_ports[co->index]; 2882 port = &sci_port->port; 2883 2884 /* 2885 * Refuse to handle uninitialized ports. 2886 */ 2887 if (!port->ops) 2888 return -ENODEV; 2889 2890 ret = sci_remap_port(port); 2891 if (unlikely(ret != 0)) 2892 return ret; 2893 2894 if (options) 2895 uart_parse_options(options, &baud, &parity, &bits, &flow); 2896 2897 return uart_set_options(port, co, baud, parity, bits, flow); 2898 } 2899 2900 static struct console serial_console = { 2901 .name = "ttySC", 2902 .device = uart_console_device, 2903 .write = serial_console_write, 2904 .setup = serial_console_setup, 2905 .flags = CON_PRINTBUFFER, 2906 .index = -1, 2907 .data = &sci_uart_driver, 2908 }; 2909 2910 static struct console early_serial_console = { 2911 .name = "early_ttySC", 2912 .write = serial_console_write, 2913 .flags = CON_PRINTBUFFER, 2914 .index = -1, 2915 }; 2916 2917 static char early_serial_buf[32]; 2918 2919 static int sci_probe_earlyprintk(struct platform_device *pdev) 2920 { 2921 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev); 2922 2923 if (early_serial_console.data) 2924 return -EEXIST; 2925 2926 early_serial_console.index = pdev->id; 2927 2928 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true); 2929 2930 serial_console_setup(&early_serial_console, early_serial_buf); 2931 2932 if (!strstr(early_serial_buf, "keep")) 2933 early_serial_console.flags |= CON_BOOT; 2934 2935 register_console(&early_serial_console); 2936 return 0; 2937 } 2938 2939 #define SCI_CONSOLE (&serial_console) 2940 2941 #else 2942 static inline int sci_probe_earlyprintk(struct platform_device *pdev) 2943 { 2944 return -EINVAL; 2945 } 2946 2947 #define SCI_CONSOLE NULL 2948 2949 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */ 2950 2951 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized"; 2952 2953 static struct uart_driver sci_uart_driver = { 2954 .owner = THIS_MODULE, 2955 .driver_name = "sci", 2956 .dev_name = "ttySC", 2957 .major = SCI_MAJOR, 2958 .minor = SCI_MINOR_START, 2959 .nr = SCI_NPORTS, 2960 .cons = SCI_CONSOLE, 2961 }; 2962 2963 static int sci_remove(struct platform_device *dev) 2964 { 2965 struct sci_port *port = platform_get_drvdata(dev); 2966 2967 uart_remove_one_port(&sci_uart_driver, &port->port); 2968 2969 sci_cleanup_single(port); 2970 2971 if (port->port.fifosize > 1) { 2972 sysfs_remove_file(&dev->dev.kobj, 2973 &dev_attr_rx_fifo_trigger.attr); 2974 } 2975 if (port->port.type == PORT_SCIFA || port->port.type == PORT_SCIFB) { 2976 sysfs_remove_file(&dev->dev.kobj, 2977 &dev_attr_rx_fifo_timeout.attr); 2978 } 2979 2980 return 0; 2981 } 2982 2983 2984 #define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype)) 2985 #define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16) 2986 #define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff) 2987 2988 static const struct of_device_id of_sci_match[] = { 2989 /* SoC-specific types */ 2990 { 2991 .compatible = "renesas,scif-r7s72100", 2992 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE), 2993 }, 2994 /* Family-specific types */ 2995 { 2996 .compatible = "renesas,rcar-gen1-scif", 2997 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 2998 }, { 2999 .compatible = "renesas,rcar-gen2-scif", 3000 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3001 }, { 3002 .compatible = "renesas,rcar-gen3-scif", 3003 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3004 }, 3005 /* Generic types */ 3006 { 3007 .compatible = "renesas,scif", 3008 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE), 3009 }, { 3010 .compatible = "renesas,scifa", 3011 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE), 3012 }, { 3013 .compatible = "renesas,scifb", 3014 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE), 3015 }, { 3016 .compatible = "renesas,hscif", 3017 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE), 3018 }, { 3019 .compatible = "renesas,sci", 3020 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE), 3021 }, { 3022 /* Terminator */ 3023 }, 3024 }; 3025 MODULE_DEVICE_TABLE(of, of_sci_match); 3026 3027 static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev, 3028 unsigned int *dev_id) 3029 { 3030 struct device_node *np = pdev->dev.of_node; 3031 const struct of_device_id *match; 3032 struct plat_sci_port *p; 3033 struct sci_port *sp; 3034 int id; 3035 3036 if (!IS_ENABLED(CONFIG_OF) || !np) 3037 return NULL; 3038 3039 match = of_match_node(of_sci_match, np); 3040 if (!match) 3041 return NULL; 3042 3043 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL); 3044 if (!p) 3045 return NULL; 3046 3047 /* Get the line number from the aliases node. */ 3048 id = of_alias_get_id(np, "serial"); 3049 if (id < 0) { 3050 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id); 3051 return NULL; 3052 } 3053 3054 sp = &sci_ports[id]; 3055 *dev_id = id; 3056 3057 p->type = SCI_OF_TYPE(match->data); 3058 p->regtype = SCI_OF_REGTYPE(match->data); 3059 3060 if (of_find_property(np, "uart-has-rtscts", NULL)) 3061 sp->has_rtscts = true; 3062 3063 return p; 3064 } 3065 3066 static int sci_probe_single(struct platform_device *dev, 3067 unsigned int index, 3068 struct plat_sci_port *p, 3069 struct sci_port *sciport) 3070 { 3071 int ret; 3072 3073 /* Sanity check */ 3074 if (unlikely(index >= SCI_NPORTS)) { 3075 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n", 3076 index+1, SCI_NPORTS); 3077 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n"); 3078 return -EINVAL; 3079 } 3080 3081 ret = sci_init_single(dev, sciport, index, p, false); 3082 if (ret) 3083 return ret; 3084 3085 sciport->gpios = mctrl_gpio_init(&sciport->port, 0); 3086 if (IS_ERR(sciport->gpios) && PTR_ERR(sciport->gpios) != -ENOSYS) 3087 return PTR_ERR(sciport->gpios); 3088 3089 if (sciport->has_rtscts) { 3090 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios, 3091 UART_GPIO_CTS)) || 3092 !IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios, 3093 UART_GPIO_RTS))) { 3094 dev_err(&dev->dev, "Conflicting RTS/CTS config\n"); 3095 return -EINVAL; 3096 } 3097 sciport->port.flags |= UPF_HARD_FLOW; 3098 } 3099 3100 ret = uart_add_one_port(&sci_uart_driver, &sciport->port); 3101 if (ret) { 3102 sci_cleanup_single(sciport); 3103 return ret; 3104 } 3105 3106 return 0; 3107 } 3108 3109 static int sci_probe(struct platform_device *dev) 3110 { 3111 struct plat_sci_port *p; 3112 struct sci_port *sp; 3113 unsigned int dev_id; 3114 int ret; 3115 3116 /* 3117 * If we've come here via earlyprintk initialization, head off to 3118 * the special early probe. We don't have sufficient device state 3119 * to make it beyond this yet. 3120 */ 3121 if (is_early_platform_device(dev)) 3122 return sci_probe_earlyprintk(dev); 3123 3124 if (dev->dev.of_node) { 3125 p = sci_parse_dt(dev, &dev_id); 3126 if (p == NULL) 3127 return -EINVAL; 3128 } else { 3129 p = dev->dev.platform_data; 3130 if (p == NULL) { 3131 dev_err(&dev->dev, "no platform data supplied\n"); 3132 return -EINVAL; 3133 } 3134 3135 dev_id = dev->id; 3136 } 3137 3138 sp = &sci_ports[dev_id]; 3139 platform_set_drvdata(dev, sp); 3140 3141 ret = sci_probe_single(dev, dev_id, p, sp); 3142 if (ret) 3143 return ret; 3144 3145 if (sp->port.fifosize > 1) { 3146 ret = sysfs_create_file(&dev->dev.kobj, 3147 &dev_attr_rx_fifo_trigger.attr); 3148 if (ret) 3149 return ret; 3150 } 3151 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB) { 3152 ret = sysfs_create_file(&dev->dev.kobj, 3153 &dev_attr_rx_fifo_timeout.attr); 3154 if (ret) { 3155 if (sp->port.fifosize > 1) { 3156 sysfs_remove_file(&dev->dev.kobj, 3157 &dev_attr_rx_fifo_trigger.attr); 3158 } 3159 return ret; 3160 } 3161 } 3162 3163 #ifdef CONFIG_SH_STANDARD_BIOS 3164 sh_bios_gdb_detach(); 3165 #endif 3166 3167 return 0; 3168 } 3169 3170 static __maybe_unused int sci_suspend(struct device *dev) 3171 { 3172 struct sci_port *sport = dev_get_drvdata(dev); 3173 3174 if (sport) 3175 uart_suspend_port(&sci_uart_driver, &sport->port); 3176 3177 return 0; 3178 } 3179 3180 static __maybe_unused int sci_resume(struct device *dev) 3181 { 3182 struct sci_port *sport = dev_get_drvdata(dev); 3183 3184 if (sport) 3185 uart_resume_port(&sci_uart_driver, &sport->port); 3186 3187 return 0; 3188 } 3189 3190 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume); 3191 3192 static struct platform_driver sci_driver = { 3193 .probe = sci_probe, 3194 .remove = sci_remove, 3195 .driver = { 3196 .name = "sh-sci", 3197 .pm = &sci_dev_pm_ops, 3198 .of_match_table = of_match_ptr(of_sci_match), 3199 }, 3200 }; 3201 3202 static int __init sci_init(void) 3203 { 3204 int ret; 3205 3206 pr_info("%s\n", banner); 3207 3208 ret = uart_register_driver(&sci_uart_driver); 3209 if (likely(ret == 0)) { 3210 ret = platform_driver_register(&sci_driver); 3211 if (unlikely(ret)) 3212 uart_unregister_driver(&sci_uart_driver); 3213 } 3214 3215 return ret; 3216 } 3217 3218 static void __exit sci_exit(void) 3219 { 3220 platform_driver_unregister(&sci_driver); 3221 uart_unregister_driver(&sci_uart_driver); 3222 } 3223 3224 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE 3225 early_platform_init_buffer("earlyprintk", &sci_driver, 3226 early_serial_buf, ARRAY_SIZE(early_serial_buf)); 3227 #endif 3228 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON 3229 static struct __init plat_sci_port port_cfg; 3230 3231 static int __init early_console_setup(struct earlycon_device *device, 3232 int type) 3233 { 3234 if (!device->port.membase) 3235 return -ENODEV; 3236 3237 device->port.serial_in = sci_serial_in; 3238 device->port.serial_out = sci_serial_out; 3239 device->port.type = type; 3240 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port)); 3241 port_cfg.type = type; 3242 sci_ports[0].cfg = &port_cfg; 3243 sci_ports[0].params = sci_probe_regmap(&port_cfg); 3244 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR); 3245 sci_serial_out(&sci_ports[0].port, SCSCR, 3246 SCSCR_RE | SCSCR_TE | port_cfg.scscr); 3247 3248 device->con->write = serial_console_write; 3249 return 0; 3250 } 3251 static int __init sci_early_console_setup(struct earlycon_device *device, 3252 const char *opt) 3253 { 3254 return early_console_setup(device, PORT_SCI); 3255 } 3256 static int __init scif_early_console_setup(struct earlycon_device *device, 3257 const char *opt) 3258 { 3259 return early_console_setup(device, PORT_SCIF); 3260 } 3261 static int __init scifa_early_console_setup(struct earlycon_device *device, 3262 const char *opt) 3263 { 3264 return early_console_setup(device, PORT_SCIFA); 3265 } 3266 static int __init scifb_early_console_setup(struct earlycon_device *device, 3267 const char *opt) 3268 { 3269 return early_console_setup(device, PORT_SCIFB); 3270 } 3271 static int __init hscif_early_console_setup(struct earlycon_device *device, 3272 const char *opt) 3273 { 3274 return early_console_setup(device, PORT_HSCIF); 3275 } 3276 3277 OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup); 3278 OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup); 3279 OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup); 3280 OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup); 3281 OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup); 3282 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */ 3283 3284 module_init(sci_init); 3285 module_exit(sci_exit); 3286 3287 MODULE_LICENSE("GPL"); 3288 MODULE_ALIAS("platform:sh-sci"); 3289 MODULE_AUTHOR("Paul Mundt"); 3290 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver"); 3291