1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) 4 * 5 * Copyright (C) 2002 - 2011 Paul Mundt 6 * Copyright (C) 2015 Glider bvba 7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007). 8 * 9 * based off of the old drivers/char/sh-sci.c by: 10 * 11 * Copyright (C) 1999, 2000 Niibe Yutaka 12 * Copyright (C) 2000 Sugioka Toshinobu 13 * Modified to support multiple serial ports. Stuart Menefy (May 2000). 14 * Modified to support SecureEdge. David McCullough (2002) 15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003). 16 * Removed SH7300 support (Jul 2007). 17 */ 18 #undef DEBUG 19 20 #include <linux/clk.h> 21 #include <linux/console.h> 22 #include <linux/ctype.h> 23 #include <linux/cpufreq.h> 24 #include <linux/delay.h> 25 #include <linux/dmaengine.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/err.h> 28 #include <linux/errno.h> 29 #include <linux/init.h> 30 #include <linux/interrupt.h> 31 #include <linux/ioport.h> 32 #include <linux/ktime.h> 33 #include <linux/major.h> 34 #include <linux/module.h> 35 #include <linux/mm.h> 36 #include <linux/of.h> 37 #include <linux/of_device.h> 38 #include <linux/platform_device.h> 39 #include <linux/pm_runtime.h> 40 #include <linux/scatterlist.h> 41 #include <linux/serial.h> 42 #include <linux/serial_sci.h> 43 #include <linux/sh_dma.h> 44 #include <linux/slab.h> 45 #include <linux/string.h> 46 #include <linux/sysrq.h> 47 #include <linux/timer.h> 48 #include <linux/tty.h> 49 #include <linux/tty_flip.h> 50 51 #ifdef CONFIG_SUPERH 52 #include <asm/sh_bios.h> 53 #include <asm/platform_early.h> 54 #endif 55 56 #include "serial_mctrl_gpio.h" 57 #include "sh-sci.h" 58 59 /* Offsets into the sci_port->irqs array */ 60 enum { 61 SCIx_ERI_IRQ, 62 SCIx_RXI_IRQ, 63 SCIx_TXI_IRQ, 64 SCIx_BRI_IRQ, 65 SCIx_DRI_IRQ, 66 SCIx_TEI_IRQ, 67 SCIx_NR_IRQS, 68 69 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */ 70 }; 71 72 #define SCIx_IRQ_IS_MUXED(port) \ 73 ((port)->irqs[SCIx_ERI_IRQ] == \ 74 (port)->irqs[SCIx_RXI_IRQ]) || \ 75 ((port)->irqs[SCIx_ERI_IRQ] && \ 76 ((port)->irqs[SCIx_RXI_IRQ] < 0)) 77 78 enum SCI_CLKS { 79 SCI_FCK, /* Functional Clock */ 80 SCI_SCK, /* Optional External Clock */ 81 SCI_BRG_INT, /* Optional BRG Internal Clock Source */ 82 SCI_SCIF_CLK, /* Optional BRG External Clock Source */ 83 SCI_NUM_CLKS 84 }; 85 86 /* Bit x set means sampling rate x + 1 is supported */ 87 #define SCI_SR(x) BIT((x) - 1) 88 #define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1) 89 90 #define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \ 91 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \ 92 SCI_SR(19) | SCI_SR(27) 93 94 #define min_sr(_port) ffs((_port)->sampling_rate_mask) 95 #define max_sr(_port) fls((_port)->sampling_rate_mask) 96 97 /* Iterate over all supported sampling rates, from high to low */ 98 #define for_each_sr(_sr, _port) \ 99 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \ 100 if ((_port)->sampling_rate_mask & SCI_SR((_sr))) 101 102 struct plat_sci_reg { 103 u8 offset, size; 104 }; 105 106 struct sci_port_params { 107 const struct plat_sci_reg regs[SCIx_NR_REGS]; 108 unsigned int fifosize; 109 unsigned int overrun_reg; 110 unsigned int overrun_mask; 111 unsigned int sampling_rate_mask; 112 unsigned int error_mask; 113 unsigned int error_clear; 114 }; 115 116 struct sci_port { 117 struct uart_port port; 118 119 /* Platform configuration */ 120 const struct sci_port_params *params; 121 const struct plat_sci_port *cfg; 122 unsigned int sampling_rate_mask; 123 resource_size_t reg_size; 124 struct mctrl_gpios *gpios; 125 126 /* Clocks */ 127 struct clk *clks[SCI_NUM_CLKS]; 128 unsigned long clk_rates[SCI_NUM_CLKS]; 129 130 int irqs[SCIx_NR_IRQS]; 131 char *irqstr[SCIx_NR_IRQS]; 132 133 struct dma_chan *chan_tx; 134 struct dma_chan *chan_rx; 135 136 #ifdef CONFIG_SERIAL_SH_SCI_DMA 137 struct dma_chan *chan_tx_saved; 138 struct dma_chan *chan_rx_saved; 139 dma_cookie_t cookie_tx; 140 dma_cookie_t cookie_rx[2]; 141 dma_cookie_t active_rx; 142 dma_addr_t tx_dma_addr; 143 unsigned int tx_dma_len; 144 struct scatterlist sg_rx[2]; 145 void *rx_buf[2]; 146 size_t buf_len_rx; 147 struct work_struct work_tx; 148 struct hrtimer rx_timer; 149 unsigned int rx_timeout; /* microseconds */ 150 #endif 151 unsigned int rx_frame; 152 int rx_trigger; 153 struct timer_list rx_fifo_timer; 154 int rx_fifo_timeout; 155 u16 hscif_tot; 156 157 bool has_rtscts; 158 bool autorts; 159 }; 160 161 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS 162 163 static struct sci_port sci_ports[SCI_NPORTS]; 164 static unsigned long sci_ports_in_use; 165 static struct uart_driver sci_uart_driver; 166 167 static inline struct sci_port * 168 to_sci_port(struct uart_port *uart) 169 { 170 return container_of(uart, struct sci_port, port); 171 } 172 173 static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { 174 /* 175 * Common SCI definitions, dependent on the port's regshift 176 * value. 177 */ 178 [SCIx_SCI_REGTYPE] = { 179 .regs = { 180 [SCSMR] = { 0x00, 8 }, 181 [SCBRR] = { 0x01, 8 }, 182 [SCSCR] = { 0x02, 8 }, 183 [SCxTDR] = { 0x03, 8 }, 184 [SCxSR] = { 0x04, 8 }, 185 [SCxRDR] = { 0x05, 8 }, 186 }, 187 .fifosize = 1, 188 .overrun_reg = SCxSR, 189 .overrun_mask = SCI_ORER, 190 .sampling_rate_mask = SCI_SR(32), 191 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, 192 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, 193 }, 194 195 /* 196 * Common definitions for legacy IrDA ports. 197 */ 198 [SCIx_IRDA_REGTYPE] = { 199 .regs = { 200 [SCSMR] = { 0x00, 8 }, 201 [SCBRR] = { 0x02, 8 }, 202 [SCSCR] = { 0x04, 8 }, 203 [SCxTDR] = { 0x06, 8 }, 204 [SCxSR] = { 0x08, 16 }, 205 [SCxRDR] = { 0x0a, 8 }, 206 [SCFCR] = { 0x0c, 8 }, 207 [SCFDR] = { 0x0e, 16 }, 208 }, 209 .fifosize = 1, 210 .overrun_reg = SCxSR, 211 .overrun_mask = SCI_ORER, 212 .sampling_rate_mask = SCI_SR(32), 213 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, 214 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, 215 }, 216 217 /* 218 * Common SCIFA definitions. 219 */ 220 [SCIx_SCIFA_REGTYPE] = { 221 .regs = { 222 [SCSMR] = { 0x00, 16 }, 223 [SCBRR] = { 0x04, 8 }, 224 [SCSCR] = { 0x08, 16 }, 225 [SCxTDR] = { 0x20, 8 }, 226 [SCxSR] = { 0x14, 16 }, 227 [SCxRDR] = { 0x24, 8 }, 228 [SCFCR] = { 0x18, 16 }, 229 [SCFDR] = { 0x1c, 16 }, 230 [SCPCR] = { 0x30, 16 }, 231 [SCPDR] = { 0x34, 16 }, 232 }, 233 .fifosize = 64, 234 .overrun_reg = SCxSR, 235 .overrun_mask = SCIFA_ORER, 236 .sampling_rate_mask = SCI_SR_SCIFAB, 237 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 238 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 239 }, 240 241 /* 242 * Common SCIFB definitions. 243 */ 244 [SCIx_SCIFB_REGTYPE] = { 245 .regs = { 246 [SCSMR] = { 0x00, 16 }, 247 [SCBRR] = { 0x04, 8 }, 248 [SCSCR] = { 0x08, 16 }, 249 [SCxTDR] = { 0x40, 8 }, 250 [SCxSR] = { 0x14, 16 }, 251 [SCxRDR] = { 0x60, 8 }, 252 [SCFCR] = { 0x18, 16 }, 253 [SCTFDR] = { 0x38, 16 }, 254 [SCRFDR] = { 0x3c, 16 }, 255 [SCPCR] = { 0x30, 16 }, 256 [SCPDR] = { 0x34, 16 }, 257 }, 258 .fifosize = 256, 259 .overrun_reg = SCxSR, 260 .overrun_mask = SCIFA_ORER, 261 .sampling_rate_mask = SCI_SR_SCIFAB, 262 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 263 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 264 }, 265 266 /* 267 * Common SH-2(A) SCIF definitions for ports with FIFO data 268 * count registers. 269 */ 270 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = { 271 .regs = { 272 [SCSMR] = { 0x00, 16 }, 273 [SCBRR] = { 0x04, 8 }, 274 [SCSCR] = { 0x08, 16 }, 275 [SCxTDR] = { 0x0c, 8 }, 276 [SCxSR] = { 0x10, 16 }, 277 [SCxRDR] = { 0x14, 8 }, 278 [SCFCR] = { 0x18, 16 }, 279 [SCFDR] = { 0x1c, 16 }, 280 [SCSPTR] = { 0x20, 16 }, 281 [SCLSR] = { 0x24, 16 }, 282 }, 283 .fifosize = 16, 284 .overrun_reg = SCLSR, 285 .overrun_mask = SCLSR_ORER, 286 .sampling_rate_mask = SCI_SR(32), 287 .error_mask = SCIF_DEFAULT_ERROR_MASK, 288 .error_clear = SCIF_ERROR_CLEAR, 289 }, 290 291 /* 292 * The "SCIFA" that is in RZ/T and RZ/A2. 293 * It looks like a normal SCIF with FIFO data, but with a 294 * compressed address space. Also, the break out of interrupts 295 * are different: ERI/BRI, RXI, TXI, TEI, DRI. 296 */ 297 [SCIx_RZ_SCIFA_REGTYPE] = { 298 .regs = { 299 [SCSMR] = { 0x00, 16 }, 300 [SCBRR] = { 0x02, 8 }, 301 [SCSCR] = { 0x04, 16 }, 302 [SCxTDR] = { 0x06, 8 }, 303 [SCxSR] = { 0x08, 16 }, 304 [SCxRDR] = { 0x0A, 8 }, 305 [SCFCR] = { 0x0C, 16 }, 306 [SCFDR] = { 0x0E, 16 }, 307 [SCSPTR] = { 0x10, 16 }, 308 [SCLSR] = { 0x12, 16 }, 309 }, 310 .fifosize = 16, 311 .overrun_reg = SCLSR, 312 .overrun_mask = SCLSR_ORER, 313 .sampling_rate_mask = SCI_SR(32), 314 .error_mask = SCIF_DEFAULT_ERROR_MASK, 315 .error_clear = SCIF_ERROR_CLEAR, 316 }, 317 318 /* 319 * Common SH-3 SCIF definitions. 320 */ 321 [SCIx_SH3_SCIF_REGTYPE] = { 322 .regs = { 323 [SCSMR] = { 0x00, 8 }, 324 [SCBRR] = { 0x02, 8 }, 325 [SCSCR] = { 0x04, 8 }, 326 [SCxTDR] = { 0x06, 8 }, 327 [SCxSR] = { 0x08, 16 }, 328 [SCxRDR] = { 0x0a, 8 }, 329 [SCFCR] = { 0x0c, 8 }, 330 [SCFDR] = { 0x0e, 16 }, 331 }, 332 .fifosize = 16, 333 .overrun_reg = SCLSR, 334 .overrun_mask = SCLSR_ORER, 335 .sampling_rate_mask = SCI_SR(32), 336 .error_mask = SCIF_DEFAULT_ERROR_MASK, 337 .error_clear = SCIF_ERROR_CLEAR, 338 }, 339 340 /* 341 * Common SH-4(A) SCIF(B) definitions. 342 */ 343 [SCIx_SH4_SCIF_REGTYPE] = { 344 .regs = { 345 [SCSMR] = { 0x00, 16 }, 346 [SCBRR] = { 0x04, 8 }, 347 [SCSCR] = { 0x08, 16 }, 348 [SCxTDR] = { 0x0c, 8 }, 349 [SCxSR] = { 0x10, 16 }, 350 [SCxRDR] = { 0x14, 8 }, 351 [SCFCR] = { 0x18, 16 }, 352 [SCFDR] = { 0x1c, 16 }, 353 [SCSPTR] = { 0x20, 16 }, 354 [SCLSR] = { 0x24, 16 }, 355 }, 356 .fifosize = 16, 357 .overrun_reg = SCLSR, 358 .overrun_mask = SCLSR_ORER, 359 .sampling_rate_mask = SCI_SR(32), 360 .error_mask = SCIF_DEFAULT_ERROR_MASK, 361 .error_clear = SCIF_ERROR_CLEAR, 362 }, 363 364 /* 365 * Common SCIF definitions for ports with a Baud Rate Generator for 366 * External Clock (BRG). 367 */ 368 [SCIx_SH4_SCIF_BRG_REGTYPE] = { 369 .regs = { 370 [SCSMR] = { 0x00, 16 }, 371 [SCBRR] = { 0x04, 8 }, 372 [SCSCR] = { 0x08, 16 }, 373 [SCxTDR] = { 0x0c, 8 }, 374 [SCxSR] = { 0x10, 16 }, 375 [SCxRDR] = { 0x14, 8 }, 376 [SCFCR] = { 0x18, 16 }, 377 [SCFDR] = { 0x1c, 16 }, 378 [SCSPTR] = { 0x20, 16 }, 379 [SCLSR] = { 0x24, 16 }, 380 [SCDL] = { 0x30, 16 }, 381 [SCCKS] = { 0x34, 16 }, 382 }, 383 .fifosize = 16, 384 .overrun_reg = SCLSR, 385 .overrun_mask = SCLSR_ORER, 386 .sampling_rate_mask = SCI_SR(32), 387 .error_mask = SCIF_DEFAULT_ERROR_MASK, 388 .error_clear = SCIF_ERROR_CLEAR, 389 }, 390 391 /* 392 * Common HSCIF definitions. 393 */ 394 [SCIx_HSCIF_REGTYPE] = { 395 .regs = { 396 [SCSMR] = { 0x00, 16 }, 397 [SCBRR] = { 0x04, 8 }, 398 [SCSCR] = { 0x08, 16 }, 399 [SCxTDR] = { 0x0c, 8 }, 400 [SCxSR] = { 0x10, 16 }, 401 [SCxRDR] = { 0x14, 8 }, 402 [SCFCR] = { 0x18, 16 }, 403 [SCFDR] = { 0x1c, 16 }, 404 [SCSPTR] = { 0x20, 16 }, 405 [SCLSR] = { 0x24, 16 }, 406 [HSSRR] = { 0x40, 16 }, 407 [SCDL] = { 0x30, 16 }, 408 [SCCKS] = { 0x34, 16 }, 409 [HSRTRGR] = { 0x54, 16 }, 410 [HSTTRGR] = { 0x58, 16 }, 411 }, 412 .fifosize = 128, 413 .overrun_reg = SCLSR, 414 .overrun_mask = SCLSR_ORER, 415 .sampling_rate_mask = SCI_SR_RANGE(8, 32), 416 .error_mask = SCIF_DEFAULT_ERROR_MASK, 417 .error_clear = SCIF_ERROR_CLEAR, 418 }, 419 420 /* 421 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR 422 * register. 423 */ 424 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = { 425 .regs = { 426 [SCSMR] = { 0x00, 16 }, 427 [SCBRR] = { 0x04, 8 }, 428 [SCSCR] = { 0x08, 16 }, 429 [SCxTDR] = { 0x0c, 8 }, 430 [SCxSR] = { 0x10, 16 }, 431 [SCxRDR] = { 0x14, 8 }, 432 [SCFCR] = { 0x18, 16 }, 433 [SCFDR] = { 0x1c, 16 }, 434 [SCLSR] = { 0x24, 16 }, 435 }, 436 .fifosize = 16, 437 .overrun_reg = SCLSR, 438 .overrun_mask = SCLSR_ORER, 439 .sampling_rate_mask = SCI_SR(32), 440 .error_mask = SCIF_DEFAULT_ERROR_MASK, 441 .error_clear = SCIF_ERROR_CLEAR, 442 }, 443 444 /* 445 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data 446 * count registers. 447 */ 448 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = { 449 .regs = { 450 [SCSMR] = { 0x00, 16 }, 451 [SCBRR] = { 0x04, 8 }, 452 [SCSCR] = { 0x08, 16 }, 453 [SCxTDR] = { 0x0c, 8 }, 454 [SCxSR] = { 0x10, 16 }, 455 [SCxRDR] = { 0x14, 8 }, 456 [SCFCR] = { 0x18, 16 }, 457 [SCFDR] = { 0x1c, 16 }, 458 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */ 459 [SCRFDR] = { 0x20, 16 }, 460 [SCSPTR] = { 0x24, 16 }, 461 [SCLSR] = { 0x28, 16 }, 462 }, 463 .fifosize = 16, 464 .overrun_reg = SCLSR, 465 .overrun_mask = SCLSR_ORER, 466 .sampling_rate_mask = SCI_SR(32), 467 .error_mask = SCIF_DEFAULT_ERROR_MASK, 468 .error_clear = SCIF_ERROR_CLEAR, 469 }, 470 471 /* 472 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR 473 * registers. 474 */ 475 [SCIx_SH7705_SCIF_REGTYPE] = { 476 .regs = { 477 [SCSMR] = { 0x00, 16 }, 478 [SCBRR] = { 0x04, 8 }, 479 [SCSCR] = { 0x08, 16 }, 480 [SCxTDR] = { 0x20, 8 }, 481 [SCxSR] = { 0x14, 16 }, 482 [SCxRDR] = { 0x24, 8 }, 483 [SCFCR] = { 0x18, 16 }, 484 [SCFDR] = { 0x1c, 16 }, 485 }, 486 .fifosize = 64, 487 .overrun_reg = SCxSR, 488 .overrun_mask = SCIFA_ORER, 489 .sampling_rate_mask = SCI_SR(16), 490 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 491 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 492 }, 493 }; 494 495 #define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset]) 496 497 /* 498 * The "offset" here is rather misleading, in that it refers to an enum 499 * value relative to the port mapping rather than the fixed offset 500 * itself, which needs to be manually retrieved from the platform's 501 * register map for the given port. 502 */ 503 static unsigned int sci_serial_in(struct uart_port *p, int offset) 504 { 505 const struct plat_sci_reg *reg = sci_getreg(p, offset); 506 507 if (reg->size == 8) 508 return ioread8(p->membase + (reg->offset << p->regshift)); 509 else if (reg->size == 16) 510 return ioread16(p->membase + (reg->offset << p->regshift)); 511 else 512 WARN(1, "Invalid register access\n"); 513 514 return 0; 515 } 516 517 static void sci_serial_out(struct uart_port *p, int offset, int value) 518 { 519 const struct plat_sci_reg *reg = sci_getreg(p, offset); 520 521 if (reg->size == 8) 522 iowrite8(value, p->membase + (reg->offset << p->regshift)); 523 else if (reg->size == 16) 524 iowrite16(value, p->membase + (reg->offset << p->regshift)); 525 else 526 WARN(1, "Invalid register access\n"); 527 } 528 529 static void sci_port_enable(struct sci_port *sci_port) 530 { 531 unsigned int i; 532 533 if (!sci_port->port.dev) 534 return; 535 536 pm_runtime_get_sync(sci_port->port.dev); 537 538 for (i = 0; i < SCI_NUM_CLKS; i++) { 539 clk_prepare_enable(sci_port->clks[i]); 540 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]); 541 } 542 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK]; 543 } 544 545 static void sci_port_disable(struct sci_port *sci_port) 546 { 547 unsigned int i; 548 549 if (!sci_port->port.dev) 550 return; 551 552 for (i = SCI_NUM_CLKS; i-- > 0; ) 553 clk_disable_unprepare(sci_port->clks[i]); 554 555 pm_runtime_put_sync(sci_port->port.dev); 556 } 557 558 static inline unsigned long port_rx_irq_mask(struct uart_port *port) 559 { 560 /* 561 * Not all ports (such as SCIFA) will support REIE. Rather than 562 * special-casing the port type, we check the port initialization 563 * IRQ enable mask to see whether the IRQ is desired at all. If 564 * it's unset, it's logically inferred that there's no point in 565 * testing for it. 566 */ 567 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE); 568 } 569 570 static void sci_start_tx(struct uart_port *port) 571 { 572 struct sci_port *s = to_sci_port(port); 573 unsigned short ctrl; 574 575 #ifdef CONFIG_SERIAL_SH_SCI_DMA 576 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 577 u16 new, scr = serial_port_in(port, SCSCR); 578 if (s->chan_tx) 579 new = scr | SCSCR_TDRQE; 580 else 581 new = scr & ~SCSCR_TDRQE; 582 if (new != scr) 583 serial_port_out(port, SCSCR, new); 584 } 585 586 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) && 587 dma_submit_error(s->cookie_tx)) { 588 s->cookie_tx = 0; 589 schedule_work(&s->work_tx); 590 } 591 #endif 592 593 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 594 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ 595 ctrl = serial_port_in(port, SCSCR); 596 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE); 597 } 598 } 599 600 static void sci_stop_tx(struct uart_port *port) 601 { 602 unsigned short ctrl; 603 604 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ 605 ctrl = serial_port_in(port, SCSCR); 606 607 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 608 ctrl &= ~SCSCR_TDRQE; 609 610 ctrl &= ~SCSCR_TIE; 611 612 serial_port_out(port, SCSCR, ctrl); 613 } 614 615 static void sci_start_rx(struct uart_port *port) 616 { 617 unsigned short ctrl; 618 619 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port); 620 621 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 622 ctrl &= ~SCSCR_RDRQE; 623 624 serial_port_out(port, SCSCR, ctrl); 625 } 626 627 static void sci_stop_rx(struct uart_port *port) 628 { 629 unsigned short ctrl; 630 631 ctrl = serial_port_in(port, SCSCR); 632 633 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 634 ctrl &= ~SCSCR_RDRQE; 635 636 ctrl &= ~port_rx_irq_mask(port); 637 638 serial_port_out(port, SCSCR, ctrl); 639 } 640 641 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask) 642 { 643 if (port->type == PORT_SCI) { 644 /* Just store the mask */ 645 serial_port_out(port, SCxSR, mask); 646 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) { 647 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */ 648 /* Only clear the status bits we want to clear */ 649 serial_port_out(port, SCxSR, 650 serial_port_in(port, SCxSR) & mask); 651 } else { 652 /* Store the mask, clear parity/framing errors */ 653 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC)); 654 } 655 } 656 657 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ 658 defined(CONFIG_SERIAL_SH_SCI_EARLYCON) 659 660 #ifdef CONFIG_CONSOLE_POLL 661 static int sci_poll_get_char(struct uart_port *port) 662 { 663 unsigned short status; 664 int c; 665 666 do { 667 status = serial_port_in(port, SCxSR); 668 if (status & SCxSR_ERRORS(port)) { 669 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); 670 continue; 671 } 672 break; 673 } while (1); 674 675 if (!(status & SCxSR_RDxF(port))) 676 return NO_POLL_CHAR; 677 678 c = serial_port_in(port, SCxRDR); 679 680 /* Dummy read */ 681 serial_port_in(port, SCxSR); 682 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 683 684 return c; 685 } 686 #endif 687 688 static void sci_poll_put_char(struct uart_port *port, unsigned char c) 689 { 690 unsigned short status; 691 692 do { 693 status = serial_port_in(port, SCxSR); 694 } while (!(status & SCxSR_TDxE(port))); 695 696 serial_port_out(port, SCxTDR, c); 697 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port)); 698 } 699 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE || 700 CONFIG_SERIAL_SH_SCI_EARLYCON */ 701 702 static void sci_init_pins(struct uart_port *port, unsigned int cflag) 703 { 704 struct sci_port *s = to_sci_port(port); 705 706 /* 707 * Use port-specific handler if provided. 708 */ 709 if (s->cfg->ops && s->cfg->ops->init_pins) { 710 s->cfg->ops->init_pins(port, cflag); 711 return; 712 } 713 714 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 715 u16 data = serial_port_in(port, SCPDR); 716 u16 ctrl = serial_port_in(port, SCPCR); 717 718 /* Enable RXD and TXD pin functions */ 719 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC); 720 if (to_sci_port(port)->has_rtscts) { 721 /* RTS# is output, active low, unless autorts */ 722 if (!(port->mctrl & TIOCM_RTS)) { 723 ctrl |= SCPCR_RTSC; 724 data |= SCPDR_RTSD; 725 } else if (!s->autorts) { 726 ctrl |= SCPCR_RTSC; 727 data &= ~SCPDR_RTSD; 728 } else { 729 /* Enable RTS# pin function */ 730 ctrl &= ~SCPCR_RTSC; 731 } 732 /* Enable CTS# pin function */ 733 ctrl &= ~SCPCR_CTSC; 734 } 735 serial_port_out(port, SCPDR, data); 736 serial_port_out(port, SCPCR, ctrl); 737 } else if (sci_getreg(port, SCSPTR)->size) { 738 u16 status = serial_port_in(port, SCSPTR); 739 740 /* RTS# is always output; and active low, unless autorts */ 741 status |= SCSPTR_RTSIO; 742 if (!(port->mctrl & TIOCM_RTS)) 743 status |= SCSPTR_RTSDT; 744 else if (!s->autorts) 745 status &= ~SCSPTR_RTSDT; 746 /* CTS# and SCK are inputs */ 747 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO); 748 serial_port_out(port, SCSPTR, status); 749 } 750 } 751 752 static int sci_txfill(struct uart_port *port) 753 { 754 struct sci_port *s = to_sci_port(port); 755 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; 756 const struct plat_sci_reg *reg; 757 758 reg = sci_getreg(port, SCTFDR); 759 if (reg->size) 760 return serial_port_in(port, SCTFDR) & fifo_mask; 761 762 reg = sci_getreg(port, SCFDR); 763 if (reg->size) 764 return serial_port_in(port, SCFDR) >> 8; 765 766 return !(serial_port_in(port, SCxSR) & SCI_TDRE); 767 } 768 769 static int sci_txroom(struct uart_port *port) 770 { 771 return port->fifosize - sci_txfill(port); 772 } 773 774 static int sci_rxfill(struct uart_port *port) 775 { 776 struct sci_port *s = to_sci_port(port); 777 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; 778 const struct plat_sci_reg *reg; 779 780 reg = sci_getreg(port, SCRFDR); 781 if (reg->size) 782 return serial_port_in(port, SCRFDR) & fifo_mask; 783 784 reg = sci_getreg(port, SCFDR); 785 if (reg->size) 786 return serial_port_in(port, SCFDR) & fifo_mask; 787 788 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0; 789 } 790 791 /* ********************************************************************** * 792 * the interrupt related routines * 793 * ********************************************************************** */ 794 795 static void sci_transmit_chars(struct uart_port *port) 796 { 797 struct circ_buf *xmit = &port->state->xmit; 798 unsigned int stopped = uart_tx_stopped(port); 799 unsigned short status; 800 unsigned short ctrl; 801 int count; 802 803 status = serial_port_in(port, SCxSR); 804 if (!(status & SCxSR_TDxE(port))) { 805 ctrl = serial_port_in(port, SCSCR); 806 if (uart_circ_empty(xmit)) 807 ctrl &= ~SCSCR_TIE; 808 else 809 ctrl |= SCSCR_TIE; 810 serial_port_out(port, SCSCR, ctrl); 811 return; 812 } 813 814 count = sci_txroom(port); 815 816 do { 817 unsigned char c; 818 819 if (port->x_char) { 820 c = port->x_char; 821 port->x_char = 0; 822 } else if (!uart_circ_empty(xmit) && !stopped) { 823 c = xmit->buf[xmit->tail]; 824 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 825 } else { 826 break; 827 } 828 829 serial_port_out(port, SCxTDR, c); 830 831 port->icount.tx++; 832 } while (--count > 0); 833 834 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port)); 835 836 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 837 uart_write_wakeup(port); 838 if (uart_circ_empty(xmit)) 839 sci_stop_tx(port); 840 841 } 842 843 /* On SH3, SCIF may read end-of-break as a space->mark char */ 844 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); }) 845 846 static void sci_receive_chars(struct uart_port *port) 847 { 848 struct tty_port *tport = &port->state->port; 849 int i, count, copied = 0; 850 unsigned short status; 851 unsigned char flag; 852 853 status = serial_port_in(port, SCxSR); 854 if (!(status & SCxSR_RDxF(port))) 855 return; 856 857 while (1) { 858 /* Don't copy more bytes than there is room for in the buffer */ 859 count = tty_buffer_request_room(tport, sci_rxfill(port)); 860 861 /* If for any reason we can't copy more data, we're done! */ 862 if (count == 0) 863 break; 864 865 if (port->type == PORT_SCI) { 866 char c = serial_port_in(port, SCxRDR); 867 if (uart_handle_sysrq_char(port, c)) 868 count = 0; 869 else 870 tty_insert_flip_char(tport, c, TTY_NORMAL); 871 } else { 872 for (i = 0; i < count; i++) { 873 char c = serial_port_in(port, SCxRDR); 874 875 status = serial_port_in(port, SCxSR); 876 if (uart_handle_sysrq_char(port, c)) { 877 count--; i--; 878 continue; 879 } 880 881 /* Store data and status */ 882 if (status & SCxSR_FER(port)) { 883 flag = TTY_FRAME; 884 port->icount.frame++; 885 dev_notice(port->dev, "frame error\n"); 886 } else if (status & SCxSR_PER(port)) { 887 flag = TTY_PARITY; 888 port->icount.parity++; 889 dev_notice(port->dev, "parity error\n"); 890 } else 891 flag = TTY_NORMAL; 892 893 tty_insert_flip_char(tport, c, flag); 894 } 895 } 896 897 serial_port_in(port, SCxSR); /* dummy read */ 898 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 899 900 copied += count; 901 port->icount.rx += count; 902 } 903 904 if (copied) { 905 /* Tell the rest of the system the news. New characters! */ 906 tty_flip_buffer_push(tport); 907 } else { 908 /* TTY buffers full; read from RX reg to prevent lockup */ 909 serial_port_in(port, SCxRDR); 910 serial_port_in(port, SCxSR); /* dummy read */ 911 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 912 } 913 } 914 915 static int sci_handle_errors(struct uart_port *port) 916 { 917 int copied = 0; 918 unsigned short status = serial_port_in(port, SCxSR); 919 struct tty_port *tport = &port->state->port; 920 struct sci_port *s = to_sci_port(port); 921 922 /* Handle overruns */ 923 if (status & s->params->overrun_mask) { 924 port->icount.overrun++; 925 926 /* overrun error */ 927 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN)) 928 copied++; 929 930 dev_notice(port->dev, "overrun error\n"); 931 } 932 933 if (status & SCxSR_FER(port)) { 934 /* frame error */ 935 port->icount.frame++; 936 937 if (tty_insert_flip_char(tport, 0, TTY_FRAME)) 938 copied++; 939 940 dev_notice(port->dev, "frame error\n"); 941 } 942 943 if (status & SCxSR_PER(port)) { 944 /* parity error */ 945 port->icount.parity++; 946 947 if (tty_insert_flip_char(tport, 0, TTY_PARITY)) 948 copied++; 949 950 dev_notice(port->dev, "parity error\n"); 951 } 952 953 if (copied) 954 tty_flip_buffer_push(tport); 955 956 return copied; 957 } 958 959 static int sci_handle_fifo_overrun(struct uart_port *port) 960 { 961 struct tty_port *tport = &port->state->port; 962 struct sci_port *s = to_sci_port(port); 963 const struct plat_sci_reg *reg; 964 int copied = 0; 965 u16 status; 966 967 reg = sci_getreg(port, s->params->overrun_reg); 968 if (!reg->size) 969 return 0; 970 971 status = serial_port_in(port, s->params->overrun_reg); 972 if (status & s->params->overrun_mask) { 973 status &= ~s->params->overrun_mask; 974 serial_port_out(port, s->params->overrun_reg, status); 975 976 port->icount.overrun++; 977 978 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 979 tty_flip_buffer_push(tport); 980 981 dev_dbg(port->dev, "overrun error\n"); 982 copied++; 983 } 984 985 return copied; 986 } 987 988 static int sci_handle_breaks(struct uart_port *port) 989 { 990 int copied = 0; 991 unsigned short status = serial_port_in(port, SCxSR); 992 struct tty_port *tport = &port->state->port; 993 994 if (uart_handle_break(port)) 995 return 0; 996 997 if (status & SCxSR_BRK(port)) { 998 port->icount.brk++; 999 1000 /* Notify of BREAK */ 1001 if (tty_insert_flip_char(tport, 0, TTY_BREAK)) 1002 copied++; 1003 1004 dev_dbg(port->dev, "BREAK detected\n"); 1005 } 1006 1007 if (copied) 1008 tty_flip_buffer_push(tport); 1009 1010 copied += sci_handle_fifo_overrun(port); 1011 1012 return copied; 1013 } 1014 1015 static int scif_set_rtrg(struct uart_port *port, int rx_trig) 1016 { 1017 unsigned int bits; 1018 1019 if (rx_trig < 1) 1020 rx_trig = 1; 1021 if (rx_trig >= port->fifosize) 1022 rx_trig = port->fifosize; 1023 1024 /* HSCIF can be set to an arbitrary level. */ 1025 if (sci_getreg(port, HSRTRGR)->size) { 1026 serial_port_out(port, HSRTRGR, rx_trig); 1027 return rx_trig; 1028 } 1029 1030 switch (port->type) { 1031 case PORT_SCIF: 1032 if (rx_trig < 4) { 1033 bits = 0; 1034 rx_trig = 1; 1035 } else if (rx_trig < 8) { 1036 bits = SCFCR_RTRG0; 1037 rx_trig = 4; 1038 } else if (rx_trig < 14) { 1039 bits = SCFCR_RTRG1; 1040 rx_trig = 8; 1041 } else { 1042 bits = SCFCR_RTRG0 | SCFCR_RTRG1; 1043 rx_trig = 14; 1044 } 1045 break; 1046 case PORT_SCIFA: 1047 case PORT_SCIFB: 1048 if (rx_trig < 16) { 1049 bits = 0; 1050 rx_trig = 1; 1051 } else if (rx_trig < 32) { 1052 bits = SCFCR_RTRG0; 1053 rx_trig = 16; 1054 } else if (rx_trig < 48) { 1055 bits = SCFCR_RTRG1; 1056 rx_trig = 32; 1057 } else { 1058 bits = SCFCR_RTRG0 | SCFCR_RTRG1; 1059 rx_trig = 48; 1060 } 1061 break; 1062 default: 1063 WARN(1, "unknown FIFO configuration"); 1064 return 1; 1065 } 1066 1067 serial_port_out(port, SCFCR, 1068 (serial_port_in(port, SCFCR) & 1069 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits); 1070 1071 return rx_trig; 1072 } 1073 1074 static int scif_rtrg_enabled(struct uart_port *port) 1075 { 1076 if (sci_getreg(port, HSRTRGR)->size) 1077 return serial_port_in(port, HSRTRGR) != 0; 1078 else 1079 return (serial_port_in(port, SCFCR) & 1080 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0; 1081 } 1082 1083 static void rx_fifo_timer_fn(struct timer_list *t) 1084 { 1085 struct sci_port *s = from_timer(s, t, rx_fifo_timer); 1086 struct uart_port *port = &s->port; 1087 1088 dev_dbg(port->dev, "Rx timed out\n"); 1089 scif_set_rtrg(port, 1); 1090 } 1091 1092 static ssize_t rx_fifo_trigger_show(struct device *dev, 1093 struct device_attribute *attr, char *buf) 1094 { 1095 struct uart_port *port = dev_get_drvdata(dev); 1096 struct sci_port *sci = to_sci_port(port); 1097 1098 return sprintf(buf, "%d\n", sci->rx_trigger); 1099 } 1100 1101 static ssize_t rx_fifo_trigger_store(struct device *dev, 1102 struct device_attribute *attr, 1103 const char *buf, size_t count) 1104 { 1105 struct uart_port *port = dev_get_drvdata(dev); 1106 struct sci_port *sci = to_sci_port(port); 1107 int ret; 1108 long r; 1109 1110 ret = kstrtol(buf, 0, &r); 1111 if (ret) 1112 return ret; 1113 1114 sci->rx_trigger = scif_set_rtrg(port, r); 1115 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1116 scif_set_rtrg(port, 1); 1117 1118 return count; 1119 } 1120 1121 static DEVICE_ATTR_RW(rx_fifo_trigger); 1122 1123 static ssize_t rx_fifo_timeout_show(struct device *dev, 1124 struct device_attribute *attr, 1125 char *buf) 1126 { 1127 struct uart_port *port = dev_get_drvdata(dev); 1128 struct sci_port *sci = to_sci_port(port); 1129 int v; 1130 1131 if (port->type == PORT_HSCIF) 1132 v = sci->hscif_tot >> HSSCR_TOT_SHIFT; 1133 else 1134 v = sci->rx_fifo_timeout; 1135 1136 return sprintf(buf, "%d\n", v); 1137 } 1138 1139 static ssize_t rx_fifo_timeout_store(struct device *dev, 1140 struct device_attribute *attr, 1141 const char *buf, 1142 size_t count) 1143 { 1144 struct uart_port *port = dev_get_drvdata(dev); 1145 struct sci_port *sci = to_sci_port(port); 1146 int ret; 1147 long r; 1148 1149 ret = kstrtol(buf, 0, &r); 1150 if (ret) 1151 return ret; 1152 1153 if (port->type == PORT_HSCIF) { 1154 if (r < 0 || r > 3) 1155 return -EINVAL; 1156 sci->hscif_tot = r << HSSCR_TOT_SHIFT; 1157 } else { 1158 sci->rx_fifo_timeout = r; 1159 scif_set_rtrg(port, 1); 1160 if (r > 0) 1161 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0); 1162 } 1163 1164 return count; 1165 } 1166 1167 static DEVICE_ATTR_RW(rx_fifo_timeout); 1168 1169 1170 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1171 static void sci_dma_tx_complete(void *arg) 1172 { 1173 struct sci_port *s = arg; 1174 struct uart_port *port = &s->port; 1175 struct circ_buf *xmit = &port->state->xmit; 1176 unsigned long flags; 1177 1178 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1179 1180 spin_lock_irqsave(&port->lock, flags); 1181 1182 xmit->tail += s->tx_dma_len; 1183 xmit->tail &= UART_XMIT_SIZE - 1; 1184 1185 port->icount.tx += s->tx_dma_len; 1186 1187 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1188 uart_write_wakeup(port); 1189 1190 if (!uart_circ_empty(xmit)) { 1191 s->cookie_tx = 0; 1192 schedule_work(&s->work_tx); 1193 } else { 1194 s->cookie_tx = -EINVAL; 1195 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1196 u16 ctrl = serial_port_in(port, SCSCR); 1197 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE); 1198 } 1199 } 1200 1201 spin_unlock_irqrestore(&port->lock, flags); 1202 } 1203 1204 /* Locking: called with port lock held */ 1205 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count) 1206 { 1207 struct uart_port *port = &s->port; 1208 struct tty_port *tport = &port->state->port; 1209 int copied; 1210 1211 copied = tty_insert_flip_string(tport, buf, count); 1212 if (copied < count) 1213 port->icount.buf_overrun++; 1214 1215 port->icount.rx += copied; 1216 1217 return copied; 1218 } 1219 1220 static int sci_dma_rx_find_active(struct sci_port *s) 1221 { 1222 unsigned int i; 1223 1224 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) 1225 if (s->active_rx == s->cookie_rx[i]) 1226 return i; 1227 1228 return -1; 1229 } 1230 1231 static void sci_dma_rx_chan_invalidate(struct sci_port *s) 1232 { 1233 unsigned int i; 1234 1235 s->chan_rx = NULL; 1236 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) 1237 s->cookie_rx[i] = -EINVAL; 1238 s->active_rx = 0; 1239 } 1240 1241 static void sci_dma_rx_release(struct sci_port *s) 1242 { 1243 struct dma_chan *chan = s->chan_rx_saved; 1244 1245 s->chan_rx_saved = NULL; 1246 sci_dma_rx_chan_invalidate(s); 1247 dmaengine_terminate_sync(chan); 1248 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0], 1249 sg_dma_address(&s->sg_rx[0])); 1250 dma_release_channel(chan); 1251 } 1252 1253 static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec) 1254 { 1255 long sec = usec / 1000000; 1256 long nsec = (usec % 1000000) * 1000; 1257 ktime_t t = ktime_set(sec, nsec); 1258 1259 hrtimer_start(hrt, t, HRTIMER_MODE_REL); 1260 } 1261 1262 static void sci_dma_rx_reenable_irq(struct sci_port *s) 1263 { 1264 struct uart_port *port = &s->port; 1265 u16 scr; 1266 1267 /* Direct new serial port interrupts back to CPU */ 1268 scr = serial_port_in(port, SCSCR); 1269 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1270 scr &= ~SCSCR_RDRQE; 1271 enable_irq(s->irqs[SCIx_RXI_IRQ]); 1272 } 1273 serial_port_out(port, SCSCR, scr | SCSCR_RIE); 1274 } 1275 1276 static void sci_dma_rx_complete(void *arg) 1277 { 1278 struct sci_port *s = arg; 1279 struct dma_chan *chan = s->chan_rx; 1280 struct uart_port *port = &s->port; 1281 struct dma_async_tx_descriptor *desc; 1282 unsigned long flags; 1283 int active, count = 0; 1284 1285 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line, 1286 s->active_rx); 1287 1288 spin_lock_irqsave(&port->lock, flags); 1289 1290 active = sci_dma_rx_find_active(s); 1291 if (active >= 0) 1292 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx); 1293 1294 start_hrtimer_us(&s->rx_timer, s->rx_timeout); 1295 1296 if (count) 1297 tty_flip_buffer_push(&port->state->port); 1298 1299 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1, 1300 DMA_DEV_TO_MEM, 1301 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1302 if (!desc) 1303 goto fail; 1304 1305 desc->callback = sci_dma_rx_complete; 1306 desc->callback_param = s; 1307 s->cookie_rx[active] = dmaengine_submit(desc); 1308 if (dma_submit_error(s->cookie_rx[active])) 1309 goto fail; 1310 1311 s->active_rx = s->cookie_rx[!active]; 1312 1313 dma_async_issue_pending(chan); 1314 1315 spin_unlock_irqrestore(&port->lock, flags); 1316 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n", 1317 __func__, s->cookie_rx[active], active, s->active_rx); 1318 return; 1319 1320 fail: 1321 spin_unlock_irqrestore(&port->lock, flags); 1322 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n"); 1323 /* Switch to PIO */ 1324 spin_lock_irqsave(&port->lock, flags); 1325 dmaengine_terminate_async(chan); 1326 sci_dma_rx_chan_invalidate(s); 1327 sci_dma_rx_reenable_irq(s); 1328 spin_unlock_irqrestore(&port->lock, flags); 1329 } 1330 1331 static void sci_dma_tx_release(struct sci_port *s) 1332 { 1333 struct dma_chan *chan = s->chan_tx_saved; 1334 1335 cancel_work_sync(&s->work_tx); 1336 s->chan_tx_saved = s->chan_tx = NULL; 1337 s->cookie_tx = -EINVAL; 1338 dmaengine_terminate_sync(chan); 1339 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE, 1340 DMA_TO_DEVICE); 1341 dma_release_channel(chan); 1342 } 1343 1344 static int sci_dma_rx_submit(struct sci_port *s, bool port_lock_held) 1345 { 1346 struct dma_chan *chan = s->chan_rx; 1347 struct uart_port *port = &s->port; 1348 unsigned long flags; 1349 int i; 1350 1351 for (i = 0; i < 2; i++) { 1352 struct scatterlist *sg = &s->sg_rx[i]; 1353 struct dma_async_tx_descriptor *desc; 1354 1355 desc = dmaengine_prep_slave_sg(chan, 1356 sg, 1, DMA_DEV_TO_MEM, 1357 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1358 if (!desc) 1359 goto fail; 1360 1361 desc->callback = sci_dma_rx_complete; 1362 desc->callback_param = s; 1363 s->cookie_rx[i] = dmaengine_submit(desc); 1364 if (dma_submit_error(s->cookie_rx[i])) 1365 goto fail; 1366 1367 } 1368 1369 s->active_rx = s->cookie_rx[0]; 1370 1371 dma_async_issue_pending(chan); 1372 return 0; 1373 1374 fail: 1375 /* Switch to PIO */ 1376 if (!port_lock_held) 1377 spin_lock_irqsave(&port->lock, flags); 1378 if (i) 1379 dmaengine_terminate_async(chan); 1380 sci_dma_rx_chan_invalidate(s); 1381 sci_start_rx(port); 1382 if (!port_lock_held) 1383 spin_unlock_irqrestore(&port->lock, flags); 1384 return -EAGAIN; 1385 } 1386 1387 static void sci_dma_tx_work_fn(struct work_struct *work) 1388 { 1389 struct sci_port *s = container_of(work, struct sci_port, work_tx); 1390 struct dma_async_tx_descriptor *desc; 1391 struct dma_chan *chan = s->chan_tx; 1392 struct uart_port *port = &s->port; 1393 struct circ_buf *xmit = &port->state->xmit; 1394 unsigned long flags; 1395 dma_addr_t buf; 1396 int head, tail; 1397 1398 /* 1399 * DMA is idle now. 1400 * Port xmit buffer is already mapped, and it is one page... Just adjust 1401 * offsets and lengths. Since it is a circular buffer, we have to 1402 * transmit till the end, and then the rest. Take the port lock to get a 1403 * consistent xmit buffer state. 1404 */ 1405 spin_lock_irq(&port->lock); 1406 head = xmit->head; 1407 tail = xmit->tail; 1408 buf = s->tx_dma_addr + (tail & (UART_XMIT_SIZE - 1)); 1409 s->tx_dma_len = min_t(unsigned int, 1410 CIRC_CNT(head, tail, UART_XMIT_SIZE), 1411 CIRC_CNT_TO_END(head, tail, UART_XMIT_SIZE)); 1412 if (!s->tx_dma_len) { 1413 /* Transmit buffer has been flushed */ 1414 spin_unlock_irq(&port->lock); 1415 return; 1416 } 1417 1418 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len, 1419 DMA_MEM_TO_DEV, 1420 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1421 if (!desc) { 1422 spin_unlock_irq(&port->lock); 1423 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n"); 1424 goto switch_to_pio; 1425 } 1426 1427 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len, 1428 DMA_TO_DEVICE); 1429 1430 desc->callback = sci_dma_tx_complete; 1431 desc->callback_param = s; 1432 s->cookie_tx = dmaengine_submit(desc); 1433 if (dma_submit_error(s->cookie_tx)) { 1434 spin_unlock_irq(&port->lock); 1435 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n"); 1436 goto switch_to_pio; 1437 } 1438 1439 spin_unlock_irq(&port->lock); 1440 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", 1441 __func__, xmit->buf, tail, head, s->cookie_tx); 1442 1443 dma_async_issue_pending(chan); 1444 return; 1445 1446 switch_to_pio: 1447 spin_lock_irqsave(&port->lock, flags); 1448 s->chan_tx = NULL; 1449 sci_start_tx(port); 1450 spin_unlock_irqrestore(&port->lock, flags); 1451 return; 1452 } 1453 1454 static enum hrtimer_restart sci_dma_rx_timer_fn(struct hrtimer *t) 1455 { 1456 struct sci_port *s = container_of(t, struct sci_port, rx_timer); 1457 struct dma_chan *chan = s->chan_rx; 1458 struct uart_port *port = &s->port; 1459 struct dma_tx_state state; 1460 enum dma_status status; 1461 unsigned long flags; 1462 unsigned int read; 1463 int active, count; 1464 1465 dev_dbg(port->dev, "DMA Rx timed out\n"); 1466 1467 spin_lock_irqsave(&port->lock, flags); 1468 1469 active = sci_dma_rx_find_active(s); 1470 if (active < 0) { 1471 spin_unlock_irqrestore(&port->lock, flags); 1472 return HRTIMER_NORESTART; 1473 } 1474 1475 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); 1476 if (status == DMA_COMPLETE) { 1477 spin_unlock_irqrestore(&port->lock, flags); 1478 dev_dbg(port->dev, "Cookie %d #%d has already completed\n", 1479 s->active_rx, active); 1480 1481 /* Let packet complete handler take care of the packet */ 1482 return HRTIMER_NORESTART; 1483 } 1484 1485 dmaengine_pause(chan); 1486 1487 /* 1488 * sometimes DMA transfer doesn't stop even if it is stopped and 1489 * data keeps on coming until transaction is complete so check 1490 * for DMA_COMPLETE again 1491 * Let packet complete handler take care of the packet 1492 */ 1493 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); 1494 if (status == DMA_COMPLETE) { 1495 spin_unlock_irqrestore(&port->lock, flags); 1496 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped"); 1497 return HRTIMER_NORESTART; 1498 } 1499 1500 /* Handle incomplete DMA receive */ 1501 dmaengine_terminate_async(s->chan_rx); 1502 read = sg_dma_len(&s->sg_rx[active]) - state.residue; 1503 1504 if (read) { 1505 count = sci_dma_rx_push(s, s->rx_buf[active], read); 1506 if (count) 1507 tty_flip_buffer_push(&port->state->port); 1508 } 1509 1510 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1511 sci_dma_rx_submit(s, true); 1512 1513 sci_dma_rx_reenable_irq(s); 1514 1515 spin_unlock_irqrestore(&port->lock, flags); 1516 1517 return HRTIMER_NORESTART; 1518 } 1519 1520 static struct dma_chan *sci_request_dma_chan(struct uart_port *port, 1521 enum dma_transfer_direction dir) 1522 { 1523 struct dma_chan *chan; 1524 struct dma_slave_config cfg; 1525 int ret; 1526 1527 chan = dma_request_slave_channel(port->dev, 1528 dir == DMA_MEM_TO_DEV ? "tx" : "rx"); 1529 if (!chan) { 1530 dev_dbg(port->dev, "dma_request_slave_channel failed\n"); 1531 return NULL; 1532 } 1533 1534 memset(&cfg, 0, sizeof(cfg)); 1535 cfg.direction = dir; 1536 if (dir == DMA_MEM_TO_DEV) { 1537 cfg.dst_addr = port->mapbase + 1538 (sci_getreg(port, SCxTDR)->offset << port->regshift); 1539 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1540 } else { 1541 cfg.src_addr = port->mapbase + 1542 (sci_getreg(port, SCxRDR)->offset << port->regshift); 1543 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1544 } 1545 1546 ret = dmaengine_slave_config(chan, &cfg); 1547 if (ret) { 1548 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret); 1549 dma_release_channel(chan); 1550 return NULL; 1551 } 1552 1553 return chan; 1554 } 1555 1556 static void sci_request_dma(struct uart_port *port) 1557 { 1558 struct sci_port *s = to_sci_port(port); 1559 struct dma_chan *chan; 1560 1561 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line); 1562 1563 /* 1564 * DMA on console may interfere with Kernel log messages which use 1565 * plain putchar(). So, simply don't use it with a console. 1566 */ 1567 if (uart_console(port)) 1568 return; 1569 1570 if (!port->dev->of_node) 1571 return; 1572 1573 s->cookie_tx = -EINVAL; 1574 1575 /* 1576 * Don't request a dma channel if no channel was specified 1577 * in the device tree. 1578 */ 1579 if (!of_find_property(port->dev->of_node, "dmas", NULL)) 1580 return; 1581 1582 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV); 1583 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan); 1584 if (chan) { 1585 /* UART circular tx buffer is an aligned page. */ 1586 s->tx_dma_addr = dma_map_single(chan->device->dev, 1587 port->state->xmit.buf, 1588 UART_XMIT_SIZE, 1589 DMA_TO_DEVICE); 1590 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) { 1591 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n"); 1592 dma_release_channel(chan); 1593 } else { 1594 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n", 1595 __func__, UART_XMIT_SIZE, 1596 port->state->xmit.buf, &s->tx_dma_addr); 1597 1598 INIT_WORK(&s->work_tx, sci_dma_tx_work_fn); 1599 s->chan_tx_saved = s->chan_tx = chan; 1600 } 1601 } 1602 1603 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM); 1604 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan); 1605 if (chan) { 1606 unsigned int i; 1607 dma_addr_t dma; 1608 void *buf; 1609 1610 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize); 1611 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2, 1612 &dma, GFP_KERNEL); 1613 if (!buf) { 1614 dev_warn(port->dev, 1615 "Failed to allocate Rx dma buffer, using PIO\n"); 1616 dma_release_channel(chan); 1617 return; 1618 } 1619 1620 for (i = 0; i < 2; i++) { 1621 struct scatterlist *sg = &s->sg_rx[i]; 1622 1623 sg_init_table(sg, 1); 1624 s->rx_buf[i] = buf; 1625 sg_dma_address(sg) = dma; 1626 sg_dma_len(sg) = s->buf_len_rx; 1627 1628 buf += s->buf_len_rx; 1629 dma += s->buf_len_rx; 1630 } 1631 1632 hrtimer_init(&s->rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 1633 s->rx_timer.function = sci_dma_rx_timer_fn; 1634 1635 s->chan_rx_saved = s->chan_rx = chan; 1636 1637 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1638 sci_dma_rx_submit(s, false); 1639 } 1640 } 1641 1642 static void sci_free_dma(struct uart_port *port) 1643 { 1644 struct sci_port *s = to_sci_port(port); 1645 1646 if (s->chan_tx_saved) 1647 sci_dma_tx_release(s); 1648 if (s->chan_rx_saved) 1649 sci_dma_rx_release(s); 1650 } 1651 1652 static void sci_flush_buffer(struct uart_port *port) 1653 { 1654 struct sci_port *s = to_sci_port(port); 1655 1656 /* 1657 * In uart_flush_buffer(), the xmit circular buffer has just been 1658 * cleared, so we have to reset tx_dma_len accordingly, and stop any 1659 * pending transfers 1660 */ 1661 s->tx_dma_len = 0; 1662 if (s->chan_tx) { 1663 dmaengine_terminate_async(s->chan_tx); 1664 s->cookie_tx = -EINVAL; 1665 } 1666 } 1667 #else /* !CONFIG_SERIAL_SH_SCI_DMA */ 1668 static inline void sci_request_dma(struct uart_port *port) 1669 { 1670 } 1671 1672 static inline void sci_free_dma(struct uart_port *port) 1673 { 1674 } 1675 1676 #define sci_flush_buffer NULL 1677 #endif /* !CONFIG_SERIAL_SH_SCI_DMA */ 1678 1679 static irqreturn_t sci_rx_interrupt(int irq, void *ptr) 1680 { 1681 struct uart_port *port = ptr; 1682 struct sci_port *s = to_sci_port(port); 1683 1684 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1685 if (s->chan_rx) { 1686 u16 scr = serial_port_in(port, SCSCR); 1687 u16 ssr = serial_port_in(port, SCxSR); 1688 1689 /* Disable future Rx interrupts */ 1690 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1691 disable_irq_nosync(irq); 1692 scr |= SCSCR_RDRQE; 1693 } else { 1694 if (sci_dma_rx_submit(s, false) < 0) 1695 goto handle_pio; 1696 1697 scr &= ~SCSCR_RIE; 1698 } 1699 serial_port_out(port, SCSCR, scr); 1700 /* Clear current interrupt */ 1701 serial_port_out(port, SCxSR, 1702 ssr & ~(SCIF_DR | SCxSR_RDxF(port))); 1703 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n", 1704 jiffies, s->rx_timeout); 1705 start_hrtimer_us(&s->rx_timer, s->rx_timeout); 1706 1707 return IRQ_HANDLED; 1708 } 1709 1710 handle_pio: 1711 #endif 1712 1713 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) { 1714 if (!scif_rtrg_enabled(port)) 1715 scif_set_rtrg(port, s->rx_trigger); 1716 1717 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP( 1718 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000)); 1719 } 1720 1721 /* I think sci_receive_chars has to be called irrespective 1722 * of whether the I_IXOFF is set, otherwise, how is the interrupt 1723 * to be disabled? 1724 */ 1725 sci_receive_chars(port); 1726 1727 return IRQ_HANDLED; 1728 } 1729 1730 static irqreturn_t sci_tx_interrupt(int irq, void *ptr) 1731 { 1732 struct uart_port *port = ptr; 1733 unsigned long flags; 1734 1735 spin_lock_irqsave(&port->lock, flags); 1736 sci_transmit_chars(port); 1737 spin_unlock_irqrestore(&port->lock, flags); 1738 1739 return IRQ_HANDLED; 1740 } 1741 1742 static irqreturn_t sci_br_interrupt(int irq, void *ptr) 1743 { 1744 struct uart_port *port = ptr; 1745 1746 /* Handle BREAKs */ 1747 sci_handle_breaks(port); 1748 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port)); 1749 1750 return IRQ_HANDLED; 1751 } 1752 1753 static irqreturn_t sci_er_interrupt(int irq, void *ptr) 1754 { 1755 struct uart_port *port = ptr; 1756 struct sci_port *s = to_sci_port(port); 1757 1758 if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) { 1759 /* Break and Error interrupts are muxed */ 1760 unsigned short ssr_status = serial_port_in(port, SCxSR); 1761 1762 /* Break Interrupt */ 1763 if (ssr_status & SCxSR_BRK(port)) 1764 sci_br_interrupt(irq, ptr); 1765 1766 /* Break only? */ 1767 if (!(ssr_status & SCxSR_ERRORS(port))) 1768 return IRQ_HANDLED; 1769 } 1770 1771 /* Handle errors */ 1772 if (port->type == PORT_SCI) { 1773 if (sci_handle_errors(port)) { 1774 /* discard character in rx buffer */ 1775 serial_port_in(port, SCxSR); 1776 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 1777 } 1778 } else { 1779 sci_handle_fifo_overrun(port); 1780 if (!s->chan_rx) 1781 sci_receive_chars(port); 1782 } 1783 1784 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); 1785 1786 /* Kick the transmission */ 1787 if (!s->chan_tx) 1788 sci_tx_interrupt(irq, ptr); 1789 1790 return IRQ_HANDLED; 1791 } 1792 1793 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) 1794 { 1795 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0; 1796 struct uart_port *port = ptr; 1797 struct sci_port *s = to_sci_port(port); 1798 irqreturn_t ret = IRQ_NONE; 1799 1800 ssr_status = serial_port_in(port, SCxSR); 1801 scr_status = serial_port_in(port, SCSCR); 1802 if (s->params->overrun_reg == SCxSR) 1803 orer_status = ssr_status; 1804 else if (sci_getreg(port, s->params->overrun_reg)->size) 1805 orer_status = serial_port_in(port, s->params->overrun_reg); 1806 1807 err_enabled = scr_status & port_rx_irq_mask(port); 1808 1809 /* Tx Interrupt */ 1810 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) && 1811 !s->chan_tx) 1812 ret = sci_tx_interrupt(irq, ptr); 1813 1814 /* 1815 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF / 1816 * DR flags 1817 */ 1818 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) && 1819 (scr_status & SCSCR_RIE)) 1820 ret = sci_rx_interrupt(irq, ptr); 1821 1822 /* Error Interrupt */ 1823 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled) 1824 ret = sci_er_interrupt(irq, ptr); 1825 1826 /* Break Interrupt */ 1827 if ((ssr_status & SCxSR_BRK(port)) && err_enabled) 1828 ret = sci_br_interrupt(irq, ptr); 1829 1830 /* Overrun Interrupt */ 1831 if (orer_status & s->params->overrun_mask) { 1832 sci_handle_fifo_overrun(port); 1833 ret = IRQ_HANDLED; 1834 } 1835 1836 return ret; 1837 } 1838 1839 static const struct sci_irq_desc { 1840 const char *desc; 1841 irq_handler_t handler; 1842 } sci_irq_desc[] = { 1843 /* 1844 * Split out handlers, the default case. 1845 */ 1846 [SCIx_ERI_IRQ] = { 1847 .desc = "rx err", 1848 .handler = sci_er_interrupt, 1849 }, 1850 1851 [SCIx_RXI_IRQ] = { 1852 .desc = "rx full", 1853 .handler = sci_rx_interrupt, 1854 }, 1855 1856 [SCIx_TXI_IRQ] = { 1857 .desc = "tx empty", 1858 .handler = sci_tx_interrupt, 1859 }, 1860 1861 [SCIx_BRI_IRQ] = { 1862 .desc = "break", 1863 .handler = sci_br_interrupt, 1864 }, 1865 1866 [SCIx_DRI_IRQ] = { 1867 .desc = "rx ready", 1868 .handler = sci_rx_interrupt, 1869 }, 1870 1871 [SCIx_TEI_IRQ] = { 1872 .desc = "tx end", 1873 .handler = sci_tx_interrupt, 1874 }, 1875 1876 /* 1877 * Special muxed handler. 1878 */ 1879 [SCIx_MUX_IRQ] = { 1880 .desc = "mux", 1881 .handler = sci_mpxed_interrupt, 1882 }, 1883 }; 1884 1885 static int sci_request_irq(struct sci_port *port) 1886 { 1887 struct uart_port *up = &port->port; 1888 int i, j, w, ret = 0; 1889 1890 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) { 1891 const struct sci_irq_desc *desc; 1892 int irq; 1893 1894 /* Check if already registered (muxed) */ 1895 for (w = 0; w < i; w++) 1896 if (port->irqs[w] == port->irqs[i]) 1897 w = i + 1; 1898 if (w > i) 1899 continue; 1900 1901 if (SCIx_IRQ_IS_MUXED(port)) { 1902 i = SCIx_MUX_IRQ; 1903 irq = up->irq; 1904 } else { 1905 irq = port->irqs[i]; 1906 1907 /* 1908 * Certain port types won't support all of the 1909 * available interrupt sources. 1910 */ 1911 if (unlikely(irq < 0)) 1912 continue; 1913 } 1914 1915 desc = sci_irq_desc + i; 1916 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s", 1917 dev_name(up->dev), desc->desc); 1918 if (!port->irqstr[j]) { 1919 ret = -ENOMEM; 1920 goto out_nomem; 1921 } 1922 1923 ret = request_irq(irq, desc->handler, up->irqflags, 1924 port->irqstr[j], port); 1925 if (unlikely(ret)) { 1926 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc); 1927 goto out_noirq; 1928 } 1929 } 1930 1931 return 0; 1932 1933 out_noirq: 1934 while (--i >= 0) 1935 free_irq(port->irqs[i], port); 1936 1937 out_nomem: 1938 while (--j >= 0) 1939 kfree(port->irqstr[j]); 1940 1941 return ret; 1942 } 1943 1944 static void sci_free_irq(struct sci_port *port) 1945 { 1946 int i, j; 1947 1948 /* 1949 * Intentionally in reverse order so we iterate over the muxed 1950 * IRQ first. 1951 */ 1952 for (i = 0; i < SCIx_NR_IRQS; i++) { 1953 int irq = port->irqs[i]; 1954 1955 /* 1956 * Certain port types won't support all of the available 1957 * interrupt sources. 1958 */ 1959 if (unlikely(irq < 0)) 1960 continue; 1961 1962 /* Check if already freed (irq was muxed) */ 1963 for (j = 0; j < i; j++) 1964 if (port->irqs[j] == irq) 1965 j = i + 1; 1966 if (j > i) 1967 continue; 1968 1969 free_irq(port->irqs[i], port); 1970 kfree(port->irqstr[i]); 1971 1972 if (SCIx_IRQ_IS_MUXED(port)) { 1973 /* If there's only one IRQ, we're done. */ 1974 return; 1975 } 1976 } 1977 } 1978 1979 static unsigned int sci_tx_empty(struct uart_port *port) 1980 { 1981 unsigned short status = serial_port_in(port, SCxSR); 1982 unsigned short in_tx_fifo = sci_txfill(port); 1983 1984 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0; 1985 } 1986 1987 static void sci_set_rts(struct uart_port *port, bool state) 1988 { 1989 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1990 u16 data = serial_port_in(port, SCPDR); 1991 1992 /* Active low */ 1993 if (state) 1994 data &= ~SCPDR_RTSD; 1995 else 1996 data |= SCPDR_RTSD; 1997 serial_port_out(port, SCPDR, data); 1998 1999 /* RTS# is output */ 2000 serial_port_out(port, SCPCR, 2001 serial_port_in(port, SCPCR) | SCPCR_RTSC); 2002 } else if (sci_getreg(port, SCSPTR)->size) { 2003 u16 ctrl = serial_port_in(port, SCSPTR); 2004 2005 /* Active low */ 2006 if (state) 2007 ctrl &= ~SCSPTR_RTSDT; 2008 else 2009 ctrl |= SCSPTR_RTSDT; 2010 serial_port_out(port, SCSPTR, ctrl); 2011 } 2012 } 2013 2014 static bool sci_get_cts(struct uart_port *port) 2015 { 2016 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 2017 /* Active low */ 2018 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD); 2019 } else if (sci_getreg(port, SCSPTR)->size) { 2020 /* Active low */ 2021 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT); 2022 } 2023 2024 return true; 2025 } 2026 2027 /* 2028 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally 2029 * CTS/RTS is supported in hardware by at least one port and controlled 2030 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently 2031 * handled via the ->init_pins() op, which is a bit of a one-way street, 2032 * lacking any ability to defer pin control -- this will later be 2033 * converted over to the GPIO framework). 2034 * 2035 * Other modes (such as loopback) are supported generically on certain 2036 * port types, but not others. For these it's sufficient to test for the 2037 * existence of the support register and simply ignore the port type. 2038 */ 2039 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) 2040 { 2041 struct sci_port *s = to_sci_port(port); 2042 2043 if (mctrl & TIOCM_LOOP) { 2044 const struct plat_sci_reg *reg; 2045 2046 /* 2047 * Standard loopback mode for SCFCR ports. 2048 */ 2049 reg = sci_getreg(port, SCFCR); 2050 if (reg->size) 2051 serial_port_out(port, SCFCR, 2052 serial_port_in(port, SCFCR) | 2053 SCFCR_LOOP); 2054 } 2055 2056 mctrl_gpio_set(s->gpios, mctrl); 2057 2058 if (!s->has_rtscts) 2059 return; 2060 2061 if (!(mctrl & TIOCM_RTS)) { 2062 /* Disable Auto RTS */ 2063 serial_port_out(port, SCFCR, 2064 serial_port_in(port, SCFCR) & ~SCFCR_MCE); 2065 2066 /* Clear RTS */ 2067 sci_set_rts(port, 0); 2068 } else if (s->autorts) { 2069 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 2070 /* Enable RTS# pin function */ 2071 serial_port_out(port, SCPCR, 2072 serial_port_in(port, SCPCR) & ~SCPCR_RTSC); 2073 } 2074 2075 /* Enable Auto RTS */ 2076 serial_port_out(port, SCFCR, 2077 serial_port_in(port, SCFCR) | SCFCR_MCE); 2078 } else { 2079 /* Set RTS */ 2080 sci_set_rts(port, 1); 2081 } 2082 } 2083 2084 static unsigned int sci_get_mctrl(struct uart_port *port) 2085 { 2086 struct sci_port *s = to_sci_port(port); 2087 struct mctrl_gpios *gpios = s->gpios; 2088 unsigned int mctrl = 0; 2089 2090 mctrl_gpio_get(gpios, &mctrl); 2091 2092 /* 2093 * CTS/RTS is handled in hardware when supported, while nothing 2094 * else is wired up. 2095 */ 2096 if (s->autorts) { 2097 if (sci_get_cts(port)) 2098 mctrl |= TIOCM_CTS; 2099 } else if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)) { 2100 mctrl |= TIOCM_CTS; 2101 } 2102 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)) 2103 mctrl |= TIOCM_DSR; 2104 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)) 2105 mctrl |= TIOCM_CAR; 2106 2107 return mctrl; 2108 } 2109 2110 static void sci_enable_ms(struct uart_port *port) 2111 { 2112 mctrl_gpio_enable_ms(to_sci_port(port)->gpios); 2113 } 2114 2115 static void sci_break_ctl(struct uart_port *port, int break_state) 2116 { 2117 unsigned short scscr, scsptr; 2118 unsigned long flags; 2119 2120 /* check wheter the port has SCSPTR */ 2121 if (!sci_getreg(port, SCSPTR)->size) { 2122 /* 2123 * Not supported by hardware. Most parts couple break and rx 2124 * interrupts together, with break detection always enabled. 2125 */ 2126 return; 2127 } 2128 2129 spin_lock_irqsave(&port->lock, flags); 2130 scsptr = serial_port_in(port, SCSPTR); 2131 scscr = serial_port_in(port, SCSCR); 2132 2133 if (break_state == -1) { 2134 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT; 2135 scscr &= ~SCSCR_TE; 2136 } else { 2137 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO; 2138 scscr |= SCSCR_TE; 2139 } 2140 2141 serial_port_out(port, SCSPTR, scsptr); 2142 serial_port_out(port, SCSCR, scscr); 2143 spin_unlock_irqrestore(&port->lock, flags); 2144 } 2145 2146 static int sci_startup(struct uart_port *port) 2147 { 2148 struct sci_port *s = to_sci_port(port); 2149 int ret; 2150 2151 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 2152 2153 sci_request_dma(port); 2154 2155 ret = sci_request_irq(s); 2156 if (unlikely(ret < 0)) { 2157 sci_free_dma(port); 2158 return ret; 2159 } 2160 2161 return 0; 2162 } 2163 2164 static void sci_shutdown(struct uart_port *port) 2165 { 2166 struct sci_port *s = to_sci_port(port); 2167 unsigned long flags; 2168 u16 scr; 2169 2170 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 2171 2172 s->autorts = false; 2173 mctrl_gpio_disable_ms(to_sci_port(port)->gpios); 2174 2175 spin_lock_irqsave(&port->lock, flags); 2176 sci_stop_rx(port); 2177 sci_stop_tx(port); 2178 /* 2179 * Stop RX and TX, disable related interrupts, keep clock source 2180 * and HSCIF TOT bits 2181 */ 2182 scr = serial_port_in(port, SCSCR); 2183 serial_port_out(port, SCSCR, scr & 2184 (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot)); 2185 spin_unlock_irqrestore(&port->lock, flags); 2186 2187 #ifdef CONFIG_SERIAL_SH_SCI_DMA 2188 if (s->chan_rx_saved) { 2189 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__, 2190 port->line); 2191 hrtimer_cancel(&s->rx_timer); 2192 } 2193 #endif 2194 2195 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) 2196 del_timer_sync(&s->rx_fifo_timer); 2197 sci_free_irq(s); 2198 sci_free_dma(port); 2199 } 2200 2201 static int sci_sck_calc(struct sci_port *s, unsigned int bps, 2202 unsigned int *srr) 2203 { 2204 unsigned long freq = s->clk_rates[SCI_SCK]; 2205 int err, min_err = INT_MAX; 2206 unsigned int sr; 2207 2208 if (s->port.type != PORT_HSCIF) 2209 freq *= 2; 2210 2211 for_each_sr(sr, s) { 2212 err = DIV_ROUND_CLOSEST(freq, sr) - bps; 2213 if (abs(err) >= abs(min_err)) 2214 continue; 2215 2216 min_err = err; 2217 *srr = sr - 1; 2218 2219 if (!err) 2220 break; 2221 } 2222 2223 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err, 2224 *srr + 1); 2225 return min_err; 2226 } 2227 2228 static int sci_brg_calc(struct sci_port *s, unsigned int bps, 2229 unsigned long freq, unsigned int *dlr, 2230 unsigned int *srr) 2231 { 2232 int err, min_err = INT_MAX; 2233 unsigned int sr, dl; 2234 2235 if (s->port.type != PORT_HSCIF) 2236 freq *= 2; 2237 2238 for_each_sr(sr, s) { 2239 dl = DIV_ROUND_CLOSEST(freq, sr * bps); 2240 dl = clamp(dl, 1U, 65535U); 2241 2242 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps; 2243 if (abs(err) >= abs(min_err)) 2244 continue; 2245 2246 min_err = err; 2247 *dlr = dl; 2248 *srr = sr - 1; 2249 2250 if (!err) 2251 break; 2252 } 2253 2254 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps, 2255 min_err, *dlr, *srr + 1); 2256 return min_err; 2257 } 2258 2259 /* calculate sample rate, BRR, and clock select */ 2260 static int sci_scbrr_calc(struct sci_port *s, unsigned int bps, 2261 unsigned int *brr, unsigned int *srr, 2262 unsigned int *cks) 2263 { 2264 unsigned long freq = s->clk_rates[SCI_FCK]; 2265 unsigned int sr, br, prediv, scrate, c; 2266 int err, min_err = INT_MAX; 2267 2268 if (s->port.type != PORT_HSCIF) 2269 freq *= 2; 2270 2271 /* 2272 * Find the combination of sample rate and clock select with the 2273 * smallest deviation from the desired baud rate. 2274 * Prefer high sample rates to maximise the receive margin. 2275 * 2276 * M: Receive margin (%) 2277 * N: Ratio of bit rate to clock (N = sampling rate) 2278 * D: Clock duty (D = 0 to 1.0) 2279 * L: Frame length (L = 9 to 12) 2280 * F: Absolute value of clock frequency deviation 2281 * 2282 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) - 2283 * (|D - 0.5| / N * (1 + F))| 2284 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation. 2285 */ 2286 for_each_sr(sr, s) { 2287 for (c = 0; c <= 3; c++) { 2288 /* integerized formulas from HSCIF documentation */ 2289 prediv = sr * (1 << (2 * c + 1)); 2290 2291 /* 2292 * We need to calculate: 2293 * 2294 * br = freq / (prediv * bps) clamped to [1..256] 2295 * err = freq / (br * prediv) - bps 2296 * 2297 * Watch out for overflow when calculating the desired 2298 * sampling clock rate! 2299 */ 2300 if (bps > UINT_MAX / prediv) 2301 break; 2302 2303 scrate = prediv * bps; 2304 br = DIV_ROUND_CLOSEST(freq, scrate); 2305 br = clamp(br, 1U, 256U); 2306 2307 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps; 2308 if (abs(err) >= abs(min_err)) 2309 continue; 2310 2311 min_err = err; 2312 *brr = br - 1; 2313 *srr = sr - 1; 2314 *cks = c; 2315 2316 if (!err) 2317 goto found; 2318 } 2319 } 2320 2321 found: 2322 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps, 2323 min_err, *brr, *srr + 1, *cks); 2324 return min_err; 2325 } 2326 2327 static void sci_reset(struct uart_port *port) 2328 { 2329 const struct plat_sci_reg *reg; 2330 unsigned int status; 2331 struct sci_port *s = to_sci_port(port); 2332 2333 serial_port_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */ 2334 2335 reg = sci_getreg(port, SCFCR); 2336 if (reg->size) 2337 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); 2338 2339 sci_clear_SCxSR(port, 2340 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) & 2341 SCxSR_BREAK_CLEAR(port)); 2342 if (sci_getreg(port, SCLSR)->size) { 2343 status = serial_port_in(port, SCLSR); 2344 status &= ~(SCLSR_TO | SCLSR_ORER); 2345 serial_port_out(port, SCLSR, status); 2346 } 2347 2348 if (s->rx_trigger > 1) { 2349 if (s->rx_fifo_timeout) { 2350 scif_set_rtrg(port, 1); 2351 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0); 2352 } else { 2353 if (port->type == PORT_SCIFA || 2354 port->type == PORT_SCIFB) 2355 scif_set_rtrg(port, 1); 2356 else 2357 scif_set_rtrg(port, s->rx_trigger); 2358 } 2359 } 2360 } 2361 2362 static void sci_set_termios(struct uart_port *port, struct ktermios *termios, 2363 struct ktermios *old) 2364 { 2365 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits; 2366 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0; 2367 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0; 2368 struct sci_port *s = to_sci_port(port); 2369 const struct plat_sci_reg *reg; 2370 int min_err = INT_MAX, err; 2371 unsigned long max_freq = 0; 2372 int best_clk = -1; 2373 unsigned long flags; 2374 2375 if ((termios->c_cflag & CSIZE) == CS7) 2376 smr_val |= SCSMR_CHR; 2377 if (termios->c_cflag & PARENB) 2378 smr_val |= SCSMR_PE; 2379 if (termios->c_cflag & PARODD) 2380 smr_val |= SCSMR_PE | SCSMR_ODD; 2381 if (termios->c_cflag & CSTOPB) 2382 smr_val |= SCSMR_STOP; 2383 2384 /* 2385 * earlyprintk comes here early on with port->uartclk set to zero. 2386 * the clock framework is not up and running at this point so here 2387 * we assume that 115200 is the maximum baud rate. please note that 2388 * the baud rate is not programmed during earlyprintk - it is assumed 2389 * that the previous boot loader has enabled required clocks and 2390 * setup the baud rate generator hardware for us already. 2391 */ 2392 if (!port->uartclk) { 2393 baud = uart_get_baud_rate(port, termios, old, 0, 115200); 2394 goto done; 2395 } 2396 2397 for (i = 0; i < SCI_NUM_CLKS; i++) 2398 max_freq = max(max_freq, s->clk_rates[i]); 2399 2400 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s)); 2401 if (!baud) 2402 goto done; 2403 2404 /* 2405 * There can be multiple sources for the sampling clock. Find the one 2406 * that gives us the smallest deviation from the desired baud rate. 2407 */ 2408 2409 /* Optional Undivided External Clock */ 2410 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA && 2411 port->type != PORT_SCIFB) { 2412 err = sci_sck_calc(s, baud, &srr1); 2413 if (abs(err) < abs(min_err)) { 2414 best_clk = SCI_SCK; 2415 scr_val = SCSCR_CKE1; 2416 sccks = SCCKS_CKS; 2417 min_err = err; 2418 srr = srr1; 2419 if (!err) 2420 goto done; 2421 } 2422 } 2423 2424 /* Optional BRG Frequency Divided External Clock */ 2425 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) { 2426 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1, 2427 &srr1); 2428 if (abs(err) < abs(min_err)) { 2429 best_clk = SCI_SCIF_CLK; 2430 scr_val = SCSCR_CKE1; 2431 sccks = 0; 2432 min_err = err; 2433 dl = dl1; 2434 srr = srr1; 2435 if (!err) 2436 goto done; 2437 } 2438 } 2439 2440 /* Optional BRG Frequency Divided Internal Clock */ 2441 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) { 2442 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1, 2443 &srr1); 2444 if (abs(err) < abs(min_err)) { 2445 best_clk = SCI_BRG_INT; 2446 scr_val = SCSCR_CKE1; 2447 sccks = SCCKS_XIN; 2448 min_err = err; 2449 dl = dl1; 2450 srr = srr1; 2451 if (!min_err) 2452 goto done; 2453 } 2454 } 2455 2456 /* Divided Functional Clock using standard Bit Rate Register */ 2457 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1); 2458 if (abs(err) < abs(min_err)) { 2459 best_clk = SCI_FCK; 2460 scr_val = 0; 2461 min_err = err; 2462 brr = brr1; 2463 srr = srr1; 2464 cks = cks1; 2465 } 2466 2467 done: 2468 if (best_clk >= 0) 2469 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n", 2470 s->clks[best_clk], baud, min_err); 2471 2472 sci_port_enable(s); 2473 2474 /* 2475 * Program the optional External Baud Rate Generator (BRG) first. 2476 * It controls the mux to select (H)SCK or frequency divided clock. 2477 */ 2478 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) { 2479 serial_port_out(port, SCDL, dl); 2480 serial_port_out(port, SCCKS, sccks); 2481 } 2482 2483 spin_lock_irqsave(&port->lock, flags); 2484 2485 sci_reset(port); 2486 2487 uart_update_timeout(port, termios->c_cflag, baud); 2488 2489 /* byte size and parity */ 2490 switch (termios->c_cflag & CSIZE) { 2491 case CS5: 2492 bits = 7; 2493 break; 2494 case CS6: 2495 bits = 8; 2496 break; 2497 case CS7: 2498 bits = 9; 2499 break; 2500 default: 2501 bits = 10; 2502 break; 2503 } 2504 2505 if (termios->c_cflag & CSTOPB) 2506 bits++; 2507 if (termios->c_cflag & PARENB) 2508 bits++; 2509 2510 if (best_clk >= 0) { 2511 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 2512 switch (srr + 1) { 2513 case 5: smr_val |= SCSMR_SRC_5; break; 2514 case 7: smr_val |= SCSMR_SRC_7; break; 2515 case 11: smr_val |= SCSMR_SRC_11; break; 2516 case 13: smr_val |= SCSMR_SRC_13; break; 2517 case 16: smr_val |= SCSMR_SRC_16; break; 2518 case 17: smr_val |= SCSMR_SRC_17; break; 2519 case 19: smr_val |= SCSMR_SRC_19; break; 2520 case 27: smr_val |= SCSMR_SRC_27; break; 2521 } 2522 smr_val |= cks; 2523 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); 2524 serial_port_out(port, SCSMR, smr_val); 2525 serial_port_out(port, SCBRR, brr); 2526 if (sci_getreg(port, HSSRR)->size) { 2527 unsigned int hssrr = srr | HSCIF_SRE; 2528 /* Calculate deviation from intended rate at the 2529 * center of the last stop bit in sampling clocks. 2530 */ 2531 int last_stop = bits * 2 - 1; 2532 int deviation = DIV_ROUND_CLOSEST(min_err * last_stop * 2533 (int)(srr + 1), 2534 2 * (int)baud); 2535 2536 if (abs(deviation) >= 2) { 2537 /* At least two sampling clocks off at the 2538 * last stop bit; we can increase the error 2539 * margin by shifting the sampling point. 2540 */ 2541 int shift = clamp(deviation / 2, -8, 7); 2542 2543 hssrr |= (shift << HSCIF_SRHP_SHIFT) & 2544 HSCIF_SRHP_MASK; 2545 hssrr |= HSCIF_SRDE; 2546 } 2547 serial_port_out(port, HSSRR, hssrr); 2548 } 2549 2550 /* Wait one bit interval */ 2551 udelay((1000000 + (baud - 1)) / baud); 2552 } else { 2553 /* Don't touch the bit rate configuration */ 2554 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0); 2555 smr_val |= serial_port_in(port, SCSMR) & 2556 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS); 2557 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); 2558 serial_port_out(port, SCSMR, smr_val); 2559 } 2560 2561 sci_init_pins(port, termios->c_cflag); 2562 2563 port->status &= ~UPSTAT_AUTOCTS; 2564 s->autorts = false; 2565 reg = sci_getreg(port, SCFCR); 2566 if (reg->size) { 2567 unsigned short ctrl = serial_port_in(port, SCFCR); 2568 2569 if ((port->flags & UPF_HARD_FLOW) && 2570 (termios->c_cflag & CRTSCTS)) { 2571 /* There is no CTS interrupt to restart the hardware */ 2572 port->status |= UPSTAT_AUTOCTS; 2573 /* MCE is enabled when RTS is raised */ 2574 s->autorts = true; 2575 } 2576 2577 /* 2578 * As we've done a sci_reset() above, ensure we don't 2579 * interfere with the FIFOs while toggling MCE. As the 2580 * reset values could still be set, simply mask them out. 2581 */ 2582 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST); 2583 2584 serial_port_out(port, SCFCR, ctrl); 2585 } 2586 if (port->flags & UPF_HARD_FLOW) { 2587 /* Refresh (Auto) RTS */ 2588 sci_set_mctrl(port, port->mctrl); 2589 } 2590 2591 scr_val |= SCSCR_RE | SCSCR_TE | 2592 (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)); 2593 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); 2594 if ((srr + 1 == 5) && 2595 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) { 2596 /* 2597 * In asynchronous mode, when the sampling rate is 1/5, first 2598 * received data may become invalid on some SCIFA and SCIFB. 2599 * To avoid this problem wait more than 1 serial data time (1 2600 * bit time x serial data number) after setting SCSCR.RE = 1. 2601 */ 2602 udelay(DIV_ROUND_UP(10 * 1000000, baud)); 2603 } 2604 2605 /* 2606 * Calculate delay for 2 DMA buffers (4 FIFO). 2607 * See serial_core.c::uart_update_timeout(). 2608 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above 2609 * function calculates 1 jiffie for the data plus 5 jiffies for the 2610 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA 2611 * buffers (4 FIFO sizes), but when performing a faster transfer, the 2612 * value obtained by this formula is too small. Therefore, if the value 2613 * is smaller than 20ms, use 20ms as the timeout value for DMA. 2614 */ 2615 s->rx_frame = (10000 * bits) / (baud / 100); 2616 #ifdef CONFIG_SERIAL_SH_SCI_DMA 2617 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame; 2618 if (s->rx_timeout < 20) 2619 s->rx_timeout = 20; 2620 #endif 2621 2622 if ((termios->c_cflag & CREAD) != 0) 2623 sci_start_rx(port); 2624 2625 spin_unlock_irqrestore(&port->lock, flags); 2626 2627 sci_port_disable(s); 2628 2629 if (UART_ENABLE_MS(port, termios->c_cflag)) 2630 sci_enable_ms(port); 2631 } 2632 2633 static void sci_pm(struct uart_port *port, unsigned int state, 2634 unsigned int oldstate) 2635 { 2636 struct sci_port *sci_port = to_sci_port(port); 2637 2638 switch (state) { 2639 case UART_PM_STATE_OFF: 2640 sci_port_disable(sci_port); 2641 break; 2642 default: 2643 sci_port_enable(sci_port); 2644 break; 2645 } 2646 } 2647 2648 static const char *sci_type(struct uart_port *port) 2649 { 2650 switch (port->type) { 2651 case PORT_IRDA: 2652 return "irda"; 2653 case PORT_SCI: 2654 return "sci"; 2655 case PORT_SCIF: 2656 return "scif"; 2657 case PORT_SCIFA: 2658 return "scifa"; 2659 case PORT_SCIFB: 2660 return "scifb"; 2661 case PORT_HSCIF: 2662 return "hscif"; 2663 } 2664 2665 return NULL; 2666 } 2667 2668 static int sci_remap_port(struct uart_port *port) 2669 { 2670 struct sci_port *sport = to_sci_port(port); 2671 2672 /* 2673 * Nothing to do if there's already an established membase. 2674 */ 2675 if (port->membase) 2676 return 0; 2677 2678 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { 2679 port->membase = ioremap(port->mapbase, sport->reg_size); 2680 if (unlikely(!port->membase)) { 2681 dev_err(port->dev, "can't remap port#%d\n", port->line); 2682 return -ENXIO; 2683 } 2684 } else { 2685 /* 2686 * For the simple (and majority of) cases where we don't 2687 * need to do any remapping, just cast the cookie 2688 * directly. 2689 */ 2690 port->membase = (void __iomem *)(uintptr_t)port->mapbase; 2691 } 2692 2693 return 0; 2694 } 2695 2696 static void sci_release_port(struct uart_port *port) 2697 { 2698 struct sci_port *sport = to_sci_port(port); 2699 2700 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { 2701 iounmap(port->membase); 2702 port->membase = NULL; 2703 } 2704 2705 release_mem_region(port->mapbase, sport->reg_size); 2706 } 2707 2708 static int sci_request_port(struct uart_port *port) 2709 { 2710 struct resource *res; 2711 struct sci_port *sport = to_sci_port(port); 2712 int ret; 2713 2714 res = request_mem_region(port->mapbase, sport->reg_size, 2715 dev_name(port->dev)); 2716 if (unlikely(res == NULL)) { 2717 dev_err(port->dev, "request_mem_region failed."); 2718 return -EBUSY; 2719 } 2720 2721 ret = sci_remap_port(port); 2722 if (unlikely(ret != 0)) { 2723 release_resource(res); 2724 return ret; 2725 } 2726 2727 return 0; 2728 } 2729 2730 static void sci_config_port(struct uart_port *port, int flags) 2731 { 2732 if (flags & UART_CONFIG_TYPE) { 2733 struct sci_port *sport = to_sci_port(port); 2734 2735 port->type = sport->cfg->type; 2736 sci_request_port(port); 2737 } 2738 } 2739 2740 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser) 2741 { 2742 if (ser->baud_base < 2400) 2743 /* No paper tape reader for Mitch.. */ 2744 return -EINVAL; 2745 2746 return 0; 2747 } 2748 2749 static const struct uart_ops sci_uart_ops = { 2750 .tx_empty = sci_tx_empty, 2751 .set_mctrl = sci_set_mctrl, 2752 .get_mctrl = sci_get_mctrl, 2753 .start_tx = sci_start_tx, 2754 .stop_tx = sci_stop_tx, 2755 .stop_rx = sci_stop_rx, 2756 .enable_ms = sci_enable_ms, 2757 .break_ctl = sci_break_ctl, 2758 .startup = sci_startup, 2759 .shutdown = sci_shutdown, 2760 .flush_buffer = sci_flush_buffer, 2761 .set_termios = sci_set_termios, 2762 .pm = sci_pm, 2763 .type = sci_type, 2764 .release_port = sci_release_port, 2765 .request_port = sci_request_port, 2766 .config_port = sci_config_port, 2767 .verify_port = sci_verify_port, 2768 #ifdef CONFIG_CONSOLE_POLL 2769 .poll_get_char = sci_poll_get_char, 2770 .poll_put_char = sci_poll_put_char, 2771 #endif 2772 }; 2773 2774 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev) 2775 { 2776 const char *clk_names[] = { 2777 [SCI_FCK] = "fck", 2778 [SCI_SCK] = "sck", 2779 [SCI_BRG_INT] = "brg_int", 2780 [SCI_SCIF_CLK] = "scif_clk", 2781 }; 2782 struct clk *clk; 2783 unsigned int i; 2784 2785 if (sci_port->cfg->type == PORT_HSCIF) 2786 clk_names[SCI_SCK] = "hsck"; 2787 2788 for (i = 0; i < SCI_NUM_CLKS; i++) { 2789 clk = devm_clk_get(dev, clk_names[i]); 2790 if (PTR_ERR(clk) == -EPROBE_DEFER) 2791 return -EPROBE_DEFER; 2792 2793 if (IS_ERR(clk) && i == SCI_FCK) { 2794 /* 2795 * "fck" used to be called "sci_ick", and we need to 2796 * maintain DT backward compatibility. 2797 */ 2798 clk = devm_clk_get(dev, "sci_ick"); 2799 if (PTR_ERR(clk) == -EPROBE_DEFER) 2800 return -EPROBE_DEFER; 2801 2802 if (!IS_ERR(clk)) 2803 goto found; 2804 2805 /* 2806 * Not all SH platforms declare a clock lookup entry 2807 * for SCI devices, in which case we need to get the 2808 * global "peripheral_clk" clock. 2809 */ 2810 clk = devm_clk_get(dev, "peripheral_clk"); 2811 if (!IS_ERR(clk)) 2812 goto found; 2813 2814 dev_err(dev, "failed to get %s (%ld)\n", clk_names[i], 2815 PTR_ERR(clk)); 2816 return PTR_ERR(clk); 2817 } 2818 2819 found: 2820 if (IS_ERR(clk)) 2821 dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i], 2822 PTR_ERR(clk)); 2823 else 2824 dev_dbg(dev, "clk %s is %pC rate %lu\n", clk_names[i], 2825 clk, clk_get_rate(clk)); 2826 sci_port->clks[i] = IS_ERR(clk) ? NULL : clk; 2827 } 2828 return 0; 2829 } 2830 2831 static const struct sci_port_params * 2832 sci_probe_regmap(const struct plat_sci_port *cfg) 2833 { 2834 unsigned int regtype; 2835 2836 if (cfg->regtype != SCIx_PROBE_REGTYPE) 2837 return &sci_port_params[cfg->regtype]; 2838 2839 switch (cfg->type) { 2840 case PORT_SCI: 2841 regtype = SCIx_SCI_REGTYPE; 2842 break; 2843 case PORT_IRDA: 2844 regtype = SCIx_IRDA_REGTYPE; 2845 break; 2846 case PORT_SCIFA: 2847 regtype = SCIx_SCIFA_REGTYPE; 2848 break; 2849 case PORT_SCIFB: 2850 regtype = SCIx_SCIFB_REGTYPE; 2851 break; 2852 case PORT_SCIF: 2853 /* 2854 * The SH-4 is a bit of a misnomer here, although that's 2855 * where this particular port layout originated. This 2856 * configuration (or some slight variation thereof) 2857 * remains the dominant model for all SCIFs. 2858 */ 2859 regtype = SCIx_SH4_SCIF_REGTYPE; 2860 break; 2861 case PORT_HSCIF: 2862 regtype = SCIx_HSCIF_REGTYPE; 2863 break; 2864 default: 2865 pr_err("Can't probe register map for given port\n"); 2866 return NULL; 2867 } 2868 2869 return &sci_port_params[regtype]; 2870 } 2871 2872 static int sci_init_single(struct platform_device *dev, 2873 struct sci_port *sci_port, unsigned int index, 2874 const struct plat_sci_port *p, bool early) 2875 { 2876 struct uart_port *port = &sci_port->port; 2877 const struct resource *res; 2878 unsigned int i; 2879 int ret; 2880 2881 sci_port->cfg = p; 2882 2883 port->ops = &sci_uart_ops; 2884 port->iotype = UPIO_MEM; 2885 port->line = index; 2886 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SH_SCI_CONSOLE); 2887 2888 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 2889 if (res == NULL) 2890 return -ENOMEM; 2891 2892 port->mapbase = res->start; 2893 sci_port->reg_size = resource_size(res); 2894 2895 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) { 2896 if (i) 2897 sci_port->irqs[i] = platform_get_irq_optional(dev, i); 2898 else 2899 sci_port->irqs[i] = platform_get_irq(dev, i); 2900 } 2901 2902 /* The SCI generates several interrupts. They can be muxed together or 2903 * connected to different interrupt lines. In the muxed case only one 2904 * interrupt resource is specified as there is only one interrupt ID. 2905 * In the non-muxed case, up to 6 interrupt signals might be generated 2906 * from the SCI, however those signals might have their own individual 2907 * interrupt ID numbers, or muxed together with another interrupt. 2908 */ 2909 if (sci_port->irqs[0] < 0) 2910 return -ENXIO; 2911 2912 if (sci_port->irqs[1] < 0) 2913 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++) 2914 sci_port->irqs[i] = sci_port->irqs[0]; 2915 2916 sci_port->params = sci_probe_regmap(p); 2917 if (unlikely(sci_port->params == NULL)) 2918 return -EINVAL; 2919 2920 switch (p->type) { 2921 case PORT_SCIFB: 2922 sci_port->rx_trigger = 48; 2923 break; 2924 case PORT_HSCIF: 2925 sci_port->rx_trigger = 64; 2926 break; 2927 case PORT_SCIFA: 2928 sci_port->rx_trigger = 32; 2929 break; 2930 case PORT_SCIF: 2931 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) 2932 /* RX triggering not implemented for this IP */ 2933 sci_port->rx_trigger = 1; 2934 else 2935 sci_port->rx_trigger = 8; 2936 break; 2937 default: 2938 sci_port->rx_trigger = 1; 2939 break; 2940 } 2941 2942 sci_port->rx_fifo_timeout = 0; 2943 sci_port->hscif_tot = 0; 2944 2945 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't 2946 * match the SoC datasheet, this should be investigated. Let platform 2947 * data override the sampling rate for now. 2948 */ 2949 sci_port->sampling_rate_mask = p->sampling_rate 2950 ? SCI_SR(p->sampling_rate) 2951 : sci_port->params->sampling_rate_mask; 2952 2953 if (!early) { 2954 ret = sci_init_clocks(sci_port, &dev->dev); 2955 if (ret < 0) 2956 return ret; 2957 2958 port->dev = &dev->dev; 2959 2960 pm_runtime_enable(&dev->dev); 2961 } 2962 2963 port->type = p->type; 2964 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags; 2965 port->fifosize = sci_port->params->fifosize; 2966 2967 if (port->type == PORT_SCI) { 2968 if (sci_port->reg_size >= 0x20) 2969 port->regshift = 2; 2970 else 2971 port->regshift = 1; 2972 } 2973 2974 /* 2975 * The UART port needs an IRQ value, so we peg this to the RX IRQ 2976 * for the multi-IRQ ports, which is where we are primarily 2977 * concerned with the shutdown path synchronization. 2978 * 2979 * For the muxed case there's nothing more to do. 2980 */ 2981 port->irq = sci_port->irqs[SCIx_RXI_IRQ]; 2982 port->irqflags = 0; 2983 2984 port->serial_in = sci_serial_in; 2985 port->serial_out = sci_serial_out; 2986 2987 return 0; 2988 } 2989 2990 static void sci_cleanup_single(struct sci_port *port) 2991 { 2992 pm_runtime_disable(port->port.dev); 2993 } 2994 2995 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ 2996 defined(CONFIG_SERIAL_SH_SCI_EARLYCON) 2997 static void serial_console_putchar(struct uart_port *port, int ch) 2998 { 2999 sci_poll_put_char(port, ch); 3000 } 3001 3002 /* 3003 * Print a string to the serial port trying not to disturb 3004 * any possible real use of the port... 3005 */ 3006 static void serial_console_write(struct console *co, const char *s, 3007 unsigned count) 3008 { 3009 struct sci_port *sci_port = &sci_ports[co->index]; 3010 struct uart_port *port = &sci_port->port; 3011 unsigned short bits, ctrl, ctrl_temp; 3012 unsigned long flags; 3013 int locked = 1; 3014 3015 if (port->sysrq) 3016 locked = 0; 3017 else if (oops_in_progress) 3018 locked = spin_trylock_irqsave(&port->lock, flags); 3019 else 3020 spin_lock_irqsave(&port->lock, flags); 3021 3022 /* first save SCSCR then disable interrupts, keep clock source */ 3023 ctrl = serial_port_in(port, SCSCR); 3024 ctrl_temp = SCSCR_RE | SCSCR_TE | 3025 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) | 3026 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0)); 3027 serial_port_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot); 3028 3029 uart_console_write(port, s, count, serial_console_putchar); 3030 3031 /* wait until fifo is empty and last bit has been transmitted */ 3032 bits = SCxSR_TDxE(port) | SCxSR_TEND(port); 3033 while ((serial_port_in(port, SCxSR) & bits) != bits) 3034 cpu_relax(); 3035 3036 /* restore the SCSCR */ 3037 serial_port_out(port, SCSCR, ctrl); 3038 3039 if (locked) 3040 spin_unlock_irqrestore(&port->lock, flags); 3041 } 3042 3043 static int serial_console_setup(struct console *co, char *options) 3044 { 3045 struct sci_port *sci_port; 3046 struct uart_port *port; 3047 int baud = 115200; 3048 int bits = 8; 3049 int parity = 'n'; 3050 int flow = 'n'; 3051 int ret; 3052 3053 /* 3054 * Refuse to handle any bogus ports. 3055 */ 3056 if (co->index < 0 || co->index >= SCI_NPORTS) 3057 return -ENODEV; 3058 3059 sci_port = &sci_ports[co->index]; 3060 port = &sci_port->port; 3061 3062 /* 3063 * Refuse to handle uninitialized ports. 3064 */ 3065 if (!port->ops) 3066 return -ENODEV; 3067 3068 ret = sci_remap_port(port); 3069 if (unlikely(ret != 0)) 3070 return ret; 3071 3072 if (options) 3073 uart_parse_options(options, &baud, &parity, &bits, &flow); 3074 3075 return uart_set_options(port, co, baud, parity, bits, flow); 3076 } 3077 3078 static struct console serial_console = { 3079 .name = "ttySC", 3080 .device = uart_console_device, 3081 .write = serial_console_write, 3082 .setup = serial_console_setup, 3083 .flags = CON_PRINTBUFFER, 3084 .index = -1, 3085 .data = &sci_uart_driver, 3086 }; 3087 3088 #ifdef CONFIG_SUPERH 3089 static struct console early_serial_console = { 3090 .name = "early_ttySC", 3091 .write = serial_console_write, 3092 .flags = CON_PRINTBUFFER, 3093 .index = -1, 3094 }; 3095 3096 static char early_serial_buf[32]; 3097 3098 static int sci_probe_earlyprintk(struct platform_device *pdev) 3099 { 3100 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev); 3101 3102 if (early_serial_console.data) 3103 return -EEXIST; 3104 3105 early_serial_console.index = pdev->id; 3106 3107 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true); 3108 3109 serial_console_setup(&early_serial_console, early_serial_buf); 3110 3111 if (!strstr(early_serial_buf, "keep")) 3112 early_serial_console.flags |= CON_BOOT; 3113 3114 register_console(&early_serial_console); 3115 return 0; 3116 } 3117 #endif 3118 3119 #define SCI_CONSOLE (&serial_console) 3120 3121 #else 3122 static inline int sci_probe_earlyprintk(struct platform_device *pdev) 3123 { 3124 return -EINVAL; 3125 } 3126 3127 #define SCI_CONSOLE NULL 3128 3129 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */ 3130 3131 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized"; 3132 3133 static DEFINE_MUTEX(sci_uart_registration_lock); 3134 static struct uart_driver sci_uart_driver = { 3135 .owner = THIS_MODULE, 3136 .driver_name = "sci", 3137 .dev_name = "ttySC", 3138 .major = SCI_MAJOR, 3139 .minor = SCI_MINOR_START, 3140 .nr = SCI_NPORTS, 3141 .cons = SCI_CONSOLE, 3142 }; 3143 3144 static int sci_remove(struct platform_device *dev) 3145 { 3146 struct sci_port *port = platform_get_drvdata(dev); 3147 unsigned int type = port->port.type; /* uart_remove_... clears it */ 3148 3149 sci_ports_in_use &= ~BIT(port->port.line); 3150 uart_remove_one_port(&sci_uart_driver, &port->port); 3151 3152 sci_cleanup_single(port); 3153 3154 if (port->port.fifosize > 1) 3155 device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger); 3156 if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF) 3157 device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout); 3158 3159 return 0; 3160 } 3161 3162 3163 #define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype)) 3164 #define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16) 3165 #define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff) 3166 3167 static const struct of_device_id of_sci_match[] = { 3168 /* SoC-specific types */ 3169 { 3170 .compatible = "renesas,scif-r7s72100", 3171 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE), 3172 }, 3173 { 3174 .compatible = "renesas,scif-r7s9210", 3175 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE), 3176 }, 3177 /* Family-specific types */ 3178 { 3179 .compatible = "renesas,rcar-gen1-scif", 3180 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3181 }, { 3182 .compatible = "renesas,rcar-gen2-scif", 3183 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3184 }, { 3185 .compatible = "renesas,rcar-gen3-scif", 3186 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3187 }, 3188 /* Generic types */ 3189 { 3190 .compatible = "renesas,scif", 3191 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE), 3192 }, { 3193 .compatible = "renesas,scifa", 3194 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE), 3195 }, { 3196 .compatible = "renesas,scifb", 3197 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE), 3198 }, { 3199 .compatible = "renesas,hscif", 3200 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE), 3201 }, { 3202 .compatible = "renesas,sci", 3203 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE), 3204 }, { 3205 /* Terminator */ 3206 }, 3207 }; 3208 MODULE_DEVICE_TABLE(of, of_sci_match); 3209 3210 static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev, 3211 unsigned int *dev_id) 3212 { 3213 struct device_node *np = pdev->dev.of_node; 3214 struct plat_sci_port *p; 3215 struct sci_port *sp; 3216 const void *data; 3217 int id; 3218 3219 if (!IS_ENABLED(CONFIG_OF) || !np) 3220 return NULL; 3221 3222 data = of_device_get_match_data(&pdev->dev); 3223 3224 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL); 3225 if (!p) 3226 return NULL; 3227 3228 /* Get the line number from the aliases node. */ 3229 id = of_alias_get_id(np, "serial"); 3230 if (id < 0 && ~sci_ports_in_use) 3231 id = ffz(sci_ports_in_use); 3232 if (id < 0) { 3233 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id); 3234 return NULL; 3235 } 3236 if (id >= ARRAY_SIZE(sci_ports)) { 3237 dev_err(&pdev->dev, "serial%d out of range\n", id); 3238 return NULL; 3239 } 3240 3241 sp = &sci_ports[id]; 3242 *dev_id = id; 3243 3244 p->type = SCI_OF_TYPE(data); 3245 p->regtype = SCI_OF_REGTYPE(data); 3246 3247 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts"); 3248 3249 return p; 3250 } 3251 3252 static int sci_probe_single(struct platform_device *dev, 3253 unsigned int index, 3254 struct plat_sci_port *p, 3255 struct sci_port *sciport) 3256 { 3257 int ret; 3258 3259 /* Sanity check */ 3260 if (unlikely(index >= SCI_NPORTS)) { 3261 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n", 3262 index+1, SCI_NPORTS); 3263 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n"); 3264 return -EINVAL; 3265 } 3266 BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8); 3267 if (sci_ports_in_use & BIT(index)) 3268 return -EBUSY; 3269 3270 mutex_lock(&sci_uart_registration_lock); 3271 if (!sci_uart_driver.state) { 3272 ret = uart_register_driver(&sci_uart_driver); 3273 if (ret) { 3274 mutex_unlock(&sci_uart_registration_lock); 3275 return ret; 3276 } 3277 } 3278 mutex_unlock(&sci_uart_registration_lock); 3279 3280 ret = sci_init_single(dev, sciport, index, p, false); 3281 if (ret) 3282 return ret; 3283 3284 sciport->gpios = mctrl_gpio_init(&sciport->port, 0); 3285 if (IS_ERR(sciport->gpios)) 3286 return PTR_ERR(sciport->gpios); 3287 3288 if (sciport->has_rtscts) { 3289 if (mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_CTS) || 3290 mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_RTS)) { 3291 dev_err(&dev->dev, "Conflicting RTS/CTS config\n"); 3292 return -EINVAL; 3293 } 3294 sciport->port.flags |= UPF_HARD_FLOW; 3295 } 3296 3297 ret = uart_add_one_port(&sci_uart_driver, &sciport->port); 3298 if (ret) { 3299 sci_cleanup_single(sciport); 3300 return ret; 3301 } 3302 3303 return 0; 3304 } 3305 3306 static int sci_probe(struct platform_device *dev) 3307 { 3308 struct plat_sci_port *p; 3309 struct sci_port *sp; 3310 unsigned int dev_id; 3311 int ret; 3312 3313 /* 3314 * If we've come here via earlyprintk initialization, head off to 3315 * the special early probe. We don't have sufficient device state 3316 * to make it beyond this yet. 3317 */ 3318 #ifdef CONFIG_SUPERH 3319 if (is_sh_early_platform_device(dev)) 3320 return sci_probe_earlyprintk(dev); 3321 #endif 3322 3323 if (dev->dev.of_node) { 3324 p = sci_parse_dt(dev, &dev_id); 3325 if (p == NULL) 3326 return -EINVAL; 3327 } else { 3328 p = dev->dev.platform_data; 3329 if (p == NULL) { 3330 dev_err(&dev->dev, "no platform data supplied\n"); 3331 return -EINVAL; 3332 } 3333 3334 dev_id = dev->id; 3335 } 3336 3337 sp = &sci_ports[dev_id]; 3338 platform_set_drvdata(dev, sp); 3339 3340 ret = sci_probe_single(dev, dev_id, p, sp); 3341 if (ret) 3342 return ret; 3343 3344 if (sp->port.fifosize > 1) { 3345 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_trigger); 3346 if (ret) 3347 return ret; 3348 } 3349 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB || 3350 sp->port.type == PORT_HSCIF) { 3351 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout); 3352 if (ret) { 3353 if (sp->port.fifosize > 1) { 3354 device_remove_file(&dev->dev, 3355 &dev_attr_rx_fifo_trigger); 3356 } 3357 return ret; 3358 } 3359 } 3360 3361 #ifdef CONFIG_SH_STANDARD_BIOS 3362 sh_bios_gdb_detach(); 3363 #endif 3364 3365 sci_ports_in_use |= BIT(dev_id); 3366 return 0; 3367 } 3368 3369 static __maybe_unused int sci_suspend(struct device *dev) 3370 { 3371 struct sci_port *sport = dev_get_drvdata(dev); 3372 3373 if (sport) 3374 uart_suspend_port(&sci_uart_driver, &sport->port); 3375 3376 return 0; 3377 } 3378 3379 static __maybe_unused int sci_resume(struct device *dev) 3380 { 3381 struct sci_port *sport = dev_get_drvdata(dev); 3382 3383 if (sport) 3384 uart_resume_port(&sci_uart_driver, &sport->port); 3385 3386 return 0; 3387 } 3388 3389 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume); 3390 3391 static struct platform_driver sci_driver = { 3392 .probe = sci_probe, 3393 .remove = sci_remove, 3394 .driver = { 3395 .name = "sh-sci", 3396 .pm = &sci_dev_pm_ops, 3397 .of_match_table = of_match_ptr(of_sci_match), 3398 }, 3399 }; 3400 3401 static int __init sci_init(void) 3402 { 3403 pr_info("%s\n", banner); 3404 3405 return platform_driver_register(&sci_driver); 3406 } 3407 3408 static void __exit sci_exit(void) 3409 { 3410 platform_driver_unregister(&sci_driver); 3411 3412 if (sci_uart_driver.state) 3413 uart_unregister_driver(&sci_uart_driver); 3414 } 3415 3416 #if defined(CONFIG_SUPERH) && defined(CONFIG_SERIAL_SH_SCI_CONSOLE) 3417 sh_early_platform_init_buffer("earlyprintk", &sci_driver, 3418 early_serial_buf, ARRAY_SIZE(early_serial_buf)); 3419 #endif 3420 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON 3421 static struct plat_sci_port port_cfg __initdata; 3422 3423 static int __init early_console_setup(struct earlycon_device *device, 3424 int type) 3425 { 3426 if (!device->port.membase) 3427 return -ENODEV; 3428 3429 device->port.serial_in = sci_serial_in; 3430 device->port.serial_out = sci_serial_out; 3431 device->port.type = type; 3432 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port)); 3433 port_cfg.type = type; 3434 sci_ports[0].cfg = &port_cfg; 3435 sci_ports[0].params = sci_probe_regmap(&port_cfg); 3436 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR); 3437 sci_serial_out(&sci_ports[0].port, SCSCR, 3438 SCSCR_RE | SCSCR_TE | port_cfg.scscr); 3439 3440 device->con->write = serial_console_write; 3441 return 0; 3442 } 3443 static int __init sci_early_console_setup(struct earlycon_device *device, 3444 const char *opt) 3445 { 3446 return early_console_setup(device, PORT_SCI); 3447 } 3448 static int __init scif_early_console_setup(struct earlycon_device *device, 3449 const char *opt) 3450 { 3451 return early_console_setup(device, PORT_SCIF); 3452 } 3453 static int __init rzscifa_early_console_setup(struct earlycon_device *device, 3454 const char *opt) 3455 { 3456 port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE; 3457 return early_console_setup(device, PORT_SCIF); 3458 } 3459 static int __init scifa_early_console_setup(struct earlycon_device *device, 3460 const char *opt) 3461 { 3462 return early_console_setup(device, PORT_SCIFA); 3463 } 3464 static int __init scifb_early_console_setup(struct earlycon_device *device, 3465 const char *opt) 3466 { 3467 return early_console_setup(device, PORT_SCIFB); 3468 } 3469 static int __init hscif_early_console_setup(struct earlycon_device *device, 3470 const char *opt) 3471 { 3472 return early_console_setup(device, PORT_HSCIF); 3473 } 3474 3475 OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup); 3476 OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup); 3477 OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup); 3478 OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup); 3479 OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup); 3480 OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup); 3481 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */ 3482 3483 module_init(sci_init); 3484 module_exit(sci_exit); 3485 3486 MODULE_LICENSE("GPL"); 3487 MODULE_ALIAS("platform:sh-sci"); 3488 MODULE_AUTHOR("Paul Mundt"); 3489 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver"); 3490