1 /* 2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) 3 * 4 * Copyright (C) 2002 - 2011 Paul Mundt 5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007). 6 * 7 * based off of the old drivers/char/sh-sci.c by: 8 * 9 * Copyright (C) 1999, 2000 Niibe Yutaka 10 * Copyright (C) 2000 Sugioka Toshinobu 11 * Modified to support multiple serial ports. Stuart Menefy (May 2000). 12 * Modified to support SecureEdge. David McCullough (2002) 13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003). 14 * Removed SH7300 support (Jul 2007). 15 * 16 * This file is subject to the terms and conditions of the GNU General Public 17 * License. See the file "COPYING" in the main directory of this archive 18 * for more details. 19 */ 20 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 21 #define SUPPORT_SYSRQ 22 #endif 23 24 #undef DEBUG 25 26 #include <linux/clk.h> 27 #include <linux/console.h> 28 #include <linux/ctype.h> 29 #include <linux/cpufreq.h> 30 #include <linux/delay.h> 31 #include <linux/dmaengine.h> 32 #include <linux/dma-mapping.h> 33 #include <linux/err.h> 34 #include <linux/errno.h> 35 #include <linux/init.h> 36 #include <linux/interrupt.h> 37 #include <linux/ioport.h> 38 #include <linux/major.h> 39 #include <linux/module.h> 40 #include <linux/mm.h> 41 #include <linux/notifier.h> 42 #include <linux/platform_device.h> 43 #include <linux/pm_runtime.h> 44 #include <linux/scatterlist.h> 45 #include <linux/serial.h> 46 #include <linux/serial_sci.h> 47 #include <linux/sh_dma.h> 48 #include <linux/slab.h> 49 #include <linux/string.h> 50 #include <linux/sysrq.h> 51 #include <linux/timer.h> 52 #include <linux/tty.h> 53 #include <linux/tty_flip.h> 54 55 #ifdef CONFIG_SUPERH 56 #include <asm/sh_bios.h> 57 #endif 58 59 #include "sh-sci.h" 60 61 /* Offsets into the sci_port->irqs array */ 62 enum { 63 SCIx_ERI_IRQ, 64 SCIx_RXI_IRQ, 65 SCIx_TXI_IRQ, 66 SCIx_BRI_IRQ, 67 SCIx_NR_IRQS, 68 69 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */ 70 }; 71 72 #define SCIx_IRQ_IS_MUXED(port) \ 73 ((port)->irqs[SCIx_ERI_IRQ] == \ 74 (port)->irqs[SCIx_RXI_IRQ]) || \ 75 ((port)->irqs[SCIx_ERI_IRQ] && \ 76 ((port)->irqs[SCIx_RXI_IRQ] < 0)) 77 78 struct sci_port { 79 struct uart_port port; 80 81 /* Platform configuration */ 82 struct plat_sci_port *cfg; 83 int overrun_bit; 84 unsigned int error_mask; 85 unsigned int sampling_rate; 86 87 88 /* Break timer */ 89 struct timer_list break_timer; 90 int break_flag; 91 92 /* Interface clock */ 93 struct clk *iclk; 94 /* Function clock */ 95 struct clk *fclk; 96 97 int irqs[SCIx_NR_IRQS]; 98 char *irqstr[SCIx_NR_IRQS]; 99 100 struct dma_chan *chan_tx; 101 struct dma_chan *chan_rx; 102 103 #ifdef CONFIG_SERIAL_SH_SCI_DMA 104 struct dma_async_tx_descriptor *desc_tx; 105 struct dma_async_tx_descriptor *desc_rx[2]; 106 dma_cookie_t cookie_tx; 107 dma_cookie_t cookie_rx[2]; 108 dma_cookie_t active_rx; 109 struct scatterlist sg_tx; 110 unsigned int sg_len_tx; 111 struct scatterlist sg_rx[2]; 112 size_t buf_len_rx; 113 struct sh_dmae_slave param_tx; 114 struct sh_dmae_slave param_rx; 115 struct work_struct work_tx; 116 struct work_struct work_rx; 117 struct timer_list rx_timer; 118 unsigned int rx_timeout; 119 #endif 120 121 struct notifier_block freq_transition; 122 }; 123 124 /* Function prototypes */ 125 static void sci_start_tx(struct uart_port *port); 126 static void sci_stop_tx(struct uart_port *port); 127 static void sci_start_rx(struct uart_port *port); 128 129 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS 130 131 static struct sci_port sci_ports[SCI_NPORTS]; 132 static struct uart_driver sci_uart_driver; 133 134 static inline struct sci_port * 135 to_sci_port(struct uart_port *uart) 136 { 137 return container_of(uart, struct sci_port, port); 138 } 139 140 struct plat_sci_reg { 141 u8 offset, size; 142 }; 143 144 /* Helper for invalidating specific entries of an inherited map. */ 145 #define sci_reg_invalid { .offset = 0, .size = 0 } 146 147 static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { 148 [SCIx_PROBE_REGTYPE] = { 149 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid, 150 }, 151 152 /* 153 * Common SCI definitions, dependent on the port's regshift 154 * value. 155 */ 156 [SCIx_SCI_REGTYPE] = { 157 [SCSMR] = { 0x00, 8 }, 158 [SCBRR] = { 0x01, 8 }, 159 [SCSCR] = { 0x02, 8 }, 160 [SCxTDR] = { 0x03, 8 }, 161 [SCxSR] = { 0x04, 8 }, 162 [SCxRDR] = { 0x05, 8 }, 163 [SCFCR] = sci_reg_invalid, 164 [SCFDR] = sci_reg_invalid, 165 [SCTFDR] = sci_reg_invalid, 166 [SCRFDR] = sci_reg_invalid, 167 [SCSPTR] = sci_reg_invalid, 168 [SCLSR] = sci_reg_invalid, 169 [HSSRR] = sci_reg_invalid, 170 }, 171 172 /* 173 * Common definitions for legacy IrDA ports, dependent on 174 * regshift value. 175 */ 176 [SCIx_IRDA_REGTYPE] = { 177 [SCSMR] = { 0x00, 8 }, 178 [SCBRR] = { 0x01, 8 }, 179 [SCSCR] = { 0x02, 8 }, 180 [SCxTDR] = { 0x03, 8 }, 181 [SCxSR] = { 0x04, 8 }, 182 [SCxRDR] = { 0x05, 8 }, 183 [SCFCR] = { 0x06, 8 }, 184 [SCFDR] = { 0x07, 16 }, 185 [SCTFDR] = sci_reg_invalid, 186 [SCRFDR] = sci_reg_invalid, 187 [SCSPTR] = sci_reg_invalid, 188 [SCLSR] = sci_reg_invalid, 189 [HSSRR] = sci_reg_invalid, 190 }, 191 192 /* 193 * Common SCIFA definitions. 194 */ 195 [SCIx_SCIFA_REGTYPE] = { 196 [SCSMR] = { 0x00, 16 }, 197 [SCBRR] = { 0x04, 8 }, 198 [SCSCR] = { 0x08, 16 }, 199 [SCxTDR] = { 0x20, 8 }, 200 [SCxSR] = { 0x14, 16 }, 201 [SCxRDR] = { 0x24, 8 }, 202 [SCFCR] = { 0x18, 16 }, 203 [SCFDR] = { 0x1c, 16 }, 204 [SCTFDR] = sci_reg_invalid, 205 [SCRFDR] = sci_reg_invalid, 206 [SCSPTR] = sci_reg_invalid, 207 [SCLSR] = sci_reg_invalid, 208 [HSSRR] = sci_reg_invalid, 209 }, 210 211 /* 212 * Common SCIFB definitions. 213 */ 214 [SCIx_SCIFB_REGTYPE] = { 215 [SCSMR] = { 0x00, 16 }, 216 [SCBRR] = { 0x04, 8 }, 217 [SCSCR] = { 0x08, 16 }, 218 [SCxTDR] = { 0x40, 8 }, 219 [SCxSR] = { 0x14, 16 }, 220 [SCxRDR] = { 0x60, 8 }, 221 [SCFCR] = { 0x18, 16 }, 222 [SCFDR] = sci_reg_invalid, 223 [SCTFDR] = { 0x38, 16 }, 224 [SCRFDR] = { 0x3c, 16 }, 225 [SCSPTR] = sci_reg_invalid, 226 [SCLSR] = sci_reg_invalid, 227 [HSSRR] = sci_reg_invalid, 228 }, 229 230 /* 231 * Common SH-2(A) SCIF definitions for ports with FIFO data 232 * count registers. 233 */ 234 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = { 235 [SCSMR] = { 0x00, 16 }, 236 [SCBRR] = { 0x04, 8 }, 237 [SCSCR] = { 0x08, 16 }, 238 [SCxTDR] = { 0x0c, 8 }, 239 [SCxSR] = { 0x10, 16 }, 240 [SCxRDR] = { 0x14, 8 }, 241 [SCFCR] = { 0x18, 16 }, 242 [SCFDR] = { 0x1c, 16 }, 243 [SCTFDR] = sci_reg_invalid, 244 [SCRFDR] = sci_reg_invalid, 245 [SCSPTR] = { 0x20, 16 }, 246 [SCLSR] = { 0x24, 16 }, 247 [HSSRR] = sci_reg_invalid, 248 }, 249 250 /* 251 * Common SH-3 SCIF definitions. 252 */ 253 [SCIx_SH3_SCIF_REGTYPE] = { 254 [SCSMR] = { 0x00, 8 }, 255 [SCBRR] = { 0x02, 8 }, 256 [SCSCR] = { 0x04, 8 }, 257 [SCxTDR] = { 0x06, 8 }, 258 [SCxSR] = { 0x08, 16 }, 259 [SCxRDR] = { 0x0a, 8 }, 260 [SCFCR] = { 0x0c, 8 }, 261 [SCFDR] = { 0x0e, 16 }, 262 [SCTFDR] = sci_reg_invalid, 263 [SCRFDR] = sci_reg_invalid, 264 [SCSPTR] = sci_reg_invalid, 265 [SCLSR] = sci_reg_invalid, 266 [HSSRR] = sci_reg_invalid, 267 }, 268 269 /* 270 * Common SH-4(A) SCIF(B) definitions. 271 */ 272 [SCIx_SH4_SCIF_REGTYPE] = { 273 [SCSMR] = { 0x00, 16 }, 274 [SCBRR] = { 0x04, 8 }, 275 [SCSCR] = { 0x08, 16 }, 276 [SCxTDR] = { 0x0c, 8 }, 277 [SCxSR] = { 0x10, 16 }, 278 [SCxRDR] = { 0x14, 8 }, 279 [SCFCR] = { 0x18, 16 }, 280 [SCFDR] = { 0x1c, 16 }, 281 [SCTFDR] = sci_reg_invalid, 282 [SCRFDR] = sci_reg_invalid, 283 [SCSPTR] = { 0x20, 16 }, 284 [SCLSR] = { 0x24, 16 }, 285 [HSSRR] = sci_reg_invalid, 286 }, 287 288 /* 289 * Common HSCIF definitions. 290 */ 291 [SCIx_HSCIF_REGTYPE] = { 292 [SCSMR] = { 0x00, 16 }, 293 [SCBRR] = { 0x04, 8 }, 294 [SCSCR] = { 0x08, 16 }, 295 [SCxTDR] = { 0x0c, 8 }, 296 [SCxSR] = { 0x10, 16 }, 297 [SCxRDR] = { 0x14, 8 }, 298 [SCFCR] = { 0x18, 16 }, 299 [SCFDR] = { 0x1c, 16 }, 300 [SCTFDR] = sci_reg_invalid, 301 [SCRFDR] = sci_reg_invalid, 302 [SCSPTR] = { 0x20, 16 }, 303 [SCLSR] = { 0x24, 16 }, 304 [HSSRR] = { 0x40, 16 }, 305 }, 306 307 /* 308 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR 309 * register. 310 */ 311 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = { 312 [SCSMR] = { 0x00, 16 }, 313 [SCBRR] = { 0x04, 8 }, 314 [SCSCR] = { 0x08, 16 }, 315 [SCxTDR] = { 0x0c, 8 }, 316 [SCxSR] = { 0x10, 16 }, 317 [SCxRDR] = { 0x14, 8 }, 318 [SCFCR] = { 0x18, 16 }, 319 [SCFDR] = { 0x1c, 16 }, 320 [SCTFDR] = sci_reg_invalid, 321 [SCRFDR] = sci_reg_invalid, 322 [SCSPTR] = sci_reg_invalid, 323 [SCLSR] = { 0x24, 16 }, 324 [HSSRR] = sci_reg_invalid, 325 }, 326 327 /* 328 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data 329 * count registers. 330 */ 331 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = { 332 [SCSMR] = { 0x00, 16 }, 333 [SCBRR] = { 0x04, 8 }, 334 [SCSCR] = { 0x08, 16 }, 335 [SCxTDR] = { 0x0c, 8 }, 336 [SCxSR] = { 0x10, 16 }, 337 [SCxRDR] = { 0x14, 8 }, 338 [SCFCR] = { 0x18, 16 }, 339 [SCFDR] = { 0x1c, 16 }, 340 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */ 341 [SCRFDR] = { 0x20, 16 }, 342 [SCSPTR] = { 0x24, 16 }, 343 [SCLSR] = { 0x28, 16 }, 344 [HSSRR] = sci_reg_invalid, 345 }, 346 347 /* 348 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR 349 * registers. 350 */ 351 [SCIx_SH7705_SCIF_REGTYPE] = { 352 [SCSMR] = { 0x00, 16 }, 353 [SCBRR] = { 0x04, 8 }, 354 [SCSCR] = { 0x08, 16 }, 355 [SCxTDR] = { 0x20, 8 }, 356 [SCxSR] = { 0x14, 16 }, 357 [SCxRDR] = { 0x24, 8 }, 358 [SCFCR] = { 0x18, 16 }, 359 [SCFDR] = { 0x1c, 16 }, 360 [SCTFDR] = sci_reg_invalid, 361 [SCRFDR] = sci_reg_invalid, 362 [SCSPTR] = sci_reg_invalid, 363 [SCLSR] = sci_reg_invalid, 364 [HSSRR] = sci_reg_invalid, 365 }, 366 }; 367 368 #define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset) 369 370 /* 371 * The "offset" here is rather misleading, in that it refers to an enum 372 * value relative to the port mapping rather than the fixed offset 373 * itself, which needs to be manually retrieved from the platform's 374 * register map for the given port. 375 */ 376 static unsigned int sci_serial_in(struct uart_port *p, int offset) 377 { 378 struct plat_sci_reg *reg = sci_getreg(p, offset); 379 380 if (reg->size == 8) 381 return ioread8(p->membase + (reg->offset << p->regshift)); 382 else if (reg->size == 16) 383 return ioread16(p->membase + (reg->offset << p->regshift)); 384 else 385 WARN(1, "Invalid register access\n"); 386 387 return 0; 388 } 389 390 static void sci_serial_out(struct uart_port *p, int offset, int value) 391 { 392 struct plat_sci_reg *reg = sci_getreg(p, offset); 393 394 if (reg->size == 8) 395 iowrite8(value, p->membase + (reg->offset << p->regshift)); 396 else if (reg->size == 16) 397 iowrite16(value, p->membase + (reg->offset << p->regshift)); 398 else 399 WARN(1, "Invalid register access\n"); 400 } 401 402 static int sci_probe_regmap(struct plat_sci_port *cfg) 403 { 404 switch (cfg->type) { 405 case PORT_SCI: 406 cfg->regtype = SCIx_SCI_REGTYPE; 407 break; 408 case PORT_IRDA: 409 cfg->regtype = SCIx_IRDA_REGTYPE; 410 break; 411 case PORT_SCIFA: 412 cfg->regtype = SCIx_SCIFA_REGTYPE; 413 break; 414 case PORT_SCIFB: 415 cfg->regtype = SCIx_SCIFB_REGTYPE; 416 break; 417 case PORT_SCIF: 418 /* 419 * The SH-4 is a bit of a misnomer here, although that's 420 * where this particular port layout originated. This 421 * configuration (or some slight variation thereof) 422 * remains the dominant model for all SCIFs. 423 */ 424 cfg->regtype = SCIx_SH4_SCIF_REGTYPE; 425 break; 426 case PORT_HSCIF: 427 cfg->regtype = SCIx_HSCIF_REGTYPE; 428 break; 429 default: 430 printk(KERN_ERR "Can't probe register map for given port\n"); 431 return -EINVAL; 432 } 433 434 return 0; 435 } 436 437 static void sci_port_enable(struct sci_port *sci_port) 438 { 439 if (!sci_port->port.dev) 440 return; 441 442 pm_runtime_get_sync(sci_port->port.dev); 443 444 clk_prepare_enable(sci_port->iclk); 445 sci_port->port.uartclk = clk_get_rate(sci_port->iclk); 446 clk_prepare_enable(sci_port->fclk); 447 } 448 449 static void sci_port_disable(struct sci_port *sci_port) 450 { 451 if (!sci_port->port.dev) 452 return; 453 454 /* Cancel the break timer to ensure that the timer handler will not try 455 * to access the hardware with clocks and power disabled. Reset the 456 * break flag to make the break debouncing state machine ready for the 457 * next break. 458 */ 459 del_timer_sync(&sci_port->break_timer); 460 sci_port->break_flag = 0; 461 462 clk_disable_unprepare(sci_port->fclk); 463 clk_disable_unprepare(sci_port->iclk); 464 465 pm_runtime_put_sync(sci_port->port.dev); 466 } 467 468 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) 469 470 #ifdef CONFIG_CONSOLE_POLL 471 static int sci_poll_get_char(struct uart_port *port) 472 { 473 unsigned short status; 474 int c; 475 476 do { 477 status = serial_port_in(port, SCxSR); 478 if (status & SCxSR_ERRORS(port)) { 479 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port)); 480 continue; 481 } 482 break; 483 } while (1); 484 485 if (!(status & SCxSR_RDxF(port))) 486 return NO_POLL_CHAR; 487 488 c = serial_port_in(port, SCxRDR); 489 490 /* Dummy read */ 491 serial_port_in(port, SCxSR); 492 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); 493 494 return c; 495 } 496 #endif 497 498 static void sci_poll_put_char(struct uart_port *port, unsigned char c) 499 { 500 unsigned short status; 501 502 do { 503 status = serial_port_in(port, SCxSR); 504 } while (!(status & SCxSR_TDxE(port))); 505 506 serial_port_out(port, SCxTDR, c); 507 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port)); 508 } 509 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */ 510 511 static void sci_init_pins(struct uart_port *port, unsigned int cflag) 512 { 513 struct sci_port *s = to_sci_port(port); 514 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR; 515 516 /* 517 * Use port-specific handler if provided. 518 */ 519 if (s->cfg->ops && s->cfg->ops->init_pins) { 520 s->cfg->ops->init_pins(port, cflag); 521 return; 522 } 523 524 /* 525 * For the generic path SCSPTR is necessary. Bail out if that's 526 * unavailable, too. 527 */ 528 if (!reg->size) 529 return; 530 531 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) && 532 ((!(cflag & CRTSCTS)))) { 533 unsigned short status; 534 535 status = serial_port_in(port, SCSPTR); 536 status &= ~SCSPTR_CTSIO; 537 status |= SCSPTR_RTSIO; 538 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */ 539 } 540 } 541 542 static int sci_txfill(struct uart_port *port) 543 { 544 struct plat_sci_reg *reg; 545 546 reg = sci_getreg(port, SCTFDR); 547 if (reg->size) 548 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1); 549 550 reg = sci_getreg(port, SCFDR); 551 if (reg->size) 552 return serial_port_in(port, SCFDR) >> 8; 553 554 return !(serial_port_in(port, SCxSR) & SCI_TDRE); 555 } 556 557 static int sci_txroom(struct uart_port *port) 558 { 559 return port->fifosize - sci_txfill(port); 560 } 561 562 static int sci_rxfill(struct uart_port *port) 563 { 564 struct plat_sci_reg *reg; 565 566 reg = sci_getreg(port, SCRFDR); 567 if (reg->size) 568 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1); 569 570 reg = sci_getreg(port, SCFDR); 571 if (reg->size) 572 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1); 573 574 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0; 575 } 576 577 /* 578 * SCI helper for checking the state of the muxed port/RXD pins. 579 */ 580 static inline int sci_rxd_in(struct uart_port *port) 581 { 582 struct sci_port *s = to_sci_port(port); 583 584 if (s->cfg->port_reg <= 0) 585 return 1; 586 587 /* Cast for ARM damage */ 588 return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg); 589 } 590 591 /* ********************************************************************** * 592 * the interrupt related routines * 593 * ********************************************************************** */ 594 595 static void sci_transmit_chars(struct uart_port *port) 596 { 597 struct circ_buf *xmit = &port->state->xmit; 598 unsigned int stopped = uart_tx_stopped(port); 599 unsigned short status; 600 unsigned short ctrl; 601 int count; 602 603 status = serial_port_in(port, SCxSR); 604 if (!(status & SCxSR_TDxE(port))) { 605 ctrl = serial_port_in(port, SCSCR); 606 if (uart_circ_empty(xmit)) 607 ctrl &= ~SCSCR_TIE; 608 else 609 ctrl |= SCSCR_TIE; 610 serial_port_out(port, SCSCR, ctrl); 611 return; 612 } 613 614 count = sci_txroom(port); 615 616 do { 617 unsigned char c; 618 619 if (port->x_char) { 620 c = port->x_char; 621 port->x_char = 0; 622 } else if (!uart_circ_empty(xmit) && !stopped) { 623 c = xmit->buf[xmit->tail]; 624 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 625 } else { 626 break; 627 } 628 629 serial_port_out(port, SCxTDR, c); 630 631 port->icount.tx++; 632 } while (--count > 0); 633 634 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); 635 636 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 637 uart_write_wakeup(port); 638 if (uart_circ_empty(xmit)) { 639 sci_stop_tx(port); 640 } else { 641 ctrl = serial_port_in(port, SCSCR); 642 643 if (port->type != PORT_SCI) { 644 serial_port_in(port, SCxSR); /* Dummy read */ 645 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); 646 } 647 648 ctrl |= SCSCR_TIE; 649 serial_port_out(port, SCSCR, ctrl); 650 } 651 } 652 653 /* On SH3, SCIF may read end-of-break as a space->mark char */ 654 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); }) 655 656 static void sci_receive_chars(struct uart_port *port) 657 { 658 struct sci_port *sci_port = to_sci_port(port); 659 struct tty_port *tport = &port->state->port; 660 int i, count, copied = 0; 661 unsigned short status; 662 unsigned char flag; 663 664 status = serial_port_in(port, SCxSR); 665 if (!(status & SCxSR_RDxF(port))) 666 return; 667 668 while (1) { 669 /* Don't copy more bytes than there is room for in the buffer */ 670 count = tty_buffer_request_room(tport, sci_rxfill(port)); 671 672 /* If for any reason we can't copy more data, we're done! */ 673 if (count == 0) 674 break; 675 676 if (port->type == PORT_SCI) { 677 char c = serial_port_in(port, SCxRDR); 678 if (uart_handle_sysrq_char(port, c) || 679 sci_port->break_flag) 680 count = 0; 681 else 682 tty_insert_flip_char(tport, c, TTY_NORMAL); 683 } else { 684 for (i = 0; i < count; i++) { 685 char c = serial_port_in(port, SCxRDR); 686 687 status = serial_port_in(port, SCxSR); 688 #if defined(CONFIG_CPU_SH3) 689 /* Skip "chars" during break */ 690 if (sci_port->break_flag) { 691 if ((c == 0) && 692 (status & SCxSR_FER(port))) { 693 count--; i--; 694 continue; 695 } 696 697 /* Nonzero => end-of-break */ 698 dev_dbg(port->dev, "debounce<%02x>\n", c); 699 sci_port->break_flag = 0; 700 701 if (STEPFN(c)) { 702 count--; i--; 703 continue; 704 } 705 } 706 #endif /* CONFIG_CPU_SH3 */ 707 if (uart_handle_sysrq_char(port, c)) { 708 count--; i--; 709 continue; 710 } 711 712 /* Store data and status */ 713 if (status & SCxSR_FER(port)) { 714 flag = TTY_FRAME; 715 port->icount.frame++; 716 dev_notice(port->dev, "frame error\n"); 717 } else if (status & SCxSR_PER(port)) { 718 flag = TTY_PARITY; 719 port->icount.parity++; 720 dev_notice(port->dev, "parity error\n"); 721 } else 722 flag = TTY_NORMAL; 723 724 tty_insert_flip_char(tport, c, flag); 725 } 726 } 727 728 serial_port_in(port, SCxSR); /* dummy read */ 729 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); 730 731 copied += count; 732 port->icount.rx += count; 733 } 734 735 if (copied) { 736 /* Tell the rest of the system the news. New characters! */ 737 tty_flip_buffer_push(tport); 738 } else { 739 serial_port_in(port, SCxSR); /* dummy read */ 740 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); 741 } 742 } 743 744 #define SCI_BREAK_JIFFIES (HZ/20) 745 746 /* 747 * The sci generates interrupts during the break, 748 * 1 per millisecond or so during the break period, for 9600 baud. 749 * So dont bother disabling interrupts. 750 * But dont want more than 1 break event. 751 * Use a kernel timer to periodically poll the rx line until 752 * the break is finished. 753 */ 754 static inline void sci_schedule_break_timer(struct sci_port *port) 755 { 756 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES); 757 } 758 759 /* Ensure that two consecutive samples find the break over. */ 760 static void sci_break_timer(unsigned long data) 761 { 762 struct sci_port *port = (struct sci_port *)data; 763 764 if (sci_rxd_in(&port->port) == 0) { 765 port->break_flag = 1; 766 sci_schedule_break_timer(port); 767 } else if (port->break_flag == 1) { 768 /* break is over. */ 769 port->break_flag = 2; 770 sci_schedule_break_timer(port); 771 } else 772 port->break_flag = 0; 773 } 774 775 static int sci_handle_errors(struct uart_port *port) 776 { 777 int copied = 0; 778 unsigned short status = serial_port_in(port, SCxSR); 779 struct tty_port *tport = &port->state->port; 780 struct sci_port *s = to_sci_port(port); 781 782 /* Handle overruns */ 783 if (status & (1 << s->overrun_bit)) { 784 port->icount.overrun++; 785 786 /* overrun error */ 787 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN)) 788 copied++; 789 790 dev_notice(port->dev, "overrun error"); 791 } 792 793 if (status & SCxSR_FER(port)) { 794 if (sci_rxd_in(port) == 0) { 795 /* Notify of BREAK */ 796 struct sci_port *sci_port = to_sci_port(port); 797 798 if (!sci_port->break_flag) { 799 port->icount.brk++; 800 801 sci_port->break_flag = 1; 802 sci_schedule_break_timer(sci_port); 803 804 /* Do sysrq handling. */ 805 if (uart_handle_break(port)) 806 return 0; 807 808 dev_dbg(port->dev, "BREAK detected\n"); 809 810 if (tty_insert_flip_char(tport, 0, TTY_BREAK)) 811 copied++; 812 } 813 814 } else { 815 /* frame error */ 816 port->icount.frame++; 817 818 if (tty_insert_flip_char(tport, 0, TTY_FRAME)) 819 copied++; 820 821 dev_notice(port->dev, "frame error\n"); 822 } 823 } 824 825 if (status & SCxSR_PER(port)) { 826 /* parity error */ 827 port->icount.parity++; 828 829 if (tty_insert_flip_char(tport, 0, TTY_PARITY)) 830 copied++; 831 832 dev_notice(port->dev, "parity error"); 833 } 834 835 if (copied) 836 tty_flip_buffer_push(tport); 837 838 return copied; 839 } 840 841 static int sci_handle_fifo_overrun(struct uart_port *port) 842 { 843 struct tty_port *tport = &port->state->port; 844 struct sci_port *s = to_sci_port(port); 845 struct plat_sci_reg *reg; 846 int copied = 0; 847 848 reg = sci_getreg(port, SCLSR); 849 if (!reg->size) 850 return 0; 851 852 if ((serial_port_in(port, SCLSR) & (1 << s->overrun_bit))) { 853 serial_port_out(port, SCLSR, 0); 854 855 port->icount.overrun++; 856 857 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 858 tty_flip_buffer_push(tport); 859 860 dev_notice(port->dev, "overrun error\n"); 861 copied++; 862 } 863 864 return copied; 865 } 866 867 static int sci_handle_breaks(struct uart_port *port) 868 { 869 int copied = 0; 870 unsigned short status = serial_port_in(port, SCxSR); 871 struct tty_port *tport = &port->state->port; 872 struct sci_port *s = to_sci_port(port); 873 874 if (uart_handle_break(port)) 875 return 0; 876 877 if (!s->break_flag && status & SCxSR_BRK(port)) { 878 #if defined(CONFIG_CPU_SH3) 879 /* Debounce break */ 880 s->break_flag = 1; 881 #endif 882 883 port->icount.brk++; 884 885 /* Notify of BREAK */ 886 if (tty_insert_flip_char(tport, 0, TTY_BREAK)) 887 copied++; 888 889 dev_dbg(port->dev, "BREAK detected\n"); 890 } 891 892 if (copied) 893 tty_flip_buffer_push(tport); 894 895 copied += sci_handle_fifo_overrun(port); 896 897 return copied; 898 } 899 900 static irqreturn_t sci_rx_interrupt(int irq, void *ptr) 901 { 902 #ifdef CONFIG_SERIAL_SH_SCI_DMA 903 struct uart_port *port = ptr; 904 struct sci_port *s = to_sci_port(port); 905 906 if (s->chan_rx) { 907 u16 scr = serial_port_in(port, SCSCR); 908 u16 ssr = serial_port_in(port, SCxSR); 909 910 /* Disable future Rx interrupts */ 911 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 912 disable_irq_nosync(irq); 913 scr |= 0x4000; 914 } else { 915 scr &= ~SCSCR_RIE; 916 } 917 serial_port_out(port, SCSCR, scr); 918 /* Clear current interrupt */ 919 serial_port_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port))); 920 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n", 921 jiffies, s->rx_timeout); 922 mod_timer(&s->rx_timer, jiffies + s->rx_timeout); 923 924 return IRQ_HANDLED; 925 } 926 #endif 927 928 /* I think sci_receive_chars has to be called irrespective 929 * of whether the I_IXOFF is set, otherwise, how is the interrupt 930 * to be disabled? 931 */ 932 sci_receive_chars(ptr); 933 934 return IRQ_HANDLED; 935 } 936 937 static irqreturn_t sci_tx_interrupt(int irq, void *ptr) 938 { 939 struct uart_port *port = ptr; 940 unsigned long flags; 941 942 spin_lock_irqsave(&port->lock, flags); 943 sci_transmit_chars(port); 944 spin_unlock_irqrestore(&port->lock, flags); 945 946 return IRQ_HANDLED; 947 } 948 949 static irqreturn_t sci_er_interrupt(int irq, void *ptr) 950 { 951 struct uart_port *port = ptr; 952 953 /* Handle errors */ 954 if (port->type == PORT_SCI) { 955 if (sci_handle_errors(port)) { 956 /* discard character in rx buffer */ 957 serial_port_in(port, SCxSR); 958 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); 959 } 960 } else { 961 sci_handle_fifo_overrun(port); 962 sci_rx_interrupt(irq, ptr); 963 } 964 965 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port)); 966 967 /* Kick the transmission */ 968 sci_tx_interrupt(irq, ptr); 969 970 return IRQ_HANDLED; 971 } 972 973 static irqreturn_t sci_br_interrupt(int irq, void *ptr) 974 { 975 struct uart_port *port = ptr; 976 977 /* Handle BREAKs */ 978 sci_handle_breaks(port); 979 serial_port_out(port, SCxSR, SCxSR_BREAK_CLEAR(port)); 980 981 return IRQ_HANDLED; 982 } 983 984 static inline unsigned long port_rx_irq_mask(struct uart_port *port) 985 { 986 /* 987 * Not all ports (such as SCIFA) will support REIE. Rather than 988 * special-casing the port type, we check the port initialization 989 * IRQ enable mask to see whether the IRQ is desired at all. If 990 * it's unset, it's logically inferred that there's no point in 991 * testing for it. 992 */ 993 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE); 994 } 995 996 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) 997 { 998 unsigned short ssr_status, scr_status, err_enabled; 999 struct uart_port *port = ptr; 1000 struct sci_port *s = to_sci_port(port); 1001 irqreturn_t ret = IRQ_NONE; 1002 1003 ssr_status = serial_port_in(port, SCxSR); 1004 scr_status = serial_port_in(port, SCSCR); 1005 err_enabled = scr_status & port_rx_irq_mask(port); 1006 1007 /* Tx Interrupt */ 1008 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) && 1009 !s->chan_tx) 1010 ret = sci_tx_interrupt(irq, ptr); 1011 1012 /* 1013 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF / 1014 * DR flags 1015 */ 1016 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) && 1017 (scr_status & SCSCR_RIE)) 1018 ret = sci_rx_interrupt(irq, ptr); 1019 1020 /* Error Interrupt */ 1021 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled) 1022 ret = sci_er_interrupt(irq, ptr); 1023 1024 /* Break Interrupt */ 1025 if ((ssr_status & SCxSR_BRK(port)) && err_enabled) 1026 ret = sci_br_interrupt(irq, ptr); 1027 1028 return ret; 1029 } 1030 1031 /* 1032 * Here we define a transition notifier so that we can update all of our 1033 * ports' baud rate when the peripheral clock changes. 1034 */ 1035 static int sci_notifier(struct notifier_block *self, 1036 unsigned long phase, void *p) 1037 { 1038 struct sci_port *sci_port; 1039 unsigned long flags; 1040 1041 sci_port = container_of(self, struct sci_port, freq_transition); 1042 1043 if ((phase == CPUFREQ_POSTCHANGE) || 1044 (phase == CPUFREQ_RESUMECHANGE)) { 1045 struct uart_port *port = &sci_port->port; 1046 1047 spin_lock_irqsave(&port->lock, flags); 1048 port->uartclk = clk_get_rate(sci_port->iclk); 1049 spin_unlock_irqrestore(&port->lock, flags); 1050 } 1051 1052 return NOTIFY_OK; 1053 } 1054 1055 static struct sci_irq_desc { 1056 const char *desc; 1057 irq_handler_t handler; 1058 } sci_irq_desc[] = { 1059 /* 1060 * Split out handlers, the default case. 1061 */ 1062 [SCIx_ERI_IRQ] = { 1063 .desc = "rx err", 1064 .handler = sci_er_interrupt, 1065 }, 1066 1067 [SCIx_RXI_IRQ] = { 1068 .desc = "rx full", 1069 .handler = sci_rx_interrupt, 1070 }, 1071 1072 [SCIx_TXI_IRQ] = { 1073 .desc = "tx empty", 1074 .handler = sci_tx_interrupt, 1075 }, 1076 1077 [SCIx_BRI_IRQ] = { 1078 .desc = "break", 1079 .handler = sci_br_interrupt, 1080 }, 1081 1082 /* 1083 * Special muxed handler. 1084 */ 1085 [SCIx_MUX_IRQ] = { 1086 .desc = "mux", 1087 .handler = sci_mpxed_interrupt, 1088 }, 1089 }; 1090 1091 static int sci_request_irq(struct sci_port *port) 1092 { 1093 struct uart_port *up = &port->port; 1094 int i, j, ret = 0; 1095 1096 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) { 1097 struct sci_irq_desc *desc; 1098 int irq; 1099 1100 if (SCIx_IRQ_IS_MUXED(port)) { 1101 i = SCIx_MUX_IRQ; 1102 irq = up->irq; 1103 } else { 1104 irq = port->irqs[i]; 1105 1106 /* 1107 * Certain port types won't support all of the 1108 * available interrupt sources. 1109 */ 1110 if (unlikely(irq < 0)) 1111 continue; 1112 } 1113 1114 desc = sci_irq_desc + i; 1115 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s", 1116 dev_name(up->dev), desc->desc); 1117 if (!port->irqstr[j]) { 1118 dev_err(up->dev, "Failed to allocate %s IRQ string\n", 1119 desc->desc); 1120 goto out_nomem; 1121 } 1122 1123 ret = request_irq(irq, desc->handler, up->irqflags, 1124 port->irqstr[j], port); 1125 if (unlikely(ret)) { 1126 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc); 1127 goto out_noirq; 1128 } 1129 } 1130 1131 return 0; 1132 1133 out_noirq: 1134 while (--i >= 0) 1135 free_irq(port->irqs[i], port); 1136 1137 out_nomem: 1138 while (--j >= 0) 1139 kfree(port->irqstr[j]); 1140 1141 return ret; 1142 } 1143 1144 static void sci_free_irq(struct sci_port *port) 1145 { 1146 int i; 1147 1148 /* 1149 * Intentionally in reverse order so we iterate over the muxed 1150 * IRQ first. 1151 */ 1152 for (i = 0; i < SCIx_NR_IRQS; i++) { 1153 int irq = port->irqs[i]; 1154 1155 /* 1156 * Certain port types won't support all of the available 1157 * interrupt sources. 1158 */ 1159 if (unlikely(irq < 0)) 1160 continue; 1161 1162 free_irq(port->irqs[i], port); 1163 kfree(port->irqstr[i]); 1164 1165 if (SCIx_IRQ_IS_MUXED(port)) { 1166 /* If there's only one IRQ, we're done. */ 1167 return; 1168 } 1169 } 1170 } 1171 1172 static unsigned int sci_tx_empty(struct uart_port *port) 1173 { 1174 unsigned short status = serial_port_in(port, SCxSR); 1175 unsigned short in_tx_fifo = sci_txfill(port); 1176 1177 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0; 1178 } 1179 1180 /* 1181 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally 1182 * CTS/RTS is supported in hardware by at least one port and controlled 1183 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently 1184 * handled via the ->init_pins() op, which is a bit of a one-way street, 1185 * lacking any ability to defer pin control -- this will later be 1186 * converted over to the GPIO framework). 1187 * 1188 * Other modes (such as loopback) are supported generically on certain 1189 * port types, but not others. For these it's sufficient to test for the 1190 * existence of the support register and simply ignore the port type. 1191 */ 1192 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) 1193 { 1194 if (mctrl & TIOCM_LOOP) { 1195 struct plat_sci_reg *reg; 1196 1197 /* 1198 * Standard loopback mode for SCFCR ports. 1199 */ 1200 reg = sci_getreg(port, SCFCR); 1201 if (reg->size) 1202 serial_port_out(port, SCFCR, serial_port_in(port, SCFCR) | 1); 1203 } 1204 } 1205 1206 static unsigned int sci_get_mctrl(struct uart_port *port) 1207 { 1208 /* 1209 * CTS/RTS is handled in hardware when supported, while nothing 1210 * else is wired up. Keep it simple and simply assert DSR/CAR. 1211 */ 1212 return TIOCM_DSR | TIOCM_CAR; 1213 } 1214 1215 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1216 static void sci_dma_tx_complete(void *arg) 1217 { 1218 struct sci_port *s = arg; 1219 struct uart_port *port = &s->port; 1220 struct circ_buf *xmit = &port->state->xmit; 1221 unsigned long flags; 1222 1223 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1224 1225 spin_lock_irqsave(&port->lock, flags); 1226 1227 xmit->tail += sg_dma_len(&s->sg_tx); 1228 xmit->tail &= UART_XMIT_SIZE - 1; 1229 1230 port->icount.tx += sg_dma_len(&s->sg_tx); 1231 1232 async_tx_ack(s->desc_tx); 1233 s->desc_tx = NULL; 1234 1235 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1236 uart_write_wakeup(port); 1237 1238 if (!uart_circ_empty(xmit)) { 1239 s->cookie_tx = 0; 1240 schedule_work(&s->work_tx); 1241 } else { 1242 s->cookie_tx = -EINVAL; 1243 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1244 u16 ctrl = serial_port_in(port, SCSCR); 1245 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE); 1246 } 1247 } 1248 1249 spin_unlock_irqrestore(&port->lock, flags); 1250 } 1251 1252 /* Locking: called with port lock held */ 1253 static int sci_dma_rx_push(struct sci_port *s, size_t count) 1254 { 1255 struct uart_port *port = &s->port; 1256 struct tty_port *tport = &port->state->port; 1257 int i, active, room; 1258 1259 room = tty_buffer_request_room(tport, count); 1260 1261 if (s->active_rx == s->cookie_rx[0]) { 1262 active = 0; 1263 } else if (s->active_rx == s->cookie_rx[1]) { 1264 active = 1; 1265 } else { 1266 dev_err(port->dev, "cookie %d not found!\n", s->active_rx); 1267 return 0; 1268 } 1269 1270 if (room < count) 1271 dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n", 1272 count - room); 1273 if (!room) 1274 return room; 1275 1276 for (i = 0; i < room; i++) 1277 tty_insert_flip_char(tport, ((u8 *)sg_virt(&s->sg_rx[active]))[i], 1278 TTY_NORMAL); 1279 1280 port->icount.rx += room; 1281 1282 return room; 1283 } 1284 1285 static void sci_dma_rx_complete(void *arg) 1286 { 1287 struct sci_port *s = arg; 1288 struct uart_port *port = &s->port; 1289 unsigned long flags; 1290 int count; 1291 1292 dev_dbg(port->dev, "%s(%d) active #%d\n", __func__, port->line, s->active_rx); 1293 1294 spin_lock_irqsave(&port->lock, flags); 1295 1296 count = sci_dma_rx_push(s, s->buf_len_rx); 1297 1298 mod_timer(&s->rx_timer, jiffies + s->rx_timeout); 1299 1300 spin_unlock_irqrestore(&port->lock, flags); 1301 1302 if (count) 1303 tty_flip_buffer_push(&port->state->port); 1304 1305 schedule_work(&s->work_rx); 1306 } 1307 1308 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio) 1309 { 1310 struct dma_chan *chan = s->chan_rx; 1311 struct uart_port *port = &s->port; 1312 1313 s->chan_rx = NULL; 1314 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL; 1315 dma_release_channel(chan); 1316 if (sg_dma_address(&s->sg_rx[0])) 1317 dma_free_coherent(port->dev, s->buf_len_rx * 2, 1318 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0])); 1319 if (enable_pio) 1320 sci_start_rx(port); 1321 } 1322 1323 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio) 1324 { 1325 struct dma_chan *chan = s->chan_tx; 1326 struct uart_port *port = &s->port; 1327 1328 s->chan_tx = NULL; 1329 s->cookie_tx = -EINVAL; 1330 dma_release_channel(chan); 1331 if (enable_pio) 1332 sci_start_tx(port); 1333 } 1334 1335 static void sci_submit_rx(struct sci_port *s) 1336 { 1337 struct dma_chan *chan = s->chan_rx; 1338 int i; 1339 1340 for (i = 0; i < 2; i++) { 1341 struct scatterlist *sg = &s->sg_rx[i]; 1342 struct dma_async_tx_descriptor *desc; 1343 1344 desc = dmaengine_prep_slave_sg(chan, 1345 sg, 1, DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT); 1346 1347 if (desc) { 1348 s->desc_rx[i] = desc; 1349 desc->callback = sci_dma_rx_complete; 1350 desc->callback_param = s; 1351 s->cookie_rx[i] = desc->tx_submit(desc); 1352 } 1353 1354 if (!desc || s->cookie_rx[i] < 0) { 1355 if (i) { 1356 async_tx_ack(s->desc_rx[0]); 1357 s->cookie_rx[0] = -EINVAL; 1358 } 1359 if (desc) { 1360 async_tx_ack(desc); 1361 s->cookie_rx[i] = -EINVAL; 1362 } 1363 dev_warn(s->port.dev, 1364 "failed to re-start DMA, using PIO\n"); 1365 sci_rx_dma_release(s, true); 1366 return; 1367 } 1368 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__, 1369 s->cookie_rx[i], i); 1370 } 1371 1372 s->active_rx = s->cookie_rx[0]; 1373 1374 dma_async_issue_pending(chan); 1375 } 1376 1377 static void work_fn_rx(struct work_struct *work) 1378 { 1379 struct sci_port *s = container_of(work, struct sci_port, work_rx); 1380 struct uart_port *port = &s->port; 1381 struct dma_async_tx_descriptor *desc; 1382 int new; 1383 1384 if (s->active_rx == s->cookie_rx[0]) { 1385 new = 0; 1386 } else if (s->active_rx == s->cookie_rx[1]) { 1387 new = 1; 1388 } else { 1389 dev_err(port->dev, "cookie %d not found!\n", s->active_rx); 1390 return; 1391 } 1392 desc = s->desc_rx[new]; 1393 1394 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) != 1395 DMA_COMPLETE) { 1396 /* Handle incomplete DMA receive */ 1397 struct dma_chan *chan = s->chan_rx; 1398 struct shdma_desc *sh_desc = container_of(desc, 1399 struct shdma_desc, async_tx); 1400 unsigned long flags; 1401 int count; 1402 1403 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0); 1404 dev_dbg(port->dev, "Read %zu bytes with cookie %d\n", 1405 sh_desc->partial, sh_desc->cookie); 1406 1407 spin_lock_irqsave(&port->lock, flags); 1408 count = sci_dma_rx_push(s, sh_desc->partial); 1409 spin_unlock_irqrestore(&port->lock, flags); 1410 1411 if (count) 1412 tty_flip_buffer_push(&port->state->port); 1413 1414 sci_submit_rx(s); 1415 1416 return; 1417 } 1418 1419 s->cookie_rx[new] = desc->tx_submit(desc); 1420 if (s->cookie_rx[new] < 0) { 1421 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n"); 1422 sci_rx_dma_release(s, true); 1423 return; 1424 } 1425 1426 s->active_rx = s->cookie_rx[!new]; 1427 1428 dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n", __func__, 1429 s->cookie_rx[new], new, s->active_rx); 1430 } 1431 1432 static void work_fn_tx(struct work_struct *work) 1433 { 1434 struct sci_port *s = container_of(work, struct sci_port, work_tx); 1435 struct dma_async_tx_descriptor *desc; 1436 struct dma_chan *chan = s->chan_tx; 1437 struct uart_port *port = &s->port; 1438 struct circ_buf *xmit = &port->state->xmit; 1439 struct scatterlist *sg = &s->sg_tx; 1440 1441 /* 1442 * DMA is idle now. 1443 * Port xmit buffer is already mapped, and it is one page... Just adjust 1444 * offsets and lengths. Since it is a circular buffer, we have to 1445 * transmit till the end, and then the rest. Take the port lock to get a 1446 * consistent xmit buffer state. 1447 */ 1448 spin_lock_irq(&port->lock); 1449 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1); 1450 sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) + 1451 sg->offset; 1452 sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE), 1453 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE)); 1454 spin_unlock_irq(&port->lock); 1455 1456 BUG_ON(!sg_dma_len(sg)); 1457 1458 desc = dmaengine_prep_slave_sg(chan, 1459 sg, s->sg_len_tx, DMA_MEM_TO_DEV, 1460 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1461 if (!desc) { 1462 /* switch to PIO */ 1463 sci_tx_dma_release(s, true); 1464 return; 1465 } 1466 1467 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE); 1468 1469 spin_lock_irq(&port->lock); 1470 s->desc_tx = desc; 1471 desc->callback = sci_dma_tx_complete; 1472 desc->callback_param = s; 1473 spin_unlock_irq(&port->lock); 1474 s->cookie_tx = desc->tx_submit(desc); 1475 if (s->cookie_tx < 0) { 1476 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n"); 1477 /* switch to PIO */ 1478 sci_tx_dma_release(s, true); 1479 return; 1480 } 1481 1482 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", __func__, 1483 xmit->buf, xmit->tail, xmit->head, s->cookie_tx); 1484 1485 dma_async_issue_pending(chan); 1486 } 1487 #endif 1488 1489 static void sci_start_tx(struct uart_port *port) 1490 { 1491 struct sci_port *s = to_sci_port(port); 1492 unsigned short ctrl; 1493 1494 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1495 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1496 u16 new, scr = serial_port_in(port, SCSCR); 1497 if (s->chan_tx) 1498 new = scr | 0x8000; 1499 else 1500 new = scr & ~0x8000; 1501 if (new != scr) 1502 serial_port_out(port, SCSCR, new); 1503 } 1504 1505 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) && 1506 s->cookie_tx < 0) { 1507 s->cookie_tx = 0; 1508 schedule_work(&s->work_tx); 1509 } 1510 #endif 1511 1512 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1513 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ 1514 ctrl = serial_port_in(port, SCSCR); 1515 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE); 1516 } 1517 } 1518 1519 static void sci_stop_tx(struct uart_port *port) 1520 { 1521 unsigned short ctrl; 1522 1523 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ 1524 ctrl = serial_port_in(port, SCSCR); 1525 1526 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1527 ctrl &= ~0x8000; 1528 1529 ctrl &= ~SCSCR_TIE; 1530 1531 serial_port_out(port, SCSCR, ctrl); 1532 } 1533 1534 static void sci_start_rx(struct uart_port *port) 1535 { 1536 unsigned short ctrl; 1537 1538 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port); 1539 1540 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1541 ctrl &= ~0x4000; 1542 1543 serial_port_out(port, SCSCR, ctrl); 1544 } 1545 1546 static void sci_stop_rx(struct uart_port *port) 1547 { 1548 unsigned short ctrl; 1549 1550 ctrl = serial_port_in(port, SCSCR); 1551 1552 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1553 ctrl &= ~0x4000; 1554 1555 ctrl &= ~port_rx_irq_mask(port); 1556 1557 serial_port_out(port, SCSCR, ctrl); 1558 } 1559 1560 static void sci_enable_ms(struct uart_port *port) 1561 { 1562 /* 1563 * Not supported by hardware, always a nop. 1564 */ 1565 } 1566 1567 static void sci_break_ctl(struct uart_port *port, int break_state) 1568 { 1569 struct sci_port *s = to_sci_port(port); 1570 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR; 1571 unsigned short scscr, scsptr; 1572 1573 /* check wheter the port has SCSPTR */ 1574 if (!reg->size) { 1575 /* 1576 * Not supported by hardware. Most parts couple break and rx 1577 * interrupts together, with break detection always enabled. 1578 */ 1579 return; 1580 } 1581 1582 scsptr = serial_port_in(port, SCSPTR); 1583 scscr = serial_port_in(port, SCSCR); 1584 1585 if (break_state == -1) { 1586 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT; 1587 scscr &= ~SCSCR_TE; 1588 } else { 1589 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO; 1590 scscr |= SCSCR_TE; 1591 } 1592 1593 serial_port_out(port, SCSPTR, scsptr); 1594 serial_port_out(port, SCSCR, scscr); 1595 } 1596 1597 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1598 static bool filter(struct dma_chan *chan, void *slave) 1599 { 1600 struct sh_dmae_slave *param = slave; 1601 1602 dev_dbg(chan->device->dev, "%s: slave ID %d\n", __func__, 1603 param->shdma_slave.slave_id); 1604 1605 chan->private = ¶m->shdma_slave; 1606 return true; 1607 } 1608 1609 static void rx_timer_fn(unsigned long arg) 1610 { 1611 struct sci_port *s = (struct sci_port *)arg; 1612 struct uart_port *port = &s->port; 1613 u16 scr = serial_port_in(port, SCSCR); 1614 1615 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1616 scr &= ~0x4000; 1617 enable_irq(s->irqs[SCIx_RXI_IRQ]); 1618 } 1619 serial_port_out(port, SCSCR, scr | SCSCR_RIE); 1620 dev_dbg(port->dev, "DMA Rx timed out\n"); 1621 schedule_work(&s->work_rx); 1622 } 1623 1624 static void sci_request_dma(struct uart_port *port) 1625 { 1626 struct sci_port *s = to_sci_port(port); 1627 struct sh_dmae_slave *param; 1628 struct dma_chan *chan; 1629 dma_cap_mask_t mask; 1630 int nent; 1631 1632 dev_dbg(port->dev, "%s: port %d\n", __func__, 1633 port->line); 1634 1635 if (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0) 1636 return; 1637 1638 dma_cap_zero(mask); 1639 dma_cap_set(DMA_SLAVE, mask); 1640 1641 param = &s->param_tx; 1642 1643 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */ 1644 param->shdma_slave.slave_id = s->cfg->dma_slave_tx; 1645 1646 s->cookie_tx = -EINVAL; 1647 chan = dma_request_channel(mask, filter, param); 1648 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan); 1649 if (chan) { 1650 s->chan_tx = chan; 1651 sg_init_table(&s->sg_tx, 1); 1652 /* UART circular tx buffer is an aligned page. */ 1653 BUG_ON((uintptr_t)port->state->xmit.buf & ~PAGE_MASK); 1654 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf), 1655 UART_XMIT_SIZE, 1656 (uintptr_t)port->state->xmit.buf & ~PAGE_MASK); 1657 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE); 1658 if (!nent) 1659 sci_tx_dma_release(s, false); 1660 else 1661 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__, 1662 sg_dma_len(&s->sg_tx), port->state->xmit.buf, 1663 &sg_dma_address(&s->sg_tx)); 1664 1665 s->sg_len_tx = nent; 1666 1667 INIT_WORK(&s->work_tx, work_fn_tx); 1668 } 1669 1670 param = &s->param_rx; 1671 1672 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */ 1673 param->shdma_slave.slave_id = s->cfg->dma_slave_rx; 1674 1675 chan = dma_request_channel(mask, filter, param); 1676 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan); 1677 if (chan) { 1678 dma_addr_t dma[2]; 1679 void *buf[2]; 1680 int i; 1681 1682 s->chan_rx = chan; 1683 1684 s->buf_len_rx = 2 * max(16, (int)port->fifosize); 1685 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2, 1686 &dma[0], GFP_KERNEL); 1687 1688 if (!buf[0]) { 1689 dev_warn(port->dev, 1690 "failed to allocate dma buffer, using PIO\n"); 1691 sci_rx_dma_release(s, true); 1692 return; 1693 } 1694 1695 buf[1] = buf[0] + s->buf_len_rx; 1696 dma[1] = dma[0] + s->buf_len_rx; 1697 1698 for (i = 0; i < 2; i++) { 1699 struct scatterlist *sg = &s->sg_rx[i]; 1700 1701 sg_init_table(sg, 1); 1702 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx, 1703 (uintptr_t)buf[i] & ~PAGE_MASK); 1704 sg_dma_address(sg) = dma[i]; 1705 } 1706 1707 INIT_WORK(&s->work_rx, work_fn_rx); 1708 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s); 1709 1710 sci_submit_rx(s); 1711 } 1712 } 1713 1714 static void sci_free_dma(struct uart_port *port) 1715 { 1716 struct sci_port *s = to_sci_port(port); 1717 1718 if (s->chan_tx) 1719 sci_tx_dma_release(s, false); 1720 if (s->chan_rx) 1721 sci_rx_dma_release(s, false); 1722 } 1723 #else 1724 static inline void sci_request_dma(struct uart_port *port) 1725 { 1726 } 1727 1728 static inline void sci_free_dma(struct uart_port *port) 1729 { 1730 } 1731 #endif 1732 1733 static int sci_startup(struct uart_port *port) 1734 { 1735 struct sci_port *s = to_sci_port(port); 1736 unsigned long flags; 1737 int ret; 1738 1739 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1740 1741 ret = sci_request_irq(s); 1742 if (unlikely(ret < 0)) 1743 return ret; 1744 1745 sci_request_dma(port); 1746 1747 spin_lock_irqsave(&port->lock, flags); 1748 sci_start_tx(port); 1749 sci_start_rx(port); 1750 spin_unlock_irqrestore(&port->lock, flags); 1751 1752 return 0; 1753 } 1754 1755 static void sci_shutdown(struct uart_port *port) 1756 { 1757 struct sci_port *s = to_sci_port(port); 1758 unsigned long flags; 1759 1760 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1761 1762 spin_lock_irqsave(&port->lock, flags); 1763 sci_stop_rx(port); 1764 sci_stop_tx(port); 1765 spin_unlock_irqrestore(&port->lock, flags); 1766 1767 sci_free_dma(port); 1768 sci_free_irq(s); 1769 } 1770 1771 static unsigned int sci_scbrr_calc(struct sci_port *s, unsigned int bps, 1772 unsigned long freq) 1773 { 1774 if (s->sampling_rate) 1775 return DIV_ROUND_CLOSEST(freq, s->sampling_rate * bps) - 1; 1776 1777 /* Warn, but use a safe default */ 1778 WARN_ON(1); 1779 1780 return ((freq + 16 * bps) / (32 * bps) - 1); 1781 } 1782 1783 /* calculate sample rate, BRR, and clock select for HSCIF */ 1784 static void sci_baud_calc_hscif(unsigned int bps, unsigned long freq, 1785 int *brr, unsigned int *srr, 1786 unsigned int *cks) 1787 { 1788 int sr, c, br, err; 1789 int min_err = 1000; /* 100% */ 1790 1791 /* Find the combination of sample rate and clock select with the 1792 smallest deviation from the desired baud rate. */ 1793 for (sr = 8; sr <= 32; sr++) { 1794 for (c = 0; c <= 3; c++) { 1795 /* integerized formulas from HSCIF documentation */ 1796 br = freq / (sr * (1 << (2 * c + 1)) * bps) - 1; 1797 if (br < 0 || br > 255) 1798 continue; 1799 err = freq / ((br + 1) * bps * sr * 1800 (1 << (2 * c + 1)) / 1000) - 1000; 1801 if (min_err > err) { 1802 min_err = err; 1803 *brr = br; 1804 *srr = sr - 1; 1805 *cks = c; 1806 } 1807 } 1808 } 1809 1810 if (min_err == 1000) { 1811 WARN_ON(1); 1812 /* use defaults */ 1813 *brr = 255; 1814 *srr = 15; 1815 *cks = 0; 1816 } 1817 } 1818 1819 static void sci_reset(struct uart_port *port) 1820 { 1821 struct plat_sci_reg *reg; 1822 unsigned int status; 1823 1824 do { 1825 status = serial_port_in(port, SCxSR); 1826 } while (!(status & SCxSR_TEND(port))); 1827 1828 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */ 1829 1830 reg = sci_getreg(port, SCFCR); 1831 if (reg->size) 1832 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); 1833 } 1834 1835 static void sci_set_termios(struct uart_port *port, struct ktermios *termios, 1836 struct ktermios *old) 1837 { 1838 struct sci_port *s = to_sci_port(port); 1839 struct plat_sci_reg *reg; 1840 unsigned int baud, smr_val, max_baud, cks = 0; 1841 int t = -1; 1842 unsigned int srr = 15; 1843 1844 /* 1845 * earlyprintk comes here early on with port->uartclk set to zero. 1846 * the clock framework is not up and running at this point so here 1847 * we assume that 115200 is the maximum baud rate. please note that 1848 * the baud rate is not programmed during earlyprintk - it is assumed 1849 * that the previous boot loader has enabled required clocks and 1850 * setup the baud rate generator hardware for us already. 1851 */ 1852 max_baud = port->uartclk ? port->uartclk / 16 : 115200; 1853 1854 baud = uart_get_baud_rate(port, termios, old, 0, max_baud); 1855 if (likely(baud && port->uartclk)) { 1856 if (s->cfg->type == PORT_HSCIF) { 1857 sci_baud_calc_hscif(baud, port->uartclk, &t, &srr, 1858 &cks); 1859 } else { 1860 t = sci_scbrr_calc(s, baud, port->uartclk); 1861 for (cks = 0; t >= 256 && cks <= 3; cks++) 1862 t >>= 2; 1863 } 1864 } 1865 1866 sci_port_enable(s); 1867 1868 sci_reset(port); 1869 1870 smr_val = serial_port_in(port, SCSMR) & 3; 1871 1872 if ((termios->c_cflag & CSIZE) == CS7) 1873 smr_val |= 0x40; 1874 if (termios->c_cflag & PARENB) 1875 smr_val |= 0x20; 1876 if (termios->c_cflag & PARODD) 1877 smr_val |= 0x30; 1878 if (termios->c_cflag & CSTOPB) 1879 smr_val |= 0x08; 1880 1881 uart_update_timeout(port, termios->c_cflag, baud); 1882 1883 dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n", 1884 __func__, smr_val, cks, t, s->cfg->scscr); 1885 1886 if (t >= 0) { 1887 serial_port_out(port, SCSMR, (smr_val & ~3) | cks); 1888 serial_port_out(port, SCBRR, t); 1889 reg = sci_getreg(port, HSSRR); 1890 if (reg->size) 1891 serial_port_out(port, HSSRR, srr | HSCIF_SRE); 1892 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */ 1893 } else 1894 serial_port_out(port, SCSMR, smr_val); 1895 1896 sci_init_pins(port, termios->c_cflag); 1897 1898 reg = sci_getreg(port, SCFCR); 1899 if (reg->size) { 1900 unsigned short ctrl = serial_port_in(port, SCFCR); 1901 1902 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) { 1903 if (termios->c_cflag & CRTSCTS) 1904 ctrl |= SCFCR_MCE; 1905 else 1906 ctrl &= ~SCFCR_MCE; 1907 } 1908 1909 /* 1910 * As we've done a sci_reset() above, ensure we don't 1911 * interfere with the FIFOs while toggling MCE. As the 1912 * reset values could still be set, simply mask them out. 1913 */ 1914 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST); 1915 1916 serial_port_out(port, SCFCR, ctrl); 1917 } 1918 1919 serial_port_out(port, SCSCR, s->cfg->scscr); 1920 1921 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1922 /* 1923 * Calculate delay for 1.5 DMA buffers: see 1924 * drivers/serial/serial_core.c::uart_update_timeout(). With 10 bits 1925 * (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function 1926 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)." 1927 * Then below we calculate 3 jiffies (12ms) for 1.5 DMA buffers (3 FIFO 1928 * sizes), but it has been found out experimentally, that this is not 1929 * enough: the driver too often needlessly runs on a DMA timeout. 20ms 1930 * as a minimum seem to work perfectly. 1931 */ 1932 if (s->chan_rx) { 1933 s->rx_timeout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 / 1934 port->fifosize / 2; 1935 dev_dbg(port->dev, 1936 "DMA Rx t-out %ums, tty t-out %u jiffies\n", 1937 s->rx_timeout * 1000 / HZ, port->timeout); 1938 if (s->rx_timeout < msecs_to_jiffies(20)) 1939 s->rx_timeout = msecs_to_jiffies(20); 1940 } 1941 #endif 1942 1943 if ((termios->c_cflag & CREAD) != 0) 1944 sci_start_rx(port); 1945 1946 sci_port_disable(s); 1947 } 1948 1949 static void sci_pm(struct uart_port *port, unsigned int state, 1950 unsigned int oldstate) 1951 { 1952 struct sci_port *sci_port = to_sci_port(port); 1953 1954 switch (state) { 1955 case 3: 1956 sci_port_disable(sci_port); 1957 break; 1958 default: 1959 sci_port_enable(sci_port); 1960 break; 1961 } 1962 } 1963 1964 static const char *sci_type(struct uart_port *port) 1965 { 1966 switch (port->type) { 1967 case PORT_IRDA: 1968 return "irda"; 1969 case PORT_SCI: 1970 return "sci"; 1971 case PORT_SCIF: 1972 return "scif"; 1973 case PORT_SCIFA: 1974 return "scifa"; 1975 case PORT_SCIFB: 1976 return "scifb"; 1977 case PORT_HSCIF: 1978 return "hscif"; 1979 } 1980 1981 return NULL; 1982 } 1983 1984 static inline unsigned long sci_port_size(struct uart_port *port) 1985 { 1986 /* 1987 * Pick an arbitrary size that encapsulates all of the base 1988 * registers by default. This can be optimized later, or derived 1989 * from platform resource data at such a time that ports begin to 1990 * behave more erratically. 1991 */ 1992 if (port->type == PORT_HSCIF) 1993 return 96; 1994 else 1995 return 64; 1996 } 1997 1998 static int sci_remap_port(struct uart_port *port) 1999 { 2000 unsigned long size = sci_port_size(port); 2001 2002 /* 2003 * Nothing to do if there's already an established membase. 2004 */ 2005 if (port->membase) 2006 return 0; 2007 2008 if (port->flags & UPF_IOREMAP) { 2009 port->membase = ioremap_nocache(port->mapbase, size); 2010 if (unlikely(!port->membase)) { 2011 dev_err(port->dev, "can't remap port#%d\n", port->line); 2012 return -ENXIO; 2013 } 2014 } else { 2015 /* 2016 * For the simple (and majority of) cases where we don't 2017 * need to do any remapping, just cast the cookie 2018 * directly. 2019 */ 2020 port->membase = (void __iomem *)port->mapbase; 2021 } 2022 2023 return 0; 2024 } 2025 2026 static void sci_release_port(struct uart_port *port) 2027 { 2028 if (port->flags & UPF_IOREMAP) { 2029 iounmap(port->membase); 2030 port->membase = NULL; 2031 } 2032 2033 release_mem_region(port->mapbase, sci_port_size(port)); 2034 } 2035 2036 static int sci_request_port(struct uart_port *port) 2037 { 2038 unsigned long size = sci_port_size(port); 2039 struct resource *res; 2040 int ret; 2041 2042 res = request_mem_region(port->mapbase, size, dev_name(port->dev)); 2043 if (unlikely(res == NULL)) 2044 return -EBUSY; 2045 2046 ret = sci_remap_port(port); 2047 if (unlikely(ret != 0)) { 2048 release_resource(res); 2049 return ret; 2050 } 2051 2052 return 0; 2053 } 2054 2055 static void sci_config_port(struct uart_port *port, int flags) 2056 { 2057 if (flags & UART_CONFIG_TYPE) { 2058 struct sci_port *sport = to_sci_port(port); 2059 2060 port->type = sport->cfg->type; 2061 sci_request_port(port); 2062 } 2063 } 2064 2065 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser) 2066 { 2067 if (ser->baud_base < 2400) 2068 /* No paper tape reader for Mitch.. */ 2069 return -EINVAL; 2070 2071 return 0; 2072 } 2073 2074 static struct uart_ops sci_uart_ops = { 2075 .tx_empty = sci_tx_empty, 2076 .set_mctrl = sci_set_mctrl, 2077 .get_mctrl = sci_get_mctrl, 2078 .start_tx = sci_start_tx, 2079 .stop_tx = sci_stop_tx, 2080 .stop_rx = sci_stop_rx, 2081 .enable_ms = sci_enable_ms, 2082 .break_ctl = sci_break_ctl, 2083 .startup = sci_startup, 2084 .shutdown = sci_shutdown, 2085 .set_termios = sci_set_termios, 2086 .pm = sci_pm, 2087 .type = sci_type, 2088 .release_port = sci_release_port, 2089 .request_port = sci_request_port, 2090 .config_port = sci_config_port, 2091 .verify_port = sci_verify_port, 2092 #ifdef CONFIG_CONSOLE_POLL 2093 .poll_get_char = sci_poll_get_char, 2094 .poll_put_char = sci_poll_put_char, 2095 #endif 2096 }; 2097 2098 static int sci_init_single(struct platform_device *dev, 2099 struct sci_port *sci_port, unsigned int index, 2100 struct plat_sci_port *p, bool early) 2101 { 2102 struct uart_port *port = &sci_port->port; 2103 const struct resource *res; 2104 unsigned int sampling_rate; 2105 unsigned int i; 2106 int ret; 2107 2108 sci_port->cfg = p; 2109 2110 port->ops = &sci_uart_ops; 2111 port->iotype = UPIO_MEM; 2112 port->line = index; 2113 2114 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 2115 if (res == NULL) 2116 return -ENOMEM; 2117 2118 port->mapbase = res->start; 2119 2120 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) 2121 sci_port->irqs[i] = platform_get_irq(dev, i); 2122 2123 /* The SCI generates several interrupts. They can be muxed together or 2124 * connected to different interrupt lines. In the muxed case only one 2125 * interrupt resource is specified. In the non-muxed case three or four 2126 * interrupt resources are specified, as the BRI interrupt is optional. 2127 */ 2128 if (sci_port->irqs[0] < 0) 2129 return -ENXIO; 2130 2131 if (sci_port->irqs[1] < 0) { 2132 sci_port->irqs[1] = sci_port->irqs[0]; 2133 sci_port->irqs[2] = sci_port->irqs[0]; 2134 sci_port->irqs[3] = sci_port->irqs[0]; 2135 } 2136 2137 if (p->regtype == SCIx_PROBE_REGTYPE) { 2138 ret = sci_probe_regmap(p); 2139 if (unlikely(ret)) 2140 return ret; 2141 } 2142 2143 switch (p->type) { 2144 case PORT_SCIFB: 2145 port->fifosize = 256; 2146 sci_port->overrun_bit = 9; 2147 sampling_rate = 16; 2148 break; 2149 case PORT_HSCIF: 2150 port->fifosize = 128; 2151 sampling_rate = 0; 2152 sci_port->overrun_bit = 0; 2153 break; 2154 case PORT_SCIFA: 2155 port->fifosize = 64; 2156 sci_port->overrun_bit = 9; 2157 sampling_rate = 16; 2158 break; 2159 case PORT_SCIF: 2160 port->fifosize = 16; 2161 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) { 2162 sci_port->overrun_bit = 9; 2163 sampling_rate = 16; 2164 } else { 2165 sci_port->overrun_bit = 0; 2166 sampling_rate = 32; 2167 } 2168 break; 2169 default: 2170 port->fifosize = 1; 2171 sci_port->overrun_bit = 5; 2172 sampling_rate = 32; 2173 break; 2174 } 2175 2176 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't 2177 * match the SoC datasheet, this should be investigated. Let platform 2178 * data override the sampling rate for now. 2179 */ 2180 sci_port->sampling_rate = p->sampling_rate ? p->sampling_rate 2181 : sampling_rate; 2182 2183 if (!early) { 2184 sci_port->iclk = clk_get(&dev->dev, "sci_ick"); 2185 if (IS_ERR(sci_port->iclk)) { 2186 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk"); 2187 if (IS_ERR(sci_port->iclk)) { 2188 dev_err(&dev->dev, "can't get iclk\n"); 2189 return PTR_ERR(sci_port->iclk); 2190 } 2191 } 2192 2193 /* 2194 * The function clock is optional, ignore it if we can't 2195 * find it. 2196 */ 2197 sci_port->fclk = clk_get(&dev->dev, "sci_fck"); 2198 if (IS_ERR(sci_port->fclk)) 2199 sci_port->fclk = NULL; 2200 2201 port->dev = &dev->dev; 2202 2203 pm_runtime_enable(&dev->dev); 2204 } 2205 2206 sci_port->break_timer.data = (unsigned long)sci_port; 2207 sci_port->break_timer.function = sci_break_timer; 2208 init_timer(&sci_port->break_timer); 2209 2210 /* 2211 * Establish some sensible defaults for the error detection. 2212 */ 2213 sci_port->error_mask = (p->type == PORT_SCI) ? 2214 SCI_DEFAULT_ERROR_MASK : SCIF_DEFAULT_ERROR_MASK; 2215 2216 /* 2217 * Establish sensible defaults for the overrun detection, unless 2218 * the part has explicitly disabled support for it. 2219 */ 2220 2221 /* 2222 * Make the error mask inclusive of overrun detection, if 2223 * supported. 2224 */ 2225 sci_port->error_mask |= 1 << sci_port->overrun_bit; 2226 2227 port->type = p->type; 2228 port->flags = UPF_FIXED_PORT | p->flags; 2229 port->regshift = p->regshift; 2230 2231 /* 2232 * The UART port needs an IRQ value, so we peg this to the RX IRQ 2233 * for the multi-IRQ ports, which is where we are primarily 2234 * concerned with the shutdown path synchronization. 2235 * 2236 * For the muxed case there's nothing more to do. 2237 */ 2238 port->irq = sci_port->irqs[SCIx_RXI_IRQ]; 2239 port->irqflags = 0; 2240 2241 port->serial_in = sci_serial_in; 2242 port->serial_out = sci_serial_out; 2243 2244 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0) 2245 dev_dbg(port->dev, "DMA tx %d, rx %d\n", 2246 p->dma_slave_tx, p->dma_slave_rx); 2247 2248 return 0; 2249 } 2250 2251 static void sci_cleanup_single(struct sci_port *port) 2252 { 2253 clk_put(port->iclk); 2254 clk_put(port->fclk); 2255 2256 pm_runtime_disable(port->port.dev); 2257 } 2258 2259 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE 2260 static void serial_console_putchar(struct uart_port *port, int ch) 2261 { 2262 sci_poll_put_char(port, ch); 2263 } 2264 2265 /* 2266 * Print a string to the serial port trying not to disturb 2267 * any possible real use of the port... 2268 */ 2269 static void serial_console_write(struct console *co, const char *s, 2270 unsigned count) 2271 { 2272 struct sci_port *sci_port = &sci_ports[co->index]; 2273 struct uart_port *port = &sci_port->port; 2274 unsigned short bits, ctrl; 2275 unsigned long flags; 2276 int locked = 1; 2277 2278 local_irq_save(flags); 2279 if (port->sysrq) 2280 locked = 0; 2281 else if (oops_in_progress) 2282 locked = spin_trylock(&port->lock); 2283 else 2284 spin_lock(&port->lock); 2285 2286 /* first save the SCSCR then disable the interrupts */ 2287 ctrl = serial_port_in(port, SCSCR); 2288 serial_port_out(port, SCSCR, sci_port->cfg->scscr); 2289 2290 uart_console_write(port, s, count, serial_console_putchar); 2291 2292 /* wait until fifo is empty and last bit has been transmitted */ 2293 bits = SCxSR_TDxE(port) | SCxSR_TEND(port); 2294 while ((serial_port_in(port, SCxSR) & bits) != bits) 2295 cpu_relax(); 2296 2297 /* restore the SCSCR */ 2298 serial_port_out(port, SCSCR, ctrl); 2299 2300 if (locked) 2301 spin_unlock(&port->lock); 2302 local_irq_restore(flags); 2303 } 2304 2305 static int serial_console_setup(struct console *co, char *options) 2306 { 2307 struct sci_port *sci_port; 2308 struct uart_port *port; 2309 int baud = 115200; 2310 int bits = 8; 2311 int parity = 'n'; 2312 int flow = 'n'; 2313 int ret; 2314 2315 /* 2316 * Refuse to handle any bogus ports. 2317 */ 2318 if (co->index < 0 || co->index >= SCI_NPORTS) 2319 return -ENODEV; 2320 2321 sci_port = &sci_ports[co->index]; 2322 port = &sci_port->port; 2323 2324 /* 2325 * Refuse to handle uninitialized ports. 2326 */ 2327 if (!port->ops) 2328 return -ENODEV; 2329 2330 ret = sci_remap_port(port); 2331 if (unlikely(ret != 0)) 2332 return ret; 2333 2334 if (options) 2335 uart_parse_options(options, &baud, &parity, &bits, &flow); 2336 2337 return uart_set_options(port, co, baud, parity, bits, flow); 2338 } 2339 2340 static struct console serial_console = { 2341 .name = "ttySC", 2342 .device = uart_console_device, 2343 .write = serial_console_write, 2344 .setup = serial_console_setup, 2345 .flags = CON_PRINTBUFFER, 2346 .index = -1, 2347 .data = &sci_uart_driver, 2348 }; 2349 2350 static struct console early_serial_console = { 2351 .name = "early_ttySC", 2352 .write = serial_console_write, 2353 .flags = CON_PRINTBUFFER, 2354 .index = -1, 2355 }; 2356 2357 static char early_serial_buf[32]; 2358 2359 static int sci_probe_earlyprintk(struct platform_device *pdev) 2360 { 2361 struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev); 2362 2363 if (early_serial_console.data) 2364 return -EEXIST; 2365 2366 early_serial_console.index = pdev->id; 2367 2368 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true); 2369 2370 serial_console_setup(&early_serial_console, early_serial_buf); 2371 2372 if (!strstr(early_serial_buf, "keep")) 2373 early_serial_console.flags |= CON_BOOT; 2374 2375 register_console(&early_serial_console); 2376 return 0; 2377 } 2378 2379 #define SCI_CONSOLE (&serial_console) 2380 2381 #else 2382 static inline int sci_probe_earlyprintk(struct platform_device *pdev) 2383 { 2384 return -EINVAL; 2385 } 2386 2387 #define SCI_CONSOLE NULL 2388 2389 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */ 2390 2391 static char banner[] __initdata = 2392 KERN_INFO "SuperH (H)SCI(F) driver initialized\n"; 2393 2394 static struct uart_driver sci_uart_driver = { 2395 .owner = THIS_MODULE, 2396 .driver_name = "sci", 2397 .dev_name = "ttySC", 2398 .major = SCI_MAJOR, 2399 .minor = SCI_MINOR_START, 2400 .nr = SCI_NPORTS, 2401 .cons = SCI_CONSOLE, 2402 }; 2403 2404 static int sci_remove(struct platform_device *dev) 2405 { 2406 struct sci_port *port = platform_get_drvdata(dev); 2407 2408 cpufreq_unregister_notifier(&port->freq_transition, 2409 CPUFREQ_TRANSITION_NOTIFIER); 2410 2411 uart_remove_one_port(&sci_uart_driver, &port->port); 2412 2413 sci_cleanup_single(port); 2414 2415 return 0; 2416 } 2417 2418 static int sci_probe_single(struct platform_device *dev, 2419 unsigned int index, 2420 struct plat_sci_port *p, 2421 struct sci_port *sciport) 2422 { 2423 int ret; 2424 2425 /* Sanity check */ 2426 if (unlikely(index >= SCI_NPORTS)) { 2427 dev_notice(&dev->dev, "Attempting to register port " 2428 "%d when only %d are available.\n", 2429 index+1, SCI_NPORTS); 2430 dev_notice(&dev->dev, "Consider bumping " 2431 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n"); 2432 return -EINVAL; 2433 } 2434 2435 ret = sci_init_single(dev, sciport, index, p, false); 2436 if (ret) 2437 return ret; 2438 2439 ret = uart_add_one_port(&sci_uart_driver, &sciport->port); 2440 if (ret) { 2441 sci_cleanup_single(sciport); 2442 return ret; 2443 } 2444 2445 return 0; 2446 } 2447 2448 static int sci_probe(struct platform_device *dev) 2449 { 2450 struct plat_sci_port *p = dev_get_platdata(&dev->dev); 2451 struct sci_port *sp = &sci_ports[dev->id]; 2452 int ret; 2453 2454 /* 2455 * If we've come here via earlyprintk initialization, head off to 2456 * the special early probe. We don't have sufficient device state 2457 * to make it beyond this yet. 2458 */ 2459 if (is_early_platform_device(dev)) 2460 return sci_probe_earlyprintk(dev); 2461 2462 platform_set_drvdata(dev, sp); 2463 2464 ret = sci_probe_single(dev, dev->id, p, sp); 2465 if (ret) 2466 return ret; 2467 2468 sp->freq_transition.notifier_call = sci_notifier; 2469 2470 ret = cpufreq_register_notifier(&sp->freq_transition, 2471 CPUFREQ_TRANSITION_NOTIFIER); 2472 if (unlikely(ret < 0)) { 2473 sci_cleanup_single(sp); 2474 return ret; 2475 } 2476 2477 #ifdef CONFIG_SH_STANDARD_BIOS 2478 sh_bios_gdb_detach(); 2479 #endif 2480 2481 return 0; 2482 } 2483 2484 static int sci_suspend(struct device *dev) 2485 { 2486 struct sci_port *sport = dev_get_drvdata(dev); 2487 2488 if (sport) 2489 uart_suspend_port(&sci_uart_driver, &sport->port); 2490 2491 return 0; 2492 } 2493 2494 static int sci_resume(struct device *dev) 2495 { 2496 struct sci_port *sport = dev_get_drvdata(dev); 2497 2498 if (sport) 2499 uart_resume_port(&sci_uart_driver, &sport->port); 2500 2501 return 0; 2502 } 2503 2504 static const struct dev_pm_ops sci_dev_pm_ops = { 2505 .suspend = sci_suspend, 2506 .resume = sci_resume, 2507 }; 2508 2509 static struct platform_driver sci_driver = { 2510 .probe = sci_probe, 2511 .remove = sci_remove, 2512 .driver = { 2513 .name = "sh-sci", 2514 .owner = THIS_MODULE, 2515 .pm = &sci_dev_pm_ops, 2516 }, 2517 }; 2518 2519 static int __init sci_init(void) 2520 { 2521 int ret; 2522 2523 printk(banner); 2524 2525 ret = uart_register_driver(&sci_uart_driver); 2526 if (likely(ret == 0)) { 2527 ret = platform_driver_register(&sci_driver); 2528 if (unlikely(ret)) 2529 uart_unregister_driver(&sci_uart_driver); 2530 } 2531 2532 return ret; 2533 } 2534 2535 static void __exit sci_exit(void) 2536 { 2537 platform_driver_unregister(&sci_driver); 2538 uart_unregister_driver(&sci_uart_driver); 2539 } 2540 2541 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE 2542 early_platform_init_buffer("earlyprintk", &sci_driver, 2543 early_serial_buf, ARRAY_SIZE(early_serial_buf)); 2544 #endif 2545 module_init(sci_init); 2546 module_exit(sci_exit); 2547 2548 MODULE_LICENSE("GPL"); 2549 MODULE_ALIAS("platform:sh-sci"); 2550 MODULE_AUTHOR("Paul Mundt"); 2551 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver"); 2552