1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) 4 * 5 * Copyright (C) 2002 - 2011 Paul Mundt 6 * Copyright (C) 2015 Glider bvba 7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007). 8 * 9 * based off of the old drivers/char/sh-sci.c by: 10 * 11 * Copyright (C) 1999, 2000 Niibe Yutaka 12 * Copyright (C) 2000 Sugioka Toshinobu 13 * Modified to support multiple serial ports. Stuart Menefy (May 2000). 14 * Modified to support SecureEdge. David McCullough (2002) 15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003). 16 * Removed SH7300 support (Jul 2007). 17 */ 18 #undef DEBUG 19 20 #include <linux/clk.h> 21 #include <linux/console.h> 22 #include <linux/ctype.h> 23 #include <linux/cpufreq.h> 24 #include <linux/delay.h> 25 #include <linux/dmaengine.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/err.h> 28 #include <linux/errno.h> 29 #include <linux/init.h> 30 #include <linux/interrupt.h> 31 #include <linux/ioport.h> 32 #include <linux/ktime.h> 33 #include <linux/major.h> 34 #include <linux/minmax.h> 35 #include <linux/module.h> 36 #include <linux/mm.h> 37 #include <linux/of.h> 38 #include <linux/platform_device.h> 39 #include <linux/pm_runtime.h> 40 #include <linux/reset.h> 41 #include <linux/scatterlist.h> 42 #include <linux/serial.h> 43 #include <linux/serial_sci.h> 44 #include <linux/sh_dma.h> 45 #include <linux/slab.h> 46 #include <linux/string.h> 47 #include <linux/sysrq.h> 48 #include <linux/timer.h> 49 #include <linux/tty.h> 50 #include <linux/tty_flip.h> 51 52 #ifdef CONFIG_SUPERH 53 #include <asm/sh_bios.h> 54 #include <asm/platform_early.h> 55 #endif 56 57 #include "serial_mctrl_gpio.h" 58 #include "sh-sci.h" 59 60 /* Offsets into the sci_port->irqs array */ 61 enum { 62 SCIx_ERI_IRQ, 63 SCIx_RXI_IRQ, 64 SCIx_TXI_IRQ, 65 SCIx_BRI_IRQ, 66 SCIx_DRI_IRQ, 67 SCIx_TEI_IRQ, 68 SCIx_NR_IRQS, 69 70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */ 71 }; 72 73 #define SCIx_IRQ_IS_MUXED(port) \ 74 ((port)->irqs[SCIx_ERI_IRQ] == \ 75 (port)->irqs[SCIx_RXI_IRQ]) || \ 76 ((port)->irqs[SCIx_ERI_IRQ] && \ 77 ((port)->irqs[SCIx_RXI_IRQ] < 0)) 78 79 enum SCI_CLKS { 80 SCI_FCK, /* Functional Clock */ 81 SCI_SCK, /* Optional External Clock */ 82 SCI_BRG_INT, /* Optional BRG Internal Clock Source */ 83 SCI_SCIF_CLK, /* Optional BRG External Clock Source */ 84 SCI_NUM_CLKS 85 }; 86 87 /* Bit x set means sampling rate x + 1 is supported */ 88 #define SCI_SR(x) BIT((x) - 1) 89 #define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1) 90 91 #define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \ 92 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \ 93 SCI_SR(19) | SCI_SR(27) 94 95 #define min_sr(_port) ffs((_port)->sampling_rate_mask) 96 #define max_sr(_port) fls((_port)->sampling_rate_mask) 97 98 /* Iterate over all supported sampling rates, from high to low */ 99 #define for_each_sr(_sr, _port) \ 100 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \ 101 if ((_port)->sampling_rate_mask & SCI_SR((_sr))) 102 103 struct plat_sci_reg { 104 u8 offset, size; 105 }; 106 107 struct sci_port_params { 108 const struct plat_sci_reg regs[SCIx_NR_REGS]; 109 unsigned int fifosize; 110 unsigned int overrun_reg; 111 unsigned int overrun_mask; 112 unsigned int sampling_rate_mask; 113 unsigned int error_mask; 114 unsigned int error_clear; 115 }; 116 117 struct sci_port { 118 struct uart_port port; 119 120 /* Platform configuration */ 121 const struct sci_port_params *params; 122 const struct plat_sci_port *cfg; 123 unsigned int sampling_rate_mask; 124 resource_size_t reg_size; 125 struct mctrl_gpios *gpios; 126 127 /* Clocks */ 128 struct clk *clks[SCI_NUM_CLKS]; 129 unsigned long clk_rates[SCI_NUM_CLKS]; 130 131 int irqs[SCIx_NR_IRQS]; 132 char *irqstr[SCIx_NR_IRQS]; 133 134 struct dma_chan *chan_tx; 135 struct dma_chan *chan_rx; 136 137 #ifdef CONFIG_SERIAL_SH_SCI_DMA 138 struct dma_chan *chan_tx_saved; 139 struct dma_chan *chan_rx_saved; 140 dma_cookie_t cookie_tx; 141 dma_cookie_t cookie_rx[2]; 142 dma_cookie_t active_rx; 143 dma_addr_t tx_dma_addr; 144 unsigned int tx_dma_len; 145 struct scatterlist sg_rx[2]; 146 void *rx_buf[2]; 147 size_t buf_len_rx; 148 struct work_struct work_tx; 149 struct hrtimer rx_timer; 150 unsigned int rx_timeout; /* microseconds */ 151 #endif 152 unsigned int rx_frame; 153 int rx_trigger; 154 struct timer_list rx_fifo_timer; 155 int rx_fifo_timeout; 156 u16 hscif_tot; 157 158 bool has_rtscts; 159 bool autorts; 160 }; 161 162 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS 163 164 static struct sci_port sci_ports[SCI_NPORTS]; 165 static unsigned long sci_ports_in_use; 166 static struct uart_driver sci_uart_driver; 167 168 static inline struct sci_port * 169 to_sci_port(struct uart_port *uart) 170 { 171 return container_of(uart, struct sci_port, port); 172 } 173 174 static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { 175 /* 176 * Common SCI definitions, dependent on the port's regshift 177 * value. 178 */ 179 [SCIx_SCI_REGTYPE] = { 180 .regs = { 181 [SCSMR] = { 0x00, 8 }, 182 [SCBRR] = { 0x01, 8 }, 183 [SCSCR] = { 0x02, 8 }, 184 [SCxTDR] = { 0x03, 8 }, 185 [SCxSR] = { 0x04, 8 }, 186 [SCxRDR] = { 0x05, 8 }, 187 }, 188 .fifosize = 1, 189 .overrun_reg = SCxSR, 190 .overrun_mask = SCI_ORER, 191 .sampling_rate_mask = SCI_SR(32), 192 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, 193 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, 194 }, 195 196 /* 197 * Common definitions for legacy IrDA ports. 198 */ 199 [SCIx_IRDA_REGTYPE] = { 200 .regs = { 201 [SCSMR] = { 0x00, 8 }, 202 [SCBRR] = { 0x02, 8 }, 203 [SCSCR] = { 0x04, 8 }, 204 [SCxTDR] = { 0x06, 8 }, 205 [SCxSR] = { 0x08, 16 }, 206 [SCxRDR] = { 0x0a, 8 }, 207 [SCFCR] = { 0x0c, 8 }, 208 [SCFDR] = { 0x0e, 16 }, 209 }, 210 .fifosize = 1, 211 .overrun_reg = SCxSR, 212 .overrun_mask = SCI_ORER, 213 .sampling_rate_mask = SCI_SR(32), 214 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, 215 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, 216 }, 217 218 /* 219 * Common SCIFA definitions. 220 */ 221 [SCIx_SCIFA_REGTYPE] = { 222 .regs = { 223 [SCSMR] = { 0x00, 16 }, 224 [SCBRR] = { 0x04, 8 }, 225 [SCSCR] = { 0x08, 16 }, 226 [SCxTDR] = { 0x20, 8 }, 227 [SCxSR] = { 0x14, 16 }, 228 [SCxRDR] = { 0x24, 8 }, 229 [SCFCR] = { 0x18, 16 }, 230 [SCFDR] = { 0x1c, 16 }, 231 [SCPCR] = { 0x30, 16 }, 232 [SCPDR] = { 0x34, 16 }, 233 }, 234 .fifosize = 64, 235 .overrun_reg = SCxSR, 236 .overrun_mask = SCIFA_ORER, 237 .sampling_rate_mask = SCI_SR_SCIFAB, 238 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 239 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 240 }, 241 242 /* 243 * Common SCIFB definitions. 244 */ 245 [SCIx_SCIFB_REGTYPE] = { 246 .regs = { 247 [SCSMR] = { 0x00, 16 }, 248 [SCBRR] = { 0x04, 8 }, 249 [SCSCR] = { 0x08, 16 }, 250 [SCxTDR] = { 0x40, 8 }, 251 [SCxSR] = { 0x14, 16 }, 252 [SCxRDR] = { 0x60, 8 }, 253 [SCFCR] = { 0x18, 16 }, 254 [SCTFDR] = { 0x38, 16 }, 255 [SCRFDR] = { 0x3c, 16 }, 256 [SCPCR] = { 0x30, 16 }, 257 [SCPDR] = { 0x34, 16 }, 258 }, 259 .fifosize = 256, 260 .overrun_reg = SCxSR, 261 .overrun_mask = SCIFA_ORER, 262 .sampling_rate_mask = SCI_SR_SCIFAB, 263 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 264 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 265 }, 266 267 /* 268 * Common SH-2(A) SCIF definitions for ports with FIFO data 269 * count registers. 270 */ 271 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = { 272 .regs = { 273 [SCSMR] = { 0x00, 16 }, 274 [SCBRR] = { 0x04, 8 }, 275 [SCSCR] = { 0x08, 16 }, 276 [SCxTDR] = { 0x0c, 8 }, 277 [SCxSR] = { 0x10, 16 }, 278 [SCxRDR] = { 0x14, 8 }, 279 [SCFCR] = { 0x18, 16 }, 280 [SCFDR] = { 0x1c, 16 }, 281 [SCSPTR] = { 0x20, 16 }, 282 [SCLSR] = { 0x24, 16 }, 283 }, 284 .fifosize = 16, 285 .overrun_reg = SCLSR, 286 .overrun_mask = SCLSR_ORER, 287 .sampling_rate_mask = SCI_SR(32), 288 .error_mask = SCIF_DEFAULT_ERROR_MASK, 289 .error_clear = SCIF_ERROR_CLEAR, 290 }, 291 292 /* 293 * The "SCIFA" that is in RZ/A2, RZ/G2L and RZ/T. 294 * It looks like a normal SCIF with FIFO data, but with a 295 * compressed address space. Also, the break out of interrupts 296 * are different: ERI/BRI, RXI, TXI, TEI, DRI. 297 */ 298 [SCIx_RZ_SCIFA_REGTYPE] = { 299 .regs = { 300 [SCSMR] = { 0x00, 16 }, 301 [SCBRR] = { 0x02, 8 }, 302 [SCSCR] = { 0x04, 16 }, 303 [SCxTDR] = { 0x06, 8 }, 304 [SCxSR] = { 0x08, 16 }, 305 [SCxRDR] = { 0x0A, 8 }, 306 [SCFCR] = { 0x0C, 16 }, 307 [SCFDR] = { 0x0E, 16 }, 308 [SCSPTR] = { 0x10, 16 }, 309 [SCLSR] = { 0x12, 16 }, 310 [SEMR] = { 0x14, 8 }, 311 }, 312 .fifosize = 16, 313 .overrun_reg = SCLSR, 314 .overrun_mask = SCLSR_ORER, 315 .sampling_rate_mask = SCI_SR(32), 316 .error_mask = SCIF_DEFAULT_ERROR_MASK, 317 .error_clear = SCIF_ERROR_CLEAR, 318 }, 319 320 /* 321 * Common SH-3 SCIF definitions. 322 */ 323 [SCIx_SH3_SCIF_REGTYPE] = { 324 .regs = { 325 [SCSMR] = { 0x00, 8 }, 326 [SCBRR] = { 0x02, 8 }, 327 [SCSCR] = { 0x04, 8 }, 328 [SCxTDR] = { 0x06, 8 }, 329 [SCxSR] = { 0x08, 16 }, 330 [SCxRDR] = { 0x0a, 8 }, 331 [SCFCR] = { 0x0c, 8 }, 332 [SCFDR] = { 0x0e, 16 }, 333 }, 334 .fifosize = 16, 335 .overrun_reg = SCLSR, 336 .overrun_mask = SCLSR_ORER, 337 .sampling_rate_mask = SCI_SR(32), 338 .error_mask = SCIF_DEFAULT_ERROR_MASK, 339 .error_clear = SCIF_ERROR_CLEAR, 340 }, 341 342 /* 343 * Common SH-4(A) SCIF(B) definitions. 344 */ 345 [SCIx_SH4_SCIF_REGTYPE] = { 346 .regs = { 347 [SCSMR] = { 0x00, 16 }, 348 [SCBRR] = { 0x04, 8 }, 349 [SCSCR] = { 0x08, 16 }, 350 [SCxTDR] = { 0x0c, 8 }, 351 [SCxSR] = { 0x10, 16 }, 352 [SCxRDR] = { 0x14, 8 }, 353 [SCFCR] = { 0x18, 16 }, 354 [SCFDR] = { 0x1c, 16 }, 355 [SCSPTR] = { 0x20, 16 }, 356 [SCLSR] = { 0x24, 16 }, 357 }, 358 .fifosize = 16, 359 .overrun_reg = SCLSR, 360 .overrun_mask = SCLSR_ORER, 361 .sampling_rate_mask = SCI_SR(32), 362 .error_mask = SCIF_DEFAULT_ERROR_MASK, 363 .error_clear = SCIF_ERROR_CLEAR, 364 }, 365 366 /* 367 * Common SCIF definitions for ports with a Baud Rate Generator for 368 * External Clock (BRG). 369 */ 370 [SCIx_SH4_SCIF_BRG_REGTYPE] = { 371 .regs = { 372 [SCSMR] = { 0x00, 16 }, 373 [SCBRR] = { 0x04, 8 }, 374 [SCSCR] = { 0x08, 16 }, 375 [SCxTDR] = { 0x0c, 8 }, 376 [SCxSR] = { 0x10, 16 }, 377 [SCxRDR] = { 0x14, 8 }, 378 [SCFCR] = { 0x18, 16 }, 379 [SCFDR] = { 0x1c, 16 }, 380 [SCSPTR] = { 0x20, 16 }, 381 [SCLSR] = { 0x24, 16 }, 382 [SCDL] = { 0x30, 16 }, 383 [SCCKS] = { 0x34, 16 }, 384 }, 385 .fifosize = 16, 386 .overrun_reg = SCLSR, 387 .overrun_mask = SCLSR_ORER, 388 .sampling_rate_mask = SCI_SR(32), 389 .error_mask = SCIF_DEFAULT_ERROR_MASK, 390 .error_clear = SCIF_ERROR_CLEAR, 391 }, 392 393 /* 394 * Common HSCIF definitions. 395 */ 396 [SCIx_HSCIF_REGTYPE] = { 397 .regs = { 398 [SCSMR] = { 0x00, 16 }, 399 [SCBRR] = { 0x04, 8 }, 400 [SCSCR] = { 0x08, 16 }, 401 [SCxTDR] = { 0x0c, 8 }, 402 [SCxSR] = { 0x10, 16 }, 403 [SCxRDR] = { 0x14, 8 }, 404 [SCFCR] = { 0x18, 16 }, 405 [SCFDR] = { 0x1c, 16 }, 406 [SCSPTR] = { 0x20, 16 }, 407 [SCLSR] = { 0x24, 16 }, 408 [HSSRR] = { 0x40, 16 }, 409 [SCDL] = { 0x30, 16 }, 410 [SCCKS] = { 0x34, 16 }, 411 [HSRTRGR] = { 0x54, 16 }, 412 [HSTTRGR] = { 0x58, 16 }, 413 }, 414 .fifosize = 128, 415 .overrun_reg = SCLSR, 416 .overrun_mask = SCLSR_ORER, 417 .sampling_rate_mask = SCI_SR_RANGE(8, 32), 418 .error_mask = SCIF_DEFAULT_ERROR_MASK, 419 .error_clear = SCIF_ERROR_CLEAR, 420 }, 421 422 /* 423 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR 424 * register. 425 */ 426 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = { 427 .regs = { 428 [SCSMR] = { 0x00, 16 }, 429 [SCBRR] = { 0x04, 8 }, 430 [SCSCR] = { 0x08, 16 }, 431 [SCxTDR] = { 0x0c, 8 }, 432 [SCxSR] = { 0x10, 16 }, 433 [SCxRDR] = { 0x14, 8 }, 434 [SCFCR] = { 0x18, 16 }, 435 [SCFDR] = { 0x1c, 16 }, 436 [SCLSR] = { 0x24, 16 }, 437 }, 438 .fifosize = 16, 439 .overrun_reg = SCLSR, 440 .overrun_mask = SCLSR_ORER, 441 .sampling_rate_mask = SCI_SR(32), 442 .error_mask = SCIF_DEFAULT_ERROR_MASK, 443 .error_clear = SCIF_ERROR_CLEAR, 444 }, 445 446 /* 447 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data 448 * count registers. 449 */ 450 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = { 451 .regs = { 452 [SCSMR] = { 0x00, 16 }, 453 [SCBRR] = { 0x04, 8 }, 454 [SCSCR] = { 0x08, 16 }, 455 [SCxTDR] = { 0x0c, 8 }, 456 [SCxSR] = { 0x10, 16 }, 457 [SCxRDR] = { 0x14, 8 }, 458 [SCFCR] = { 0x18, 16 }, 459 [SCFDR] = { 0x1c, 16 }, 460 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */ 461 [SCRFDR] = { 0x20, 16 }, 462 [SCSPTR] = { 0x24, 16 }, 463 [SCLSR] = { 0x28, 16 }, 464 }, 465 .fifosize = 16, 466 .overrun_reg = SCLSR, 467 .overrun_mask = SCLSR_ORER, 468 .sampling_rate_mask = SCI_SR(32), 469 .error_mask = SCIF_DEFAULT_ERROR_MASK, 470 .error_clear = SCIF_ERROR_CLEAR, 471 }, 472 473 /* 474 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR 475 * registers. 476 */ 477 [SCIx_SH7705_SCIF_REGTYPE] = { 478 .regs = { 479 [SCSMR] = { 0x00, 16 }, 480 [SCBRR] = { 0x04, 8 }, 481 [SCSCR] = { 0x08, 16 }, 482 [SCxTDR] = { 0x20, 8 }, 483 [SCxSR] = { 0x14, 16 }, 484 [SCxRDR] = { 0x24, 8 }, 485 [SCFCR] = { 0x18, 16 }, 486 [SCFDR] = { 0x1c, 16 }, 487 }, 488 .fifosize = 64, 489 .overrun_reg = SCxSR, 490 .overrun_mask = SCIFA_ORER, 491 .sampling_rate_mask = SCI_SR(16), 492 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 493 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 494 }, 495 }; 496 497 #define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset]) 498 499 /* 500 * The "offset" here is rather misleading, in that it refers to an enum 501 * value relative to the port mapping rather than the fixed offset 502 * itself, which needs to be manually retrieved from the platform's 503 * register map for the given port. 504 */ 505 static unsigned int sci_serial_in(struct uart_port *p, int offset) 506 { 507 const struct plat_sci_reg *reg = sci_getreg(p, offset); 508 509 if (reg->size == 8) 510 return ioread8(p->membase + (reg->offset << p->regshift)); 511 else if (reg->size == 16) 512 return ioread16(p->membase + (reg->offset << p->regshift)); 513 else 514 WARN(1, "Invalid register access\n"); 515 516 return 0; 517 } 518 519 static void sci_serial_out(struct uart_port *p, int offset, int value) 520 { 521 const struct plat_sci_reg *reg = sci_getreg(p, offset); 522 523 if (reg->size == 8) 524 iowrite8(value, p->membase + (reg->offset << p->regshift)); 525 else if (reg->size == 16) 526 iowrite16(value, p->membase + (reg->offset << p->regshift)); 527 else 528 WARN(1, "Invalid register access\n"); 529 } 530 531 static void sci_port_enable(struct sci_port *sci_port) 532 { 533 unsigned int i; 534 535 if (!sci_port->port.dev) 536 return; 537 538 pm_runtime_get_sync(sci_port->port.dev); 539 540 for (i = 0; i < SCI_NUM_CLKS; i++) { 541 clk_prepare_enable(sci_port->clks[i]); 542 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]); 543 } 544 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK]; 545 } 546 547 static void sci_port_disable(struct sci_port *sci_port) 548 { 549 unsigned int i; 550 551 if (!sci_port->port.dev) 552 return; 553 554 for (i = SCI_NUM_CLKS; i-- > 0; ) 555 clk_disable_unprepare(sci_port->clks[i]); 556 557 pm_runtime_put_sync(sci_port->port.dev); 558 } 559 560 static inline unsigned long port_rx_irq_mask(struct uart_port *port) 561 { 562 /* 563 * Not all ports (such as SCIFA) will support REIE. Rather than 564 * special-casing the port type, we check the port initialization 565 * IRQ enable mask to see whether the IRQ is desired at all. If 566 * it's unset, it's logically inferred that there's no point in 567 * testing for it. 568 */ 569 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE); 570 } 571 572 static void sci_start_tx(struct uart_port *port) 573 { 574 struct sci_port *s = to_sci_port(port); 575 unsigned short ctrl; 576 577 #ifdef CONFIG_SERIAL_SH_SCI_DMA 578 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 579 u16 new, scr = serial_port_in(port, SCSCR); 580 if (s->chan_tx) 581 new = scr | SCSCR_TDRQE; 582 else 583 new = scr & ~SCSCR_TDRQE; 584 if (new != scr) 585 serial_port_out(port, SCSCR, new); 586 } 587 588 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) && 589 dma_submit_error(s->cookie_tx)) { 590 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) 591 /* Switch irq from SCIF to DMA */ 592 disable_irq_nosync(s->irqs[SCIx_TXI_IRQ]); 593 594 s->cookie_tx = 0; 595 schedule_work(&s->work_tx); 596 } 597 #endif 598 599 if (!s->chan_tx || s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE || 600 port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 601 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ 602 ctrl = serial_port_in(port, SCSCR); 603 604 /* 605 * For SCI, TE (transmit enable) must be set after setting TIE 606 * (transmit interrupt enable) or in the same instruction to start 607 * the transmit process. 608 */ 609 if (port->type == PORT_SCI) 610 ctrl |= SCSCR_TE; 611 612 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE); 613 } 614 } 615 616 static void sci_stop_tx(struct uart_port *port) 617 { 618 unsigned short ctrl; 619 620 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ 621 ctrl = serial_port_in(port, SCSCR); 622 623 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 624 ctrl &= ~SCSCR_TDRQE; 625 626 ctrl &= ~SCSCR_TIE; 627 628 serial_port_out(port, SCSCR, ctrl); 629 630 #ifdef CONFIG_SERIAL_SH_SCI_DMA 631 if (to_sci_port(port)->chan_tx && 632 !dma_submit_error(to_sci_port(port)->cookie_tx)) { 633 dmaengine_terminate_async(to_sci_port(port)->chan_tx); 634 to_sci_port(port)->cookie_tx = -EINVAL; 635 } 636 #endif 637 } 638 639 static void sci_start_rx(struct uart_port *port) 640 { 641 unsigned short ctrl; 642 643 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port); 644 645 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 646 ctrl &= ~SCSCR_RDRQE; 647 648 serial_port_out(port, SCSCR, ctrl); 649 } 650 651 static void sci_stop_rx(struct uart_port *port) 652 { 653 unsigned short ctrl; 654 655 ctrl = serial_port_in(port, SCSCR); 656 657 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 658 ctrl &= ~SCSCR_RDRQE; 659 660 ctrl &= ~port_rx_irq_mask(port); 661 662 serial_port_out(port, SCSCR, ctrl); 663 } 664 665 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask) 666 { 667 if (port->type == PORT_SCI) { 668 /* Just store the mask */ 669 serial_port_out(port, SCxSR, mask); 670 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) { 671 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */ 672 /* Only clear the status bits we want to clear */ 673 serial_port_out(port, SCxSR, 674 serial_port_in(port, SCxSR) & mask); 675 } else { 676 /* Store the mask, clear parity/framing errors */ 677 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC)); 678 } 679 } 680 681 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ 682 defined(CONFIG_SERIAL_SH_SCI_EARLYCON) 683 684 #ifdef CONFIG_CONSOLE_POLL 685 static int sci_poll_get_char(struct uart_port *port) 686 { 687 unsigned short status; 688 int c; 689 690 do { 691 status = serial_port_in(port, SCxSR); 692 if (status & SCxSR_ERRORS(port)) { 693 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); 694 continue; 695 } 696 break; 697 } while (1); 698 699 if (!(status & SCxSR_RDxF(port))) 700 return NO_POLL_CHAR; 701 702 c = serial_port_in(port, SCxRDR); 703 704 /* Dummy read */ 705 serial_port_in(port, SCxSR); 706 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 707 708 return c; 709 } 710 #endif 711 712 static void sci_poll_put_char(struct uart_port *port, unsigned char c) 713 { 714 unsigned short status; 715 716 do { 717 status = serial_port_in(port, SCxSR); 718 } while (!(status & SCxSR_TDxE(port))); 719 720 serial_port_out(port, SCxTDR, c); 721 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port)); 722 } 723 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE || 724 CONFIG_SERIAL_SH_SCI_EARLYCON */ 725 726 static void sci_init_pins(struct uart_port *port, unsigned int cflag) 727 { 728 struct sci_port *s = to_sci_port(port); 729 730 /* 731 * Use port-specific handler if provided. 732 */ 733 if (s->cfg->ops && s->cfg->ops->init_pins) { 734 s->cfg->ops->init_pins(port, cflag); 735 return; 736 } 737 738 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 739 u16 data = serial_port_in(port, SCPDR); 740 u16 ctrl = serial_port_in(port, SCPCR); 741 742 /* Enable RXD and TXD pin functions */ 743 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC); 744 if (to_sci_port(port)->has_rtscts) { 745 /* RTS# is output, active low, unless autorts */ 746 if (!(port->mctrl & TIOCM_RTS)) { 747 ctrl |= SCPCR_RTSC; 748 data |= SCPDR_RTSD; 749 } else if (!s->autorts) { 750 ctrl |= SCPCR_RTSC; 751 data &= ~SCPDR_RTSD; 752 } else { 753 /* Enable RTS# pin function */ 754 ctrl &= ~SCPCR_RTSC; 755 } 756 /* Enable CTS# pin function */ 757 ctrl &= ~SCPCR_CTSC; 758 } 759 serial_port_out(port, SCPDR, data); 760 serial_port_out(port, SCPCR, ctrl); 761 } else if (sci_getreg(port, SCSPTR)->size) { 762 u16 status = serial_port_in(port, SCSPTR); 763 764 /* RTS# is always output; and active low, unless autorts */ 765 status |= SCSPTR_RTSIO; 766 if (!(port->mctrl & TIOCM_RTS)) 767 status |= SCSPTR_RTSDT; 768 else if (!s->autorts) 769 status &= ~SCSPTR_RTSDT; 770 /* CTS# and SCK are inputs */ 771 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO); 772 serial_port_out(port, SCSPTR, status); 773 } 774 } 775 776 static int sci_txfill(struct uart_port *port) 777 { 778 struct sci_port *s = to_sci_port(port); 779 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; 780 const struct plat_sci_reg *reg; 781 782 reg = sci_getreg(port, SCTFDR); 783 if (reg->size) 784 return serial_port_in(port, SCTFDR) & fifo_mask; 785 786 reg = sci_getreg(port, SCFDR); 787 if (reg->size) 788 return serial_port_in(port, SCFDR) >> 8; 789 790 return !(serial_port_in(port, SCxSR) & SCI_TDRE); 791 } 792 793 static int sci_txroom(struct uart_port *port) 794 { 795 return port->fifosize - sci_txfill(port); 796 } 797 798 static int sci_rxfill(struct uart_port *port) 799 { 800 struct sci_port *s = to_sci_port(port); 801 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; 802 const struct plat_sci_reg *reg; 803 804 reg = sci_getreg(port, SCRFDR); 805 if (reg->size) 806 return serial_port_in(port, SCRFDR) & fifo_mask; 807 808 reg = sci_getreg(port, SCFDR); 809 if (reg->size) 810 return serial_port_in(port, SCFDR) & fifo_mask; 811 812 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0; 813 } 814 815 /* ********************************************************************** * 816 * the interrupt related routines * 817 * ********************************************************************** */ 818 819 static void sci_transmit_chars(struct uart_port *port) 820 { 821 struct circ_buf *xmit = &port->state->xmit; 822 unsigned int stopped = uart_tx_stopped(port); 823 unsigned short status; 824 unsigned short ctrl; 825 int count; 826 827 status = serial_port_in(port, SCxSR); 828 if (!(status & SCxSR_TDxE(port))) { 829 ctrl = serial_port_in(port, SCSCR); 830 if (uart_circ_empty(xmit)) 831 ctrl &= ~SCSCR_TIE; 832 else 833 ctrl |= SCSCR_TIE; 834 serial_port_out(port, SCSCR, ctrl); 835 return; 836 } 837 838 count = sci_txroom(port); 839 840 do { 841 unsigned char c; 842 843 if (port->x_char) { 844 c = port->x_char; 845 port->x_char = 0; 846 } else if (!uart_circ_empty(xmit) && !stopped) { 847 c = xmit->buf[xmit->tail]; 848 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 849 } else if (port->type == PORT_SCI && uart_circ_empty(xmit)) { 850 ctrl = serial_port_in(port, SCSCR); 851 ctrl &= ~SCSCR_TE; 852 serial_port_out(port, SCSCR, ctrl); 853 return; 854 } else { 855 break; 856 } 857 858 serial_port_out(port, SCxTDR, c); 859 860 port->icount.tx++; 861 } while (--count > 0); 862 863 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port)); 864 865 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 866 uart_write_wakeup(port); 867 if (uart_circ_empty(xmit)) { 868 if (port->type == PORT_SCI) { 869 ctrl = serial_port_in(port, SCSCR); 870 ctrl &= ~SCSCR_TIE; 871 ctrl |= SCSCR_TEIE; 872 serial_port_out(port, SCSCR, ctrl); 873 } 874 875 sci_stop_tx(port); 876 } 877 } 878 879 static void sci_receive_chars(struct uart_port *port) 880 { 881 struct tty_port *tport = &port->state->port; 882 int i, count, copied = 0; 883 unsigned short status; 884 unsigned char flag; 885 886 status = serial_port_in(port, SCxSR); 887 if (!(status & SCxSR_RDxF(port))) 888 return; 889 890 while (1) { 891 /* Don't copy more bytes than there is room for in the buffer */ 892 count = tty_buffer_request_room(tport, sci_rxfill(port)); 893 894 /* If for any reason we can't copy more data, we're done! */ 895 if (count == 0) 896 break; 897 898 if (port->type == PORT_SCI) { 899 char c = serial_port_in(port, SCxRDR); 900 if (uart_handle_sysrq_char(port, c)) 901 count = 0; 902 else 903 tty_insert_flip_char(tport, c, TTY_NORMAL); 904 } else { 905 for (i = 0; i < count; i++) { 906 char c; 907 908 if (port->type == PORT_SCIF || 909 port->type == PORT_HSCIF) { 910 status = serial_port_in(port, SCxSR); 911 c = serial_port_in(port, SCxRDR); 912 } else { 913 c = serial_port_in(port, SCxRDR); 914 status = serial_port_in(port, SCxSR); 915 } 916 if (uart_handle_sysrq_char(port, c)) { 917 count--; i--; 918 continue; 919 } 920 921 /* Store data and status */ 922 if (status & SCxSR_FER(port)) { 923 flag = TTY_FRAME; 924 port->icount.frame++; 925 } else if (status & SCxSR_PER(port)) { 926 flag = TTY_PARITY; 927 port->icount.parity++; 928 } else 929 flag = TTY_NORMAL; 930 931 tty_insert_flip_char(tport, c, flag); 932 } 933 } 934 935 serial_port_in(port, SCxSR); /* dummy read */ 936 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 937 938 copied += count; 939 port->icount.rx += count; 940 } 941 942 if (copied) { 943 /* Tell the rest of the system the news. New characters! */ 944 tty_flip_buffer_push(tport); 945 } else { 946 /* TTY buffers full; read from RX reg to prevent lockup */ 947 serial_port_in(port, SCxRDR); 948 serial_port_in(port, SCxSR); /* dummy read */ 949 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 950 } 951 } 952 953 static int sci_handle_errors(struct uart_port *port) 954 { 955 int copied = 0; 956 unsigned short status = serial_port_in(port, SCxSR); 957 struct tty_port *tport = &port->state->port; 958 struct sci_port *s = to_sci_port(port); 959 960 /* Handle overruns */ 961 if (status & s->params->overrun_mask) { 962 port->icount.overrun++; 963 964 /* overrun error */ 965 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN)) 966 copied++; 967 } 968 969 if (status & SCxSR_FER(port)) { 970 /* frame error */ 971 port->icount.frame++; 972 973 if (tty_insert_flip_char(tport, 0, TTY_FRAME)) 974 copied++; 975 } 976 977 if (status & SCxSR_PER(port)) { 978 /* parity error */ 979 port->icount.parity++; 980 981 if (tty_insert_flip_char(tport, 0, TTY_PARITY)) 982 copied++; 983 } 984 985 if (copied) 986 tty_flip_buffer_push(tport); 987 988 return copied; 989 } 990 991 static int sci_handle_fifo_overrun(struct uart_port *port) 992 { 993 struct tty_port *tport = &port->state->port; 994 struct sci_port *s = to_sci_port(port); 995 const struct plat_sci_reg *reg; 996 int copied = 0; 997 u16 status; 998 999 reg = sci_getreg(port, s->params->overrun_reg); 1000 if (!reg->size) 1001 return 0; 1002 1003 status = serial_port_in(port, s->params->overrun_reg); 1004 if (status & s->params->overrun_mask) { 1005 status &= ~s->params->overrun_mask; 1006 serial_port_out(port, s->params->overrun_reg, status); 1007 1008 port->icount.overrun++; 1009 1010 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 1011 tty_flip_buffer_push(tport); 1012 copied++; 1013 } 1014 1015 return copied; 1016 } 1017 1018 static int sci_handle_breaks(struct uart_port *port) 1019 { 1020 int copied = 0; 1021 unsigned short status = serial_port_in(port, SCxSR); 1022 struct tty_port *tport = &port->state->port; 1023 1024 if (uart_handle_break(port)) 1025 return 0; 1026 1027 if (status & SCxSR_BRK(port)) { 1028 port->icount.brk++; 1029 1030 /* Notify of BREAK */ 1031 if (tty_insert_flip_char(tport, 0, TTY_BREAK)) 1032 copied++; 1033 } 1034 1035 if (copied) 1036 tty_flip_buffer_push(tport); 1037 1038 copied += sci_handle_fifo_overrun(port); 1039 1040 return copied; 1041 } 1042 1043 static int scif_set_rtrg(struct uart_port *port, int rx_trig) 1044 { 1045 unsigned int bits; 1046 1047 if (rx_trig >= port->fifosize) 1048 rx_trig = port->fifosize - 1; 1049 if (rx_trig < 1) 1050 rx_trig = 1; 1051 1052 /* HSCIF can be set to an arbitrary level. */ 1053 if (sci_getreg(port, HSRTRGR)->size) { 1054 serial_port_out(port, HSRTRGR, rx_trig); 1055 return rx_trig; 1056 } 1057 1058 switch (port->type) { 1059 case PORT_SCIF: 1060 if (rx_trig < 4) { 1061 bits = 0; 1062 rx_trig = 1; 1063 } else if (rx_trig < 8) { 1064 bits = SCFCR_RTRG0; 1065 rx_trig = 4; 1066 } else if (rx_trig < 14) { 1067 bits = SCFCR_RTRG1; 1068 rx_trig = 8; 1069 } else { 1070 bits = SCFCR_RTRG0 | SCFCR_RTRG1; 1071 rx_trig = 14; 1072 } 1073 break; 1074 case PORT_SCIFA: 1075 case PORT_SCIFB: 1076 if (rx_trig < 16) { 1077 bits = 0; 1078 rx_trig = 1; 1079 } else if (rx_trig < 32) { 1080 bits = SCFCR_RTRG0; 1081 rx_trig = 16; 1082 } else if (rx_trig < 48) { 1083 bits = SCFCR_RTRG1; 1084 rx_trig = 32; 1085 } else { 1086 bits = SCFCR_RTRG0 | SCFCR_RTRG1; 1087 rx_trig = 48; 1088 } 1089 break; 1090 default: 1091 WARN(1, "unknown FIFO configuration"); 1092 return 1; 1093 } 1094 1095 serial_port_out(port, SCFCR, 1096 (serial_port_in(port, SCFCR) & 1097 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits); 1098 1099 return rx_trig; 1100 } 1101 1102 static int scif_rtrg_enabled(struct uart_port *port) 1103 { 1104 if (sci_getreg(port, HSRTRGR)->size) 1105 return serial_port_in(port, HSRTRGR) != 0; 1106 else 1107 return (serial_port_in(port, SCFCR) & 1108 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0; 1109 } 1110 1111 static void rx_fifo_timer_fn(struct timer_list *t) 1112 { 1113 struct sci_port *s = from_timer(s, t, rx_fifo_timer); 1114 struct uart_port *port = &s->port; 1115 1116 dev_dbg(port->dev, "Rx timed out\n"); 1117 scif_set_rtrg(port, 1); 1118 } 1119 1120 static ssize_t rx_fifo_trigger_show(struct device *dev, 1121 struct device_attribute *attr, char *buf) 1122 { 1123 struct uart_port *port = dev_get_drvdata(dev); 1124 struct sci_port *sci = to_sci_port(port); 1125 1126 return sprintf(buf, "%d\n", sci->rx_trigger); 1127 } 1128 1129 static ssize_t rx_fifo_trigger_store(struct device *dev, 1130 struct device_attribute *attr, 1131 const char *buf, size_t count) 1132 { 1133 struct uart_port *port = dev_get_drvdata(dev); 1134 struct sci_port *sci = to_sci_port(port); 1135 int ret; 1136 long r; 1137 1138 ret = kstrtol(buf, 0, &r); 1139 if (ret) 1140 return ret; 1141 1142 sci->rx_trigger = scif_set_rtrg(port, r); 1143 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1144 scif_set_rtrg(port, 1); 1145 1146 return count; 1147 } 1148 1149 static DEVICE_ATTR_RW(rx_fifo_trigger); 1150 1151 static ssize_t rx_fifo_timeout_show(struct device *dev, 1152 struct device_attribute *attr, 1153 char *buf) 1154 { 1155 struct uart_port *port = dev_get_drvdata(dev); 1156 struct sci_port *sci = to_sci_port(port); 1157 int v; 1158 1159 if (port->type == PORT_HSCIF) 1160 v = sci->hscif_tot >> HSSCR_TOT_SHIFT; 1161 else 1162 v = sci->rx_fifo_timeout; 1163 1164 return sprintf(buf, "%d\n", v); 1165 } 1166 1167 static ssize_t rx_fifo_timeout_store(struct device *dev, 1168 struct device_attribute *attr, 1169 const char *buf, 1170 size_t count) 1171 { 1172 struct uart_port *port = dev_get_drvdata(dev); 1173 struct sci_port *sci = to_sci_port(port); 1174 int ret; 1175 long r; 1176 1177 ret = kstrtol(buf, 0, &r); 1178 if (ret) 1179 return ret; 1180 1181 if (port->type == PORT_HSCIF) { 1182 if (r < 0 || r > 3) 1183 return -EINVAL; 1184 sci->hscif_tot = r << HSSCR_TOT_SHIFT; 1185 } else { 1186 sci->rx_fifo_timeout = r; 1187 scif_set_rtrg(port, 1); 1188 if (r > 0) 1189 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0); 1190 } 1191 1192 return count; 1193 } 1194 1195 static DEVICE_ATTR_RW(rx_fifo_timeout); 1196 1197 1198 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1199 static void sci_dma_tx_complete(void *arg) 1200 { 1201 struct sci_port *s = arg; 1202 struct uart_port *port = &s->port; 1203 struct circ_buf *xmit = &port->state->xmit; 1204 unsigned long flags; 1205 1206 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1207 1208 spin_lock_irqsave(&port->lock, flags); 1209 1210 uart_xmit_advance(port, s->tx_dma_len); 1211 1212 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1213 uart_write_wakeup(port); 1214 1215 if (!uart_circ_empty(xmit)) { 1216 s->cookie_tx = 0; 1217 schedule_work(&s->work_tx); 1218 } else { 1219 s->cookie_tx = -EINVAL; 1220 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || 1221 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { 1222 u16 ctrl = serial_port_in(port, SCSCR); 1223 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE); 1224 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { 1225 /* Switch irq from DMA to SCIF */ 1226 dmaengine_pause(s->chan_tx_saved); 1227 enable_irq(s->irqs[SCIx_TXI_IRQ]); 1228 } 1229 } 1230 } 1231 1232 spin_unlock_irqrestore(&port->lock, flags); 1233 } 1234 1235 /* Locking: called with port lock held */ 1236 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count) 1237 { 1238 struct uart_port *port = &s->port; 1239 struct tty_port *tport = &port->state->port; 1240 int copied; 1241 1242 copied = tty_insert_flip_string(tport, buf, count); 1243 if (copied < count) 1244 port->icount.buf_overrun++; 1245 1246 port->icount.rx += copied; 1247 1248 return copied; 1249 } 1250 1251 static int sci_dma_rx_find_active(struct sci_port *s) 1252 { 1253 unsigned int i; 1254 1255 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) 1256 if (s->active_rx == s->cookie_rx[i]) 1257 return i; 1258 1259 return -1; 1260 } 1261 1262 static void sci_dma_rx_chan_invalidate(struct sci_port *s) 1263 { 1264 unsigned int i; 1265 1266 s->chan_rx = NULL; 1267 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) 1268 s->cookie_rx[i] = -EINVAL; 1269 s->active_rx = 0; 1270 } 1271 1272 static void sci_dma_rx_release(struct sci_port *s) 1273 { 1274 struct dma_chan *chan = s->chan_rx_saved; 1275 struct uart_port *port = &s->port; 1276 unsigned long flags; 1277 1278 uart_port_lock_irqsave(port, &flags); 1279 s->chan_rx_saved = NULL; 1280 sci_dma_rx_chan_invalidate(s); 1281 uart_port_unlock_irqrestore(port, flags); 1282 1283 dmaengine_terminate_sync(chan); 1284 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0], 1285 sg_dma_address(&s->sg_rx[0])); 1286 dma_release_channel(chan); 1287 } 1288 1289 static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec) 1290 { 1291 long sec = usec / 1000000; 1292 long nsec = (usec % 1000000) * 1000; 1293 ktime_t t = ktime_set(sec, nsec); 1294 1295 hrtimer_start(hrt, t, HRTIMER_MODE_REL); 1296 } 1297 1298 static void sci_dma_rx_reenable_irq(struct sci_port *s) 1299 { 1300 struct uart_port *port = &s->port; 1301 u16 scr; 1302 1303 /* Direct new serial port interrupts back to CPU */ 1304 scr = serial_port_in(port, SCSCR); 1305 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || 1306 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { 1307 enable_irq(s->irqs[SCIx_RXI_IRQ]); 1308 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) 1309 scif_set_rtrg(port, s->rx_trigger); 1310 else 1311 scr &= ~SCSCR_RDRQE; 1312 } 1313 serial_port_out(port, SCSCR, scr | SCSCR_RIE); 1314 } 1315 1316 static void sci_dma_rx_complete(void *arg) 1317 { 1318 struct sci_port *s = arg; 1319 struct dma_chan *chan = s->chan_rx; 1320 struct uart_port *port = &s->port; 1321 struct dma_async_tx_descriptor *desc; 1322 unsigned long flags; 1323 int active, count = 0; 1324 1325 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line, 1326 s->active_rx); 1327 1328 spin_lock_irqsave(&port->lock, flags); 1329 1330 active = sci_dma_rx_find_active(s); 1331 if (active >= 0) 1332 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx); 1333 1334 start_hrtimer_us(&s->rx_timer, s->rx_timeout); 1335 1336 if (count) 1337 tty_flip_buffer_push(&port->state->port); 1338 1339 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1, 1340 DMA_DEV_TO_MEM, 1341 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1342 if (!desc) 1343 goto fail; 1344 1345 desc->callback = sci_dma_rx_complete; 1346 desc->callback_param = s; 1347 s->cookie_rx[active] = dmaengine_submit(desc); 1348 if (dma_submit_error(s->cookie_rx[active])) 1349 goto fail; 1350 1351 s->active_rx = s->cookie_rx[!active]; 1352 1353 dma_async_issue_pending(chan); 1354 1355 spin_unlock_irqrestore(&port->lock, flags); 1356 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n", 1357 __func__, s->cookie_rx[active], active, s->active_rx); 1358 return; 1359 1360 fail: 1361 spin_unlock_irqrestore(&port->lock, flags); 1362 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n"); 1363 /* Switch to PIO */ 1364 spin_lock_irqsave(&port->lock, flags); 1365 dmaengine_terminate_async(chan); 1366 sci_dma_rx_chan_invalidate(s); 1367 sci_dma_rx_reenable_irq(s); 1368 spin_unlock_irqrestore(&port->lock, flags); 1369 } 1370 1371 static void sci_dma_tx_release(struct sci_port *s) 1372 { 1373 struct dma_chan *chan = s->chan_tx_saved; 1374 1375 cancel_work_sync(&s->work_tx); 1376 s->chan_tx_saved = s->chan_tx = NULL; 1377 s->cookie_tx = -EINVAL; 1378 dmaengine_terminate_sync(chan); 1379 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE, 1380 DMA_TO_DEVICE); 1381 dma_release_channel(chan); 1382 } 1383 1384 static int sci_dma_rx_submit(struct sci_port *s, bool port_lock_held) 1385 { 1386 struct dma_chan *chan = s->chan_rx; 1387 struct uart_port *port = &s->port; 1388 unsigned long flags; 1389 int i; 1390 1391 for (i = 0; i < 2; i++) { 1392 struct scatterlist *sg = &s->sg_rx[i]; 1393 struct dma_async_tx_descriptor *desc; 1394 1395 desc = dmaengine_prep_slave_sg(chan, 1396 sg, 1, DMA_DEV_TO_MEM, 1397 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1398 if (!desc) 1399 goto fail; 1400 1401 desc->callback = sci_dma_rx_complete; 1402 desc->callback_param = s; 1403 s->cookie_rx[i] = dmaengine_submit(desc); 1404 if (dma_submit_error(s->cookie_rx[i])) 1405 goto fail; 1406 1407 } 1408 1409 s->active_rx = s->cookie_rx[0]; 1410 1411 dma_async_issue_pending(chan); 1412 return 0; 1413 1414 fail: 1415 /* Switch to PIO */ 1416 if (!port_lock_held) 1417 spin_lock_irqsave(&port->lock, flags); 1418 if (i) 1419 dmaengine_terminate_async(chan); 1420 sci_dma_rx_chan_invalidate(s); 1421 sci_start_rx(port); 1422 if (!port_lock_held) 1423 spin_unlock_irqrestore(&port->lock, flags); 1424 return -EAGAIN; 1425 } 1426 1427 static void sci_dma_tx_work_fn(struct work_struct *work) 1428 { 1429 struct sci_port *s = container_of(work, struct sci_port, work_tx); 1430 struct dma_async_tx_descriptor *desc; 1431 struct dma_chan *chan = s->chan_tx; 1432 struct uart_port *port = &s->port; 1433 struct circ_buf *xmit = &port->state->xmit; 1434 unsigned long flags; 1435 dma_addr_t buf; 1436 int head, tail; 1437 1438 /* 1439 * DMA is idle now. 1440 * Port xmit buffer is already mapped, and it is one page... Just adjust 1441 * offsets and lengths. Since it is a circular buffer, we have to 1442 * transmit till the end, and then the rest. Take the port lock to get a 1443 * consistent xmit buffer state. 1444 */ 1445 spin_lock_irq(&port->lock); 1446 head = xmit->head; 1447 tail = xmit->tail; 1448 buf = s->tx_dma_addr + tail; 1449 s->tx_dma_len = CIRC_CNT_TO_END(head, tail, UART_XMIT_SIZE); 1450 if (!s->tx_dma_len) { 1451 /* Transmit buffer has been flushed */ 1452 spin_unlock_irq(&port->lock); 1453 return; 1454 } 1455 1456 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len, 1457 DMA_MEM_TO_DEV, 1458 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1459 if (!desc) { 1460 spin_unlock_irq(&port->lock); 1461 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n"); 1462 goto switch_to_pio; 1463 } 1464 1465 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len, 1466 DMA_TO_DEVICE); 1467 1468 desc->callback = sci_dma_tx_complete; 1469 desc->callback_param = s; 1470 s->cookie_tx = dmaengine_submit(desc); 1471 if (dma_submit_error(s->cookie_tx)) { 1472 spin_unlock_irq(&port->lock); 1473 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n"); 1474 goto switch_to_pio; 1475 } 1476 1477 spin_unlock_irq(&port->lock); 1478 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", 1479 __func__, xmit->buf, tail, head, s->cookie_tx); 1480 1481 dma_async_issue_pending(chan); 1482 return; 1483 1484 switch_to_pio: 1485 spin_lock_irqsave(&port->lock, flags); 1486 s->chan_tx = NULL; 1487 sci_start_tx(port); 1488 spin_unlock_irqrestore(&port->lock, flags); 1489 return; 1490 } 1491 1492 static enum hrtimer_restart sci_dma_rx_timer_fn(struct hrtimer *t) 1493 { 1494 struct sci_port *s = container_of(t, struct sci_port, rx_timer); 1495 struct dma_chan *chan = s->chan_rx; 1496 struct uart_port *port = &s->port; 1497 struct dma_tx_state state; 1498 enum dma_status status; 1499 unsigned long flags; 1500 unsigned int read; 1501 int active, count; 1502 1503 dev_dbg(port->dev, "DMA Rx timed out\n"); 1504 1505 spin_lock_irqsave(&port->lock, flags); 1506 1507 active = sci_dma_rx_find_active(s); 1508 if (active < 0) { 1509 spin_unlock_irqrestore(&port->lock, flags); 1510 return HRTIMER_NORESTART; 1511 } 1512 1513 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); 1514 if (status == DMA_COMPLETE) { 1515 spin_unlock_irqrestore(&port->lock, flags); 1516 dev_dbg(port->dev, "Cookie %d #%d has already completed\n", 1517 s->active_rx, active); 1518 1519 /* Let packet complete handler take care of the packet */ 1520 return HRTIMER_NORESTART; 1521 } 1522 1523 dmaengine_pause(chan); 1524 1525 /* 1526 * sometimes DMA transfer doesn't stop even if it is stopped and 1527 * data keeps on coming until transaction is complete so check 1528 * for DMA_COMPLETE again 1529 * Let packet complete handler take care of the packet 1530 */ 1531 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); 1532 if (status == DMA_COMPLETE) { 1533 spin_unlock_irqrestore(&port->lock, flags); 1534 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped"); 1535 return HRTIMER_NORESTART; 1536 } 1537 1538 /* Handle incomplete DMA receive */ 1539 dmaengine_terminate_async(s->chan_rx); 1540 read = sg_dma_len(&s->sg_rx[active]) - state.residue; 1541 1542 if (read) { 1543 count = sci_dma_rx_push(s, s->rx_buf[active], read); 1544 if (count) 1545 tty_flip_buffer_push(&port->state->port); 1546 } 1547 1548 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || 1549 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) 1550 sci_dma_rx_submit(s, true); 1551 1552 sci_dma_rx_reenable_irq(s); 1553 1554 spin_unlock_irqrestore(&port->lock, flags); 1555 1556 return HRTIMER_NORESTART; 1557 } 1558 1559 static struct dma_chan *sci_request_dma_chan(struct uart_port *port, 1560 enum dma_transfer_direction dir) 1561 { 1562 struct dma_chan *chan; 1563 struct dma_slave_config cfg; 1564 int ret; 1565 1566 chan = dma_request_slave_channel(port->dev, 1567 dir == DMA_MEM_TO_DEV ? "tx" : "rx"); 1568 if (!chan) { 1569 dev_dbg(port->dev, "dma_request_slave_channel failed\n"); 1570 return NULL; 1571 } 1572 1573 memset(&cfg, 0, sizeof(cfg)); 1574 cfg.direction = dir; 1575 cfg.dst_addr = port->mapbase + 1576 (sci_getreg(port, SCxTDR)->offset << port->regshift); 1577 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1578 cfg.src_addr = port->mapbase + 1579 (sci_getreg(port, SCxRDR)->offset << port->regshift); 1580 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1581 1582 ret = dmaengine_slave_config(chan, &cfg); 1583 if (ret) { 1584 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret); 1585 dma_release_channel(chan); 1586 return NULL; 1587 } 1588 1589 return chan; 1590 } 1591 1592 static void sci_request_dma(struct uart_port *port) 1593 { 1594 struct sci_port *s = to_sci_port(port); 1595 struct dma_chan *chan; 1596 1597 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line); 1598 1599 /* 1600 * DMA on console may interfere with Kernel log messages which use 1601 * plain putchar(). So, simply don't use it with a console. 1602 */ 1603 if (uart_console(port)) 1604 return; 1605 1606 if (!port->dev->of_node) 1607 return; 1608 1609 s->cookie_tx = -EINVAL; 1610 1611 /* 1612 * Don't request a dma channel if no channel was specified 1613 * in the device tree. 1614 */ 1615 if (!of_property_present(port->dev->of_node, "dmas")) 1616 return; 1617 1618 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV); 1619 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan); 1620 if (chan) { 1621 /* UART circular tx buffer is an aligned page. */ 1622 s->tx_dma_addr = dma_map_single(chan->device->dev, 1623 port->state->xmit.buf, 1624 UART_XMIT_SIZE, 1625 DMA_TO_DEVICE); 1626 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) { 1627 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n"); 1628 dma_release_channel(chan); 1629 } else { 1630 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n", 1631 __func__, UART_XMIT_SIZE, 1632 port->state->xmit.buf, &s->tx_dma_addr); 1633 1634 INIT_WORK(&s->work_tx, sci_dma_tx_work_fn); 1635 s->chan_tx_saved = s->chan_tx = chan; 1636 } 1637 } 1638 1639 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM); 1640 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan); 1641 if (chan) { 1642 unsigned int i; 1643 dma_addr_t dma; 1644 void *buf; 1645 1646 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize); 1647 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2, 1648 &dma, GFP_KERNEL); 1649 if (!buf) { 1650 dev_warn(port->dev, 1651 "Failed to allocate Rx dma buffer, using PIO\n"); 1652 dma_release_channel(chan); 1653 return; 1654 } 1655 1656 for (i = 0; i < 2; i++) { 1657 struct scatterlist *sg = &s->sg_rx[i]; 1658 1659 sg_init_table(sg, 1); 1660 s->rx_buf[i] = buf; 1661 sg_dma_address(sg) = dma; 1662 sg_dma_len(sg) = s->buf_len_rx; 1663 1664 buf += s->buf_len_rx; 1665 dma += s->buf_len_rx; 1666 } 1667 1668 hrtimer_init(&s->rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 1669 s->rx_timer.function = sci_dma_rx_timer_fn; 1670 1671 s->chan_rx_saved = s->chan_rx = chan; 1672 1673 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || 1674 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) 1675 sci_dma_rx_submit(s, false); 1676 } 1677 } 1678 1679 static void sci_free_dma(struct uart_port *port) 1680 { 1681 struct sci_port *s = to_sci_port(port); 1682 1683 if (s->chan_tx_saved) 1684 sci_dma_tx_release(s); 1685 if (s->chan_rx_saved) 1686 sci_dma_rx_release(s); 1687 } 1688 1689 static void sci_flush_buffer(struct uart_port *port) 1690 { 1691 struct sci_port *s = to_sci_port(port); 1692 1693 /* 1694 * In uart_flush_buffer(), the xmit circular buffer has just been 1695 * cleared, so we have to reset tx_dma_len accordingly, and stop any 1696 * pending transfers 1697 */ 1698 s->tx_dma_len = 0; 1699 if (s->chan_tx) { 1700 dmaengine_terminate_async(s->chan_tx); 1701 s->cookie_tx = -EINVAL; 1702 } 1703 } 1704 #else /* !CONFIG_SERIAL_SH_SCI_DMA */ 1705 static inline void sci_request_dma(struct uart_port *port) 1706 { 1707 } 1708 1709 static inline void sci_free_dma(struct uart_port *port) 1710 { 1711 } 1712 1713 #define sci_flush_buffer NULL 1714 #endif /* !CONFIG_SERIAL_SH_SCI_DMA */ 1715 1716 static irqreturn_t sci_rx_interrupt(int irq, void *ptr) 1717 { 1718 struct uart_port *port = ptr; 1719 struct sci_port *s = to_sci_port(port); 1720 1721 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1722 if (s->chan_rx) { 1723 u16 scr = serial_port_in(port, SCSCR); 1724 u16 ssr = serial_port_in(port, SCxSR); 1725 1726 /* Disable future Rx interrupts */ 1727 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || 1728 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { 1729 disable_irq_nosync(s->irqs[SCIx_RXI_IRQ]); 1730 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { 1731 scif_set_rtrg(port, 1); 1732 scr |= SCSCR_RIE; 1733 } else { 1734 scr |= SCSCR_RDRQE; 1735 } 1736 } else { 1737 if (sci_dma_rx_submit(s, false) < 0) 1738 goto handle_pio; 1739 1740 scr &= ~SCSCR_RIE; 1741 } 1742 serial_port_out(port, SCSCR, scr); 1743 /* Clear current interrupt */ 1744 serial_port_out(port, SCxSR, 1745 ssr & ~(SCIF_DR | SCxSR_RDxF(port))); 1746 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n", 1747 jiffies, s->rx_timeout); 1748 start_hrtimer_us(&s->rx_timer, s->rx_timeout); 1749 1750 return IRQ_HANDLED; 1751 } 1752 1753 handle_pio: 1754 #endif 1755 1756 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) { 1757 if (!scif_rtrg_enabled(port)) 1758 scif_set_rtrg(port, s->rx_trigger); 1759 1760 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP( 1761 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000)); 1762 } 1763 1764 /* I think sci_receive_chars has to be called irrespective 1765 * of whether the I_IXOFF is set, otherwise, how is the interrupt 1766 * to be disabled? 1767 */ 1768 sci_receive_chars(port); 1769 1770 return IRQ_HANDLED; 1771 } 1772 1773 static irqreturn_t sci_tx_interrupt(int irq, void *ptr) 1774 { 1775 struct uart_port *port = ptr; 1776 unsigned long flags; 1777 1778 spin_lock_irqsave(&port->lock, flags); 1779 sci_transmit_chars(port); 1780 spin_unlock_irqrestore(&port->lock, flags); 1781 1782 return IRQ_HANDLED; 1783 } 1784 1785 static irqreturn_t sci_tx_end_interrupt(int irq, void *ptr) 1786 { 1787 struct uart_port *port = ptr; 1788 unsigned long flags; 1789 unsigned short ctrl; 1790 1791 if (port->type != PORT_SCI) 1792 return sci_tx_interrupt(irq, ptr); 1793 1794 spin_lock_irqsave(&port->lock, flags); 1795 ctrl = serial_port_in(port, SCSCR); 1796 ctrl &= ~(SCSCR_TE | SCSCR_TEIE); 1797 serial_port_out(port, SCSCR, ctrl); 1798 spin_unlock_irqrestore(&port->lock, flags); 1799 1800 return IRQ_HANDLED; 1801 } 1802 1803 static irqreturn_t sci_br_interrupt(int irq, void *ptr) 1804 { 1805 struct uart_port *port = ptr; 1806 1807 /* Handle BREAKs */ 1808 sci_handle_breaks(port); 1809 1810 /* drop invalid character received before break was detected */ 1811 serial_port_in(port, SCxRDR); 1812 1813 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port)); 1814 1815 return IRQ_HANDLED; 1816 } 1817 1818 static irqreturn_t sci_er_interrupt(int irq, void *ptr) 1819 { 1820 struct uart_port *port = ptr; 1821 struct sci_port *s = to_sci_port(port); 1822 1823 if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) { 1824 /* Break and Error interrupts are muxed */ 1825 unsigned short ssr_status = serial_port_in(port, SCxSR); 1826 1827 /* Break Interrupt */ 1828 if (ssr_status & SCxSR_BRK(port)) 1829 sci_br_interrupt(irq, ptr); 1830 1831 /* Break only? */ 1832 if (!(ssr_status & SCxSR_ERRORS(port))) 1833 return IRQ_HANDLED; 1834 } 1835 1836 /* Handle errors */ 1837 if (port->type == PORT_SCI) { 1838 if (sci_handle_errors(port)) { 1839 /* discard character in rx buffer */ 1840 serial_port_in(port, SCxSR); 1841 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 1842 } 1843 } else { 1844 sci_handle_fifo_overrun(port); 1845 if (!s->chan_rx) 1846 sci_receive_chars(port); 1847 } 1848 1849 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); 1850 1851 /* Kick the transmission */ 1852 if (!s->chan_tx) 1853 sci_tx_interrupt(irq, ptr); 1854 1855 return IRQ_HANDLED; 1856 } 1857 1858 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) 1859 { 1860 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0; 1861 struct uart_port *port = ptr; 1862 struct sci_port *s = to_sci_port(port); 1863 irqreturn_t ret = IRQ_NONE; 1864 1865 ssr_status = serial_port_in(port, SCxSR); 1866 scr_status = serial_port_in(port, SCSCR); 1867 if (s->params->overrun_reg == SCxSR) 1868 orer_status = ssr_status; 1869 else if (sci_getreg(port, s->params->overrun_reg)->size) 1870 orer_status = serial_port_in(port, s->params->overrun_reg); 1871 1872 err_enabled = scr_status & port_rx_irq_mask(port); 1873 1874 /* Tx Interrupt */ 1875 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) && 1876 !s->chan_tx) 1877 ret = sci_tx_interrupt(irq, ptr); 1878 1879 /* 1880 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF / 1881 * DR flags 1882 */ 1883 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) && 1884 (scr_status & SCSCR_RIE)) 1885 ret = sci_rx_interrupt(irq, ptr); 1886 1887 /* Error Interrupt */ 1888 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled) 1889 ret = sci_er_interrupt(irq, ptr); 1890 1891 /* Break Interrupt */ 1892 if (s->irqs[SCIx_ERI_IRQ] != s->irqs[SCIx_BRI_IRQ] && 1893 (ssr_status & SCxSR_BRK(port)) && err_enabled) 1894 ret = sci_br_interrupt(irq, ptr); 1895 1896 /* Overrun Interrupt */ 1897 if (orer_status & s->params->overrun_mask) { 1898 sci_handle_fifo_overrun(port); 1899 ret = IRQ_HANDLED; 1900 } 1901 1902 return ret; 1903 } 1904 1905 static const struct sci_irq_desc { 1906 const char *desc; 1907 irq_handler_t handler; 1908 } sci_irq_desc[] = { 1909 /* 1910 * Split out handlers, the default case. 1911 */ 1912 [SCIx_ERI_IRQ] = { 1913 .desc = "rx err", 1914 .handler = sci_er_interrupt, 1915 }, 1916 1917 [SCIx_RXI_IRQ] = { 1918 .desc = "rx full", 1919 .handler = sci_rx_interrupt, 1920 }, 1921 1922 [SCIx_TXI_IRQ] = { 1923 .desc = "tx empty", 1924 .handler = sci_tx_interrupt, 1925 }, 1926 1927 [SCIx_BRI_IRQ] = { 1928 .desc = "break", 1929 .handler = sci_br_interrupt, 1930 }, 1931 1932 [SCIx_DRI_IRQ] = { 1933 .desc = "rx ready", 1934 .handler = sci_rx_interrupt, 1935 }, 1936 1937 [SCIx_TEI_IRQ] = { 1938 .desc = "tx end", 1939 .handler = sci_tx_end_interrupt, 1940 }, 1941 1942 /* 1943 * Special muxed handler. 1944 */ 1945 [SCIx_MUX_IRQ] = { 1946 .desc = "mux", 1947 .handler = sci_mpxed_interrupt, 1948 }, 1949 }; 1950 1951 static int sci_request_irq(struct sci_port *port) 1952 { 1953 struct uart_port *up = &port->port; 1954 int i, j, w, ret = 0; 1955 1956 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) { 1957 const struct sci_irq_desc *desc; 1958 int irq; 1959 1960 /* Check if already registered (muxed) */ 1961 for (w = 0; w < i; w++) 1962 if (port->irqs[w] == port->irqs[i]) 1963 w = i + 1; 1964 if (w > i) 1965 continue; 1966 1967 if (SCIx_IRQ_IS_MUXED(port)) { 1968 i = SCIx_MUX_IRQ; 1969 irq = up->irq; 1970 } else { 1971 irq = port->irqs[i]; 1972 1973 /* 1974 * Certain port types won't support all of the 1975 * available interrupt sources. 1976 */ 1977 if (unlikely(irq < 0)) 1978 continue; 1979 } 1980 1981 desc = sci_irq_desc + i; 1982 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s", 1983 dev_name(up->dev), desc->desc); 1984 if (!port->irqstr[j]) { 1985 ret = -ENOMEM; 1986 goto out_nomem; 1987 } 1988 1989 ret = request_irq(irq, desc->handler, up->irqflags, 1990 port->irqstr[j], port); 1991 if (unlikely(ret)) { 1992 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc); 1993 goto out_noirq; 1994 } 1995 } 1996 1997 return 0; 1998 1999 out_noirq: 2000 while (--i >= 0) 2001 free_irq(port->irqs[i], port); 2002 2003 out_nomem: 2004 while (--j >= 0) 2005 kfree(port->irqstr[j]); 2006 2007 return ret; 2008 } 2009 2010 static void sci_free_irq(struct sci_port *port) 2011 { 2012 int i, j; 2013 2014 /* 2015 * Intentionally in reverse order so we iterate over the muxed 2016 * IRQ first. 2017 */ 2018 for (i = 0; i < SCIx_NR_IRQS; i++) { 2019 int irq = port->irqs[i]; 2020 2021 /* 2022 * Certain port types won't support all of the available 2023 * interrupt sources. 2024 */ 2025 if (unlikely(irq < 0)) 2026 continue; 2027 2028 /* Check if already freed (irq was muxed) */ 2029 for (j = 0; j < i; j++) 2030 if (port->irqs[j] == irq) 2031 j = i + 1; 2032 if (j > i) 2033 continue; 2034 2035 free_irq(port->irqs[i], port); 2036 kfree(port->irqstr[i]); 2037 2038 if (SCIx_IRQ_IS_MUXED(port)) { 2039 /* If there's only one IRQ, we're done. */ 2040 return; 2041 } 2042 } 2043 } 2044 2045 static unsigned int sci_tx_empty(struct uart_port *port) 2046 { 2047 unsigned short status = serial_port_in(port, SCxSR); 2048 unsigned short in_tx_fifo = sci_txfill(port); 2049 2050 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0; 2051 } 2052 2053 static void sci_set_rts(struct uart_port *port, bool state) 2054 { 2055 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 2056 u16 data = serial_port_in(port, SCPDR); 2057 2058 /* Active low */ 2059 if (state) 2060 data &= ~SCPDR_RTSD; 2061 else 2062 data |= SCPDR_RTSD; 2063 serial_port_out(port, SCPDR, data); 2064 2065 /* RTS# is output */ 2066 serial_port_out(port, SCPCR, 2067 serial_port_in(port, SCPCR) | SCPCR_RTSC); 2068 } else if (sci_getreg(port, SCSPTR)->size) { 2069 u16 ctrl = serial_port_in(port, SCSPTR); 2070 2071 /* Active low */ 2072 if (state) 2073 ctrl &= ~SCSPTR_RTSDT; 2074 else 2075 ctrl |= SCSPTR_RTSDT; 2076 serial_port_out(port, SCSPTR, ctrl); 2077 } 2078 } 2079 2080 static bool sci_get_cts(struct uart_port *port) 2081 { 2082 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 2083 /* Active low */ 2084 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD); 2085 } else if (sci_getreg(port, SCSPTR)->size) { 2086 /* Active low */ 2087 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT); 2088 } 2089 2090 return true; 2091 } 2092 2093 /* 2094 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally 2095 * CTS/RTS is supported in hardware by at least one port and controlled 2096 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently 2097 * handled via the ->init_pins() op, which is a bit of a one-way street, 2098 * lacking any ability to defer pin control -- this will later be 2099 * converted over to the GPIO framework). 2100 * 2101 * Other modes (such as loopback) are supported generically on certain 2102 * port types, but not others. For these it's sufficient to test for the 2103 * existence of the support register and simply ignore the port type. 2104 */ 2105 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) 2106 { 2107 struct sci_port *s = to_sci_port(port); 2108 2109 if (mctrl & TIOCM_LOOP) { 2110 const struct plat_sci_reg *reg; 2111 2112 /* 2113 * Standard loopback mode for SCFCR ports. 2114 */ 2115 reg = sci_getreg(port, SCFCR); 2116 if (reg->size) 2117 serial_port_out(port, SCFCR, 2118 serial_port_in(port, SCFCR) | 2119 SCFCR_LOOP); 2120 } 2121 2122 mctrl_gpio_set(s->gpios, mctrl); 2123 2124 if (!s->has_rtscts) 2125 return; 2126 2127 if (!(mctrl & TIOCM_RTS)) { 2128 /* Disable Auto RTS */ 2129 serial_port_out(port, SCFCR, 2130 serial_port_in(port, SCFCR) & ~SCFCR_MCE); 2131 2132 /* Clear RTS */ 2133 sci_set_rts(port, 0); 2134 } else if (s->autorts) { 2135 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 2136 /* Enable RTS# pin function */ 2137 serial_port_out(port, SCPCR, 2138 serial_port_in(port, SCPCR) & ~SCPCR_RTSC); 2139 } 2140 2141 /* Enable Auto RTS */ 2142 serial_port_out(port, SCFCR, 2143 serial_port_in(port, SCFCR) | SCFCR_MCE); 2144 } else { 2145 /* Set RTS */ 2146 sci_set_rts(port, 1); 2147 } 2148 } 2149 2150 static unsigned int sci_get_mctrl(struct uart_port *port) 2151 { 2152 struct sci_port *s = to_sci_port(port); 2153 struct mctrl_gpios *gpios = s->gpios; 2154 unsigned int mctrl = 0; 2155 2156 mctrl_gpio_get(gpios, &mctrl); 2157 2158 /* 2159 * CTS/RTS is handled in hardware when supported, while nothing 2160 * else is wired up. 2161 */ 2162 if (s->autorts) { 2163 if (sci_get_cts(port)) 2164 mctrl |= TIOCM_CTS; 2165 } else if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)) { 2166 mctrl |= TIOCM_CTS; 2167 } 2168 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)) 2169 mctrl |= TIOCM_DSR; 2170 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)) 2171 mctrl |= TIOCM_CAR; 2172 2173 return mctrl; 2174 } 2175 2176 static void sci_enable_ms(struct uart_port *port) 2177 { 2178 mctrl_gpio_enable_ms(to_sci_port(port)->gpios); 2179 } 2180 2181 static void sci_break_ctl(struct uart_port *port, int break_state) 2182 { 2183 unsigned short scscr, scsptr; 2184 unsigned long flags; 2185 2186 /* check whether the port has SCSPTR */ 2187 if (!sci_getreg(port, SCSPTR)->size) { 2188 /* 2189 * Not supported by hardware. Most parts couple break and rx 2190 * interrupts together, with break detection always enabled. 2191 */ 2192 return; 2193 } 2194 2195 spin_lock_irqsave(&port->lock, flags); 2196 scsptr = serial_port_in(port, SCSPTR); 2197 scscr = serial_port_in(port, SCSCR); 2198 2199 if (break_state == -1) { 2200 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT; 2201 scscr &= ~SCSCR_TE; 2202 } else { 2203 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO; 2204 scscr |= SCSCR_TE; 2205 } 2206 2207 serial_port_out(port, SCSPTR, scsptr); 2208 serial_port_out(port, SCSCR, scscr); 2209 spin_unlock_irqrestore(&port->lock, flags); 2210 } 2211 2212 static int sci_startup(struct uart_port *port) 2213 { 2214 struct sci_port *s = to_sci_port(port); 2215 int ret; 2216 2217 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 2218 2219 sci_request_dma(port); 2220 2221 ret = sci_request_irq(s); 2222 if (unlikely(ret < 0)) { 2223 sci_free_dma(port); 2224 return ret; 2225 } 2226 2227 return 0; 2228 } 2229 2230 static void sci_shutdown(struct uart_port *port) 2231 { 2232 struct sci_port *s = to_sci_port(port); 2233 unsigned long flags; 2234 u16 scr; 2235 2236 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 2237 2238 s->autorts = false; 2239 mctrl_gpio_disable_ms(to_sci_port(port)->gpios); 2240 2241 spin_lock_irqsave(&port->lock, flags); 2242 sci_stop_rx(port); 2243 sci_stop_tx(port); 2244 /* 2245 * Stop RX and TX, disable related interrupts, keep clock source 2246 * and HSCIF TOT bits 2247 */ 2248 scr = serial_port_in(port, SCSCR); 2249 serial_port_out(port, SCSCR, scr & 2250 (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot)); 2251 spin_unlock_irqrestore(&port->lock, flags); 2252 2253 #ifdef CONFIG_SERIAL_SH_SCI_DMA 2254 if (s->chan_rx_saved) { 2255 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__, 2256 port->line); 2257 hrtimer_cancel(&s->rx_timer); 2258 } 2259 #endif 2260 2261 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) 2262 del_timer_sync(&s->rx_fifo_timer); 2263 sci_free_irq(s); 2264 sci_free_dma(port); 2265 } 2266 2267 static int sci_sck_calc(struct sci_port *s, unsigned int bps, 2268 unsigned int *srr) 2269 { 2270 unsigned long freq = s->clk_rates[SCI_SCK]; 2271 int err, min_err = INT_MAX; 2272 unsigned int sr; 2273 2274 if (s->port.type != PORT_HSCIF) 2275 freq *= 2; 2276 2277 for_each_sr(sr, s) { 2278 err = DIV_ROUND_CLOSEST(freq, sr) - bps; 2279 if (abs(err) >= abs(min_err)) 2280 continue; 2281 2282 min_err = err; 2283 *srr = sr - 1; 2284 2285 if (!err) 2286 break; 2287 } 2288 2289 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err, 2290 *srr + 1); 2291 return min_err; 2292 } 2293 2294 static int sci_brg_calc(struct sci_port *s, unsigned int bps, 2295 unsigned long freq, unsigned int *dlr, 2296 unsigned int *srr) 2297 { 2298 int err, min_err = INT_MAX; 2299 unsigned int sr, dl; 2300 2301 if (s->port.type != PORT_HSCIF) 2302 freq *= 2; 2303 2304 for_each_sr(sr, s) { 2305 dl = DIV_ROUND_CLOSEST(freq, sr * bps); 2306 dl = clamp(dl, 1U, 65535U); 2307 2308 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps; 2309 if (abs(err) >= abs(min_err)) 2310 continue; 2311 2312 min_err = err; 2313 *dlr = dl; 2314 *srr = sr - 1; 2315 2316 if (!err) 2317 break; 2318 } 2319 2320 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps, 2321 min_err, *dlr, *srr + 1); 2322 return min_err; 2323 } 2324 2325 /* calculate sample rate, BRR, and clock select */ 2326 static int sci_scbrr_calc(struct sci_port *s, unsigned int bps, 2327 unsigned int *brr, unsigned int *srr, 2328 unsigned int *cks) 2329 { 2330 unsigned long freq = s->clk_rates[SCI_FCK]; 2331 unsigned int sr, br, prediv, scrate, c; 2332 int err, min_err = INT_MAX; 2333 2334 if (s->port.type != PORT_HSCIF) 2335 freq *= 2; 2336 2337 /* 2338 * Find the combination of sample rate and clock select with the 2339 * smallest deviation from the desired baud rate. 2340 * Prefer high sample rates to maximise the receive margin. 2341 * 2342 * M: Receive margin (%) 2343 * N: Ratio of bit rate to clock (N = sampling rate) 2344 * D: Clock duty (D = 0 to 1.0) 2345 * L: Frame length (L = 9 to 12) 2346 * F: Absolute value of clock frequency deviation 2347 * 2348 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) - 2349 * (|D - 0.5| / N * (1 + F))| 2350 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation. 2351 */ 2352 for_each_sr(sr, s) { 2353 for (c = 0; c <= 3; c++) { 2354 /* integerized formulas from HSCIF documentation */ 2355 prediv = sr << (2 * c + 1); 2356 2357 /* 2358 * We need to calculate: 2359 * 2360 * br = freq / (prediv * bps) clamped to [1..256] 2361 * err = freq / (br * prediv) - bps 2362 * 2363 * Watch out for overflow when calculating the desired 2364 * sampling clock rate! 2365 */ 2366 if (bps > UINT_MAX / prediv) 2367 break; 2368 2369 scrate = prediv * bps; 2370 br = DIV_ROUND_CLOSEST(freq, scrate); 2371 br = clamp(br, 1U, 256U); 2372 2373 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps; 2374 if (abs(err) >= abs(min_err)) 2375 continue; 2376 2377 min_err = err; 2378 *brr = br - 1; 2379 *srr = sr - 1; 2380 *cks = c; 2381 2382 if (!err) 2383 goto found; 2384 } 2385 } 2386 2387 found: 2388 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps, 2389 min_err, *brr, *srr + 1, *cks); 2390 return min_err; 2391 } 2392 2393 static void sci_reset(struct uart_port *port) 2394 { 2395 const struct plat_sci_reg *reg; 2396 unsigned int status; 2397 struct sci_port *s = to_sci_port(port); 2398 2399 serial_port_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */ 2400 2401 reg = sci_getreg(port, SCFCR); 2402 if (reg->size) 2403 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); 2404 2405 sci_clear_SCxSR(port, 2406 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) & 2407 SCxSR_BREAK_CLEAR(port)); 2408 if (sci_getreg(port, SCLSR)->size) { 2409 status = serial_port_in(port, SCLSR); 2410 status &= ~(SCLSR_TO | SCLSR_ORER); 2411 serial_port_out(port, SCLSR, status); 2412 } 2413 2414 if (s->rx_trigger > 1) { 2415 if (s->rx_fifo_timeout) { 2416 scif_set_rtrg(port, 1); 2417 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0); 2418 } else { 2419 if (port->type == PORT_SCIFA || 2420 port->type == PORT_SCIFB) 2421 scif_set_rtrg(port, 1); 2422 else 2423 scif_set_rtrg(port, s->rx_trigger); 2424 } 2425 } 2426 } 2427 2428 static void sci_set_termios(struct uart_port *port, struct ktermios *termios, 2429 const struct ktermios *old) 2430 { 2431 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits; 2432 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0; 2433 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0; 2434 struct sci_port *s = to_sci_port(port); 2435 const struct plat_sci_reg *reg; 2436 int min_err = INT_MAX, err; 2437 unsigned long max_freq = 0; 2438 int best_clk = -1; 2439 unsigned long flags; 2440 2441 if ((termios->c_cflag & CSIZE) == CS7) { 2442 smr_val |= SCSMR_CHR; 2443 } else { 2444 termios->c_cflag &= ~CSIZE; 2445 termios->c_cflag |= CS8; 2446 } 2447 if (termios->c_cflag & PARENB) 2448 smr_val |= SCSMR_PE; 2449 if (termios->c_cflag & PARODD) 2450 smr_val |= SCSMR_PE | SCSMR_ODD; 2451 if (termios->c_cflag & CSTOPB) 2452 smr_val |= SCSMR_STOP; 2453 2454 /* 2455 * earlyprintk comes here early on with port->uartclk set to zero. 2456 * the clock framework is not up and running at this point so here 2457 * we assume that 115200 is the maximum baud rate. please note that 2458 * the baud rate is not programmed during earlyprintk - it is assumed 2459 * that the previous boot loader has enabled required clocks and 2460 * setup the baud rate generator hardware for us already. 2461 */ 2462 if (!port->uartclk) { 2463 baud = uart_get_baud_rate(port, termios, old, 0, 115200); 2464 goto done; 2465 } 2466 2467 for (i = 0; i < SCI_NUM_CLKS; i++) 2468 max_freq = max(max_freq, s->clk_rates[i]); 2469 2470 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s)); 2471 if (!baud) 2472 goto done; 2473 2474 /* 2475 * There can be multiple sources for the sampling clock. Find the one 2476 * that gives us the smallest deviation from the desired baud rate. 2477 */ 2478 2479 /* Optional Undivided External Clock */ 2480 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA && 2481 port->type != PORT_SCIFB) { 2482 err = sci_sck_calc(s, baud, &srr1); 2483 if (abs(err) < abs(min_err)) { 2484 best_clk = SCI_SCK; 2485 scr_val = SCSCR_CKE1; 2486 sccks = SCCKS_CKS; 2487 min_err = err; 2488 srr = srr1; 2489 if (!err) 2490 goto done; 2491 } 2492 } 2493 2494 /* Optional BRG Frequency Divided External Clock */ 2495 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) { 2496 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1, 2497 &srr1); 2498 if (abs(err) < abs(min_err)) { 2499 best_clk = SCI_SCIF_CLK; 2500 scr_val = SCSCR_CKE1; 2501 sccks = 0; 2502 min_err = err; 2503 dl = dl1; 2504 srr = srr1; 2505 if (!err) 2506 goto done; 2507 } 2508 } 2509 2510 /* Optional BRG Frequency Divided Internal Clock */ 2511 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) { 2512 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1, 2513 &srr1); 2514 if (abs(err) < abs(min_err)) { 2515 best_clk = SCI_BRG_INT; 2516 scr_val = SCSCR_CKE1; 2517 sccks = SCCKS_XIN; 2518 min_err = err; 2519 dl = dl1; 2520 srr = srr1; 2521 if (!min_err) 2522 goto done; 2523 } 2524 } 2525 2526 /* Divided Functional Clock using standard Bit Rate Register */ 2527 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1); 2528 if (abs(err) < abs(min_err)) { 2529 best_clk = SCI_FCK; 2530 scr_val = 0; 2531 min_err = err; 2532 brr = brr1; 2533 srr = srr1; 2534 cks = cks1; 2535 } 2536 2537 done: 2538 if (best_clk >= 0) 2539 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n", 2540 s->clks[best_clk], baud, min_err); 2541 2542 sci_port_enable(s); 2543 2544 /* 2545 * Program the optional External Baud Rate Generator (BRG) first. 2546 * It controls the mux to select (H)SCK or frequency divided clock. 2547 */ 2548 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) { 2549 serial_port_out(port, SCDL, dl); 2550 serial_port_out(port, SCCKS, sccks); 2551 } 2552 2553 spin_lock_irqsave(&port->lock, flags); 2554 2555 sci_reset(port); 2556 2557 uart_update_timeout(port, termios->c_cflag, baud); 2558 2559 /* byte size and parity */ 2560 bits = tty_get_frame_size(termios->c_cflag); 2561 2562 if (sci_getreg(port, SEMR)->size) 2563 serial_port_out(port, SEMR, 0); 2564 2565 if (best_clk >= 0) { 2566 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 2567 switch (srr + 1) { 2568 case 5: smr_val |= SCSMR_SRC_5; break; 2569 case 7: smr_val |= SCSMR_SRC_7; break; 2570 case 11: smr_val |= SCSMR_SRC_11; break; 2571 case 13: smr_val |= SCSMR_SRC_13; break; 2572 case 16: smr_val |= SCSMR_SRC_16; break; 2573 case 17: smr_val |= SCSMR_SRC_17; break; 2574 case 19: smr_val |= SCSMR_SRC_19; break; 2575 case 27: smr_val |= SCSMR_SRC_27; break; 2576 } 2577 smr_val |= cks; 2578 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); 2579 serial_port_out(port, SCSMR, smr_val); 2580 serial_port_out(port, SCBRR, brr); 2581 if (sci_getreg(port, HSSRR)->size) { 2582 unsigned int hssrr = srr | HSCIF_SRE; 2583 /* Calculate deviation from intended rate at the 2584 * center of the last stop bit in sampling clocks. 2585 */ 2586 int last_stop = bits * 2 - 1; 2587 int deviation = DIV_ROUND_CLOSEST(min_err * last_stop * 2588 (int)(srr + 1), 2589 2 * (int)baud); 2590 2591 if (abs(deviation) >= 2) { 2592 /* At least two sampling clocks off at the 2593 * last stop bit; we can increase the error 2594 * margin by shifting the sampling point. 2595 */ 2596 int shift = clamp(deviation / 2, -8, 7); 2597 2598 hssrr |= (shift << HSCIF_SRHP_SHIFT) & 2599 HSCIF_SRHP_MASK; 2600 hssrr |= HSCIF_SRDE; 2601 } 2602 serial_port_out(port, HSSRR, hssrr); 2603 } 2604 2605 /* Wait one bit interval */ 2606 udelay((1000000 + (baud - 1)) / baud); 2607 } else { 2608 /* Don't touch the bit rate configuration */ 2609 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0); 2610 smr_val |= serial_port_in(port, SCSMR) & 2611 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS); 2612 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); 2613 serial_port_out(port, SCSMR, smr_val); 2614 } 2615 2616 sci_init_pins(port, termios->c_cflag); 2617 2618 port->status &= ~UPSTAT_AUTOCTS; 2619 s->autorts = false; 2620 reg = sci_getreg(port, SCFCR); 2621 if (reg->size) { 2622 unsigned short ctrl = serial_port_in(port, SCFCR); 2623 2624 if ((port->flags & UPF_HARD_FLOW) && 2625 (termios->c_cflag & CRTSCTS)) { 2626 /* There is no CTS interrupt to restart the hardware */ 2627 port->status |= UPSTAT_AUTOCTS; 2628 /* MCE is enabled when RTS is raised */ 2629 s->autorts = true; 2630 } 2631 2632 /* 2633 * As we've done a sci_reset() above, ensure we don't 2634 * interfere with the FIFOs while toggling MCE. As the 2635 * reset values could still be set, simply mask them out. 2636 */ 2637 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST); 2638 2639 serial_port_out(port, SCFCR, ctrl); 2640 } 2641 if (port->flags & UPF_HARD_FLOW) { 2642 /* Refresh (Auto) RTS */ 2643 sci_set_mctrl(port, port->mctrl); 2644 } 2645 2646 /* 2647 * For SCI, TE (transmit enable) must be set after setting TIE 2648 * (transmit interrupt enable) or in the same instruction to 2649 * start the transmitting process. So skip setting TE here for SCI. 2650 */ 2651 if (port->type != PORT_SCI) 2652 scr_val |= SCSCR_TE; 2653 scr_val |= SCSCR_RE | (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)); 2654 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); 2655 if ((srr + 1 == 5) && 2656 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) { 2657 /* 2658 * In asynchronous mode, when the sampling rate is 1/5, first 2659 * received data may become invalid on some SCIFA and SCIFB. 2660 * To avoid this problem wait more than 1 serial data time (1 2661 * bit time x serial data number) after setting SCSCR.RE = 1. 2662 */ 2663 udelay(DIV_ROUND_UP(10 * 1000000, baud)); 2664 } 2665 2666 /* Calculate delay for 2 DMA buffers (4 FIFO). */ 2667 s->rx_frame = (10000 * bits) / (baud / 100); 2668 #ifdef CONFIG_SERIAL_SH_SCI_DMA 2669 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame; 2670 #endif 2671 2672 if ((termios->c_cflag & CREAD) != 0) 2673 sci_start_rx(port); 2674 2675 spin_unlock_irqrestore(&port->lock, flags); 2676 2677 sci_port_disable(s); 2678 2679 if (UART_ENABLE_MS(port, termios->c_cflag)) 2680 sci_enable_ms(port); 2681 } 2682 2683 static void sci_pm(struct uart_port *port, unsigned int state, 2684 unsigned int oldstate) 2685 { 2686 struct sci_port *sci_port = to_sci_port(port); 2687 2688 switch (state) { 2689 case UART_PM_STATE_OFF: 2690 sci_port_disable(sci_port); 2691 break; 2692 default: 2693 sci_port_enable(sci_port); 2694 break; 2695 } 2696 } 2697 2698 static const char *sci_type(struct uart_port *port) 2699 { 2700 switch (port->type) { 2701 case PORT_IRDA: 2702 return "irda"; 2703 case PORT_SCI: 2704 return "sci"; 2705 case PORT_SCIF: 2706 return "scif"; 2707 case PORT_SCIFA: 2708 return "scifa"; 2709 case PORT_SCIFB: 2710 return "scifb"; 2711 case PORT_HSCIF: 2712 return "hscif"; 2713 } 2714 2715 return NULL; 2716 } 2717 2718 static int sci_remap_port(struct uart_port *port) 2719 { 2720 struct sci_port *sport = to_sci_port(port); 2721 2722 /* 2723 * Nothing to do if there's already an established membase. 2724 */ 2725 if (port->membase) 2726 return 0; 2727 2728 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { 2729 port->membase = ioremap(port->mapbase, sport->reg_size); 2730 if (unlikely(!port->membase)) { 2731 dev_err(port->dev, "can't remap port#%d\n", port->line); 2732 return -ENXIO; 2733 } 2734 } else { 2735 /* 2736 * For the simple (and majority of) cases where we don't 2737 * need to do any remapping, just cast the cookie 2738 * directly. 2739 */ 2740 port->membase = (void __iomem *)(uintptr_t)port->mapbase; 2741 } 2742 2743 return 0; 2744 } 2745 2746 static void sci_release_port(struct uart_port *port) 2747 { 2748 struct sci_port *sport = to_sci_port(port); 2749 2750 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { 2751 iounmap(port->membase); 2752 port->membase = NULL; 2753 } 2754 2755 release_mem_region(port->mapbase, sport->reg_size); 2756 } 2757 2758 static int sci_request_port(struct uart_port *port) 2759 { 2760 struct resource *res; 2761 struct sci_port *sport = to_sci_port(port); 2762 int ret; 2763 2764 res = request_mem_region(port->mapbase, sport->reg_size, 2765 dev_name(port->dev)); 2766 if (unlikely(res == NULL)) { 2767 dev_err(port->dev, "request_mem_region failed."); 2768 return -EBUSY; 2769 } 2770 2771 ret = sci_remap_port(port); 2772 if (unlikely(ret != 0)) { 2773 release_resource(res); 2774 return ret; 2775 } 2776 2777 return 0; 2778 } 2779 2780 static void sci_config_port(struct uart_port *port, int flags) 2781 { 2782 if (flags & UART_CONFIG_TYPE) { 2783 struct sci_port *sport = to_sci_port(port); 2784 2785 port->type = sport->cfg->type; 2786 sci_request_port(port); 2787 } 2788 } 2789 2790 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser) 2791 { 2792 if (ser->baud_base < 2400) 2793 /* No paper tape reader for Mitch.. */ 2794 return -EINVAL; 2795 2796 return 0; 2797 } 2798 2799 static const struct uart_ops sci_uart_ops = { 2800 .tx_empty = sci_tx_empty, 2801 .set_mctrl = sci_set_mctrl, 2802 .get_mctrl = sci_get_mctrl, 2803 .start_tx = sci_start_tx, 2804 .stop_tx = sci_stop_tx, 2805 .stop_rx = sci_stop_rx, 2806 .enable_ms = sci_enable_ms, 2807 .break_ctl = sci_break_ctl, 2808 .startup = sci_startup, 2809 .shutdown = sci_shutdown, 2810 .flush_buffer = sci_flush_buffer, 2811 .set_termios = sci_set_termios, 2812 .pm = sci_pm, 2813 .type = sci_type, 2814 .release_port = sci_release_port, 2815 .request_port = sci_request_port, 2816 .config_port = sci_config_port, 2817 .verify_port = sci_verify_port, 2818 #ifdef CONFIG_CONSOLE_POLL 2819 .poll_get_char = sci_poll_get_char, 2820 .poll_put_char = sci_poll_put_char, 2821 #endif 2822 }; 2823 2824 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev) 2825 { 2826 const char *clk_names[] = { 2827 [SCI_FCK] = "fck", 2828 [SCI_SCK] = "sck", 2829 [SCI_BRG_INT] = "brg_int", 2830 [SCI_SCIF_CLK] = "scif_clk", 2831 }; 2832 struct clk *clk; 2833 unsigned int i; 2834 2835 if (sci_port->cfg->type == PORT_HSCIF) 2836 clk_names[SCI_SCK] = "hsck"; 2837 2838 for (i = 0; i < SCI_NUM_CLKS; i++) { 2839 clk = devm_clk_get_optional(dev, clk_names[i]); 2840 if (IS_ERR(clk)) 2841 return PTR_ERR(clk); 2842 2843 if (!clk && i == SCI_FCK) { 2844 /* 2845 * Not all SH platforms declare a clock lookup entry 2846 * for SCI devices, in which case we need to get the 2847 * global "peripheral_clk" clock. 2848 */ 2849 clk = devm_clk_get(dev, "peripheral_clk"); 2850 if (IS_ERR(clk)) 2851 return dev_err_probe(dev, PTR_ERR(clk), 2852 "failed to get %s\n", 2853 clk_names[i]); 2854 } 2855 2856 if (!clk) 2857 dev_dbg(dev, "failed to get %s\n", clk_names[i]); 2858 else 2859 dev_dbg(dev, "clk %s is %pC rate %lu\n", clk_names[i], 2860 clk, clk_get_rate(clk)); 2861 sci_port->clks[i] = clk; 2862 } 2863 return 0; 2864 } 2865 2866 static const struct sci_port_params * 2867 sci_probe_regmap(const struct plat_sci_port *cfg) 2868 { 2869 unsigned int regtype; 2870 2871 if (cfg->regtype != SCIx_PROBE_REGTYPE) 2872 return &sci_port_params[cfg->regtype]; 2873 2874 switch (cfg->type) { 2875 case PORT_SCI: 2876 regtype = SCIx_SCI_REGTYPE; 2877 break; 2878 case PORT_IRDA: 2879 regtype = SCIx_IRDA_REGTYPE; 2880 break; 2881 case PORT_SCIFA: 2882 regtype = SCIx_SCIFA_REGTYPE; 2883 break; 2884 case PORT_SCIFB: 2885 regtype = SCIx_SCIFB_REGTYPE; 2886 break; 2887 case PORT_SCIF: 2888 /* 2889 * The SH-4 is a bit of a misnomer here, although that's 2890 * where this particular port layout originated. This 2891 * configuration (or some slight variation thereof) 2892 * remains the dominant model for all SCIFs. 2893 */ 2894 regtype = SCIx_SH4_SCIF_REGTYPE; 2895 break; 2896 case PORT_HSCIF: 2897 regtype = SCIx_HSCIF_REGTYPE; 2898 break; 2899 default: 2900 pr_err("Can't probe register map for given port\n"); 2901 return NULL; 2902 } 2903 2904 return &sci_port_params[regtype]; 2905 } 2906 2907 static int sci_init_single(struct platform_device *dev, 2908 struct sci_port *sci_port, unsigned int index, 2909 const struct plat_sci_port *p, bool early) 2910 { 2911 struct uart_port *port = &sci_port->port; 2912 const struct resource *res; 2913 unsigned int i; 2914 int ret; 2915 2916 sci_port->cfg = p; 2917 2918 port->ops = &sci_uart_ops; 2919 port->iotype = UPIO_MEM; 2920 port->line = index; 2921 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SH_SCI_CONSOLE); 2922 2923 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 2924 if (res == NULL) 2925 return -ENOMEM; 2926 2927 port->mapbase = res->start; 2928 sci_port->reg_size = resource_size(res); 2929 2930 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) { 2931 if (i) 2932 sci_port->irqs[i] = platform_get_irq_optional(dev, i); 2933 else 2934 sci_port->irqs[i] = platform_get_irq(dev, i); 2935 } 2936 2937 /* 2938 * The fourth interrupt on SCI port is transmit end interrupt, so 2939 * shuffle the interrupts. 2940 */ 2941 if (p->type == PORT_SCI) 2942 swap(sci_port->irqs[SCIx_BRI_IRQ], sci_port->irqs[SCIx_TEI_IRQ]); 2943 2944 /* The SCI generates several interrupts. They can be muxed together or 2945 * connected to different interrupt lines. In the muxed case only one 2946 * interrupt resource is specified as there is only one interrupt ID. 2947 * In the non-muxed case, up to 6 interrupt signals might be generated 2948 * from the SCI, however those signals might have their own individual 2949 * interrupt ID numbers, or muxed together with another interrupt. 2950 */ 2951 if (sci_port->irqs[0] < 0) 2952 return -ENXIO; 2953 2954 if (sci_port->irqs[1] < 0) 2955 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++) 2956 sci_port->irqs[i] = sci_port->irqs[0]; 2957 2958 sci_port->params = sci_probe_regmap(p); 2959 if (unlikely(sci_port->params == NULL)) 2960 return -EINVAL; 2961 2962 switch (p->type) { 2963 case PORT_SCIFB: 2964 sci_port->rx_trigger = 48; 2965 break; 2966 case PORT_HSCIF: 2967 sci_port->rx_trigger = 64; 2968 break; 2969 case PORT_SCIFA: 2970 sci_port->rx_trigger = 32; 2971 break; 2972 case PORT_SCIF: 2973 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) 2974 /* RX triggering not implemented for this IP */ 2975 sci_port->rx_trigger = 1; 2976 else 2977 sci_port->rx_trigger = 8; 2978 break; 2979 default: 2980 sci_port->rx_trigger = 1; 2981 break; 2982 } 2983 2984 sci_port->rx_fifo_timeout = 0; 2985 sci_port->hscif_tot = 0; 2986 2987 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't 2988 * match the SoC datasheet, this should be investigated. Let platform 2989 * data override the sampling rate for now. 2990 */ 2991 sci_port->sampling_rate_mask = p->sampling_rate 2992 ? SCI_SR(p->sampling_rate) 2993 : sci_port->params->sampling_rate_mask; 2994 2995 if (!early) { 2996 ret = sci_init_clocks(sci_port, &dev->dev); 2997 if (ret < 0) 2998 return ret; 2999 3000 port->dev = &dev->dev; 3001 3002 pm_runtime_enable(&dev->dev); 3003 } 3004 3005 port->type = p->type; 3006 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags; 3007 port->fifosize = sci_port->params->fifosize; 3008 3009 if (port->type == PORT_SCI && !dev->dev.of_node) { 3010 if (sci_port->reg_size >= 0x20) 3011 port->regshift = 2; 3012 else 3013 port->regshift = 1; 3014 } 3015 3016 /* 3017 * The UART port needs an IRQ value, so we peg this to the RX IRQ 3018 * for the multi-IRQ ports, which is where we are primarily 3019 * concerned with the shutdown path synchronization. 3020 * 3021 * For the muxed case there's nothing more to do. 3022 */ 3023 port->irq = sci_port->irqs[SCIx_RXI_IRQ]; 3024 port->irqflags = 0; 3025 3026 port->serial_in = sci_serial_in; 3027 port->serial_out = sci_serial_out; 3028 3029 return 0; 3030 } 3031 3032 static void sci_cleanup_single(struct sci_port *port) 3033 { 3034 pm_runtime_disable(port->port.dev); 3035 } 3036 3037 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ 3038 defined(CONFIG_SERIAL_SH_SCI_EARLYCON) 3039 static void serial_console_putchar(struct uart_port *port, unsigned char ch) 3040 { 3041 sci_poll_put_char(port, ch); 3042 } 3043 3044 /* 3045 * Print a string to the serial port trying not to disturb 3046 * any possible real use of the port... 3047 */ 3048 static void serial_console_write(struct console *co, const char *s, 3049 unsigned count) 3050 { 3051 struct sci_port *sci_port = &sci_ports[co->index]; 3052 struct uart_port *port = &sci_port->port; 3053 unsigned short bits, ctrl, ctrl_temp; 3054 unsigned long flags; 3055 int locked = 1; 3056 3057 if (port->sysrq) 3058 locked = 0; 3059 else if (oops_in_progress) 3060 locked = spin_trylock_irqsave(&port->lock, flags); 3061 else 3062 spin_lock_irqsave(&port->lock, flags); 3063 3064 /* first save SCSCR then disable interrupts, keep clock source */ 3065 ctrl = serial_port_in(port, SCSCR); 3066 ctrl_temp = SCSCR_RE | SCSCR_TE | 3067 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) | 3068 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0)); 3069 serial_port_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot); 3070 3071 uart_console_write(port, s, count, serial_console_putchar); 3072 3073 /* wait until fifo is empty and last bit has been transmitted */ 3074 bits = SCxSR_TDxE(port) | SCxSR_TEND(port); 3075 while ((serial_port_in(port, SCxSR) & bits) != bits) 3076 cpu_relax(); 3077 3078 /* restore the SCSCR */ 3079 serial_port_out(port, SCSCR, ctrl); 3080 3081 if (locked) 3082 spin_unlock_irqrestore(&port->lock, flags); 3083 } 3084 3085 static int serial_console_setup(struct console *co, char *options) 3086 { 3087 struct sci_port *sci_port; 3088 struct uart_port *port; 3089 int baud = 115200; 3090 int bits = 8; 3091 int parity = 'n'; 3092 int flow = 'n'; 3093 int ret; 3094 3095 /* 3096 * Refuse to handle any bogus ports. 3097 */ 3098 if (co->index < 0 || co->index >= SCI_NPORTS) 3099 return -ENODEV; 3100 3101 sci_port = &sci_ports[co->index]; 3102 port = &sci_port->port; 3103 3104 /* 3105 * Refuse to handle uninitialized ports. 3106 */ 3107 if (!port->ops) 3108 return -ENODEV; 3109 3110 ret = sci_remap_port(port); 3111 if (unlikely(ret != 0)) 3112 return ret; 3113 3114 if (options) 3115 uart_parse_options(options, &baud, &parity, &bits, &flow); 3116 3117 return uart_set_options(port, co, baud, parity, bits, flow); 3118 } 3119 3120 static struct console serial_console = { 3121 .name = "ttySC", 3122 .device = uart_console_device, 3123 .write = serial_console_write, 3124 .setup = serial_console_setup, 3125 .flags = CON_PRINTBUFFER, 3126 .index = -1, 3127 .data = &sci_uart_driver, 3128 }; 3129 3130 #ifdef CONFIG_SUPERH 3131 static char early_serial_buf[32]; 3132 3133 static int early_serial_console_setup(struct console *co, char *options) 3134 { 3135 /* 3136 * This early console is always registered using the earlyprintk= 3137 * parameter, which does not call add_preferred_console(). Thus 3138 * @options is always NULL and the options for this early console 3139 * are passed using a custom buffer. 3140 */ 3141 WARN_ON(options); 3142 3143 return serial_console_setup(co, early_serial_buf); 3144 } 3145 3146 static struct console early_serial_console = { 3147 .name = "early_ttySC", 3148 .write = serial_console_write, 3149 .setup = early_serial_console_setup, 3150 .flags = CON_PRINTBUFFER, 3151 .index = -1, 3152 }; 3153 3154 static int sci_probe_earlyprintk(struct platform_device *pdev) 3155 { 3156 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev); 3157 3158 if (early_serial_console.data) 3159 return -EEXIST; 3160 3161 early_serial_console.index = pdev->id; 3162 3163 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true); 3164 3165 if (!strstr(early_serial_buf, "keep")) 3166 early_serial_console.flags |= CON_BOOT; 3167 3168 register_console(&early_serial_console); 3169 return 0; 3170 } 3171 #endif 3172 3173 #define SCI_CONSOLE (&serial_console) 3174 3175 #else 3176 static inline int sci_probe_earlyprintk(struct platform_device *pdev) 3177 { 3178 return -EINVAL; 3179 } 3180 3181 #define SCI_CONSOLE NULL 3182 3183 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */ 3184 3185 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized"; 3186 3187 static DEFINE_MUTEX(sci_uart_registration_lock); 3188 static struct uart_driver sci_uart_driver = { 3189 .owner = THIS_MODULE, 3190 .driver_name = "sci", 3191 .dev_name = "ttySC", 3192 .major = SCI_MAJOR, 3193 .minor = SCI_MINOR_START, 3194 .nr = SCI_NPORTS, 3195 .cons = SCI_CONSOLE, 3196 }; 3197 3198 static int sci_remove(struct platform_device *dev) 3199 { 3200 struct sci_port *port = platform_get_drvdata(dev); 3201 unsigned int type = port->port.type; /* uart_remove_... clears it */ 3202 3203 sci_ports_in_use &= ~BIT(port->port.line); 3204 uart_remove_one_port(&sci_uart_driver, &port->port); 3205 3206 sci_cleanup_single(port); 3207 3208 if (port->port.fifosize > 1) 3209 device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger); 3210 if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF) 3211 device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout); 3212 3213 return 0; 3214 } 3215 3216 3217 #define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype)) 3218 #define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16) 3219 #define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff) 3220 3221 static const struct of_device_id of_sci_match[] __maybe_unused = { 3222 /* SoC-specific types */ 3223 { 3224 .compatible = "renesas,scif-r7s72100", 3225 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE), 3226 }, 3227 { 3228 .compatible = "renesas,scif-r7s9210", 3229 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE), 3230 }, 3231 { 3232 .compatible = "renesas,scif-r9a07g044", 3233 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE), 3234 }, 3235 /* Family-specific types */ 3236 { 3237 .compatible = "renesas,rcar-gen1-scif", 3238 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3239 }, { 3240 .compatible = "renesas,rcar-gen2-scif", 3241 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3242 }, { 3243 .compatible = "renesas,rcar-gen3-scif", 3244 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3245 }, { 3246 .compatible = "renesas,rcar-gen4-scif", 3247 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3248 }, 3249 /* Generic types */ 3250 { 3251 .compatible = "renesas,scif", 3252 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE), 3253 }, { 3254 .compatible = "renesas,scifa", 3255 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE), 3256 }, { 3257 .compatible = "renesas,scifb", 3258 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE), 3259 }, { 3260 .compatible = "renesas,hscif", 3261 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE), 3262 }, { 3263 .compatible = "renesas,sci", 3264 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE), 3265 }, { 3266 /* Terminator */ 3267 }, 3268 }; 3269 MODULE_DEVICE_TABLE(of, of_sci_match); 3270 3271 static void sci_reset_control_assert(void *data) 3272 { 3273 reset_control_assert(data); 3274 } 3275 3276 static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev, 3277 unsigned int *dev_id) 3278 { 3279 struct device_node *np = pdev->dev.of_node; 3280 struct reset_control *rstc; 3281 struct plat_sci_port *p; 3282 struct sci_port *sp; 3283 const void *data; 3284 int id, ret; 3285 3286 if (!IS_ENABLED(CONFIG_OF) || !np) 3287 return ERR_PTR(-EINVAL); 3288 3289 data = of_device_get_match_data(&pdev->dev); 3290 3291 rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); 3292 if (IS_ERR(rstc)) 3293 return ERR_PTR(dev_err_probe(&pdev->dev, PTR_ERR(rstc), 3294 "failed to get reset ctrl\n")); 3295 3296 ret = reset_control_deassert(rstc); 3297 if (ret) { 3298 dev_err(&pdev->dev, "failed to deassert reset %d\n", ret); 3299 return ERR_PTR(ret); 3300 } 3301 3302 ret = devm_add_action_or_reset(&pdev->dev, sci_reset_control_assert, rstc); 3303 if (ret) { 3304 dev_err(&pdev->dev, "failed to register assert devm action, %d\n", 3305 ret); 3306 return ERR_PTR(ret); 3307 } 3308 3309 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL); 3310 if (!p) 3311 return ERR_PTR(-ENOMEM); 3312 3313 /* Get the line number from the aliases node. */ 3314 id = of_alias_get_id(np, "serial"); 3315 if (id < 0 && ~sci_ports_in_use) 3316 id = ffz(sci_ports_in_use); 3317 if (id < 0) { 3318 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id); 3319 return ERR_PTR(-EINVAL); 3320 } 3321 if (id >= ARRAY_SIZE(sci_ports)) { 3322 dev_err(&pdev->dev, "serial%d out of range\n", id); 3323 return ERR_PTR(-EINVAL); 3324 } 3325 3326 sp = &sci_ports[id]; 3327 *dev_id = id; 3328 3329 p->type = SCI_OF_TYPE(data); 3330 p->regtype = SCI_OF_REGTYPE(data); 3331 3332 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts"); 3333 3334 return p; 3335 } 3336 3337 static int sci_probe_single(struct platform_device *dev, 3338 unsigned int index, 3339 struct plat_sci_port *p, 3340 struct sci_port *sciport) 3341 { 3342 int ret; 3343 3344 /* Sanity check */ 3345 if (unlikely(index >= SCI_NPORTS)) { 3346 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n", 3347 index+1, SCI_NPORTS); 3348 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n"); 3349 return -EINVAL; 3350 } 3351 BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8); 3352 if (sci_ports_in_use & BIT(index)) 3353 return -EBUSY; 3354 3355 mutex_lock(&sci_uart_registration_lock); 3356 if (!sci_uart_driver.state) { 3357 ret = uart_register_driver(&sci_uart_driver); 3358 if (ret) { 3359 mutex_unlock(&sci_uart_registration_lock); 3360 return ret; 3361 } 3362 } 3363 mutex_unlock(&sci_uart_registration_lock); 3364 3365 ret = sci_init_single(dev, sciport, index, p, false); 3366 if (ret) 3367 return ret; 3368 3369 sciport->gpios = mctrl_gpio_init(&sciport->port, 0); 3370 if (IS_ERR(sciport->gpios)) 3371 return PTR_ERR(sciport->gpios); 3372 3373 if (sciport->has_rtscts) { 3374 if (mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_CTS) || 3375 mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_RTS)) { 3376 dev_err(&dev->dev, "Conflicting RTS/CTS config\n"); 3377 return -EINVAL; 3378 } 3379 sciport->port.flags |= UPF_HARD_FLOW; 3380 } 3381 3382 ret = uart_add_one_port(&sci_uart_driver, &sciport->port); 3383 if (ret) { 3384 sci_cleanup_single(sciport); 3385 return ret; 3386 } 3387 3388 return 0; 3389 } 3390 3391 static int sci_probe(struct platform_device *dev) 3392 { 3393 struct plat_sci_port *p; 3394 struct sci_port *sp; 3395 unsigned int dev_id; 3396 int ret; 3397 3398 /* 3399 * If we've come here via earlyprintk initialization, head off to 3400 * the special early probe. We don't have sufficient device state 3401 * to make it beyond this yet. 3402 */ 3403 #ifdef CONFIG_SUPERH 3404 if (is_sh_early_platform_device(dev)) 3405 return sci_probe_earlyprintk(dev); 3406 #endif 3407 3408 if (dev->dev.of_node) { 3409 p = sci_parse_dt(dev, &dev_id); 3410 if (IS_ERR(p)) 3411 return PTR_ERR(p); 3412 } else { 3413 p = dev->dev.platform_data; 3414 if (p == NULL) { 3415 dev_err(&dev->dev, "no platform data supplied\n"); 3416 return -EINVAL; 3417 } 3418 3419 dev_id = dev->id; 3420 } 3421 3422 sp = &sci_ports[dev_id]; 3423 platform_set_drvdata(dev, sp); 3424 3425 ret = sci_probe_single(dev, dev_id, p, sp); 3426 if (ret) 3427 return ret; 3428 3429 if (sp->port.fifosize > 1) { 3430 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_trigger); 3431 if (ret) 3432 return ret; 3433 } 3434 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB || 3435 sp->port.type == PORT_HSCIF) { 3436 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout); 3437 if (ret) { 3438 if (sp->port.fifosize > 1) { 3439 device_remove_file(&dev->dev, 3440 &dev_attr_rx_fifo_trigger); 3441 } 3442 return ret; 3443 } 3444 } 3445 3446 #ifdef CONFIG_SH_STANDARD_BIOS 3447 sh_bios_gdb_detach(); 3448 #endif 3449 3450 sci_ports_in_use |= BIT(dev_id); 3451 return 0; 3452 } 3453 3454 static __maybe_unused int sci_suspend(struct device *dev) 3455 { 3456 struct sci_port *sport = dev_get_drvdata(dev); 3457 3458 if (sport) 3459 uart_suspend_port(&sci_uart_driver, &sport->port); 3460 3461 return 0; 3462 } 3463 3464 static __maybe_unused int sci_resume(struct device *dev) 3465 { 3466 struct sci_port *sport = dev_get_drvdata(dev); 3467 3468 if (sport) 3469 uart_resume_port(&sci_uart_driver, &sport->port); 3470 3471 return 0; 3472 } 3473 3474 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume); 3475 3476 static struct platform_driver sci_driver = { 3477 .probe = sci_probe, 3478 .remove = sci_remove, 3479 .driver = { 3480 .name = "sh-sci", 3481 .pm = &sci_dev_pm_ops, 3482 .of_match_table = of_match_ptr(of_sci_match), 3483 }, 3484 }; 3485 3486 static int __init sci_init(void) 3487 { 3488 pr_info("%s\n", banner); 3489 3490 return platform_driver_register(&sci_driver); 3491 } 3492 3493 static void __exit sci_exit(void) 3494 { 3495 platform_driver_unregister(&sci_driver); 3496 3497 if (sci_uart_driver.state) 3498 uart_unregister_driver(&sci_uart_driver); 3499 } 3500 3501 #if defined(CONFIG_SUPERH) && defined(CONFIG_SERIAL_SH_SCI_CONSOLE) 3502 sh_early_platform_init_buffer("earlyprintk", &sci_driver, 3503 early_serial_buf, ARRAY_SIZE(early_serial_buf)); 3504 #endif 3505 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON 3506 static struct plat_sci_port port_cfg __initdata; 3507 3508 static int __init early_console_setup(struct earlycon_device *device, 3509 int type) 3510 { 3511 if (!device->port.membase) 3512 return -ENODEV; 3513 3514 device->port.serial_in = sci_serial_in; 3515 device->port.serial_out = sci_serial_out; 3516 device->port.type = type; 3517 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port)); 3518 port_cfg.type = type; 3519 sci_ports[0].cfg = &port_cfg; 3520 sci_ports[0].params = sci_probe_regmap(&port_cfg); 3521 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR); 3522 sci_serial_out(&sci_ports[0].port, SCSCR, 3523 SCSCR_RE | SCSCR_TE | port_cfg.scscr); 3524 3525 device->con->write = serial_console_write; 3526 return 0; 3527 } 3528 static int __init sci_early_console_setup(struct earlycon_device *device, 3529 const char *opt) 3530 { 3531 return early_console_setup(device, PORT_SCI); 3532 } 3533 static int __init scif_early_console_setup(struct earlycon_device *device, 3534 const char *opt) 3535 { 3536 return early_console_setup(device, PORT_SCIF); 3537 } 3538 static int __init rzscifa_early_console_setup(struct earlycon_device *device, 3539 const char *opt) 3540 { 3541 port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE; 3542 return early_console_setup(device, PORT_SCIF); 3543 } 3544 3545 static int __init scifa_early_console_setup(struct earlycon_device *device, 3546 const char *opt) 3547 { 3548 return early_console_setup(device, PORT_SCIFA); 3549 } 3550 static int __init scifb_early_console_setup(struct earlycon_device *device, 3551 const char *opt) 3552 { 3553 return early_console_setup(device, PORT_SCIFB); 3554 } 3555 static int __init hscif_early_console_setup(struct earlycon_device *device, 3556 const char *opt) 3557 { 3558 return early_console_setup(device, PORT_HSCIF); 3559 } 3560 3561 OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup); 3562 OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup); 3563 OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup); 3564 OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a07g044", rzscifa_early_console_setup); 3565 OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup); 3566 OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup); 3567 OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup); 3568 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */ 3569 3570 module_init(sci_init); 3571 module_exit(sci_exit); 3572 3573 MODULE_LICENSE("GPL"); 3574 MODULE_ALIAS("platform:sh-sci"); 3575 MODULE_AUTHOR("Paul Mundt"); 3576 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver"); 3577