1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) 4 * 5 * Copyright (C) 2002 - 2011 Paul Mundt 6 * Copyright (C) 2015 Glider bvba 7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007). 8 * 9 * based off of the old drivers/char/sh-sci.c by: 10 * 11 * Copyright (C) 1999, 2000 Niibe Yutaka 12 * Copyright (C) 2000 Sugioka Toshinobu 13 * Modified to support multiple serial ports. Stuart Menefy (May 2000). 14 * Modified to support SecureEdge. David McCullough (2002) 15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003). 16 * Removed SH7300 support (Jul 2007). 17 */ 18 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 19 #define SUPPORT_SYSRQ 20 #endif 21 22 #undef DEBUG 23 24 #include <linux/clk.h> 25 #include <linux/console.h> 26 #include <linux/ctype.h> 27 #include <linux/cpufreq.h> 28 #include <linux/delay.h> 29 #include <linux/dmaengine.h> 30 #include <linux/dma-mapping.h> 31 #include <linux/err.h> 32 #include <linux/errno.h> 33 #include <linux/init.h> 34 #include <linux/interrupt.h> 35 #include <linux/ioport.h> 36 #include <linux/ktime.h> 37 #include <linux/major.h> 38 #include <linux/module.h> 39 #include <linux/mm.h> 40 #include <linux/of.h> 41 #include <linux/of_device.h> 42 #include <linux/platform_device.h> 43 #include <linux/pm_runtime.h> 44 #include <linux/scatterlist.h> 45 #include <linux/serial.h> 46 #include <linux/serial_sci.h> 47 #include <linux/sh_dma.h> 48 #include <linux/slab.h> 49 #include <linux/string.h> 50 #include <linux/sysrq.h> 51 #include <linux/timer.h> 52 #include <linux/tty.h> 53 #include <linux/tty_flip.h> 54 55 #ifdef CONFIG_SUPERH 56 #include <asm/sh_bios.h> 57 #endif 58 59 #include "serial_mctrl_gpio.h" 60 #include "sh-sci.h" 61 62 /* Offsets into the sci_port->irqs array */ 63 enum { 64 SCIx_ERI_IRQ, 65 SCIx_RXI_IRQ, 66 SCIx_TXI_IRQ, 67 SCIx_BRI_IRQ, 68 SCIx_DRI_IRQ, 69 SCIx_TEI_IRQ, 70 SCIx_NR_IRQS, 71 72 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */ 73 }; 74 75 #define SCIx_IRQ_IS_MUXED(port) \ 76 ((port)->irqs[SCIx_ERI_IRQ] == \ 77 (port)->irqs[SCIx_RXI_IRQ]) || \ 78 ((port)->irqs[SCIx_ERI_IRQ] && \ 79 ((port)->irqs[SCIx_RXI_IRQ] < 0)) 80 81 enum SCI_CLKS { 82 SCI_FCK, /* Functional Clock */ 83 SCI_SCK, /* Optional External Clock */ 84 SCI_BRG_INT, /* Optional BRG Internal Clock Source */ 85 SCI_SCIF_CLK, /* Optional BRG External Clock Source */ 86 SCI_NUM_CLKS 87 }; 88 89 /* Bit x set means sampling rate x + 1 is supported */ 90 #define SCI_SR(x) BIT((x) - 1) 91 #define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1) 92 93 #define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \ 94 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \ 95 SCI_SR(19) | SCI_SR(27) 96 97 #define min_sr(_port) ffs((_port)->sampling_rate_mask) 98 #define max_sr(_port) fls((_port)->sampling_rate_mask) 99 100 /* Iterate over all supported sampling rates, from high to low */ 101 #define for_each_sr(_sr, _port) \ 102 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \ 103 if ((_port)->sampling_rate_mask & SCI_SR((_sr))) 104 105 struct plat_sci_reg { 106 u8 offset, size; 107 }; 108 109 struct sci_port_params { 110 const struct plat_sci_reg regs[SCIx_NR_REGS]; 111 unsigned int fifosize; 112 unsigned int overrun_reg; 113 unsigned int overrun_mask; 114 unsigned int sampling_rate_mask; 115 unsigned int error_mask; 116 unsigned int error_clear; 117 }; 118 119 struct sci_port { 120 struct uart_port port; 121 122 /* Platform configuration */ 123 const struct sci_port_params *params; 124 const struct plat_sci_port *cfg; 125 unsigned int sampling_rate_mask; 126 resource_size_t reg_size; 127 struct mctrl_gpios *gpios; 128 129 /* Clocks */ 130 struct clk *clks[SCI_NUM_CLKS]; 131 unsigned long clk_rates[SCI_NUM_CLKS]; 132 133 int irqs[SCIx_NR_IRQS]; 134 char *irqstr[SCIx_NR_IRQS]; 135 136 struct dma_chan *chan_tx; 137 struct dma_chan *chan_rx; 138 139 #ifdef CONFIG_SERIAL_SH_SCI_DMA 140 struct dma_chan *chan_tx_saved; 141 struct dma_chan *chan_rx_saved; 142 dma_cookie_t cookie_tx; 143 dma_cookie_t cookie_rx[2]; 144 dma_cookie_t active_rx; 145 dma_addr_t tx_dma_addr; 146 unsigned int tx_dma_len; 147 struct scatterlist sg_rx[2]; 148 void *rx_buf[2]; 149 size_t buf_len_rx; 150 struct work_struct work_tx; 151 struct hrtimer rx_timer; 152 unsigned int rx_timeout; /* microseconds */ 153 #endif 154 unsigned int rx_frame; 155 int rx_trigger; 156 struct timer_list rx_fifo_timer; 157 int rx_fifo_timeout; 158 u16 hscif_tot; 159 160 bool has_rtscts; 161 bool autorts; 162 }; 163 164 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS 165 166 static struct sci_port sci_ports[SCI_NPORTS]; 167 static unsigned long sci_ports_in_use; 168 static struct uart_driver sci_uart_driver; 169 170 static inline struct sci_port * 171 to_sci_port(struct uart_port *uart) 172 { 173 return container_of(uart, struct sci_port, port); 174 } 175 176 static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { 177 /* 178 * Common SCI definitions, dependent on the port's regshift 179 * value. 180 */ 181 [SCIx_SCI_REGTYPE] = { 182 .regs = { 183 [SCSMR] = { 0x00, 8 }, 184 [SCBRR] = { 0x01, 8 }, 185 [SCSCR] = { 0x02, 8 }, 186 [SCxTDR] = { 0x03, 8 }, 187 [SCxSR] = { 0x04, 8 }, 188 [SCxRDR] = { 0x05, 8 }, 189 }, 190 .fifosize = 1, 191 .overrun_reg = SCxSR, 192 .overrun_mask = SCI_ORER, 193 .sampling_rate_mask = SCI_SR(32), 194 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, 195 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, 196 }, 197 198 /* 199 * Common definitions for legacy IrDA ports. 200 */ 201 [SCIx_IRDA_REGTYPE] = { 202 .regs = { 203 [SCSMR] = { 0x00, 8 }, 204 [SCBRR] = { 0x02, 8 }, 205 [SCSCR] = { 0x04, 8 }, 206 [SCxTDR] = { 0x06, 8 }, 207 [SCxSR] = { 0x08, 16 }, 208 [SCxRDR] = { 0x0a, 8 }, 209 [SCFCR] = { 0x0c, 8 }, 210 [SCFDR] = { 0x0e, 16 }, 211 }, 212 .fifosize = 1, 213 .overrun_reg = SCxSR, 214 .overrun_mask = SCI_ORER, 215 .sampling_rate_mask = SCI_SR(32), 216 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, 217 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, 218 }, 219 220 /* 221 * Common SCIFA definitions. 222 */ 223 [SCIx_SCIFA_REGTYPE] = { 224 .regs = { 225 [SCSMR] = { 0x00, 16 }, 226 [SCBRR] = { 0x04, 8 }, 227 [SCSCR] = { 0x08, 16 }, 228 [SCxTDR] = { 0x20, 8 }, 229 [SCxSR] = { 0x14, 16 }, 230 [SCxRDR] = { 0x24, 8 }, 231 [SCFCR] = { 0x18, 16 }, 232 [SCFDR] = { 0x1c, 16 }, 233 [SCPCR] = { 0x30, 16 }, 234 [SCPDR] = { 0x34, 16 }, 235 }, 236 .fifosize = 64, 237 .overrun_reg = SCxSR, 238 .overrun_mask = SCIFA_ORER, 239 .sampling_rate_mask = SCI_SR_SCIFAB, 240 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 241 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 242 }, 243 244 /* 245 * Common SCIFB definitions. 246 */ 247 [SCIx_SCIFB_REGTYPE] = { 248 .regs = { 249 [SCSMR] = { 0x00, 16 }, 250 [SCBRR] = { 0x04, 8 }, 251 [SCSCR] = { 0x08, 16 }, 252 [SCxTDR] = { 0x40, 8 }, 253 [SCxSR] = { 0x14, 16 }, 254 [SCxRDR] = { 0x60, 8 }, 255 [SCFCR] = { 0x18, 16 }, 256 [SCTFDR] = { 0x38, 16 }, 257 [SCRFDR] = { 0x3c, 16 }, 258 [SCPCR] = { 0x30, 16 }, 259 [SCPDR] = { 0x34, 16 }, 260 }, 261 .fifosize = 256, 262 .overrun_reg = SCxSR, 263 .overrun_mask = SCIFA_ORER, 264 .sampling_rate_mask = SCI_SR_SCIFAB, 265 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 266 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 267 }, 268 269 /* 270 * Common SH-2(A) SCIF definitions for ports with FIFO data 271 * count registers. 272 */ 273 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = { 274 .regs = { 275 [SCSMR] = { 0x00, 16 }, 276 [SCBRR] = { 0x04, 8 }, 277 [SCSCR] = { 0x08, 16 }, 278 [SCxTDR] = { 0x0c, 8 }, 279 [SCxSR] = { 0x10, 16 }, 280 [SCxRDR] = { 0x14, 8 }, 281 [SCFCR] = { 0x18, 16 }, 282 [SCFDR] = { 0x1c, 16 }, 283 [SCSPTR] = { 0x20, 16 }, 284 [SCLSR] = { 0x24, 16 }, 285 }, 286 .fifosize = 16, 287 .overrun_reg = SCLSR, 288 .overrun_mask = SCLSR_ORER, 289 .sampling_rate_mask = SCI_SR(32), 290 .error_mask = SCIF_DEFAULT_ERROR_MASK, 291 .error_clear = SCIF_ERROR_CLEAR, 292 }, 293 294 /* 295 * The "SCIFA" that is in RZ/T and RZ/A2. 296 * It looks like a normal SCIF with FIFO data, but with a 297 * compressed address space. Also, the break out of interrupts 298 * are different: ERI/BRI, RXI, TXI, TEI, DRI. 299 */ 300 [SCIx_RZ_SCIFA_REGTYPE] = { 301 .regs = { 302 [SCSMR] = { 0x00, 16 }, 303 [SCBRR] = { 0x02, 8 }, 304 [SCSCR] = { 0x04, 16 }, 305 [SCxTDR] = { 0x06, 8 }, 306 [SCxSR] = { 0x08, 16 }, 307 [SCxRDR] = { 0x0A, 8 }, 308 [SCFCR] = { 0x0C, 16 }, 309 [SCFDR] = { 0x0E, 16 }, 310 [SCSPTR] = { 0x10, 16 }, 311 [SCLSR] = { 0x12, 16 }, 312 }, 313 .fifosize = 16, 314 .overrun_reg = SCLSR, 315 .overrun_mask = SCLSR_ORER, 316 .sampling_rate_mask = SCI_SR(32), 317 .error_mask = SCIF_DEFAULT_ERROR_MASK, 318 .error_clear = SCIF_ERROR_CLEAR, 319 }, 320 321 /* 322 * Common SH-3 SCIF definitions. 323 */ 324 [SCIx_SH3_SCIF_REGTYPE] = { 325 .regs = { 326 [SCSMR] = { 0x00, 8 }, 327 [SCBRR] = { 0x02, 8 }, 328 [SCSCR] = { 0x04, 8 }, 329 [SCxTDR] = { 0x06, 8 }, 330 [SCxSR] = { 0x08, 16 }, 331 [SCxRDR] = { 0x0a, 8 }, 332 [SCFCR] = { 0x0c, 8 }, 333 [SCFDR] = { 0x0e, 16 }, 334 }, 335 .fifosize = 16, 336 .overrun_reg = SCLSR, 337 .overrun_mask = SCLSR_ORER, 338 .sampling_rate_mask = SCI_SR(32), 339 .error_mask = SCIF_DEFAULT_ERROR_MASK, 340 .error_clear = SCIF_ERROR_CLEAR, 341 }, 342 343 /* 344 * Common SH-4(A) SCIF(B) definitions. 345 */ 346 [SCIx_SH4_SCIF_REGTYPE] = { 347 .regs = { 348 [SCSMR] = { 0x00, 16 }, 349 [SCBRR] = { 0x04, 8 }, 350 [SCSCR] = { 0x08, 16 }, 351 [SCxTDR] = { 0x0c, 8 }, 352 [SCxSR] = { 0x10, 16 }, 353 [SCxRDR] = { 0x14, 8 }, 354 [SCFCR] = { 0x18, 16 }, 355 [SCFDR] = { 0x1c, 16 }, 356 [SCSPTR] = { 0x20, 16 }, 357 [SCLSR] = { 0x24, 16 }, 358 }, 359 .fifosize = 16, 360 .overrun_reg = SCLSR, 361 .overrun_mask = SCLSR_ORER, 362 .sampling_rate_mask = SCI_SR(32), 363 .error_mask = SCIF_DEFAULT_ERROR_MASK, 364 .error_clear = SCIF_ERROR_CLEAR, 365 }, 366 367 /* 368 * Common SCIF definitions for ports with a Baud Rate Generator for 369 * External Clock (BRG). 370 */ 371 [SCIx_SH4_SCIF_BRG_REGTYPE] = { 372 .regs = { 373 [SCSMR] = { 0x00, 16 }, 374 [SCBRR] = { 0x04, 8 }, 375 [SCSCR] = { 0x08, 16 }, 376 [SCxTDR] = { 0x0c, 8 }, 377 [SCxSR] = { 0x10, 16 }, 378 [SCxRDR] = { 0x14, 8 }, 379 [SCFCR] = { 0x18, 16 }, 380 [SCFDR] = { 0x1c, 16 }, 381 [SCSPTR] = { 0x20, 16 }, 382 [SCLSR] = { 0x24, 16 }, 383 [SCDL] = { 0x30, 16 }, 384 [SCCKS] = { 0x34, 16 }, 385 }, 386 .fifosize = 16, 387 .overrun_reg = SCLSR, 388 .overrun_mask = SCLSR_ORER, 389 .sampling_rate_mask = SCI_SR(32), 390 .error_mask = SCIF_DEFAULT_ERROR_MASK, 391 .error_clear = SCIF_ERROR_CLEAR, 392 }, 393 394 /* 395 * Common HSCIF definitions. 396 */ 397 [SCIx_HSCIF_REGTYPE] = { 398 .regs = { 399 [SCSMR] = { 0x00, 16 }, 400 [SCBRR] = { 0x04, 8 }, 401 [SCSCR] = { 0x08, 16 }, 402 [SCxTDR] = { 0x0c, 8 }, 403 [SCxSR] = { 0x10, 16 }, 404 [SCxRDR] = { 0x14, 8 }, 405 [SCFCR] = { 0x18, 16 }, 406 [SCFDR] = { 0x1c, 16 }, 407 [SCSPTR] = { 0x20, 16 }, 408 [SCLSR] = { 0x24, 16 }, 409 [HSSRR] = { 0x40, 16 }, 410 [SCDL] = { 0x30, 16 }, 411 [SCCKS] = { 0x34, 16 }, 412 [HSRTRGR] = { 0x54, 16 }, 413 [HSTTRGR] = { 0x58, 16 }, 414 }, 415 .fifosize = 128, 416 .overrun_reg = SCLSR, 417 .overrun_mask = SCLSR_ORER, 418 .sampling_rate_mask = SCI_SR_RANGE(8, 32), 419 .error_mask = SCIF_DEFAULT_ERROR_MASK, 420 .error_clear = SCIF_ERROR_CLEAR, 421 }, 422 423 /* 424 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR 425 * register. 426 */ 427 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = { 428 .regs = { 429 [SCSMR] = { 0x00, 16 }, 430 [SCBRR] = { 0x04, 8 }, 431 [SCSCR] = { 0x08, 16 }, 432 [SCxTDR] = { 0x0c, 8 }, 433 [SCxSR] = { 0x10, 16 }, 434 [SCxRDR] = { 0x14, 8 }, 435 [SCFCR] = { 0x18, 16 }, 436 [SCFDR] = { 0x1c, 16 }, 437 [SCLSR] = { 0x24, 16 }, 438 }, 439 .fifosize = 16, 440 .overrun_reg = SCLSR, 441 .overrun_mask = SCLSR_ORER, 442 .sampling_rate_mask = SCI_SR(32), 443 .error_mask = SCIF_DEFAULT_ERROR_MASK, 444 .error_clear = SCIF_ERROR_CLEAR, 445 }, 446 447 /* 448 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data 449 * count registers. 450 */ 451 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = { 452 .regs = { 453 [SCSMR] = { 0x00, 16 }, 454 [SCBRR] = { 0x04, 8 }, 455 [SCSCR] = { 0x08, 16 }, 456 [SCxTDR] = { 0x0c, 8 }, 457 [SCxSR] = { 0x10, 16 }, 458 [SCxRDR] = { 0x14, 8 }, 459 [SCFCR] = { 0x18, 16 }, 460 [SCFDR] = { 0x1c, 16 }, 461 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */ 462 [SCRFDR] = { 0x20, 16 }, 463 [SCSPTR] = { 0x24, 16 }, 464 [SCLSR] = { 0x28, 16 }, 465 }, 466 .fifosize = 16, 467 .overrun_reg = SCLSR, 468 .overrun_mask = SCLSR_ORER, 469 .sampling_rate_mask = SCI_SR(32), 470 .error_mask = SCIF_DEFAULT_ERROR_MASK, 471 .error_clear = SCIF_ERROR_CLEAR, 472 }, 473 474 /* 475 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR 476 * registers. 477 */ 478 [SCIx_SH7705_SCIF_REGTYPE] = { 479 .regs = { 480 [SCSMR] = { 0x00, 16 }, 481 [SCBRR] = { 0x04, 8 }, 482 [SCSCR] = { 0x08, 16 }, 483 [SCxTDR] = { 0x20, 8 }, 484 [SCxSR] = { 0x14, 16 }, 485 [SCxRDR] = { 0x24, 8 }, 486 [SCFCR] = { 0x18, 16 }, 487 [SCFDR] = { 0x1c, 16 }, 488 }, 489 .fifosize = 64, 490 .overrun_reg = SCxSR, 491 .overrun_mask = SCIFA_ORER, 492 .sampling_rate_mask = SCI_SR(16), 493 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 494 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 495 }, 496 }; 497 498 #define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset]) 499 500 /* 501 * The "offset" here is rather misleading, in that it refers to an enum 502 * value relative to the port mapping rather than the fixed offset 503 * itself, which needs to be manually retrieved from the platform's 504 * register map for the given port. 505 */ 506 static unsigned int sci_serial_in(struct uart_port *p, int offset) 507 { 508 const struct plat_sci_reg *reg = sci_getreg(p, offset); 509 510 if (reg->size == 8) 511 return ioread8(p->membase + (reg->offset << p->regshift)); 512 else if (reg->size == 16) 513 return ioread16(p->membase + (reg->offset << p->regshift)); 514 else 515 WARN(1, "Invalid register access\n"); 516 517 return 0; 518 } 519 520 static void sci_serial_out(struct uart_port *p, int offset, int value) 521 { 522 const struct plat_sci_reg *reg = sci_getreg(p, offset); 523 524 if (reg->size == 8) 525 iowrite8(value, p->membase + (reg->offset << p->regshift)); 526 else if (reg->size == 16) 527 iowrite16(value, p->membase + (reg->offset << p->regshift)); 528 else 529 WARN(1, "Invalid register access\n"); 530 } 531 532 static void sci_port_enable(struct sci_port *sci_port) 533 { 534 unsigned int i; 535 536 if (!sci_port->port.dev) 537 return; 538 539 pm_runtime_get_sync(sci_port->port.dev); 540 541 for (i = 0; i < SCI_NUM_CLKS; i++) { 542 clk_prepare_enable(sci_port->clks[i]); 543 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]); 544 } 545 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK]; 546 } 547 548 static void sci_port_disable(struct sci_port *sci_port) 549 { 550 unsigned int i; 551 552 if (!sci_port->port.dev) 553 return; 554 555 for (i = SCI_NUM_CLKS; i-- > 0; ) 556 clk_disable_unprepare(sci_port->clks[i]); 557 558 pm_runtime_put_sync(sci_port->port.dev); 559 } 560 561 static inline unsigned long port_rx_irq_mask(struct uart_port *port) 562 { 563 /* 564 * Not all ports (such as SCIFA) will support REIE. Rather than 565 * special-casing the port type, we check the port initialization 566 * IRQ enable mask to see whether the IRQ is desired at all. If 567 * it's unset, it's logically inferred that there's no point in 568 * testing for it. 569 */ 570 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE); 571 } 572 573 static void sci_start_tx(struct uart_port *port) 574 { 575 struct sci_port *s = to_sci_port(port); 576 unsigned short ctrl; 577 578 #ifdef CONFIG_SERIAL_SH_SCI_DMA 579 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 580 u16 new, scr = serial_port_in(port, SCSCR); 581 if (s->chan_tx) 582 new = scr | SCSCR_TDRQE; 583 else 584 new = scr & ~SCSCR_TDRQE; 585 if (new != scr) 586 serial_port_out(port, SCSCR, new); 587 } 588 589 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) && 590 dma_submit_error(s->cookie_tx)) { 591 s->cookie_tx = 0; 592 schedule_work(&s->work_tx); 593 } 594 #endif 595 596 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 597 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ 598 ctrl = serial_port_in(port, SCSCR); 599 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE); 600 } 601 } 602 603 static void sci_stop_tx(struct uart_port *port) 604 { 605 unsigned short ctrl; 606 607 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ 608 ctrl = serial_port_in(port, SCSCR); 609 610 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 611 ctrl &= ~SCSCR_TDRQE; 612 613 ctrl &= ~SCSCR_TIE; 614 615 serial_port_out(port, SCSCR, ctrl); 616 } 617 618 static void sci_start_rx(struct uart_port *port) 619 { 620 unsigned short ctrl; 621 622 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port); 623 624 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 625 ctrl &= ~SCSCR_RDRQE; 626 627 serial_port_out(port, SCSCR, ctrl); 628 } 629 630 static void sci_stop_rx(struct uart_port *port) 631 { 632 unsigned short ctrl; 633 634 ctrl = serial_port_in(port, SCSCR); 635 636 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 637 ctrl &= ~SCSCR_RDRQE; 638 639 ctrl &= ~port_rx_irq_mask(port); 640 641 serial_port_out(port, SCSCR, ctrl); 642 } 643 644 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask) 645 { 646 if (port->type == PORT_SCI) { 647 /* Just store the mask */ 648 serial_port_out(port, SCxSR, mask); 649 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) { 650 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */ 651 /* Only clear the status bits we want to clear */ 652 serial_port_out(port, SCxSR, 653 serial_port_in(port, SCxSR) & mask); 654 } else { 655 /* Store the mask, clear parity/framing errors */ 656 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC)); 657 } 658 } 659 660 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ 661 defined(CONFIG_SERIAL_SH_SCI_EARLYCON) 662 663 #ifdef CONFIG_CONSOLE_POLL 664 static int sci_poll_get_char(struct uart_port *port) 665 { 666 unsigned short status; 667 int c; 668 669 do { 670 status = serial_port_in(port, SCxSR); 671 if (status & SCxSR_ERRORS(port)) { 672 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); 673 continue; 674 } 675 break; 676 } while (1); 677 678 if (!(status & SCxSR_RDxF(port))) 679 return NO_POLL_CHAR; 680 681 c = serial_port_in(port, SCxRDR); 682 683 /* Dummy read */ 684 serial_port_in(port, SCxSR); 685 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 686 687 return c; 688 } 689 #endif 690 691 static void sci_poll_put_char(struct uart_port *port, unsigned char c) 692 { 693 unsigned short status; 694 695 do { 696 status = serial_port_in(port, SCxSR); 697 } while (!(status & SCxSR_TDxE(port))); 698 699 serial_port_out(port, SCxTDR, c); 700 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port)); 701 } 702 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE || 703 CONFIG_SERIAL_SH_SCI_EARLYCON */ 704 705 static void sci_init_pins(struct uart_port *port, unsigned int cflag) 706 { 707 struct sci_port *s = to_sci_port(port); 708 709 /* 710 * Use port-specific handler if provided. 711 */ 712 if (s->cfg->ops && s->cfg->ops->init_pins) { 713 s->cfg->ops->init_pins(port, cflag); 714 return; 715 } 716 717 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 718 u16 data = serial_port_in(port, SCPDR); 719 u16 ctrl = serial_port_in(port, SCPCR); 720 721 /* Enable RXD and TXD pin functions */ 722 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC); 723 if (to_sci_port(port)->has_rtscts) { 724 /* RTS# is output, active low, unless autorts */ 725 if (!(port->mctrl & TIOCM_RTS)) { 726 ctrl |= SCPCR_RTSC; 727 data |= SCPDR_RTSD; 728 } else if (!s->autorts) { 729 ctrl |= SCPCR_RTSC; 730 data &= ~SCPDR_RTSD; 731 } else { 732 /* Enable RTS# pin function */ 733 ctrl &= ~SCPCR_RTSC; 734 } 735 /* Enable CTS# pin function */ 736 ctrl &= ~SCPCR_CTSC; 737 } 738 serial_port_out(port, SCPDR, data); 739 serial_port_out(port, SCPCR, ctrl); 740 } else if (sci_getreg(port, SCSPTR)->size) { 741 u16 status = serial_port_in(port, SCSPTR); 742 743 /* RTS# is always output; and active low, unless autorts */ 744 status |= SCSPTR_RTSIO; 745 if (!(port->mctrl & TIOCM_RTS)) 746 status |= SCSPTR_RTSDT; 747 else if (!s->autorts) 748 status &= ~SCSPTR_RTSDT; 749 /* CTS# and SCK are inputs */ 750 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO); 751 serial_port_out(port, SCSPTR, status); 752 } 753 } 754 755 static int sci_txfill(struct uart_port *port) 756 { 757 struct sci_port *s = to_sci_port(port); 758 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; 759 const struct plat_sci_reg *reg; 760 761 reg = sci_getreg(port, SCTFDR); 762 if (reg->size) 763 return serial_port_in(port, SCTFDR) & fifo_mask; 764 765 reg = sci_getreg(port, SCFDR); 766 if (reg->size) 767 return serial_port_in(port, SCFDR) >> 8; 768 769 return !(serial_port_in(port, SCxSR) & SCI_TDRE); 770 } 771 772 static int sci_txroom(struct uart_port *port) 773 { 774 return port->fifosize - sci_txfill(port); 775 } 776 777 static int sci_rxfill(struct uart_port *port) 778 { 779 struct sci_port *s = to_sci_port(port); 780 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; 781 const struct plat_sci_reg *reg; 782 783 reg = sci_getreg(port, SCRFDR); 784 if (reg->size) 785 return serial_port_in(port, SCRFDR) & fifo_mask; 786 787 reg = sci_getreg(port, SCFDR); 788 if (reg->size) 789 return serial_port_in(port, SCFDR) & fifo_mask; 790 791 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0; 792 } 793 794 /* ********************************************************************** * 795 * the interrupt related routines * 796 * ********************************************************************** */ 797 798 static void sci_transmit_chars(struct uart_port *port) 799 { 800 struct circ_buf *xmit = &port->state->xmit; 801 unsigned int stopped = uart_tx_stopped(port); 802 unsigned short status; 803 unsigned short ctrl; 804 int count; 805 806 status = serial_port_in(port, SCxSR); 807 if (!(status & SCxSR_TDxE(port))) { 808 ctrl = serial_port_in(port, SCSCR); 809 if (uart_circ_empty(xmit)) 810 ctrl &= ~SCSCR_TIE; 811 else 812 ctrl |= SCSCR_TIE; 813 serial_port_out(port, SCSCR, ctrl); 814 return; 815 } 816 817 count = sci_txroom(port); 818 819 do { 820 unsigned char c; 821 822 if (port->x_char) { 823 c = port->x_char; 824 port->x_char = 0; 825 } else if (!uart_circ_empty(xmit) && !stopped) { 826 c = xmit->buf[xmit->tail]; 827 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 828 } else { 829 break; 830 } 831 832 serial_port_out(port, SCxTDR, c); 833 834 port->icount.tx++; 835 } while (--count > 0); 836 837 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port)); 838 839 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 840 uart_write_wakeup(port); 841 if (uart_circ_empty(xmit)) 842 sci_stop_tx(port); 843 844 } 845 846 /* On SH3, SCIF may read end-of-break as a space->mark char */ 847 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); }) 848 849 static void sci_receive_chars(struct uart_port *port) 850 { 851 struct tty_port *tport = &port->state->port; 852 int i, count, copied = 0; 853 unsigned short status; 854 unsigned char flag; 855 856 status = serial_port_in(port, SCxSR); 857 if (!(status & SCxSR_RDxF(port))) 858 return; 859 860 while (1) { 861 /* Don't copy more bytes than there is room for in the buffer */ 862 count = tty_buffer_request_room(tport, sci_rxfill(port)); 863 864 /* If for any reason we can't copy more data, we're done! */ 865 if (count == 0) 866 break; 867 868 if (port->type == PORT_SCI) { 869 char c = serial_port_in(port, SCxRDR); 870 if (uart_handle_sysrq_char(port, c)) 871 count = 0; 872 else 873 tty_insert_flip_char(tport, c, TTY_NORMAL); 874 } else { 875 for (i = 0; i < count; i++) { 876 char c = serial_port_in(port, SCxRDR); 877 878 status = serial_port_in(port, SCxSR); 879 if (uart_handle_sysrq_char(port, c)) { 880 count--; i--; 881 continue; 882 } 883 884 /* Store data and status */ 885 if (status & SCxSR_FER(port)) { 886 flag = TTY_FRAME; 887 port->icount.frame++; 888 dev_notice(port->dev, "frame error\n"); 889 } else if (status & SCxSR_PER(port)) { 890 flag = TTY_PARITY; 891 port->icount.parity++; 892 dev_notice(port->dev, "parity error\n"); 893 } else 894 flag = TTY_NORMAL; 895 896 tty_insert_flip_char(tport, c, flag); 897 } 898 } 899 900 serial_port_in(port, SCxSR); /* dummy read */ 901 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 902 903 copied += count; 904 port->icount.rx += count; 905 } 906 907 if (copied) { 908 /* Tell the rest of the system the news. New characters! */ 909 tty_flip_buffer_push(tport); 910 } else { 911 /* TTY buffers full; read from RX reg to prevent lockup */ 912 serial_port_in(port, SCxRDR); 913 serial_port_in(port, SCxSR); /* dummy read */ 914 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 915 } 916 } 917 918 static int sci_handle_errors(struct uart_port *port) 919 { 920 int copied = 0; 921 unsigned short status = serial_port_in(port, SCxSR); 922 struct tty_port *tport = &port->state->port; 923 struct sci_port *s = to_sci_port(port); 924 925 /* Handle overruns */ 926 if (status & s->params->overrun_mask) { 927 port->icount.overrun++; 928 929 /* overrun error */ 930 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN)) 931 copied++; 932 933 dev_notice(port->dev, "overrun error\n"); 934 } 935 936 if (status & SCxSR_FER(port)) { 937 /* frame error */ 938 port->icount.frame++; 939 940 if (tty_insert_flip_char(tport, 0, TTY_FRAME)) 941 copied++; 942 943 dev_notice(port->dev, "frame error\n"); 944 } 945 946 if (status & SCxSR_PER(port)) { 947 /* parity error */ 948 port->icount.parity++; 949 950 if (tty_insert_flip_char(tport, 0, TTY_PARITY)) 951 copied++; 952 953 dev_notice(port->dev, "parity error\n"); 954 } 955 956 if (copied) 957 tty_flip_buffer_push(tport); 958 959 return copied; 960 } 961 962 static int sci_handle_fifo_overrun(struct uart_port *port) 963 { 964 struct tty_port *tport = &port->state->port; 965 struct sci_port *s = to_sci_port(port); 966 const struct plat_sci_reg *reg; 967 int copied = 0; 968 u16 status; 969 970 reg = sci_getreg(port, s->params->overrun_reg); 971 if (!reg->size) 972 return 0; 973 974 status = serial_port_in(port, s->params->overrun_reg); 975 if (status & s->params->overrun_mask) { 976 status &= ~s->params->overrun_mask; 977 serial_port_out(port, s->params->overrun_reg, status); 978 979 port->icount.overrun++; 980 981 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 982 tty_flip_buffer_push(tport); 983 984 dev_dbg(port->dev, "overrun error\n"); 985 copied++; 986 } 987 988 return copied; 989 } 990 991 static int sci_handle_breaks(struct uart_port *port) 992 { 993 int copied = 0; 994 unsigned short status = serial_port_in(port, SCxSR); 995 struct tty_port *tport = &port->state->port; 996 997 if (uart_handle_break(port)) 998 return 0; 999 1000 if (status & SCxSR_BRK(port)) { 1001 port->icount.brk++; 1002 1003 /* Notify of BREAK */ 1004 if (tty_insert_flip_char(tport, 0, TTY_BREAK)) 1005 copied++; 1006 1007 dev_dbg(port->dev, "BREAK detected\n"); 1008 } 1009 1010 if (copied) 1011 tty_flip_buffer_push(tport); 1012 1013 copied += sci_handle_fifo_overrun(port); 1014 1015 return copied; 1016 } 1017 1018 static int scif_set_rtrg(struct uart_port *port, int rx_trig) 1019 { 1020 unsigned int bits; 1021 1022 if (rx_trig < 1) 1023 rx_trig = 1; 1024 if (rx_trig >= port->fifosize) 1025 rx_trig = port->fifosize; 1026 1027 /* HSCIF can be set to an arbitrary level. */ 1028 if (sci_getreg(port, HSRTRGR)->size) { 1029 serial_port_out(port, HSRTRGR, rx_trig); 1030 return rx_trig; 1031 } 1032 1033 switch (port->type) { 1034 case PORT_SCIF: 1035 if (rx_trig < 4) { 1036 bits = 0; 1037 rx_trig = 1; 1038 } else if (rx_trig < 8) { 1039 bits = SCFCR_RTRG0; 1040 rx_trig = 4; 1041 } else if (rx_trig < 14) { 1042 bits = SCFCR_RTRG1; 1043 rx_trig = 8; 1044 } else { 1045 bits = SCFCR_RTRG0 | SCFCR_RTRG1; 1046 rx_trig = 14; 1047 } 1048 break; 1049 case PORT_SCIFA: 1050 case PORT_SCIFB: 1051 if (rx_trig < 16) { 1052 bits = 0; 1053 rx_trig = 1; 1054 } else if (rx_trig < 32) { 1055 bits = SCFCR_RTRG0; 1056 rx_trig = 16; 1057 } else if (rx_trig < 48) { 1058 bits = SCFCR_RTRG1; 1059 rx_trig = 32; 1060 } else { 1061 bits = SCFCR_RTRG0 | SCFCR_RTRG1; 1062 rx_trig = 48; 1063 } 1064 break; 1065 default: 1066 WARN(1, "unknown FIFO configuration"); 1067 return 1; 1068 } 1069 1070 serial_port_out(port, SCFCR, 1071 (serial_port_in(port, SCFCR) & 1072 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits); 1073 1074 return rx_trig; 1075 } 1076 1077 static int scif_rtrg_enabled(struct uart_port *port) 1078 { 1079 if (sci_getreg(port, HSRTRGR)->size) 1080 return serial_port_in(port, HSRTRGR) != 0; 1081 else 1082 return (serial_port_in(port, SCFCR) & 1083 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0; 1084 } 1085 1086 static void rx_fifo_timer_fn(struct timer_list *t) 1087 { 1088 struct sci_port *s = from_timer(s, t, rx_fifo_timer); 1089 struct uart_port *port = &s->port; 1090 1091 dev_dbg(port->dev, "Rx timed out\n"); 1092 scif_set_rtrg(port, 1); 1093 } 1094 1095 static ssize_t rx_trigger_show(struct device *dev, 1096 struct device_attribute *attr, 1097 char *buf) 1098 { 1099 struct uart_port *port = dev_get_drvdata(dev); 1100 struct sci_port *sci = to_sci_port(port); 1101 1102 return sprintf(buf, "%d\n", sci->rx_trigger); 1103 } 1104 1105 static ssize_t rx_trigger_store(struct device *dev, 1106 struct device_attribute *attr, 1107 const char *buf, 1108 size_t count) 1109 { 1110 struct uart_port *port = dev_get_drvdata(dev); 1111 struct sci_port *sci = to_sci_port(port); 1112 int ret; 1113 long r; 1114 1115 ret = kstrtol(buf, 0, &r); 1116 if (ret) 1117 return ret; 1118 1119 sci->rx_trigger = scif_set_rtrg(port, r); 1120 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1121 scif_set_rtrg(port, 1); 1122 1123 return count; 1124 } 1125 1126 static DEVICE_ATTR(rx_fifo_trigger, 0644, rx_trigger_show, rx_trigger_store); 1127 1128 static ssize_t rx_fifo_timeout_show(struct device *dev, 1129 struct device_attribute *attr, 1130 char *buf) 1131 { 1132 struct uart_port *port = dev_get_drvdata(dev); 1133 struct sci_port *sci = to_sci_port(port); 1134 int v; 1135 1136 if (port->type == PORT_HSCIF) 1137 v = sci->hscif_tot >> HSSCR_TOT_SHIFT; 1138 else 1139 v = sci->rx_fifo_timeout; 1140 1141 return sprintf(buf, "%d\n", v); 1142 } 1143 1144 static ssize_t rx_fifo_timeout_store(struct device *dev, 1145 struct device_attribute *attr, 1146 const char *buf, 1147 size_t count) 1148 { 1149 struct uart_port *port = dev_get_drvdata(dev); 1150 struct sci_port *sci = to_sci_port(port); 1151 int ret; 1152 long r; 1153 1154 ret = kstrtol(buf, 0, &r); 1155 if (ret) 1156 return ret; 1157 1158 if (port->type == PORT_HSCIF) { 1159 if (r < 0 || r > 3) 1160 return -EINVAL; 1161 sci->hscif_tot = r << HSSCR_TOT_SHIFT; 1162 } else { 1163 sci->rx_fifo_timeout = r; 1164 scif_set_rtrg(port, 1); 1165 if (r > 0) 1166 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0); 1167 } 1168 1169 return count; 1170 } 1171 1172 static DEVICE_ATTR_RW(rx_fifo_timeout); 1173 1174 1175 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1176 static void sci_dma_tx_complete(void *arg) 1177 { 1178 struct sci_port *s = arg; 1179 struct uart_port *port = &s->port; 1180 struct circ_buf *xmit = &port->state->xmit; 1181 unsigned long flags; 1182 1183 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1184 1185 spin_lock_irqsave(&port->lock, flags); 1186 1187 xmit->tail += s->tx_dma_len; 1188 xmit->tail &= UART_XMIT_SIZE - 1; 1189 1190 port->icount.tx += s->tx_dma_len; 1191 1192 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1193 uart_write_wakeup(port); 1194 1195 if (!uart_circ_empty(xmit)) { 1196 s->cookie_tx = 0; 1197 schedule_work(&s->work_tx); 1198 } else { 1199 s->cookie_tx = -EINVAL; 1200 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1201 u16 ctrl = serial_port_in(port, SCSCR); 1202 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE); 1203 } 1204 } 1205 1206 spin_unlock_irqrestore(&port->lock, flags); 1207 } 1208 1209 /* Locking: called with port lock held */ 1210 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count) 1211 { 1212 struct uart_port *port = &s->port; 1213 struct tty_port *tport = &port->state->port; 1214 int copied; 1215 1216 copied = tty_insert_flip_string(tport, buf, count); 1217 if (copied < count) 1218 port->icount.buf_overrun++; 1219 1220 port->icount.rx += copied; 1221 1222 return copied; 1223 } 1224 1225 static int sci_dma_rx_find_active(struct sci_port *s) 1226 { 1227 unsigned int i; 1228 1229 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) 1230 if (s->active_rx == s->cookie_rx[i]) 1231 return i; 1232 1233 return -1; 1234 } 1235 1236 static void sci_dma_rx_chan_invalidate(struct sci_port *s) 1237 { 1238 unsigned int i; 1239 1240 s->chan_rx = NULL; 1241 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) 1242 s->cookie_rx[i] = -EINVAL; 1243 s->active_rx = 0; 1244 } 1245 1246 static void sci_dma_rx_release(struct sci_port *s) 1247 { 1248 struct dma_chan *chan = s->chan_rx_saved; 1249 1250 s->chan_rx_saved = NULL; 1251 sci_dma_rx_chan_invalidate(s); 1252 dmaengine_terminate_sync(chan); 1253 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0], 1254 sg_dma_address(&s->sg_rx[0])); 1255 dma_release_channel(chan); 1256 } 1257 1258 static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec) 1259 { 1260 long sec = usec / 1000000; 1261 long nsec = (usec % 1000000) * 1000; 1262 ktime_t t = ktime_set(sec, nsec); 1263 1264 hrtimer_start(hrt, t, HRTIMER_MODE_REL); 1265 } 1266 1267 static void sci_dma_rx_reenable_irq(struct sci_port *s) 1268 { 1269 struct uart_port *port = &s->port; 1270 u16 scr; 1271 1272 /* Direct new serial port interrupts back to CPU */ 1273 scr = serial_port_in(port, SCSCR); 1274 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1275 scr &= ~SCSCR_RDRQE; 1276 enable_irq(s->irqs[SCIx_RXI_IRQ]); 1277 } 1278 serial_port_out(port, SCSCR, scr | SCSCR_RIE); 1279 } 1280 1281 static void sci_dma_rx_complete(void *arg) 1282 { 1283 struct sci_port *s = arg; 1284 struct dma_chan *chan = s->chan_rx; 1285 struct uart_port *port = &s->port; 1286 struct dma_async_tx_descriptor *desc; 1287 unsigned long flags; 1288 int active, count = 0; 1289 1290 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line, 1291 s->active_rx); 1292 1293 spin_lock_irqsave(&port->lock, flags); 1294 1295 active = sci_dma_rx_find_active(s); 1296 if (active >= 0) 1297 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx); 1298 1299 start_hrtimer_us(&s->rx_timer, s->rx_timeout); 1300 1301 if (count) 1302 tty_flip_buffer_push(&port->state->port); 1303 1304 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1, 1305 DMA_DEV_TO_MEM, 1306 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1307 if (!desc) 1308 goto fail; 1309 1310 desc->callback = sci_dma_rx_complete; 1311 desc->callback_param = s; 1312 s->cookie_rx[active] = dmaengine_submit(desc); 1313 if (dma_submit_error(s->cookie_rx[active])) 1314 goto fail; 1315 1316 s->active_rx = s->cookie_rx[!active]; 1317 1318 dma_async_issue_pending(chan); 1319 1320 spin_unlock_irqrestore(&port->lock, flags); 1321 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n", 1322 __func__, s->cookie_rx[active], active, s->active_rx); 1323 return; 1324 1325 fail: 1326 spin_unlock_irqrestore(&port->lock, flags); 1327 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n"); 1328 /* Switch to PIO */ 1329 spin_lock_irqsave(&port->lock, flags); 1330 dmaengine_terminate_async(chan); 1331 sci_dma_rx_chan_invalidate(s); 1332 sci_dma_rx_reenable_irq(s); 1333 spin_unlock_irqrestore(&port->lock, flags); 1334 } 1335 1336 static void sci_dma_tx_release(struct sci_port *s) 1337 { 1338 struct dma_chan *chan = s->chan_tx_saved; 1339 1340 cancel_work_sync(&s->work_tx); 1341 s->chan_tx_saved = s->chan_tx = NULL; 1342 s->cookie_tx = -EINVAL; 1343 dmaengine_terminate_sync(chan); 1344 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE, 1345 DMA_TO_DEVICE); 1346 dma_release_channel(chan); 1347 } 1348 1349 static int sci_dma_rx_submit(struct sci_port *s, bool port_lock_held) 1350 { 1351 struct dma_chan *chan = s->chan_rx; 1352 struct uart_port *port = &s->port; 1353 unsigned long flags; 1354 int i; 1355 1356 for (i = 0; i < 2; i++) { 1357 struct scatterlist *sg = &s->sg_rx[i]; 1358 struct dma_async_tx_descriptor *desc; 1359 1360 desc = dmaengine_prep_slave_sg(chan, 1361 sg, 1, DMA_DEV_TO_MEM, 1362 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1363 if (!desc) 1364 goto fail; 1365 1366 desc->callback = sci_dma_rx_complete; 1367 desc->callback_param = s; 1368 s->cookie_rx[i] = dmaengine_submit(desc); 1369 if (dma_submit_error(s->cookie_rx[i])) 1370 goto fail; 1371 1372 } 1373 1374 s->active_rx = s->cookie_rx[0]; 1375 1376 dma_async_issue_pending(chan); 1377 return 0; 1378 1379 fail: 1380 /* Switch to PIO */ 1381 if (!port_lock_held) 1382 spin_lock_irqsave(&port->lock, flags); 1383 if (i) 1384 dmaengine_terminate_async(chan); 1385 sci_dma_rx_chan_invalidate(s); 1386 sci_start_rx(port); 1387 if (!port_lock_held) 1388 spin_unlock_irqrestore(&port->lock, flags); 1389 return -EAGAIN; 1390 } 1391 1392 static void sci_dma_tx_work_fn(struct work_struct *work) 1393 { 1394 struct sci_port *s = container_of(work, struct sci_port, work_tx); 1395 struct dma_async_tx_descriptor *desc; 1396 struct dma_chan *chan = s->chan_tx; 1397 struct uart_port *port = &s->port; 1398 struct circ_buf *xmit = &port->state->xmit; 1399 unsigned long flags; 1400 dma_addr_t buf; 1401 1402 /* 1403 * DMA is idle now. 1404 * Port xmit buffer is already mapped, and it is one page... Just adjust 1405 * offsets and lengths. Since it is a circular buffer, we have to 1406 * transmit till the end, and then the rest. Take the port lock to get a 1407 * consistent xmit buffer state. 1408 */ 1409 spin_lock_irq(&port->lock); 1410 buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1)); 1411 s->tx_dma_len = min_t(unsigned int, 1412 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE), 1413 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE)); 1414 spin_unlock_irq(&port->lock); 1415 1416 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len, 1417 DMA_MEM_TO_DEV, 1418 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1419 if (!desc) { 1420 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n"); 1421 goto switch_to_pio; 1422 } 1423 1424 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len, 1425 DMA_TO_DEVICE); 1426 1427 spin_lock_irq(&port->lock); 1428 desc->callback = sci_dma_tx_complete; 1429 desc->callback_param = s; 1430 spin_unlock_irq(&port->lock); 1431 s->cookie_tx = dmaengine_submit(desc); 1432 if (dma_submit_error(s->cookie_tx)) { 1433 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n"); 1434 goto switch_to_pio; 1435 } 1436 1437 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", 1438 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx); 1439 1440 dma_async_issue_pending(chan); 1441 return; 1442 1443 switch_to_pio: 1444 spin_lock_irqsave(&port->lock, flags); 1445 s->chan_tx = NULL; 1446 sci_start_tx(port); 1447 spin_unlock_irqrestore(&port->lock, flags); 1448 return; 1449 } 1450 1451 static enum hrtimer_restart sci_dma_rx_timer_fn(struct hrtimer *t) 1452 { 1453 struct sci_port *s = container_of(t, struct sci_port, rx_timer); 1454 struct dma_chan *chan = s->chan_rx; 1455 struct uart_port *port = &s->port; 1456 struct dma_tx_state state; 1457 enum dma_status status; 1458 unsigned long flags; 1459 unsigned int read; 1460 int active, count; 1461 1462 dev_dbg(port->dev, "DMA Rx timed out\n"); 1463 1464 spin_lock_irqsave(&port->lock, flags); 1465 1466 active = sci_dma_rx_find_active(s); 1467 if (active < 0) { 1468 spin_unlock_irqrestore(&port->lock, flags); 1469 return HRTIMER_NORESTART; 1470 } 1471 1472 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); 1473 if (status == DMA_COMPLETE) { 1474 spin_unlock_irqrestore(&port->lock, flags); 1475 dev_dbg(port->dev, "Cookie %d #%d has already completed\n", 1476 s->active_rx, active); 1477 1478 /* Let packet complete handler take care of the packet */ 1479 return HRTIMER_NORESTART; 1480 } 1481 1482 dmaengine_pause(chan); 1483 1484 /* 1485 * sometimes DMA transfer doesn't stop even if it is stopped and 1486 * data keeps on coming until transaction is complete so check 1487 * for DMA_COMPLETE again 1488 * Let packet complete handler take care of the packet 1489 */ 1490 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); 1491 if (status == DMA_COMPLETE) { 1492 spin_unlock_irqrestore(&port->lock, flags); 1493 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped"); 1494 return HRTIMER_NORESTART; 1495 } 1496 1497 /* Handle incomplete DMA receive */ 1498 dmaengine_terminate_async(s->chan_rx); 1499 read = sg_dma_len(&s->sg_rx[active]) - state.residue; 1500 1501 if (read) { 1502 count = sci_dma_rx_push(s, s->rx_buf[active], read); 1503 if (count) 1504 tty_flip_buffer_push(&port->state->port); 1505 } 1506 1507 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1508 sci_dma_rx_submit(s, true); 1509 1510 sci_dma_rx_reenable_irq(s); 1511 1512 spin_unlock_irqrestore(&port->lock, flags); 1513 1514 return HRTIMER_NORESTART; 1515 } 1516 1517 static struct dma_chan *sci_request_dma_chan(struct uart_port *port, 1518 enum dma_transfer_direction dir) 1519 { 1520 struct dma_chan *chan; 1521 struct dma_slave_config cfg; 1522 int ret; 1523 1524 chan = dma_request_slave_channel(port->dev, 1525 dir == DMA_MEM_TO_DEV ? "tx" : "rx"); 1526 if (!chan) { 1527 dev_dbg(port->dev, "dma_request_slave_channel failed\n"); 1528 return NULL; 1529 } 1530 1531 memset(&cfg, 0, sizeof(cfg)); 1532 cfg.direction = dir; 1533 if (dir == DMA_MEM_TO_DEV) { 1534 cfg.dst_addr = port->mapbase + 1535 (sci_getreg(port, SCxTDR)->offset << port->regshift); 1536 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1537 } else { 1538 cfg.src_addr = port->mapbase + 1539 (sci_getreg(port, SCxRDR)->offset << port->regshift); 1540 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1541 } 1542 1543 ret = dmaengine_slave_config(chan, &cfg); 1544 if (ret) { 1545 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret); 1546 dma_release_channel(chan); 1547 return NULL; 1548 } 1549 1550 return chan; 1551 } 1552 1553 static void sci_request_dma(struct uart_port *port) 1554 { 1555 struct sci_port *s = to_sci_port(port); 1556 struct dma_chan *chan; 1557 1558 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line); 1559 1560 if (!port->dev->of_node) 1561 return; 1562 1563 s->cookie_tx = -EINVAL; 1564 1565 /* 1566 * Don't request a dma channel if no channel was specified 1567 * in the device tree. 1568 */ 1569 if (!of_find_property(port->dev->of_node, "dmas", NULL)) 1570 return; 1571 1572 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV); 1573 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan); 1574 if (chan) { 1575 /* UART circular tx buffer is an aligned page. */ 1576 s->tx_dma_addr = dma_map_single(chan->device->dev, 1577 port->state->xmit.buf, 1578 UART_XMIT_SIZE, 1579 DMA_TO_DEVICE); 1580 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) { 1581 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n"); 1582 dma_release_channel(chan); 1583 } else { 1584 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n", 1585 __func__, UART_XMIT_SIZE, 1586 port->state->xmit.buf, &s->tx_dma_addr); 1587 1588 INIT_WORK(&s->work_tx, sci_dma_tx_work_fn); 1589 s->chan_tx_saved = s->chan_tx = chan; 1590 } 1591 } 1592 1593 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM); 1594 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan); 1595 if (chan) { 1596 unsigned int i; 1597 dma_addr_t dma; 1598 void *buf; 1599 1600 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize); 1601 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2, 1602 &dma, GFP_KERNEL); 1603 if (!buf) { 1604 dev_warn(port->dev, 1605 "Failed to allocate Rx dma buffer, using PIO\n"); 1606 dma_release_channel(chan); 1607 return; 1608 } 1609 1610 for (i = 0; i < 2; i++) { 1611 struct scatterlist *sg = &s->sg_rx[i]; 1612 1613 sg_init_table(sg, 1); 1614 s->rx_buf[i] = buf; 1615 sg_dma_address(sg) = dma; 1616 sg_dma_len(sg) = s->buf_len_rx; 1617 1618 buf += s->buf_len_rx; 1619 dma += s->buf_len_rx; 1620 } 1621 1622 hrtimer_init(&s->rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 1623 s->rx_timer.function = sci_dma_rx_timer_fn; 1624 1625 s->chan_rx_saved = s->chan_rx = chan; 1626 1627 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1628 sci_dma_rx_submit(s, false); 1629 } 1630 } 1631 1632 static void sci_free_dma(struct uart_port *port) 1633 { 1634 struct sci_port *s = to_sci_port(port); 1635 1636 if (s->chan_tx_saved) 1637 sci_dma_tx_release(s); 1638 if (s->chan_rx_saved) 1639 sci_dma_rx_release(s); 1640 } 1641 1642 static void sci_flush_buffer(struct uart_port *port) 1643 { 1644 /* 1645 * In uart_flush_buffer(), the xmit circular buffer has just been 1646 * cleared, so we have to reset tx_dma_len accordingly. 1647 */ 1648 to_sci_port(port)->tx_dma_len = 0; 1649 } 1650 #else /* !CONFIG_SERIAL_SH_SCI_DMA */ 1651 static inline void sci_request_dma(struct uart_port *port) 1652 { 1653 } 1654 1655 static inline void sci_free_dma(struct uart_port *port) 1656 { 1657 } 1658 1659 #define sci_flush_buffer NULL 1660 #endif /* !CONFIG_SERIAL_SH_SCI_DMA */ 1661 1662 static irqreturn_t sci_rx_interrupt(int irq, void *ptr) 1663 { 1664 struct uart_port *port = ptr; 1665 struct sci_port *s = to_sci_port(port); 1666 1667 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1668 if (s->chan_rx) { 1669 u16 scr = serial_port_in(port, SCSCR); 1670 u16 ssr = serial_port_in(port, SCxSR); 1671 1672 /* Disable future Rx interrupts */ 1673 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1674 disable_irq_nosync(irq); 1675 scr |= SCSCR_RDRQE; 1676 } else { 1677 if (sci_dma_rx_submit(s, false) < 0) 1678 goto handle_pio; 1679 1680 scr &= ~SCSCR_RIE; 1681 } 1682 serial_port_out(port, SCSCR, scr); 1683 /* Clear current interrupt */ 1684 serial_port_out(port, SCxSR, 1685 ssr & ~(SCIF_DR | SCxSR_RDxF(port))); 1686 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n", 1687 jiffies, s->rx_timeout); 1688 start_hrtimer_us(&s->rx_timer, s->rx_timeout); 1689 1690 return IRQ_HANDLED; 1691 } 1692 1693 handle_pio: 1694 #endif 1695 1696 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) { 1697 if (!scif_rtrg_enabled(port)) 1698 scif_set_rtrg(port, s->rx_trigger); 1699 1700 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP( 1701 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000)); 1702 } 1703 1704 /* I think sci_receive_chars has to be called irrespective 1705 * of whether the I_IXOFF is set, otherwise, how is the interrupt 1706 * to be disabled? 1707 */ 1708 sci_receive_chars(port); 1709 1710 return IRQ_HANDLED; 1711 } 1712 1713 static irqreturn_t sci_tx_interrupt(int irq, void *ptr) 1714 { 1715 struct uart_port *port = ptr; 1716 unsigned long flags; 1717 1718 spin_lock_irqsave(&port->lock, flags); 1719 sci_transmit_chars(port); 1720 spin_unlock_irqrestore(&port->lock, flags); 1721 1722 return IRQ_HANDLED; 1723 } 1724 1725 static irqreturn_t sci_br_interrupt(int irq, void *ptr) 1726 { 1727 struct uart_port *port = ptr; 1728 1729 /* Handle BREAKs */ 1730 sci_handle_breaks(port); 1731 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port)); 1732 1733 return IRQ_HANDLED; 1734 } 1735 1736 static irqreturn_t sci_er_interrupt(int irq, void *ptr) 1737 { 1738 struct uart_port *port = ptr; 1739 struct sci_port *s = to_sci_port(port); 1740 1741 if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) { 1742 /* Break and Error interrupts are muxed */ 1743 unsigned short ssr_status = serial_port_in(port, SCxSR); 1744 1745 /* Break Interrupt */ 1746 if (ssr_status & SCxSR_BRK(port)) 1747 sci_br_interrupt(irq, ptr); 1748 1749 /* Break only? */ 1750 if (!(ssr_status & SCxSR_ERRORS(port))) 1751 return IRQ_HANDLED; 1752 } 1753 1754 /* Handle errors */ 1755 if (port->type == PORT_SCI) { 1756 if (sci_handle_errors(port)) { 1757 /* discard character in rx buffer */ 1758 serial_port_in(port, SCxSR); 1759 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 1760 } 1761 } else { 1762 sci_handle_fifo_overrun(port); 1763 if (!s->chan_rx) 1764 sci_receive_chars(port); 1765 } 1766 1767 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); 1768 1769 /* Kick the transmission */ 1770 if (!s->chan_tx) 1771 sci_tx_interrupt(irq, ptr); 1772 1773 return IRQ_HANDLED; 1774 } 1775 1776 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) 1777 { 1778 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0; 1779 struct uart_port *port = ptr; 1780 struct sci_port *s = to_sci_port(port); 1781 irqreturn_t ret = IRQ_NONE; 1782 1783 ssr_status = serial_port_in(port, SCxSR); 1784 scr_status = serial_port_in(port, SCSCR); 1785 if (s->params->overrun_reg == SCxSR) 1786 orer_status = ssr_status; 1787 else if (sci_getreg(port, s->params->overrun_reg)->size) 1788 orer_status = serial_port_in(port, s->params->overrun_reg); 1789 1790 err_enabled = scr_status & port_rx_irq_mask(port); 1791 1792 /* Tx Interrupt */ 1793 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) && 1794 !s->chan_tx) 1795 ret = sci_tx_interrupt(irq, ptr); 1796 1797 /* 1798 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF / 1799 * DR flags 1800 */ 1801 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) && 1802 (scr_status & SCSCR_RIE)) 1803 ret = sci_rx_interrupt(irq, ptr); 1804 1805 /* Error Interrupt */ 1806 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled) 1807 ret = sci_er_interrupt(irq, ptr); 1808 1809 /* Break Interrupt */ 1810 if ((ssr_status & SCxSR_BRK(port)) && err_enabled) 1811 ret = sci_br_interrupt(irq, ptr); 1812 1813 /* Overrun Interrupt */ 1814 if (orer_status & s->params->overrun_mask) { 1815 sci_handle_fifo_overrun(port); 1816 ret = IRQ_HANDLED; 1817 } 1818 1819 return ret; 1820 } 1821 1822 static const struct sci_irq_desc { 1823 const char *desc; 1824 irq_handler_t handler; 1825 } sci_irq_desc[] = { 1826 /* 1827 * Split out handlers, the default case. 1828 */ 1829 [SCIx_ERI_IRQ] = { 1830 .desc = "rx err", 1831 .handler = sci_er_interrupt, 1832 }, 1833 1834 [SCIx_RXI_IRQ] = { 1835 .desc = "rx full", 1836 .handler = sci_rx_interrupt, 1837 }, 1838 1839 [SCIx_TXI_IRQ] = { 1840 .desc = "tx empty", 1841 .handler = sci_tx_interrupt, 1842 }, 1843 1844 [SCIx_BRI_IRQ] = { 1845 .desc = "break", 1846 .handler = sci_br_interrupt, 1847 }, 1848 1849 [SCIx_DRI_IRQ] = { 1850 .desc = "rx ready", 1851 .handler = sci_rx_interrupt, 1852 }, 1853 1854 [SCIx_TEI_IRQ] = { 1855 .desc = "tx end", 1856 .handler = sci_tx_interrupt, 1857 }, 1858 1859 /* 1860 * Special muxed handler. 1861 */ 1862 [SCIx_MUX_IRQ] = { 1863 .desc = "mux", 1864 .handler = sci_mpxed_interrupt, 1865 }, 1866 }; 1867 1868 static int sci_request_irq(struct sci_port *port) 1869 { 1870 struct uart_port *up = &port->port; 1871 int i, j, w, ret = 0; 1872 1873 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) { 1874 const struct sci_irq_desc *desc; 1875 int irq; 1876 1877 /* Check if already registered (muxed) */ 1878 for (w = 0; w < i; w++) 1879 if (port->irqs[w] == port->irqs[i]) 1880 w = i + 1; 1881 if (w > i) 1882 continue; 1883 1884 if (SCIx_IRQ_IS_MUXED(port)) { 1885 i = SCIx_MUX_IRQ; 1886 irq = up->irq; 1887 } else { 1888 irq = port->irqs[i]; 1889 1890 /* 1891 * Certain port types won't support all of the 1892 * available interrupt sources. 1893 */ 1894 if (unlikely(irq < 0)) 1895 continue; 1896 } 1897 1898 desc = sci_irq_desc + i; 1899 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s", 1900 dev_name(up->dev), desc->desc); 1901 if (!port->irqstr[j]) { 1902 ret = -ENOMEM; 1903 goto out_nomem; 1904 } 1905 1906 ret = request_irq(irq, desc->handler, up->irqflags, 1907 port->irqstr[j], port); 1908 if (unlikely(ret)) { 1909 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc); 1910 goto out_noirq; 1911 } 1912 } 1913 1914 return 0; 1915 1916 out_noirq: 1917 while (--i >= 0) 1918 free_irq(port->irqs[i], port); 1919 1920 out_nomem: 1921 while (--j >= 0) 1922 kfree(port->irqstr[j]); 1923 1924 return ret; 1925 } 1926 1927 static void sci_free_irq(struct sci_port *port) 1928 { 1929 int i, j; 1930 1931 /* 1932 * Intentionally in reverse order so we iterate over the muxed 1933 * IRQ first. 1934 */ 1935 for (i = 0; i < SCIx_NR_IRQS; i++) { 1936 int irq = port->irqs[i]; 1937 1938 /* 1939 * Certain port types won't support all of the available 1940 * interrupt sources. 1941 */ 1942 if (unlikely(irq < 0)) 1943 continue; 1944 1945 /* Check if already freed (irq was muxed) */ 1946 for (j = 0; j < i; j++) 1947 if (port->irqs[j] == irq) 1948 j = i + 1; 1949 if (j > i) 1950 continue; 1951 1952 free_irq(port->irqs[i], port); 1953 kfree(port->irqstr[i]); 1954 1955 if (SCIx_IRQ_IS_MUXED(port)) { 1956 /* If there's only one IRQ, we're done. */ 1957 return; 1958 } 1959 } 1960 } 1961 1962 static unsigned int sci_tx_empty(struct uart_port *port) 1963 { 1964 unsigned short status = serial_port_in(port, SCxSR); 1965 unsigned short in_tx_fifo = sci_txfill(port); 1966 1967 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0; 1968 } 1969 1970 static void sci_set_rts(struct uart_port *port, bool state) 1971 { 1972 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1973 u16 data = serial_port_in(port, SCPDR); 1974 1975 /* Active low */ 1976 if (state) 1977 data &= ~SCPDR_RTSD; 1978 else 1979 data |= SCPDR_RTSD; 1980 serial_port_out(port, SCPDR, data); 1981 1982 /* RTS# is output */ 1983 serial_port_out(port, SCPCR, 1984 serial_port_in(port, SCPCR) | SCPCR_RTSC); 1985 } else if (sci_getreg(port, SCSPTR)->size) { 1986 u16 ctrl = serial_port_in(port, SCSPTR); 1987 1988 /* Active low */ 1989 if (state) 1990 ctrl &= ~SCSPTR_RTSDT; 1991 else 1992 ctrl |= SCSPTR_RTSDT; 1993 serial_port_out(port, SCSPTR, ctrl); 1994 } 1995 } 1996 1997 static bool sci_get_cts(struct uart_port *port) 1998 { 1999 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 2000 /* Active low */ 2001 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD); 2002 } else if (sci_getreg(port, SCSPTR)->size) { 2003 /* Active low */ 2004 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT); 2005 } 2006 2007 return true; 2008 } 2009 2010 /* 2011 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally 2012 * CTS/RTS is supported in hardware by at least one port and controlled 2013 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently 2014 * handled via the ->init_pins() op, which is a bit of a one-way street, 2015 * lacking any ability to defer pin control -- this will later be 2016 * converted over to the GPIO framework). 2017 * 2018 * Other modes (such as loopback) are supported generically on certain 2019 * port types, but not others. For these it's sufficient to test for the 2020 * existence of the support register and simply ignore the port type. 2021 */ 2022 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) 2023 { 2024 struct sci_port *s = to_sci_port(port); 2025 2026 if (mctrl & TIOCM_LOOP) { 2027 const struct plat_sci_reg *reg; 2028 2029 /* 2030 * Standard loopback mode for SCFCR ports. 2031 */ 2032 reg = sci_getreg(port, SCFCR); 2033 if (reg->size) 2034 serial_port_out(port, SCFCR, 2035 serial_port_in(port, SCFCR) | 2036 SCFCR_LOOP); 2037 } 2038 2039 mctrl_gpio_set(s->gpios, mctrl); 2040 2041 if (!s->has_rtscts) 2042 return; 2043 2044 if (!(mctrl & TIOCM_RTS)) { 2045 /* Disable Auto RTS */ 2046 serial_port_out(port, SCFCR, 2047 serial_port_in(port, SCFCR) & ~SCFCR_MCE); 2048 2049 /* Clear RTS */ 2050 sci_set_rts(port, 0); 2051 } else if (s->autorts) { 2052 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 2053 /* Enable RTS# pin function */ 2054 serial_port_out(port, SCPCR, 2055 serial_port_in(port, SCPCR) & ~SCPCR_RTSC); 2056 } 2057 2058 /* Enable Auto RTS */ 2059 serial_port_out(port, SCFCR, 2060 serial_port_in(port, SCFCR) | SCFCR_MCE); 2061 } else { 2062 /* Set RTS */ 2063 sci_set_rts(port, 1); 2064 } 2065 } 2066 2067 static unsigned int sci_get_mctrl(struct uart_port *port) 2068 { 2069 struct sci_port *s = to_sci_port(port); 2070 struct mctrl_gpios *gpios = s->gpios; 2071 unsigned int mctrl = 0; 2072 2073 mctrl_gpio_get(gpios, &mctrl); 2074 2075 /* 2076 * CTS/RTS is handled in hardware when supported, while nothing 2077 * else is wired up. 2078 */ 2079 if (s->autorts) { 2080 if (sci_get_cts(port)) 2081 mctrl |= TIOCM_CTS; 2082 } else if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS))) { 2083 mctrl |= TIOCM_CTS; 2084 } 2085 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR))) 2086 mctrl |= TIOCM_DSR; 2087 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD))) 2088 mctrl |= TIOCM_CAR; 2089 2090 return mctrl; 2091 } 2092 2093 static void sci_enable_ms(struct uart_port *port) 2094 { 2095 mctrl_gpio_enable_ms(to_sci_port(port)->gpios); 2096 } 2097 2098 static void sci_break_ctl(struct uart_port *port, int break_state) 2099 { 2100 unsigned short scscr, scsptr; 2101 unsigned long flags; 2102 2103 /* check wheter the port has SCSPTR */ 2104 if (!sci_getreg(port, SCSPTR)->size) { 2105 /* 2106 * Not supported by hardware. Most parts couple break and rx 2107 * interrupts together, with break detection always enabled. 2108 */ 2109 return; 2110 } 2111 2112 spin_lock_irqsave(&port->lock, flags); 2113 scsptr = serial_port_in(port, SCSPTR); 2114 scscr = serial_port_in(port, SCSCR); 2115 2116 if (break_state == -1) { 2117 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT; 2118 scscr &= ~SCSCR_TE; 2119 } else { 2120 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO; 2121 scscr |= SCSCR_TE; 2122 } 2123 2124 serial_port_out(port, SCSPTR, scsptr); 2125 serial_port_out(port, SCSCR, scscr); 2126 spin_unlock_irqrestore(&port->lock, flags); 2127 } 2128 2129 static int sci_startup(struct uart_port *port) 2130 { 2131 struct sci_port *s = to_sci_port(port); 2132 int ret; 2133 2134 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 2135 2136 sci_request_dma(port); 2137 2138 ret = sci_request_irq(s); 2139 if (unlikely(ret < 0)) { 2140 sci_free_dma(port); 2141 return ret; 2142 } 2143 2144 return 0; 2145 } 2146 2147 static void sci_shutdown(struct uart_port *port) 2148 { 2149 struct sci_port *s = to_sci_port(port); 2150 unsigned long flags; 2151 u16 scr; 2152 2153 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 2154 2155 s->autorts = false; 2156 mctrl_gpio_disable_ms(to_sci_port(port)->gpios); 2157 2158 spin_lock_irqsave(&port->lock, flags); 2159 sci_stop_rx(port); 2160 sci_stop_tx(port); 2161 /* 2162 * Stop RX and TX, disable related interrupts, keep clock source 2163 * and HSCIF TOT bits 2164 */ 2165 scr = serial_port_in(port, SCSCR); 2166 serial_port_out(port, SCSCR, scr & 2167 (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot)); 2168 spin_unlock_irqrestore(&port->lock, flags); 2169 2170 #ifdef CONFIG_SERIAL_SH_SCI_DMA 2171 if (s->chan_rx_saved) { 2172 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__, 2173 port->line); 2174 hrtimer_cancel(&s->rx_timer); 2175 } 2176 #endif 2177 2178 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) 2179 del_timer_sync(&s->rx_fifo_timer); 2180 sci_free_irq(s); 2181 sci_free_dma(port); 2182 } 2183 2184 static int sci_sck_calc(struct sci_port *s, unsigned int bps, 2185 unsigned int *srr) 2186 { 2187 unsigned long freq = s->clk_rates[SCI_SCK]; 2188 int err, min_err = INT_MAX; 2189 unsigned int sr; 2190 2191 if (s->port.type != PORT_HSCIF) 2192 freq *= 2; 2193 2194 for_each_sr(sr, s) { 2195 err = DIV_ROUND_CLOSEST(freq, sr) - bps; 2196 if (abs(err) >= abs(min_err)) 2197 continue; 2198 2199 min_err = err; 2200 *srr = sr - 1; 2201 2202 if (!err) 2203 break; 2204 } 2205 2206 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err, 2207 *srr + 1); 2208 return min_err; 2209 } 2210 2211 static int sci_brg_calc(struct sci_port *s, unsigned int bps, 2212 unsigned long freq, unsigned int *dlr, 2213 unsigned int *srr) 2214 { 2215 int err, min_err = INT_MAX; 2216 unsigned int sr, dl; 2217 2218 if (s->port.type != PORT_HSCIF) 2219 freq *= 2; 2220 2221 for_each_sr(sr, s) { 2222 dl = DIV_ROUND_CLOSEST(freq, sr * bps); 2223 dl = clamp(dl, 1U, 65535U); 2224 2225 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps; 2226 if (abs(err) >= abs(min_err)) 2227 continue; 2228 2229 min_err = err; 2230 *dlr = dl; 2231 *srr = sr - 1; 2232 2233 if (!err) 2234 break; 2235 } 2236 2237 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps, 2238 min_err, *dlr, *srr + 1); 2239 return min_err; 2240 } 2241 2242 /* calculate sample rate, BRR, and clock select */ 2243 static int sci_scbrr_calc(struct sci_port *s, unsigned int bps, 2244 unsigned int *brr, unsigned int *srr, 2245 unsigned int *cks) 2246 { 2247 unsigned long freq = s->clk_rates[SCI_FCK]; 2248 unsigned int sr, br, prediv, scrate, c; 2249 int err, min_err = INT_MAX; 2250 2251 if (s->port.type != PORT_HSCIF) 2252 freq *= 2; 2253 2254 /* 2255 * Find the combination of sample rate and clock select with the 2256 * smallest deviation from the desired baud rate. 2257 * Prefer high sample rates to maximise the receive margin. 2258 * 2259 * M: Receive margin (%) 2260 * N: Ratio of bit rate to clock (N = sampling rate) 2261 * D: Clock duty (D = 0 to 1.0) 2262 * L: Frame length (L = 9 to 12) 2263 * F: Absolute value of clock frequency deviation 2264 * 2265 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) - 2266 * (|D - 0.5| / N * (1 + F))| 2267 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation. 2268 */ 2269 for_each_sr(sr, s) { 2270 for (c = 0; c <= 3; c++) { 2271 /* integerized formulas from HSCIF documentation */ 2272 prediv = sr * (1 << (2 * c + 1)); 2273 2274 /* 2275 * We need to calculate: 2276 * 2277 * br = freq / (prediv * bps) clamped to [1..256] 2278 * err = freq / (br * prediv) - bps 2279 * 2280 * Watch out for overflow when calculating the desired 2281 * sampling clock rate! 2282 */ 2283 if (bps > UINT_MAX / prediv) 2284 break; 2285 2286 scrate = prediv * bps; 2287 br = DIV_ROUND_CLOSEST(freq, scrate); 2288 br = clamp(br, 1U, 256U); 2289 2290 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps; 2291 if (abs(err) >= abs(min_err)) 2292 continue; 2293 2294 min_err = err; 2295 *brr = br - 1; 2296 *srr = sr - 1; 2297 *cks = c; 2298 2299 if (!err) 2300 goto found; 2301 } 2302 } 2303 2304 found: 2305 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps, 2306 min_err, *brr, *srr + 1, *cks); 2307 return min_err; 2308 } 2309 2310 static void sci_reset(struct uart_port *port) 2311 { 2312 const struct plat_sci_reg *reg; 2313 unsigned int status; 2314 struct sci_port *s = to_sci_port(port); 2315 2316 serial_port_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */ 2317 2318 reg = sci_getreg(port, SCFCR); 2319 if (reg->size) 2320 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); 2321 2322 sci_clear_SCxSR(port, 2323 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) & 2324 SCxSR_BREAK_CLEAR(port)); 2325 if (sci_getreg(port, SCLSR)->size) { 2326 status = serial_port_in(port, SCLSR); 2327 status &= ~(SCLSR_TO | SCLSR_ORER); 2328 serial_port_out(port, SCLSR, status); 2329 } 2330 2331 if (s->rx_trigger > 1) { 2332 if (s->rx_fifo_timeout) { 2333 scif_set_rtrg(port, 1); 2334 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0); 2335 } else { 2336 if (port->type == PORT_SCIFA || 2337 port->type == PORT_SCIFB) 2338 scif_set_rtrg(port, 1); 2339 else 2340 scif_set_rtrg(port, s->rx_trigger); 2341 } 2342 } 2343 } 2344 2345 static void sci_set_termios(struct uart_port *port, struct ktermios *termios, 2346 struct ktermios *old) 2347 { 2348 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits; 2349 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0; 2350 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0; 2351 struct sci_port *s = to_sci_port(port); 2352 const struct plat_sci_reg *reg; 2353 int min_err = INT_MAX, err; 2354 unsigned long max_freq = 0; 2355 int best_clk = -1; 2356 unsigned long flags; 2357 2358 if ((termios->c_cflag & CSIZE) == CS7) 2359 smr_val |= SCSMR_CHR; 2360 if (termios->c_cflag & PARENB) 2361 smr_val |= SCSMR_PE; 2362 if (termios->c_cflag & PARODD) 2363 smr_val |= SCSMR_PE | SCSMR_ODD; 2364 if (termios->c_cflag & CSTOPB) 2365 smr_val |= SCSMR_STOP; 2366 2367 /* 2368 * earlyprintk comes here early on with port->uartclk set to zero. 2369 * the clock framework is not up and running at this point so here 2370 * we assume that 115200 is the maximum baud rate. please note that 2371 * the baud rate is not programmed during earlyprintk - it is assumed 2372 * that the previous boot loader has enabled required clocks and 2373 * setup the baud rate generator hardware for us already. 2374 */ 2375 if (!port->uartclk) { 2376 baud = uart_get_baud_rate(port, termios, old, 0, 115200); 2377 goto done; 2378 } 2379 2380 for (i = 0; i < SCI_NUM_CLKS; i++) 2381 max_freq = max(max_freq, s->clk_rates[i]); 2382 2383 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s)); 2384 if (!baud) 2385 goto done; 2386 2387 /* 2388 * There can be multiple sources for the sampling clock. Find the one 2389 * that gives us the smallest deviation from the desired baud rate. 2390 */ 2391 2392 /* Optional Undivided External Clock */ 2393 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA && 2394 port->type != PORT_SCIFB) { 2395 err = sci_sck_calc(s, baud, &srr1); 2396 if (abs(err) < abs(min_err)) { 2397 best_clk = SCI_SCK; 2398 scr_val = SCSCR_CKE1; 2399 sccks = SCCKS_CKS; 2400 min_err = err; 2401 srr = srr1; 2402 if (!err) 2403 goto done; 2404 } 2405 } 2406 2407 /* Optional BRG Frequency Divided External Clock */ 2408 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) { 2409 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1, 2410 &srr1); 2411 if (abs(err) < abs(min_err)) { 2412 best_clk = SCI_SCIF_CLK; 2413 scr_val = SCSCR_CKE1; 2414 sccks = 0; 2415 min_err = err; 2416 dl = dl1; 2417 srr = srr1; 2418 if (!err) 2419 goto done; 2420 } 2421 } 2422 2423 /* Optional BRG Frequency Divided Internal Clock */ 2424 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) { 2425 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1, 2426 &srr1); 2427 if (abs(err) < abs(min_err)) { 2428 best_clk = SCI_BRG_INT; 2429 scr_val = SCSCR_CKE1; 2430 sccks = SCCKS_XIN; 2431 min_err = err; 2432 dl = dl1; 2433 srr = srr1; 2434 if (!min_err) 2435 goto done; 2436 } 2437 } 2438 2439 /* Divided Functional Clock using standard Bit Rate Register */ 2440 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1); 2441 if (abs(err) < abs(min_err)) { 2442 best_clk = SCI_FCK; 2443 scr_val = 0; 2444 min_err = err; 2445 brr = brr1; 2446 srr = srr1; 2447 cks = cks1; 2448 } 2449 2450 done: 2451 if (best_clk >= 0) 2452 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n", 2453 s->clks[best_clk], baud, min_err); 2454 2455 sci_port_enable(s); 2456 2457 /* 2458 * Program the optional External Baud Rate Generator (BRG) first. 2459 * It controls the mux to select (H)SCK or frequency divided clock. 2460 */ 2461 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) { 2462 serial_port_out(port, SCDL, dl); 2463 serial_port_out(port, SCCKS, sccks); 2464 } 2465 2466 spin_lock_irqsave(&port->lock, flags); 2467 2468 sci_reset(port); 2469 2470 uart_update_timeout(port, termios->c_cflag, baud); 2471 2472 /* byte size and parity */ 2473 switch (termios->c_cflag & CSIZE) { 2474 case CS5: 2475 bits = 7; 2476 break; 2477 case CS6: 2478 bits = 8; 2479 break; 2480 case CS7: 2481 bits = 9; 2482 break; 2483 default: 2484 bits = 10; 2485 break; 2486 } 2487 2488 if (termios->c_cflag & CSTOPB) 2489 bits++; 2490 if (termios->c_cflag & PARENB) 2491 bits++; 2492 2493 if (best_clk >= 0) { 2494 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 2495 switch (srr + 1) { 2496 case 5: smr_val |= SCSMR_SRC_5; break; 2497 case 7: smr_val |= SCSMR_SRC_7; break; 2498 case 11: smr_val |= SCSMR_SRC_11; break; 2499 case 13: smr_val |= SCSMR_SRC_13; break; 2500 case 16: smr_val |= SCSMR_SRC_16; break; 2501 case 17: smr_val |= SCSMR_SRC_17; break; 2502 case 19: smr_val |= SCSMR_SRC_19; break; 2503 case 27: smr_val |= SCSMR_SRC_27; break; 2504 } 2505 smr_val |= cks; 2506 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); 2507 serial_port_out(port, SCSMR, smr_val); 2508 serial_port_out(port, SCBRR, brr); 2509 if (sci_getreg(port, HSSRR)->size) { 2510 unsigned int hssrr = srr | HSCIF_SRE; 2511 /* Calculate deviation from intended rate at the 2512 * center of the last stop bit in sampling clocks. 2513 */ 2514 int last_stop = bits * 2 - 1; 2515 int deviation = DIV_ROUND_CLOSEST(min_err * last_stop * 2516 (int)(srr + 1), 2517 2 * (int)baud); 2518 2519 if (abs(deviation) >= 2) { 2520 /* At least two sampling clocks off at the 2521 * last stop bit; we can increase the error 2522 * margin by shifting the sampling point. 2523 */ 2524 int shift = clamp(deviation / 2, -8, 7); 2525 2526 hssrr |= (shift << HSCIF_SRHP_SHIFT) & 2527 HSCIF_SRHP_MASK; 2528 hssrr |= HSCIF_SRDE; 2529 } 2530 serial_port_out(port, HSSRR, hssrr); 2531 } 2532 2533 /* Wait one bit interval */ 2534 udelay((1000000 + (baud - 1)) / baud); 2535 } else { 2536 /* Don't touch the bit rate configuration */ 2537 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0); 2538 smr_val |= serial_port_in(port, SCSMR) & 2539 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS); 2540 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); 2541 serial_port_out(port, SCSMR, smr_val); 2542 } 2543 2544 sci_init_pins(port, termios->c_cflag); 2545 2546 port->status &= ~UPSTAT_AUTOCTS; 2547 s->autorts = false; 2548 reg = sci_getreg(port, SCFCR); 2549 if (reg->size) { 2550 unsigned short ctrl = serial_port_in(port, SCFCR); 2551 2552 if ((port->flags & UPF_HARD_FLOW) && 2553 (termios->c_cflag & CRTSCTS)) { 2554 /* There is no CTS interrupt to restart the hardware */ 2555 port->status |= UPSTAT_AUTOCTS; 2556 /* MCE is enabled when RTS is raised */ 2557 s->autorts = true; 2558 } 2559 2560 /* 2561 * As we've done a sci_reset() above, ensure we don't 2562 * interfere with the FIFOs while toggling MCE. As the 2563 * reset values could still be set, simply mask them out. 2564 */ 2565 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST); 2566 2567 serial_port_out(port, SCFCR, ctrl); 2568 } 2569 if (port->flags & UPF_HARD_FLOW) { 2570 /* Refresh (Auto) RTS */ 2571 sci_set_mctrl(port, port->mctrl); 2572 } 2573 2574 scr_val |= SCSCR_RE | SCSCR_TE | 2575 (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)); 2576 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); 2577 if ((srr + 1 == 5) && 2578 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) { 2579 /* 2580 * In asynchronous mode, when the sampling rate is 1/5, first 2581 * received data may become invalid on some SCIFA and SCIFB. 2582 * To avoid this problem wait more than 1 serial data time (1 2583 * bit time x serial data number) after setting SCSCR.RE = 1. 2584 */ 2585 udelay(DIV_ROUND_UP(10 * 1000000, baud)); 2586 } 2587 2588 /* 2589 * Calculate delay for 2 DMA buffers (4 FIFO). 2590 * See serial_core.c::uart_update_timeout(). 2591 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above 2592 * function calculates 1 jiffie for the data plus 5 jiffies for the 2593 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA 2594 * buffers (4 FIFO sizes), but when performing a faster transfer, the 2595 * value obtained by this formula is too small. Therefore, if the value 2596 * is smaller than 20ms, use 20ms as the timeout value for DMA. 2597 */ 2598 s->rx_frame = (10000 * bits) / (baud / 100); 2599 #ifdef CONFIG_SERIAL_SH_SCI_DMA 2600 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame; 2601 if (s->rx_timeout < 20) 2602 s->rx_timeout = 20; 2603 #endif 2604 2605 if ((termios->c_cflag & CREAD) != 0) 2606 sci_start_rx(port); 2607 2608 spin_unlock_irqrestore(&port->lock, flags); 2609 2610 sci_port_disable(s); 2611 2612 if (UART_ENABLE_MS(port, termios->c_cflag)) 2613 sci_enable_ms(port); 2614 } 2615 2616 static void sci_pm(struct uart_port *port, unsigned int state, 2617 unsigned int oldstate) 2618 { 2619 struct sci_port *sci_port = to_sci_port(port); 2620 2621 switch (state) { 2622 case UART_PM_STATE_OFF: 2623 sci_port_disable(sci_port); 2624 break; 2625 default: 2626 sci_port_enable(sci_port); 2627 break; 2628 } 2629 } 2630 2631 static const char *sci_type(struct uart_port *port) 2632 { 2633 switch (port->type) { 2634 case PORT_IRDA: 2635 return "irda"; 2636 case PORT_SCI: 2637 return "sci"; 2638 case PORT_SCIF: 2639 return "scif"; 2640 case PORT_SCIFA: 2641 return "scifa"; 2642 case PORT_SCIFB: 2643 return "scifb"; 2644 case PORT_HSCIF: 2645 return "hscif"; 2646 } 2647 2648 return NULL; 2649 } 2650 2651 static int sci_remap_port(struct uart_port *port) 2652 { 2653 struct sci_port *sport = to_sci_port(port); 2654 2655 /* 2656 * Nothing to do if there's already an established membase. 2657 */ 2658 if (port->membase) 2659 return 0; 2660 2661 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { 2662 port->membase = ioremap_nocache(port->mapbase, sport->reg_size); 2663 if (unlikely(!port->membase)) { 2664 dev_err(port->dev, "can't remap port#%d\n", port->line); 2665 return -ENXIO; 2666 } 2667 } else { 2668 /* 2669 * For the simple (and majority of) cases where we don't 2670 * need to do any remapping, just cast the cookie 2671 * directly. 2672 */ 2673 port->membase = (void __iomem *)(uintptr_t)port->mapbase; 2674 } 2675 2676 return 0; 2677 } 2678 2679 static void sci_release_port(struct uart_port *port) 2680 { 2681 struct sci_port *sport = to_sci_port(port); 2682 2683 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { 2684 iounmap(port->membase); 2685 port->membase = NULL; 2686 } 2687 2688 release_mem_region(port->mapbase, sport->reg_size); 2689 } 2690 2691 static int sci_request_port(struct uart_port *port) 2692 { 2693 struct resource *res; 2694 struct sci_port *sport = to_sci_port(port); 2695 int ret; 2696 2697 res = request_mem_region(port->mapbase, sport->reg_size, 2698 dev_name(port->dev)); 2699 if (unlikely(res == NULL)) { 2700 dev_err(port->dev, "request_mem_region failed."); 2701 return -EBUSY; 2702 } 2703 2704 ret = sci_remap_port(port); 2705 if (unlikely(ret != 0)) { 2706 release_resource(res); 2707 return ret; 2708 } 2709 2710 return 0; 2711 } 2712 2713 static void sci_config_port(struct uart_port *port, int flags) 2714 { 2715 if (flags & UART_CONFIG_TYPE) { 2716 struct sci_port *sport = to_sci_port(port); 2717 2718 port->type = sport->cfg->type; 2719 sci_request_port(port); 2720 } 2721 } 2722 2723 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser) 2724 { 2725 if (ser->baud_base < 2400) 2726 /* No paper tape reader for Mitch.. */ 2727 return -EINVAL; 2728 2729 return 0; 2730 } 2731 2732 static const struct uart_ops sci_uart_ops = { 2733 .tx_empty = sci_tx_empty, 2734 .set_mctrl = sci_set_mctrl, 2735 .get_mctrl = sci_get_mctrl, 2736 .start_tx = sci_start_tx, 2737 .stop_tx = sci_stop_tx, 2738 .stop_rx = sci_stop_rx, 2739 .enable_ms = sci_enable_ms, 2740 .break_ctl = sci_break_ctl, 2741 .startup = sci_startup, 2742 .shutdown = sci_shutdown, 2743 .flush_buffer = sci_flush_buffer, 2744 .set_termios = sci_set_termios, 2745 .pm = sci_pm, 2746 .type = sci_type, 2747 .release_port = sci_release_port, 2748 .request_port = sci_request_port, 2749 .config_port = sci_config_port, 2750 .verify_port = sci_verify_port, 2751 #ifdef CONFIG_CONSOLE_POLL 2752 .poll_get_char = sci_poll_get_char, 2753 .poll_put_char = sci_poll_put_char, 2754 #endif 2755 }; 2756 2757 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev) 2758 { 2759 const char *clk_names[] = { 2760 [SCI_FCK] = "fck", 2761 [SCI_SCK] = "sck", 2762 [SCI_BRG_INT] = "brg_int", 2763 [SCI_SCIF_CLK] = "scif_clk", 2764 }; 2765 struct clk *clk; 2766 unsigned int i; 2767 2768 if (sci_port->cfg->type == PORT_HSCIF) 2769 clk_names[SCI_SCK] = "hsck"; 2770 2771 for (i = 0; i < SCI_NUM_CLKS; i++) { 2772 clk = devm_clk_get(dev, clk_names[i]); 2773 if (PTR_ERR(clk) == -EPROBE_DEFER) 2774 return -EPROBE_DEFER; 2775 2776 if (IS_ERR(clk) && i == SCI_FCK) { 2777 /* 2778 * "fck" used to be called "sci_ick", and we need to 2779 * maintain DT backward compatibility. 2780 */ 2781 clk = devm_clk_get(dev, "sci_ick"); 2782 if (PTR_ERR(clk) == -EPROBE_DEFER) 2783 return -EPROBE_DEFER; 2784 2785 if (!IS_ERR(clk)) 2786 goto found; 2787 2788 /* 2789 * Not all SH platforms declare a clock lookup entry 2790 * for SCI devices, in which case we need to get the 2791 * global "peripheral_clk" clock. 2792 */ 2793 clk = devm_clk_get(dev, "peripheral_clk"); 2794 if (!IS_ERR(clk)) 2795 goto found; 2796 2797 dev_err(dev, "failed to get %s (%ld)\n", clk_names[i], 2798 PTR_ERR(clk)); 2799 return PTR_ERR(clk); 2800 } 2801 2802 found: 2803 if (IS_ERR(clk)) 2804 dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i], 2805 PTR_ERR(clk)); 2806 else 2807 dev_dbg(dev, "clk %s is %pC rate %lu\n", clk_names[i], 2808 clk, clk_get_rate(clk)); 2809 sci_port->clks[i] = IS_ERR(clk) ? NULL : clk; 2810 } 2811 return 0; 2812 } 2813 2814 static const struct sci_port_params * 2815 sci_probe_regmap(const struct plat_sci_port *cfg) 2816 { 2817 unsigned int regtype; 2818 2819 if (cfg->regtype != SCIx_PROBE_REGTYPE) 2820 return &sci_port_params[cfg->regtype]; 2821 2822 switch (cfg->type) { 2823 case PORT_SCI: 2824 regtype = SCIx_SCI_REGTYPE; 2825 break; 2826 case PORT_IRDA: 2827 regtype = SCIx_IRDA_REGTYPE; 2828 break; 2829 case PORT_SCIFA: 2830 regtype = SCIx_SCIFA_REGTYPE; 2831 break; 2832 case PORT_SCIFB: 2833 regtype = SCIx_SCIFB_REGTYPE; 2834 break; 2835 case PORT_SCIF: 2836 /* 2837 * The SH-4 is a bit of a misnomer here, although that's 2838 * where this particular port layout originated. This 2839 * configuration (or some slight variation thereof) 2840 * remains the dominant model for all SCIFs. 2841 */ 2842 regtype = SCIx_SH4_SCIF_REGTYPE; 2843 break; 2844 case PORT_HSCIF: 2845 regtype = SCIx_HSCIF_REGTYPE; 2846 break; 2847 default: 2848 pr_err("Can't probe register map for given port\n"); 2849 return NULL; 2850 } 2851 2852 return &sci_port_params[regtype]; 2853 } 2854 2855 static int sci_init_single(struct platform_device *dev, 2856 struct sci_port *sci_port, unsigned int index, 2857 const struct plat_sci_port *p, bool early) 2858 { 2859 struct uart_port *port = &sci_port->port; 2860 const struct resource *res; 2861 unsigned int i; 2862 int ret; 2863 2864 sci_port->cfg = p; 2865 2866 port->ops = &sci_uart_ops; 2867 port->iotype = UPIO_MEM; 2868 port->line = index; 2869 2870 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 2871 if (res == NULL) 2872 return -ENOMEM; 2873 2874 port->mapbase = res->start; 2875 sci_port->reg_size = resource_size(res); 2876 2877 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) 2878 sci_port->irqs[i] = platform_get_irq(dev, i); 2879 2880 /* The SCI generates several interrupts. They can be muxed together or 2881 * connected to different interrupt lines. In the muxed case only one 2882 * interrupt resource is specified as there is only one interrupt ID. 2883 * In the non-muxed case, up to 6 interrupt signals might be generated 2884 * from the SCI, however those signals might have their own individual 2885 * interrupt ID numbers, or muxed together with another interrupt. 2886 */ 2887 if (sci_port->irqs[0] < 0) 2888 return -ENXIO; 2889 2890 if (sci_port->irqs[1] < 0) 2891 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++) 2892 sci_port->irqs[i] = sci_port->irqs[0]; 2893 2894 sci_port->params = sci_probe_regmap(p); 2895 if (unlikely(sci_port->params == NULL)) 2896 return -EINVAL; 2897 2898 switch (p->type) { 2899 case PORT_SCIFB: 2900 sci_port->rx_trigger = 48; 2901 break; 2902 case PORT_HSCIF: 2903 sci_port->rx_trigger = 64; 2904 break; 2905 case PORT_SCIFA: 2906 sci_port->rx_trigger = 32; 2907 break; 2908 case PORT_SCIF: 2909 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) 2910 /* RX triggering not implemented for this IP */ 2911 sci_port->rx_trigger = 1; 2912 else 2913 sci_port->rx_trigger = 8; 2914 break; 2915 default: 2916 sci_port->rx_trigger = 1; 2917 break; 2918 } 2919 2920 sci_port->rx_fifo_timeout = 0; 2921 sci_port->hscif_tot = 0; 2922 2923 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't 2924 * match the SoC datasheet, this should be investigated. Let platform 2925 * data override the sampling rate for now. 2926 */ 2927 sci_port->sampling_rate_mask = p->sampling_rate 2928 ? SCI_SR(p->sampling_rate) 2929 : sci_port->params->sampling_rate_mask; 2930 2931 if (!early) { 2932 ret = sci_init_clocks(sci_port, &dev->dev); 2933 if (ret < 0) 2934 return ret; 2935 2936 port->dev = &dev->dev; 2937 2938 pm_runtime_enable(&dev->dev); 2939 } 2940 2941 port->type = p->type; 2942 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags; 2943 port->fifosize = sci_port->params->fifosize; 2944 2945 if (port->type == PORT_SCI) { 2946 if (sci_port->reg_size >= 0x20) 2947 port->regshift = 2; 2948 else 2949 port->regshift = 1; 2950 } 2951 2952 /* 2953 * The UART port needs an IRQ value, so we peg this to the RX IRQ 2954 * for the multi-IRQ ports, which is where we are primarily 2955 * concerned with the shutdown path synchronization. 2956 * 2957 * For the muxed case there's nothing more to do. 2958 */ 2959 port->irq = sci_port->irqs[SCIx_RXI_IRQ]; 2960 port->irqflags = 0; 2961 2962 port->serial_in = sci_serial_in; 2963 port->serial_out = sci_serial_out; 2964 2965 return 0; 2966 } 2967 2968 static void sci_cleanup_single(struct sci_port *port) 2969 { 2970 pm_runtime_disable(port->port.dev); 2971 } 2972 2973 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ 2974 defined(CONFIG_SERIAL_SH_SCI_EARLYCON) 2975 static void serial_console_putchar(struct uart_port *port, int ch) 2976 { 2977 sci_poll_put_char(port, ch); 2978 } 2979 2980 /* 2981 * Print a string to the serial port trying not to disturb 2982 * any possible real use of the port... 2983 */ 2984 static void serial_console_write(struct console *co, const char *s, 2985 unsigned count) 2986 { 2987 struct sci_port *sci_port = &sci_ports[co->index]; 2988 struct uart_port *port = &sci_port->port; 2989 unsigned short bits, ctrl, ctrl_temp; 2990 unsigned long flags; 2991 int locked = 1; 2992 2993 #if defined(SUPPORT_SYSRQ) 2994 if (port->sysrq) 2995 locked = 0; 2996 else 2997 #endif 2998 if (oops_in_progress) 2999 locked = spin_trylock_irqsave(&port->lock, flags); 3000 else 3001 spin_lock_irqsave(&port->lock, flags); 3002 3003 /* first save SCSCR then disable interrupts, keep clock source */ 3004 ctrl = serial_port_in(port, SCSCR); 3005 ctrl_temp = SCSCR_RE | SCSCR_TE | 3006 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) | 3007 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0)); 3008 serial_port_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot); 3009 3010 uart_console_write(port, s, count, serial_console_putchar); 3011 3012 /* wait until fifo is empty and last bit has been transmitted */ 3013 bits = SCxSR_TDxE(port) | SCxSR_TEND(port); 3014 while ((serial_port_in(port, SCxSR) & bits) != bits) 3015 cpu_relax(); 3016 3017 /* restore the SCSCR */ 3018 serial_port_out(port, SCSCR, ctrl); 3019 3020 if (locked) 3021 spin_unlock_irqrestore(&port->lock, flags); 3022 } 3023 3024 static int serial_console_setup(struct console *co, char *options) 3025 { 3026 struct sci_port *sci_port; 3027 struct uart_port *port; 3028 int baud = 115200; 3029 int bits = 8; 3030 int parity = 'n'; 3031 int flow = 'n'; 3032 int ret; 3033 3034 /* 3035 * Refuse to handle any bogus ports. 3036 */ 3037 if (co->index < 0 || co->index >= SCI_NPORTS) 3038 return -ENODEV; 3039 3040 sci_port = &sci_ports[co->index]; 3041 port = &sci_port->port; 3042 3043 /* 3044 * Refuse to handle uninitialized ports. 3045 */ 3046 if (!port->ops) 3047 return -ENODEV; 3048 3049 ret = sci_remap_port(port); 3050 if (unlikely(ret != 0)) 3051 return ret; 3052 3053 if (options) 3054 uart_parse_options(options, &baud, &parity, &bits, &flow); 3055 3056 return uart_set_options(port, co, baud, parity, bits, flow); 3057 } 3058 3059 static struct console serial_console = { 3060 .name = "ttySC", 3061 .device = uart_console_device, 3062 .write = serial_console_write, 3063 .setup = serial_console_setup, 3064 .flags = CON_PRINTBUFFER, 3065 .index = -1, 3066 .data = &sci_uart_driver, 3067 }; 3068 3069 static struct console early_serial_console = { 3070 .name = "early_ttySC", 3071 .write = serial_console_write, 3072 .flags = CON_PRINTBUFFER, 3073 .index = -1, 3074 }; 3075 3076 static char early_serial_buf[32]; 3077 3078 static int sci_probe_earlyprintk(struct platform_device *pdev) 3079 { 3080 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev); 3081 3082 if (early_serial_console.data) 3083 return -EEXIST; 3084 3085 early_serial_console.index = pdev->id; 3086 3087 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true); 3088 3089 serial_console_setup(&early_serial_console, early_serial_buf); 3090 3091 if (!strstr(early_serial_buf, "keep")) 3092 early_serial_console.flags |= CON_BOOT; 3093 3094 register_console(&early_serial_console); 3095 return 0; 3096 } 3097 3098 #define SCI_CONSOLE (&serial_console) 3099 3100 #else 3101 static inline int sci_probe_earlyprintk(struct platform_device *pdev) 3102 { 3103 return -EINVAL; 3104 } 3105 3106 #define SCI_CONSOLE NULL 3107 3108 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */ 3109 3110 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized"; 3111 3112 static DEFINE_MUTEX(sci_uart_registration_lock); 3113 static struct uart_driver sci_uart_driver = { 3114 .owner = THIS_MODULE, 3115 .driver_name = "sci", 3116 .dev_name = "ttySC", 3117 .major = SCI_MAJOR, 3118 .minor = SCI_MINOR_START, 3119 .nr = SCI_NPORTS, 3120 .cons = SCI_CONSOLE, 3121 }; 3122 3123 static int sci_remove(struct platform_device *dev) 3124 { 3125 struct sci_port *port = platform_get_drvdata(dev); 3126 unsigned int type = port->port.type; /* uart_remove_... clears it */ 3127 3128 sci_ports_in_use &= ~BIT(port->port.line); 3129 uart_remove_one_port(&sci_uart_driver, &port->port); 3130 3131 sci_cleanup_single(port); 3132 3133 if (port->port.fifosize > 1) { 3134 sysfs_remove_file(&dev->dev.kobj, 3135 &dev_attr_rx_fifo_trigger.attr); 3136 } 3137 if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF) { 3138 sysfs_remove_file(&dev->dev.kobj, 3139 &dev_attr_rx_fifo_timeout.attr); 3140 } 3141 3142 return 0; 3143 } 3144 3145 3146 #define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype)) 3147 #define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16) 3148 #define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff) 3149 3150 static const struct of_device_id of_sci_match[] = { 3151 /* SoC-specific types */ 3152 { 3153 .compatible = "renesas,scif-r7s72100", 3154 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE), 3155 }, 3156 { 3157 .compatible = "renesas,scif-r7s9210", 3158 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE), 3159 }, 3160 /* Family-specific types */ 3161 { 3162 .compatible = "renesas,rcar-gen1-scif", 3163 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3164 }, { 3165 .compatible = "renesas,rcar-gen2-scif", 3166 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3167 }, { 3168 .compatible = "renesas,rcar-gen3-scif", 3169 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3170 }, 3171 /* Generic types */ 3172 { 3173 .compatible = "renesas,scif", 3174 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE), 3175 }, { 3176 .compatible = "renesas,scifa", 3177 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE), 3178 }, { 3179 .compatible = "renesas,scifb", 3180 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE), 3181 }, { 3182 .compatible = "renesas,hscif", 3183 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE), 3184 }, { 3185 .compatible = "renesas,sci", 3186 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE), 3187 }, { 3188 /* Terminator */ 3189 }, 3190 }; 3191 MODULE_DEVICE_TABLE(of, of_sci_match); 3192 3193 static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev, 3194 unsigned int *dev_id) 3195 { 3196 struct device_node *np = pdev->dev.of_node; 3197 struct plat_sci_port *p; 3198 struct sci_port *sp; 3199 const void *data; 3200 int id; 3201 3202 if (!IS_ENABLED(CONFIG_OF) || !np) 3203 return NULL; 3204 3205 data = of_device_get_match_data(&pdev->dev); 3206 3207 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL); 3208 if (!p) 3209 return NULL; 3210 3211 /* Get the line number from the aliases node. */ 3212 id = of_alias_get_id(np, "serial"); 3213 if (id < 0 && ~sci_ports_in_use) 3214 id = ffz(sci_ports_in_use); 3215 if (id < 0) { 3216 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id); 3217 return NULL; 3218 } 3219 if (id >= ARRAY_SIZE(sci_ports)) { 3220 dev_err(&pdev->dev, "serial%d out of range\n", id); 3221 return NULL; 3222 } 3223 3224 sp = &sci_ports[id]; 3225 *dev_id = id; 3226 3227 p->type = SCI_OF_TYPE(data); 3228 p->regtype = SCI_OF_REGTYPE(data); 3229 3230 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts"); 3231 3232 return p; 3233 } 3234 3235 static int sci_probe_single(struct platform_device *dev, 3236 unsigned int index, 3237 struct plat_sci_port *p, 3238 struct sci_port *sciport) 3239 { 3240 int ret; 3241 3242 /* Sanity check */ 3243 if (unlikely(index >= SCI_NPORTS)) { 3244 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n", 3245 index+1, SCI_NPORTS); 3246 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n"); 3247 return -EINVAL; 3248 } 3249 BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8); 3250 if (sci_ports_in_use & BIT(index)) 3251 return -EBUSY; 3252 3253 mutex_lock(&sci_uart_registration_lock); 3254 if (!sci_uart_driver.state) { 3255 ret = uart_register_driver(&sci_uart_driver); 3256 if (ret) { 3257 mutex_unlock(&sci_uart_registration_lock); 3258 return ret; 3259 } 3260 } 3261 mutex_unlock(&sci_uart_registration_lock); 3262 3263 ret = sci_init_single(dev, sciport, index, p, false); 3264 if (ret) 3265 return ret; 3266 3267 sciport->gpios = mctrl_gpio_init(&sciport->port, 0); 3268 if (IS_ERR(sciport->gpios) && PTR_ERR(sciport->gpios) != -ENOSYS) 3269 return PTR_ERR(sciport->gpios); 3270 3271 if (sciport->has_rtscts) { 3272 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios, 3273 UART_GPIO_CTS)) || 3274 !IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios, 3275 UART_GPIO_RTS))) { 3276 dev_err(&dev->dev, "Conflicting RTS/CTS config\n"); 3277 return -EINVAL; 3278 } 3279 sciport->port.flags |= UPF_HARD_FLOW; 3280 } 3281 3282 ret = uart_add_one_port(&sci_uart_driver, &sciport->port); 3283 if (ret) { 3284 sci_cleanup_single(sciport); 3285 return ret; 3286 } 3287 3288 return 0; 3289 } 3290 3291 static int sci_probe(struct platform_device *dev) 3292 { 3293 struct plat_sci_port *p; 3294 struct sci_port *sp; 3295 unsigned int dev_id; 3296 int ret; 3297 3298 /* 3299 * If we've come here via earlyprintk initialization, head off to 3300 * the special early probe. We don't have sufficient device state 3301 * to make it beyond this yet. 3302 */ 3303 if (is_early_platform_device(dev)) 3304 return sci_probe_earlyprintk(dev); 3305 3306 if (dev->dev.of_node) { 3307 p = sci_parse_dt(dev, &dev_id); 3308 if (p == NULL) 3309 return -EINVAL; 3310 } else { 3311 p = dev->dev.platform_data; 3312 if (p == NULL) { 3313 dev_err(&dev->dev, "no platform data supplied\n"); 3314 return -EINVAL; 3315 } 3316 3317 dev_id = dev->id; 3318 } 3319 3320 sp = &sci_ports[dev_id]; 3321 platform_set_drvdata(dev, sp); 3322 3323 ret = sci_probe_single(dev, dev_id, p, sp); 3324 if (ret) 3325 return ret; 3326 3327 if (sp->port.fifosize > 1) { 3328 ret = sysfs_create_file(&dev->dev.kobj, 3329 &dev_attr_rx_fifo_trigger.attr); 3330 if (ret) 3331 return ret; 3332 } 3333 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB || 3334 sp->port.type == PORT_HSCIF) { 3335 ret = sysfs_create_file(&dev->dev.kobj, 3336 &dev_attr_rx_fifo_timeout.attr); 3337 if (ret) { 3338 if (sp->port.fifosize > 1) { 3339 sysfs_remove_file(&dev->dev.kobj, 3340 &dev_attr_rx_fifo_trigger.attr); 3341 } 3342 return ret; 3343 } 3344 } 3345 3346 #ifdef CONFIG_SH_STANDARD_BIOS 3347 sh_bios_gdb_detach(); 3348 #endif 3349 3350 sci_ports_in_use |= BIT(dev_id); 3351 return 0; 3352 } 3353 3354 static __maybe_unused int sci_suspend(struct device *dev) 3355 { 3356 struct sci_port *sport = dev_get_drvdata(dev); 3357 3358 if (sport) 3359 uart_suspend_port(&sci_uart_driver, &sport->port); 3360 3361 return 0; 3362 } 3363 3364 static __maybe_unused int sci_resume(struct device *dev) 3365 { 3366 struct sci_port *sport = dev_get_drvdata(dev); 3367 3368 if (sport) 3369 uart_resume_port(&sci_uart_driver, &sport->port); 3370 3371 return 0; 3372 } 3373 3374 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume); 3375 3376 static struct platform_driver sci_driver = { 3377 .probe = sci_probe, 3378 .remove = sci_remove, 3379 .driver = { 3380 .name = "sh-sci", 3381 .pm = &sci_dev_pm_ops, 3382 .of_match_table = of_match_ptr(of_sci_match), 3383 }, 3384 }; 3385 3386 static int __init sci_init(void) 3387 { 3388 pr_info("%s\n", banner); 3389 3390 return platform_driver_register(&sci_driver); 3391 } 3392 3393 static void __exit sci_exit(void) 3394 { 3395 platform_driver_unregister(&sci_driver); 3396 3397 if (sci_uart_driver.state) 3398 uart_unregister_driver(&sci_uart_driver); 3399 } 3400 3401 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE 3402 early_platform_init_buffer("earlyprintk", &sci_driver, 3403 early_serial_buf, ARRAY_SIZE(early_serial_buf)); 3404 #endif 3405 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON 3406 static struct plat_sci_port port_cfg __initdata; 3407 3408 static int __init early_console_setup(struct earlycon_device *device, 3409 int type) 3410 { 3411 if (!device->port.membase) 3412 return -ENODEV; 3413 3414 device->port.serial_in = sci_serial_in; 3415 device->port.serial_out = sci_serial_out; 3416 device->port.type = type; 3417 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port)); 3418 port_cfg.type = type; 3419 sci_ports[0].cfg = &port_cfg; 3420 sci_ports[0].params = sci_probe_regmap(&port_cfg); 3421 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR); 3422 sci_serial_out(&sci_ports[0].port, SCSCR, 3423 SCSCR_RE | SCSCR_TE | port_cfg.scscr); 3424 3425 device->con->write = serial_console_write; 3426 return 0; 3427 } 3428 static int __init sci_early_console_setup(struct earlycon_device *device, 3429 const char *opt) 3430 { 3431 return early_console_setup(device, PORT_SCI); 3432 } 3433 static int __init scif_early_console_setup(struct earlycon_device *device, 3434 const char *opt) 3435 { 3436 return early_console_setup(device, PORT_SCIF); 3437 } 3438 static int __init rzscifa_early_console_setup(struct earlycon_device *device, 3439 const char *opt) 3440 { 3441 port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE; 3442 return early_console_setup(device, PORT_SCIF); 3443 } 3444 static int __init scifa_early_console_setup(struct earlycon_device *device, 3445 const char *opt) 3446 { 3447 return early_console_setup(device, PORT_SCIFA); 3448 } 3449 static int __init scifb_early_console_setup(struct earlycon_device *device, 3450 const char *opt) 3451 { 3452 return early_console_setup(device, PORT_SCIFB); 3453 } 3454 static int __init hscif_early_console_setup(struct earlycon_device *device, 3455 const char *opt) 3456 { 3457 return early_console_setup(device, PORT_HSCIF); 3458 } 3459 3460 OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup); 3461 OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup); 3462 OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup); 3463 OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup); 3464 OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup); 3465 OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup); 3466 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */ 3467 3468 module_init(sci_init); 3469 module_exit(sci_exit); 3470 3471 MODULE_LICENSE("GPL"); 3472 MODULE_ALIAS("platform:sh-sci"); 3473 MODULE_AUTHOR("Paul Mundt"); 3474 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver"); 3475